1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct rte_ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct rte_ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct rte_ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr);
144 /* Default hash key buffer for RSS */
145 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
147 struct rte_i40evf_xstats_name_off {
148 char name[RTE_ETH_XSTATS_NAME_SIZE];
152 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
153 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
154 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
155 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
156 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
157 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
158 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
159 rx_unknown_protocol)},
160 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
161 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
162 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
163 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
164 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
165 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
168 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
169 sizeof(rte_i40evf_stats_strings[0]))
171 static const struct eth_dev_ops i40evf_eth_dev_ops = {
172 .dev_configure = i40evf_dev_configure,
173 .dev_start = i40evf_dev_start,
174 .dev_stop = i40evf_dev_stop,
175 .promiscuous_enable = i40evf_dev_promiscuous_enable,
176 .promiscuous_disable = i40evf_dev_promiscuous_disable,
177 .allmulticast_enable = i40evf_dev_allmulticast_enable,
178 .allmulticast_disable = i40evf_dev_allmulticast_disable,
179 .link_update = i40evf_dev_link_update,
180 .stats_get = i40evf_dev_stats_get,
181 .stats_reset = i40evf_dev_xstats_reset,
182 .xstats_get = i40evf_dev_xstats_get,
183 .xstats_get_names = i40evf_dev_xstats_get_names,
184 .xstats_reset = i40evf_dev_xstats_reset,
185 .dev_close = i40evf_dev_close,
186 .dev_reset = i40evf_dev_reset,
187 .dev_infos_get = i40evf_dev_info_get,
188 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
189 .vlan_filter_set = i40evf_vlan_filter_set,
190 .vlan_offload_set = i40evf_vlan_offload_set,
191 .rx_queue_start = i40evf_dev_rx_queue_start,
192 .rx_queue_stop = i40evf_dev_rx_queue_stop,
193 .tx_queue_start = i40evf_dev_tx_queue_start,
194 .tx_queue_stop = i40evf_dev_tx_queue_stop,
195 .rx_queue_setup = i40e_dev_rx_queue_setup,
196 .rx_queue_release = i40e_dev_rx_queue_release,
197 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
198 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
199 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
200 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
201 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
202 .tx_queue_setup = i40e_dev_tx_queue_setup,
203 .tx_queue_release = i40e_dev_tx_queue_release,
204 .rx_queue_count = i40e_dev_rx_queue_count,
205 .rxq_info_get = i40e_rxq_info_get,
206 .txq_info_get = i40e_txq_info_get,
207 .mac_addr_add = i40evf_add_mac_addr,
208 .mac_addr_remove = i40evf_del_mac_addr,
209 .set_mc_addr_list = i40evf_set_mc_addr_list,
210 .reta_update = i40evf_dev_rss_reta_update,
211 .reta_query = i40evf_dev_rss_reta_query,
212 .rss_hash_update = i40evf_dev_rss_hash_update,
213 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
214 .mtu_set = i40evf_dev_mtu_set,
215 .mac_addr_set = i40evf_set_default_mac_addr,
219 * Read data in admin queue to get msg from pf driver
221 static enum i40evf_aq_result
222 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
224 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
225 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
226 struct i40e_arq_event_info event;
227 enum virtchnl_ops opcode;
228 enum i40e_status_code retval;
230 enum i40evf_aq_result result = I40EVF_MSG_NON;
232 event.buf_len = data->buf_len;
233 event.msg_buf = data->msg;
234 ret = i40e_clean_arq_element(hw, &event, NULL);
235 /* Can't read any msg from adminQ */
237 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
238 result = I40EVF_MSG_ERR;
242 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
243 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
245 if (opcode == VIRTCHNL_OP_EVENT) {
246 struct virtchnl_pf_event *vpe =
247 (struct virtchnl_pf_event *)event.msg_buf;
249 result = I40EVF_MSG_SYS;
250 switch (vpe->event) {
251 case VIRTCHNL_EVENT_LINK_CHANGE:
253 vpe->event_data.link_event.link_status;
255 vpe->event_data.link_event.link_speed;
256 vf->pend_msg |= PFMSG_LINK_CHANGE;
257 PMD_DRV_LOG(INFO, "Link status update:%s",
258 vf->link_up ? "up" : "down");
260 case VIRTCHNL_EVENT_RESET_IMPENDING:
262 vf->pend_msg |= PFMSG_RESET_IMPENDING;
263 PMD_DRV_LOG(INFO, "vf is reseting");
265 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
266 vf->dev_closed = true;
267 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
268 PMD_DRV_LOG(INFO, "PF driver closed");
271 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
272 __func__, vpe->event);
275 /* async reply msg on command issued by vf previously */
276 result = I40EVF_MSG_CMD;
277 /* Actual data length read from PF */
278 data->msg_len = event.msg_len;
281 data->result = retval;
288 * clear current command. Only call in case execute
289 * _atomic_set_cmd successfully.
292 _clear_cmd(struct i40e_vf *vf)
295 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
299 * Check there is pending cmd in execution. If none, set new command.
302 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
304 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
305 VIRTCHNL_OP_UNKNOWN, ops);
308 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
313 #define MAX_TRY_TIMES 200
314 #define ASQ_DELAY_MS 10
317 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
320 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
321 struct i40evf_arq_msg_info info;
322 enum i40evf_aq_result ret;
325 if (_atomic_set_cmd(vf, args->ops))
328 info.msg = args->out_buffer;
329 info.buf_len = args->out_size;
330 info.ops = VIRTCHNL_OP_UNKNOWN;
331 info.result = I40E_SUCCESS;
333 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
334 args->in_args, args->in_args_size, NULL);
336 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
342 case VIRTCHNL_OP_RESET_VF:
343 /*no need to process in this function */
346 case VIRTCHNL_OP_VERSION:
347 case VIRTCHNL_OP_GET_VF_RESOURCES:
348 /* for init adminq commands, need to poll the response */
351 ret = i40evf_read_pfmsg(dev, &info);
352 vf->cmd_retval = info.result;
353 if (ret == I40EVF_MSG_CMD) {
356 } else if (ret == I40EVF_MSG_ERR)
358 rte_delay_ms(ASQ_DELAY_MS);
359 /* If don't read msg or read sys event, continue */
360 } while (i++ < MAX_TRY_TIMES);
363 case VIRTCHNL_OP_REQUEST_QUEUES:
365 * ignore async reply, only wait for system message,
366 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
367 * if not, means request queues failed.
371 ret = i40evf_read_pfmsg(dev, &info);
372 vf->cmd_retval = info.result;
373 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
376 } else if (ret == I40EVF_MSG_ERR ||
377 ret == I40EVF_MSG_CMD) {
380 rte_delay_ms(ASQ_DELAY_MS);
381 /* If don't read msg or read sys event, continue */
382 } while (i++ < MAX_TRY_TIMES);
387 /* for other adminq in running time, waiting the cmd done flag */
390 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
394 rte_delay_ms(ASQ_DELAY_MS);
395 /* If don't read msg or read sys event, continue */
396 } while (i++ < MAX_TRY_TIMES);
397 /* If there's no response is received, clear command */
398 if (i >= MAX_TRY_TIMES) {
399 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
405 return err | vf->cmd_retval;
409 * Check API version with sync wait until version read or fail from admin queue
412 i40evf_check_api_version(struct rte_eth_dev *dev)
414 struct virtchnl_version_info version, *pver;
416 struct vf_cmd_info args;
417 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
419 version.major = VIRTCHNL_VERSION_MAJOR;
420 version.minor = VIRTCHNL_VERSION_MINOR;
422 args.ops = VIRTCHNL_OP_VERSION;
423 args.in_args = (uint8_t *)&version;
424 args.in_args_size = sizeof(version);
425 args.out_buffer = vf->aq_resp;
426 args.out_size = I40E_AQ_BUF_SZ;
428 err = i40evf_execute_vf_cmd(dev, &args);
430 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
434 pver = (struct virtchnl_version_info *)args.out_buffer;
435 vf->version_major = pver->major;
436 vf->version_minor = pver->minor;
437 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
438 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
439 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
441 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
442 vf->version_major, vf->version_minor,
443 VIRTCHNL_VERSION_MAJOR,
444 VIRTCHNL_VERSION_MINOR);
452 i40evf_get_vf_resource(struct rte_eth_dev *dev)
454 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
455 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
457 struct vf_cmd_info args;
460 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
461 args.out_buffer = vf->aq_resp;
462 args.out_size = I40E_AQ_BUF_SZ;
464 caps = VIRTCHNL_VF_OFFLOAD_L2 |
465 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
466 VIRTCHNL_VF_OFFLOAD_RSS_REG |
467 VIRTCHNL_VF_OFFLOAD_VLAN |
468 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
469 args.in_args = (uint8_t *)∩︀
470 args.in_args_size = sizeof(caps);
473 args.in_args_size = 0;
475 err = i40evf_execute_vf_cmd(dev, &args);
478 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
482 len = sizeof(struct virtchnl_vf_resource) +
483 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
485 rte_memcpy(vf->vf_res, args.out_buffer,
486 RTE_MIN(args.out_size, len));
487 i40e_vf_parse_hw_config(hw, vf->vf_res);
493 i40evf_config_promisc(struct rte_eth_dev *dev,
495 bool enable_multicast)
497 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
499 struct vf_cmd_info args;
500 struct virtchnl_promisc_info promisc;
503 promisc.vsi_id = vf->vsi_res->vsi_id;
506 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
508 if (enable_multicast)
509 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
511 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
512 args.in_args = (uint8_t *)&promisc;
513 args.in_args_size = sizeof(promisc);
514 args.out_buffer = vf->aq_resp;
515 args.out_size = I40E_AQ_BUF_SZ;
517 err = i40evf_execute_vf_cmd(dev, &args);
520 PMD_DRV_LOG(ERR, "fail to execute command "
521 "CONFIG_PROMISCUOUS_MODE");
526 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
528 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
529 struct vf_cmd_info args;
532 memset(&args, 0, sizeof(args));
533 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
535 args.in_args_size = 0;
536 args.out_buffer = vf->aq_resp;
537 args.out_size = I40E_AQ_BUF_SZ;
538 ret = i40evf_execute_vf_cmd(dev, &args);
540 PMD_DRV_LOG(ERR, "Failed to execute command of "
541 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
547 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
549 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
550 struct vf_cmd_info args;
553 memset(&args, 0, sizeof(args));
554 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
556 args.in_args_size = 0;
557 args.out_buffer = vf->aq_resp;
558 args.out_size = I40E_AQ_BUF_SZ;
559 ret = i40evf_execute_vf_cmd(dev, &args);
561 PMD_DRV_LOG(ERR, "Failed to execute command of "
562 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
568 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
572 struct i40e_tx_queue *txq)
574 txq_info->vsi_id = vsi_id;
575 txq_info->queue_id = queue_id;
576 if (queue_id < nb_txq) {
577 txq_info->ring_len = txq->nb_tx_desc;
578 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
583 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
587 uint32_t max_pkt_size,
588 struct i40e_rx_queue *rxq)
590 rxq_info->vsi_id = vsi_id;
591 rxq_info->queue_id = queue_id;
592 rxq_info->max_pkt_size = max_pkt_size;
593 if (queue_id < nb_rxq) {
594 rxq_info->ring_len = rxq->nb_rx_desc;
595 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
596 rxq_info->databuffer_size =
597 (rte_pktmbuf_data_room_size(rxq->mp) -
598 RTE_PKTMBUF_HEADROOM);
603 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
605 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
606 struct i40e_rx_queue **rxq =
607 (struct i40e_rx_queue **)dev->data->rx_queues;
608 struct i40e_tx_queue **txq =
609 (struct i40e_tx_queue **)dev->data->tx_queues;
610 struct virtchnl_vsi_queue_config_info *vc_vqci;
611 struct virtchnl_queue_pair_info *vc_qpi;
612 struct vf_cmd_info args;
613 uint16_t i, nb_qp = vf->num_queue_pairs;
614 const uint32_t size =
615 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
619 memset(buff, 0, sizeof(buff));
620 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
621 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
622 vc_vqci->num_queue_pairs = nb_qp;
624 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
625 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
626 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
627 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
628 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
629 vf->max_pkt_len, rxq[i]);
631 memset(&args, 0, sizeof(args));
632 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
633 args.in_args = (uint8_t *)vc_vqci;
634 args.in_args_size = size;
635 args.out_buffer = vf->aq_resp;
636 args.out_size = I40E_AQ_BUF_SZ;
637 ret = i40evf_execute_vf_cmd(dev, &args);
639 PMD_DRV_LOG(ERR, "Failed to execute command of "
640 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
646 i40evf_config_irq_map(struct rte_eth_dev *dev)
648 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
649 struct vf_cmd_info args;
650 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
651 sizeof(struct virtchnl_vector_map)];
652 struct virtchnl_irq_map_info *map_info;
653 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
654 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
658 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
659 rte_intr_allow_others(intr_handle))
660 vector_id = I40E_RX_VEC_START;
662 vector_id = I40E_MISC_VEC_ID;
664 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
665 map_info->num_vectors = 1;
666 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
667 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
668 /* Alway use default dynamic MSIX interrupt */
669 map_info->vecmap[0].vector_id = vector_id;
670 /* Don't map any tx queue */
671 map_info->vecmap[0].txq_map = 0;
672 map_info->vecmap[0].rxq_map = 0;
673 for (i = 0; i < dev->data->nb_rx_queues; i++) {
674 map_info->vecmap[0].rxq_map |= 1 << i;
675 if (rte_intr_dp_is_en(intr_handle))
676 intr_handle->intr_vec[i] = vector_id;
679 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
680 args.in_args = (u8 *)cmd_buffer;
681 args.in_args_size = sizeof(cmd_buffer);
682 args.out_buffer = vf->aq_resp;
683 args.out_size = I40E_AQ_BUF_SZ;
684 err = i40evf_execute_vf_cmd(dev, &args);
686 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
692 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
695 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
696 struct virtchnl_queue_select queue_select;
698 struct vf_cmd_info args;
699 memset(&queue_select, 0, sizeof(queue_select));
700 queue_select.vsi_id = vf->vsi_res->vsi_id;
703 queue_select.rx_queues |= 1 << qid;
705 queue_select.tx_queues |= 1 << qid;
708 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
710 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
711 args.in_args = (u8 *)&queue_select;
712 args.in_args_size = sizeof(queue_select);
713 args.out_buffer = vf->aq_resp;
714 args.out_size = I40E_AQ_BUF_SZ;
715 err = i40evf_execute_vf_cmd(dev, &args);
717 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
718 isrx ? "RX" : "TX", qid, on ? "on" : "off");
724 i40evf_start_queues(struct rte_eth_dev *dev)
726 struct rte_eth_dev_data *dev_data = dev->data;
728 struct i40e_rx_queue *rxq;
729 struct i40e_tx_queue *txq;
731 for (i = 0; i < dev->data->nb_rx_queues; i++) {
732 rxq = dev_data->rx_queues[i];
733 if (rxq->rx_deferred_start)
735 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
736 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
741 for (i = 0; i < dev->data->nb_tx_queues; i++) {
742 txq = dev_data->tx_queues[i];
743 if (txq->tx_deferred_start)
745 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
746 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
755 i40evf_stop_queues(struct rte_eth_dev *dev)
759 /* Stop TX queues first */
760 for (i = 0; i < dev->data->nb_tx_queues; i++) {
761 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
762 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
767 /* Then stop RX queues */
768 for (i = 0; i < dev->data->nb_rx_queues; i++) {
769 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
770 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
779 i40evf_add_mac_addr(struct rte_eth_dev *dev,
780 struct rte_ether_addr *addr,
781 __rte_unused uint32_t index,
782 __rte_unused uint32_t pool)
784 struct virtchnl_ether_addr_list *list;
785 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
786 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
787 sizeof(struct virtchnl_ether_addr)];
789 struct vf_cmd_info args;
791 if (rte_is_zero_ether_addr(addr)) {
792 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
793 addr->addr_bytes[0], addr->addr_bytes[1],
794 addr->addr_bytes[2], addr->addr_bytes[3],
795 addr->addr_bytes[4], addr->addr_bytes[5]);
796 return I40E_ERR_INVALID_MAC_ADDR;
799 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
800 list->vsi_id = vf->vsi_res->vsi_id;
801 list->num_elements = 1;
802 rte_memcpy(list->list[0].addr, addr->addr_bytes,
803 sizeof(addr->addr_bytes));
805 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
806 args.in_args = cmd_buffer;
807 args.in_args_size = sizeof(cmd_buffer);
808 args.out_buffer = vf->aq_resp;
809 args.out_size = I40E_AQ_BUF_SZ;
810 err = i40evf_execute_vf_cmd(dev, &args);
812 PMD_DRV_LOG(ERR, "fail to execute command "
813 "OP_ADD_ETHER_ADDRESS");
821 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
822 struct rte_ether_addr *addr)
824 struct virtchnl_ether_addr_list *list;
825 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
826 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
827 sizeof(struct virtchnl_ether_addr)];
829 struct vf_cmd_info args;
831 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
832 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
833 addr->addr_bytes[0], addr->addr_bytes[1],
834 addr->addr_bytes[2], addr->addr_bytes[3],
835 addr->addr_bytes[4], addr->addr_bytes[5]);
839 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
840 list->vsi_id = vf->vsi_res->vsi_id;
841 list->num_elements = 1;
842 rte_memcpy(list->list[0].addr, addr->addr_bytes,
843 sizeof(addr->addr_bytes));
845 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
846 args.in_args = cmd_buffer;
847 args.in_args_size = sizeof(cmd_buffer);
848 args.out_buffer = vf->aq_resp;
849 args.out_size = I40E_AQ_BUF_SZ;
850 err = i40evf_execute_vf_cmd(dev, &args);
852 PMD_DRV_LOG(ERR, "fail to execute command "
853 "OP_DEL_ETHER_ADDRESS");
860 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
862 struct rte_eth_dev_data *data = dev->data;
863 struct rte_ether_addr *addr;
865 addr = &data->mac_addrs[index];
867 i40evf_del_mac_addr_by_addr(dev, addr);
871 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
873 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
874 struct virtchnl_queue_select q_stats;
876 struct vf_cmd_info args;
878 memset(&q_stats, 0, sizeof(q_stats));
879 q_stats.vsi_id = vf->vsi_res->vsi_id;
880 args.ops = VIRTCHNL_OP_GET_STATS;
881 args.in_args = (u8 *)&q_stats;
882 args.in_args_size = sizeof(q_stats);
883 args.out_buffer = vf->aq_resp;
884 args.out_size = I40E_AQ_BUF_SZ;
886 err = i40evf_execute_vf_cmd(dev, &args);
888 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
892 *pstats = (struct i40e_eth_stats *)args.out_buffer;
897 i40evf_stat_update_48(uint64_t *offset,
900 if (*stat >= *offset)
901 *stat = *stat - *offset;
903 *stat = (uint64_t)((*stat +
904 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
906 *stat &= I40E_48_BIT_MASK;
910 i40evf_stat_update_32(uint64_t *offset,
913 if (*stat >= *offset)
914 *stat = (uint64_t)(*stat - *offset);
916 *stat = (uint64_t)((*stat +
917 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
921 i40evf_update_stats(struct i40e_vsi *vsi,
922 struct i40e_eth_stats *nes)
924 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
926 i40evf_stat_update_48(&oes->rx_bytes,
928 i40evf_stat_update_48(&oes->rx_unicast,
930 i40evf_stat_update_48(&oes->rx_multicast,
932 i40evf_stat_update_48(&oes->rx_broadcast,
934 i40evf_stat_update_32(&oes->rx_discards,
936 i40evf_stat_update_32(&oes->rx_unknown_protocol,
937 &nes->rx_unknown_protocol);
938 i40evf_stat_update_48(&oes->tx_bytes,
940 i40evf_stat_update_48(&oes->tx_unicast,
942 i40evf_stat_update_48(&oes->tx_multicast,
944 i40evf_stat_update_48(&oes->tx_broadcast,
946 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
947 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
951 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
954 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
955 struct i40e_eth_stats *pstats = NULL;
957 /* read stat values to clear hardware registers */
958 ret = i40evf_query_stats(dev, &pstats);
960 /* set stats offset base on current values */
962 vf->vsi.eth_stats_offset = *pstats;
965 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
966 struct rte_eth_xstat_name *xstats_names,
967 __rte_unused unsigned limit)
971 if (xstats_names != NULL)
972 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
973 snprintf(xstats_names[i].name,
974 sizeof(xstats_names[i].name),
975 "%s", rte_i40evf_stats_strings[i].name);
977 return I40EVF_NB_XSTATS;
980 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
981 struct rte_eth_xstat *xstats, unsigned n)
985 struct i40e_eth_stats *pstats = NULL;
986 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
987 struct i40e_vsi *vsi = &vf->vsi;
989 if (n < I40EVF_NB_XSTATS)
990 return I40EVF_NB_XSTATS;
992 ret = i40evf_query_stats(dev, &pstats);
999 i40evf_update_stats(vsi, pstats);
1001 /* loop over xstats array and values from pstats */
1002 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1004 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1005 rte_i40evf_stats_strings[i].offset);
1008 return I40EVF_NB_XSTATS;
1012 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1014 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1015 struct virtchnl_vlan_filter_list *vlan_list;
1016 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1019 struct vf_cmd_info args;
1021 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1022 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1023 vlan_list->num_elements = 1;
1024 vlan_list->vlan_id[0] = vlanid;
1026 args.ops = VIRTCHNL_OP_ADD_VLAN;
1027 args.in_args = (u8 *)&cmd_buffer;
1028 args.in_args_size = sizeof(cmd_buffer);
1029 args.out_buffer = vf->aq_resp;
1030 args.out_size = I40E_AQ_BUF_SZ;
1031 err = i40evf_execute_vf_cmd(dev, &args);
1033 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1039 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1041 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1042 struct virtchnl_vf_res_request vfres;
1043 struct vf_cmd_info args;
1046 vfres.num_queue_pairs = num;
1048 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1049 args.in_args = (u8 *)&vfres;
1050 args.in_args_size = sizeof(vfres);
1051 args.out_buffer = vf->aq_resp;
1052 args.out_size = I40E_AQ_BUF_SZ;
1053 err = i40evf_execute_vf_cmd(dev, &args);
1055 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1061 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1063 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1064 struct virtchnl_vlan_filter_list *vlan_list;
1065 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1068 struct vf_cmd_info args;
1070 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1071 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1072 vlan_list->num_elements = 1;
1073 vlan_list->vlan_id[0] = vlanid;
1075 args.ops = VIRTCHNL_OP_DEL_VLAN;
1076 args.in_args = (u8 *)&cmd_buffer;
1077 args.in_args_size = sizeof(cmd_buffer);
1078 args.out_buffer = vf->aq_resp;
1079 args.out_size = I40E_AQ_BUF_SZ;
1080 err = i40evf_execute_vf_cmd(dev, &args);
1082 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1087 static const struct rte_pci_id pci_id_i40evf_map[] = {
1088 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1089 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1090 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1091 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1092 { .vendor_id = 0, /* sentinel */ },
1097 i40evf_disable_irq0(struct i40e_hw *hw)
1099 /* Disable all interrupt types */
1100 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1101 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1102 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1103 I40EVF_WRITE_FLUSH(hw);
1108 i40evf_enable_irq0(struct i40e_hw *hw)
1110 /* Enable admin queue interrupt trigger */
1113 i40evf_disable_irq0(hw);
1114 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1115 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1116 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1117 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1119 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1120 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1121 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1122 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1124 I40EVF_WRITE_FLUSH(hw);
1128 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1131 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1134 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1135 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1136 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1137 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1138 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1139 reset == VIRTCHNL_VFR_COMPLETED)
1144 if (i >= MAX_RESET_WAIT_CNT)
1147 vf->vf_reset = false;
1148 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1153 i40evf_reset_vf(struct rte_eth_dev *dev)
1156 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1159 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1163 * After issuing vf reset command to pf, pf won't necessarily
1164 * reset vf, it depends on what state it exactly is. If it's not
1165 * initialized yet, it won't have vf reset since it's in a certain
1166 * state. If not, it will try to reset. Even vf is reset, pf will
1167 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1168 * it to ACTIVE. In this duration, vf may not catch the moment that
1169 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1173 ret = i40evf_check_vf_reset_done(dev);
1175 PMD_INIT_LOG(ERR, "VF is still resetting");
1183 i40evf_init_vf(struct rte_eth_dev *dev)
1186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1187 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1189 i40e_calc_itr_interval(0, 0);
1191 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1192 vf->dev_data = dev->data;
1193 err = i40e_set_mac_type(hw);
1195 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1199 err = i40evf_check_vf_reset_done(dev);
1203 i40e_init_adminq_parameter(hw);
1204 err = i40e_init_adminq(hw);
1206 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1210 /* Reset VF and wait until it's complete */
1211 if (i40evf_reset_vf(dev)) {
1212 PMD_INIT_LOG(ERR, "reset NIC failed");
1216 /* VF reset, shutdown admin queue and initialize again */
1217 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1218 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1222 i40e_init_adminq_parameter(hw);
1223 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1224 PMD_INIT_LOG(ERR, "init_adminq failed");
1228 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1230 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1233 if (i40evf_check_api_version(dev) != 0) {
1234 PMD_INIT_LOG(ERR, "check_api version failed");
1237 bufsz = sizeof(struct virtchnl_vf_resource) +
1238 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1239 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1241 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1245 if (i40evf_get_vf_resource(dev) != 0) {
1246 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1250 /* got VF config message back from PF, now we can parse it */
1251 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1252 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1253 vf->vsi_res = &vf->vf_res->vsi_res[i];
1257 PMD_INIT_LOG(ERR, "no LAN VSI found");
1261 if (hw->mac.type == I40E_MAC_X722_VF)
1262 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1263 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1265 switch (vf->vsi_res->vsi_type) {
1266 case VIRTCHNL_VSI_SRIOV:
1267 vf->vsi.type = I40E_VSI_SRIOV;
1270 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1273 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1274 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1276 /* Store the MAC address configured by host, or generate random one */
1277 if (rte_is_valid_assigned_ether_addr(
1278 (struct rte_ether_addr *)hw->mac.addr))
1279 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1281 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1283 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1284 (I40E_ITR_INDEX_DEFAULT <<
1285 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1287 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1288 I40EVF_WRITE_FLUSH(hw);
1293 rte_free(vf->vf_res);
1296 rte_free(vf->aq_resp);
1298 i40e_shutdown_adminq(hw); /* ignore error */
1304 i40evf_uninit_vf(struct rte_eth_dev *dev)
1306 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1307 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309 PMD_INIT_FUNC_TRACE();
1311 if (hw->adapter_closed == 0)
1312 i40evf_dev_close(dev);
1313 rte_free(vf->vf_res);
1315 rte_free(vf->aq_resp);
1322 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1323 __rte_unused uint16_t msglen)
1325 struct virtchnl_pf_event *pf_msg =
1326 (struct virtchnl_pf_event *)msg;
1327 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1329 switch (pf_msg->event) {
1330 case VIRTCHNL_EVENT_RESET_IMPENDING:
1331 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1332 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1335 case VIRTCHNL_EVENT_LINK_CHANGE:
1336 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1337 vf->link_up = pf_msg->event_data.link_event.link_status;
1338 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1340 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1341 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1344 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1350 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1352 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1354 struct i40e_arq_event_info info;
1355 uint16_t pending, aq_opc;
1356 enum virtchnl_ops msg_opc;
1357 enum i40e_status_code msg_ret;
1360 info.buf_len = I40E_AQ_BUF_SZ;
1362 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1365 info.msg_buf = vf->aq_resp;
1369 ret = i40e_clean_arq_element(hw, &info, &pending);
1371 if (ret != I40E_SUCCESS) {
1372 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1376 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1377 /* For the message sent from pf to vf, opcode is stored in
1378 * cookie_high of struct i40e_aq_desc, while return error code
1379 * are stored in cookie_low, Which is done by
1380 * i40e_aq_send_msg_to_vf in PF driver.*/
1381 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1382 info.desc.cookie_high);
1383 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1384 info.desc.cookie_low);
1386 case i40e_aqc_opc_send_msg_to_vf:
1387 if (msg_opc == VIRTCHNL_OP_EVENT)
1389 i40evf_handle_pf_event(dev, info.msg_buf,
1392 /* read message and it's expected one */
1393 if (msg_opc == vf->pend_cmd) {
1394 vf->cmd_retval = msg_ret;
1395 /* prevent compiler reordering */
1396 rte_compiler_barrier();
1399 PMD_DRV_LOG(ERR, "command mismatch,"
1400 "expect %u, get %u",
1401 vf->pend_cmd, msg_opc);
1402 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1403 " opcode = %d", msg_opc);
1407 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1415 * Interrupt handler triggered by NIC for handling
1416 * specific interrupt. Only adminq interrupt is processed in VF.
1419 * Pointer to interrupt handle.
1421 * The address of parameter (struct rte_eth_dev *) regsitered before.
1427 i40evf_dev_alarm_handler(void *param)
1429 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1430 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433 i40evf_disable_irq0(hw);
1435 /* read out interrupt causes */
1436 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1438 /* No interrupt event indicated */
1439 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1442 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1443 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1444 i40evf_handle_aq_msg(dev);
1447 /* Link Status Change interrupt */
1448 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1449 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1453 i40evf_enable_irq0(hw);
1454 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1455 i40evf_dev_alarm_handler, dev);
1459 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1462 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1463 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1465 PMD_INIT_FUNC_TRACE();
1467 /* assign ops func pointer */
1468 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1469 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1470 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1473 * For secondary processes, we don't initialise any further as primary
1474 * has already done this work.
1476 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1477 i40e_set_rx_function(eth_dev);
1478 i40e_set_tx_function(eth_dev);
1481 i40e_set_default_ptype_table(eth_dev);
1482 i40e_set_default_pctype_table(eth_dev);
1483 rte_eth_copy_pci_info(eth_dev, pci_dev);
1485 hw->vendor_id = pci_dev->id.vendor_id;
1486 hw->device_id = pci_dev->id.device_id;
1487 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1488 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1489 hw->bus.device = pci_dev->addr.devid;
1490 hw->bus.func = pci_dev->addr.function;
1491 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1492 hw->adapter_stopped = 0;
1493 hw->adapter_closed = 0;
1495 if(i40evf_init_vf(eth_dev) != 0) {
1496 PMD_INIT_LOG(ERR, "Init vf failed");
1500 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1501 i40evf_dev_alarm_handler, eth_dev);
1503 /* configure and enable device interrupt */
1504 i40evf_enable_irq0(hw);
1507 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1508 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1510 if (eth_dev->data->mac_addrs == NULL) {
1511 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1512 " store MAC addresses",
1513 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1516 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1517 ð_dev->data->mac_addrs[0]);
1523 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1525 PMD_INIT_FUNC_TRACE();
1527 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1530 eth_dev->dev_ops = NULL;
1531 eth_dev->rx_pkt_burst = NULL;
1532 eth_dev->tx_pkt_burst = NULL;
1534 if (i40evf_uninit_vf(eth_dev) != 0) {
1535 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1542 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1543 struct rte_pci_device *pci_dev)
1545 return rte_eth_dev_pci_generic_probe(pci_dev,
1546 sizeof(struct i40e_adapter), i40evf_dev_init);
1549 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1551 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1555 * virtual function driver struct
1557 static struct rte_pci_driver rte_i40evf_pmd = {
1558 .id_table = pci_id_i40evf_map,
1559 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1560 .probe = eth_i40evf_pci_probe,
1561 .remove = eth_i40evf_pci_remove,
1564 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1565 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1566 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1569 i40evf_dev_configure(struct rte_eth_dev *dev)
1571 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1572 struct i40e_adapter *ad =
1573 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1574 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1575 dev->data->nb_tx_queues);
1577 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1578 * allocation or vector Rx preconditions we will reset it.
1580 ad->rx_bulk_alloc_allowed = true;
1581 ad->rx_vec_allowed = true;
1582 ad->tx_simple_allowed = true;
1583 ad->tx_vec_allowed = true;
1585 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1588 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1589 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1590 ret = i40evf_request_queues(dev, num_queue_pairs);
1594 ret = i40evf_dev_reset(dev);
1599 return i40evf_init_vlan(dev);
1603 i40evf_init_vlan(struct rte_eth_dev *dev)
1605 /* Apply vlan offload setting */
1606 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1612 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1614 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1615 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1617 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1620 /* Vlan stripping setting */
1621 if (mask & ETH_VLAN_STRIP_MASK) {
1622 /* Enable or disable VLAN stripping */
1623 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1624 i40evf_enable_vlan_strip(dev);
1626 i40evf_disable_vlan_strip(dev);
1633 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1635 struct i40e_rx_queue *rxq;
1637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639 PMD_INIT_FUNC_TRACE();
1641 rxq = dev->data->rx_queues[rx_queue_id];
1643 err = i40e_alloc_rx_queue_mbufs(rxq);
1645 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1651 /* Init the RX tail register. */
1652 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1653 I40EVF_WRITE_FLUSH(hw);
1655 /* Ready to switch the queue on */
1656 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1658 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1662 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1668 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1670 struct i40e_rx_queue *rxq;
1673 rxq = dev->data->rx_queues[rx_queue_id];
1675 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1677 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1682 i40e_rx_queue_release_mbufs(rxq);
1683 i40e_reset_rx_queue(rxq);
1684 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1690 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1694 PMD_INIT_FUNC_TRACE();
1696 /* Ready to switch the queue on */
1697 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1699 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1703 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1709 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1711 struct i40e_tx_queue *txq;
1714 txq = dev->data->tx_queues[tx_queue_id];
1716 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1718 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1723 i40e_tx_queue_release_mbufs(txq);
1724 i40e_reset_tx_queue(txq);
1725 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1731 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1736 ret = i40evf_add_vlan(dev, vlan_id);
1738 ret = i40evf_del_vlan(dev,vlan_id);
1744 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1746 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747 struct rte_eth_dev_data *dev_data = dev->data;
1748 struct rte_pktmbuf_pool_private *mbp_priv;
1749 uint16_t buf_size, len;
1751 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1752 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1753 I40EVF_WRITE_FLUSH(hw);
1755 /* Calculate the maximum packet length allowed */
1756 mbp_priv = rte_mempool_get_priv(rxq->mp);
1757 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1758 RTE_PKTMBUF_HEADROOM);
1759 rxq->hs_mode = i40e_header_split_none;
1760 rxq->rx_hdr_len = 0;
1761 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1762 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1763 rxq->max_pkt_len = RTE_MIN(len,
1764 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1767 * Check if the jumbo frame and maximum packet length are set correctly
1769 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1770 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1771 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1772 PMD_DRV_LOG(ERR, "maximum packet length must be "
1773 "larger than %u and smaller than %u, as jumbo "
1774 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1775 (uint32_t)I40E_FRAME_SIZE_MAX);
1776 return I40E_ERR_CONFIG;
1779 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1780 rxq->max_pkt_len > ETHER_MAX_LEN) {
1781 PMD_DRV_LOG(ERR, "maximum packet length must be "
1782 "larger than %u and smaller than %u, as jumbo "
1783 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1784 (uint32_t)ETHER_MAX_LEN);
1785 return I40E_ERR_CONFIG;
1789 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1790 rxq->max_pkt_len > buf_size)
1791 dev_data->scattered_rx = 1;
1797 i40evf_rx_init(struct rte_eth_dev *dev)
1799 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1801 int ret = I40E_SUCCESS;
1802 struct i40e_rx_queue **rxq =
1803 (struct i40e_rx_queue **)dev->data->rx_queues;
1805 i40evf_config_rss(vf);
1806 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1807 if (!rxq[i] || !rxq[i]->q_set)
1809 ret = i40evf_rxq_init(dev, rxq[i]);
1810 if (ret != I40E_SUCCESS)
1813 if (ret == I40E_SUCCESS)
1814 i40e_set_rx_function(dev);
1820 i40evf_tx_init(struct rte_eth_dev *dev)
1823 struct i40e_tx_queue **txq =
1824 (struct i40e_tx_queue **)dev->data->tx_queues;
1825 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827 for (i = 0; i < dev->data->nb_tx_queues; i++)
1828 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1830 i40e_set_tx_function(dev);
1834 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1838 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1840 if (!rte_intr_allow_others(intr_handle)) {
1842 I40E_VFINT_DYN_CTL01,
1843 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1844 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1845 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1846 I40EVF_WRITE_FLUSH(hw);
1850 I40EVF_WRITE_FLUSH(hw);
1854 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1856 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1858 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1860 if (!rte_intr_allow_others(intr_handle)) {
1861 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1862 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1863 I40EVF_WRITE_FLUSH(hw);
1867 I40EVF_WRITE_FLUSH(hw);
1871 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1873 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877 i40e_calc_itr_interval(0, 0);
1880 msix_intr = intr_handle->intr_vec[queue_id];
1881 if (msix_intr == I40E_MISC_VEC_ID)
1882 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1883 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1884 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1885 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1887 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1890 I40E_VFINT_DYN_CTLN1(msix_intr -
1892 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1893 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1894 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1896 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1898 I40EVF_WRITE_FLUSH(hw);
1904 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1907 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1908 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911 msix_intr = intr_handle->intr_vec[queue_id];
1912 if (msix_intr == I40E_MISC_VEC_ID)
1913 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1916 I40E_VFINT_DYN_CTLN1(msix_intr -
1920 I40EVF_WRITE_FLUSH(hw);
1926 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1928 struct virtchnl_ether_addr_list *list;
1929 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1934 struct rte_ether_addr *addr;
1935 struct vf_cmd_info args;
1939 len = sizeof(struct virtchnl_ether_addr_list);
1940 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1941 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
1943 len += sizeof(struct virtchnl_ether_addr);
1944 if (len >= I40E_AQ_BUF_SZ) {
1950 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1952 PMD_DRV_LOG(ERR, "fail to allocate memory");
1956 for (i = begin; i < next_begin; i++) {
1957 addr = &dev->data->mac_addrs[i];
1958 if (rte_is_zero_ether_addr(addr))
1960 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1961 sizeof(addr->addr_bytes));
1962 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1963 addr->addr_bytes[0], addr->addr_bytes[1],
1964 addr->addr_bytes[2], addr->addr_bytes[3],
1965 addr->addr_bytes[4], addr->addr_bytes[5]);
1968 list->vsi_id = vf->vsi_res->vsi_id;
1969 list->num_elements = j;
1970 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1971 VIRTCHNL_OP_DEL_ETH_ADDR;
1972 args.in_args = (uint8_t *)list;
1973 args.in_args_size = len;
1974 args.out_buffer = vf->aq_resp;
1975 args.out_size = I40E_AQ_BUF_SZ;
1976 err = i40evf_execute_vf_cmd(dev, &args);
1978 PMD_DRV_LOG(ERR, "fail to execute command %s",
1979 add ? "OP_ADD_ETHER_ADDRESS" :
1980 "OP_DEL_ETHER_ADDRESS");
1989 } while (begin < I40E_NUM_MACADDR_MAX);
1993 i40evf_dev_start(struct rte_eth_dev *dev)
1995 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1996 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1998 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1999 uint32_t intr_vector = 0;
2001 PMD_INIT_FUNC_TRACE();
2003 hw->adapter_stopped = 0;
2005 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2006 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2007 dev->data->nb_tx_queues);
2009 /* check and configure queue intr-vector mapping */
2010 if (rte_intr_cap_multiple(intr_handle) &&
2011 dev->data->dev_conf.intr_conf.rxq) {
2012 intr_vector = dev->data->nb_rx_queues;
2013 if (rte_intr_efd_enable(intr_handle, intr_vector))
2017 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2018 intr_handle->intr_vec =
2019 rte_zmalloc("intr_vec",
2020 dev->data->nb_rx_queues * sizeof(int), 0);
2021 if (!intr_handle->intr_vec) {
2022 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2023 " intr_vec", dev->data->nb_rx_queues);
2028 if (i40evf_rx_init(dev) != 0){
2029 PMD_DRV_LOG(ERR, "failed to do RX init");
2033 i40evf_tx_init(dev);
2035 if (i40evf_configure_vsi_queues(dev) != 0) {
2036 PMD_DRV_LOG(ERR, "configure queues failed");
2039 if (i40evf_config_irq_map(dev)) {
2040 PMD_DRV_LOG(ERR, "config_irq_map failed");
2044 /* Set all mac addrs */
2045 i40evf_add_del_all_mac_addr(dev, TRUE);
2046 /* Set all multicast addresses */
2047 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2050 if (i40evf_start_queues(dev) != 0) {
2051 PMD_DRV_LOG(ERR, "enable queues failed");
2055 /* only enable interrupt in rx interrupt mode */
2056 if (dev->data->dev_conf.intr_conf.rxq != 0)
2057 rte_intr_enable(intr_handle);
2059 i40evf_enable_queues_intr(dev);
2064 i40evf_add_del_all_mac_addr(dev, FALSE);
2065 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2072 i40evf_dev_stop(struct rte_eth_dev *dev)
2074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2075 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2079 PMD_INIT_FUNC_TRACE();
2081 if (dev->data->dev_conf.intr_conf.rxq != 0)
2082 rte_intr_disable(intr_handle);
2084 if (hw->adapter_stopped == 1)
2086 i40evf_stop_queues(dev);
2087 i40evf_disable_queues_intr(dev);
2088 i40e_dev_clear_queues(dev);
2090 /* Clean datapath event and queue/vec mapping */
2091 rte_intr_efd_disable(intr_handle);
2092 if (intr_handle->intr_vec) {
2093 rte_free(intr_handle->intr_vec);
2094 intr_handle->intr_vec = NULL;
2096 /* remove all mac addrs */
2097 i40evf_add_del_all_mac_addr(dev, FALSE);
2098 /* remove all multicast addresses */
2099 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2101 hw->adapter_stopped = 1;
2106 i40evf_dev_link_update(struct rte_eth_dev *dev,
2107 __rte_unused int wait_to_complete)
2109 struct rte_eth_link new_link;
2110 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2112 * DPDK pf host provide interfacet to acquire link status
2113 * while Linux driver does not
2116 memset(&new_link, 0, sizeof(new_link));
2117 /* Linux driver PF host */
2118 switch (vf->link_speed) {
2119 case I40E_LINK_SPEED_100MB:
2120 new_link.link_speed = ETH_SPEED_NUM_100M;
2122 case I40E_LINK_SPEED_1GB:
2123 new_link.link_speed = ETH_SPEED_NUM_1G;
2125 case I40E_LINK_SPEED_10GB:
2126 new_link.link_speed = ETH_SPEED_NUM_10G;
2128 case I40E_LINK_SPEED_20GB:
2129 new_link.link_speed = ETH_SPEED_NUM_20G;
2131 case I40E_LINK_SPEED_25GB:
2132 new_link.link_speed = ETH_SPEED_NUM_25G;
2134 case I40E_LINK_SPEED_40GB:
2135 new_link.link_speed = ETH_SPEED_NUM_40G;
2138 new_link.link_speed = ETH_SPEED_NUM_100M;
2141 /* full duplex only */
2142 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2143 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2145 new_link.link_autoneg =
2146 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2148 return rte_eth_linkstatus_set(dev, &new_link);
2152 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2154 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2157 /* If enabled, just return */
2158 if (vf->promisc_unicast_enabled)
2161 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2163 vf->promisc_unicast_enabled = TRUE;
2167 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2169 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2172 /* If disabled, just return */
2173 if (!vf->promisc_unicast_enabled)
2176 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2178 vf->promisc_unicast_enabled = FALSE;
2182 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2184 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2187 /* If enabled, just return */
2188 if (vf->promisc_multicast_enabled)
2191 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2193 vf->promisc_multicast_enabled = TRUE;
2197 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2199 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2202 /* If enabled, just return */
2203 if (!vf->promisc_multicast_enabled)
2206 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2208 vf->promisc_multicast_enabled = FALSE;
2212 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2214 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2216 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2217 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2218 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2219 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2220 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2221 dev_info->min_mtu = ETHER_MIN_MTU;
2222 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2223 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2224 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2225 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2226 dev_info->rx_queue_offload_capa = 0;
2227 dev_info->rx_offload_capa =
2228 DEV_RX_OFFLOAD_VLAN_STRIP |
2229 DEV_RX_OFFLOAD_QINQ_STRIP |
2230 DEV_RX_OFFLOAD_IPV4_CKSUM |
2231 DEV_RX_OFFLOAD_UDP_CKSUM |
2232 DEV_RX_OFFLOAD_TCP_CKSUM |
2233 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2234 DEV_RX_OFFLOAD_SCATTER |
2235 DEV_RX_OFFLOAD_JUMBO_FRAME |
2236 DEV_RX_OFFLOAD_VLAN_FILTER;
2238 dev_info->tx_queue_offload_capa = 0;
2239 dev_info->tx_offload_capa =
2240 DEV_TX_OFFLOAD_VLAN_INSERT |
2241 DEV_TX_OFFLOAD_QINQ_INSERT |
2242 DEV_TX_OFFLOAD_IPV4_CKSUM |
2243 DEV_TX_OFFLOAD_UDP_CKSUM |
2244 DEV_TX_OFFLOAD_TCP_CKSUM |
2245 DEV_TX_OFFLOAD_SCTP_CKSUM |
2246 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2247 DEV_TX_OFFLOAD_TCP_TSO |
2248 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2249 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2250 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2251 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2252 DEV_TX_OFFLOAD_MULTI_SEGS;
2254 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2256 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2257 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2258 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2260 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2265 dev_info->default_txconf = (struct rte_eth_txconf) {
2267 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2268 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2269 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2271 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2272 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2276 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2277 .nb_max = I40E_MAX_RING_DESC,
2278 .nb_min = I40E_MIN_RING_DESC,
2279 .nb_align = I40E_ALIGN_RING_DESC,
2282 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2283 .nb_max = I40E_MAX_RING_DESC,
2284 .nb_min = I40E_MIN_RING_DESC,
2285 .nb_align = I40E_ALIGN_RING_DESC,
2290 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2293 struct i40e_eth_stats *pstats = NULL;
2294 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2295 struct i40e_vsi *vsi = &vf->vsi;
2297 ret = i40evf_query_stats(dev, &pstats);
2299 i40evf_update_stats(vsi, pstats);
2301 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2302 pstats->rx_broadcast;
2303 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2305 stats->imissed = pstats->rx_discards;
2306 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2307 stats->ibytes = pstats->rx_bytes;
2308 stats->obytes = pstats->tx_bytes;
2310 PMD_DRV_LOG(ERR, "Get statistics failed");
2316 i40evf_dev_close(struct rte_eth_dev *dev)
2318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320 i40evf_dev_stop(dev);
2321 i40e_dev_free_queues(dev);
2323 * disable promiscuous mode before reset vf
2324 * it is a workaround solution when work with kernel driver
2325 * and it is not the normal way
2327 i40evf_dev_promiscuous_disable(dev);
2328 i40evf_dev_allmulticast_disable(dev);
2329 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2331 i40evf_reset_vf(dev);
2332 i40e_shutdown_adminq(hw);
2333 i40evf_disable_irq0(hw);
2334 hw->adapter_closed = 1;
2338 * Reset VF device only to re-initialize resources in PMD layer
2341 i40evf_dev_reset(struct rte_eth_dev *dev)
2345 ret = i40evf_dev_uninit(dev);
2349 ret = i40evf_dev_init(dev);
2355 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2357 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2358 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2364 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2365 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2368 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2372 uint32_t *lut_dw = (uint32_t *)lut;
2373 uint16_t i, lut_size_dw = lut_size / 4;
2375 for (i = 0; i < lut_size_dw; i++)
2376 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2383 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2392 vf = I40E_VSI_TO_VF(vsi);
2393 hw = I40E_VSI_TO_HW(vsi);
2395 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2396 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2399 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2403 uint32_t *lut_dw = (uint32_t *)lut;
2404 uint16_t i, lut_size_dw = lut_size / 4;
2406 for (i = 0; i < lut_size_dw; i++)
2407 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2408 I40EVF_WRITE_FLUSH(hw);
2415 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2416 struct rte_eth_rss_reta_entry64 *reta_conf,
2419 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2421 uint16_t i, idx, shift;
2424 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2425 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2426 "(%d) doesn't match the number of hardware can "
2427 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2431 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2433 PMD_DRV_LOG(ERR, "No memory can be allocated");
2436 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2439 for (i = 0; i < reta_size; i++) {
2440 idx = i / RTE_RETA_GROUP_SIZE;
2441 shift = i % RTE_RETA_GROUP_SIZE;
2442 if (reta_conf[idx].mask & (1ULL << shift))
2443 lut[i] = reta_conf[idx].reta[shift];
2445 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2454 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2455 struct rte_eth_rss_reta_entry64 *reta_conf,
2458 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2459 uint16_t i, idx, shift;
2463 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2464 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2465 "(%d) doesn't match the number of hardware can "
2466 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2470 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2472 PMD_DRV_LOG(ERR, "No memory can be allocated");
2476 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2479 for (i = 0; i < reta_size; i++) {
2480 idx = i / RTE_RETA_GROUP_SIZE;
2481 shift = i % RTE_RETA_GROUP_SIZE;
2482 if (reta_conf[idx].mask & (1ULL << shift))
2483 reta_conf[idx].reta[shift] = lut[i];
2493 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2495 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2496 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2499 if (!key || key_len == 0) {
2500 PMD_DRV_LOG(DEBUG, "No key to be configured");
2502 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2504 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2508 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2509 struct i40e_aqc_get_set_rss_key_data *key_dw =
2510 (struct i40e_aqc_get_set_rss_key_data *)key;
2512 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2514 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2517 uint32_t *hash_key = (uint32_t *)key;
2520 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2521 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2522 I40EVF_WRITE_FLUSH(hw);
2529 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2531 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2532 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2535 if (!key || !key_len)
2538 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2539 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2540 (struct i40e_aqc_get_set_rss_key_data *)key);
2542 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2546 uint32_t *key_dw = (uint32_t *)key;
2549 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2550 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2552 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2558 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2560 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2564 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2565 rss_conf->rss_key_len);
2569 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2570 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2571 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2572 I40EVF_WRITE_FLUSH(hw);
2578 i40evf_disable_rss(struct i40e_vf *vf)
2580 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2582 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2583 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2584 I40EVF_WRITE_FLUSH(hw);
2588 i40evf_config_rss(struct i40e_vf *vf)
2590 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2591 struct rte_eth_rss_conf rss_conf;
2592 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2595 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2596 i40evf_disable_rss(vf);
2597 PMD_DRV_LOG(DEBUG, "RSS not configured");
2601 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2602 /* Fill out the look up table */
2603 for (i = 0, j = 0; i < nb_q; i++, j++) {
2606 lut = (lut << 8) | j;
2608 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2611 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2612 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2613 i40evf_disable_rss(vf);
2614 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2618 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2619 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2620 /* Calculate the default hash key */
2621 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2622 rss_key_default[i] = (uint32_t)rte_rand();
2623 rss_conf.rss_key = (uint8_t *)rss_key_default;
2624 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2628 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2632 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2633 struct rte_eth_rss_conf *rss_conf)
2635 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2636 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2640 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2641 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2643 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2644 if (rss_hf != 0) /* Enable RSS */
2650 if (rss_hf == 0) /* Disable RSS */
2653 return i40evf_hw_rss_hash_set(vf, rss_conf);
2657 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2658 struct rte_eth_rss_conf *rss_conf)
2660 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2664 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2665 &rss_conf->rss_key_len);
2667 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2668 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2669 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2675 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2677 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2678 struct rte_eth_dev_data *dev_data = vf->dev_data;
2679 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2682 /* check if mtu is within the allowed range */
2683 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2686 /* mtu setting is forbidden if port is start */
2687 if (dev_data->dev_started) {
2688 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2693 if (frame_size > ETHER_MAX_LEN)
2694 dev_data->dev_conf.rxmode.offloads |=
2695 DEV_RX_OFFLOAD_JUMBO_FRAME;
2697 dev_data->dev_conf.rxmode.offloads &=
2698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2699 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2705 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2706 struct rte_ether_addr *mac_addr)
2708 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2712 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2716 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2719 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2721 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2724 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2729 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2730 struct rte_ether_addr *mc_addrs,
2731 uint32_t mc_addrs_num, bool add)
2733 struct virtchnl_ether_addr_list *list;
2734 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2735 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2736 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2739 struct vf_cmd_info args;
2741 if (mc_addrs == NULL || mc_addrs_num == 0)
2744 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2747 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2748 list->vsi_id = vf->vsi_res->vsi_id;
2749 list->num_elements = mc_addrs_num;
2751 for (i = 0; i < mc_addrs_num; i++) {
2752 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2753 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2754 mc_addrs[i].addr_bytes[0],
2755 mc_addrs[i].addr_bytes[1],
2756 mc_addrs[i].addr_bytes[2],
2757 mc_addrs[i].addr_bytes[3],
2758 mc_addrs[i].addr_bytes[4],
2759 mc_addrs[i].addr_bytes[5]);
2763 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2764 sizeof(list->list[i].addr));
2767 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2768 args.in_args = cmd_buffer;
2769 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2770 i * sizeof(struct virtchnl_ether_addr);
2771 args.out_buffer = vf->aq_resp;
2772 args.out_size = I40E_AQ_BUF_SZ;
2773 err = i40evf_execute_vf_cmd(dev, &args);
2775 PMD_DRV_LOG(ERR, "fail to execute command %s",
2776 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2784 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2785 struct rte_ether_addr *mc_addrs,
2786 uint32_t mc_addrs_num)
2788 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2791 /* flush previous addresses */
2792 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2797 vf->mc_addrs_num = 0;
2800 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2805 vf->mc_addrs_num = mc_addrs_num;
2806 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));