1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct rte_ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct rte_ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct rte_ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr);
144 i40evf_dev_alarm_handler(void *param);
146 /* Default hash key buffer for RSS */
147 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
149 struct rte_i40evf_xstats_name_off {
150 char name[RTE_ETH_XSTATS_NAME_SIZE];
154 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
155 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
156 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
157 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
158 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
159 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
160 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
161 rx_unknown_protocol)},
162 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
163 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
164 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
165 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
166 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
167 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
170 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
171 sizeof(rte_i40evf_stats_strings[0]))
173 static const struct eth_dev_ops i40evf_eth_dev_ops = {
174 .dev_configure = i40evf_dev_configure,
175 .dev_start = i40evf_dev_start,
176 .dev_stop = i40evf_dev_stop,
177 .promiscuous_enable = i40evf_dev_promiscuous_enable,
178 .promiscuous_disable = i40evf_dev_promiscuous_disable,
179 .allmulticast_enable = i40evf_dev_allmulticast_enable,
180 .allmulticast_disable = i40evf_dev_allmulticast_disable,
181 .link_update = i40evf_dev_link_update,
182 .stats_get = i40evf_dev_stats_get,
183 .stats_reset = i40evf_dev_xstats_reset,
184 .xstats_get = i40evf_dev_xstats_get,
185 .xstats_get_names = i40evf_dev_xstats_get_names,
186 .xstats_reset = i40evf_dev_xstats_reset,
187 .dev_close = i40evf_dev_close,
188 .dev_reset = i40evf_dev_reset,
189 .dev_infos_get = i40evf_dev_info_get,
190 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
191 .vlan_filter_set = i40evf_vlan_filter_set,
192 .vlan_offload_set = i40evf_vlan_offload_set,
193 .rx_queue_start = i40evf_dev_rx_queue_start,
194 .rx_queue_stop = i40evf_dev_rx_queue_stop,
195 .tx_queue_start = i40evf_dev_tx_queue_start,
196 .tx_queue_stop = i40evf_dev_tx_queue_stop,
197 .rx_queue_setup = i40e_dev_rx_queue_setup,
198 .rx_queue_release = i40e_dev_rx_queue_release,
199 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
200 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
201 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
202 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
203 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
204 .tx_queue_setup = i40e_dev_tx_queue_setup,
205 .tx_queue_release = i40e_dev_tx_queue_release,
206 .rx_queue_count = i40e_dev_rx_queue_count,
207 .rxq_info_get = i40e_rxq_info_get,
208 .txq_info_get = i40e_txq_info_get,
209 .mac_addr_add = i40evf_add_mac_addr,
210 .mac_addr_remove = i40evf_del_mac_addr,
211 .set_mc_addr_list = i40evf_set_mc_addr_list,
212 .reta_update = i40evf_dev_rss_reta_update,
213 .reta_query = i40evf_dev_rss_reta_query,
214 .rss_hash_update = i40evf_dev_rss_hash_update,
215 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
216 .mtu_set = i40evf_dev_mtu_set,
217 .mac_addr_set = i40evf_set_default_mac_addr,
218 .tx_done_cleanup = i40e_tx_done_cleanup,
222 * Read data in admin queue to get msg from pf driver
224 static enum i40evf_aq_result
225 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
227 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
228 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
229 struct i40e_arq_event_info event;
230 enum virtchnl_ops opcode;
231 enum i40e_status_code retval;
233 enum i40evf_aq_result result = I40EVF_MSG_NON;
235 event.buf_len = data->buf_len;
236 event.msg_buf = data->msg;
237 ret = i40e_clean_arq_element(hw, &event, NULL);
238 /* Can't read any msg from adminQ */
240 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
241 result = I40EVF_MSG_ERR;
245 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
246 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
248 if (opcode == VIRTCHNL_OP_EVENT) {
249 struct virtchnl_pf_event *vpe =
250 (struct virtchnl_pf_event *)event.msg_buf;
252 result = I40EVF_MSG_SYS;
253 switch (vpe->event) {
254 case VIRTCHNL_EVENT_LINK_CHANGE:
256 vpe->event_data.link_event.link_status;
258 vpe->event_data.link_event.link_speed;
259 vf->pend_msg |= PFMSG_LINK_CHANGE;
260 PMD_DRV_LOG(INFO, "Link status update:%s",
261 vf->link_up ? "up" : "down");
263 case VIRTCHNL_EVENT_RESET_IMPENDING:
265 vf->pend_msg |= PFMSG_RESET_IMPENDING;
266 PMD_DRV_LOG(INFO, "vf is reseting");
268 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
269 vf->dev_closed = true;
270 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
271 PMD_DRV_LOG(INFO, "PF driver closed");
274 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
275 __func__, vpe->event);
278 /* async reply msg on command issued by vf previously */
279 result = I40EVF_MSG_CMD;
280 /* Actual data length read from PF */
281 data->msg_len = event.msg_len;
284 data->result = retval;
291 * clear current command. Only call in case execute
292 * _atomic_set_cmd successfully.
295 _clear_cmd(struct i40e_vf *vf)
298 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
302 * Check there is pending cmd in execution. If none, set new command.
305 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
307 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
308 VIRTCHNL_OP_UNKNOWN, ops);
311 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
316 #define MAX_TRY_TIMES 200
317 #define ASQ_DELAY_MS 10
320 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
323 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
324 struct i40evf_arq_msg_info info;
325 enum i40evf_aq_result ret;
328 if (_atomic_set_cmd(vf, args->ops))
331 info.msg = args->out_buffer;
332 info.buf_len = args->out_size;
333 info.ops = VIRTCHNL_OP_UNKNOWN;
334 info.result = I40E_SUCCESS;
336 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
337 args->in_args, args->in_args_size, NULL);
339 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
345 case VIRTCHNL_OP_RESET_VF:
346 /*no need to process in this function */
349 case VIRTCHNL_OP_VERSION:
350 case VIRTCHNL_OP_GET_VF_RESOURCES:
351 /* for init adminq commands, need to poll the response */
354 ret = i40evf_read_pfmsg(dev, &info);
355 vf->cmd_retval = info.result;
356 if (ret == I40EVF_MSG_CMD) {
359 } else if (ret == I40EVF_MSG_ERR)
361 rte_delay_ms(ASQ_DELAY_MS);
362 /* If don't read msg or read sys event, continue */
363 } while (i++ < MAX_TRY_TIMES);
366 case VIRTCHNL_OP_REQUEST_QUEUES:
368 * ignore async reply, only wait for system message,
369 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
370 * if not, means request queues failed.
374 ret = i40evf_read_pfmsg(dev, &info);
375 vf->cmd_retval = info.result;
376 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
379 } else if (ret == I40EVF_MSG_ERR ||
380 ret == I40EVF_MSG_CMD) {
383 rte_delay_ms(ASQ_DELAY_MS);
384 /* If don't read msg or read sys event, continue */
385 } while (i++ < MAX_TRY_TIMES);
390 /* for other adminq in running time, waiting the cmd done flag */
393 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
397 rte_delay_ms(ASQ_DELAY_MS);
398 /* If don't read msg or read sys event, continue */
399 } while (i++ < MAX_TRY_TIMES);
400 /* If there's no response is received, clear command */
401 if (i >= MAX_TRY_TIMES) {
402 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
408 return err | vf->cmd_retval;
412 * Check API version with sync wait until version read or fail from admin queue
415 i40evf_check_api_version(struct rte_eth_dev *dev)
417 struct virtchnl_version_info version, *pver;
419 struct vf_cmd_info args;
420 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
422 version.major = VIRTCHNL_VERSION_MAJOR;
423 version.minor = VIRTCHNL_VERSION_MINOR;
425 args.ops = VIRTCHNL_OP_VERSION;
426 args.in_args = (uint8_t *)&version;
427 args.in_args_size = sizeof(version);
428 args.out_buffer = vf->aq_resp;
429 args.out_size = I40E_AQ_BUF_SZ;
431 err = i40evf_execute_vf_cmd(dev, &args);
433 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
437 pver = (struct virtchnl_version_info *)args.out_buffer;
438 vf->version_major = pver->major;
439 vf->version_minor = pver->minor;
440 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
441 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
442 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
444 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
445 vf->version_major, vf->version_minor,
446 VIRTCHNL_VERSION_MAJOR,
447 VIRTCHNL_VERSION_MINOR);
455 i40evf_get_vf_resource(struct rte_eth_dev *dev)
457 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
458 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
460 struct vf_cmd_info args;
463 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
464 args.out_buffer = vf->aq_resp;
465 args.out_size = I40E_AQ_BUF_SZ;
467 caps = VIRTCHNL_VF_OFFLOAD_L2 |
468 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
469 VIRTCHNL_VF_OFFLOAD_RSS_REG |
470 VIRTCHNL_VF_OFFLOAD_VLAN |
471 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
472 args.in_args = (uint8_t *)∩︀
473 args.in_args_size = sizeof(caps);
476 args.in_args_size = 0;
478 err = i40evf_execute_vf_cmd(dev, &args);
481 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
485 len = sizeof(struct virtchnl_vf_resource) +
486 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
488 rte_memcpy(vf->vf_res, args.out_buffer,
489 RTE_MIN(args.out_size, len));
490 i40e_vf_parse_hw_config(hw, vf->vf_res);
496 i40evf_config_promisc(struct rte_eth_dev *dev,
498 bool enable_multicast)
500 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
502 struct vf_cmd_info args;
503 struct virtchnl_promisc_info promisc;
506 promisc.vsi_id = vf->vsi_res->vsi_id;
509 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
511 if (enable_multicast)
512 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
514 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
515 args.in_args = (uint8_t *)&promisc;
516 args.in_args_size = sizeof(promisc);
517 args.out_buffer = vf->aq_resp;
518 args.out_size = I40E_AQ_BUF_SZ;
520 err = i40evf_execute_vf_cmd(dev, &args);
523 PMD_DRV_LOG(ERR, "fail to execute command "
524 "CONFIG_PROMISCUOUS_MODE");
529 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
531 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
532 struct vf_cmd_info args;
535 memset(&args, 0, sizeof(args));
536 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
538 args.in_args_size = 0;
539 args.out_buffer = vf->aq_resp;
540 args.out_size = I40E_AQ_BUF_SZ;
541 ret = i40evf_execute_vf_cmd(dev, &args);
543 PMD_DRV_LOG(ERR, "Failed to execute command of "
544 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
550 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
552 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
553 struct vf_cmd_info args;
556 memset(&args, 0, sizeof(args));
557 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
559 args.in_args_size = 0;
560 args.out_buffer = vf->aq_resp;
561 args.out_size = I40E_AQ_BUF_SZ;
562 ret = i40evf_execute_vf_cmd(dev, &args);
564 PMD_DRV_LOG(ERR, "Failed to execute command of "
565 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
571 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
575 struct i40e_tx_queue *txq)
577 txq_info->vsi_id = vsi_id;
578 txq_info->queue_id = queue_id;
579 if (queue_id < nb_txq && txq) {
580 txq_info->ring_len = txq->nb_tx_desc;
581 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
586 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
590 uint32_t max_pkt_size,
591 struct i40e_rx_queue *rxq)
593 rxq_info->vsi_id = vsi_id;
594 rxq_info->queue_id = queue_id;
595 rxq_info->max_pkt_size = max_pkt_size;
596 if (queue_id < nb_rxq && rxq) {
597 rxq_info->ring_len = rxq->nb_rx_desc;
598 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
599 rxq_info->databuffer_size =
600 (rte_pktmbuf_data_room_size(rxq->mp) -
601 RTE_PKTMBUF_HEADROOM);
606 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
608 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
609 struct i40e_rx_queue **rxq =
610 (struct i40e_rx_queue **)dev->data->rx_queues;
611 struct i40e_tx_queue **txq =
612 (struct i40e_tx_queue **)dev->data->tx_queues;
613 struct virtchnl_vsi_queue_config_info *vc_vqci;
614 struct virtchnl_queue_pair_info *vc_qpi;
615 struct vf_cmd_info args;
616 uint16_t i, nb_qp = vf->num_queue_pairs;
617 const uint32_t size =
618 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
622 memset(buff, 0, sizeof(buff));
623 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
624 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
625 vc_vqci->num_queue_pairs = nb_qp;
627 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
628 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
629 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
630 txq ? txq[i] : NULL);
631 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
632 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
633 vf->max_pkt_len, rxq ? rxq[i] : NULL);
635 memset(&args, 0, sizeof(args));
636 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
637 args.in_args = (uint8_t *)vc_vqci;
638 args.in_args_size = size;
639 args.out_buffer = vf->aq_resp;
640 args.out_size = I40E_AQ_BUF_SZ;
641 ret = i40evf_execute_vf_cmd(dev, &args);
643 PMD_DRV_LOG(ERR, "Failed to execute command of "
644 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
650 i40evf_config_irq_map(struct rte_eth_dev *dev)
652 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
653 struct vf_cmd_info args;
654 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
655 sizeof(struct virtchnl_vector_map) * dev->data->nb_rx_queues];
656 struct virtchnl_irq_map_info *map_info;
657 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
658 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
663 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
664 rte_intr_allow_others(intr_handle))
665 vector_id = I40E_RX_VEC_START;
667 vector_id = I40E_MISC_VEC_ID;
669 nb_msix = RTE_MIN(vf->vf_res->max_vectors,
670 intr_handle->nb_efd);
672 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
673 map_info->num_vectors = dev->data->nb_rx_queues;
674 for (i = 0; i < dev->data->nb_rx_queues; i++) {
675 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
676 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
677 /* Always use default dynamic MSIX interrupt */
678 map_info->vecmap[i].vector_id = vector_id;
679 /* Don't map any tx queue */
680 map_info->vecmap[i].txq_map = 0;
681 map_info->vecmap[i].rxq_map = 1 << i;
682 if (rte_intr_dp_is_en(intr_handle))
683 intr_handle->intr_vec[i] = vector_id;
684 if (vector_id > I40E_MISC_VEC_ID)
686 if (vector_id > nb_msix)
687 vector_id = I40E_RX_VEC_START;
690 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
691 args.in_args = (u8 *)cmd_buffer;
692 args.in_args_size = sizeof(cmd_buffer);
693 args.out_buffer = vf->aq_resp;
694 args.out_size = I40E_AQ_BUF_SZ;
695 err = i40evf_execute_vf_cmd(dev, &args);
697 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
703 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
706 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
707 struct virtchnl_queue_select queue_select;
709 struct vf_cmd_info args;
710 memset(&queue_select, 0, sizeof(queue_select));
711 queue_select.vsi_id = vf->vsi_res->vsi_id;
714 queue_select.rx_queues |= 1 << qid;
716 queue_select.tx_queues |= 1 << qid;
719 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
721 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
722 args.in_args = (u8 *)&queue_select;
723 args.in_args_size = sizeof(queue_select);
724 args.out_buffer = vf->aq_resp;
725 args.out_size = I40E_AQ_BUF_SZ;
726 err = i40evf_execute_vf_cmd(dev, &args);
728 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
729 isrx ? "RX" : "TX", qid, on ? "on" : "off");
735 i40evf_start_queues(struct rte_eth_dev *dev)
737 struct rte_eth_dev_data *dev_data = dev->data;
739 struct i40e_rx_queue *rxq;
740 struct i40e_tx_queue *txq;
742 for (i = 0; i < dev->data->nb_rx_queues; i++) {
743 rxq = dev_data->rx_queues[i];
744 if (rxq->rx_deferred_start)
746 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
747 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
752 for (i = 0; i < dev->data->nb_tx_queues; i++) {
753 txq = dev_data->tx_queues[i];
754 if (txq->tx_deferred_start)
756 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
757 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
766 i40evf_stop_queues(struct rte_eth_dev *dev)
770 /* Stop TX queues first */
771 for (i = 0; i < dev->data->nb_tx_queues; i++) {
772 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
773 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
778 /* Then stop RX queues */
779 for (i = 0; i < dev->data->nb_rx_queues; i++) {
780 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
781 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
790 i40evf_add_mac_addr(struct rte_eth_dev *dev,
791 struct rte_ether_addr *addr,
792 __rte_unused uint32_t index,
793 __rte_unused uint32_t pool)
795 struct virtchnl_ether_addr_list *list;
796 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
797 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
798 sizeof(struct virtchnl_ether_addr)];
800 struct vf_cmd_info args;
802 if (rte_is_zero_ether_addr(addr)) {
803 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
804 addr->addr_bytes[0], addr->addr_bytes[1],
805 addr->addr_bytes[2], addr->addr_bytes[3],
806 addr->addr_bytes[4], addr->addr_bytes[5]);
807 return I40E_ERR_INVALID_MAC_ADDR;
810 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
811 list->vsi_id = vf->vsi_res->vsi_id;
812 list->num_elements = 1;
813 rte_memcpy(list->list[0].addr, addr->addr_bytes,
814 sizeof(addr->addr_bytes));
816 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
817 args.in_args = cmd_buffer;
818 args.in_args_size = sizeof(cmd_buffer);
819 args.out_buffer = vf->aq_resp;
820 args.out_size = I40E_AQ_BUF_SZ;
821 err = i40evf_execute_vf_cmd(dev, &args);
823 PMD_DRV_LOG(ERR, "fail to execute command "
824 "OP_ADD_ETHER_ADDRESS");
832 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
833 struct rte_ether_addr *addr)
835 struct virtchnl_ether_addr_list *list;
836 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
837 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
838 sizeof(struct virtchnl_ether_addr)];
840 struct vf_cmd_info args;
842 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
843 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
844 addr->addr_bytes[0], addr->addr_bytes[1],
845 addr->addr_bytes[2], addr->addr_bytes[3],
846 addr->addr_bytes[4], addr->addr_bytes[5]);
850 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
851 list->vsi_id = vf->vsi_res->vsi_id;
852 list->num_elements = 1;
853 rte_memcpy(list->list[0].addr, addr->addr_bytes,
854 sizeof(addr->addr_bytes));
856 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
857 args.in_args = cmd_buffer;
858 args.in_args_size = sizeof(cmd_buffer);
859 args.out_buffer = vf->aq_resp;
860 args.out_size = I40E_AQ_BUF_SZ;
861 err = i40evf_execute_vf_cmd(dev, &args);
863 PMD_DRV_LOG(ERR, "fail to execute command "
864 "OP_DEL_ETHER_ADDRESS");
871 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
873 struct rte_eth_dev_data *data = dev->data;
874 struct rte_ether_addr *addr;
876 addr = &data->mac_addrs[index];
878 i40evf_del_mac_addr_by_addr(dev, addr);
882 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
884 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
885 struct virtchnl_queue_select q_stats;
887 struct vf_cmd_info args;
889 memset(&q_stats, 0, sizeof(q_stats));
890 q_stats.vsi_id = vf->vsi_res->vsi_id;
891 args.ops = VIRTCHNL_OP_GET_STATS;
892 args.in_args = (u8 *)&q_stats;
893 args.in_args_size = sizeof(q_stats);
894 args.out_buffer = vf->aq_resp;
895 args.out_size = I40E_AQ_BUF_SZ;
897 err = i40evf_execute_vf_cmd(dev, &args);
899 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
903 *pstats = (struct i40e_eth_stats *)args.out_buffer;
908 i40evf_stat_update_48(uint64_t *offset,
911 if (*stat >= *offset)
912 *stat = *stat - *offset;
914 *stat = (uint64_t)((*stat +
915 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
917 *stat &= I40E_48_BIT_MASK;
921 i40evf_stat_update_32(uint64_t *offset,
924 if (*stat >= *offset)
925 *stat = (uint64_t)(*stat - *offset);
927 *stat = (uint64_t)((*stat +
928 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
932 i40evf_update_stats(struct i40e_vsi *vsi,
933 struct i40e_eth_stats *nes)
935 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
937 i40evf_stat_update_48(&oes->rx_bytes,
939 i40evf_stat_update_48(&oes->rx_unicast,
941 i40evf_stat_update_48(&oes->rx_multicast,
943 i40evf_stat_update_48(&oes->rx_broadcast,
945 i40evf_stat_update_32(&oes->rx_discards,
947 i40evf_stat_update_32(&oes->rx_unknown_protocol,
948 &nes->rx_unknown_protocol);
949 i40evf_stat_update_48(&oes->tx_bytes,
951 i40evf_stat_update_48(&oes->tx_unicast,
953 i40evf_stat_update_48(&oes->tx_multicast,
955 i40evf_stat_update_48(&oes->tx_broadcast,
957 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
958 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
962 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
965 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
966 struct i40e_eth_stats *pstats = NULL;
968 /* read stat values to clear hardware registers */
969 ret = i40evf_query_stats(dev, &pstats);
971 /* set stats offset base on current values */
973 vf->vsi.eth_stats_offset = *pstats;
978 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
979 struct rte_eth_xstat_name *xstats_names,
980 __rte_unused unsigned limit)
984 if (xstats_names != NULL)
985 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
986 snprintf(xstats_names[i].name,
987 sizeof(xstats_names[i].name),
988 "%s", rte_i40evf_stats_strings[i].name);
990 return I40EVF_NB_XSTATS;
993 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
994 struct rte_eth_xstat *xstats, unsigned n)
998 struct i40e_eth_stats *pstats = NULL;
999 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1000 struct i40e_vsi *vsi = &vf->vsi;
1002 if (n < I40EVF_NB_XSTATS)
1003 return I40EVF_NB_XSTATS;
1005 ret = i40evf_query_stats(dev, &pstats);
1012 i40evf_update_stats(vsi, pstats);
1014 /* loop over xstats array and values from pstats */
1015 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1017 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1018 rte_i40evf_stats_strings[i].offset);
1021 return I40EVF_NB_XSTATS;
1025 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1027 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1028 struct virtchnl_vlan_filter_list *vlan_list;
1029 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1032 struct vf_cmd_info args;
1034 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1035 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1036 vlan_list->num_elements = 1;
1037 vlan_list->vlan_id[0] = vlanid;
1039 args.ops = VIRTCHNL_OP_ADD_VLAN;
1040 args.in_args = (u8 *)&cmd_buffer;
1041 args.in_args_size = sizeof(cmd_buffer);
1042 args.out_buffer = vf->aq_resp;
1043 args.out_size = I40E_AQ_BUF_SZ;
1044 err = i40evf_execute_vf_cmd(dev, &args);
1046 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1052 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1054 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1055 struct virtchnl_vf_res_request vfres;
1056 struct vf_cmd_info args;
1059 vfres.num_queue_pairs = num;
1061 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1062 args.in_args = (u8 *)&vfres;
1063 args.in_args_size = sizeof(vfres);
1064 args.out_buffer = vf->aq_resp;
1065 args.out_size = I40E_AQ_BUF_SZ;
1067 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1068 err = i40evf_execute_vf_cmd(dev, &args);
1070 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1072 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1073 i40evf_dev_alarm_handler, dev);
1078 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1080 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1081 struct virtchnl_vlan_filter_list *vlan_list;
1082 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1085 struct vf_cmd_info args;
1087 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1088 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1089 vlan_list->num_elements = 1;
1090 vlan_list->vlan_id[0] = vlanid;
1092 args.ops = VIRTCHNL_OP_DEL_VLAN;
1093 args.in_args = (u8 *)&cmd_buffer;
1094 args.in_args_size = sizeof(cmd_buffer);
1095 args.out_buffer = vf->aq_resp;
1096 args.out_size = I40E_AQ_BUF_SZ;
1097 err = i40evf_execute_vf_cmd(dev, &args);
1099 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1104 static const struct rte_pci_id pci_id_i40evf_map[] = {
1105 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1106 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1107 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1108 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1109 { .vendor_id = 0, /* sentinel */ },
1114 i40evf_disable_irq0(struct i40e_hw *hw)
1116 /* Disable all interrupt types */
1117 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1118 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1119 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1120 I40EVF_WRITE_FLUSH(hw);
1125 i40evf_enable_irq0(struct i40e_hw *hw)
1127 /* Enable admin queue interrupt trigger */
1130 i40evf_disable_irq0(hw);
1131 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1132 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1133 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1134 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1136 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1137 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1138 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1139 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1141 I40EVF_WRITE_FLUSH(hw);
1145 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1148 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1151 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1152 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1153 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1154 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1155 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1156 reset == VIRTCHNL_VFR_COMPLETED)
1161 if (i >= MAX_RESET_WAIT_CNT)
1164 vf->vf_reset = false;
1165 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1170 i40evf_reset_vf(struct rte_eth_dev *dev)
1173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1176 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1180 * After issuing vf reset command to pf, pf won't necessarily
1181 * reset vf, it depends on what state it exactly is. If it's not
1182 * initialized yet, it won't have vf reset since it's in a certain
1183 * state. If not, it will try to reset. Even vf is reset, pf will
1184 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1185 * it to ACTIVE. In this duration, vf may not catch the moment that
1186 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1190 ret = i40evf_check_vf_reset_done(dev);
1192 PMD_INIT_LOG(ERR, "VF is still resetting");
1200 i40evf_init_vf(struct rte_eth_dev *dev)
1203 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1206 i40e_calc_itr_interval(0, 0);
1208 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1209 vf->dev_data = dev->data;
1210 err = i40e_set_mac_type(hw);
1212 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1216 err = i40evf_check_vf_reset_done(dev);
1220 i40e_init_adminq_parameter(hw);
1221 err = i40e_init_adminq(hw);
1223 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1227 /* Reset VF and wait until it's complete */
1228 if (i40evf_reset_vf(dev)) {
1229 PMD_INIT_LOG(ERR, "reset NIC failed");
1233 /* VF reset, shutdown admin queue and initialize again */
1234 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1235 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1239 i40e_init_adminq_parameter(hw);
1240 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1241 PMD_INIT_LOG(ERR, "init_adminq failed");
1245 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1247 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1250 if (i40evf_check_api_version(dev) != 0) {
1251 PMD_INIT_LOG(ERR, "check_api version failed");
1254 bufsz = sizeof(struct virtchnl_vf_resource) +
1255 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1256 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1258 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1262 if (i40evf_get_vf_resource(dev) != 0) {
1263 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1267 /* got VF config message back from PF, now we can parse it */
1268 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1269 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1270 vf->vsi_res = &vf->vf_res->vsi_res[i];
1274 PMD_INIT_LOG(ERR, "no LAN VSI found");
1278 if (hw->mac.type == I40E_MAC_X722_VF)
1279 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1280 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1282 switch (vf->vsi_res->vsi_type) {
1283 case VIRTCHNL_VSI_SRIOV:
1284 vf->vsi.type = I40E_VSI_SRIOV;
1287 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1290 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1291 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1293 /* Store the MAC address configured by host, or generate random one */
1294 if (rte_is_valid_assigned_ether_addr(
1295 (struct rte_ether_addr *)hw->mac.addr))
1296 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1298 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1300 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1301 (I40E_ITR_INDEX_DEFAULT <<
1302 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1304 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1305 I40EVF_WRITE_FLUSH(hw);
1310 rte_free(vf->vf_res);
1313 rte_free(vf->aq_resp);
1315 i40e_shutdown_adminq(hw); /* ignore error */
1321 i40evf_uninit_vf(struct rte_eth_dev *dev)
1323 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325 PMD_INIT_FUNC_TRACE();
1327 if (hw->adapter_closed == 0)
1328 i40evf_dev_close(dev);
1334 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1335 __rte_unused uint16_t msglen)
1337 struct virtchnl_pf_event *pf_msg =
1338 (struct virtchnl_pf_event *)msg;
1339 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1341 switch (pf_msg->event) {
1342 case VIRTCHNL_EVENT_RESET_IMPENDING:
1343 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1344 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1347 case VIRTCHNL_EVENT_LINK_CHANGE:
1348 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1349 vf->link_up = pf_msg->event_data.link_event.link_status;
1350 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1352 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1353 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1356 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1362 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1364 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1366 struct i40e_arq_event_info info;
1367 uint16_t pending, aq_opc;
1368 enum virtchnl_ops msg_opc;
1369 enum i40e_status_code msg_ret;
1372 info.buf_len = I40E_AQ_BUF_SZ;
1374 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1377 info.msg_buf = vf->aq_resp;
1381 ret = i40e_clean_arq_element(hw, &info, &pending);
1383 if (ret != I40E_SUCCESS) {
1384 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1388 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1389 /* For the message sent from pf to vf, opcode is stored in
1390 * cookie_high of struct i40e_aq_desc, while return error code
1391 * are stored in cookie_low, Which is done by
1392 * i40e_aq_send_msg_to_vf in PF driver.*/
1393 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1394 info.desc.cookie_high);
1395 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1396 info.desc.cookie_low);
1398 case i40e_aqc_opc_send_msg_to_vf:
1399 if (msg_opc == VIRTCHNL_OP_EVENT)
1401 i40evf_handle_pf_event(dev, info.msg_buf,
1404 /* read message and it's expected one */
1405 if (msg_opc == vf->pend_cmd) {
1406 vf->cmd_retval = msg_ret;
1407 /* prevent compiler reordering */
1408 rte_compiler_barrier();
1411 PMD_DRV_LOG(ERR, "command mismatch,"
1412 "expect %u, get %u",
1413 vf->pend_cmd, msg_opc);
1414 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1415 " opcode = %d", msg_opc);
1419 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1427 * Interrupt handler triggered by NIC for handling
1428 * specific interrupt. Only adminq interrupt is processed in VF.
1431 * Pointer to interrupt handle.
1433 * The address of parameter (struct rte_eth_dev *) regsitered before.
1439 i40evf_dev_alarm_handler(void *param)
1441 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 i40evf_disable_irq0(hw);
1447 /* read out interrupt causes */
1448 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1450 /* No interrupt event indicated */
1451 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1454 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1455 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1456 i40evf_handle_aq_msg(dev);
1459 /* Link Status Change interrupt */
1460 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1461 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1465 i40evf_enable_irq0(hw);
1466 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1467 i40evf_dev_alarm_handler, dev);
1471 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1474 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1475 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1477 PMD_INIT_FUNC_TRACE();
1479 /* assign ops func pointer */
1480 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1481 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1482 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1485 * For secondary processes, we don't initialise any further as primary
1486 * has already done this work.
1488 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1489 i40e_set_rx_function(eth_dev);
1490 i40e_set_tx_function(eth_dev);
1493 i40e_set_default_ptype_table(eth_dev);
1494 rte_eth_copy_pci_info(eth_dev, pci_dev);
1496 hw->vendor_id = pci_dev->id.vendor_id;
1497 hw->device_id = pci_dev->id.device_id;
1498 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1499 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1500 hw->bus.device = pci_dev->addr.devid;
1501 hw->bus.func = pci_dev->addr.function;
1502 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1503 hw->adapter_stopped = 0;
1504 hw->adapter_closed = 0;
1506 /* Pass the information to the rte_eth_dev_close() that it should also
1507 * release the private port resources.
1509 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1511 if(i40evf_init_vf(eth_dev) != 0) {
1512 PMD_INIT_LOG(ERR, "Init vf failed");
1516 i40e_set_default_pctype_table(eth_dev);
1517 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1518 i40evf_dev_alarm_handler, eth_dev);
1520 /* configure and enable device interrupt */
1521 i40evf_enable_irq0(hw);
1524 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1525 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1527 if (eth_dev->data->mac_addrs == NULL) {
1528 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1529 " store MAC addresses",
1530 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1533 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1534 ð_dev->data->mac_addrs[0]);
1540 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1542 PMD_INIT_FUNC_TRACE();
1544 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1547 if (i40evf_uninit_vf(eth_dev) != 0) {
1548 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1555 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1556 struct rte_pci_device *pci_dev)
1558 return rte_eth_dev_pci_generic_probe(pci_dev,
1559 sizeof(struct i40e_adapter), i40evf_dev_init);
1562 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1564 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1568 * virtual function driver struct
1570 static struct rte_pci_driver rte_i40evf_pmd = {
1571 .id_table = pci_id_i40evf_map,
1572 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1573 .probe = eth_i40evf_pci_probe,
1574 .remove = eth_i40evf_pci_remove,
1577 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1578 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1579 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1582 i40evf_dev_configure(struct rte_eth_dev *dev)
1584 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1585 struct i40e_adapter *ad =
1586 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1587 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1588 dev->data->nb_tx_queues);
1590 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1591 * allocation or vector Rx preconditions we will reset it.
1593 ad->rx_bulk_alloc_allowed = true;
1594 ad->rx_vec_allowed = true;
1595 ad->tx_simple_allowed = true;
1596 ad->tx_vec_allowed = true;
1598 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1601 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1602 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1603 ret = i40evf_request_queues(dev, num_queue_pairs);
1607 ret = i40evf_dev_reset(dev);
1612 return i40evf_init_vlan(dev);
1616 i40evf_init_vlan(struct rte_eth_dev *dev)
1618 /* Apply vlan offload setting */
1619 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1625 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1627 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1628 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1630 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1633 /* Vlan stripping setting */
1634 if (mask & ETH_VLAN_STRIP_MASK) {
1635 /* Enable or disable VLAN stripping */
1636 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1637 i40evf_enable_vlan_strip(dev);
1639 i40evf_disable_vlan_strip(dev);
1646 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1648 struct i40e_rx_queue *rxq;
1650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652 PMD_INIT_FUNC_TRACE();
1654 rxq = dev->data->rx_queues[rx_queue_id];
1656 err = i40e_alloc_rx_queue_mbufs(rxq);
1658 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1664 /* Init the RX tail register. */
1665 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1666 I40EVF_WRITE_FLUSH(hw);
1668 /* Ready to switch the queue on */
1669 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1671 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1675 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1681 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1683 struct i40e_rx_queue *rxq;
1686 rxq = dev->data->rx_queues[rx_queue_id];
1688 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1690 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1695 i40e_rx_queue_release_mbufs(rxq);
1696 i40e_reset_rx_queue(rxq);
1697 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1703 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1707 PMD_INIT_FUNC_TRACE();
1709 /* Ready to switch the queue on */
1710 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1712 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1716 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1722 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1724 struct i40e_tx_queue *txq;
1727 txq = dev->data->tx_queues[tx_queue_id];
1729 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1731 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1736 i40e_tx_queue_release_mbufs(txq);
1737 i40e_reset_tx_queue(txq);
1738 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1744 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1749 ret = i40evf_add_vlan(dev, vlan_id);
1751 ret = i40evf_del_vlan(dev,vlan_id);
1757 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1759 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1760 struct rte_eth_dev_data *dev_data = dev->data;
1761 struct rte_pktmbuf_pool_private *mbp_priv;
1762 uint16_t buf_size, len;
1764 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1765 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1766 I40EVF_WRITE_FLUSH(hw);
1768 /* Calculate the maximum packet length allowed */
1769 mbp_priv = rte_mempool_get_priv(rxq->mp);
1770 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1771 RTE_PKTMBUF_HEADROOM);
1772 rxq->hs_mode = i40e_header_split_none;
1773 rxq->rx_hdr_len = 0;
1774 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1775 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1776 rxq->max_pkt_len = RTE_MIN(len,
1777 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1780 * Check if the jumbo frame and maximum packet length are set correctly
1782 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1783 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1784 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1785 PMD_DRV_LOG(ERR, "maximum packet length must be "
1786 "larger than %u and smaller than %u, as jumbo "
1787 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1788 (uint32_t)I40E_FRAME_SIZE_MAX);
1789 return I40E_ERR_CONFIG;
1792 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1793 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1794 PMD_DRV_LOG(ERR, "maximum packet length must be "
1795 "larger than %u and smaller than %u, as jumbo "
1796 "frame is disabled",
1797 (uint32_t)RTE_ETHER_MIN_LEN,
1798 (uint32_t)RTE_ETHER_MAX_LEN);
1799 return I40E_ERR_CONFIG;
1803 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1804 rxq->max_pkt_len > buf_size)
1805 dev_data->scattered_rx = 1;
1811 i40evf_rx_init(struct rte_eth_dev *dev)
1813 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1815 int ret = I40E_SUCCESS;
1816 struct i40e_rx_queue **rxq =
1817 (struct i40e_rx_queue **)dev->data->rx_queues;
1819 i40evf_config_rss(vf);
1820 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1821 if (!rxq[i] || !rxq[i]->q_set)
1823 ret = i40evf_rxq_init(dev, rxq[i]);
1824 if (ret != I40E_SUCCESS)
1827 if (ret == I40E_SUCCESS)
1828 i40e_set_rx_function(dev);
1834 i40evf_tx_init(struct rte_eth_dev *dev)
1837 struct i40e_tx_queue **txq =
1838 (struct i40e_tx_queue **)dev->data->tx_queues;
1839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841 for (i = 0; i < dev->data->nb_tx_queues; i++)
1842 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1844 i40e_set_tx_function(dev);
1848 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1851 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1852 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1854 if (!rte_intr_allow_others(intr_handle)) {
1856 I40E_VFINT_DYN_CTL01,
1857 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1858 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1859 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1860 I40EVF_WRITE_FLUSH(hw);
1864 I40EVF_WRITE_FLUSH(hw);
1868 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1872 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1874 if (!rte_intr_allow_others(intr_handle)) {
1875 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1876 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1877 I40EVF_WRITE_FLUSH(hw);
1881 I40EVF_WRITE_FLUSH(hw);
1885 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1887 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1888 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891 i40e_calc_itr_interval(0, 0);
1894 msix_intr = intr_handle->intr_vec[queue_id];
1895 if (msix_intr == I40E_MISC_VEC_ID)
1896 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1897 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1898 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1899 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1901 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1904 I40E_VFINT_DYN_CTLN1(msix_intr -
1906 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1907 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1908 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1910 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1912 I40EVF_WRITE_FLUSH(hw);
1918 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1920 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1921 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925 msix_intr = intr_handle->intr_vec[queue_id];
1926 if (msix_intr == I40E_MISC_VEC_ID)
1927 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1930 I40E_VFINT_DYN_CTLN1(msix_intr -
1934 I40EVF_WRITE_FLUSH(hw);
1940 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1942 struct virtchnl_ether_addr_list *list;
1943 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1948 struct rte_ether_addr *addr;
1949 struct vf_cmd_info args;
1953 len = sizeof(struct virtchnl_ether_addr_list);
1954 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1955 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
1957 len += sizeof(struct virtchnl_ether_addr);
1958 if (len >= I40E_AQ_BUF_SZ) {
1964 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1966 PMD_DRV_LOG(ERR, "fail to allocate memory");
1970 for (i = begin; i < next_begin; i++) {
1971 addr = &dev->data->mac_addrs[i];
1972 if (rte_is_zero_ether_addr(addr))
1974 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1975 sizeof(addr->addr_bytes));
1976 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1977 addr->addr_bytes[0], addr->addr_bytes[1],
1978 addr->addr_bytes[2], addr->addr_bytes[3],
1979 addr->addr_bytes[4], addr->addr_bytes[5]);
1982 list->vsi_id = vf->vsi_res->vsi_id;
1983 list->num_elements = j;
1984 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1985 VIRTCHNL_OP_DEL_ETH_ADDR;
1986 args.in_args = (uint8_t *)list;
1987 args.in_args_size = len;
1988 args.out_buffer = vf->aq_resp;
1989 args.out_size = I40E_AQ_BUF_SZ;
1990 err = i40evf_execute_vf_cmd(dev, &args);
1992 PMD_DRV_LOG(ERR, "fail to execute command %s",
1993 add ? "OP_ADD_ETHER_ADDRESS" :
1994 "OP_DEL_ETHER_ADDRESS");
2003 } while (begin < I40E_NUM_MACADDR_MAX);
2007 i40evf_dev_start(struct rte_eth_dev *dev)
2009 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2012 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2013 uint32_t intr_vector = 0;
2015 PMD_INIT_FUNC_TRACE();
2017 hw->adapter_stopped = 0;
2019 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2020 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2021 dev->data->nb_tx_queues);
2023 /* check and configure queue intr-vector mapping */
2024 if (rte_intr_cap_multiple(intr_handle) &&
2025 dev->data->dev_conf.intr_conf.rxq) {
2026 intr_vector = dev->data->nb_rx_queues;
2027 if (rte_intr_efd_enable(intr_handle, intr_vector))
2031 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2032 intr_handle->intr_vec =
2033 rte_zmalloc("intr_vec",
2034 dev->data->nb_rx_queues * sizeof(int), 0);
2035 if (!intr_handle->intr_vec) {
2036 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2037 " intr_vec", dev->data->nb_rx_queues);
2042 if (i40evf_rx_init(dev) != 0){
2043 PMD_DRV_LOG(ERR, "failed to do RX init");
2047 i40evf_tx_init(dev);
2049 if (i40evf_configure_vsi_queues(dev) != 0) {
2050 PMD_DRV_LOG(ERR, "configure queues failed");
2053 if (i40evf_config_irq_map(dev)) {
2054 PMD_DRV_LOG(ERR, "config_irq_map failed");
2058 /* Set all mac addrs */
2059 i40evf_add_del_all_mac_addr(dev, TRUE);
2060 /* Set all multicast addresses */
2061 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2064 if (i40evf_start_queues(dev) != 0) {
2065 PMD_DRV_LOG(ERR, "enable queues failed");
2069 /* only enable interrupt in rx interrupt mode */
2070 if (dev->data->dev_conf.intr_conf.rxq != 0)
2071 rte_intr_enable(intr_handle);
2073 i40evf_enable_queues_intr(dev);
2078 i40evf_add_del_all_mac_addr(dev, FALSE);
2079 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2086 i40evf_dev_stop(struct rte_eth_dev *dev)
2088 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2089 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2090 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2093 PMD_INIT_FUNC_TRACE();
2095 if (dev->data->dev_conf.intr_conf.rxq != 0)
2096 rte_intr_disable(intr_handle);
2098 if (hw->adapter_stopped == 1)
2100 i40evf_stop_queues(dev);
2101 i40evf_disable_queues_intr(dev);
2102 i40e_dev_clear_queues(dev);
2104 /* Clean datapath event and queue/vec mapping */
2105 rte_intr_efd_disable(intr_handle);
2106 if (intr_handle->intr_vec) {
2107 rte_free(intr_handle->intr_vec);
2108 intr_handle->intr_vec = NULL;
2110 /* remove all mac addrs */
2111 i40evf_add_del_all_mac_addr(dev, FALSE);
2112 /* remove all multicast addresses */
2113 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2115 hw->adapter_stopped = 1;
2120 i40evf_dev_link_update(struct rte_eth_dev *dev,
2121 __rte_unused int wait_to_complete)
2123 struct rte_eth_link new_link;
2124 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2126 * DPDK pf host provide interfacet to acquire link status
2127 * while Linux driver does not
2130 memset(&new_link, 0, sizeof(new_link));
2131 /* Linux driver PF host */
2132 switch (vf->link_speed) {
2133 case I40E_LINK_SPEED_100MB:
2134 new_link.link_speed = ETH_SPEED_NUM_100M;
2136 case I40E_LINK_SPEED_1GB:
2137 new_link.link_speed = ETH_SPEED_NUM_1G;
2139 case I40E_LINK_SPEED_10GB:
2140 new_link.link_speed = ETH_SPEED_NUM_10G;
2142 case I40E_LINK_SPEED_20GB:
2143 new_link.link_speed = ETH_SPEED_NUM_20G;
2145 case I40E_LINK_SPEED_25GB:
2146 new_link.link_speed = ETH_SPEED_NUM_25G;
2148 case I40E_LINK_SPEED_40GB:
2149 new_link.link_speed = ETH_SPEED_NUM_40G;
2152 new_link.link_speed = ETH_SPEED_NUM_NONE;
2155 /* full duplex only */
2156 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2157 new_link.link_status = vf->link_up &&
2158 new_link.link_speed != ETH_SPEED_NUM_NONE
2161 new_link.link_autoneg =
2162 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2164 return rte_eth_linkstatus_set(dev, &new_link);
2168 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2170 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2173 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2175 vf->promisc_unicast_enabled = TRUE;
2183 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2185 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2188 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2190 vf->promisc_unicast_enabled = FALSE;
2198 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2200 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2203 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2205 vf->promisc_multicast_enabled = TRUE;
2213 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2215 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2218 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2220 vf->promisc_multicast_enabled = FALSE;
2228 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2230 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2232 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2233 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2234 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2235 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2236 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2237 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2238 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2239 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2240 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2241 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2242 dev_info->rx_queue_offload_capa = 0;
2243 dev_info->rx_offload_capa =
2244 DEV_RX_OFFLOAD_VLAN_STRIP |
2245 DEV_RX_OFFLOAD_QINQ_STRIP |
2246 DEV_RX_OFFLOAD_IPV4_CKSUM |
2247 DEV_RX_OFFLOAD_UDP_CKSUM |
2248 DEV_RX_OFFLOAD_TCP_CKSUM |
2249 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2250 DEV_RX_OFFLOAD_SCATTER |
2251 DEV_RX_OFFLOAD_JUMBO_FRAME |
2252 DEV_RX_OFFLOAD_VLAN_FILTER;
2254 dev_info->tx_queue_offload_capa = 0;
2255 dev_info->tx_offload_capa =
2256 DEV_TX_OFFLOAD_VLAN_INSERT |
2257 DEV_TX_OFFLOAD_QINQ_INSERT |
2258 DEV_TX_OFFLOAD_IPV4_CKSUM |
2259 DEV_TX_OFFLOAD_UDP_CKSUM |
2260 DEV_TX_OFFLOAD_TCP_CKSUM |
2261 DEV_TX_OFFLOAD_SCTP_CKSUM |
2262 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2263 DEV_TX_OFFLOAD_TCP_TSO |
2264 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2265 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2266 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2267 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2268 DEV_TX_OFFLOAD_MULTI_SEGS;
2270 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2272 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2273 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2274 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2276 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2281 dev_info->default_txconf = (struct rte_eth_txconf) {
2283 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2284 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2285 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2287 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2288 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2292 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2293 .nb_max = I40E_MAX_RING_DESC,
2294 .nb_min = I40E_MIN_RING_DESC,
2295 .nb_align = I40E_ALIGN_RING_DESC,
2298 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2299 .nb_max = I40E_MAX_RING_DESC,
2300 .nb_min = I40E_MIN_RING_DESC,
2301 .nb_align = I40E_ALIGN_RING_DESC,
2308 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2311 struct i40e_eth_stats *pstats = NULL;
2312 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2313 struct i40e_vsi *vsi = &vf->vsi;
2315 ret = i40evf_query_stats(dev, &pstats);
2317 i40evf_update_stats(vsi, pstats);
2319 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2320 pstats->rx_broadcast;
2321 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2323 stats->imissed = pstats->rx_discards;
2324 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2325 stats->ibytes = pstats->rx_bytes;
2326 stats->obytes = pstats->tx_bytes;
2328 PMD_DRV_LOG(ERR, "Get statistics failed");
2334 i40evf_dev_close(struct rte_eth_dev *dev)
2336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2339 i40evf_dev_stop(dev);
2340 i40e_dev_free_queues(dev);
2342 * disable promiscuous mode before reset vf
2343 * it is a workaround solution when work with kernel driver
2344 * and it is not the normal way
2346 i40evf_dev_promiscuous_disable(dev);
2347 i40evf_dev_allmulticast_disable(dev);
2348 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2350 i40evf_reset_vf(dev);
2351 i40e_shutdown_adminq(hw);
2352 i40evf_disable_irq0(hw);
2354 dev->dev_ops = NULL;
2355 dev->rx_pkt_burst = NULL;
2356 dev->tx_pkt_burst = NULL;
2358 rte_free(vf->vf_res);
2360 rte_free(vf->aq_resp);
2363 hw->adapter_closed = 1;
2367 * Reset VF device only to re-initialize resources in PMD layer
2370 i40evf_dev_reset(struct rte_eth_dev *dev)
2374 ret = i40evf_dev_uninit(dev);
2378 ret = i40evf_dev_init(dev);
2384 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2386 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2387 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2393 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2394 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2397 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2401 uint32_t *lut_dw = (uint32_t *)lut;
2402 uint16_t i, lut_size_dw = lut_size / 4;
2404 for (i = 0; i < lut_size_dw; i++)
2405 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2412 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2421 vf = I40E_VSI_TO_VF(vsi);
2422 hw = I40E_VSI_TO_HW(vsi);
2424 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2425 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2428 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2432 uint32_t *lut_dw = (uint32_t *)lut;
2433 uint16_t i, lut_size_dw = lut_size / 4;
2435 for (i = 0; i < lut_size_dw; i++)
2436 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2437 I40EVF_WRITE_FLUSH(hw);
2444 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2445 struct rte_eth_rss_reta_entry64 *reta_conf,
2448 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2450 uint16_t i, idx, shift;
2453 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2454 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2455 "(%d) doesn't match the number of hardware can "
2456 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2460 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2462 PMD_DRV_LOG(ERR, "No memory can be allocated");
2465 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2468 for (i = 0; i < reta_size; i++) {
2469 idx = i / RTE_RETA_GROUP_SIZE;
2470 shift = i % RTE_RETA_GROUP_SIZE;
2471 if (reta_conf[idx].mask & (1ULL << shift))
2472 lut[i] = reta_conf[idx].reta[shift];
2474 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2483 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2484 struct rte_eth_rss_reta_entry64 *reta_conf,
2487 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2488 uint16_t i, idx, shift;
2492 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2493 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2494 "(%d) doesn't match the number of hardware can "
2495 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2499 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2501 PMD_DRV_LOG(ERR, "No memory can be allocated");
2505 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2508 for (i = 0; i < reta_size; i++) {
2509 idx = i / RTE_RETA_GROUP_SIZE;
2510 shift = i % RTE_RETA_GROUP_SIZE;
2511 if (reta_conf[idx].mask & (1ULL << shift))
2512 reta_conf[idx].reta[shift] = lut[i];
2522 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2524 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2525 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2528 if (!key || key_len == 0) {
2529 PMD_DRV_LOG(DEBUG, "No key to be configured");
2531 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2533 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2537 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2538 struct i40e_aqc_get_set_rss_key_data *key_dw =
2539 (struct i40e_aqc_get_set_rss_key_data *)key;
2541 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2543 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2546 uint32_t *hash_key = (uint32_t *)key;
2549 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2550 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2551 I40EVF_WRITE_FLUSH(hw);
2558 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2560 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2561 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2564 if (!key || !key_len)
2567 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2568 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2569 (struct i40e_aqc_get_set_rss_key_data *)key);
2571 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2575 uint32_t *key_dw = (uint32_t *)key;
2578 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2579 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2581 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2587 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2589 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2593 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2594 rss_conf->rss_key_len);
2598 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2599 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2600 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2601 I40EVF_WRITE_FLUSH(hw);
2607 i40evf_disable_rss(struct i40e_vf *vf)
2609 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2611 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2612 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2613 I40EVF_WRITE_FLUSH(hw);
2617 i40evf_config_rss(struct i40e_vf *vf)
2619 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2620 struct rte_eth_rss_conf rss_conf;
2621 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2622 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2627 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2628 i40evf_disable_rss(vf);
2629 PMD_DRV_LOG(DEBUG, "RSS not configured");
2633 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2634 /* Fill out the look up table */
2635 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2636 for (i = 0, j = 0; i < nb_q; i++, j++) {
2639 lut = (lut << 8) | j;
2641 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2644 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2646 PMD_DRV_LOG(ERR, "No memory can be allocated");
2650 for (i = 0; i < rss_lut_size; i++)
2651 lut_info[i] = i % vf->num_queue_pairs;
2653 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2660 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2661 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2662 i40evf_disable_rss(vf);
2663 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2667 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2668 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2669 /* Calculate the default hash key */
2670 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2671 rss_key_default[i] = (uint32_t)rte_rand();
2672 rss_conf.rss_key = (uint8_t *)rss_key_default;
2673 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2677 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2681 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2682 struct rte_eth_rss_conf *rss_conf)
2684 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2689 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2690 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2692 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2693 if (rss_hf != 0) /* Enable RSS */
2699 if (rss_hf == 0) /* Disable RSS */
2702 return i40evf_hw_rss_hash_set(vf, rss_conf);
2706 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2707 struct rte_eth_rss_conf *rss_conf)
2709 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2710 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2714 &rss_conf->rss_key_len);
2716 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2717 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2718 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2724 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2726 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2727 struct rte_eth_dev_data *dev_data = vf->dev_data;
2728 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2731 /* check if mtu is within the allowed range */
2732 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2735 /* mtu setting is forbidden if port is start */
2736 if (dev_data->dev_started) {
2737 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2742 if (frame_size > RTE_ETHER_MAX_LEN)
2743 dev_data->dev_conf.rxmode.offloads |=
2744 DEV_RX_OFFLOAD_JUMBO_FRAME;
2746 dev_data->dev_conf.rxmode.offloads &=
2747 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2748 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2754 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2755 struct rte_ether_addr *mac_addr)
2757 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2760 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2761 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2765 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2768 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2770 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2773 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2778 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2779 struct rte_ether_addr *mc_addrs,
2780 uint32_t mc_addrs_num, bool add)
2782 struct virtchnl_ether_addr_list *list;
2783 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2784 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2785 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2788 struct vf_cmd_info args;
2790 if (mc_addrs == NULL || mc_addrs_num == 0)
2793 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2796 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2797 list->vsi_id = vf->vsi_res->vsi_id;
2798 list->num_elements = mc_addrs_num;
2800 for (i = 0; i < mc_addrs_num; i++) {
2801 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2802 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2803 mc_addrs[i].addr_bytes[0],
2804 mc_addrs[i].addr_bytes[1],
2805 mc_addrs[i].addr_bytes[2],
2806 mc_addrs[i].addr_bytes[3],
2807 mc_addrs[i].addr_bytes[4],
2808 mc_addrs[i].addr_bytes[5]);
2812 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2813 sizeof(list->list[i].addr));
2816 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2817 args.in_args = cmd_buffer;
2818 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2819 i * sizeof(struct virtchnl_ether_addr);
2820 args.out_buffer = vf->aq_resp;
2821 args.out_size = I40E_AQ_BUF_SZ;
2822 err = i40evf_execute_vf_cmd(dev, &args);
2824 PMD_DRV_LOG(ERR, "fail to execute command %s",
2825 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2833 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2834 struct rte_ether_addr *mc_addrs,
2835 uint32_t mc_addrs_num)
2837 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2840 /* flush previous addresses */
2841 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2846 vf->mc_addrs_num = 0;
2849 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2854 vf->mc_addrs_num = mc_addrs_num;
2855 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2861 is_i40evf_supported(struct rte_eth_dev *dev)
2863 return is_device_supported(dev, &rte_i40evf_pmd);