drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_ip.h>
  48 #include <rte_udp.h>
  49 #include <rte_tcp.h>
  50 #include <rte_sctp.h>
  51
  52 #include "i40e_logs.h"
  53 #include "base/i40e_type.h"
  54 #include "i40e_ethdev.h"
  55 #include "i40e_rxtx.h"
  56
  57 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  58 #ifndef IPV6_ADDR_LEN
  59 #define IPV6_ADDR_LEN              16
  60 #endif
  61
  62 #define I40E_FDIR_PKT_LEN                   512
  63 #define I40E_FDIR_IP_DEFAULT_LEN            420
  64 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  65 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  66 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  67 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000
  68 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  69 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  70 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  71
  72 /* Wait count and interval for fdir filter programming */
  73 #define I40E_FDIR_WAIT_COUNT       10
  74 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  75
  76 /* Wait count and interval for fdir filter flush */
  77 #define I40E_FDIR_FLUSH_RETRY       50
  78 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  79
  80 #define I40E_COUNTER_PF           2
  81 /* Statistic counter index for one pf */
  82 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  83 #define I40E_MAX_FLX_SOURCE_OFF           480
  84 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  85
  86 #define NONUSE_FLX_PIT_DEST_OFF 63
  87 #define NONUSE_FLX_PIT_FSIZE    1
  88 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  89         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  90                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  91         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  92                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  93         ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
  94                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
  95                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
  96
  97 #define I40E_FDIR_FLOWS ( \
  98         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 101         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
 108
 109 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 110
 111 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
 112 static int i40e_check_fdir_flex_conf(
 113         const struct rte_eth_fdir_flex_conf *conf);
 114 static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 115                          const struct rte_eth_flex_payload_cfg *cfg);
 116 static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 117                 enum i40e_filter_pctype pctype,
 118                 const struct rte_eth_fdir_flex_mask *mask_cfg);
 119 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
 120                                      const struct rte_eth_fdir_input *fdir_input,
 121                                      unsigned char *raw_pkt);
 122 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 123                             const struct rte_eth_fdir_filter *filter,
 124                             bool add);
 125 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 126                         enum i40e_filter_pctype pctype,
 127                         const struct rte_eth_fdir_filter *filter,
 128                         bool add);
 129 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 130 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
 131                            struct rte_eth_fdir_info *fdir);
 132 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
 133                            struct rte_eth_fdir_stats *stat);
 134
 135 static int
 136 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 137 {
 138         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 139         struct i40e_hmc_obj_rxq rx_ctx;
 140         int err = I40E_SUCCESS;
 141
 142         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 143         /* Init the RX queue in hardware */
 144         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 145         rx_ctx.hbuff = 0;
 146         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 147         rx_ctx.qlen = rxq->nb_rx_desc;
 148 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 149         rx_ctx.dsize = 1;
 150 #endif
 151         rx_ctx.dtype = i40e_header_split_none;
 152         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 153         rx_ctx.rxmax = ETHER_MAX_LEN;
 154         rx_ctx.tphrdesc_ena = 1;
 155         rx_ctx.tphwdesc_ena = 1;
 156         rx_ctx.tphdata_ena = 1;
 157         rx_ctx.tphhead_ena = 1;
 158         rx_ctx.lrxqthresh = 2;
 159         rx_ctx.crcstrip = 0;
 160         rx_ctx.l2tsel = 1;
 161         rx_ctx.showiv = 1;
 162         rx_ctx.prefena = 1;
 163
 164         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 165         if (err != I40E_SUCCESS) {
 166                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 167                 return err;
 168         }
 169         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 170         if (err != I40E_SUCCESS) {
 171                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 172                 return err;
 173         }
 174         rxq->qrx_tail = hw->hw_addr +
 175                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 176
 177         rte_wmb();
 178         /* Init the RX tail regieter. */
 179         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 180         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 181
 182         return err;
 183 }
 184
 185 /*
 186  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 187  * @pf: board private structure
 188  */
 189 int
 190 i40e_fdir_setup(struct i40e_pf *pf)
 191 {
 192         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 193         struct i40e_vsi *vsi;
 194         int err = I40E_SUCCESS;
 195         char z_name[RTE_MEMZONE_NAMESIZE];
 196         const struct rte_memzone *mz = NULL;
 197         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 198
 199         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 200                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 201                 return I40E_NOT_SUPPORTED;
 202         }
 203
 204         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 205                         " num_filters_best_effort = %u.",
 206                         hw->func_caps.fd_filters_guaranteed,
 207                         hw->func_caps.fd_filters_best_effort);
 208
 209         vsi = pf->fdir.fdir_vsi;
 210         if (vsi) {
 211                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 212                 return I40E_SUCCESS;
 213         }
 214         /* make new FDIR VSI */
 215         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 216         if (!vsi) {
 217                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 218                 return I40E_ERR_NO_AVAILABLE_VSI;
 219         }
 220         pf->fdir.fdir_vsi = vsi;
 221
 222         /*Fdir tx queue setup*/
 223         err = i40e_fdir_setup_tx_resources(pf);
 224         if (err) {
 225                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 226                 goto fail_setup_tx;
 227         }
 228
 229         /*Fdir rx queue setup*/
 230         err = i40e_fdir_setup_rx_resources(pf);
 231         if (err) {
 232                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 233                 goto fail_setup_rx;
 234         }
 235
 236         err = i40e_tx_queue_init(pf->fdir.txq);
 237         if (err) {
 238                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 239                 goto fail_mem;
 240         }
 241
 242         /* need switch on before dev start*/
 243         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 244         if (err) {
 245                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 246                 goto fail_mem;
 247         }
 248
 249         /* Init the rx queue in hardware */
 250         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 251         if (err) {
 252                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 253                 goto fail_mem;
 254         }
 255
 256         /* switch on rx queue */
 257         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 258         if (err) {
 259                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 260                 goto fail_mem;
 261         }
 262
 263         /* reserve memory for the fdir programming packet */
 264         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 265                         eth_dev->driver->pci_drv.name,
 266                         I40E_FDIR_MZ_NAME,
 267                         eth_dev->data->port_id);
 268         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 269         if (!mz) {
 270                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 271                                  "flow director program packet.");
 272                 err = I40E_ERR_NO_MEMORY;
 273                 goto fail_mem;
 274         }
 275         pf->fdir.prg_pkt = mz->addr;
 276 #ifdef RTE_LIBRTE_XEN_DOM0
 277         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 278 #else
 279         pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
 280 #endif
 281         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 282         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 283                     vsi->base_queue);
 284         return I40E_SUCCESS;
 285
 286 fail_mem:
 287         i40e_dev_rx_queue_release(pf->fdir.rxq);
 288         pf->fdir.rxq = NULL;
 289 fail_setup_rx:
 290         i40e_dev_tx_queue_release(pf->fdir.txq);
 291         pf->fdir.txq = NULL;
 292 fail_setup_tx:
 293         i40e_vsi_release(vsi);
 294         pf->fdir.fdir_vsi = NULL;
 295         return err;
 296 }
 297
 298 /*
 299  * i40e_fdir_teardown - release the Flow Director resources
 300  * @pf: board private structure
 301  */
 302 void
 303 i40e_fdir_teardown(struct i40e_pf *pf)
 304 {
 305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 306         struct i40e_vsi *vsi;
 307
 308         vsi = pf->fdir.fdir_vsi;
 309         if (!vsi)
 310                 return;
 311         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 312         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 313         i40e_dev_rx_queue_release(pf->fdir.rxq);
 314         pf->fdir.rxq = NULL;
 315         i40e_dev_tx_queue_release(pf->fdir.txq);
 316         pf->fdir.txq = NULL;
 317         i40e_vsi_release(vsi);
 318         pf->fdir.fdir_vsi = NULL;
 319 }
 320
 321 /* check whether the flow director table in empty */
 322 static inline int
 323 i40e_fdir_empty(struct i40e_hw *hw)
 324 {
 325         uint32_t guarant_cnt, best_cnt;
 326
 327         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 328                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 329                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 330         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 331                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 332                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 333         if (best_cnt + guarant_cnt > 0)
 334                 return -1;
 335
 336         return 0;
 337 }
 338
 339 /*
 340  * Initialize the configuration about bytes stream extracted as flexible payload
 341  * and mask setting
 342  */
 343 static inline void
 344 i40e_init_flx_pld(struct i40e_pf *pf)
 345 {
 346         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 347         uint8_t pctype;
 348         int i, index;
 349
 350         /*
 351          * Define the bytes stream extracted as flexible payload in
 352          * field vector. By default, select 8 words from the beginning
 353          * of payload as flexible payload.
 354          */
 355         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 356                 index = i * I40E_MAX_FLXPLD_FIED;
 357                 pf->fdir.flex_set[index].src_offset = 0;
 358                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 359                 pf->fdir.flex_set[index].dst_offset = 0;
 360                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 361                 I40E_WRITE_REG(hw,
 362                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 363                 I40E_WRITE_REG(hw,
 364                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 365         }
 366
 367         /* initialize the masks */
 368         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 369              pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
 370                 pf->fdir.flex_mask[pctype].word_mask = 0;
 371                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 372                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 373                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 374                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 375                         I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 376                 }
 377         }
 378 }
 379
 380 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 381
 382 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 383         if ((flex_pit2).src_offset < \
 384                 (flex_pit1).src_offset + (flex_pit1).size) { \
 385                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 386                         " less than than previous offset" \
 387                         " + previous FSIZE."); \
 388                 return -EINVAL; \
 389         } \
 390 } while (0)
 391
 392 /*
 393  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 394  * and the flex_pit will be sorted by it's src_offset value
 395  */
 396 static inline uint16_t
 397 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 398                         struct i40e_fdir_flex_pit *flex_pit)
 399 {
 400         uint16_t src_tmp, size, num = 0;
 401         uint16_t i, k, j = 0;
 402
 403         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 404                 size = 1;
 405                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 406                         if (src_offset[j + 1] == src_offset[j] + 1)
 407                                 size++;
 408                         else
 409                                 break;
 410                 }
 411                 src_tmp = src_offset[j] + 1 - size;
 412                 /* the flex_pit need to be sort by src_offset */
 413                 for (i = 0; i < num; i++) {
 414                         if (src_tmp < flex_pit[i].src_offset)
 415                                 break;
 416                 }
 417                 /* if insert required, move backward */
 418                 for (k = num; k > i; k--)
 419                         flex_pit[k] = flex_pit[k - 1];
 420                 /* insert */
 421                 flex_pit[i].dst_offset = j + 1 - size;
 422                 flex_pit[i].src_offset = src_tmp;
 423                 flex_pit[i].size = size;
 424                 j++;
 425                 num++;
 426         }
 427         return num;
 428 }
 429
 430 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 431 static inline int
 432 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 433 {
 434         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 435         uint16_t num, i;
 436
 437         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 438                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 439                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 440                         return -EINVAL;
 441                 }
 442         }
 443
 444         memset(flex_pit, 0, sizeof(flex_pit));
 445         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 446         if (num > I40E_MAX_FLXPLD_FIED) {
 447                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 448                 return -EINVAL;
 449         }
 450         for (i = 0; i < num; i++) {
 451                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 452                         flex_pit[i].src_offset & 0x01) {
 453                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 454                                 " in word");
 455                         return -EINVAL;
 456                 }
 457                 if (i != num - 1)
 458                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 459         }
 460         return 0;
 461 }
 462
 463 /*
 464  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 465  * arguments are valid
 466  */
 467 static int
 468 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 469 {
 470         const struct rte_eth_flex_payload_cfg *flex_cfg;
 471         const struct rte_eth_fdir_flex_mask *flex_mask;
 472         uint16_t mask_tmp;
 473         uint8_t nb_bitmask;
 474         uint16_t i, j;
 475         int ret = 0;
 476
 477         if (conf == NULL) {
 478                 PMD_DRV_LOG(INFO, "NULL pointer.");
 479                 return -EINVAL;
 480         }
 481         /* check flexible payload setting configuration */
 482         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 483                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 484                 return -EINVAL;
 485         }
 486         for (i = 0; i < conf->nb_payloads; i++) {
 487                 flex_cfg = &conf->flex_set[i];
 488                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 489                         PMD_DRV_LOG(ERR, "invalid payload type.");
 490                         return -EINVAL;
 491                 }
 492                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 493                 if (ret < 0) {
 494                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 495                         return -EINVAL;
 496                 }
 497         }
 498
 499         /* check flex mask setting configuration */
 500         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 501                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 502                 return -EINVAL;
 503         }
 504         for (i = 0; i < conf->nb_flexmasks; i++) {
 505                 flex_mask = &conf->flex_mask[i];
 506                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 507                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 508                         return -EINVAL;
 509                 }
 510                 nb_bitmask = 0;
 511                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 512                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 513                                              flex_mask->mask[j + 1]);
 514                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 515                                 nb_bitmask++;
 516                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 517                                         PMD_DRV_LOG(ERR, " exceed maximal"
 518                                                 " number of bitmasks.");
 519                                         return -EINVAL;
 520                                 }
 521                         }
 522                 }
 523         }
 524         return 0;
 525 }
 526
 527 /*
 528  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 529  * @pf: board private structure
 530  * @cfg: the rule how bytes stream is extracted as flexible payload
 531  */
 532 static void
 533 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 534                          const struct rte_eth_flex_payload_cfg *cfg)
 535 {
 536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 537         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 538         uint32_t flx_pit;
 539         uint16_t num, min_next_off;  /* in words */
 540         uint8_t field_idx = 0;
 541         uint8_t layer_idx = 0;
 542         uint16_t i;
 543
 544         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 545                 layer_idx = I40E_FLXPLD_L2_IDX;
 546         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 547                 layer_idx = I40E_FLXPLD_L3_IDX;
 548         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 549                 layer_idx = I40E_FLXPLD_L4_IDX;
 550
 551         memset(flex_pit, 0, sizeof(flex_pit));
 552         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 553
 554         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 555                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 556                 /* record the info in fdir structure */
 557                 pf->fdir.flex_set[field_idx].src_offset =
 558                         flex_pit[i].src_offset / sizeof(uint16_t);
 559                 pf->fdir.flex_set[field_idx].size =
 560                         flex_pit[i].size / sizeof(uint16_t);
 561                 pf->fdir.flex_set[field_idx].dst_offset =
 562                         flex_pit[i].dst_offset / sizeof(uint16_t);
 563                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 564                                 pf->fdir.flex_set[field_idx].size,
 565                                 pf->fdir.flex_set[field_idx].dst_offset);
 566
 567                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 568         }
 569         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 570                                 pf->fdir.flex_set[field_idx].size;
 571
 572         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 573                 /* set the non-used register obeying register's constrain */
 574                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 575                            NONUSE_FLX_PIT_DEST_OFF);
 576                 I40E_WRITE_REG(hw,
 577                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 578                         flx_pit);
 579                 min_next_off++;
 580         }
 581 }
 582
 583 /*
 584  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 585  * @pf: board private structure
 586  * @pctype: packet classify type
 587  * @flex_masks: mask for flexible payload
 588  */
 589 static void
 590 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 591                 enum i40e_filter_pctype pctype,
 592                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 593 {
 594         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 595         struct i40e_fdir_flex_mask *flex_mask;
 596         uint32_t flxinset, fd_mask;
 597         uint16_t mask_tmp;
 598         uint8_t i, nb_bitmask = 0;
 599
 600         flex_mask = &pf->fdir.flex_mask[pctype];
 601         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 602         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 603                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 604                 if (mask_tmp != 0x0) {
 605                         flex_mask->word_mask |=
 606                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 607                         if (mask_tmp != UINT16_MAX) {
 608                                 /* set bit mask */
 609                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 610                                 flex_mask->bitmask[nb_bitmask].offset =
 611                                         i / sizeof(uint16_t);
 612                                 nb_bitmask++;
 613                         }
 614                 }
 615         }
 616         /* write mask to hw */
 617         flxinset = (flex_mask->word_mask <<
 618                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 619                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 620         I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 621
 622         for (i = 0; i < nb_bitmask; i++) {
 623                 fd_mask = (flex_mask->bitmask[i].mask <<
 624                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 625                         I40E_PRTQF_FD_MSK_MASK_MASK;
 626                 fd_mask |= ((flex_mask->bitmask[i].offset +
 627                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 628                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 629                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 630                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 631         }
 632 }
 633
 634 /*
 635  * Configure flow director related setting
 636  */
 637 int
 638 i40e_fdir_configure(struct rte_eth_dev *dev)
 639 {
 640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 642         struct rte_eth_fdir_flex_conf *conf;
 643         enum i40e_filter_pctype pctype;
 644         uint32_t val;
 645         uint8_t i;
 646         int ret = 0;
 647
 648         /*
 649         * configuration need to be done before
 650         * flow director filters are added
 651         * If filters exist, flush them.
 652         */
 653         if (i40e_fdir_empty(hw) < 0) {
 654                 ret = i40e_fdir_flush(dev);
 655                 if (ret) {
 656                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 657                         return ret;
 658                 }
 659         }
 660
 661         /* enable FDIR filter */
 662         val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
 663         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 664         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 665
 666         i40e_init_flx_pld(pf); /* set flex config to default value */
 667
 668         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 669         ret = i40e_check_fdir_flex_conf(conf);
 670         if (ret < 0) {
 671                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 672                 return -EINVAL;
 673         }
 674         /* configure flex payload */
 675         for (i = 0; i < conf->nb_payloads; i++)
 676                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 677         /* configure flex mask*/
 678         for (i = 0; i < conf->nb_flexmasks; i++) {
 679                 pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);
 680                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 681         }
 682
 683         return ret;
 684 }
 685
 686 static inline void
 687 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 688                                unsigned char *raw_pkt)
 689 {
 690         struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
 691         struct ipv4_hdr *ip;
 692         struct ipv6_hdr *ip6;
 693         static const uint8_t next_proto[] = {
 694                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 695                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 696                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 697                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 698                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 699                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 700                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 701                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 702                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 703                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 704         };
 705
 706         switch (fdir_input->flow_type) {
 707         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 708         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 709         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 710         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 711         case RTE_ETH_FLOW_FRAG_IPV4:
 712                 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 713
 714                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 715                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 716                 /* set len to by default */
 717                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 718                 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
 719                 /*
 720                  * The source and destination fields in the transmitted packet
 721                  * need to be presented in a reversed order with respect
 722                  * to the expected received packets.
 723                  */
 724                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 725                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 726                 ip->next_proto_id = next_proto[fdir_input->flow_type];
 727                 break;
 728         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 729         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 730         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 731         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 732         case RTE_ETH_FLOW_FRAG_IPV6:
 733                 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 734
 735                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 736                 ip6->vtc_flow =
 737                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
 738                 ip6->payload_len =
 739                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 740                 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 741
 742                 /*
 743                  * The source and destination fields in the transmitted packet
 744                  * need to be presented in a reversed order with respect
 745                  * to the expected received packets.
 746                  */
 747                 rte_memcpy(&(ip6->src_addr),
 748                            &(fdir_input->flow.ipv6_flow.dst_ip),
 749                            IPV6_ADDR_LEN);
 750                 rte_memcpy(&(ip6->dst_addr),
 751                            &(fdir_input->flow.ipv6_flow.src_ip),
 752                            IPV6_ADDR_LEN);
 753                 ip6->proto = next_proto[fdir_input->flow_type];
 754                 break;
 755         default:
 756                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 757                             fdir_input->flow_type);
 758                 break;
 759         }
 760 }
 761
 762
 763 /*
 764  * i40e_fdir_construct_pkt - construct packet based on fields in input
 765  * @pf: board private structure
 766  * @fdir_input: input set of the flow director entry
 767  * @raw_pkt: a packet to be constructed
 768  */
 769 static int
 770 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 771                              const struct rte_eth_fdir_input *fdir_input,
 772                              unsigned char *raw_pkt)
 773 {
 774         unsigned char *payload, *ptr;
 775         struct udp_hdr *udp;
 776         struct tcp_hdr *tcp;
 777         struct sctp_hdr *sctp;
 778         uint8_t size, dst = 0;
 779         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 780
 781         /* fill the ethernet and IP head */
 782         i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
 783
 784         /* fill the L4 head */
 785         switch (fdir_input->flow_type) {
 786         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 787                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 788                                 sizeof(struct ipv4_hdr));
 789                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 790                 /*
 791                  * The source and destination fields in the transmitted packet
 792                  * need to be presented in a reversed order with respect
 793                  * to the expected received packets.
 794                  */
 795                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 796                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 797                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 798                 break;
 799
 800         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 801                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 802                                          sizeof(struct ipv4_hdr));
 803                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 804                 /*
 805                  * The source and destination fields in the transmitted packet
 806                  * need to be presented in a reversed order with respect
 807                  * to the expected received packets.
 808                  */
 809                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 810                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 811                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 812                 break;
 813
 814         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 815                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 816                                            sizeof(struct ipv4_hdr));
 817                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 818                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 819                 break;
 820
 821         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 822         case RTE_ETH_FLOW_FRAG_IPV4:
 823                 payload = raw_pkt + sizeof(struct ether_hdr) +
 824                           sizeof(struct ipv4_hdr);
 825                 set_idx = I40E_FLXPLD_L3_IDX;
 826                 break;
 827
 828         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 829                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 830                                          sizeof(struct ipv6_hdr));
 831                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 832                 /*
 833                  * The source and destination fields in the transmitted packet
 834                  * need to be presented in a reversed order with respect
 835                  * to the expected received packets.
 836                  */
 837                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 838                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 839                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 840                 break;
 841
 842         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 843                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 844                                          sizeof(struct ipv6_hdr));
 845                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 846                 /*
 847                  * The source and destination fields in the transmitted packet
 848                  * need to be presented in a reversed order with respect
 849                  * to the expected received packets.
 850                  */
 851                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 852                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 853                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 854                 break;
 855
 856         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 857                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 858                                            sizeof(struct ipv6_hdr));
 859                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 860                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 861                 break;
 862
 863         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 864         case RTE_ETH_FLOW_FRAG_IPV6:
 865                 payload = raw_pkt + sizeof(struct ether_hdr) +
 866                           sizeof(struct ipv6_hdr);
 867                 set_idx = I40E_FLXPLD_L3_IDX;
 868                 break;
 869         default:
 870                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 871                 return -EINVAL;
 872         }
 873
 874         /* fill the flexbytes to payload */
 875         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 876                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 877                 size = pf->fdir.flex_set[pit_idx].size;
 878                 if (size == 0)
 879                         continue;
 880                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 881                 ptr = payload +
 882                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 883                 (void)rte_memcpy(ptr,
 884                                  &fdir_input->flow_ext.flexbytes[dst],
 885                                  size * sizeof(uint16_t));
 886         }
 887
 888         return 0;
 889 }
 890
 891 /* Construct the tx flags */
 892 static inline uint64_t
 893 i40e_build_ctob(uint32_t td_cmd,
 894                 uint32_t td_offset,
 895                 unsigned int size,
 896                 uint32_t td_tag)
 897 {
 898         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 899                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 900                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 901                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 902                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 903 }
 904
 905 /*
 906  * check the programming status descriptor in rx queue.
 907  * done after Programming Flow Director is programmed on
 908  * tx queue
 909  */
 910 static inline int
 911 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 912 {
 913         volatile union i40e_rx_desc *rxdp;
 914         uint64_t qword1;
 915         uint32_t rx_status;
 916         uint32_t len, id;
 917         uint32_t error;
 918         int ret = 0;
 919
 920         rxdp = &rxq->rx_ring[rxq->rx_tail];
 921         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 922         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 923                         >> I40E_RXD_QW1_STATUS_SHIFT;
 924
 925         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 926                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 927                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 928                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 929
 930                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 931                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 932                         error = (qword1 &
 933                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 934                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 935                         if (error == (0x1 <<
 936                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 937                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 938                                             " (FD_ID %u): programming status"
 939                                             " reported.",
 940                                             rxdp->wb.qword0.hi_dword.fd_id);
 941                                 ret = -1;
 942                         } else if (error == (0x1 <<
 943                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 944                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 945                                             " (FD_ID %u): programming status"
 946                                             " reported.",
 947                                             rxdp->wb.qword0.hi_dword.fd_id);
 948                                 ret = -1;
 949                         } else
 950                                 PMD_DRV_LOG(ERR, "invalid programming status"
 951                                             " reported, error = %u.", error);
 952                 } else
 953                         PMD_DRV_LOG(ERR, "unknown programming status"
 954                                     " reported, len = %d, id = %u.", len, id);
 955                 rxdp->wb.qword1.status_error_len = 0;
 956                 rxq->rx_tail++;
 957                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 958                         rxq->rx_tail = 0;
 959         }
 960         return ret;
 961 }
 962
 963 /*
 964  * i40e_add_del_fdir_filter - add or remove a flow director filter.
 965  * @pf: board private structure
 966  * @filter: fdir filter entry
 967  * @add: 0 - delete, 1 - add
 968  */
 969 static int
 970 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 971                             const struct rte_eth_fdir_filter *filter,
 972                             bool add)
 973 {
 974         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 975         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
 976         enum i40e_filter_pctype pctype;
 977         int ret = 0;
 978
 979         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
 980                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
 981                         " check the mode in fdir_conf.");
 982                 return -ENOTSUP;
 983         }
 984
 985         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
 986                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
 987                 return -EINVAL;
 988         }
 989         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
 990                 PMD_DRV_LOG(ERR, "Invalid queue ID");
 991                 return -EINVAL;
 992         }
 993
 994         memset(pkt, 0, I40E_FDIR_PKT_LEN);
 995
 996         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
 997         if (ret < 0) {
 998                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
 999                 return ret;
1000         }
1001         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1002         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1003         if (ret < 0) {
1004                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1005                             pctype);
1006                 return ret;
1007         }
1008         return ret;
1009 }
1010
1011 /*
1012  * i40e_fdir_filter_programming - Program a flow director filter rule.
1013  * Is done by Flow Director Programming Descriptor followed by packet
1014  * structure that contains the filter fields need to match.
1015  * @pf: board private structure
1016  * @pctype: pctype
1017  * @filter: fdir filter entry
1018  * @add: 0 - delelet, 1 - add
1019  */
1020 static int
1021 i40e_fdir_filter_programming(struct i40e_pf *pf,
1022                         enum i40e_filter_pctype pctype,
1023                         const struct rte_eth_fdir_filter *filter,
1024                         bool add)
1025 {
1026         struct i40e_tx_queue *txq = pf->fdir.txq;
1027         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1028         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1029         volatile struct i40e_tx_desc *txdp;
1030         volatile struct i40e_filter_program_desc *fdirdp;
1031         uint32_t td_cmd;
1032         uint16_t i;
1033         uint8_t dest;
1034
1035         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1036         fdirdp = (volatile struct i40e_filter_program_desc *)
1037                         (&(txq->tx_ring[txq->tx_tail]));
1038
1039         fdirdp->qindex_flex_ptype_vsi =
1040                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1041                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1042                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1043
1044         fdirdp->qindex_flex_ptype_vsi |=
1045                         rte_cpu_to_le_32((fdir_action->flex_off <<
1046                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1047                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1048
1049         fdirdp->qindex_flex_ptype_vsi |=
1050                         rte_cpu_to_le_32((pctype <<
1051                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1052                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1053
1054         /* Use LAN VSI Id by default */
1055         fdirdp->qindex_flex_ptype_vsi |=
1056                 rte_cpu_to_le_32((pf->main_vsi->vsi_id <<
1057                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1058                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1059
1060         fdirdp->dtype_cmd_cntindex =
1061                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1062
1063         if (add)
1064                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1065                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1066                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1067         else
1068                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1069                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1070                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1071
1072         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1073                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1074         else
1075                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1076         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1077                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1078                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1079
1080         fdirdp->dtype_cmd_cntindex |=
1081                 rte_cpu_to_le_32((fdir_action->report_status<<
1082                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1083                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1084
1085         fdirdp->dtype_cmd_cntindex |=
1086                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1087         fdirdp->dtype_cmd_cntindex |=
1088                         rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1089                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1090                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1091
1092         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1093
1094         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1095         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1096         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1097         td_cmd = I40E_TX_DESC_CMD_EOP |
1098                  I40E_TX_DESC_CMD_RS  |
1099                  I40E_TX_DESC_CMD_DUMMY;
1100
1101         txdp->cmd_type_offset_bsz =
1102                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1103
1104         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1105         if (txq->tx_tail >= txq->nb_tx_desc)
1106                 txq->tx_tail = 0;
1107         /* Update the tx tail register */
1108         rte_wmb();
1109         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1110
1111         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1112                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1113                 if (txdp->cmd_type_offset_bsz &
1114                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1115                         break;
1116         }
1117         if (i >= I40E_FDIR_WAIT_COUNT) {
1118                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1119                             " time out to get DD on tx queue.");
1120                 return -ETIMEDOUT;
1121         }
1122         /* totally delay 10 ms to check programming status*/
1123         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1124         if (i40e_check_fdir_programming_status(rxq) < 0) {
1125                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1126                             " programming status reported.");
1127                 return -ENOSYS;
1128         }
1129
1130         return 0;
1131 }
1132
1133 /*
1134  * i40e_fdir_flush - clear all filters of Flow Director table
1135  * @pf: board private structure
1136  */
1137 static int
1138 i40e_fdir_flush(struct rte_eth_dev *dev)
1139 {
1140         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1141         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1142         uint32_t reg;
1143         uint16_t guarant_cnt, best_cnt;
1144         uint16_t i;
1145
1146         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1147         I40E_WRITE_FLUSH(hw);
1148
1149         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1150                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1151                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1152                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1153                         break;
1154         }
1155         if (i >= I40E_FDIR_FLUSH_RETRY) {
1156                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1157                 return -ETIMEDOUT;
1158         }
1159         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1160                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1161                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1162         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1163                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1164                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1165         if (guarant_cnt != 0 || best_cnt != 0) {
1166                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1167                 return -ENOSYS;
1168         } else
1169                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1170         return 0;
1171 }
1172
1173 static inline void
1174 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1175                         struct rte_eth_flex_payload_cfg *flex_set,
1176                         uint16_t *num)
1177 {
1178         struct i40e_fdir_flex_pit *flex_pit;
1179         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1180         uint16_t src, dst, size, j, k;
1181         uint8_t i, layer_idx;
1182
1183         for (layer_idx = I40E_FLXPLD_L2_IDX;
1184              layer_idx <= I40E_FLXPLD_L4_IDX;
1185              layer_idx++) {
1186                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1187                         ptr->type = RTE_ETH_L2_PAYLOAD;
1188                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1189                         ptr->type = RTE_ETH_L3_PAYLOAD;
1190                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1191                         ptr->type = RTE_ETH_L4_PAYLOAD;
1192
1193                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1194                         flex_pit = &pf->fdir.flex_set[layer_idx *
1195                                 I40E_MAX_FLXPLD_FIED + i];
1196                         if (flex_pit->size == 0)
1197                                 continue;
1198                         src = flex_pit->src_offset * sizeof(uint16_t);
1199                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1200                         size = flex_pit->size * sizeof(uint16_t);
1201                         for (j = src, k = dst; j < src + size; j++, k++)
1202                                 ptr->src_offset[k] = j;
1203                 }
1204                 (*num)++;
1205                 ptr++;
1206         }
1207 }
1208
1209 static inline void
1210 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1211                         struct rte_eth_fdir_flex_mask *flex_mask,
1212                         uint16_t *num)
1213 {
1214         struct i40e_fdir_flex_mask *mask;
1215         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1216         uint16_t flow_type;
1217         uint8_t i, j;
1218         uint16_t off_bytes, mask_tmp;
1219
1220         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1221              i <= I40E_FILTER_PCTYPE_FRAG_IPV6;
1222              i++) {
1223                 mask =  &pf->fdir.flex_mask[i];
1224                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1225                         continue;
1226                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1227                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1228                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1229                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1230                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1231                         } else {
1232                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1233                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1234                         }
1235                 }
1236                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1237                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1238                         mask_tmp = ~mask->bitmask[j].mask;
1239                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1240                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1241                 }
1242                 ptr->flow_type = flow_type;
1243                 ptr++;
1244                 (*num)++;
1245         }
1246 }
1247
1248 /*
1249  * i40e_fdir_info_get - get information of Flow Director
1250  * @pf: ethernet device to get info from
1251  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1252  *    the flow director information.
1253  */
1254 static void
1255 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1256 {
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1259         uint16_t num_flex_set = 0;
1260         uint16_t num_flex_mask = 0;
1261
1262         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1263                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1264         else
1265                 fdir->mode = RTE_FDIR_MODE_NONE;
1266
1267         fdir->guarant_spc =
1268                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1269         fdir->best_spc =
1270                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1271         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1272         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1273         fdir->flex_payload_unit = sizeof(uint16_t);
1274         fdir->flex_bitmask_unit = sizeof(uint16_t);
1275         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1276         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1277         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1278
1279         i40e_fdir_info_get_flex_set(pf,
1280                                 fdir->flex_conf.flex_set,
1281                                 &num_flex_set);
1282         i40e_fdir_info_get_flex_mask(pf,
1283                                 fdir->flex_conf.flex_mask,
1284                                 &num_flex_mask);
1285
1286         fdir->flex_conf.nb_payloads = num_flex_set;
1287         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1288 }
1289
1290 /*
1291  * i40e_fdir_stat_get - get statistics of Flow Director
1292  * @pf: ethernet device to get info from
1293  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1294  *    the flow director statistics.
1295  */
1296 static void
1297 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1298 {
1299         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1300         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1301         uint32_t fdstat;
1302
1303         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1304         stat->guarant_cnt =
1305                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1306                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1307         stat->best_cnt =
1308                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1309                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1310 }
1311
1312 /*
1313  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1314  * @pf: board private structure
1315  * @filter_op:operation will be taken.
1316  * @arg: a pointer to specific structure corresponding to the filter_op
1317  */
1318 int
1319 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1320                        enum rte_filter_op filter_op,
1321                        void *arg)
1322 {
1323         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1324         int ret = 0;
1325
1326         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1327                 return -ENOTSUP;
1328
1329         if (filter_op == RTE_ETH_FILTER_NOP)
1330                 return 0;
1331
1332         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1333                 return -EINVAL;
1334
1335         switch (filter_op) {
1336         case RTE_ETH_FILTER_ADD:
1337                 ret = i40e_add_del_fdir_filter(dev,
1338                         (struct rte_eth_fdir_filter *)arg,
1339                         TRUE);
1340                 break;
1341         case RTE_ETH_FILTER_DELETE:
1342                 ret = i40e_add_del_fdir_filter(dev,
1343                         (struct rte_eth_fdir_filter *)arg,
1344                         FALSE);
1345                 break;
1346         case RTE_ETH_FILTER_FLUSH:
1347                 ret = i40e_fdir_flush(dev);
1348                 break;
1349         case RTE_ETH_FILTER_INFO:
1350                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1351                 break;
1352         case RTE_ETH_FILTER_STATS:
1353                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1354                 break;
1355         default:
1356                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1357                 ret = -EINVAL;
1358                 break;
1359         }
1360         return ret;
1361 }