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34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
71 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
72 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
73 #define I40E_FDIR_UDP_DEFAULT_LEN 400
75 /* Wait time for fdir filter programming */
76 #define I40E_FDIR_MAX_WAIT_US 10000
78 /* Wait count and interval for fdir filter flush */
79 #define I40E_FDIR_FLUSH_RETRY 50
80 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
82 #define I40E_COUNTER_PF 2
83 /* Statistic counter index for one pf */
84 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
86 #define I40E_FDIR_FLOWS ( \
87 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
88 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
89 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
90 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
91 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
92 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
93 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
94 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
95 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
96 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
97 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
99 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
100 enum i40e_filter_pctype pctype,
101 const struct rte_eth_fdir_filter *filter,
103 static int i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
104 struct i40e_fdir_filter *filter);
105 static struct i40e_fdir_filter *
106 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
107 const struct rte_eth_fdir_input *input);
108 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
109 struct i40e_fdir_filter *filter);
112 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
114 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
115 struct i40e_hmc_obj_rxq rx_ctx;
116 int err = I40E_SUCCESS;
118 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
119 /* Init the RX queue in hardware */
120 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
122 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
123 rx_ctx.qlen = rxq->nb_rx_desc;
124 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
127 rx_ctx.dtype = i40e_header_split_none;
128 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
129 rx_ctx.rxmax = ETHER_MAX_LEN;
130 rx_ctx.tphrdesc_ena = 1;
131 rx_ctx.tphwdesc_ena = 1;
132 rx_ctx.tphdata_ena = 1;
133 rx_ctx.tphhead_ena = 1;
134 rx_ctx.lrxqthresh = 2;
140 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
141 if (err != I40E_SUCCESS) {
142 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
145 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
146 if (err != I40E_SUCCESS) {
147 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
150 rxq->qrx_tail = hw->hw_addr +
151 I40E_QRX_TAIL(rxq->vsi->base_queue);
154 /* Init the RX tail regieter. */
155 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
156 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
162 * i40e_fdir_setup - reserve and initialize the Flow Director resources
163 * @pf: board private structure
166 i40e_fdir_setup(struct i40e_pf *pf)
168 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
169 struct i40e_vsi *vsi;
170 int err = I40E_SUCCESS;
171 char z_name[RTE_MEMZONE_NAMESIZE];
172 const struct rte_memzone *mz = NULL;
173 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
175 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
176 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
177 return I40E_NOT_SUPPORTED;
180 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
181 " num_filters_best_effort = %u.",
182 hw->func_caps.fd_filters_guaranteed,
183 hw->func_caps.fd_filters_best_effort);
185 vsi = pf->fdir.fdir_vsi;
187 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
190 /* make new FDIR VSI */
191 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
193 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
194 return I40E_ERR_NO_AVAILABLE_VSI;
196 pf->fdir.fdir_vsi = vsi;
198 /*Fdir tx queue setup*/
199 err = i40e_fdir_setup_tx_resources(pf);
201 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
205 /*Fdir rx queue setup*/
206 err = i40e_fdir_setup_rx_resources(pf);
208 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
212 err = i40e_tx_queue_init(pf->fdir.txq);
214 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
218 /* need switch on before dev start*/
219 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
221 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
225 /* Init the rx queue in hardware */
226 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
228 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
232 /* switch on rx queue */
233 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
235 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
239 /* reserve memory for the fdir programming packet */
240 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
241 eth_dev->device->driver->name,
243 eth_dev->data->port_id);
244 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
246 PMD_DRV_LOG(ERR, "Cannot init memzone for "
247 "flow director program packet.");
248 err = I40E_ERR_NO_MEMORY;
251 pf->fdir.prg_pkt = mz->addr;
252 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
254 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
255 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
260 i40e_dev_rx_queue_release(pf->fdir.rxq);
263 i40e_dev_tx_queue_release(pf->fdir.txq);
266 i40e_vsi_release(vsi);
267 pf->fdir.fdir_vsi = NULL;
272 * i40e_fdir_teardown - release the Flow Director resources
273 * @pf: board private structure
276 i40e_fdir_teardown(struct i40e_pf *pf)
278 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
279 struct i40e_vsi *vsi;
281 vsi = pf->fdir.fdir_vsi;
284 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
286 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
287 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
289 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
290 i40e_dev_rx_queue_release(pf->fdir.rxq);
292 i40e_dev_tx_queue_release(pf->fdir.txq);
294 i40e_vsi_release(vsi);
295 pf->fdir.fdir_vsi = NULL;
298 /* check whether the flow director table in empty */
300 i40e_fdir_empty(struct i40e_hw *hw)
302 uint32_t guarant_cnt, best_cnt;
304 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
305 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
306 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
307 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
308 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
309 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
310 if (best_cnt + guarant_cnt > 0)
317 * Initialize the configuration about bytes stream extracted as flexible payload
321 i40e_init_flx_pld(struct i40e_pf *pf)
323 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
328 * Define the bytes stream extracted as flexible payload in
329 * field vector. By default, select 8 words from the beginning
330 * of payload as flexible payload.
332 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
333 index = i * I40E_MAX_FLXPLD_FIED;
334 pf->fdir.flex_set[index].src_offset = 0;
335 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
336 pf->fdir.flex_set[index].dst_offset = 0;
337 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
339 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
341 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
344 /* initialize the masks */
345 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
346 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
347 if (hw->mac.type == I40E_MAC_X722) {
348 if (!I40E_VALID_PCTYPE_X722(
349 (enum i40e_filter_pctype)pctype))
352 if (!I40E_VALID_PCTYPE(
353 (enum i40e_filter_pctype)pctype))
356 pf->fdir.flex_mask[pctype].word_mask = 0;
357 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
358 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
359 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
360 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
361 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
366 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
367 if ((flex_pit2).src_offset < \
368 (flex_pit1).src_offset + (flex_pit1).size) { \
369 PMD_DRV_LOG(ERR, "src_offset should be not" \
370 " less than than previous offset" \
371 " + previous FSIZE."); \
377 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
378 * and the flex_pit will be sorted by it's src_offset value
380 static inline uint16_t
381 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
382 struct i40e_fdir_flex_pit *flex_pit)
384 uint16_t src_tmp, size, num = 0;
385 uint16_t i, k, j = 0;
387 while (j < I40E_FDIR_MAX_FLEX_LEN) {
389 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
390 if (src_offset[j + 1] == src_offset[j] + 1)
395 src_tmp = src_offset[j] + 1 - size;
396 /* the flex_pit need to be sort by src_offset */
397 for (i = 0; i < num; i++) {
398 if (src_tmp < flex_pit[i].src_offset)
401 /* if insert required, move backward */
402 for (k = num; k > i; k--)
403 flex_pit[k] = flex_pit[k - 1];
405 flex_pit[i].dst_offset = j + 1 - size;
406 flex_pit[i].src_offset = src_tmp;
407 flex_pit[i].size = size;
414 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
416 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
418 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
421 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
422 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
423 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
428 memset(flex_pit, 0, sizeof(flex_pit));
429 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
430 if (num > I40E_MAX_FLXPLD_FIED) {
431 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
434 for (i = 0; i < num; i++) {
435 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
436 flex_pit[i].src_offset & 0x01) {
437 PMD_DRV_LOG(ERR, "flexpayload should be measured"
442 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
448 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
449 * arguments are valid
452 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
454 const struct rte_eth_flex_payload_cfg *flex_cfg;
455 const struct rte_eth_fdir_flex_mask *flex_mask;
462 PMD_DRV_LOG(INFO, "NULL pointer.");
465 /* check flexible payload setting configuration */
466 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
467 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
470 for (i = 0; i < conf->nb_payloads; i++) {
471 flex_cfg = &conf->flex_set[i];
472 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
473 PMD_DRV_LOG(ERR, "invalid payload type.");
476 ret = i40e_check_fdir_flex_payload(flex_cfg);
478 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
483 /* check flex mask setting configuration */
484 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
485 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
488 for (i = 0; i < conf->nb_flexmasks; i++) {
489 flex_mask = &conf->flex_mask[i];
490 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
491 PMD_DRV_LOG(WARNING, "invalid flow type.");
495 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
496 mask_tmp = I40E_WORD(flex_mask->mask[j],
497 flex_mask->mask[j + 1]);
498 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
500 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
501 PMD_DRV_LOG(ERR, " exceed maximal"
502 " number of bitmasks.");
512 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
513 * @pf: board private structure
514 * @cfg: the rule how bytes stream is extracted as flexible payload
517 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
518 const struct rte_eth_flex_payload_cfg *cfg)
520 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
521 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
523 uint16_t num, min_next_off; /* in words */
524 uint8_t field_idx = 0;
525 uint8_t layer_idx = 0;
528 if (cfg->type == RTE_ETH_L2_PAYLOAD)
529 layer_idx = I40E_FLXPLD_L2_IDX;
530 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
531 layer_idx = I40E_FLXPLD_L3_IDX;
532 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
533 layer_idx = I40E_FLXPLD_L4_IDX;
535 memset(flex_pit, 0, sizeof(flex_pit));
536 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
538 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
539 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
540 /* record the info in fdir structure */
541 pf->fdir.flex_set[field_idx].src_offset =
542 flex_pit[i].src_offset / sizeof(uint16_t);
543 pf->fdir.flex_set[field_idx].size =
544 flex_pit[i].size / sizeof(uint16_t);
545 pf->fdir.flex_set[field_idx].dst_offset =
546 flex_pit[i].dst_offset / sizeof(uint16_t);
547 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
548 pf->fdir.flex_set[field_idx].size,
549 pf->fdir.flex_set[field_idx].dst_offset);
551 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
553 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
554 pf->fdir.flex_set[field_idx].size;
556 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
557 /* set the non-used register obeying register's constrain */
558 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
559 NONUSE_FLX_PIT_DEST_OFF);
561 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
568 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
569 * @pf: board private structure
570 * @pctype: packet classify type
571 * @flex_masks: mask for flexible payload
574 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
575 enum i40e_filter_pctype pctype,
576 const struct rte_eth_fdir_flex_mask *mask_cfg)
578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
579 struct i40e_fdir_flex_mask *flex_mask;
580 uint32_t flxinset, fd_mask;
582 uint8_t i, nb_bitmask = 0;
584 flex_mask = &pf->fdir.flex_mask[pctype];
585 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
586 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
587 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
588 if (mask_tmp != 0x0) {
589 flex_mask->word_mask |=
590 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
591 if (mask_tmp != UINT16_MAX) {
593 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
594 flex_mask->bitmask[nb_bitmask].offset =
595 i / sizeof(uint16_t);
600 /* write mask to hw */
601 flxinset = (flex_mask->word_mask <<
602 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
603 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
604 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
606 for (i = 0; i < nb_bitmask; i++) {
607 fd_mask = (flex_mask->bitmask[i].mask <<
608 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
609 I40E_PRTQF_FD_MSK_MASK_MASK;
610 fd_mask |= ((flex_mask->bitmask[i].offset +
611 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
612 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
613 I40E_PRTQF_FD_MSK_OFFSET_MASK;
614 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
619 * Configure flow director related setting
622 i40e_fdir_configure(struct rte_eth_dev *dev)
624 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
626 struct rte_eth_fdir_flex_conf *conf;
627 enum i40e_filter_pctype pctype;
633 * configuration need to be done before
634 * flow director filters are added
635 * If filters exist, flush them.
637 if (i40e_fdir_empty(hw) < 0) {
638 ret = i40e_fdir_flush(dev);
640 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
645 /* enable FDIR filter */
646 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
647 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
648 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
650 i40e_init_flx_pld(pf); /* set flex config to default value */
652 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
653 ret = i40e_check_fdir_flex_conf(conf);
655 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
658 /* configure flex payload */
659 for (i = 0; i < conf->nb_payloads; i++)
660 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
661 /* configure flex mask*/
662 for (i = 0; i < conf->nb_flexmasks; i++) {
663 if (hw->mac.type == I40E_MAC_X722) {
664 /* get translated pctype value in fd pctype register */
665 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
666 hw, I40E_GLQF_FD_PCTYPES(
667 (int)i40e_flowtype_to_pctype(
668 conf->flex_mask[i].flow_type)));
670 pctype = i40e_flowtype_to_pctype(
671 conf->flex_mask[i].flow_type);
673 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
680 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
681 unsigned char *raw_pkt,
684 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
685 uint16_t *ether_type;
686 uint8_t len = 2 * sizeof(struct ether_addr);
688 struct ipv6_hdr *ip6;
689 static const uint8_t next_proto[] = {
690 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
691 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
692 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
693 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
694 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
695 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
696 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
697 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
698 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
699 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
702 raw_pkt += 2 * sizeof(struct ether_addr);
703 if (vlan && fdir_input->flow_ext.vlan_tci) {
704 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
705 rte_memcpy(raw_pkt + sizeof(uint16_t),
706 &fdir_input->flow_ext.vlan_tci,
708 raw_pkt += sizeof(vlan_frame);
709 len += sizeof(vlan_frame);
711 ether_type = (uint16_t *)raw_pkt;
712 raw_pkt += sizeof(uint16_t);
713 len += sizeof(uint16_t);
715 switch (fdir_input->flow_type) {
716 case RTE_ETH_FLOW_L2_PAYLOAD:
717 *ether_type = fdir_input->flow.l2_flow.ether_type;
719 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
720 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
721 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
722 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
723 case RTE_ETH_FLOW_FRAG_IPV4:
724 ip = (struct ipv4_hdr *)raw_pkt;
726 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
727 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
728 /* set len to by default */
729 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
730 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
731 fdir_input->flow.ip4_flow.proto :
732 next_proto[fdir_input->flow_type];
733 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
734 fdir_input->flow.ip4_flow.ttl :
735 I40E_FDIR_IP_DEFAULT_TTL;
736 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
738 * The source and destination fields in the transmitted packet
739 * need to be presented in a reversed order with respect
740 * to the expected received packets.
742 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
743 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
744 len += sizeof(struct ipv4_hdr);
746 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
747 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
748 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
749 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
750 case RTE_ETH_FLOW_FRAG_IPV6:
751 ip6 = (struct ipv6_hdr *)raw_pkt;
753 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
755 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
756 (fdir_input->flow.ipv6_flow.tc <<
757 I40E_FDIR_IPv6_TC_OFFSET));
759 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
760 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
761 fdir_input->flow.ipv6_flow.proto :
762 next_proto[fdir_input->flow_type];
763 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
764 fdir_input->flow.ipv6_flow.hop_limits :
765 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
767 * The source and destination fields in the transmitted packet
768 * need to be presented in a reversed order with respect
769 * to the expected received packets.
771 rte_memcpy(&(ip6->src_addr),
772 &(fdir_input->flow.ipv6_flow.dst_ip),
774 rte_memcpy(&(ip6->dst_addr),
775 &(fdir_input->flow.ipv6_flow.src_ip),
777 len += sizeof(struct ipv6_hdr);
780 PMD_DRV_LOG(ERR, "unknown flow type %u.",
781 fdir_input->flow_type);
789 * i40e_fdir_construct_pkt - construct packet based on fields in input
790 * @pf: board private structure
791 * @fdir_input: input set of the flow director entry
792 * @raw_pkt: a packet to be constructed
795 i40e_fdir_construct_pkt(struct i40e_pf *pf,
796 const struct rte_eth_fdir_input *fdir_input,
797 unsigned char *raw_pkt)
799 unsigned char *payload, *ptr;
802 struct sctp_hdr *sctp;
803 uint8_t size, dst = 0;
804 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
807 /* fill the ethernet and IP head */
808 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
809 !!fdir_input->flow_ext.vlan_tci);
813 /* fill the L4 head */
814 switch (fdir_input->flow_type) {
815 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
816 udp = (struct udp_hdr *)(raw_pkt + len);
817 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
819 * The source and destination fields in the transmitted packet
820 * need to be presented in a reversed order with respect
821 * to the expected received packets.
823 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
824 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
825 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
828 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
829 tcp = (struct tcp_hdr *)(raw_pkt + len);
830 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
832 * The source and destination fields in the transmitted packet
833 * need to be presented in a reversed order with respect
834 * to the expected received packets.
836 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
837 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
838 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
841 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
842 sctp = (struct sctp_hdr *)(raw_pkt + len);
843 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
845 * The source and destination fields in the transmitted packet
846 * need to be presented in a reversed order with respect
847 * to the expected received packets.
849 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
850 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
851 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
854 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
855 case RTE_ETH_FLOW_FRAG_IPV4:
856 payload = raw_pkt + len;
857 set_idx = I40E_FLXPLD_L3_IDX;
860 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
861 udp = (struct udp_hdr *)(raw_pkt + len);
862 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
864 * The source and destination fields in the transmitted packet
865 * need to be presented in a reversed order with respect
866 * to the expected received packets.
868 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
869 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
870 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
873 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
874 tcp = (struct tcp_hdr *)(raw_pkt + len);
875 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
877 * The source and destination fields in the transmitted packet
878 * need to be presented in a reversed order with respect
879 * to the expected received packets.
881 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
882 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
883 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
886 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
887 sctp = (struct sctp_hdr *)(raw_pkt + len);
888 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
890 * The source and destination fields in the transmitted packet
891 * need to be presented in a reversed order with respect
892 * to the expected received packets.
894 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
895 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
896 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
899 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
900 case RTE_ETH_FLOW_FRAG_IPV6:
901 payload = raw_pkt + len;
902 set_idx = I40E_FLXPLD_L3_IDX;
904 case RTE_ETH_FLOW_L2_PAYLOAD:
905 payload = raw_pkt + len;
907 * ARP packet is a special case on which the payload
908 * starts after the whole ARP header
910 if (fdir_input->flow.l2_flow.ether_type ==
911 rte_cpu_to_be_16(ETHER_TYPE_ARP))
912 payload += sizeof(struct arp_hdr);
913 set_idx = I40E_FLXPLD_L2_IDX;
916 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
920 /* fill the flexbytes to payload */
921 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
922 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
923 size = pf->fdir.flex_set[pit_idx].size;
926 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
928 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
929 (void)rte_memcpy(ptr,
930 &fdir_input->flow_ext.flexbytes[dst],
931 size * sizeof(uint16_t));
937 /* Construct the tx flags */
938 static inline uint64_t
939 i40e_build_ctob(uint32_t td_cmd,
944 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
945 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
946 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
947 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
948 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
952 * check the programming status descriptor in rx queue.
953 * done after Programming Flow Director is programmed on
957 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
959 volatile union i40e_rx_desc *rxdp;
966 rxdp = &rxq->rx_ring[rxq->rx_tail];
967 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
968 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
969 >> I40E_RXD_QW1_STATUS_SHIFT;
971 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
972 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
973 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
974 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
976 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
977 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
979 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
980 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
982 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
983 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
984 " (FD_ID %u): programming status"
986 rxdp->wb.qword0.hi_dword.fd_id);
988 } else if (error == (0x1 <<
989 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
990 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
991 " (FD_ID %u): programming status"
993 rxdp->wb.qword0.hi_dword.fd_id);
996 PMD_DRV_LOG(ERR, "invalid programming status"
997 " reported, error = %u.", error);
999 PMD_DRV_LOG(ERR, "unknown programming status"
1000 " reported, len = %d, id = %u.", len, id);
1001 rxdp->wb.qword1.status_error_len = 0;
1003 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1010 i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
1011 struct i40e_fdir_filter *filter)
1013 rte_memcpy(&filter->fdir, input, sizeof(struct rte_eth_fdir_filter));
1017 /* Check if there exists the flow director filter */
1018 static struct i40e_fdir_filter *
1019 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1020 const struct rte_eth_fdir_input *input)
1024 ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1028 return fdir_info->hash_map[ret];
1031 /* Add a flow director filter into the SW list */
1033 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1035 struct i40e_fdir_info *fdir_info = &pf->fdir;
1038 ret = rte_hash_add_key(fdir_info->hash_table,
1039 &filter->fdir.input);
1042 "Failed to insert fdir filter to hash table %d!",
1046 fdir_info->hash_map[ret] = filter;
1048 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1053 /* Delete a flow director filter from the SW list */
1055 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct rte_eth_fdir_input *input)
1057 struct i40e_fdir_info *fdir_info = &pf->fdir;
1058 struct i40e_fdir_filter *filter;
1061 ret = rte_hash_del_key(fdir_info->hash_table, input);
1064 "Failed to delete fdir filter to hash table %d!",
1068 filter = fdir_info->hash_map[ret];
1069 fdir_info->hash_map[ret] = NULL;
1071 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1078 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1079 * @pf: board private structure
1080 * @filter: fdir filter entry
1081 * @add: 0 - delete, 1 - add
1084 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1085 const struct rte_eth_fdir_filter *filter,
1088 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1090 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1091 enum i40e_filter_pctype pctype;
1092 struct i40e_fdir_info *fdir_info = &pf->fdir;
1093 struct i40e_fdir_filter *fdir_filter, *node;
1094 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1097 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1098 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1099 " check the mode in fdir_conf.");
1103 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1104 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1107 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1108 PMD_DRV_LOG(ERR, "Invalid queue ID");
1111 if (filter->input.flow_ext.is_vf &&
1112 filter->input.flow_ext.dst_id >= pf->vf_num) {
1113 PMD_DRV_LOG(ERR, "Invalid VF ID");
1117 /* Check if there is the filter in SW list */
1118 memset(&check_filter, 0, sizeof(check_filter));
1119 i40e_fdir_filter_convert(filter, &check_filter);
1120 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1123 "Conflict with existing flow director rules!");
1127 if (!add && !node) {
1129 "There's no corresponding flow firector filter!");
1133 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1135 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1137 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1141 if (hw->mac.type == I40E_MAC_X722) {
1142 /* get translated pctype value in fd pctype register */
1143 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1144 hw, I40E_GLQF_FD_PCTYPES(
1145 (int)i40e_flowtype_to_pctype(
1146 filter->input.flow_type)));
1148 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1150 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1152 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1158 fdir_filter = rte_zmalloc("fdir_filter",
1159 sizeof(*fdir_filter), 0);
1160 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1161 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1163 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1170 * i40e_fdir_filter_programming - Program a flow director filter rule.
1171 * Is done by Flow Director Programming Descriptor followed by packet
1172 * structure that contains the filter fields need to match.
1173 * @pf: board private structure
1175 * @filter: fdir filter entry
1176 * @add: 0 - delete, 1 - add
1179 i40e_fdir_filter_programming(struct i40e_pf *pf,
1180 enum i40e_filter_pctype pctype,
1181 const struct rte_eth_fdir_filter *filter,
1184 struct i40e_tx_queue *txq = pf->fdir.txq;
1185 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1186 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1187 volatile struct i40e_tx_desc *txdp;
1188 volatile struct i40e_filter_program_desc *fdirdp;
1193 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1194 fdirdp = (volatile struct i40e_filter_program_desc *)
1195 (&(txq->tx_ring[txq->tx_tail]));
1197 fdirdp->qindex_flex_ptype_vsi =
1198 rte_cpu_to_le_32((fdir_action->rx_queue <<
1199 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1200 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1202 fdirdp->qindex_flex_ptype_vsi |=
1203 rte_cpu_to_le_32((fdir_action->flex_off <<
1204 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1205 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1207 fdirdp->qindex_flex_ptype_vsi |=
1208 rte_cpu_to_le_32((pctype <<
1209 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1210 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1212 if (filter->input.flow_ext.is_vf)
1213 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1215 /* Use LAN VSI Id by default */
1216 vsi_id = pf->main_vsi->vsi_id;
1217 fdirdp->qindex_flex_ptype_vsi |=
1218 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1219 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1220 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1222 fdirdp->dtype_cmd_cntindex =
1223 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1226 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1227 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1228 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1230 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1231 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1232 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1234 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1235 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1236 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1237 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1238 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1239 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1241 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1242 " unsupported fdir behavior.");
1246 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1247 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1248 I40E_TXD_FLTR_QW1_DEST_MASK);
1250 fdirdp->dtype_cmd_cntindex |=
1251 rte_cpu_to_le_32((fdir_action->report_status<<
1252 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1253 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1255 fdirdp->dtype_cmd_cntindex |=
1256 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1257 fdirdp->dtype_cmd_cntindex |=
1259 ((uint32_t)pf->fdir.match_counter_index <<
1260 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1261 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1263 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1265 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1266 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1267 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1268 td_cmd = I40E_TX_DESC_CMD_EOP |
1269 I40E_TX_DESC_CMD_RS |
1270 I40E_TX_DESC_CMD_DUMMY;
1272 txdp->cmd_type_offset_bsz =
1273 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1275 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1276 if (txq->tx_tail >= txq->nb_tx_desc)
1278 /* Update the tx tail register */
1280 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1281 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1282 if ((txdp->cmd_type_offset_bsz &
1283 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1284 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1288 if (i >= I40E_FDIR_MAX_WAIT_US) {
1289 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1290 " time out to get DD on tx queue.");
1293 /* totally delay 10 ms to check programming status*/
1294 for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1295 if (i40e_check_fdir_programming_status(rxq) >= 0)
1300 "Failed to program FDIR filter: programming status reported.");
1305 * i40e_fdir_flush - clear all filters of Flow Director table
1306 * @pf: board private structure
1309 i40e_fdir_flush(struct rte_eth_dev *dev)
1311 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1312 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1314 uint16_t guarant_cnt, best_cnt;
1317 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1318 I40E_WRITE_FLUSH(hw);
1320 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1321 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1322 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1323 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1326 if (i >= I40E_FDIR_FLUSH_RETRY) {
1327 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1330 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1331 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1332 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1333 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1334 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1335 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1336 if (guarant_cnt != 0 || best_cnt != 0) {
1337 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1340 PMD_DRV_LOG(INFO, "FD table Flush success.");
1345 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1346 struct rte_eth_flex_payload_cfg *flex_set,
1349 struct i40e_fdir_flex_pit *flex_pit;
1350 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1351 uint16_t src, dst, size, j, k;
1352 uint8_t i, layer_idx;
1354 for (layer_idx = I40E_FLXPLD_L2_IDX;
1355 layer_idx <= I40E_FLXPLD_L4_IDX;
1357 if (layer_idx == I40E_FLXPLD_L2_IDX)
1358 ptr->type = RTE_ETH_L2_PAYLOAD;
1359 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1360 ptr->type = RTE_ETH_L3_PAYLOAD;
1361 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1362 ptr->type = RTE_ETH_L4_PAYLOAD;
1364 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1365 flex_pit = &pf->fdir.flex_set[layer_idx *
1366 I40E_MAX_FLXPLD_FIED + i];
1367 if (flex_pit->size == 0)
1369 src = flex_pit->src_offset * sizeof(uint16_t);
1370 dst = flex_pit->dst_offset * sizeof(uint16_t);
1371 size = flex_pit->size * sizeof(uint16_t);
1372 for (j = src, k = dst; j < src + size; j++, k++)
1373 ptr->src_offset[k] = j;
1381 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1382 struct rte_eth_fdir_flex_mask *flex_mask,
1385 struct i40e_fdir_flex_mask *mask;
1386 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1387 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1390 uint16_t off_bytes, mask_tmp;
1392 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1393 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1395 mask = &pf->fdir.flex_mask[i];
1396 if (hw->mac.type == I40E_MAC_X722) {
1397 if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1400 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1403 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1404 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1405 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1406 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1407 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1409 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1410 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1413 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1414 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1415 mask_tmp = ~mask->bitmask[j].mask;
1416 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1417 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1419 ptr->flow_type = flow_type;
1426 * i40e_fdir_info_get - get information of Flow Director
1427 * @pf: ethernet device to get info from
1428 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1429 * the flow director information.
1432 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1435 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1436 uint16_t num_flex_set = 0;
1437 uint16_t num_flex_mask = 0;
1439 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1440 fdir->mode = RTE_FDIR_MODE_PERFECT;
1442 fdir->mode = RTE_FDIR_MODE_NONE;
1445 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1447 (uint32_t)hw->func_caps.fd_filters_best_effort;
1448 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1449 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1450 fdir->flex_payload_unit = sizeof(uint16_t);
1451 fdir->flex_bitmask_unit = sizeof(uint16_t);
1452 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1453 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1454 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1456 i40e_fdir_info_get_flex_set(pf,
1457 fdir->flex_conf.flex_set,
1459 i40e_fdir_info_get_flex_mask(pf,
1460 fdir->flex_conf.flex_mask,
1463 fdir->flex_conf.nb_payloads = num_flex_set;
1464 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1468 * i40e_fdir_stat_get - get statistics of Flow Director
1469 * @pf: ethernet device to get info from
1470 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1471 * the flow director statistics.
1474 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1477 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1480 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1482 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1483 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1485 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1486 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1490 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1491 struct rte_eth_fdir_filter_info *info)
1493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1497 PMD_DRV_LOG(ERR, "Invalid pointer");
1501 switch (info->info_type) {
1502 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1503 ret = i40e_fdir_filter_inset_select(pf,
1504 &(info->info.input_set_conf));
1507 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1516 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1517 * @pf: board private structure
1518 * @filter_op:operation will be taken.
1519 * @arg: a pointer to specific structure corresponding to the filter_op
1522 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1523 enum rte_filter_op filter_op,
1526 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1529 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1532 if (filter_op == RTE_ETH_FILTER_NOP)
1535 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1538 switch (filter_op) {
1539 case RTE_ETH_FILTER_ADD:
1540 ret = i40e_add_del_fdir_filter(dev,
1541 (struct rte_eth_fdir_filter *)arg,
1544 case RTE_ETH_FILTER_DELETE:
1545 ret = i40e_add_del_fdir_filter(dev,
1546 (struct rte_eth_fdir_filter *)arg,
1549 case RTE_ETH_FILTER_FLUSH:
1550 ret = i40e_fdir_flush(dev);
1552 case RTE_ETH_FILTER_INFO:
1553 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1555 case RTE_ETH_FILTER_SET:
1556 ret = i40e_fdir_filter_set(dev,
1557 (struct rte_eth_fdir_filter_info *)arg);
1559 case RTE_ETH_FILTER_STATS:
1560 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1563 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1570 /* Restore flow director filter */
1572 i40e_fdir_filter_restore(struct i40e_pf *pf)
1574 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
1575 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
1576 struct i40e_fdir_filter *f;
1577 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1579 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
1580 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
1582 TAILQ_FOREACH(f, fdir_list, rules)
1583 i40e_add_del_fdir_filter(dev, &f->fdir, TRUE);
1585 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1587 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1588 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1590 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1591 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1593 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
1594 guarant_cnt, best_cnt);