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34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
70 #define I40E_FDIR_IPv6_TC_OFFSET 20
72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
73 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
74 #define I40E_FDIR_UDP_DEFAULT_LEN 400
76 /* Wait count and interval for fdir filter programming */
77 #define I40E_FDIR_WAIT_COUNT 10
78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
80 /* Wait count and interval for fdir filter flush */
81 #define I40E_FDIR_FLUSH_RETRY 50
82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
84 #define I40E_COUNTER_PF 2
85 /* Statistic counter index for one pf */
86 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
87 #define I40E_MAX_FLX_SOURCE_OFF 480
88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
90 #define NONUSE_FLX_PIT_DEST_OFF 63
91 #define NONUSE_FLX_PIT_FSIZE 1
92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
93 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
94 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
95 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
96 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
97 ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
98 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
99 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
101 #define I40E_FDIR_FLOWS ( \
102 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
103 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
104 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
105 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
106 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
107 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
108 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
109 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
110 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
111 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
112 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
114 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
116 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
117 enum i40e_filter_pctype pctype,
118 const struct rte_eth_fdir_filter *filter,
120 static int i40e_fdir_flush(struct rte_eth_dev *dev);
123 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
125 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
126 struct i40e_hmc_obj_rxq rx_ctx;
127 int err = I40E_SUCCESS;
129 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
130 /* Init the RX queue in hardware */
131 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
133 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
134 rx_ctx.qlen = rxq->nb_rx_desc;
135 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
138 rx_ctx.dtype = i40e_header_split_none;
139 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
140 rx_ctx.rxmax = ETHER_MAX_LEN;
141 rx_ctx.tphrdesc_ena = 1;
142 rx_ctx.tphwdesc_ena = 1;
143 rx_ctx.tphdata_ena = 1;
144 rx_ctx.tphhead_ena = 1;
145 rx_ctx.lrxqthresh = 2;
151 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
152 if (err != I40E_SUCCESS) {
153 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
156 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
157 if (err != I40E_SUCCESS) {
158 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
161 rxq->qrx_tail = hw->hw_addr +
162 I40E_QRX_TAIL(rxq->vsi->base_queue);
165 /* Init the RX tail regieter. */
166 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
167 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
173 * i40e_fdir_setup - reserve and initialize the Flow Director resources
174 * @pf: board private structure
177 i40e_fdir_setup(struct i40e_pf *pf)
179 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
180 struct i40e_vsi *vsi;
181 int err = I40E_SUCCESS;
182 char z_name[RTE_MEMZONE_NAMESIZE];
183 const struct rte_memzone *mz = NULL;
184 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
186 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
187 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
188 return I40E_NOT_SUPPORTED;
191 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
192 " num_filters_best_effort = %u.",
193 hw->func_caps.fd_filters_guaranteed,
194 hw->func_caps.fd_filters_best_effort);
196 vsi = pf->fdir.fdir_vsi;
198 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
201 /* make new FDIR VSI */
202 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
204 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
205 return I40E_ERR_NO_AVAILABLE_VSI;
207 pf->fdir.fdir_vsi = vsi;
209 /*Fdir tx queue setup*/
210 err = i40e_fdir_setup_tx_resources(pf);
212 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
216 /*Fdir rx queue setup*/
217 err = i40e_fdir_setup_rx_resources(pf);
219 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
223 err = i40e_tx_queue_init(pf->fdir.txq);
225 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
229 /* need switch on before dev start*/
230 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
232 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
236 /* Init the rx queue in hardware */
237 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
239 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
243 /* switch on rx queue */
244 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
246 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
250 /* reserve memory for the fdir programming packet */
251 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
252 eth_dev->driver->pci_drv.name,
254 eth_dev->data->port_id);
255 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
257 PMD_DRV_LOG(ERR, "Cannot init memzone for "
258 "flow director program packet.");
259 err = I40E_ERR_NO_MEMORY;
262 pf->fdir.prg_pkt = mz->addr;
263 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
265 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
266 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
271 i40e_dev_rx_queue_release(pf->fdir.rxq);
274 i40e_dev_tx_queue_release(pf->fdir.txq);
277 i40e_vsi_release(vsi);
278 pf->fdir.fdir_vsi = NULL;
283 * i40e_fdir_teardown - release the Flow Director resources
284 * @pf: board private structure
287 i40e_fdir_teardown(struct i40e_pf *pf)
289 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
290 struct i40e_vsi *vsi;
292 vsi = pf->fdir.fdir_vsi;
295 i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
296 i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
297 i40e_dev_rx_queue_release(pf->fdir.rxq);
299 i40e_dev_tx_queue_release(pf->fdir.txq);
301 i40e_vsi_release(vsi);
302 pf->fdir.fdir_vsi = NULL;
305 /* check whether the flow director table in empty */
307 i40e_fdir_empty(struct i40e_hw *hw)
309 uint32_t guarant_cnt, best_cnt;
311 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
312 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
313 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
314 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
315 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
316 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
317 if (best_cnt + guarant_cnt > 0)
324 * Initialize the configuration about bytes stream extracted as flexible payload
328 i40e_init_flx_pld(struct i40e_pf *pf)
330 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
335 * Define the bytes stream extracted as flexible payload in
336 * field vector. By default, select 8 words from the beginning
337 * of payload as flexible payload.
339 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
340 index = i * I40E_MAX_FLXPLD_FIED;
341 pf->fdir.flex_set[index].src_offset = 0;
342 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
343 pf->fdir.flex_set[index].dst_offset = 0;
344 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
346 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
348 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
351 /* initialize the masks */
352 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
353 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
354 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))
356 pf->fdir.flex_mask[pctype].word_mask = 0;
357 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
358 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
359 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
360 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
361 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
366 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
368 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
369 if ((flex_pit2).src_offset < \
370 (flex_pit1).src_offset + (flex_pit1).size) { \
371 PMD_DRV_LOG(ERR, "src_offset should be not" \
372 " less than than previous offset" \
373 " + previous FSIZE."); \
379 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
380 * and the flex_pit will be sorted by it's src_offset value
382 static inline uint16_t
383 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
384 struct i40e_fdir_flex_pit *flex_pit)
386 uint16_t src_tmp, size, num = 0;
387 uint16_t i, k, j = 0;
389 while (j < I40E_FDIR_MAX_FLEX_LEN) {
391 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
392 if (src_offset[j + 1] == src_offset[j] + 1)
397 src_tmp = src_offset[j] + 1 - size;
398 /* the flex_pit need to be sort by src_offset */
399 for (i = 0; i < num; i++) {
400 if (src_tmp < flex_pit[i].src_offset)
403 /* if insert required, move backward */
404 for (k = num; k > i; k--)
405 flex_pit[k] = flex_pit[k - 1];
407 flex_pit[i].dst_offset = j + 1 - size;
408 flex_pit[i].src_offset = src_tmp;
409 flex_pit[i].size = size;
416 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
418 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
420 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
423 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
424 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
425 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
430 memset(flex_pit, 0, sizeof(flex_pit));
431 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
432 if (num > I40E_MAX_FLXPLD_FIED) {
433 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
436 for (i = 0; i < num; i++) {
437 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
438 flex_pit[i].src_offset & 0x01) {
439 PMD_DRV_LOG(ERR, "flexpayload should be measured"
444 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
450 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
451 * arguments are valid
454 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
456 const struct rte_eth_flex_payload_cfg *flex_cfg;
457 const struct rte_eth_fdir_flex_mask *flex_mask;
464 PMD_DRV_LOG(INFO, "NULL pointer.");
467 /* check flexible payload setting configuration */
468 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
469 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
472 for (i = 0; i < conf->nb_payloads; i++) {
473 flex_cfg = &conf->flex_set[i];
474 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
475 PMD_DRV_LOG(ERR, "invalid payload type.");
478 ret = i40e_check_fdir_flex_payload(flex_cfg);
480 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
485 /* check flex mask setting configuration */
486 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
487 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
490 for (i = 0; i < conf->nb_flexmasks; i++) {
491 flex_mask = &conf->flex_mask[i];
492 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
493 PMD_DRV_LOG(WARNING, "invalid flow type.");
497 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
498 mask_tmp = I40E_WORD(flex_mask->mask[j],
499 flex_mask->mask[j + 1]);
500 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
502 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
503 PMD_DRV_LOG(ERR, " exceed maximal"
504 " number of bitmasks.");
514 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
515 * @pf: board private structure
516 * @cfg: the rule how bytes stream is extracted as flexible payload
519 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
520 const struct rte_eth_flex_payload_cfg *cfg)
522 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
523 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
525 uint16_t num, min_next_off; /* in words */
526 uint8_t field_idx = 0;
527 uint8_t layer_idx = 0;
530 if (cfg->type == RTE_ETH_L2_PAYLOAD)
531 layer_idx = I40E_FLXPLD_L2_IDX;
532 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
533 layer_idx = I40E_FLXPLD_L3_IDX;
534 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
535 layer_idx = I40E_FLXPLD_L4_IDX;
537 memset(flex_pit, 0, sizeof(flex_pit));
538 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
540 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
541 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
542 /* record the info in fdir structure */
543 pf->fdir.flex_set[field_idx].src_offset =
544 flex_pit[i].src_offset / sizeof(uint16_t);
545 pf->fdir.flex_set[field_idx].size =
546 flex_pit[i].size / sizeof(uint16_t);
547 pf->fdir.flex_set[field_idx].dst_offset =
548 flex_pit[i].dst_offset / sizeof(uint16_t);
549 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
550 pf->fdir.flex_set[field_idx].size,
551 pf->fdir.flex_set[field_idx].dst_offset);
553 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
555 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
556 pf->fdir.flex_set[field_idx].size;
558 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
559 /* set the non-used register obeying register's constrain */
560 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
561 NONUSE_FLX_PIT_DEST_OFF);
563 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
570 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
571 * @pf: board private structure
572 * @pctype: packet classify type
573 * @flex_masks: mask for flexible payload
576 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
577 enum i40e_filter_pctype pctype,
578 const struct rte_eth_fdir_flex_mask *mask_cfg)
580 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
581 struct i40e_fdir_flex_mask *flex_mask;
582 uint32_t flxinset, fd_mask;
584 uint8_t i, nb_bitmask = 0;
586 flex_mask = &pf->fdir.flex_mask[pctype];
587 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
588 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
589 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
590 if (mask_tmp != 0x0) {
591 flex_mask->word_mask |=
592 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
593 if (mask_tmp != UINT16_MAX) {
595 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
596 flex_mask->bitmask[nb_bitmask].offset =
597 i / sizeof(uint16_t);
602 /* write mask to hw */
603 flxinset = (flex_mask->word_mask <<
604 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
605 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
606 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
608 for (i = 0; i < nb_bitmask; i++) {
609 fd_mask = (flex_mask->bitmask[i].mask <<
610 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
611 I40E_PRTQF_FD_MSK_MASK_MASK;
612 fd_mask |= ((flex_mask->bitmask[i].offset +
613 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
614 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
615 I40E_PRTQF_FD_MSK_OFFSET_MASK;
616 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
621 * Configure flow director related setting
624 i40e_fdir_configure(struct rte_eth_dev *dev)
626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
628 struct rte_eth_fdir_flex_conf *conf;
629 enum i40e_filter_pctype pctype;
635 * configuration need to be done before
636 * flow director filters are added
637 * If filters exist, flush them.
639 if (i40e_fdir_empty(hw) < 0) {
640 ret = i40e_fdir_flush(dev);
642 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
647 /* enable FDIR filter */
648 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
649 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
650 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
652 i40e_init_flx_pld(pf); /* set flex config to default value */
654 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
655 ret = i40e_check_fdir_flex_conf(conf);
657 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
660 /* configure flex payload */
661 for (i = 0; i < conf->nb_payloads; i++)
662 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
663 /* configure flex mask*/
664 for (i = 0; i < conf->nb_flexmasks; i++) {
665 pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);
666 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
673 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
674 unsigned char *raw_pkt,
677 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
678 uint16_t *ether_type;
679 uint8_t len = 2 * sizeof(struct ether_addr);
681 struct ipv6_hdr *ip6;
682 static const uint8_t next_proto[] = {
683 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
684 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
685 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
686 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
687 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
688 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
689 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
690 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
691 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
692 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
695 raw_pkt += 2 * sizeof(struct ether_addr);
696 if (vlan && fdir_input->flow_ext.vlan_tci) {
697 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
698 rte_memcpy(raw_pkt + sizeof(uint16_t),
699 &fdir_input->flow_ext.vlan_tci,
701 raw_pkt += sizeof(vlan_frame);
702 len += sizeof(vlan_frame);
704 ether_type = (uint16_t *)raw_pkt;
705 raw_pkt += sizeof(uint16_t);
706 len += sizeof(uint16_t);
708 switch (fdir_input->flow_type) {
709 case RTE_ETH_FLOW_L2_PAYLOAD:
710 *ether_type = fdir_input->flow.l2_flow.ether_type;
712 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
713 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
714 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
715 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
716 case RTE_ETH_FLOW_FRAG_IPV4:
717 ip = (struct ipv4_hdr *)raw_pkt;
719 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
720 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
721 /* set len to by default */
722 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
723 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
724 fdir_input->flow.ip4_flow.proto :
725 next_proto[fdir_input->flow_type];
726 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
727 fdir_input->flow.ip4_flow.ttl :
728 I40E_FDIR_IP_DEFAULT_TTL;
729 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
731 * The source and destination fields in the transmitted packet
732 * need to be presented in a reversed order with respect
733 * to the expected received packets.
735 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
736 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
737 len += sizeof(struct ipv4_hdr);
739 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
740 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
741 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
742 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
743 case RTE_ETH_FLOW_FRAG_IPV6:
744 ip6 = (struct ipv6_hdr *)raw_pkt;
746 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
748 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
749 (fdir_input->flow.ipv6_flow.tc <<
750 I40E_FDIR_IPv6_TC_OFFSET));
752 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
753 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
754 fdir_input->flow.ipv6_flow.proto :
755 next_proto[fdir_input->flow_type];
756 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
757 fdir_input->flow.ipv6_flow.hop_limits :
758 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
760 * The source and destination fields in the transmitted packet
761 * need to be presented in a reversed order with respect
762 * to the expected received packets.
764 rte_memcpy(&(ip6->src_addr),
765 &(fdir_input->flow.ipv6_flow.dst_ip),
767 rte_memcpy(&(ip6->dst_addr),
768 &(fdir_input->flow.ipv6_flow.src_ip),
770 len += sizeof(struct ipv6_hdr);
773 PMD_DRV_LOG(ERR, "unknown flow type %u.",
774 fdir_input->flow_type);
782 * i40e_fdir_construct_pkt - construct packet based on fields in input
783 * @pf: board private structure
784 * @fdir_input: input set of the flow director entry
785 * @raw_pkt: a packet to be constructed
788 i40e_fdir_construct_pkt(struct i40e_pf *pf,
789 const struct rte_eth_fdir_input *fdir_input,
790 unsigned char *raw_pkt)
792 unsigned char *payload, *ptr;
795 struct sctp_hdr *sctp;
796 uint8_t size, dst = 0;
797 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
800 /* fill the ethernet and IP head */
801 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
802 !!fdir_input->flow_ext.vlan_tci);
806 /* fill the L4 head */
807 switch (fdir_input->flow_type) {
808 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
809 udp = (struct udp_hdr *)(raw_pkt + len);
810 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
812 * The source and destination fields in the transmitted packet
813 * need to be presented in a reversed order with respect
814 * to the expected received packets.
816 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
817 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
818 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
821 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
822 tcp = (struct tcp_hdr *)(raw_pkt + len);
823 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
825 * The source and destination fields in the transmitted packet
826 * need to be presented in a reversed order with respect
827 * to the expected received packets.
829 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
830 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
831 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
834 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
835 sctp = (struct sctp_hdr *)(raw_pkt + len);
836 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
838 * The source and destination fields in the transmitted packet
839 * need to be presented in a reversed order with respect
840 * to the expected received packets.
842 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
843 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
844 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
847 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
848 case RTE_ETH_FLOW_FRAG_IPV4:
849 payload = raw_pkt + len;
850 set_idx = I40E_FLXPLD_L3_IDX;
853 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
854 udp = (struct udp_hdr *)(raw_pkt + len);
855 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
857 * The source and destination fields in the transmitted packet
858 * need to be presented in a reversed order with respect
859 * to the expected received packets.
861 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
862 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
863 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
866 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
867 tcp = (struct tcp_hdr *)(raw_pkt + len);
868 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
870 * The source and destination fields in the transmitted packet
871 * need to be presented in a reversed order with respect
872 * to the expected received packets.
874 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
875 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
876 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
879 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
880 sctp = (struct sctp_hdr *)(raw_pkt + len);
881 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
883 * The source and destination fields in the transmitted packet
884 * need to be presented in a reversed order with respect
885 * to the expected received packets.
887 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
888 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
889 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
892 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
893 case RTE_ETH_FLOW_FRAG_IPV6:
894 payload = raw_pkt + len;
895 set_idx = I40E_FLXPLD_L3_IDX;
897 case RTE_ETH_FLOW_L2_PAYLOAD:
898 payload = raw_pkt + len;
900 * ARP packet is a special case on which the payload
901 * starts after the whole ARP header
903 if (fdir_input->flow.l2_flow.ether_type ==
904 rte_cpu_to_be_16(ETHER_TYPE_ARP))
905 payload += sizeof(struct arp_hdr);
906 set_idx = I40E_FLXPLD_L2_IDX;
909 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
913 /* fill the flexbytes to payload */
914 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
915 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
916 size = pf->fdir.flex_set[pit_idx].size;
919 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
921 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
922 (void)rte_memcpy(ptr,
923 &fdir_input->flow_ext.flexbytes[dst],
924 size * sizeof(uint16_t));
930 /* Construct the tx flags */
931 static inline uint64_t
932 i40e_build_ctob(uint32_t td_cmd,
937 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
938 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
939 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
940 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
941 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
945 * check the programming status descriptor in rx queue.
946 * done after Programming Flow Director is programmed on
950 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
952 volatile union i40e_rx_desc *rxdp;
959 rxdp = &rxq->rx_ring[rxq->rx_tail];
960 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
961 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
962 >> I40E_RXD_QW1_STATUS_SHIFT;
964 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
965 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
966 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
967 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
969 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
970 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
972 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
973 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
975 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
976 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
977 " (FD_ID %u): programming status"
979 rxdp->wb.qword0.hi_dword.fd_id);
981 } else if (error == (0x1 <<
982 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
983 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
984 " (FD_ID %u): programming status"
986 rxdp->wb.qword0.hi_dword.fd_id);
989 PMD_DRV_LOG(ERR, "invalid programming status"
990 " reported, error = %u.", error);
992 PMD_DRV_LOG(ERR, "unknown programming status"
993 " reported, len = %d, id = %u.", len, id);
994 rxdp->wb.qword1.status_error_len = 0;
996 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1003 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1004 * @pf: board private structure
1005 * @filter: fdir filter entry
1006 * @add: 0 - delete, 1 - add
1009 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1010 const struct rte_eth_fdir_filter *filter,
1013 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1015 enum i40e_filter_pctype pctype;
1018 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1019 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1020 " check the mode in fdir_conf.");
1024 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1025 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1028 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1029 PMD_DRV_LOG(ERR, "Invalid queue ID");
1032 if (filter->input.flow_ext.is_vf &&
1033 filter->input.flow_ext.dst_id >= pf->vf_num) {
1034 PMD_DRV_LOG(ERR, "Invalid VF ID");
1038 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1040 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1042 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1045 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1046 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1048 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1056 * i40e_fdir_filter_programming - Program a flow director filter rule.
1057 * Is done by Flow Director Programming Descriptor followed by packet
1058 * structure that contains the filter fields need to match.
1059 * @pf: board private structure
1061 * @filter: fdir filter entry
1062 * @add: 0 - delete, 1 - add
1065 i40e_fdir_filter_programming(struct i40e_pf *pf,
1066 enum i40e_filter_pctype pctype,
1067 const struct rte_eth_fdir_filter *filter,
1070 struct i40e_tx_queue *txq = pf->fdir.txq;
1071 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1072 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1073 volatile struct i40e_tx_desc *txdp;
1074 volatile struct i40e_filter_program_desc *fdirdp;
1079 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1080 fdirdp = (volatile struct i40e_filter_program_desc *)
1081 (&(txq->tx_ring[txq->tx_tail]));
1083 fdirdp->qindex_flex_ptype_vsi =
1084 rte_cpu_to_le_32((fdir_action->rx_queue <<
1085 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1086 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1088 fdirdp->qindex_flex_ptype_vsi |=
1089 rte_cpu_to_le_32((fdir_action->flex_off <<
1090 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1091 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1093 fdirdp->qindex_flex_ptype_vsi |=
1094 rte_cpu_to_le_32((pctype <<
1095 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1096 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1098 if (filter->input.flow_ext.is_vf)
1099 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1101 /* Use LAN VSI Id by default */
1102 vsi_id = pf->main_vsi->vsi_id;
1103 fdirdp->qindex_flex_ptype_vsi |=
1104 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1105 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1106 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1108 fdirdp->dtype_cmd_cntindex =
1109 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1112 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1113 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1114 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1116 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1117 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1118 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1120 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1121 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1122 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1123 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1124 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1125 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1127 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1128 " unsupported fdir behavior.");
1132 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1133 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1134 I40E_TXD_FLTR_QW1_DEST_MASK);
1136 fdirdp->dtype_cmd_cntindex |=
1137 rte_cpu_to_le_32((fdir_action->report_status<<
1138 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1139 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1141 fdirdp->dtype_cmd_cntindex |=
1142 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1143 fdirdp->dtype_cmd_cntindex |=
1144 rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1145 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1146 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1148 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1150 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1151 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1152 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1153 td_cmd = I40E_TX_DESC_CMD_EOP |
1154 I40E_TX_DESC_CMD_RS |
1155 I40E_TX_DESC_CMD_DUMMY;
1157 txdp->cmd_type_offset_bsz =
1158 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1160 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1161 if (txq->tx_tail >= txq->nb_tx_desc)
1163 /* Update the tx tail register */
1165 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1167 for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1168 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1169 if ((txdp->cmd_type_offset_bsz &
1170 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1171 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1174 if (i >= I40E_FDIR_WAIT_COUNT) {
1175 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1176 " time out to get DD on tx queue.");
1179 /* totally delay 10 ms to check programming status*/
1180 rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1181 if (i40e_check_fdir_programming_status(rxq) < 0) {
1182 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1183 " programming status reported.");
1191 * i40e_fdir_flush - clear all filters of Flow Director table
1192 * @pf: board private structure
1195 i40e_fdir_flush(struct rte_eth_dev *dev)
1197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1200 uint16_t guarant_cnt, best_cnt;
1203 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1204 I40E_WRITE_FLUSH(hw);
1206 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1207 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1208 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1209 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1212 if (i >= I40E_FDIR_FLUSH_RETRY) {
1213 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1216 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1217 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1218 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1219 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1220 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1221 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1222 if (guarant_cnt != 0 || best_cnt != 0) {
1223 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1226 PMD_DRV_LOG(INFO, "FD table Flush success.");
1231 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1232 struct rte_eth_flex_payload_cfg *flex_set,
1235 struct i40e_fdir_flex_pit *flex_pit;
1236 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1237 uint16_t src, dst, size, j, k;
1238 uint8_t i, layer_idx;
1240 for (layer_idx = I40E_FLXPLD_L2_IDX;
1241 layer_idx <= I40E_FLXPLD_L4_IDX;
1243 if (layer_idx == I40E_FLXPLD_L2_IDX)
1244 ptr->type = RTE_ETH_L2_PAYLOAD;
1245 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1246 ptr->type = RTE_ETH_L3_PAYLOAD;
1247 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1248 ptr->type = RTE_ETH_L4_PAYLOAD;
1250 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1251 flex_pit = &pf->fdir.flex_set[layer_idx *
1252 I40E_MAX_FLXPLD_FIED + i];
1253 if (flex_pit->size == 0)
1255 src = flex_pit->src_offset * sizeof(uint16_t);
1256 dst = flex_pit->dst_offset * sizeof(uint16_t);
1257 size = flex_pit->size * sizeof(uint16_t);
1258 for (j = src, k = dst; j < src + size; j++, k++)
1259 ptr->src_offset[k] = j;
1267 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1268 struct rte_eth_fdir_flex_mask *flex_mask,
1271 struct i40e_fdir_flex_mask *mask;
1272 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1275 uint16_t off_bytes, mask_tmp;
1277 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1278 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1280 mask = &pf->fdir.flex_mask[i];
1281 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1283 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1284 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1285 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1286 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1287 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1289 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1290 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1293 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1294 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1295 mask_tmp = ~mask->bitmask[j].mask;
1296 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1297 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1299 ptr->flow_type = flow_type;
1306 * i40e_fdir_info_get - get information of Flow Director
1307 * @pf: ethernet device to get info from
1308 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1309 * the flow director information.
1312 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1314 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1316 uint16_t num_flex_set = 0;
1317 uint16_t num_flex_mask = 0;
1319 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1320 fdir->mode = RTE_FDIR_MODE_PERFECT;
1322 fdir->mode = RTE_FDIR_MODE_NONE;
1325 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1327 (uint32_t)hw->func_caps.fd_filters_best_effort;
1328 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1329 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1330 fdir->flex_payload_unit = sizeof(uint16_t);
1331 fdir->flex_bitmask_unit = sizeof(uint16_t);
1332 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1333 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1334 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1336 i40e_fdir_info_get_flex_set(pf,
1337 fdir->flex_conf.flex_set,
1339 i40e_fdir_info_get_flex_mask(pf,
1340 fdir->flex_conf.flex_mask,
1343 fdir->flex_conf.nb_payloads = num_flex_set;
1344 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1348 * i40e_fdir_stat_get - get statistics of Flow Director
1349 * @pf: ethernet device to get info from
1350 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1351 * the flow director statistics.
1354 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1356 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1357 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1360 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1362 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1363 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1365 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1366 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1370 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1371 struct rte_eth_fdir_filter_info *info)
1373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1377 PMD_DRV_LOG(ERR, "Invalid pointer");
1381 switch (info->info_type) {
1382 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1383 ret = i40e_fdir_filter_inset_select(pf,
1384 &(info->info.input_set_conf));
1387 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1396 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1397 * @pf: board private structure
1398 * @filter_op:operation will be taken.
1399 * @arg: a pointer to specific structure corresponding to the filter_op
1402 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1403 enum rte_filter_op filter_op,
1406 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1409 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1412 if (filter_op == RTE_ETH_FILTER_NOP)
1415 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1418 switch (filter_op) {
1419 case RTE_ETH_FILTER_ADD:
1420 ret = i40e_add_del_fdir_filter(dev,
1421 (struct rte_eth_fdir_filter *)arg,
1424 case RTE_ETH_FILTER_DELETE:
1425 ret = i40e_add_del_fdir_filter(dev,
1426 (struct rte_eth_fdir_filter *)arg,
1429 case RTE_ETH_FILTER_FLUSH:
1430 ret = i40e_fdir_flush(dev);
1432 case RTE_ETH_FILTER_INFO:
1433 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1435 case RTE_ETH_FILTER_SET:
1436 ret = i40e_fdir_filter_set(dev,
1437 (struct rte_eth_fdir_filter_info *)arg);
1439 case RTE_ETH_FILTER_STATS:
1440 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1443 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);