1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
16 #include <rte_memzone.h>
17 #include <rte_malloc.h>
23 #include <rte_hash_crc.h>
25 #include "i40e_logs.h"
26 #include "base/i40e_type.h"
27 #include "base/i40e_prototype.h"
28 #include "i40e_ethdev.h"
29 #include "i40e_rxtx.h"
31 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
33 #define IPV6_ADDR_LEN 16
37 #define IPPROTO_L2TP 115
40 #define I40E_FDIR_PKT_LEN 512
41 #define I40E_FDIR_IP_DEFAULT_LEN 420
42 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
43 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
44 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
45 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
47 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
48 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
49 #define I40E_FDIR_UDP_DEFAULT_LEN 400
50 #define I40E_FDIR_GTP_DEFAULT_LEN 384
51 #define I40E_FDIR_INNER_IP_DEFAULT_LEN 384
52 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN 344
54 #define I40E_FDIR_GTPC_DST_PORT 2123
55 #define I40E_FDIR_GTPU_DST_PORT 2152
56 #define I40E_FDIR_GTP_VER_FLAG_0X30 0x30
57 #define I40E_FDIR_GTP_VER_FLAG_0X32 0x32
58 #define I40E_FDIR_GTP_MSG_TYPE_0X01 0x01
59 #define I40E_FDIR_GTP_MSG_TYPE_0XFF 0xFF
61 #define I40E_FDIR_ESP_DST_PORT 4500
63 /* Wait time for fdir filter programming */
64 #define I40E_FDIR_MAX_WAIT_US 10000
66 /* Wait count and interval for fdir filter flush */
67 #define I40E_FDIR_FLUSH_RETRY 50
68 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
70 #define I40E_COUNTER_PF 2
71 /* Statistic counter index for one pf */
72 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
74 #define I40E_FDIR_FLOWS ( \
75 (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
76 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
77 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
78 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
79 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
80 (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
81 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
82 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
83 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
84 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
85 (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
87 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
88 enum i40e_filter_pctype pctype,
89 const struct rte_eth_fdir_filter *filter,
91 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
92 struct i40e_fdir_filter *filter);
93 static struct i40e_fdir_filter *
94 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
95 const struct i40e_fdir_input *input);
96 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
97 struct i40e_fdir_filter *filter);
99 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
100 enum i40e_filter_pctype pctype,
101 const struct i40e_fdir_filter_conf *filter,
105 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
107 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
108 struct i40e_hmc_obj_rxq rx_ctx;
109 int err = I40E_SUCCESS;
111 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
112 /* Init the RX queue in hardware */
113 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
115 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
116 rx_ctx.qlen = rxq->nb_rx_desc;
117 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
120 rx_ctx.dtype = i40e_header_split_none;
121 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
122 rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
123 rx_ctx.tphrdesc_ena = 1;
124 rx_ctx.tphwdesc_ena = 1;
125 rx_ctx.tphdata_ena = 1;
126 rx_ctx.tphhead_ena = 1;
127 rx_ctx.lrxqthresh = 2;
133 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
134 if (err != I40E_SUCCESS) {
135 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
138 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
139 if (err != I40E_SUCCESS) {
140 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
143 rxq->qrx_tail = hw->hw_addr +
144 I40E_QRX_TAIL(rxq->vsi->base_queue);
147 /* Init the RX tail regieter. */
148 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
154 * i40e_fdir_setup - reserve and initialize the Flow Director resources
155 * @pf: board private structure
158 i40e_fdir_setup(struct i40e_pf *pf)
160 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
161 struct i40e_vsi *vsi;
162 int err = I40E_SUCCESS;
163 char z_name[RTE_MEMZONE_NAMESIZE];
164 const struct rte_memzone *mz = NULL;
165 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
167 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
168 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
169 return I40E_NOT_SUPPORTED;
172 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
173 " num_filters_best_effort = %u.",
174 hw->func_caps.fd_filters_guaranteed,
175 hw->func_caps.fd_filters_best_effort);
177 vsi = pf->fdir.fdir_vsi;
179 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
182 /* make new FDIR VSI */
183 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
185 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
186 return I40E_ERR_NO_AVAILABLE_VSI;
188 pf->fdir.fdir_vsi = vsi;
190 /*Fdir tx queue setup*/
191 err = i40e_fdir_setup_tx_resources(pf);
193 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
197 /*Fdir rx queue setup*/
198 err = i40e_fdir_setup_rx_resources(pf);
200 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
204 err = i40e_tx_queue_init(pf->fdir.txq);
206 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
210 /* need switch on before dev start*/
211 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
213 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
217 /* Init the rx queue in hardware */
218 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
220 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
224 /* switch on rx queue */
225 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
227 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
231 /* reserve memory for the fdir programming packet */
232 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
233 eth_dev->device->driver->name,
235 eth_dev->data->port_id);
236 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
238 PMD_DRV_LOG(ERR, "Cannot init memzone for "
239 "flow director program packet.");
240 err = I40E_ERR_NO_MEMORY;
243 pf->fdir.prg_pkt = mz->addr;
244 pf->fdir.dma_addr = mz->iova;
246 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
247 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
252 i40e_dev_rx_queue_release(pf->fdir.rxq);
255 i40e_dev_tx_queue_release(pf->fdir.txq);
258 i40e_vsi_release(vsi);
259 pf->fdir.fdir_vsi = NULL;
264 * i40e_fdir_teardown - release the Flow Director resources
265 * @pf: board private structure
268 i40e_fdir_teardown(struct i40e_pf *pf)
270 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
271 struct i40e_vsi *vsi;
273 vsi = pf->fdir.fdir_vsi;
276 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
278 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
279 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
281 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
282 i40e_dev_rx_queue_release(pf->fdir.rxq);
284 i40e_dev_tx_queue_release(pf->fdir.txq);
286 i40e_vsi_release(vsi);
287 pf->fdir.fdir_vsi = NULL;
290 /* check whether the flow director table in empty */
292 i40e_fdir_empty(struct i40e_hw *hw)
294 uint32_t guarant_cnt, best_cnt;
296 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
297 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
298 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
299 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
300 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
301 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
302 if (best_cnt + guarant_cnt > 0)
309 * Initialize the configuration about bytes stream extracted as flexible payload
313 i40e_init_flx_pld(struct i40e_pf *pf)
315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
321 * Define the bytes stream extracted as flexible payload in
322 * field vector. By default, select 8 words from the beginning
323 * of payload as flexible payload.
325 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
326 index = i * I40E_MAX_FLXPLD_FIED;
327 pf->fdir.flex_set[index].src_offset = 0;
328 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
329 pf->fdir.flex_set[index].dst_offset = 0;
330 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
332 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
334 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
337 /* initialize the masks */
338 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
339 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
340 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
342 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
344 pf->fdir.flex_mask[pctype].word_mask = 0;
345 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
346 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
347 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
348 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
349 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
354 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
355 if ((flex_pit2).src_offset < \
356 (flex_pit1).src_offset + (flex_pit1).size) { \
357 PMD_DRV_LOG(ERR, "src_offset should be not" \
358 " less than than previous offset" \
359 " + previous FSIZE."); \
365 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
366 * and the flex_pit will be sorted by it's src_offset value
368 static inline uint16_t
369 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
370 struct i40e_fdir_flex_pit *flex_pit)
372 uint16_t src_tmp, size, num = 0;
373 uint16_t i, k, j = 0;
375 while (j < I40E_FDIR_MAX_FLEX_LEN) {
377 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
378 if (src_offset[j + 1] == src_offset[j] + 1)
383 src_tmp = src_offset[j] + 1 - size;
384 /* the flex_pit need to be sort by src_offset */
385 for (i = 0; i < num; i++) {
386 if (src_tmp < flex_pit[i].src_offset)
389 /* if insert required, move backward */
390 for (k = num; k > i; k--)
391 flex_pit[k] = flex_pit[k - 1];
393 flex_pit[i].dst_offset = j + 1 - size;
394 flex_pit[i].src_offset = src_tmp;
395 flex_pit[i].size = size;
402 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
404 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
406 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
409 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
410 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
411 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
416 memset(flex_pit, 0, sizeof(flex_pit));
417 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
418 if (num > I40E_MAX_FLXPLD_FIED) {
419 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
422 for (i = 0; i < num; i++) {
423 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
424 flex_pit[i].src_offset & 0x01) {
425 PMD_DRV_LOG(ERR, "flexpayload should be measured"
430 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
436 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
437 * arguments are valid
440 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
441 const struct rte_eth_fdir_flex_conf *conf)
443 const struct rte_eth_flex_payload_cfg *flex_cfg;
444 const struct rte_eth_fdir_flex_mask *flex_mask;
449 enum i40e_filter_pctype pctype;
452 PMD_DRV_LOG(INFO, "NULL pointer.");
455 /* check flexible payload setting configuration */
456 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
457 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
460 for (i = 0; i < conf->nb_payloads; i++) {
461 flex_cfg = &conf->flex_set[i];
462 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
463 PMD_DRV_LOG(ERR, "invalid payload type.");
466 ret = i40e_check_fdir_flex_payload(flex_cfg);
468 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
473 /* check flex mask setting configuration */
474 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
475 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
478 for (i = 0; i < conf->nb_flexmasks; i++) {
479 flex_mask = &conf->flex_mask[i];
480 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
481 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
482 PMD_DRV_LOG(WARNING, "invalid flow type.");
486 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
487 mask_tmp = I40E_WORD(flex_mask->mask[j],
488 flex_mask->mask[j + 1]);
489 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
491 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
492 PMD_DRV_LOG(ERR, " exceed maximal"
493 " number of bitmasks.");
503 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
504 * @pf: board private structure
505 * @cfg: the rule how bytes stream is extracted as flexible payload
508 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
509 const struct rte_eth_flex_payload_cfg *cfg)
511 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
512 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
513 uint32_t flx_pit, flx_ort;
514 uint16_t num, min_next_off; /* in words */
515 uint8_t field_idx = 0;
516 uint8_t layer_idx = 0;
519 if (cfg->type == RTE_ETH_L2_PAYLOAD)
520 layer_idx = I40E_FLXPLD_L2_IDX;
521 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
522 layer_idx = I40E_FLXPLD_L3_IDX;
523 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
524 layer_idx = I40E_FLXPLD_L4_IDX;
526 memset(flex_pit, 0, sizeof(flex_pit));
527 num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
531 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
532 (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
533 (layer_idx * I40E_MAX_FLXPLD_FIED);
534 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
537 for (i = 0; i < num; i++) {
538 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
539 /* record the info in fdir structure */
540 pf->fdir.flex_set[field_idx].src_offset =
541 flex_pit[i].src_offset / sizeof(uint16_t);
542 pf->fdir.flex_set[field_idx].size =
543 flex_pit[i].size / sizeof(uint16_t);
544 pf->fdir.flex_set[field_idx].dst_offset =
545 flex_pit[i].dst_offset / sizeof(uint16_t);
546 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
547 pf->fdir.flex_set[field_idx].size,
548 pf->fdir.flex_set[field_idx].dst_offset);
550 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
552 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
553 pf->fdir.flex_set[field_idx].size;
555 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
556 /* set the non-used register obeying register's constrain */
557 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
558 NONUSE_FLX_PIT_DEST_OFF);
560 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
567 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
568 * @pf: board private structure
569 * @pctype: packet classify type
570 * @flex_masks: mask for flexible payload
573 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
574 enum i40e_filter_pctype pctype,
575 const struct rte_eth_fdir_flex_mask *mask_cfg)
577 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
578 struct i40e_fdir_flex_mask *flex_mask;
579 uint32_t flxinset, fd_mask;
581 uint8_t i, nb_bitmask = 0;
583 flex_mask = &pf->fdir.flex_mask[pctype];
584 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
585 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
586 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
587 if (mask_tmp != 0x0) {
588 flex_mask->word_mask |=
589 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
590 if (mask_tmp != UINT16_MAX) {
592 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
593 flex_mask->bitmask[nb_bitmask].offset =
594 i / sizeof(uint16_t);
599 /* write mask to hw */
600 flxinset = (flex_mask->word_mask <<
601 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
602 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
603 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
605 for (i = 0; i < nb_bitmask; i++) {
606 fd_mask = (flex_mask->bitmask[i].mask <<
607 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
608 I40E_PRTQF_FD_MSK_MASK_MASK;
609 fd_mask |= ((flex_mask->bitmask[i].offset +
610 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
611 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
612 I40E_PRTQF_FD_MSK_OFFSET_MASK;
613 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
618 * Enable/disable flow director RX processing in vector routines.
621 i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on)
625 for (i = 0; i < dev->data->nb_rx_queues; i++) {
626 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
629 rxq->fdir_enabled = on;
631 PMD_DRV_LOG(DEBUG, "Flow Director processing on RX set to %d", on);
635 * Configure flow director related setting
638 i40e_fdir_configure(struct rte_eth_dev *dev)
640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
641 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
642 struct rte_eth_fdir_flex_conf *conf;
643 enum i40e_filter_pctype pctype;
649 * configuration need to be done before
650 * flow director filters are added
651 * If filters exist, flush them.
653 if (i40e_fdir_empty(hw) < 0) {
654 ret = i40e_fdir_flush(dev);
656 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
661 /* enable FDIR filter */
662 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
663 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
664 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
666 i40e_init_flx_pld(pf); /* set flex config to default value */
668 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
669 ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
671 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
675 if (!pf->support_multi_driver) {
676 /* configure flex payload */
677 for (i = 0; i < conf->nb_payloads; i++)
678 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
679 /* configure flex mask*/
680 for (i = 0; i < conf->nb_flexmasks; i++) {
681 if (hw->mac.type == I40E_MAC_X722) {
682 /* get pctype value in fd pctype register */
683 pctype = (enum i40e_filter_pctype)
685 I40E_GLQF_FD_PCTYPES(
686 (int)i40e_flowtype_to_pctype(
688 conf->flex_mask[i].flow_type)));
690 pctype = i40e_flowtype_to_pctype(pf->adapter,
691 conf->flex_mask[i].flow_type);
694 i40e_set_flex_mask_on_pctype(pf, pctype,
695 &conf->flex_mask[i]);
698 PMD_DRV_LOG(ERR, "Not support flexible payload.");
701 /* Enable FDIR processing in RX routines */
702 i40e_fdir_rx_proc_enable(dev, 1);
708 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
709 unsigned char *raw_pkt,
712 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
713 uint16_t *ether_type;
714 uint8_t len = 2 * sizeof(struct rte_ether_addr);
715 struct rte_ipv4_hdr *ip;
716 struct rte_ipv6_hdr *ip6;
717 static const uint8_t next_proto[] = {
718 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
719 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
720 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
721 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
722 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
723 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
724 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
725 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
726 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
727 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
730 raw_pkt += 2 * sizeof(struct rte_ether_addr);
731 if (vlan && fdir_input->flow_ext.vlan_tci) {
732 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
733 rte_memcpy(raw_pkt + sizeof(uint16_t),
734 &fdir_input->flow_ext.vlan_tci,
736 raw_pkt += sizeof(vlan_frame);
737 len += sizeof(vlan_frame);
739 ether_type = (uint16_t *)raw_pkt;
740 raw_pkt += sizeof(uint16_t);
741 len += sizeof(uint16_t);
743 switch (fdir_input->flow_type) {
744 case RTE_ETH_FLOW_L2_PAYLOAD:
745 *ether_type = fdir_input->flow.l2_flow.ether_type;
747 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
748 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
749 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
750 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
751 case RTE_ETH_FLOW_FRAG_IPV4:
752 ip = (struct rte_ipv4_hdr *)raw_pkt;
754 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
755 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
756 /* set len to by default */
757 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
758 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
759 fdir_input->flow.ip4_flow.proto :
760 next_proto[fdir_input->flow_type];
761 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
762 fdir_input->flow.ip4_flow.ttl :
763 I40E_FDIR_IP_DEFAULT_TTL;
764 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
766 * The source and destination fields in the transmitted packet
767 * need to be presented in a reversed order with respect
768 * to the expected received packets.
770 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
771 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
772 len += sizeof(struct rte_ipv4_hdr);
774 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
775 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
776 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
777 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
778 case RTE_ETH_FLOW_FRAG_IPV6:
779 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
781 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
783 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
784 (fdir_input->flow.ipv6_flow.tc <<
785 I40E_FDIR_IPv6_TC_OFFSET));
787 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
788 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
789 fdir_input->flow.ipv6_flow.proto :
790 next_proto[fdir_input->flow_type];
791 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
792 fdir_input->flow.ipv6_flow.hop_limits :
793 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
795 * The source and destination fields in the transmitted packet
796 * need to be presented in a reversed order with respect
797 * to the expected received packets.
799 rte_memcpy(&(ip6->src_addr),
800 &(fdir_input->flow.ipv6_flow.dst_ip),
802 rte_memcpy(&(ip6->dst_addr),
803 &(fdir_input->flow.ipv6_flow.src_ip),
805 len += sizeof(struct rte_ipv6_hdr);
808 PMD_DRV_LOG(ERR, "unknown flow type %u.",
809 fdir_input->flow_type);
817 * i40e_fdir_construct_pkt - construct packet based on fields in input
818 * @pf: board private structure
819 * @fdir_input: input set of the flow director entry
820 * @raw_pkt: a packet to be constructed
823 i40e_fdir_construct_pkt(struct i40e_pf *pf,
824 const struct rte_eth_fdir_input *fdir_input,
825 unsigned char *raw_pkt)
827 unsigned char *payload, *ptr;
828 struct rte_udp_hdr *udp;
829 struct rte_tcp_hdr *tcp;
830 struct rte_sctp_hdr *sctp;
831 uint8_t size, dst = 0;
832 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
835 /* fill the ethernet and IP head */
836 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
837 !!fdir_input->flow_ext.vlan_tci);
841 /* fill the L4 head */
842 switch (fdir_input->flow_type) {
843 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
844 udp = (struct rte_udp_hdr *)(raw_pkt + len);
845 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
847 * The source and destination fields in the transmitted packet
848 * need to be presented in a reversed order with respect
849 * to the expected received packets.
851 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
852 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
853 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
856 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
857 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
858 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
860 * The source and destination fields in the transmitted packet
861 * need to be presented in a reversed order with respect
862 * to the expected received packets.
864 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
865 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
866 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
869 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
870 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
871 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
873 * The source and destination fields in the transmitted packet
874 * need to be presented in a reversed order with respect
875 * to the expected received packets.
877 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
878 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
879 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
882 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
883 case RTE_ETH_FLOW_FRAG_IPV4:
884 payload = raw_pkt + len;
885 set_idx = I40E_FLXPLD_L3_IDX;
888 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
889 udp = (struct rte_udp_hdr *)(raw_pkt + len);
890 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
892 * The source and destination fields in the transmitted packet
893 * need to be presented in a reversed order with respect
894 * to the expected received packets.
896 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
897 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
898 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
901 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
902 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
903 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
905 * The source and destination fields in the transmitted packet
906 * need to be presented in a reversed order with respect
907 * to the expected received packets.
909 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
910 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
911 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
914 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
915 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
916 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
918 * The source and destination fields in the transmitted packet
919 * need to be presented in a reversed order with respect
920 * to the expected received packets.
922 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
923 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
924 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
927 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
928 case RTE_ETH_FLOW_FRAG_IPV6:
929 payload = raw_pkt + len;
930 set_idx = I40E_FLXPLD_L3_IDX;
932 case RTE_ETH_FLOW_L2_PAYLOAD:
933 payload = raw_pkt + len;
935 * ARP packet is a special case on which the payload
936 * starts after the whole ARP header
938 if (fdir_input->flow.l2_flow.ether_type ==
939 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
940 payload += sizeof(struct rte_arp_hdr);
941 set_idx = I40E_FLXPLD_L2_IDX;
944 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
948 /* fill the flexbytes to payload */
949 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
950 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
951 size = pf->fdir.flex_set[pit_idx].size;
954 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
956 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
958 &fdir_input->flow_ext.flexbytes[dst],
959 size * sizeof(uint16_t));
965 static struct i40e_customized_pctype *
966 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
968 struct i40e_customized_pctype *cus_pctype;
969 enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
971 for (; i < I40E_CUSTOMIZED_MAX; i++) {
972 cus_pctype = &pf->customized_pctype[i];
973 if (pctype == cus_pctype->pctype)
980 fill_ip6_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
981 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
983 struct rte_ipv6_hdr *ip6;
985 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
987 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
988 ip6->vtc_flow = rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
989 (fdir_input->flow.ipv6_flow.tc << I40E_FDIR_IPv6_TC_OFFSET));
990 ip6->payload_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
991 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
992 fdir_input->flow.ipv6_flow.proto : next_proto;
993 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
994 fdir_input->flow.ipv6_flow.hop_limits :
995 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
997 * The source and destination fields in the transmitted packet
998 * need to be presented in a reversed order with respect
999 * to the expected received packets.
1001 rte_memcpy(&ip6->src_addr, &fdir_input->flow.ipv6_flow.dst_ip,
1003 rte_memcpy(&ip6->dst_addr, &fdir_input->flow.ipv6_flow.src_ip,
1005 len += sizeof(struct rte_ipv6_hdr);
1011 fill_ip4_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
1012 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
1014 struct rte_ipv4_hdr *ip4;
1016 ip4 = (struct rte_ipv4_hdr *)raw_pkt;
1018 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
1019 ip4->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1020 /* set len to by default */
1021 ip4->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
1022 ip4->time_to_live = fdir_input->flow.ip4_flow.ttl ?
1023 fdir_input->flow.ip4_flow.ttl :
1024 I40E_FDIR_IP_DEFAULT_TTL;
1025 ip4->type_of_service = fdir_input->flow.ip4_flow.tos;
1026 ip4->next_proto_id = fdir_input->flow.ip4_flow.proto ?
1027 fdir_input->flow.ip4_flow.proto : next_proto;
1029 * The source and destination fields in the transmitted packet
1030 * need to be presented in a reversed order with respect
1031 * to the expected received packets.
1033 ip4->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1034 ip4->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1035 len += sizeof(struct rte_ipv4_hdr);
1041 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
1042 const struct i40e_fdir_input *fdir_input,
1043 unsigned char *raw_pkt,
1046 struct i40e_customized_pctype *cus_pctype = NULL;
1047 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
1048 uint16_t *ether_type;
1049 uint8_t len = 2 * sizeof(struct rte_ether_addr);
1050 uint8_t pctype = fdir_input->pctype;
1051 bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
1052 static const uint8_t next_proto[] = {
1053 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
1054 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
1055 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
1056 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
1057 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
1058 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
1059 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
1060 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
1061 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
1062 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
1065 raw_pkt += 2 * sizeof(struct rte_ether_addr);
1066 if (vlan && fdir_input->flow_ext.vlan_tci) {
1067 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
1068 rte_memcpy(raw_pkt + sizeof(uint16_t),
1069 &fdir_input->flow_ext.vlan_tci,
1071 raw_pkt += sizeof(vlan_frame);
1072 len += sizeof(vlan_frame);
1074 ether_type = (uint16_t *)raw_pkt;
1075 raw_pkt += sizeof(uint16_t);
1076 len += sizeof(uint16_t);
1078 if (is_customized_pctype) {
1079 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1081 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1082 fdir_input->pctype);
1087 if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1088 *ether_type = fdir_input->flow.l2_flow.ether_type;
1089 else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
1090 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
1091 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
1092 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1093 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
1094 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1095 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1096 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1097 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1098 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6 ||
1099 is_customized_pctype) {
1100 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
1101 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
1102 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
1103 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1104 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1105 len = fill_ip4_head(fdir_input, raw_pkt,
1106 next_proto[pctype], len, ether_type);
1107 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1108 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1109 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1110 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1111 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1112 len = fill_ip6_head(fdir_input, raw_pkt,
1113 next_proto[pctype], len,
1115 } else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1116 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1117 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1118 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1119 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
1121 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3) {
1122 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_L2TP,
1124 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1125 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_ESP,
1127 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1128 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
1130 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1131 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
1133 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6)
1134 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_ESP,
1136 else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP)
1137 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_UDP,
1139 else if (cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3)
1140 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_L2TP,
1143 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1151 * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1152 * @pf: board private structure
1153 * @fdir_input: input set of the flow director entry
1154 * @raw_pkt: a packet to be constructed
1157 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1158 const struct i40e_fdir_input *fdir_input,
1159 unsigned char *raw_pkt)
1161 unsigned char *payload = NULL;
1163 struct rte_udp_hdr *udp;
1164 struct rte_tcp_hdr *tcp;
1165 struct rte_sctp_hdr *sctp;
1166 struct rte_flow_item_gtp *gtp;
1167 struct rte_ipv4_hdr *gtp_ipv4;
1168 struct rte_ipv6_hdr *gtp_ipv6;
1169 struct rte_flow_item_l2tpv3oip *l2tpv3oip;
1170 struct rte_flow_item_esp *esp;
1171 struct rte_ipv4_hdr *esp_ipv4;
1172 struct rte_ipv6_hdr *esp_ipv6;
1174 uint8_t size, dst = 0;
1175 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1177 uint8_t pctype = fdir_input->pctype;
1178 struct i40e_customized_pctype *cus_pctype;
1180 /* raw pcket template - just copy contents of the raw packet */
1181 if (fdir_input->flow_ext.pkt_template) {
1182 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
1183 fdir_input->flow.raw_flow.length);
1187 /* fill the ethernet and IP head */
1188 len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
1189 !!fdir_input->flow_ext.vlan_tci);
1193 /* fill the L4 head */
1194 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
1195 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1196 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1198 * The source and destination fields in the transmitted packet
1199 * need to be presented in a reversed order with respect
1200 * to the expected received packets.
1202 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1203 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1204 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1205 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
1206 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1207 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1209 * The source and destination fields in the transmitted packet
1210 * need to be presented in a reversed order with respect
1211 * to the expected received packets.
1213 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1214 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1215 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1216 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
1217 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1218 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1220 * The source and destination fields in the transmitted packet
1221 * need to be presented in a reversed order with respect
1222 * to the expected received packets.
1224 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1225 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1226 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1227 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1228 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1229 payload = raw_pkt + len;
1230 set_idx = I40E_FLXPLD_L3_IDX;
1231 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1232 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1233 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1235 * The source and destination fields in the transmitted packet
1236 * need to be presented in a reversed order with respect
1237 * to the expected received packets.
1239 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1240 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1241 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1242 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1243 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1244 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1246 * The source and destination fields in the transmitted packet
1247 * need to be presented in a reversed order with respect
1248 * to the expected received packets.
1250 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1251 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1252 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1253 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1254 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1255 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1257 * The source and destination fields in the transmitted packet
1258 * need to be presented in a reversed order with respect
1259 * to the expected received packets.
1261 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1262 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1263 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1264 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1265 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1266 payload = raw_pkt + len;
1267 set_idx = I40E_FLXPLD_L3_IDX;
1268 } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1269 payload = raw_pkt + len;
1271 * ARP packet is a special case on which the payload
1272 * starts after the whole ARP header
1274 if (fdir_input->flow.l2_flow.ether_type ==
1275 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
1276 payload += sizeof(struct rte_arp_hdr);
1277 set_idx = I40E_FLXPLD_L2_IDX;
1278 } else if (fdir_input->flow_ext.customized_pctype) {
1279 /* If customized pctype is used */
1280 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1281 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1282 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1283 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1284 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1285 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1287 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1289 gtp = (struct rte_flow_item_gtp *)
1290 ((unsigned char *)udp +
1291 sizeof(struct rte_udp_hdr));
1293 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1294 gtp->teid = fdir_input->flow.gtp_flow.teid;
1295 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1297 /* GTP-C message type is not supported. */
1298 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1300 rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1301 gtp->v_pt_rsv_flags =
1302 I40E_FDIR_GTP_VER_FLAG_0X32;
1305 rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1306 gtp->v_pt_rsv_flags =
1307 I40E_FDIR_GTP_VER_FLAG_0X30;
1310 if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1311 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1312 gtp_ipv4 = (struct rte_ipv4_hdr *)
1313 ((unsigned char *)gtp +
1314 sizeof(struct rte_flow_item_gtp));
1315 gtp_ipv4->version_ihl =
1316 I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1317 gtp_ipv4->next_proto_id = IPPROTO_IP;
1318 gtp_ipv4->total_length =
1320 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1321 payload = (unsigned char *)gtp_ipv4 +
1322 sizeof(struct rte_ipv4_hdr);
1323 } else if (cus_pctype->index ==
1324 I40E_CUSTOMIZED_GTPU_IPV6) {
1325 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1326 gtp_ipv6 = (struct rte_ipv6_hdr *)
1327 ((unsigned char *)gtp +
1328 sizeof(struct rte_flow_item_gtp));
1329 gtp_ipv6->vtc_flow =
1331 I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1332 (0 << I40E_FDIR_IPv6_TC_OFFSET));
1333 gtp_ipv6->proto = IPPROTO_NONE;
1334 gtp_ipv6->payload_len =
1336 I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1337 gtp_ipv6->hop_limits =
1338 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1339 payload = (unsigned char *)gtp_ipv6 +
1340 sizeof(struct rte_ipv6_hdr);
1342 payload = (unsigned char *)gtp +
1343 sizeof(struct rte_flow_item_gtp);
1344 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3 ||
1345 cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3) {
1346 l2tpv3oip = (struct rte_flow_item_l2tpv3oip *)(raw_pkt
1349 if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3)
1350 l2tpv3oip->session_id =
1351 fdir_input->flow.ip4_l2tpv3oip_flow.session_id;
1353 l2tpv3oip->session_id =
1354 fdir_input->flow.ip6_l2tpv3oip_flow.session_id;
1355 payload = (unsigned char *)l2tpv3oip +
1356 sizeof(struct rte_flow_item_l2tpv3oip);
1357 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4 ||
1358 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6 ||
1359 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP ||
1360 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1361 if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1362 esp_ipv4 = (struct rte_ipv4_hdr *)
1364 esp = (struct rte_flow_item_esp *)esp_ipv4;
1366 fdir_input->flow.esp_ipv4_flow.spi;
1367 payload = (unsigned char *)esp +
1368 sizeof(struct rte_esp_hdr);
1369 len += sizeof(struct rte_esp_hdr);
1370 } else if (cus_pctype->index ==
1371 I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1372 esp_ipv4 = (struct rte_ipv4_hdr *)
1374 udp = (struct rte_udp_hdr *)esp_ipv4;
1375 udp->dst_port = rte_cpu_to_be_16
1376 (I40E_FDIR_ESP_DST_PORT);
1378 udp->dgram_len = rte_cpu_to_be_16
1379 (I40E_FDIR_UDP_DEFAULT_LEN);
1380 esp = (struct rte_flow_item_esp *)
1381 ((unsigned char *)esp_ipv4 +
1382 sizeof(struct rte_udp_hdr));
1384 fdir_input->flow.esp_ipv4_udp_flow.spi;
1385 payload = (unsigned char *)esp +
1386 sizeof(struct rte_esp_hdr);
1387 len += sizeof(struct rte_udp_hdr) +
1388 sizeof(struct rte_esp_hdr);
1389 } else if (cus_pctype->index ==
1390 I40E_CUSTOMIZED_ESP_IPV6) {
1391 esp_ipv6 = (struct rte_ipv6_hdr *)
1393 esp = (struct rte_flow_item_esp *)esp_ipv6;
1395 fdir_input->flow.esp_ipv6_flow.spi;
1396 payload = (unsigned char *)esp +
1397 sizeof(struct rte_esp_hdr);
1398 len += sizeof(struct rte_esp_hdr);
1399 } else if (cus_pctype->index ==
1400 I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1401 esp_ipv6 = (struct rte_ipv6_hdr *)
1403 udp = (struct rte_udp_hdr *)esp_ipv6;
1404 udp->dst_port = rte_cpu_to_be_16
1405 (I40E_FDIR_ESP_DST_PORT);
1407 udp->dgram_len = rte_cpu_to_be_16
1408 (I40E_FDIR_UDP_DEFAULT_LEN);
1409 esp = (struct rte_flow_item_esp *)
1410 ((unsigned char *)esp_ipv6 +
1411 sizeof(struct rte_udp_hdr));
1413 fdir_input->flow.esp_ipv6_udp_flow.spi;
1414 payload = (unsigned char *)esp +
1415 sizeof(struct rte_esp_hdr);
1416 len += sizeof(struct rte_udp_hdr) +
1417 sizeof(struct rte_esp_hdr);
1421 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1425 /* fill the flexbytes to payload */
1426 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1427 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1428 size = pf->fdir.flex_set[pit_idx].size;
1431 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1433 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1434 (void)rte_memcpy(ptr,
1435 &fdir_input->flow_ext.flexbytes[dst],
1436 size * sizeof(uint16_t));
1442 /* Construct the tx flags */
1443 static inline uint64_t
1444 i40e_build_ctob(uint32_t td_cmd,
1449 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1450 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
1451 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1452 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1453 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
1457 * check the programming status descriptor in rx queue.
1458 * done after Programming Flow Director is programmed on
1462 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1464 volatile union i40e_rx_desc *rxdp;
1471 rxdp = &rxq->rx_ring[rxq->rx_tail];
1472 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1473 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1474 >> I40E_RXD_QW1_STATUS_SHIFT;
1476 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1477 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1478 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1479 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1481 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1482 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1484 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1485 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1486 if (error == (0x1 <<
1487 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1488 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1489 " (FD_ID %u): programming status"
1491 rxdp->wb.qword0.hi_dword.fd_id);
1493 } else if (error == (0x1 <<
1494 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1495 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1496 " (FD_ID %u): programming status"
1498 rxdp->wb.qword0.hi_dword.fd_id);
1501 PMD_DRV_LOG(ERR, "invalid programming status"
1502 " reported, error = %u.", error);
1504 PMD_DRV_LOG(INFO, "unknown programming status"
1505 " reported, len = %d, id = %u.", len, id);
1506 rxdp->wb.qword1.status_error_len = 0;
1508 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1510 if (rxq->rx_tail == 0)
1511 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1513 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1520 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1521 struct i40e_fdir_filter *filter)
1523 rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1524 if (input->input.flow_ext.pkt_template) {
1525 filter->fdir.input.flow.raw_flow.packet = NULL;
1526 filter->fdir.input.flow.raw_flow.length =
1527 rte_hash_crc(input->input.flow.raw_flow.packet,
1528 input->input.flow.raw_flow.length,
1529 input->input.flow.raw_flow.pctype);
1534 /* Check if there exists the flow director filter */
1535 static struct i40e_fdir_filter *
1536 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1537 const struct i40e_fdir_input *input)
1541 if (input->flow_ext.pkt_template)
1542 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1543 (const void *)input,
1544 input->flow.raw_flow.length);
1546 ret = rte_hash_lookup(fdir_info->hash_table,
1547 (const void *)input);
1551 return fdir_info->hash_map[ret];
1554 /* Add a flow director filter into the SW list */
1556 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1558 struct i40e_fdir_info *fdir_info = &pf->fdir;
1561 if (filter->fdir.input.flow_ext.pkt_template)
1562 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1563 &filter->fdir.input,
1564 filter->fdir.input.flow.raw_flow.length);
1566 ret = rte_hash_add_key(fdir_info->hash_table,
1567 &filter->fdir.input);
1570 "Failed to insert fdir filter to hash table %d!",
1574 fdir_info->hash_map[ret] = filter;
1576 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1581 /* Delete a flow director filter from the SW list */
1583 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1585 struct i40e_fdir_info *fdir_info = &pf->fdir;
1586 struct i40e_fdir_filter *filter;
1589 if (input->flow_ext.pkt_template)
1590 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1592 input->flow.raw_flow.length);
1594 ret = rte_hash_del_key(fdir_info->hash_table, input);
1597 "Failed to delete fdir filter to hash table %d!",
1601 filter = fdir_info->hash_map[ret];
1602 fdir_info->hash_map[ret] = NULL;
1604 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1611 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1612 * @pf: board private structure
1613 * @filter: fdir filter entry
1614 * @add: 0 - delete, 1 - add
1617 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1618 const struct rte_eth_fdir_filter *filter,
1621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1622 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1623 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1624 enum i40e_filter_pctype pctype;
1627 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1628 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1629 " check the mode in fdir_conf.");
1633 pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1634 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1635 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1638 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1639 PMD_DRV_LOG(ERR, "Invalid queue ID");
1642 if (filter->input.flow_ext.is_vf &&
1643 filter->input.flow_ext.dst_id >= pf->vf_num) {
1644 PMD_DRV_LOG(ERR, "Invalid VF ID");
1648 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1650 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1652 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1656 if (hw->mac.type == I40E_MAC_X722) {
1657 /* get translated pctype value in fd pctype register */
1658 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1659 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1662 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1664 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1673 * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1674 * @pf: board private structure
1675 * @filter: fdir filter entry
1676 * @add: 0 - delete, 1 - add
1679 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1680 const struct i40e_fdir_filter_conf *filter,
1683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1685 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1686 enum i40e_filter_pctype pctype;
1687 struct i40e_fdir_info *fdir_info = &pf->fdir;
1688 struct i40e_fdir_filter *fdir_filter, *node;
1689 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1692 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1693 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1697 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1698 PMD_DRV_LOG(ERR, "Invalid queue ID");
1701 if (filter->input.flow_ext.is_vf &&
1702 filter->input.flow_ext.dst_id >= pf->vf_num) {
1703 PMD_DRV_LOG(ERR, "Invalid VF ID");
1706 if (filter->input.flow_ext.pkt_template) {
1707 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1708 !filter->input.flow.raw_flow.packet) {
1709 PMD_DRV_LOG(ERR, "Invalid raw packet template"
1710 " flow filter parameters!");
1713 pctype = filter->input.flow.raw_flow.pctype;
1715 pctype = filter->input.pctype;
1718 /* Check if there is the filter in SW list */
1719 memset(&check_filter, 0, sizeof(check_filter));
1720 i40e_fdir_filter_convert(filter, &check_filter);
1721 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1724 "Conflict with existing flow director rules!");
1728 if (!add && !node) {
1730 "There's no corresponding flow firector filter!");
1734 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1736 ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1738 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1742 if (hw->mac.type == I40E_MAC_X722) {
1743 /* get translated pctype value in fd pctype register */
1744 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1745 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1748 ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1750 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1756 fdir_filter = rte_zmalloc("fdir_filter",
1757 sizeof(*fdir_filter), 0);
1758 if (fdir_filter == NULL) {
1759 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
1763 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1764 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1766 rte_free(fdir_filter);
1768 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1775 * i40e_fdir_filter_programming - Program a flow director filter rule.
1776 * Is done by Flow Director Programming Descriptor followed by packet
1777 * structure that contains the filter fields need to match.
1778 * @pf: board private structure
1780 * @filter: fdir filter entry
1781 * @add: 0 - delete, 1 - add
1784 i40e_fdir_filter_programming(struct i40e_pf *pf,
1785 enum i40e_filter_pctype pctype,
1786 const struct rte_eth_fdir_filter *filter,
1789 struct i40e_tx_queue *txq = pf->fdir.txq;
1790 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1791 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1792 volatile struct i40e_tx_desc *txdp;
1793 volatile struct i40e_filter_program_desc *fdirdp;
1798 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1799 fdirdp = (volatile struct i40e_filter_program_desc *)
1800 (&(txq->tx_ring[txq->tx_tail]));
1802 fdirdp->qindex_flex_ptype_vsi =
1803 rte_cpu_to_le_32((fdir_action->rx_queue <<
1804 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1805 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1807 fdirdp->qindex_flex_ptype_vsi |=
1808 rte_cpu_to_le_32((fdir_action->flex_off <<
1809 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1810 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1812 fdirdp->qindex_flex_ptype_vsi |=
1813 rte_cpu_to_le_32((pctype <<
1814 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1815 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1817 if (filter->input.flow_ext.is_vf)
1818 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1820 /* Use LAN VSI Id by default */
1821 vsi_id = pf->main_vsi->vsi_id;
1822 fdirdp->qindex_flex_ptype_vsi |=
1823 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1824 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1825 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1827 fdirdp->dtype_cmd_cntindex =
1828 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1831 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1832 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1833 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1835 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1836 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1837 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1839 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1840 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1841 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1842 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1843 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1844 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1846 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1847 " unsupported fdir behavior.");
1851 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1852 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1853 I40E_TXD_FLTR_QW1_DEST_MASK);
1855 fdirdp->dtype_cmd_cntindex |=
1856 rte_cpu_to_le_32((fdir_action->report_status<<
1857 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1858 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1860 fdirdp->dtype_cmd_cntindex |=
1861 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1862 fdirdp->dtype_cmd_cntindex |=
1864 ((uint32_t)pf->fdir.match_counter_index <<
1865 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1866 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1868 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1870 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1871 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1872 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1873 td_cmd = I40E_TX_DESC_CMD_EOP |
1874 I40E_TX_DESC_CMD_RS |
1875 I40E_TX_DESC_CMD_DUMMY;
1877 txdp->cmd_type_offset_bsz =
1878 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1880 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1881 if (txq->tx_tail >= txq->nb_tx_desc)
1883 /* Update the tx tail register */
1885 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1886 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1887 if ((txdp->cmd_type_offset_bsz &
1888 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1889 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1893 if (i >= I40E_FDIR_MAX_WAIT_US) {
1894 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1895 " time out to get DD on tx queue.");
1898 /* totally delay 10 ms to check programming status*/
1899 for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1900 if (i40e_check_fdir_programming_status(rxq) >= 0)
1905 "Failed to program FDIR filter: programming status reported.");
1910 * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1911 * Is done by Flow Director Programming Descriptor followed by packet
1912 * structure that contains the filter fields need to match.
1913 * @pf: board private structure
1915 * @filter: fdir filter entry
1916 * @add: 0 - delete, 1 - add
1919 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1920 enum i40e_filter_pctype pctype,
1921 const struct i40e_fdir_filter_conf *filter,
1924 struct i40e_tx_queue *txq = pf->fdir.txq;
1925 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1926 const struct i40e_fdir_action *fdir_action = &filter->action;
1927 volatile struct i40e_tx_desc *txdp;
1928 volatile struct i40e_filter_program_desc *fdirdp;
1933 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1934 fdirdp = (volatile struct i40e_filter_program_desc *)
1935 (&txq->tx_ring[txq->tx_tail]);
1937 fdirdp->qindex_flex_ptype_vsi =
1938 rte_cpu_to_le_32((fdir_action->rx_queue <<
1939 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1940 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1942 fdirdp->qindex_flex_ptype_vsi |=
1943 rte_cpu_to_le_32((fdir_action->flex_off <<
1944 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1945 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1947 fdirdp->qindex_flex_ptype_vsi |=
1948 rte_cpu_to_le_32((pctype <<
1949 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1950 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1952 if (filter->input.flow_ext.is_vf)
1953 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1955 /* Use LAN VSI Id by default */
1956 vsi_id = pf->main_vsi->vsi_id;
1957 fdirdp->qindex_flex_ptype_vsi |=
1958 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1959 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1960 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1962 fdirdp->dtype_cmd_cntindex =
1963 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1966 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1967 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1968 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1970 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1971 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1972 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1974 if (fdir_action->behavior == I40E_FDIR_REJECT)
1975 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1976 else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1977 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1978 else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1979 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1981 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1985 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1986 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1987 I40E_TXD_FLTR_QW1_DEST_MASK);
1989 fdirdp->dtype_cmd_cntindex |=
1990 rte_cpu_to_le_32((fdir_action->report_status <<
1991 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1992 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1994 fdirdp->dtype_cmd_cntindex |=
1995 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1996 fdirdp->dtype_cmd_cntindex |=
1998 ((uint32_t)pf->fdir.match_counter_index <<
1999 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2000 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
2002 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
2004 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
2005 txdp = &txq->tx_ring[txq->tx_tail + 1];
2006 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
2007 td_cmd = I40E_TX_DESC_CMD_EOP |
2008 I40E_TX_DESC_CMD_RS |
2009 I40E_TX_DESC_CMD_DUMMY;
2011 txdp->cmd_type_offset_bsz =
2012 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
2014 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
2015 if (txq->tx_tail >= txq->nb_tx_desc)
2017 /* Update the tx tail register */
2019 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2020 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
2021 if ((txdp->cmd_type_offset_bsz &
2022 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
2023 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
2027 if (i >= I40E_FDIR_MAX_WAIT_US) {
2029 "Failed to program FDIR filter: time out to get DD on tx queue.");
2032 /* totally delay 10 ms to check programming status*/
2033 rte_delay_us(I40E_FDIR_MAX_WAIT_US);
2034 if (i40e_check_fdir_programming_status(rxq) < 0) {
2036 "Failed to program FDIR filter: programming status reported.");
2044 * i40e_fdir_flush - clear all filters of Flow Director table
2045 * @pf: board private structure
2048 i40e_fdir_flush(struct rte_eth_dev *dev)
2050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2051 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2053 uint16_t guarant_cnt, best_cnt;
2056 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
2057 I40E_WRITE_FLUSH(hw);
2059 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
2060 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
2061 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
2062 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
2065 if (i >= I40E_FDIR_FLUSH_RETRY) {
2066 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
2069 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2070 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2071 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2072 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2073 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2074 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2075 if (guarant_cnt != 0 || best_cnt != 0) {
2076 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
2079 PMD_DRV_LOG(INFO, "FD table Flush success.");
2084 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
2085 struct rte_eth_flex_payload_cfg *flex_set,
2088 struct i40e_fdir_flex_pit *flex_pit;
2089 struct rte_eth_flex_payload_cfg *ptr = flex_set;
2090 uint16_t src, dst, size, j, k;
2091 uint8_t i, layer_idx;
2093 for (layer_idx = I40E_FLXPLD_L2_IDX;
2094 layer_idx <= I40E_FLXPLD_L4_IDX;
2096 if (layer_idx == I40E_FLXPLD_L2_IDX)
2097 ptr->type = RTE_ETH_L2_PAYLOAD;
2098 else if (layer_idx == I40E_FLXPLD_L3_IDX)
2099 ptr->type = RTE_ETH_L3_PAYLOAD;
2100 else if (layer_idx == I40E_FLXPLD_L4_IDX)
2101 ptr->type = RTE_ETH_L4_PAYLOAD;
2103 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
2104 flex_pit = &pf->fdir.flex_set[layer_idx *
2105 I40E_MAX_FLXPLD_FIED + i];
2106 if (flex_pit->size == 0)
2108 src = flex_pit->src_offset * sizeof(uint16_t);
2109 dst = flex_pit->dst_offset * sizeof(uint16_t);
2110 size = flex_pit->size * sizeof(uint16_t);
2111 for (j = src, k = dst; j < src + size; j++, k++)
2112 ptr->src_offset[k] = j;
2120 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
2121 struct rte_eth_fdir_flex_mask *flex_mask,
2124 struct i40e_fdir_flex_mask *mask;
2125 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
2128 uint16_t off_bytes, mask_tmp;
2130 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2131 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
2133 mask = &pf->fdir.flex_mask[i];
2134 flow_type = i40e_pctype_to_flowtype(pf->adapter,
2135 (enum i40e_filter_pctype)i);
2136 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
2139 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
2140 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
2141 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
2142 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
2144 ptr->mask[j * sizeof(uint16_t)] = 0x0;
2145 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
2148 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
2149 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
2150 mask_tmp = ~mask->bitmask[j].mask;
2151 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
2152 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
2154 ptr->flow_type = flow_type;
2161 * i40e_fdir_info_get - get information of Flow Director
2162 * @pf: ethernet device to get info from
2163 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
2164 * the flow director information.
2167 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2169 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2170 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2171 uint16_t num_flex_set = 0;
2172 uint16_t num_flex_mask = 0;
2175 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2176 fdir->mode = RTE_FDIR_MODE_PERFECT;
2178 fdir->mode = RTE_FDIR_MODE_NONE;
2181 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2183 (uint32_t)hw->func_caps.fd_filters_best_effort;
2184 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2185 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2186 for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2187 fdir->flow_types_mask[i] = 0ULL;
2188 fdir->flex_payload_unit = sizeof(uint16_t);
2189 fdir->flex_bitmask_unit = sizeof(uint16_t);
2190 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2191 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2192 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2194 i40e_fdir_info_get_flex_set(pf,
2195 fdir->flex_conf.flex_set,
2197 i40e_fdir_info_get_flex_mask(pf,
2198 fdir->flex_conf.flex_mask,
2201 fdir->flex_conf.nb_payloads = num_flex_set;
2202 fdir->flex_conf.nb_flexmasks = num_flex_mask;
2206 * i40e_fdir_stat_get - get statistics of Flow Director
2207 * @pf: ethernet device to get info from
2208 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2209 * the flow director statistics.
2212 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2214 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2215 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2218 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2220 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2221 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2223 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2224 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2228 i40e_fdir_filter_set(struct rte_eth_dev *dev,
2229 struct rte_eth_fdir_filter_info *info)
2231 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2235 PMD_DRV_LOG(ERR, "Invalid pointer");
2239 switch (info->info_type) {
2240 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
2241 ret = i40e_fdir_filter_inset_select(pf,
2242 &(info->info.input_set_conf));
2245 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
2254 * i40e_fdir_ctrl_func - deal with all operations on flow director.
2255 * @pf: board private structure
2256 * @filter_op:operation will be taken.
2257 * @arg: a pointer to specific structure corresponding to the filter_op
2260 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
2261 enum rte_filter_op filter_op,
2264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2267 if ((pf->flags & I40E_FLAG_FDIR) == 0)
2270 if (filter_op == RTE_ETH_FILTER_NOP)
2273 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2276 switch (filter_op) {
2277 case RTE_ETH_FILTER_ADD:
2278 ret = i40e_add_del_fdir_filter(dev,
2279 (struct rte_eth_fdir_filter *)arg,
2282 case RTE_ETH_FILTER_DELETE:
2283 ret = i40e_add_del_fdir_filter(dev,
2284 (struct rte_eth_fdir_filter *)arg,
2287 case RTE_ETH_FILTER_FLUSH:
2288 ret = i40e_fdir_flush(dev);
2290 case RTE_ETH_FILTER_INFO:
2291 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2293 case RTE_ETH_FILTER_SET:
2294 ret = i40e_fdir_filter_set(dev,
2295 (struct rte_eth_fdir_filter_info *)arg);
2297 case RTE_ETH_FILTER_STATS:
2298 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2301 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2308 /* Restore flow director filter */
2310 i40e_fdir_filter_restore(struct i40e_pf *pf)
2312 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2313 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2314 struct i40e_fdir_filter *f;
2315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2317 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
2318 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
2320 TAILQ_FOREACH(f, fdir_list, rules)
2321 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2323 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2325 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2326 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2328 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2329 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2331 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
2332 guarant_cnt, best_cnt);