1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
16 #include <rte_memzone.h>
17 #include <rte_malloc.h>
23 #include <rte_hash_crc.h>
25 #include "i40e_logs.h"
26 #include "base/i40e_type.h"
27 #include "base/i40e_prototype.h"
28 #include "i40e_ethdev.h"
29 #include "i40e_rxtx.h"
31 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
33 #define IPV6_ADDR_LEN 16
36 #define I40E_FDIR_PKT_LEN 512
37 #define I40E_FDIR_IP_DEFAULT_LEN 420
38 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
39 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
40 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
41 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
43 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
44 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
45 #define I40E_FDIR_UDP_DEFAULT_LEN 400
46 #define I40E_FDIR_GTP_DEFAULT_LEN 384
47 #define I40E_FDIR_INNER_IP_DEFAULT_LEN 384
48 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN 344
50 #define I40E_FDIR_GTPC_DST_PORT 2123
51 #define I40E_FDIR_GTPU_DST_PORT 2152
52 #define I40E_FDIR_GTP_VER_FLAG_0X30 0x30
53 #define I40E_FDIR_GTP_VER_FLAG_0X32 0x32
54 #define I40E_FDIR_GTP_MSG_TYPE_0X01 0x01
55 #define I40E_FDIR_GTP_MSG_TYPE_0XFF 0xFF
57 /* Wait time for fdir filter programming */
58 #define I40E_FDIR_MAX_WAIT_US 10000
60 /* Wait count and interval for fdir filter flush */
61 #define I40E_FDIR_FLUSH_RETRY 50
62 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
64 #define I40E_COUNTER_PF 2
65 /* Statistic counter index for one pf */
66 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
68 #define I40E_FDIR_FLOWS ( \
69 (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
70 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
71 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
72 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
73 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
74 (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
75 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
76 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
77 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
78 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
79 (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
81 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
82 enum i40e_filter_pctype pctype,
83 const struct rte_eth_fdir_filter *filter,
85 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
86 struct i40e_fdir_filter *filter);
87 static struct i40e_fdir_filter *
88 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
89 const struct i40e_fdir_input *input);
90 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
91 struct i40e_fdir_filter *filter);
93 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
94 enum i40e_filter_pctype pctype,
95 const struct i40e_fdir_filter_conf *filter,
99 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
101 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
102 struct i40e_hmc_obj_rxq rx_ctx;
103 int err = I40E_SUCCESS;
105 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
106 /* Init the RX queue in hardware */
107 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
109 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
110 rx_ctx.qlen = rxq->nb_rx_desc;
111 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
114 rx_ctx.dtype = i40e_header_split_none;
115 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
116 rx_ctx.rxmax = ETHER_MAX_LEN;
117 rx_ctx.tphrdesc_ena = 1;
118 rx_ctx.tphwdesc_ena = 1;
119 rx_ctx.tphdata_ena = 1;
120 rx_ctx.tphhead_ena = 1;
121 rx_ctx.lrxqthresh = 2;
127 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
128 if (err != I40E_SUCCESS) {
129 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
132 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
133 if (err != I40E_SUCCESS) {
134 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
137 rxq->qrx_tail = hw->hw_addr +
138 I40E_QRX_TAIL(rxq->vsi->base_queue);
141 /* Init the RX tail regieter. */
142 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
148 * i40e_fdir_setup - reserve and initialize the Flow Director resources
149 * @pf: board private structure
152 i40e_fdir_setup(struct i40e_pf *pf)
154 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
155 struct i40e_vsi *vsi;
156 int err = I40E_SUCCESS;
157 char z_name[RTE_MEMZONE_NAMESIZE];
158 const struct rte_memzone *mz = NULL;
159 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
161 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
162 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
163 return I40E_NOT_SUPPORTED;
166 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
167 " num_filters_best_effort = %u.",
168 hw->func_caps.fd_filters_guaranteed,
169 hw->func_caps.fd_filters_best_effort);
171 vsi = pf->fdir.fdir_vsi;
173 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
176 /* make new FDIR VSI */
177 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
179 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
180 return I40E_ERR_NO_AVAILABLE_VSI;
182 pf->fdir.fdir_vsi = vsi;
184 /*Fdir tx queue setup*/
185 err = i40e_fdir_setup_tx_resources(pf);
187 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
191 /*Fdir rx queue setup*/
192 err = i40e_fdir_setup_rx_resources(pf);
194 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
198 err = i40e_tx_queue_init(pf->fdir.txq);
200 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
204 /* need switch on before dev start*/
205 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
207 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
211 /* Init the rx queue in hardware */
212 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
214 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
218 /* switch on rx queue */
219 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
221 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
225 /* reserve memory for the fdir programming packet */
226 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
227 eth_dev->device->driver->name,
229 eth_dev->data->port_id);
230 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
232 PMD_DRV_LOG(ERR, "Cannot init memzone for "
233 "flow director program packet.");
234 err = I40E_ERR_NO_MEMORY;
237 pf->fdir.prg_pkt = mz->addr;
238 pf->fdir.dma_addr = mz->iova;
240 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
241 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
246 i40e_dev_rx_queue_release(pf->fdir.rxq);
249 i40e_dev_tx_queue_release(pf->fdir.txq);
252 i40e_vsi_release(vsi);
253 pf->fdir.fdir_vsi = NULL;
258 * i40e_fdir_teardown - release the Flow Director resources
259 * @pf: board private structure
262 i40e_fdir_teardown(struct i40e_pf *pf)
264 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
265 struct i40e_vsi *vsi;
267 vsi = pf->fdir.fdir_vsi;
270 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
272 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
273 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
275 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
276 i40e_dev_rx_queue_release(pf->fdir.rxq);
278 i40e_dev_tx_queue_release(pf->fdir.txq);
280 i40e_vsi_release(vsi);
281 pf->fdir.fdir_vsi = NULL;
284 /* check whether the flow director table in empty */
286 i40e_fdir_empty(struct i40e_hw *hw)
288 uint32_t guarant_cnt, best_cnt;
290 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
291 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
292 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
293 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
294 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
295 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
296 if (best_cnt + guarant_cnt > 0)
303 * Initialize the configuration about bytes stream extracted as flexible payload
307 i40e_init_flx_pld(struct i40e_pf *pf)
309 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
315 * Define the bytes stream extracted as flexible payload in
316 * field vector. By default, select 8 words from the beginning
317 * of payload as flexible payload.
319 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
320 index = i * I40E_MAX_FLXPLD_FIED;
321 pf->fdir.flex_set[index].src_offset = 0;
322 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
323 pf->fdir.flex_set[index].dst_offset = 0;
324 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
326 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
328 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
331 /* initialize the masks */
332 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
333 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
334 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
336 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
338 pf->fdir.flex_mask[pctype].word_mask = 0;
339 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
340 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
341 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
342 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
343 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
348 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
349 if ((flex_pit2).src_offset < \
350 (flex_pit1).src_offset + (flex_pit1).size) { \
351 PMD_DRV_LOG(ERR, "src_offset should be not" \
352 " less than than previous offset" \
353 " + previous FSIZE."); \
359 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
360 * and the flex_pit will be sorted by it's src_offset value
362 static inline uint16_t
363 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
364 struct i40e_fdir_flex_pit *flex_pit)
366 uint16_t src_tmp, size, num = 0;
367 uint16_t i, k, j = 0;
369 while (j < I40E_FDIR_MAX_FLEX_LEN) {
371 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
372 if (src_offset[j + 1] == src_offset[j] + 1)
377 src_tmp = src_offset[j] + 1 - size;
378 /* the flex_pit need to be sort by src_offset */
379 for (i = 0; i < num; i++) {
380 if (src_tmp < flex_pit[i].src_offset)
383 /* if insert required, move backward */
384 for (k = num; k > i; k--)
385 flex_pit[k] = flex_pit[k - 1];
387 flex_pit[i].dst_offset = j + 1 - size;
388 flex_pit[i].src_offset = src_tmp;
389 flex_pit[i].size = size;
396 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
398 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
400 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
403 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
404 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
405 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
410 memset(flex_pit, 0, sizeof(flex_pit));
411 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
412 if (num > I40E_MAX_FLXPLD_FIED) {
413 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
416 for (i = 0; i < num; i++) {
417 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
418 flex_pit[i].src_offset & 0x01) {
419 PMD_DRV_LOG(ERR, "flexpayload should be measured"
424 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
430 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
431 * arguments are valid
434 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
435 const struct rte_eth_fdir_flex_conf *conf)
437 const struct rte_eth_flex_payload_cfg *flex_cfg;
438 const struct rte_eth_fdir_flex_mask *flex_mask;
443 enum i40e_filter_pctype pctype;
446 PMD_DRV_LOG(INFO, "NULL pointer.");
449 /* check flexible payload setting configuration */
450 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
451 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
454 for (i = 0; i < conf->nb_payloads; i++) {
455 flex_cfg = &conf->flex_set[i];
456 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
457 PMD_DRV_LOG(ERR, "invalid payload type.");
460 ret = i40e_check_fdir_flex_payload(flex_cfg);
462 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
467 /* check flex mask setting configuration */
468 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
469 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
472 for (i = 0; i < conf->nb_flexmasks; i++) {
473 flex_mask = &conf->flex_mask[i];
474 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
475 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
476 PMD_DRV_LOG(WARNING, "invalid flow type.");
480 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
481 mask_tmp = I40E_WORD(flex_mask->mask[j],
482 flex_mask->mask[j + 1]);
483 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
485 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
486 PMD_DRV_LOG(ERR, " exceed maximal"
487 " number of bitmasks.");
497 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
498 * @pf: board private structure
499 * @cfg: the rule how bytes stream is extracted as flexible payload
502 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
503 const struct rte_eth_flex_payload_cfg *cfg)
505 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
506 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
507 uint32_t flx_pit, flx_ort;
508 uint16_t num, min_next_off; /* in words */
509 uint8_t field_idx = 0;
510 uint8_t layer_idx = 0;
513 if (cfg->type == RTE_ETH_L2_PAYLOAD)
514 layer_idx = I40E_FLXPLD_L2_IDX;
515 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
516 layer_idx = I40E_FLXPLD_L3_IDX;
517 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
518 layer_idx = I40E_FLXPLD_L4_IDX;
520 memset(flex_pit, 0, sizeof(flex_pit));
521 num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
525 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
526 (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
527 (layer_idx * I40E_MAX_FLXPLD_FIED);
528 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
531 for (i = 0; i < num; i++) {
532 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
533 /* record the info in fdir structure */
534 pf->fdir.flex_set[field_idx].src_offset =
535 flex_pit[i].src_offset / sizeof(uint16_t);
536 pf->fdir.flex_set[field_idx].size =
537 flex_pit[i].size / sizeof(uint16_t);
538 pf->fdir.flex_set[field_idx].dst_offset =
539 flex_pit[i].dst_offset / sizeof(uint16_t);
540 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
541 pf->fdir.flex_set[field_idx].size,
542 pf->fdir.flex_set[field_idx].dst_offset);
544 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
546 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
547 pf->fdir.flex_set[field_idx].size;
549 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
550 /* set the non-used register obeying register's constrain */
551 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
552 NONUSE_FLX_PIT_DEST_OFF);
554 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
561 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
562 * @pf: board private structure
563 * @pctype: packet classify type
564 * @flex_masks: mask for flexible payload
567 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
568 enum i40e_filter_pctype pctype,
569 const struct rte_eth_fdir_flex_mask *mask_cfg)
571 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
572 struct i40e_fdir_flex_mask *flex_mask;
573 uint32_t flxinset, fd_mask;
575 uint8_t i, nb_bitmask = 0;
577 flex_mask = &pf->fdir.flex_mask[pctype];
578 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
579 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
580 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
581 if (mask_tmp != 0x0) {
582 flex_mask->word_mask |=
583 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
584 if (mask_tmp != UINT16_MAX) {
586 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
587 flex_mask->bitmask[nb_bitmask].offset =
588 i / sizeof(uint16_t);
593 /* write mask to hw */
594 flxinset = (flex_mask->word_mask <<
595 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
596 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
597 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
599 for (i = 0; i < nb_bitmask; i++) {
600 fd_mask = (flex_mask->bitmask[i].mask <<
601 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
602 I40E_PRTQF_FD_MSK_MASK_MASK;
603 fd_mask |= ((flex_mask->bitmask[i].offset +
604 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
605 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
606 I40E_PRTQF_FD_MSK_OFFSET_MASK;
607 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
612 * Configure flow director related setting
615 i40e_fdir_configure(struct rte_eth_dev *dev)
617 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
618 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
619 struct rte_eth_fdir_flex_conf *conf;
620 enum i40e_filter_pctype pctype;
626 * configuration need to be done before
627 * flow director filters are added
628 * If filters exist, flush them.
630 if (i40e_fdir_empty(hw) < 0) {
631 ret = i40e_fdir_flush(dev);
633 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
638 /* enable FDIR filter */
639 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
640 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
641 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
643 i40e_init_flx_pld(pf); /* set flex config to default value */
645 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
646 ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
648 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
651 /* configure flex payload */
652 for (i = 0; i < conf->nb_payloads; i++)
653 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
654 /* configure flex mask*/
655 for (i = 0; i < conf->nb_flexmasks; i++) {
656 if (hw->mac.type == I40E_MAC_X722) {
657 /* get translated pctype value in fd pctype register */
658 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
659 hw, I40E_GLQF_FD_PCTYPES(
660 (int)i40e_flowtype_to_pctype(pf->adapter,
661 conf->flex_mask[i].flow_type)));
663 pctype = i40e_flowtype_to_pctype(pf->adapter,
664 conf->flex_mask[i].flow_type);
666 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
673 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
674 unsigned char *raw_pkt,
677 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
678 uint16_t *ether_type;
679 uint8_t len = 2 * sizeof(struct ether_addr);
681 struct ipv6_hdr *ip6;
682 static const uint8_t next_proto[] = {
683 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
684 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
685 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
686 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
687 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
688 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
689 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
690 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
691 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
692 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
695 raw_pkt += 2 * sizeof(struct ether_addr);
696 if (vlan && fdir_input->flow_ext.vlan_tci) {
697 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
698 rte_memcpy(raw_pkt + sizeof(uint16_t),
699 &fdir_input->flow_ext.vlan_tci,
701 raw_pkt += sizeof(vlan_frame);
702 len += sizeof(vlan_frame);
704 ether_type = (uint16_t *)raw_pkt;
705 raw_pkt += sizeof(uint16_t);
706 len += sizeof(uint16_t);
708 switch (fdir_input->flow_type) {
709 case RTE_ETH_FLOW_L2_PAYLOAD:
710 *ether_type = fdir_input->flow.l2_flow.ether_type;
712 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
713 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
714 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
715 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
716 case RTE_ETH_FLOW_FRAG_IPV4:
717 ip = (struct ipv4_hdr *)raw_pkt;
719 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
720 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
721 /* set len to by default */
722 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
723 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
724 fdir_input->flow.ip4_flow.proto :
725 next_proto[fdir_input->flow_type];
726 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
727 fdir_input->flow.ip4_flow.ttl :
728 I40E_FDIR_IP_DEFAULT_TTL;
729 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
731 * The source and destination fields in the transmitted packet
732 * need to be presented in a reversed order with respect
733 * to the expected received packets.
735 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
736 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
737 len += sizeof(struct ipv4_hdr);
739 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
740 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
741 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
742 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
743 case RTE_ETH_FLOW_FRAG_IPV6:
744 ip6 = (struct ipv6_hdr *)raw_pkt;
746 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
748 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
749 (fdir_input->flow.ipv6_flow.tc <<
750 I40E_FDIR_IPv6_TC_OFFSET));
752 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
753 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
754 fdir_input->flow.ipv6_flow.proto :
755 next_proto[fdir_input->flow_type];
756 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
757 fdir_input->flow.ipv6_flow.hop_limits :
758 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
760 * The source and destination fields in the transmitted packet
761 * need to be presented in a reversed order with respect
762 * to the expected received packets.
764 rte_memcpy(&(ip6->src_addr),
765 &(fdir_input->flow.ipv6_flow.dst_ip),
767 rte_memcpy(&(ip6->dst_addr),
768 &(fdir_input->flow.ipv6_flow.src_ip),
770 len += sizeof(struct ipv6_hdr);
773 PMD_DRV_LOG(ERR, "unknown flow type %u.",
774 fdir_input->flow_type);
782 * i40e_fdir_construct_pkt - construct packet based on fields in input
783 * @pf: board private structure
784 * @fdir_input: input set of the flow director entry
785 * @raw_pkt: a packet to be constructed
788 i40e_fdir_construct_pkt(struct i40e_pf *pf,
789 const struct rte_eth_fdir_input *fdir_input,
790 unsigned char *raw_pkt)
792 unsigned char *payload, *ptr;
795 struct sctp_hdr *sctp;
796 uint8_t size, dst = 0;
797 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
800 /* fill the ethernet and IP head */
801 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
802 !!fdir_input->flow_ext.vlan_tci);
806 /* fill the L4 head */
807 switch (fdir_input->flow_type) {
808 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
809 udp = (struct udp_hdr *)(raw_pkt + len);
810 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
812 * The source and destination fields in the transmitted packet
813 * need to be presented in a reversed order with respect
814 * to the expected received packets.
816 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
817 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
818 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
821 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
822 tcp = (struct tcp_hdr *)(raw_pkt + len);
823 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
825 * The source and destination fields in the transmitted packet
826 * need to be presented in a reversed order with respect
827 * to the expected received packets.
829 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
830 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
831 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
834 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
835 sctp = (struct sctp_hdr *)(raw_pkt + len);
836 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
838 * The source and destination fields in the transmitted packet
839 * need to be presented in a reversed order with respect
840 * to the expected received packets.
842 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
843 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
844 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
847 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
848 case RTE_ETH_FLOW_FRAG_IPV4:
849 payload = raw_pkt + len;
850 set_idx = I40E_FLXPLD_L3_IDX;
853 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
854 udp = (struct udp_hdr *)(raw_pkt + len);
855 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
857 * The source and destination fields in the transmitted packet
858 * need to be presented in a reversed order with respect
859 * to the expected received packets.
861 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
862 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
863 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
866 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
867 tcp = (struct tcp_hdr *)(raw_pkt + len);
868 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
870 * The source and destination fields in the transmitted packet
871 * need to be presented in a reversed order with respect
872 * to the expected received packets.
874 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
875 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
876 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
879 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
880 sctp = (struct sctp_hdr *)(raw_pkt + len);
881 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
883 * The source and destination fields in the transmitted packet
884 * need to be presented in a reversed order with respect
885 * to the expected received packets.
887 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
888 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
889 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
892 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
893 case RTE_ETH_FLOW_FRAG_IPV6:
894 payload = raw_pkt + len;
895 set_idx = I40E_FLXPLD_L3_IDX;
897 case RTE_ETH_FLOW_L2_PAYLOAD:
898 payload = raw_pkt + len;
900 * ARP packet is a special case on which the payload
901 * starts after the whole ARP header
903 if (fdir_input->flow.l2_flow.ether_type ==
904 rte_cpu_to_be_16(ETHER_TYPE_ARP))
905 payload += sizeof(struct arp_hdr);
906 set_idx = I40E_FLXPLD_L2_IDX;
909 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
913 /* fill the flexbytes to payload */
914 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
915 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
916 size = pf->fdir.flex_set[pit_idx].size;
919 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
921 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
923 &fdir_input->flow_ext.flexbytes[dst],
924 size * sizeof(uint16_t));
930 static struct i40e_customized_pctype *
931 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
933 struct i40e_customized_pctype *cus_pctype;
934 enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
936 for (; i < I40E_CUSTOMIZED_MAX; i++) {
937 cus_pctype = &pf->customized_pctype[i];
938 if (pctype == cus_pctype->pctype)
945 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
946 const struct i40e_fdir_input *fdir_input,
947 unsigned char *raw_pkt,
950 struct i40e_customized_pctype *cus_pctype = NULL;
951 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
952 uint16_t *ether_type;
953 uint8_t len = 2 * sizeof(struct ether_addr);
955 struct ipv6_hdr *ip6;
956 uint8_t pctype = fdir_input->pctype;
957 bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
958 static const uint8_t next_proto[] = {
959 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
960 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
961 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
962 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
963 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
964 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
965 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
966 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
967 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
968 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
971 raw_pkt += 2 * sizeof(struct ether_addr);
972 if (vlan && fdir_input->flow_ext.vlan_tci) {
973 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
974 rte_memcpy(raw_pkt + sizeof(uint16_t),
975 &fdir_input->flow_ext.vlan_tci,
977 raw_pkt += sizeof(vlan_frame);
978 len += sizeof(vlan_frame);
980 ether_type = (uint16_t *)raw_pkt;
981 raw_pkt += sizeof(uint16_t);
982 len += sizeof(uint16_t);
984 if (is_customized_pctype) {
985 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
987 PMD_DRV_LOG(ERR, "unknown pctype %u.",
993 if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
994 *ether_type = fdir_input->flow.l2_flow.ether_type;
995 else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
996 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
997 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
998 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
999 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
1000 is_customized_pctype) {
1001 ip = (struct ipv4_hdr *)raw_pkt;
1003 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
1004 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1005 /* set len to by default */
1006 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
1007 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
1008 fdir_input->flow.ip4_flow.ttl :
1009 I40E_FDIR_IP_DEFAULT_TTL;
1010 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
1012 * The source and destination fields in the transmitted packet
1013 * need to be presented in a reversed order with respect
1014 * to the expected received packets.
1016 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1017 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1019 if (!is_customized_pctype)
1020 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
1021 fdir_input->flow.ip4_flow.proto :
1022 next_proto[fdir_input->pctype];
1023 else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1024 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1025 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1026 cus_pctype->index == I40E_CUSTOMIZED_GTPU)
1027 ip->next_proto_id = IPPROTO_UDP;
1028 len += sizeof(struct ipv4_hdr);
1029 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1030 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1031 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1032 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1033 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1034 ip6 = (struct ipv6_hdr *)raw_pkt;
1036 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
1038 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1039 (fdir_input->flow.ipv6_flow.tc <<
1040 I40E_FDIR_IPv6_TC_OFFSET));
1042 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1043 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1044 fdir_input->flow.ipv6_flow.proto :
1045 next_proto[fdir_input->pctype];
1046 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1047 fdir_input->flow.ipv6_flow.hop_limits :
1048 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1050 * The source and destination fields in the transmitted packet
1051 * need to be presented in a reversed order with respect
1052 * to the expected received packets.
1054 rte_memcpy(&ip6->src_addr,
1055 &fdir_input->flow.ipv6_flow.dst_ip,
1057 rte_memcpy(&ip6->dst_addr,
1058 &fdir_input->flow.ipv6_flow.src_ip,
1060 len += sizeof(struct ipv6_hdr);
1062 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1063 fdir_input->pctype);
1071 * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1072 * @pf: board private structure
1073 * @fdir_input: input set of the flow director entry
1074 * @raw_pkt: a packet to be constructed
1077 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1078 const struct i40e_fdir_input *fdir_input,
1079 unsigned char *raw_pkt)
1081 unsigned char *payload = NULL;
1083 struct udp_hdr *udp;
1084 struct tcp_hdr *tcp;
1085 struct sctp_hdr *sctp;
1086 struct rte_flow_item_gtp *gtp;
1087 struct ipv4_hdr *gtp_ipv4;
1088 struct ipv6_hdr *gtp_ipv6;
1089 uint8_t size, dst = 0;
1090 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1092 uint8_t pctype = fdir_input->pctype;
1093 struct i40e_customized_pctype *cus_pctype;
1095 /* raw pcket template - just copy contents of the raw packet */
1096 if (fdir_input->flow_ext.pkt_template) {
1097 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
1098 fdir_input->flow.raw_flow.length);
1102 /* fill the ethernet and IP head */
1103 len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
1104 !!fdir_input->flow_ext.vlan_tci);
1108 /* fill the L4 head */
1109 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
1110 udp = (struct udp_hdr *)(raw_pkt + len);
1111 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1113 * The source and destination fields in the transmitted packet
1114 * need to be presented in a reversed order with respect
1115 * to the expected received packets.
1117 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1118 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1119 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1120 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
1121 tcp = (struct tcp_hdr *)(raw_pkt + len);
1122 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1124 * The source and destination fields in the transmitted packet
1125 * need to be presented in a reversed order with respect
1126 * to the expected received packets.
1128 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1129 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1130 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1131 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
1132 sctp = (struct sctp_hdr *)(raw_pkt + len);
1133 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1135 * The source and destination fields in the transmitted packet
1136 * need to be presented in a reversed order with respect
1137 * to the expected received packets.
1139 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1140 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1141 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1142 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1143 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1144 payload = raw_pkt + len;
1145 set_idx = I40E_FLXPLD_L3_IDX;
1146 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1147 udp = (struct udp_hdr *)(raw_pkt + len);
1148 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1150 * The source and destination fields in the transmitted packet
1151 * need to be presented in a reversed order with respect
1152 * to the expected received packets.
1154 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1155 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1156 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1157 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1158 tcp = (struct tcp_hdr *)(raw_pkt + len);
1159 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1161 * The source and destination fields in the transmitted packet
1162 * need to be presented in a reversed order with respect
1163 * to the expected received packets.
1165 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1166 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1167 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1168 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1169 sctp = (struct sctp_hdr *)(raw_pkt + len);
1170 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1172 * The source and destination fields in the transmitted packet
1173 * need to be presented in a reversed order with respect
1174 * to the expected received packets.
1176 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1177 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1178 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1179 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1180 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1181 payload = raw_pkt + len;
1182 set_idx = I40E_FLXPLD_L3_IDX;
1183 } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1184 payload = raw_pkt + len;
1186 * ARP packet is a special case on which the payload
1187 * starts after the whole ARP header
1189 if (fdir_input->flow.l2_flow.ether_type ==
1190 rte_cpu_to_be_16(ETHER_TYPE_ARP))
1191 payload += sizeof(struct arp_hdr);
1192 set_idx = I40E_FLXPLD_L2_IDX;
1193 } else if (fdir_input->flow_ext.customized_pctype) {
1194 /* If customized pctype is used */
1195 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1196 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1197 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1198 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1199 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1200 udp = (struct udp_hdr *)(raw_pkt + len);
1202 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1204 gtp = (struct rte_flow_item_gtp *)
1205 ((unsigned char *)udp + sizeof(struct udp_hdr));
1207 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1208 gtp->teid = fdir_input->flow.gtp_flow.teid;
1209 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1211 /* GTP-C message type is not supported. */
1212 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1214 rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1215 gtp->v_pt_rsv_flags =
1216 I40E_FDIR_GTP_VER_FLAG_0X32;
1219 rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1220 gtp->v_pt_rsv_flags =
1221 I40E_FDIR_GTP_VER_FLAG_0X30;
1224 if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1225 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1226 gtp_ipv4 = (struct ipv4_hdr *)
1227 ((unsigned char *)gtp +
1228 sizeof(struct rte_flow_item_gtp));
1229 gtp_ipv4->version_ihl =
1230 I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1231 gtp_ipv4->next_proto_id = IPPROTO_IP;
1232 gtp_ipv4->total_length =
1234 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1235 payload = (unsigned char *)gtp_ipv4 +
1236 sizeof(struct ipv4_hdr);
1237 } else if (cus_pctype->index ==
1238 I40E_CUSTOMIZED_GTPU_IPV6) {
1239 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1240 gtp_ipv6 = (struct ipv6_hdr *)
1241 ((unsigned char *)gtp +
1242 sizeof(struct rte_flow_item_gtp));
1243 gtp_ipv6->vtc_flow =
1245 I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1246 (0 << I40E_FDIR_IPv6_TC_OFFSET));
1247 gtp_ipv6->proto = IPPROTO_NONE;
1248 gtp_ipv6->payload_len =
1250 I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1251 gtp_ipv6->hop_limits =
1252 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1253 payload = (unsigned char *)gtp_ipv6 +
1254 sizeof(struct ipv6_hdr);
1256 payload = (unsigned char *)gtp +
1257 sizeof(struct rte_flow_item_gtp);
1260 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1261 fdir_input->pctype);
1265 /* fill the flexbytes to payload */
1266 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1267 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1268 size = pf->fdir.flex_set[pit_idx].size;
1271 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1273 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1274 (void)rte_memcpy(ptr,
1275 &fdir_input->flow_ext.flexbytes[dst],
1276 size * sizeof(uint16_t));
1282 /* Construct the tx flags */
1283 static inline uint64_t
1284 i40e_build_ctob(uint32_t td_cmd,
1289 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1290 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
1291 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1292 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1293 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
1297 * check the programming status descriptor in rx queue.
1298 * done after Programming Flow Director is programmed on
1302 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1304 volatile union i40e_rx_desc *rxdp;
1311 rxdp = &rxq->rx_ring[rxq->rx_tail];
1312 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1313 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1314 >> I40E_RXD_QW1_STATUS_SHIFT;
1316 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1317 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1318 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1319 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1321 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1322 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1324 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1325 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1326 if (error == (0x1 <<
1327 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1328 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1329 " (FD_ID %u): programming status"
1331 rxdp->wb.qword0.hi_dword.fd_id);
1333 } else if (error == (0x1 <<
1334 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1335 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1336 " (FD_ID %u): programming status"
1338 rxdp->wb.qword0.hi_dword.fd_id);
1341 PMD_DRV_LOG(ERR, "invalid programming status"
1342 " reported, error = %u.", error);
1344 PMD_DRV_LOG(INFO, "unknown programming status"
1345 " reported, len = %d, id = %u.", len, id);
1346 rxdp->wb.qword1.status_error_len = 0;
1348 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1350 if (rxq->rx_tail == 0)
1351 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1353 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1360 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1361 struct i40e_fdir_filter *filter)
1363 rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1364 if (input->input.flow_ext.pkt_template) {
1365 filter->fdir.input.flow.raw_flow.packet = NULL;
1366 filter->fdir.input.flow.raw_flow.length =
1367 rte_hash_crc(input->input.flow.raw_flow.packet,
1368 input->input.flow.raw_flow.length,
1369 input->input.flow.raw_flow.pctype);
1374 /* Check if there exists the flow director filter */
1375 static struct i40e_fdir_filter *
1376 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1377 const struct i40e_fdir_input *input)
1381 if (input->flow_ext.pkt_template)
1382 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1383 (const void *)input,
1384 input->flow.raw_flow.length);
1386 ret = rte_hash_lookup(fdir_info->hash_table,
1387 (const void *)input);
1391 return fdir_info->hash_map[ret];
1394 /* Add a flow director filter into the SW list */
1396 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1398 struct i40e_fdir_info *fdir_info = &pf->fdir;
1401 if (filter->fdir.input.flow_ext.pkt_template)
1402 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1403 &filter->fdir.input,
1404 filter->fdir.input.flow.raw_flow.length);
1406 ret = rte_hash_add_key(fdir_info->hash_table,
1407 &filter->fdir.input);
1410 "Failed to insert fdir filter to hash table %d!",
1414 fdir_info->hash_map[ret] = filter;
1416 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1421 /* Delete a flow director filter from the SW list */
1423 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1425 struct i40e_fdir_info *fdir_info = &pf->fdir;
1426 struct i40e_fdir_filter *filter;
1429 if (input->flow_ext.pkt_template)
1430 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1432 input->flow.raw_flow.length);
1434 ret = rte_hash_del_key(fdir_info->hash_table, input);
1437 "Failed to delete fdir filter to hash table %d!",
1441 filter = fdir_info->hash_map[ret];
1442 fdir_info->hash_map[ret] = NULL;
1444 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1451 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1452 * @pf: board private structure
1453 * @filter: fdir filter entry
1454 * @add: 0 - delete, 1 - add
1457 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1458 const struct rte_eth_fdir_filter *filter,
1461 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1463 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1464 enum i40e_filter_pctype pctype;
1467 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1468 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1469 " check the mode in fdir_conf.");
1473 pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1474 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1475 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1478 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1479 PMD_DRV_LOG(ERR, "Invalid queue ID");
1482 if (filter->input.flow_ext.is_vf &&
1483 filter->input.flow_ext.dst_id >= pf->vf_num) {
1484 PMD_DRV_LOG(ERR, "Invalid VF ID");
1488 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1490 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1492 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1496 if (hw->mac.type == I40E_MAC_X722) {
1497 /* get translated pctype value in fd pctype register */
1498 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1499 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1502 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1504 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1513 * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1514 * @pf: board private structure
1515 * @filter: fdir filter entry
1516 * @add: 0 - delete, 1 - add
1519 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1520 const struct i40e_fdir_filter_conf *filter,
1523 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1525 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1526 enum i40e_filter_pctype pctype;
1527 struct i40e_fdir_info *fdir_info = &pf->fdir;
1528 struct i40e_fdir_filter *fdir_filter, *node;
1529 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1532 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1533 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1537 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1538 PMD_DRV_LOG(ERR, "Invalid queue ID");
1541 if (filter->input.flow_ext.is_vf &&
1542 filter->input.flow_ext.dst_id >= pf->vf_num) {
1543 PMD_DRV_LOG(ERR, "Invalid VF ID");
1546 if (filter->input.flow_ext.pkt_template) {
1547 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1548 !filter->input.flow.raw_flow.packet) {
1549 PMD_DRV_LOG(ERR, "Invalid raw packet template"
1550 " flow filter parameters!");
1553 pctype = filter->input.flow.raw_flow.pctype;
1555 pctype = filter->input.pctype;
1558 /* Check if there is the filter in SW list */
1559 memset(&check_filter, 0, sizeof(check_filter));
1560 i40e_fdir_filter_convert(filter, &check_filter);
1561 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1564 "Conflict with existing flow director rules!");
1568 if (!add && !node) {
1570 "There's no corresponding flow firector filter!");
1574 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1576 ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1578 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1582 if (hw->mac.type == I40E_MAC_X722) {
1583 /* get translated pctype value in fd pctype register */
1584 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1585 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1588 ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1590 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1596 fdir_filter = rte_zmalloc("fdir_filter",
1597 sizeof(*fdir_filter), 0);
1598 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1599 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1601 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1608 * i40e_fdir_filter_programming - Program a flow director filter rule.
1609 * Is done by Flow Director Programming Descriptor followed by packet
1610 * structure that contains the filter fields need to match.
1611 * @pf: board private structure
1613 * @filter: fdir filter entry
1614 * @add: 0 - delete, 1 - add
1617 i40e_fdir_filter_programming(struct i40e_pf *pf,
1618 enum i40e_filter_pctype pctype,
1619 const struct rte_eth_fdir_filter *filter,
1622 struct i40e_tx_queue *txq = pf->fdir.txq;
1623 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1624 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1625 volatile struct i40e_tx_desc *txdp;
1626 volatile struct i40e_filter_program_desc *fdirdp;
1631 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1632 fdirdp = (volatile struct i40e_filter_program_desc *)
1633 (&(txq->tx_ring[txq->tx_tail]));
1635 fdirdp->qindex_flex_ptype_vsi =
1636 rte_cpu_to_le_32((fdir_action->rx_queue <<
1637 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1638 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1640 fdirdp->qindex_flex_ptype_vsi |=
1641 rte_cpu_to_le_32((fdir_action->flex_off <<
1642 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1643 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1645 fdirdp->qindex_flex_ptype_vsi |=
1646 rte_cpu_to_le_32((pctype <<
1647 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1648 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1650 if (filter->input.flow_ext.is_vf)
1651 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1653 /* Use LAN VSI Id by default */
1654 vsi_id = pf->main_vsi->vsi_id;
1655 fdirdp->qindex_flex_ptype_vsi |=
1656 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1657 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1658 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1660 fdirdp->dtype_cmd_cntindex =
1661 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1664 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1665 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1666 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1668 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1669 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1670 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1672 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1673 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1674 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1675 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1676 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1677 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1679 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1680 " unsupported fdir behavior.");
1684 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1685 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1686 I40E_TXD_FLTR_QW1_DEST_MASK);
1688 fdirdp->dtype_cmd_cntindex |=
1689 rte_cpu_to_le_32((fdir_action->report_status<<
1690 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1691 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1693 fdirdp->dtype_cmd_cntindex |=
1694 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1695 fdirdp->dtype_cmd_cntindex |=
1697 ((uint32_t)pf->fdir.match_counter_index <<
1698 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1699 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1701 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1703 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1704 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1705 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1706 td_cmd = I40E_TX_DESC_CMD_EOP |
1707 I40E_TX_DESC_CMD_RS |
1708 I40E_TX_DESC_CMD_DUMMY;
1710 txdp->cmd_type_offset_bsz =
1711 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1713 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1714 if (txq->tx_tail >= txq->nb_tx_desc)
1716 /* Update the tx tail register */
1718 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1719 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1720 if ((txdp->cmd_type_offset_bsz &
1721 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1722 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1726 if (i >= I40E_FDIR_MAX_WAIT_US) {
1727 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1728 " time out to get DD on tx queue.");
1731 /* totally delay 10 ms to check programming status*/
1732 for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1733 if (i40e_check_fdir_programming_status(rxq) >= 0)
1738 "Failed to program FDIR filter: programming status reported.");
1743 * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1744 * Is done by Flow Director Programming Descriptor followed by packet
1745 * structure that contains the filter fields need to match.
1746 * @pf: board private structure
1748 * @filter: fdir filter entry
1749 * @add: 0 - delete, 1 - add
1752 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1753 enum i40e_filter_pctype pctype,
1754 const struct i40e_fdir_filter_conf *filter,
1757 struct i40e_tx_queue *txq = pf->fdir.txq;
1758 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1759 const struct i40e_fdir_action *fdir_action = &filter->action;
1760 volatile struct i40e_tx_desc *txdp;
1761 volatile struct i40e_filter_program_desc *fdirdp;
1766 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1767 fdirdp = (volatile struct i40e_filter_program_desc *)
1768 (&txq->tx_ring[txq->tx_tail]);
1770 fdirdp->qindex_flex_ptype_vsi =
1771 rte_cpu_to_le_32((fdir_action->rx_queue <<
1772 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1773 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1775 fdirdp->qindex_flex_ptype_vsi |=
1776 rte_cpu_to_le_32((fdir_action->flex_off <<
1777 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1778 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1780 fdirdp->qindex_flex_ptype_vsi |=
1781 rte_cpu_to_le_32((pctype <<
1782 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1783 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1785 if (filter->input.flow_ext.is_vf)
1786 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1788 /* Use LAN VSI Id by default */
1789 vsi_id = pf->main_vsi->vsi_id;
1790 fdirdp->qindex_flex_ptype_vsi |=
1791 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1792 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1793 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1795 fdirdp->dtype_cmd_cntindex =
1796 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1799 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1800 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1801 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1803 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1804 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1805 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1807 if (fdir_action->behavior == I40E_FDIR_REJECT)
1808 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1809 else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1810 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1811 else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1812 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1814 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1818 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1819 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1820 I40E_TXD_FLTR_QW1_DEST_MASK);
1822 fdirdp->dtype_cmd_cntindex |=
1823 rte_cpu_to_le_32((fdir_action->report_status <<
1824 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1825 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1827 fdirdp->dtype_cmd_cntindex |=
1828 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1829 fdirdp->dtype_cmd_cntindex |=
1831 ((uint32_t)pf->fdir.match_counter_index <<
1832 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1833 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1835 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1837 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1838 txdp = &txq->tx_ring[txq->tx_tail + 1];
1839 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1840 td_cmd = I40E_TX_DESC_CMD_EOP |
1841 I40E_TX_DESC_CMD_RS |
1842 I40E_TX_DESC_CMD_DUMMY;
1844 txdp->cmd_type_offset_bsz =
1845 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1847 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1848 if (txq->tx_tail >= txq->nb_tx_desc)
1850 /* Update the tx tail register */
1852 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1853 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1854 if ((txdp->cmd_type_offset_bsz &
1855 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1856 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1860 if (i >= I40E_FDIR_MAX_WAIT_US) {
1862 "Failed to program FDIR filter: time out to get DD on tx queue.");
1865 /* totally delay 10 ms to check programming status*/
1866 rte_delay_us(I40E_FDIR_MAX_WAIT_US);
1867 if (i40e_check_fdir_programming_status(rxq) < 0) {
1869 "Failed to program FDIR filter: programming status reported.");
1877 * i40e_fdir_flush - clear all filters of Flow Director table
1878 * @pf: board private structure
1881 i40e_fdir_flush(struct rte_eth_dev *dev)
1883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1884 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1886 uint16_t guarant_cnt, best_cnt;
1889 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1890 I40E_WRITE_FLUSH(hw);
1892 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1893 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1894 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1895 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1898 if (i >= I40E_FDIR_FLUSH_RETRY) {
1899 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1902 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1903 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1904 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1905 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1906 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1907 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1908 if (guarant_cnt != 0 || best_cnt != 0) {
1909 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1912 PMD_DRV_LOG(INFO, "FD table Flush success.");
1917 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1918 struct rte_eth_flex_payload_cfg *flex_set,
1921 struct i40e_fdir_flex_pit *flex_pit;
1922 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1923 uint16_t src, dst, size, j, k;
1924 uint8_t i, layer_idx;
1926 for (layer_idx = I40E_FLXPLD_L2_IDX;
1927 layer_idx <= I40E_FLXPLD_L4_IDX;
1929 if (layer_idx == I40E_FLXPLD_L2_IDX)
1930 ptr->type = RTE_ETH_L2_PAYLOAD;
1931 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1932 ptr->type = RTE_ETH_L3_PAYLOAD;
1933 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1934 ptr->type = RTE_ETH_L4_PAYLOAD;
1936 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1937 flex_pit = &pf->fdir.flex_set[layer_idx *
1938 I40E_MAX_FLXPLD_FIED + i];
1939 if (flex_pit->size == 0)
1941 src = flex_pit->src_offset * sizeof(uint16_t);
1942 dst = flex_pit->dst_offset * sizeof(uint16_t);
1943 size = flex_pit->size * sizeof(uint16_t);
1944 for (j = src, k = dst; j < src + size; j++, k++)
1945 ptr->src_offset[k] = j;
1953 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1954 struct rte_eth_fdir_flex_mask *flex_mask,
1957 struct i40e_fdir_flex_mask *mask;
1958 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1961 uint16_t off_bytes, mask_tmp;
1963 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1964 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1966 mask = &pf->fdir.flex_mask[i];
1967 flow_type = i40e_pctype_to_flowtype(pf->adapter,
1968 (enum i40e_filter_pctype)i);
1969 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
1972 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1973 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1974 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1975 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1977 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1978 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1981 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1982 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1983 mask_tmp = ~mask->bitmask[j].mask;
1984 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1985 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1987 ptr->flow_type = flow_type;
1994 * i40e_fdir_info_get - get information of Flow Director
1995 * @pf: ethernet device to get info from
1996 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1997 * the flow director information.
2000 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2004 uint16_t num_flex_set = 0;
2005 uint16_t num_flex_mask = 0;
2008 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2009 fdir->mode = RTE_FDIR_MODE_PERFECT;
2011 fdir->mode = RTE_FDIR_MODE_NONE;
2014 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2016 (uint32_t)hw->func_caps.fd_filters_best_effort;
2017 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2018 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2019 for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2020 fdir->flow_types_mask[i] = 0ULL;
2021 fdir->flex_payload_unit = sizeof(uint16_t);
2022 fdir->flex_bitmask_unit = sizeof(uint16_t);
2023 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2024 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2025 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2027 i40e_fdir_info_get_flex_set(pf,
2028 fdir->flex_conf.flex_set,
2030 i40e_fdir_info_get_flex_mask(pf,
2031 fdir->flex_conf.flex_mask,
2034 fdir->flex_conf.nb_payloads = num_flex_set;
2035 fdir->flex_conf.nb_flexmasks = num_flex_mask;
2039 * i40e_fdir_stat_get - get statistics of Flow Director
2040 * @pf: ethernet device to get info from
2041 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2042 * the flow director statistics.
2045 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2047 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2048 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2051 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2053 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2054 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2056 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2057 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2061 i40e_fdir_filter_set(struct rte_eth_dev *dev,
2062 struct rte_eth_fdir_filter_info *info)
2064 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2068 PMD_DRV_LOG(ERR, "Invalid pointer");
2072 switch (info->info_type) {
2073 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
2074 ret = i40e_fdir_filter_inset_select(pf,
2075 &(info->info.input_set_conf));
2078 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
2087 * i40e_fdir_ctrl_func - deal with all operations on flow director.
2088 * @pf: board private structure
2089 * @filter_op:operation will be taken.
2090 * @arg: a pointer to specific structure corresponding to the filter_op
2093 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
2094 enum rte_filter_op filter_op,
2097 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2100 if ((pf->flags & I40E_FLAG_FDIR) == 0)
2103 if (filter_op == RTE_ETH_FILTER_NOP)
2106 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2109 switch (filter_op) {
2110 case RTE_ETH_FILTER_ADD:
2111 ret = i40e_add_del_fdir_filter(dev,
2112 (struct rte_eth_fdir_filter *)arg,
2115 case RTE_ETH_FILTER_DELETE:
2116 ret = i40e_add_del_fdir_filter(dev,
2117 (struct rte_eth_fdir_filter *)arg,
2120 case RTE_ETH_FILTER_FLUSH:
2121 ret = i40e_fdir_flush(dev);
2123 case RTE_ETH_FILTER_INFO:
2124 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2126 case RTE_ETH_FILTER_SET:
2127 ret = i40e_fdir_filter_set(dev,
2128 (struct rte_eth_fdir_filter_info *)arg);
2130 case RTE_ETH_FILTER_STATS:
2131 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2134 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2141 /* Restore flow director filter */
2143 i40e_fdir_filter_restore(struct i40e_pf *pf)
2145 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2146 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2147 struct i40e_fdir_filter *f;
2148 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2150 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
2151 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
2153 TAILQ_FOREACH(f, fdir_list, rules)
2154 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2156 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2158 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2159 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2161 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2162 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2164 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
2165 guarant_cnt, best_cnt);