1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
13 #include <rte_ether.h>
14 #include <ethdev_driver.h>
16 #include <rte_memzone.h>
17 #include <rte_malloc.h>
23 #include <rte_hash_crc.h>
24 #include <rte_bitmap.h>
25 #include <rte_os_shim.h>
27 #include "i40e_logs.h"
28 #include "base/i40e_type.h"
29 #include "base/i40e_prototype.h"
30 #include "i40e_ethdev.h"
31 #include "i40e_rxtx.h"
33 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
35 #define IPV6_ADDR_LEN 16
39 #define IPPROTO_L2TP 115
42 #define I40E_FDIR_PKT_LEN 512
43 #define I40E_FDIR_IP_DEFAULT_LEN 420
44 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
45 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
46 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
47 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
49 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
50 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
51 #define I40E_FDIR_UDP_DEFAULT_LEN 400
52 #define I40E_FDIR_GTP_DEFAULT_LEN 384
53 #define I40E_FDIR_INNER_IP_DEFAULT_LEN 384
54 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN 344
56 #define I40E_FDIR_GTPC_DST_PORT 2123
57 #define I40E_FDIR_GTPU_DST_PORT 2152
58 #define I40E_FDIR_GTP_VER_FLAG_0X30 0x30
59 #define I40E_FDIR_GTP_VER_FLAG_0X32 0x32
60 #define I40E_FDIR_GTP_MSG_TYPE_0X01 0x01
61 #define I40E_FDIR_GTP_MSG_TYPE_0XFF 0xFF
63 #define I40E_FDIR_ESP_DST_PORT 4500
65 /* Wait time for fdir filter programming */
66 #define I40E_FDIR_MAX_WAIT_US 10000
68 /* Wait count and interval for fdir filter flush */
69 #define I40E_FDIR_FLUSH_RETRY 50
70 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
72 #define I40E_COUNTER_PF 2
73 /* Statistic counter index for one pf */
74 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
76 #define I40E_FDIR_FLOWS ( \
77 (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
78 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
79 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
80 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
81 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
82 (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
83 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
84 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
85 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
86 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
87 (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
89 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
90 struct i40e_fdir_filter *filter);
91 static struct i40e_fdir_filter *
92 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
93 const struct i40e_fdir_input *input);
94 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
95 struct i40e_fdir_filter *filter);
97 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
98 enum i40e_filter_pctype pctype,
99 const struct i40e_fdir_filter_conf *filter,
100 bool add, bool wait_status);
103 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
105 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
106 struct i40e_hmc_obj_rxq rx_ctx;
107 int err = I40E_SUCCESS;
109 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
110 /* Init the RX queue in hardware */
111 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
113 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
114 rx_ctx.qlen = rxq->nb_rx_desc;
115 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
118 rx_ctx.dtype = i40e_header_split_none;
119 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
120 rx_ctx.rxmax = I40E_ETH_MAX_LEN;
121 rx_ctx.tphrdesc_ena = 1;
122 rx_ctx.tphwdesc_ena = 1;
123 rx_ctx.tphdata_ena = 1;
124 rx_ctx.tphhead_ena = 1;
125 rx_ctx.lrxqthresh = 2;
131 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
132 if (err != I40E_SUCCESS) {
133 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
136 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
137 if (err != I40E_SUCCESS) {
138 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
141 rxq->qrx_tail = hw->hw_addr +
142 I40E_QRX_TAIL(rxq->vsi->base_queue);
145 /* Init the RX tail regieter. */
146 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
152 * i40e_fdir_setup - reserve and initialize the Flow Director resources
153 * @pf: board private structure
156 i40e_fdir_setup(struct i40e_pf *pf)
158 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
159 struct i40e_vsi *vsi;
160 int err = I40E_SUCCESS;
161 char z_name[RTE_MEMZONE_NAMESIZE];
162 const struct rte_memzone *mz = NULL;
163 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
166 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
167 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
168 return I40E_NOT_SUPPORTED;
171 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
172 " num_filters_best_effort = %u.",
173 hw->func_caps.fd_filters_guaranteed,
174 hw->func_caps.fd_filters_best_effort);
176 vsi = pf->fdir.fdir_vsi;
178 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
182 /* make new FDIR VSI */
183 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
185 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
186 return I40E_ERR_NO_AVAILABLE_VSI;
188 pf->fdir.fdir_vsi = vsi;
190 /*Fdir tx queue setup*/
191 err = i40e_fdir_setup_tx_resources(pf);
193 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
197 /*Fdir rx queue setup*/
198 err = i40e_fdir_setup_rx_resources(pf);
200 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
204 err = i40e_tx_queue_init(pf->fdir.txq);
206 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
210 /* need switch on before dev start*/
211 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
213 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
217 /* Init the rx queue in hardware */
218 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
220 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
224 /* switch on rx queue */
225 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
227 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
231 /* enable FDIR MSIX interrupt */
232 vsi->nb_used_qps = 1;
233 i40e_vsi_queues_bind_intr(vsi, I40E_ITR_INDEX_NONE);
234 i40e_vsi_enable_queues_intr(vsi);
236 /* reserve memory for the fdir programming packet */
237 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
238 eth_dev->device->driver->name,
240 eth_dev->data->port_id);
241 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN *
242 I40E_FDIR_PRG_PKT_CNT, SOCKET_ID_ANY);
244 PMD_DRV_LOG(ERR, "Cannot init memzone for "
245 "flow director program packet.");
246 err = I40E_ERR_NO_MEMORY;
250 for (i = 0; i < I40E_FDIR_PRG_PKT_CNT; i++) {
251 pf->fdir.prg_pkt[i] = (uint8_t *)mz->addr +
252 I40E_FDIR_PKT_LEN * i;
253 pf->fdir.dma_addr[i] = mz->iova +
254 I40E_FDIR_PKT_LEN * i;
257 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
258 pf->fdir.fdir_actual_cnt = 0;
259 pf->fdir.fdir_guarantee_free_space =
260 pf->fdir.fdir_guarantee_total_space;
262 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
267 i40e_dev_rx_queue_release(pf->fdir.rxq);
270 i40e_dev_tx_queue_release(pf->fdir.txq);
273 i40e_vsi_release(vsi);
274 pf->fdir.fdir_vsi = NULL;
279 * i40e_fdir_teardown - release the Flow Director resources
280 * @pf: board private structure
283 i40e_fdir_teardown(struct i40e_pf *pf)
285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
286 struct i40e_vsi *vsi;
287 struct rte_eth_dev *dev = pf->adapter->eth_dev;
289 vsi = pf->fdir.fdir_vsi;
293 /* disable FDIR MSIX interrupt */
294 i40e_vsi_queues_unbind_intr(vsi);
295 i40e_vsi_disable_queues_intr(vsi);
297 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
299 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
300 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
302 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
304 i40e_dev_rx_queue_release(pf->fdir.rxq);
305 rte_eth_dma_zone_free(dev, "fdir_rx_ring", pf->fdir.rxq->queue_id);
307 i40e_dev_tx_queue_release(pf->fdir.txq);
308 rte_eth_dma_zone_free(dev, "fdir_tx_ring", pf->fdir.txq->queue_id);
310 i40e_vsi_release(vsi);
311 pf->fdir.fdir_vsi = NULL;
314 /* check whether the flow director table in empty */
316 i40e_fdir_empty(struct i40e_hw *hw)
318 uint32_t guarant_cnt, best_cnt;
320 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
321 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
322 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
323 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
324 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
325 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
326 if (best_cnt + guarant_cnt > 0)
333 * Initialize the configuration about bytes stream extracted as flexible payload
337 i40e_init_flx_pld(struct i40e_pf *pf)
339 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
345 * Define the bytes stream extracted as flexible payload in
346 * field vector. By default, select 8 words from the beginning
347 * of payload as flexible payload.
349 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
350 index = i * I40E_MAX_FLXPLD_FIED;
351 pf->fdir.flex_set[index].src_offset = 0;
352 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
353 pf->fdir.flex_set[index].dst_offset = 0;
354 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
356 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
358 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
359 pf->fdir.flex_pit_flag[i] = 0;
362 /* initialize the masks */
363 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
364 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
365 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
367 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
369 pf->fdir.flex_mask[pctype].word_mask = 0;
370 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
371 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
372 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
373 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
374 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
379 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
380 if ((flex_pit2).src_offset < \
381 (flex_pit1).src_offset + (flex_pit1).size) { \
382 PMD_DRV_LOG(ERR, "src_offset should be not" \
383 " less than than previous offset" \
384 " + previous FSIZE."); \
390 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
391 * and the flex_pit will be sorted by it's src_offset value
393 static inline uint16_t
394 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
395 struct i40e_fdir_flex_pit *flex_pit)
397 uint16_t src_tmp, size, num = 0;
398 uint16_t i, k, j = 0;
400 while (j < I40E_FDIR_MAX_FLEX_LEN) {
402 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
403 if (src_offset[j + 1] == src_offset[j] + 1)
408 src_tmp = src_offset[j] + 1 - size;
409 /* the flex_pit need to be sort by src_offset */
410 for (i = 0; i < num; i++) {
411 if (src_tmp < flex_pit[i].src_offset)
414 /* if insert required, move backward */
415 for (k = num; k > i; k--)
416 flex_pit[k] = flex_pit[k - 1];
418 flex_pit[i].dst_offset = j + 1 - size;
419 flex_pit[i].src_offset = src_tmp;
420 flex_pit[i].size = size;
427 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
429 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
431 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
434 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
435 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
436 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
441 memset(flex_pit, 0, sizeof(flex_pit));
442 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
443 if (num > I40E_MAX_FLXPLD_FIED) {
444 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
447 for (i = 0; i < num; i++) {
448 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
449 flex_pit[i].src_offset & 0x01) {
450 PMD_DRV_LOG(ERR, "flexpayload should be measured"
455 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
461 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
462 * arguments are valid
465 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
466 const struct rte_eth_fdir_flex_conf *conf)
468 const struct rte_eth_flex_payload_cfg *flex_cfg;
469 const struct rte_eth_fdir_flex_mask *flex_mask;
474 enum i40e_filter_pctype pctype;
477 PMD_DRV_LOG(INFO, "NULL pointer.");
480 /* check flexible payload setting configuration */
481 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
482 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
485 for (i = 0; i < conf->nb_payloads; i++) {
486 flex_cfg = &conf->flex_set[i];
487 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
488 PMD_DRV_LOG(ERR, "invalid payload type.");
491 ret = i40e_check_fdir_flex_payload(flex_cfg);
493 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
498 /* check flex mask setting configuration */
499 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
500 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
503 for (i = 0; i < conf->nb_flexmasks; i++) {
504 flex_mask = &conf->flex_mask[i];
505 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
506 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
507 PMD_DRV_LOG(WARNING, "invalid flow type.");
511 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
512 mask_tmp = I40E_WORD(flex_mask->mask[j],
513 flex_mask->mask[j + 1]);
514 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
516 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
517 PMD_DRV_LOG(ERR, " exceed maximal"
518 " number of bitmasks.");
528 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
529 * @pf: board private structure
530 * @cfg: the rule how bytes stream is extracted as flexible payload
533 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
534 const struct rte_eth_flex_payload_cfg *cfg)
536 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
537 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
538 uint32_t flx_pit, flx_ort;
539 uint16_t num, min_next_off; /* in words */
540 uint8_t field_idx = 0;
541 uint8_t layer_idx = 0;
544 if (cfg->type == RTE_ETH_L2_PAYLOAD)
545 layer_idx = I40E_FLXPLD_L2_IDX;
546 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
547 layer_idx = I40E_FLXPLD_L3_IDX;
548 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
549 layer_idx = I40E_FLXPLD_L4_IDX;
551 memset(flex_pit, 0, sizeof(flex_pit));
552 num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
556 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
557 (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
558 (layer_idx * I40E_MAX_FLXPLD_FIED);
559 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
562 for (i = 0; i < num; i++) {
563 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
564 /* record the info in fdir structure */
565 pf->fdir.flex_set[field_idx].src_offset =
566 flex_pit[i].src_offset / sizeof(uint16_t);
567 pf->fdir.flex_set[field_idx].size =
568 flex_pit[i].size / sizeof(uint16_t);
569 pf->fdir.flex_set[field_idx].dst_offset =
570 flex_pit[i].dst_offset / sizeof(uint16_t);
571 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
572 pf->fdir.flex_set[field_idx].size,
573 pf->fdir.flex_set[field_idx].dst_offset);
575 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
577 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
578 pf->fdir.flex_set[field_idx].size;
580 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
581 /* set the non-used register obeying register's constrain */
582 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
583 NONUSE_FLX_PIT_DEST_OFF);
585 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
592 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
593 * @pf: board private structure
594 * @pctype: packet classify type
595 * @flex_masks: mask for flexible payload
598 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
599 enum i40e_filter_pctype pctype,
600 const struct rte_eth_fdir_flex_mask *mask_cfg)
602 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
603 struct i40e_fdir_flex_mask *flex_mask;
604 uint32_t flxinset, fd_mask;
606 uint8_t i, nb_bitmask = 0;
608 flex_mask = &pf->fdir.flex_mask[pctype];
609 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
610 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
611 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
612 if (mask_tmp != 0x0) {
613 flex_mask->word_mask |=
614 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
615 if (mask_tmp != UINT16_MAX) {
617 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
618 flex_mask->bitmask[nb_bitmask].offset =
619 i / sizeof(uint16_t);
624 /* write mask to hw */
625 flxinset = (flex_mask->word_mask <<
626 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
627 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
628 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
630 for (i = 0; i < nb_bitmask; i++) {
631 fd_mask = (flex_mask->bitmask[i].mask <<
632 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
633 I40E_PRTQF_FD_MSK_MASK_MASK;
634 fd_mask |= ((flex_mask->bitmask[i].offset +
635 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
636 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
637 I40E_PRTQF_FD_MSK_OFFSET_MASK;
638 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
643 * Enable/disable flow director RX processing in vector routines.
646 i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on)
650 for (i = 0; i < dev->data->nb_rx_queues; i++) {
651 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
654 rxq->fdir_enabled = on;
656 PMD_DRV_LOG(DEBUG, "Flow Director processing on RX set to %d", on);
660 * Configure flow director related setting
663 i40e_fdir_configure(struct rte_eth_dev *dev)
665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
667 struct rte_eth_fdir_flex_conf *conf;
668 enum i40e_filter_pctype pctype;
674 * configuration need to be done before
675 * flow director filters are added
676 * If filters exist, flush them.
678 if (i40e_fdir_empty(hw) < 0) {
679 ret = i40e_fdir_flush(dev);
681 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
686 /* enable FDIR filter */
687 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
688 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
689 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
691 i40e_init_flx_pld(pf); /* set flex config to default value */
693 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
694 ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
696 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
700 if (!pf->support_multi_driver) {
701 /* configure flex payload */
702 for (i = 0; i < conf->nb_payloads; i++)
703 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
704 /* configure flex mask*/
705 for (i = 0; i < conf->nb_flexmasks; i++) {
706 if (hw->mac.type == I40E_MAC_X722) {
707 /* get pctype value in fd pctype register */
708 pctype = (enum i40e_filter_pctype)
710 I40E_GLQF_FD_PCTYPES(
711 (int)i40e_flowtype_to_pctype(
713 conf->flex_mask[i].flow_type)));
715 pctype = i40e_flowtype_to_pctype(pf->adapter,
716 conf->flex_mask[i].flow_type);
719 i40e_set_flex_mask_on_pctype(pf, pctype,
720 &conf->flex_mask[i]);
723 PMD_DRV_LOG(ERR, "Not support flexible payload.");
726 /* Enable FDIR processing in RX routines */
727 i40e_fdir_rx_proc_enable(dev, 1);
733 static struct i40e_customized_pctype *
734 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
736 struct i40e_customized_pctype *cus_pctype;
737 enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
739 for (; i < I40E_CUSTOMIZED_MAX; i++) {
740 cus_pctype = &pf->customized_pctype[i];
741 if (pctype == cus_pctype->pctype)
748 fill_ip6_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
749 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
751 struct rte_ipv6_hdr *ip6;
753 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
755 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
756 ip6->vtc_flow = rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
757 (fdir_input->flow.ipv6_flow.tc << I40E_FDIR_IPv6_TC_OFFSET));
758 ip6->payload_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
759 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
760 fdir_input->flow.ipv6_flow.proto : next_proto;
761 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
762 fdir_input->flow.ipv6_flow.hop_limits :
763 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
765 * The source and destination fields in the transmitted packet
766 * need to be presented in a reversed order with respect
767 * to the expected received packets.
769 rte_memcpy(&ip6->src_addr, &fdir_input->flow.ipv6_flow.dst_ip,
771 rte_memcpy(&ip6->dst_addr, &fdir_input->flow.ipv6_flow.src_ip,
773 len += sizeof(struct rte_ipv6_hdr);
779 fill_ip4_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
780 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
782 struct rte_ipv4_hdr *ip4;
784 ip4 = (struct rte_ipv4_hdr *)raw_pkt;
786 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
787 ip4->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
788 /* set len to by default */
789 ip4->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
790 ip4->time_to_live = fdir_input->flow.ip4_flow.ttl ?
791 fdir_input->flow.ip4_flow.ttl :
792 I40E_FDIR_IP_DEFAULT_TTL;
793 ip4->type_of_service = fdir_input->flow.ip4_flow.tos;
794 ip4->next_proto_id = fdir_input->flow.ip4_flow.proto ?
795 fdir_input->flow.ip4_flow.proto : next_proto;
797 * The source and destination fields in the transmitted packet
798 * need to be presented in a reversed order with respect
799 * to the expected received packets.
801 ip4->src_addr = fdir_input->flow.ip4_flow.dst_ip;
802 ip4->dst_addr = fdir_input->flow.ip4_flow.src_ip;
803 len += sizeof(struct rte_ipv4_hdr);
809 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
810 const struct i40e_fdir_input *fdir_input,
811 unsigned char *raw_pkt,
814 struct i40e_customized_pctype *cus_pctype = NULL;
815 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
816 uint16_t *ether_type;
817 uint8_t len = 2 * sizeof(struct rte_ether_addr);
818 uint8_t pctype = fdir_input->pctype;
819 bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
820 static const uint8_t next_proto[] = {
821 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
822 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
823 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
824 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
825 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
826 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
827 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
828 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
829 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
830 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
833 rte_memcpy(raw_pkt, &fdir_input->flow.l2_flow.dst,
834 sizeof(struct rte_ether_addr));
835 rte_memcpy(raw_pkt + sizeof(struct rte_ether_addr),
836 &fdir_input->flow.l2_flow.src,
837 sizeof(struct rte_ether_addr));
838 raw_pkt += 2 * sizeof(struct rte_ether_addr);
840 if (vlan && fdir_input->flow_ext.vlan_tci) {
841 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
842 rte_memcpy(raw_pkt + sizeof(uint16_t),
843 &fdir_input->flow_ext.vlan_tci,
845 raw_pkt += sizeof(vlan_frame);
846 len += sizeof(vlan_frame);
848 ether_type = (uint16_t *)raw_pkt;
849 raw_pkt += sizeof(uint16_t);
850 len += sizeof(uint16_t);
852 if (is_customized_pctype) {
853 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
855 PMD_DRV_LOG(ERR, "unknown pctype %u.",
861 if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
862 *ether_type = fdir_input->flow.l2_flow.ether_type;
863 else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
864 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
865 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
866 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
867 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
868 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
869 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
870 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
871 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
872 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6 ||
873 is_customized_pctype) {
874 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
875 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
876 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
877 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
878 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
879 len = fill_ip4_head(fdir_input, raw_pkt,
880 next_proto[pctype], len, ether_type);
881 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
882 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
883 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
884 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
885 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
886 len = fill_ip6_head(fdir_input, raw_pkt,
887 next_proto[pctype], len,
889 } else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
890 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
891 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
892 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
893 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
895 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3) {
896 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_L2TP,
898 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
899 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_ESP,
901 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
902 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
904 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
905 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
907 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6)
908 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_ESP,
910 else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP)
911 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_UDP,
913 else if (cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3)
914 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_L2TP,
917 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
925 * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
926 * @pf: board private structure
927 * @fdir_input: input set of the flow director entry
928 * @raw_pkt: a packet to be constructed
931 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
932 const struct i40e_fdir_input *fdir_input,
933 unsigned char *raw_pkt)
935 unsigned char *payload = NULL;
937 struct rte_udp_hdr *udp;
938 struct rte_tcp_hdr *tcp;
939 struct rte_sctp_hdr *sctp;
940 struct rte_flow_item_gtp *gtp;
941 struct rte_ipv4_hdr *gtp_ipv4;
942 struct rte_ipv6_hdr *gtp_ipv6;
943 struct rte_flow_item_l2tpv3oip *l2tpv3oip;
944 struct rte_flow_item_esp *esp;
945 struct rte_ipv4_hdr *esp_ipv4;
946 struct rte_ipv6_hdr *esp_ipv6;
948 uint8_t size, dst = 0;
949 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
951 uint8_t pctype = fdir_input->pctype;
952 struct i40e_customized_pctype *cus_pctype;
954 /* raw pcket template - just copy contents of the raw packet */
955 if (fdir_input->flow_ext.pkt_template) {
956 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
957 fdir_input->flow.raw_flow.length);
961 /* fill the ethernet and IP head */
962 len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
963 !!fdir_input->flow_ext.vlan_tci);
967 /* fill the L4 head */
968 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
969 udp = (struct rte_udp_hdr *)(raw_pkt + len);
970 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
972 * The source and destination fields in the transmitted packet
973 * need to be presented in a reversed order with respect
974 * to the expected received packets.
976 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
977 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
978 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
979 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
980 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
981 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
983 * The source and destination fields in the transmitted packet
984 * need to be presented in a reversed order with respect
985 * to the expected received packets.
987 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
988 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
989 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
990 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
991 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
992 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
994 * The source and destination fields in the transmitted packet
995 * need to be presented in a reversed order with respect
996 * to the expected received packets.
998 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
999 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1000 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1001 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1002 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1003 payload = raw_pkt + len;
1004 set_idx = I40E_FLXPLD_L3_IDX;
1005 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1006 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1007 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1009 * The source and destination fields in the transmitted packet
1010 * need to be presented in a reversed order with respect
1011 * to the expected received packets.
1013 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1014 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1015 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1016 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1017 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1018 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1020 * The source and destination fields in the transmitted packet
1021 * need to be presented in a reversed order with respect
1022 * to the expected received packets.
1024 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1025 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1026 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1027 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1028 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1029 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1031 * The source and destination fields in the transmitted packet
1032 * need to be presented in a reversed order with respect
1033 * to the expected received packets.
1035 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1036 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1037 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1038 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1039 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1040 payload = raw_pkt + len;
1041 set_idx = I40E_FLXPLD_L3_IDX;
1042 } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1043 payload = raw_pkt + len;
1045 * ARP packet is a special case on which the payload
1046 * starts after the whole ARP header
1048 if (fdir_input->flow.l2_flow.ether_type ==
1049 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
1050 payload += sizeof(struct rte_arp_hdr);
1051 set_idx = I40E_FLXPLD_L2_IDX;
1052 } else if (fdir_input->flow_ext.customized_pctype) {
1053 /* If customized pctype is used */
1054 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1055 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1056 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1057 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1058 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1059 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1061 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1063 gtp = (struct rte_flow_item_gtp *)
1064 ((unsigned char *)udp +
1065 sizeof(struct rte_udp_hdr));
1067 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1068 gtp->teid = fdir_input->flow.gtp_flow.teid;
1069 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1071 /* GTP-C message type is not supported. */
1072 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1074 rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1075 gtp->v_pt_rsv_flags =
1076 I40E_FDIR_GTP_VER_FLAG_0X32;
1079 rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1080 gtp->v_pt_rsv_flags =
1081 I40E_FDIR_GTP_VER_FLAG_0X30;
1084 if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1085 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1086 gtp_ipv4 = (struct rte_ipv4_hdr *)
1087 ((unsigned char *)gtp +
1088 sizeof(struct rte_flow_item_gtp));
1089 gtp_ipv4->version_ihl =
1090 I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1091 gtp_ipv4->next_proto_id = IPPROTO_IP;
1092 gtp_ipv4->total_length =
1094 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1095 payload = (unsigned char *)gtp_ipv4 +
1096 sizeof(struct rte_ipv4_hdr);
1097 } else if (cus_pctype->index ==
1098 I40E_CUSTOMIZED_GTPU_IPV6) {
1099 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1100 gtp_ipv6 = (struct rte_ipv6_hdr *)
1101 ((unsigned char *)gtp +
1102 sizeof(struct rte_flow_item_gtp));
1103 gtp_ipv6->vtc_flow =
1105 I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1106 (0 << I40E_FDIR_IPv6_TC_OFFSET));
1107 gtp_ipv6->proto = IPPROTO_NONE;
1108 gtp_ipv6->payload_len =
1110 I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1111 gtp_ipv6->hop_limits =
1112 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1113 payload = (unsigned char *)gtp_ipv6 +
1114 sizeof(struct rte_ipv6_hdr);
1116 payload = (unsigned char *)gtp +
1117 sizeof(struct rte_flow_item_gtp);
1118 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3 ||
1119 cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3) {
1120 l2tpv3oip = (struct rte_flow_item_l2tpv3oip *)(raw_pkt
1123 if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3)
1124 l2tpv3oip->session_id =
1125 fdir_input->flow.ip4_l2tpv3oip_flow.session_id;
1127 l2tpv3oip->session_id =
1128 fdir_input->flow.ip6_l2tpv3oip_flow.session_id;
1129 payload = (unsigned char *)l2tpv3oip +
1130 sizeof(struct rte_flow_item_l2tpv3oip);
1131 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4 ||
1132 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6 ||
1133 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP ||
1134 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1135 if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1136 esp_ipv4 = (struct rte_ipv4_hdr *)
1138 esp = (struct rte_flow_item_esp *)esp_ipv4;
1140 fdir_input->flow.esp_ipv4_flow.spi;
1141 payload = (unsigned char *)esp +
1142 sizeof(struct rte_esp_hdr);
1143 len += sizeof(struct rte_esp_hdr);
1144 } else if (cus_pctype->index ==
1145 I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1146 esp_ipv4 = (struct rte_ipv4_hdr *)
1148 udp = (struct rte_udp_hdr *)esp_ipv4;
1149 udp->dst_port = rte_cpu_to_be_16
1150 (I40E_FDIR_ESP_DST_PORT);
1152 udp->dgram_len = rte_cpu_to_be_16
1153 (I40E_FDIR_UDP_DEFAULT_LEN);
1154 esp = (struct rte_flow_item_esp *)
1155 ((unsigned char *)esp_ipv4 +
1156 sizeof(struct rte_udp_hdr));
1158 fdir_input->flow.esp_ipv4_udp_flow.spi;
1159 payload = (unsigned char *)esp +
1160 sizeof(struct rte_esp_hdr);
1161 len += sizeof(struct rte_udp_hdr) +
1162 sizeof(struct rte_esp_hdr);
1163 } else if (cus_pctype->index ==
1164 I40E_CUSTOMIZED_ESP_IPV6) {
1165 esp_ipv6 = (struct rte_ipv6_hdr *)
1167 esp = (struct rte_flow_item_esp *)esp_ipv6;
1169 fdir_input->flow.esp_ipv6_flow.spi;
1170 payload = (unsigned char *)esp +
1171 sizeof(struct rte_esp_hdr);
1172 len += sizeof(struct rte_esp_hdr);
1173 } else if (cus_pctype->index ==
1174 I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1175 esp_ipv6 = (struct rte_ipv6_hdr *)
1177 udp = (struct rte_udp_hdr *)esp_ipv6;
1178 udp->dst_port = rte_cpu_to_be_16
1179 (I40E_FDIR_ESP_DST_PORT);
1181 udp->dgram_len = rte_cpu_to_be_16
1182 (I40E_FDIR_UDP_DEFAULT_LEN);
1183 esp = (struct rte_flow_item_esp *)
1184 ((unsigned char *)esp_ipv6 +
1185 sizeof(struct rte_udp_hdr));
1187 fdir_input->flow.esp_ipv6_udp_flow.spi;
1188 payload = (unsigned char *)esp +
1189 sizeof(struct rte_esp_hdr);
1190 len += sizeof(struct rte_udp_hdr) +
1191 sizeof(struct rte_esp_hdr);
1195 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1199 /* fill the flexbytes to payload */
1200 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1201 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1202 size = pf->fdir.flex_set[pit_idx].size;
1205 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1207 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1208 (void)rte_memcpy(ptr,
1209 &fdir_input->flow_ext.flexbytes[dst],
1210 size * sizeof(uint16_t));
1216 /* Construct the tx flags */
1217 static inline uint64_t
1218 i40e_build_ctob(uint32_t td_cmd,
1223 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1224 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
1225 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1226 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1227 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
1231 * check the programming status descriptor in rx queue.
1232 * done after Programming Flow Director is programmed on
1236 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1238 volatile union i40e_rx_desc *rxdp;
1245 rxdp = &rxq->rx_ring[rxq->rx_tail];
1246 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1247 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1248 >> I40E_RXD_QW1_STATUS_SHIFT;
1250 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1251 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1252 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1253 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1255 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1256 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1258 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1259 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1260 if (error == (0x1 <<
1261 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1262 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1263 " (FD_ID %u): programming status"
1265 rxdp->wb.qword0.hi_dword.fd_id);
1267 } else if (error == (0x1 <<
1268 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1269 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1270 " (FD_ID %u): programming status"
1272 rxdp->wb.qword0.hi_dword.fd_id);
1275 PMD_DRV_LOG(ERR, "invalid programming status"
1276 " reported, error = %u.", error);
1278 PMD_DRV_LOG(INFO, "unknown programming status"
1279 " reported, len = %d, id = %u.", len, id);
1280 rxdp->wb.qword1.status_error_len = 0;
1282 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1284 if (rxq->rx_tail == 0)
1285 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1287 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1294 i40e_fdir_programming_status_cleanup(struct i40e_rx_queue *rxq)
1296 uint16_t retry_count = 0;
1298 /* capture the previous error report(if any) from rx ring */
1299 while ((i40e_check_fdir_programming_status(rxq) < 0) &&
1300 (++retry_count < I40E_FDIR_NUM_RX_DESC))
1301 PMD_DRV_LOG(INFO, "error report captured.");
1305 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1306 struct i40e_fdir_filter *filter)
1308 rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1309 if (input->input.flow_ext.pkt_template) {
1310 filter->fdir.input.flow.raw_flow.packet = NULL;
1311 filter->fdir.input.flow.raw_flow.length =
1312 rte_hash_crc(input->input.flow.raw_flow.packet,
1313 input->input.flow.raw_flow.length,
1314 input->input.flow.raw_flow.pctype);
1319 /* Check if there exists the flow director filter */
1320 static struct i40e_fdir_filter *
1321 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1322 const struct i40e_fdir_input *input)
1326 if (input->flow_ext.pkt_template)
1327 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1328 (const void *)input,
1329 input->flow.raw_flow.length);
1331 ret = rte_hash_lookup(fdir_info->hash_table,
1332 (const void *)input);
1336 return fdir_info->hash_map[ret];
1339 /* Add a flow director filter into the SW list */
1341 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1343 struct i40e_fdir_info *fdir_info = &pf->fdir;
1344 struct i40e_fdir_filter *hash_filter;
1347 if (filter->fdir.input.flow_ext.pkt_template)
1348 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1349 &filter->fdir.input,
1350 filter->fdir.input.flow.raw_flow.length);
1352 ret = rte_hash_add_key(fdir_info->hash_table,
1353 &filter->fdir.input);
1356 "Failed to insert fdir filter to hash table %d!",
1361 if (fdir_info->hash_map[ret])
1364 hash_filter = &fdir_info->fdir_filter_array[ret];
1365 rte_memcpy(hash_filter, filter, sizeof(*filter));
1366 fdir_info->hash_map[ret] = hash_filter;
1367 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, hash_filter, rules);
1372 /* Delete a flow director filter from the SW list */
1374 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1376 struct i40e_fdir_info *fdir_info = &pf->fdir;
1377 struct i40e_fdir_filter *filter;
1380 if (input->flow_ext.pkt_template)
1381 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1383 input->flow.raw_flow.length);
1385 ret = rte_hash_del_key(fdir_info->hash_table, input);
1388 "Failed to delete fdir filter to hash table %d!",
1392 filter = fdir_info->hash_map[ret];
1393 fdir_info->hash_map[ret] = NULL;
1395 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1401 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info)
1403 struct rte_flow *flow = NULL;
1409 if (fdir_info->fdir_actual_cnt >=
1410 fdir_info->fdir_space_size) {
1411 PMD_DRV_LOG(ERR, "Fdir space full");
1415 ret = rte_bitmap_scan(fdir_info->fdir_flow_pool.bitmap, &pos,
1418 /* normally this won't happen as the fdir_actual_cnt should be
1419 * same with the number of the set bits in fdir_flow_pool,
1420 * but anyway handle this error condition here for safe
1423 PMD_DRV_LOG(ERR, "fdir_actual_cnt out of sync");
1427 i = rte_bsf64(slab);
1429 rte_bitmap_clear(fdir_info->fdir_flow_pool.bitmap, pos);
1430 flow = &fdir_info->fdir_flow_pool.pool[pos].flow;
1432 memset(flow, 0, sizeof(struct rte_flow));
1438 i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info,
1439 struct rte_flow *flow)
1441 struct i40e_fdir_entry *f;
1443 f = FLOW_TO_FLOW_BITMAP(flow);
1444 rte_bitmap_set(fdir_info->fdir_flow_pool.bitmap, f->idx);
1448 i40e_flow_store_flex_pit(struct i40e_pf *pf,
1449 struct i40e_fdir_flex_pit *flex_pit,
1450 enum i40e_flxpld_layer_idx layer_idx,
1455 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
1456 /* Check if the configuration is conflicted */
1457 if (pf->fdir.flex_pit_flag[layer_idx] &&
1458 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
1459 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
1460 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
1463 /* Check if the configuration exists. */
1464 if (pf->fdir.flex_pit_flag[layer_idx] &&
1465 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
1466 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
1467 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
1470 pf->fdir.flex_set[field_idx].src_offset =
1471 flex_pit->src_offset;
1472 pf->fdir.flex_set[field_idx].size =
1474 pf->fdir.flex_set[field_idx].dst_offset =
1475 flex_pit->dst_offset;
1481 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
1482 enum i40e_flxpld_layer_idx layer_idx,
1485 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1486 uint32_t flx_pit, flx_ort;
1487 uint16_t min_next_off = 0;
1492 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
1493 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
1494 (layer_idx * I40E_MAX_FLXPLD_FIED);
1495 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
1499 for (i = 0; i < raw_id; i++) {
1500 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
1501 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
1502 pf->fdir.flex_set[field_idx].size,
1503 pf->fdir.flex_set[field_idx].dst_offset);
1505 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
1506 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
1507 pf->fdir.flex_set[field_idx].size;
1510 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
1511 /* set the non-used register obeying register's constrain */
1512 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
1513 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
1514 NONUSE_FLX_PIT_DEST_OFF);
1515 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
1521 i40e_flow_store_flex_mask(struct i40e_pf *pf,
1522 enum i40e_filter_pctype pctype,
1525 struct i40e_fdir_flex_mask flex_mask;
1526 uint8_t nb_bitmask = 0;
1530 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
1531 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
1532 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
1534 flex_mask.word_mask |=
1535 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
1536 if (mask_tmp != UINT16_MAX) {
1537 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
1538 flex_mask.bitmask[nb_bitmask].offset =
1539 i / sizeof(uint16_t);
1541 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
1546 flex_mask.nb_bitmask = nb_bitmask;
1548 if (pf->fdir.flex_mask_flag[pctype] &&
1549 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
1550 sizeof(struct i40e_fdir_flex_mask))))
1552 else if (pf->fdir.flex_mask_flag[pctype] &&
1553 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
1554 sizeof(struct i40e_fdir_flex_mask))))
1557 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
1558 sizeof(struct i40e_fdir_flex_mask));
1563 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
1564 enum i40e_filter_pctype pctype)
1566 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1567 struct i40e_fdir_flex_mask *flex_mask;
1568 uint32_t flxinset, fd_mask;
1572 flex_mask = &pf->fdir.flex_mask[pctype];
1573 flxinset = (flex_mask->word_mask <<
1574 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
1575 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
1576 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
1578 for (i = 0; i < flex_mask->nb_bitmask; i++) {
1579 fd_mask = (flex_mask->bitmask[i].mask <<
1580 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
1581 I40E_PRTQF_FD_MSK_MASK_MASK;
1582 fd_mask |= ((flex_mask->bitmask[i].offset +
1583 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
1584 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
1585 I40E_PRTQF_FD_MSK_OFFSET_MASK;
1586 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
1589 pf->fdir.flex_mask_flag[pctype] = 1;
1593 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
1594 enum i40e_filter_pctype pctype,
1597 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
1598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1599 uint64_t inset_reg = 0;
1602 /* Check if the input set is valid */
1603 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
1605 PMD_DRV_LOG(ERR, "Invalid input set");
1609 /* Check if the configuration is conflicted */
1610 if (pf->fdir.inset_flag[pctype] &&
1611 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) {
1612 PMD_DRV_LOG(ERR, "Conflict with the first rule's input set.");
1616 if (pf->fdir.inset_flag[pctype] &&
1617 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
1620 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
1621 I40E_INSET_MASK_NUM_REG);
1623 PMD_DRV_LOG(ERR, "Invalid pattern mask.");
1627 if (pf->support_multi_driver) {
1628 for (i = 0; i < num; i++)
1629 if (i40e_read_rx_ctl(hw,
1630 I40E_GLQF_FD_MSK(i, pctype)) !=
1632 PMD_DRV_LOG(ERR, "Input set setting is not"
1634 " `support-multi-driver`"
1638 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
1639 if (i40e_read_rx_ctl(hw,
1640 I40E_GLQF_FD_MSK(i, pctype)) != 0) {
1641 PMD_DRV_LOG(ERR, "Input set setting is not"
1643 " `support-multi-driver`"
1649 for (i = 0; i < num; i++)
1650 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
1652 /*clear unused mask registers of the pctype */
1653 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
1654 i40e_check_write_reg(hw,
1655 I40E_GLQF_FD_MSK(i, pctype), 0);
1658 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
1660 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
1661 (uint32_t)(inset_reg & UINT32_MAX));
1662 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
1663 (uint32_t)((inset_reg >>
1664 I40E_32_BIT_WIDTH) & UINT32_MAX));
1666 I40E_WRITE_FLUSH(hw);
1668 pf->fdir.input_set[pctype] = input_set;
1669 pf->fdir.inset_flag[pctype] = 1;
1673 static inline unsigned char *
1674 i40e_find_available_buffer(struct rte_eth_dev *dev)
1676 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1677 struct i40e_fdir_info *fdir_info = &pf->fdir;
1678 struct i40e_tx_queue *txq = pf->fdir.txq;
1680 /* no available buffer
1681 * search for more available buffers from the current
1682 * descriptor, until an unavailable one
1684 if (fdir_info->txq_available_buf_count <= 0) {
1686 volatile struct i40e_tx_desc *tmp_txdp;
1688 tmp_tail = txq->tx_tail;
1689 tmp_txdp = &txq->tx_ring[tmp_tail + 1];
1692 if ((tmp_txdp->cmd_type_offset_bsz &
1693 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1694 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1695 fdir_info->txq_available_buf_count++;
1700 if (tmp_tail >= txq->nb_tx_desc)
1702 } while (tmp_tail != txq->tx_tail);
1705 if (fdir_info->txq_available_buf_count > 0)
1706 fdir_info->txq_available_buf_count--;
1709 return (unsigned char *)fdir_info->prg_pkt[txq->tx_tail >> 1];
1713 * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1714 * @pf: board private structure
1715 * @filter: fdir filter entry
1716 * @add: 0 - delete, 1 - add
1719 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1720 const struct i40e_fdir_filter_conf *filter,
1723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1725 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
1726 struct i40e_fdir_info *fdir_info = &pf->fdir;
1727 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
1728 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1729 struct i40e_fdir_flex_pit flex_pit;
1730 enum i40e_filter_pctype pctype;
1731 struct i40e_fdir_filter *node;
1732 unsigned char *pkt = NULL;
1733 bool cfg_flex_pit = true;
1734 bool wait_status = true;
1739 if (pf->fdir.fdir_vsi == NULL) {
1740 PMD_DRV_LOG(ERR, "FDIR is not enabled");
1744 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1745 PMD_DRV_LOG(ERR, "Invalid queue ID");
1748 if (filter->input.flow_ext.is_vf &&
1749 filter->input.flow_ext.dst_id >= pf->vf_num) {
1750 PMD_DRV_LOG(ERR, "Invalid VF ID");
1753 if (filter->input.flow_ext.pkt_template) {
1754 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1755 !filter->input.flow.raw_flow.packet) {
1756 PMD_DRV_LOG(ERR, "Invalid raw packet template"
1757 " flow filter parameters!");
1760 pctype = filter->input.flow.raw_flow.pctype;
1762 pctype = filter->input.pctype;
1765 /* Check if there is the filter in SW list */
1766 memset(&check_filter, 0, sizeof(check_filter));
1767 i40e_fdir_filter_convert(filter, &check_filter);
1770 /* configure the input set for common PCTYPEs*/
1771 if (!filter->input.flow_ext.customized_pctype) {
1772 ret = i40e_flow_set_fdir_inset(pf, pctype,
1773 filter->input.flow_ext.input_set);
1778 if (filter->input.flow_ext.is_flex_flow) {
1779 for (i = 0; i < filter->input.flow_ext.raw_id; i++) {
1780 layer_idx = filter->input.flow_ext.layer_idx;
1781 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
1782 flex_pit = filter->input.flow_ext.flex_pit[field_idx];
1784 /* Store flex pit to SW */
1785 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
1788 PMD_DRV_LOG(ERR, "Conflict with the"
1789 " first flexible rule.");
1791 } else if (ret > 0) {
1792 cfg_flex_pit = false;
1797 i40e_flow_set_fdir_flex_pit(pf, layer_idx,
1798 filter->input.flow_ext.raw_id);
1800 /* Store flex mask to SW */
1801 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++)
1803 filter->input.flow_ext.flex_mask[i];
1805 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
1807 PMD_DRV_LOG(ERR, "Exceed maximal"
1808 " number of bitmasks");
1810 } else if (ret == -2) {
1811 PMD_DRV_LOG(ERR, "Conflict with the"
1812 " first flexible rule");
1814 } else if (ret == 0) {
1815 i40e_flow_set_fdir_flex_msk(pf, pctype);
1819 ret = i40e_sw_fdir_filter_insert(pf, &check_filter);
1822 "Conflict with existing flow director rules!");
1826 if (fdir_info->fdir_invalprio == 1 &&
1827 fdir_info->fdir_guarantee_free_space > 0)
1828 wait_status = false;
1830 if (filter->input.flow_ext.is_flex_flow)
1831 layer_idx = filter->input.flow_ext.layer_idx;
1833 node = i40e_sw_fdir_filter_lookup(fdir_info,
1834 &check_filter.fdir.input);
1837 "There's no corresponding flow firector filter!");
1841 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1844 "Error deleting fdir rule from hash table!");
1848 pf->fdir.flex_mask_flag[pctype] = 0;
1850 if (fdir_info->fdir_invalprio == 1)
1851 wait_status = false;
1854 /* find a buffer to store the pkt */
1855 pkt = i40e_find_available_buffer(dev);
1859 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1860 ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1862 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1866 if (hw->mac.type == I40E_MAC_X722) {
1867 /* get translated pctype value in fd pctype register */
1868 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1869 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1872 ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add,
1875 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1880 if (filter->input.flow_ext.is_flex_flow) {
1882 fdir_info->flex_flow_count[layer_idx]++;
1883 pf->fdir.flex_pit_flag[layer_idx] = 1;
1885 fdir_info->flex_flow_count[layer_idx]--;
1886 if (!fdir_info->flex_flow_count[layer_idx])
1887 pf->fdir.flex_pit_flag[layer_idx] = 0;
1892 fdir_info->fdir_actual_cnt++;
1893 if (fdir_info->fdir_invalprio == 1 &&
1894 fdir_info->fdir_guarantee_free_space > 0)
1895 fdir_info->fdir_guarantee_free_space--;
1897 fdir_info->fdir_actual_cnt--;
1898 if (fdir_info->fdir_invalprio == 1 &&
1899 fdir_info->fdir_guarantee_free_space <
1900 fdir_info->fdir_guarantee_total_space)
1901 fdir_info->fdir_guarantee_free_space++;
1909 i40e_sw_fdir_filter_del(pf, &check_filter.fdir.input);
1911 i40e_sw_fdir_filter_insert(pf, &check_filter);
1917 * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1918 * Is done by Flow Director Programming Descriptor followed by packet
1919 * structure that contains the filter fields need to match.
1920 * @pf: board private structure
1922 * @filter: fdir filter entry
1923 * @add: 0 - delete, 1 - add
1926 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1927 enum i40e_filter_pctype pctype,
1928 const struct i40e_fdir_filter_conf *filter,
1929 bool add, bool wait_status)
1931 struct i40e_tx_queue *txq = pf->fdir.txq;
1932 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1933 const struct i40e_fdir_action *fdir_action = &filter->action;
1934 volatile struct i40e_tx_desc *txdp;
1935 volatile struct i40e_filter_program_desc *fdirdp;
1941 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1942 fdirdp = (volatile struct i40e_filter_program_desc *)
1943 (&txq->tx_ring[txq->tx_tail]);
1945 fdirdp->qindex_flex_ptype_vsi =
1946 rte_cpu_to_le_32((fdir_action->rx_queue <<
1947 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1948 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1950 fdirdp->qindex_flex_ptype_vsi |=
1951 rte_cpu_to_le_32((fdir_action->flex_off <<
1952 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1953 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1955 fdirdp->qindex_flex_ptype_vsi |=
1956 rte_cpu_to_le_32((pctype <<
1957 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1958 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1960 if (filter->input.flow_ext.is_vf)
1961 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1963 /* Use LAN VSI Id by default */
1964 vsi_id = pf->main_vsi->vsi_id;
1965 fdirdp->qindex_flex_ptype_vsi |=
1966 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1967 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1968 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1970 fdirdp->dtype_cmd_cntindex =
1971 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1974 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1975 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1976 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1978 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1979 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1980 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1982 if (fdir_action->behavior == I40E_FDIR_REJECT)
1983 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1984 else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1985 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1986 else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1987 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1989 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1993 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1994 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1995 I40E_TXD_FLTR_QW1_DEST_MASK);
1997 fdirdp->dtype_cmd_cntindex |=
1998 rte_cpu_to_le_32((fdir_action->report_status <<
1999 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
2000 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
2002 fdirdp->dtype_cmd_cntindex |=
2003 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
2004 fdirdp->dtype_cmd_cntindex |=
2006 ((uint32_t)pf->fdir.match_counter_index <<
2007 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2008 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
2010 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
2012 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
2013 txdp = &txq->tx_ring[txq->tx_tail + 1];
2014 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr[txq->tx_tail >> 1]);
2016 td_cmd = I40E_TX_DESC_CMD_EOP |
2017 I40E_TX_DESC_CMD_RS |
2018 I40E_TX_DESC_CMD_DUMMY;
2020 txdp->cmd_type_offset_bsz =
2021 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
2023 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
2024 if (txq->tx_tail >= txq->nb_tx_desc)
2026 /* Update the tx tail register */
2029 /* fdir program rx queue cleanup */
2030 i40e_fdir_programming_status_cleanup(rxq);
2032 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2035 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
2036 if ((txdp->cmd_type_offset_bsz &
2037 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
2038 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
2042 if (i >= I40E_FDIR_MAX_WAIT_US) {
2044 "Failed to program FDIR filter: time out to get DD on tx queue.");
2047 /* totally delay 10 ms to check programming status*/
2048 rte_delay_us(I40E_FDIR_MAX_WAIT_US);
2049 if (i40e_check_fdir_programming_status(rxq) < 0) {
2051 "Failed to program FDIR filter: programming status reported.");
2060 * i40e_fdir_flush - clear all filters of Flow Director table
2061 * @pf: board private structure
2064 i40e_fdir_flush(struct rte_eth_dev *dev)
2066 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2067 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2069 uint16_t guarant_cnt, best_cnt;
2072 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
2073 I40E_WRITE_FLUSH(hw);
2075 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
2076 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
2077 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
2078 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
2081 if (i >= I40E_FDIR_FLUSH_RETRY) {
2082 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
2085 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2086 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2087 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2088 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2089 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2090 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2091 if (guarant_cnt != 0 || best_cnt != 0) {
2092 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
2095 PMD_DRV_LOG(INFO, "FD table Flush success.");
2100 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
2101 struct rte_eth_flex_payload_cfg *flex_set,
2104 struct i40e_fdir_flex_pit *flex_pit;
2105 struct rte_eth_flex_payload_cfg *ptr = flex_set;
2106 uint16_t src, dst, size, j, k;
2107 uint8_t i, layer_idx;
2109 for (layer_idx = I40E_FLXPLD_L2_IDX;
2110 layer_idx <= I40E_FLXPLD_L4_IDX;
2112 if (layer_idx == I40E_FLXPLD_L2_IDX)
2113 ptr->type = RTE_ETH_L2_PAYLOAD;
2114 else if (layer_idx == I40E_FLXPLD_L3_IDX)
2115 ptr->type = RTE_ETH_L3_PAYLOAD;
2116 else if (layer_idx == I40E_FLXPLD_L4_IDX)
2117 ptr->type = RTE_ETH_L4_PAYLOAD;
2119 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
2120 flex_pit = &pf->fdir.flex_set[layer_idx *
2121 I40E_MAX_FLXPLD_FIED + i];
2122 if (flex_pit->size == 0)
2124 src = flex_pit->src_offset * sizeof(uint16_t);
2125 dst = flex_pit->dst_offset * sizeof(uint16_t);
2126 size = flex_pit->size * sizeof(uint16_t);
2127 for (j = src, k = dst; j < src + size; j++, k++)
2128 ptr->src_offset[k] = j;
2136 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
2137 struct rte_eth_fdir_flex_mask *flex_mask,
2140 struct i40e_fdir_flex_mask *mask;
2141 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
2144 uint16_t off_bytes, mask_tmp;
2146 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2147 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
2149 mask = &pf->fdir.flex_mask[i];
2150 flow_type = i40e_pctype_to_flowtype(pf->adapter,
2151 (enum i40e_filter_pctype)i);
2152 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
2155 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
2156 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
2157 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
2158 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
2160 ptr->mask[j * sizeof(uint16_t)] = 0x0;
2161 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
2164 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
2165 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
2166 mask_tmp = ~mask->bitmask[j].mask;
2167 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
2168 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
2170 ptr->flow_type = flow_type;
2177 * i40e_fdir_info_get - get information of Flow Director
2178 * @pf: ethernet device to get info from
2179 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
2180 * the flow director information.
2183 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2186 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2187 uint16_t num_flex_set = 0;
2188 uint16_t num_flex_mask = 0;
2191 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2192 fdir->mode = RTE_FDIR_MODE_PERFECT;
2194 fdir->mode = RTE_FDIR_MODE_NONE;
2197 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2199 (uint32_t)hw->func_caps.fd_filters_best_effort;
2200 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2201 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2202 for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2203 fdir->flow_types_mask[i] = 0ULL;
2204 fdir->flex_payload_unit = sizeof(uint16_t);
2205 fdir->flex_bitmask_unit = sizeof(uint16_t);
2206 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2207 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2208 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2210 i40e_fdir_info_get_flex_set(pf,
2211 fdir->flex_conf.flex_set,
2213 i40e_fdir_info_get_flex_mask(pf,
2214 fdir->flex_conf.flex_mask,
2217 fdir->flex_conf.nb_payloads = num_flex_set;
2218 fdir->flex_conf.nb_flexmasks = num_flex_mask;
2222 * i40e_fdir_stat_get - get statistics of Flow Director
2223 * @pf: ethernet device to get info from
2224 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2225 * the flow director statistics.
2228 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2230 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2231 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2234 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2236 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2237 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2239 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2240 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2243 /* Restore flow director filter */
2245 i40e_fdir_filter_restore(struct i40e_pf *pf)
2247 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2248 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2249 struct i40e_fdir_filter *f;
2250 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2252 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
2253 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
2255 TAILQ_FOREACH(f, fdir_list, rules)
2256 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2258 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2260 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2261 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2263 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2264 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2266 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
2267 guarant_cnt, best_cnt);