4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
70 #define I40E_FDIR_IPv6_TC_OFFSET 20
72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
73 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
74 #define I40E_FDIR_UDP_DEFAULT_LEN 400
76 /* Wait count and interval for fdir filter programming */
77 #define I40E_FDIR_WAIT_COUNT 10
78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
80 /* Wait count and interval for fdir filter flush */
81 #define I40E_FDIR_FLUSH_RETRY 50
82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
84 #define I40E_COUNTER_PF 2
85 /* Statistic counter index for one pf */
86 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
87 #define I40E_MAX_FLX_SOURCE_OFF 480
88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
90 #define NONUSE_FLX_PIT_DEST_OFF 63
91 #define NONUSE_FLX_PIT_FSIZE 1
92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
93 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
94 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
95 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
96 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
97 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
98 NONUSE_FLX_PIT_DEST_OFF : \
99 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
100 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
101 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
103 #define I40E_FDIR_FLOWS ( \
104 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
105 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
106 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
107 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
108 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
109 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
110 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
111 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
112 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
113 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
114 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
119 enum i40e_filter_pctype pctype,
120 const struct rte_eth_fdir_filter *filter,
122 static int i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
123 struct i40e_fdir_filter *filter);
124 static struct i40e_fdir_filter *
125 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
126 const struct rte_eth_fdir_input *input);
127 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
128 struct i40e_fdir_filter *filter);
131 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
133 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
134 struct i40e_hmc_obj_rxq rx_ctx;
135 int err = I40E_SUCCESS;
137 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
138 /* Init the RX queue in hardware */
139 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
141 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
142 rx_ctx.qlen = rxq->nb_rx_desc;
143 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
146 rx_ctx.dtype = i40e_header_split_none;
147 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
148 rx_ctx.rxmax = ETHER_MAX_LEN;
149 rx_ctx.tphrdesc_ena = 1;
150 rx_ctx.tphwdesc_ena = 1;
151 rx_ctx.tphdata_ena = 1;
152 rx_ctx.tphhead_ena = 1;
153 rx_ctx.lrxqthresh = 2;
159 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
160 if (err != I40E_SUCCESS) {
161 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
164 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
165 if (err != I40E_SUCCESS) {
166 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
169 rxq->qrx_tail = hw->hw_addr +
170 I40E_QRX_TAIL(rxq->vsi->base_queue);
173 /* Init the RX tail regieter. */
174 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
175 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
181 * i40e_fdir_setup - reserve and initialize the Flow Director resources
182 * @pf: board private structure
185 i40e_fdir_setup(struct i40e_pf *pf)
187 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
188 struct i40e_vsi *vsi;
189 int err = I40E_SUCCESS;
190 char z_name[RTE_MEMZONE_NAMESIZE];
191 const struct rte_memzone *mz = NULL;
192 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
194 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
195 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
196 return I40E_NOT_SUPPORTED;
199 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
200 " num_filters_best_effort = %u.",
201 hw->func_caps.fd_filters_guaranteed,
202 hw->func_caps.fd_filters_best_effort);
204 vsi = pf->fdir.fdir_vsi;
206 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
209 /* make new FDIR VSI */
210 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
212 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
213 return I40E_ERR_NO_AVAILABLE_VSI;
215 pf->fdir.fdir_vsi = vsi;
217 /*Fdir tx queue setup*/
218 err = i40e_fdir_setup_tx_resources(pf);
220 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
224 /*Fdir rx queue setup*/
225 err = i40e_fdir_setup_rx_resources(pf);
227 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
231 err = i40e_tx_queue_init(pf->fdir.txq);
233 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
237 /* need switch on before dev start*/
238 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
240 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
244 /* Init the rx queue in hardware */
245 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
247 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
251 /* switch on rx queue */
252 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
254 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
258 /* reserve memory for the fdir programming packet */
259 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
260 eth_dev->data->drv_name,
262 eth_dev->data->port_id);
263 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
265 PMD_DRV_LOG(ERR, "Cannot init memzone for "
266 "flow director program packet.");
267 err = I40E_ERR_NO_MEMORY;
270 pf->fdir.prg_pkt = mz->addr;
271 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
273 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
274 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
279 i40e_dev_rx_queue_release(pf->fdir.rxq);
282 i40e_dev_tx_queue_release(pf->fdir.txq);
285 i40e_vsi_release(vsi);
286 pf->fdir.fdir_vsi = NULL;
291 * i40e_fdir_teardown - release the Flow Director resources
292 * @pf: board private structure
295 i40e_fdir_teardown(struct i40e_pf *pf)
297 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
298 struct i40e_vsi *vsi;
300 vsi = pf->fdir.fdir_vsi;
303 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
305 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
306 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
308 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
309 i40e_dev_rx_queue_release(pf->fdir.rxq);
311 i40e_dev_tx_queue_release(pf->fdir.txq);
313 i40e_vsi_release(vsi);
314 pf->fdir.fdir_vsi = NULL;
317 /* check whether the flow director table in empty */
319 i40e_fdir_empty(struct i40e_hw *hw)
321 uint32_t guarant_cnt, best_cnt;
323 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
324 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
325 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
326 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
327 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
328 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
329 if (best_cnt + guarant_cnt > 0)
336 * Initialize the configuration about bytes stream extracted as flexible payload
340 i40e_init_flx_pld(struct i40e_pf *pf)
342 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
347 * Define the bytes stream extracted as flexible payload in
348 * field vector. By default, select 8 words from the beginning
349 * of payload as flexible payload.
351 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
352 index = i * I40E_MAX_FLXPLD_FIED;
353 pf->fdir.flex_set[index].src_offset = 0;
354 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
355 pf->fdir.flex_set[index].dst_offset = 0;
356 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
358 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
360 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
363 /* initialize the masks */
364 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
365 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
366 if (hw->mac.type == I40E_MAC_X722) {
367 if (!I40E_VALID_PCTYPE_X722(
368 (enum i40e_filter_pctype)pctype))
371 if (!I40E_VALID_PCTYPE(
372 (enum i40e_filter_pctype)pctype))
375 pf->fdir.flex_mask[pctype].word_mask = 0;
376 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
377 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
378 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
379 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
380 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
385 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
387 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
388 if ((flex_pit2).src_offset < \
389 (flex_pit1).src_offset + (flex_pit1).size) { \
390 PMD_DRV_LOG(ERR, "src_offset should be not" \
391 " less than than previous offset" \
392 " + previous FSIZE."); \
398 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
399 * and the flex_pit will be sorted by it's src_offset value
401 static inline uint16_t
402 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
403 struct i40e_fdir_flex_pit *flex_pit)
405 uint16_t src_tmp, size, num = 0;
406 uint16_t i, k, j = 0;
408 while (j < I40E_FDIR_MAX_FLEX_LEN) {
410 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
411 if (src_offset[j + 1] == src_offset[j] + 1)
416 src_tmp = src_offset[j] + 1 - size;
417 /* the flex_pit need to be sort by src_offset */
418 for (i = 0; i < num; i++) {
419 if (src_tmp < flex_pit[i].src_offset)
422 /* if insert required, move backward */
423 for (k = num; k > i; k--)
424 flex_pit[k] = flex_pit[k - 1];
426 flex_pit[i].dst_offset = j + 1 - size;
427 flex_pit[i].src_offset = src_tmp;
428 flex_pit[i].size = size;
435 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
437 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
439 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
442 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
443 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
444 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
449 memset(flex_pit, 0, sizeof(flex_pit));
450 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
451 if (num > I40E_MAX_FLXPLD_FIED) {
452 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
455 for (i = 0; i < num; i++) {
456 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
457 flex_pit[i].src_offset & 0x01) {
458 PMD_DRV_LOG(ERR, "flexpayload should be measured"
463 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
469 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
470 * arguments are valid
473 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
475 const struct rte_eth_flex_payload_cfg *flex_cfg;
476 const struct rte_eth_fdir_flex_mask *flex_mask;
483 PMD_DRV_LOG(INFO, "NULL pointer.");
486 /* check flexible payload setting configuration */
487 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
488 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
491 for (i = 0; i < conf->nb_payloads; i++) {
492 flex_cfg = &conf->flex_set[i];
493 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
494 PMD_DRV_LOG(ERR, "invalid payload type.");
497 ret = i40e_check_fdir_flex_payload(flex_cfg);
499 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
504 /* check flex mask setting configuration */
505 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
506 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
509 for (i = 0; i < conf->nb_flexmasks; i++) {
510 flex_mask = &conf->flex_mask[i];
511 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
512 PMD_DRV_LOG(WARNING, "invalid flow type.");
516 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
517 mask_tmp = I40E_WORD(flex_mask->mask[j],
518 flex_mask->mask[j + 1]);
519 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
521 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
522 PMD_DRV_LOG(ERR, " exceed maximal"
523 " number of bitmasks.");
533 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
534 * @pf: board private structure
535 * @cfg: the rule how bytes stream is extracted as flexible payload
538 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
539 const struct rte_eth_flex_payload_cfg *cfg)
541 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
542 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
544 uint16_t num, min_next_off; /* in words */
545 uint8_t field_idx = 0;
546 uint8_t layer_idx = 0;
549 if (cfg->type == RTE_ETH_L2_PAYLOAD)
550 layer_idx = I40E_FLXPLD_L2_IDX;
551 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
552 layer_idx = I40E_FLXPLD_L3_IDX;
553 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
554 layer_idx = I40E_FLXPLD_L4_IDX;
556 memset(flex_pit, 0, sizeof(flex_pit));
557 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
559 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
560 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
561 /* record the info in fdir structure */
562 pf->fdir.flex_set[field_idx].src_offset =
563 flex_pit[i].src_offset / sizeof(uint16_t);
564 pf->fdir.flex_set[field_idx].size =
565 flex_pit[i].size / sizeof(uint16_t);
566 pf->fdir.flex_set[field_idx].dst_offset =
567 flex_pit[i].dst_offset / sizeof(uint16_t);
568 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
569 pf->fdir.flex_set[field_idx].size,
570 pf->fdir.flex_set[field_idx].dst_offset);
572 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
574 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
575 pf->fdir.flex_set[field_idx].size;
577 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
578 /* set the non-used register obeying register's constrain */
579 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
580 NONUSE_FLX_PIT_DEST_OFF);
582 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
589 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
590 * @pf: board private structure
591 * @pctype: packet classify type
592 * @flex_masks: mask for flexible payload
595 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
596 enum i40e_filter_pctype pctype,
597 const struct rte_eth_fdir_flex_mask *mask_cfg)
599 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
600 struct i40e_fdir_flex_mask *flex_mask;
601 uint32_t flxinset, fd_mask;
603 uint8_t i, nb_bitmask = 0;
605 flex_mask = &pf->fdir.flex_mask[pctype];
606 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
607 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
608 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
609 if (mask_tmp != 0x0) {
610 flex_mask->word_mask |=
611 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
612 if (mask_tmp != UINT16_MAX) {
614 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
615 flex_mask->bitmask[nb_bitmask].offset =
616 i / sizeof(uint16_t);
621 /* write mask to hw */
622 flxinset = (flex_mask->word_mask <<
623 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
624 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
625 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
627 for (i = 0; i < nb_bitmask; i++) {
628 fd_mask = (flex_mask->bitmask[i].mask <<
629 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
630 I40E_PRTQF_FD_MSK_MASK_MASK;
631 fd_mask |= ((flex_mask->bitmask[i].offset +
632 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
633 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
634 I40E_PRTQF_FD_MSK_OFFSET_MASK;
635 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
640 * Configure flow director related setting
643 i40e_fdir_configure(struct rte_eth_dev *dev)
645 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
646 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
647 struct rte_eth_fdir_flex_conf *conf;
648 enum i40e_filter_pctype pctype;
654 * configuration need to be done before
655 * flow director filters are added
656 * If filters exist, flush them.
658 if (i40e_fdir_empty(hw) < 0) {
659 ret = i40e_fdir_flush(dev);
661 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
666 /* enable FDIR filter */
667 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
668 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
669 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
671 i40e_init_flx_pld(pf); /* set flex config to default value */
673 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
674 ret = i40e_check_fdir_flex_conf(conf);
676 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
679 /* configure flex payload */
680 for (i = 0; i < conf->nb_payloads; i++)
681 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
682 /* configure flex mask*/
683 for (i = 0; i < conf->nb_flexmasks; i++) {
684 if (hw->mac.type == I40E_MAC_X722) {
685 /* get translated pctype value in fd pctype register */
686 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
687 hw, I40E_GLQF_FD_PCTYPES(
688 (int)i40e_flowtype_to_pctype(
689 conf->flex_mask[i].flow_type)));
691 pctype = i40e_flowtype_to_pctype(
692 conf->flex_mask[i].flow_type);
694 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
701 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
702 unsigned char *raw_pkt,
705 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
706 uint16_t *ether_type;
707 uint8_t len = 2 * sizeof(struct ether_addr);
709 struct ipv6_hdr *ip6;
710 static const uint8_t next_proto[] = {
711 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
712 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
713 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
714 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
715 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
716 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
717 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
718 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
719 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
720 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
723 raw_pkt += 2 * sizeof(struct ether_addr);
724 if (vlan && fdir_input->flow_ext.vlan_tci) {
725 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
726 rte_memcpy(raw_pkt + sizeof(uint16_t),
727 &fdir_input->flow_ext.vlan_tci,
729 raw_pkt += sizeof(vlan_frame);
730 len += sizeof(vlan_frame);
732 ether_type = (uint16_t *)raw_pkt;
733 raw_pkt += sizeof(uint16_t);
734 len += sizeof(uint16_t);
736 switch (fdir_input->flow_type) {
737 case RTE_ETH_FLOW_L2_PAYLOAD:
738 *ether_type = fdir_input->flow.l2_flow.ether_type;
740 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
741 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
742 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
743 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
744 case RTE_ETH_FLOW_FRAG_IPV4:
745 ip = (struct ipv4_hdr *)raw_pkt;
747 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
748 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
749 /* set len to by default */
750 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
751 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
752 fdir_input->flow.ip4_flow.proto :
753 next_proto[fdir_input->flow_type];
754 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
755 fdir_input->flow.ip4_flow.ttl :
756 I40E_FDIR_IP_DEFAULT_TTL;
757 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
759 * The source and destination fields in the transmitted packet
760 * need to be presented in a reversed order with respect
761 * to the expected received packets.
763 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
764 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
765 len += sizeof(struct ipv4_hdr);
767 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
768 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
769 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
770 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
771 case RTE_ETH_FLOW_FRAG_IPV6:
772 ip6 = (struct ipv6_hdr *)raw_pkt;
774 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
776 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
777 (fdir_input->flow.ipv6_flow.tc <<
778 I40E_FDIR_IPv6_TC_OFFSET));
780 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
781 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
782 fdir_input->flow.ipv6_flow.proto :
783 next_proto[fdir_input->flow_type];
784 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
785 fdir_input->flow.ipv6_flow.hop_limits :
786 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
788 * The source and destination fields in the transmitted packet
789 * need to be presented in a reversed order with respect
790 * to the expected received packets.
792 rte_memcpy(&(ip6->src_addr),
793 &(fdir_input->flow.ipv6_flow.dst_ip),
795 rte_memcpy(&(ip6->dst_addr),
796 &(fdir_input->flow.ipv6_flow.src_ip),
798 len += sizeof(struct ipv6_hdr);
801 PMD_DRV_LOG(ERR, "unknown flow type %u.",
802 fdir_input->flow_type);
810 * i40e_fdir_construct_pkt - construct packet based on fields in input
811 * @pf: board private structure
812 * @fdir_input: input set of the flow director entry
813 * @raw_pkt: a packet to be constructed
816 i40e_fdir_construct_pkt(struct i40e_pf *pf,
817 const struct rte_eth_fdir_input *fdir_input,
818 unsigned char *raw_pkt)
820 unsigned char *payload, *ptr;
823 struct sctp_hdr *sctp;
824 uint8_t size, dst = 0;
825 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
828 /* fill the ethernet and IP head */
829 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
830 !!fdir_input->flow_ext.vlan_tci);
834 /* fill the L4 head */
835 switch (fdir_input->flow_type) {
836 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
837 udp = (struct udp_hdr *)(raw_pkt + len);
838 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
840 * The source and destination fields in the transmitted packet
841 * need to be presented in a reversed order with respect
842 * to the expected received packets.
844 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
845 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
846 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
849 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
850 tcp = (struct tcp_hdr *)(raw_pkt + len);
851 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
853 * The source and destination fields in the transmitted packet
854 * need to be presented in a reversed order with respect
855 * to the expected received packets.
857 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
858 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
859 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
862 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
863 sctp = (struct sctp_hdr *)(raw_pkt + len);
864 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
866 * The source and destination fields in the transmitted packet
867 * need to be presented in a reversed order with respect
868 * to the expected received packets.
870 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
871 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
872 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
875 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
876 case RTE_ETH_FLOW_FRAG_IPV4:
877 payload = raw_pkt + len;
878 set_idx = I40E_FLXPLD_L3_IDX;
881 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
882 udp = (struct udp_hdr *)(raw_pkt + len);
883 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
885 * The source and destination fields in the transmitted packet
886 * need to be presented in a reversed order with respect
887 * to the expected received packets.
889 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
890 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
891 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
894 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
895 tcp = (struct tcp_hdr *)(raw_pkt + len);
896 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
898 * The source and destination fields in the transmitted packet
899 * need to be presented in a reversed order with respect
900 * to the expected received packets.
902 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
903 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
904 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
907 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
908 sctp = (struct sctp_hdr *)(raw_pkt + len);
909 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
911 * The source and destination fields in the transmitted packet
912 * need to be presented in a reversed order with respect
913 * to the expected received packets.
915 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
916 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
917 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
920 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
921 case RTE_ETH_FLOW_FRAG_IPV6:
922 payload = raw_pkt + len;
923 set_idx = I40E_FLXPLD_L3_IDX;
925 case RTE_ETH_FLOW_L2_PAYLOAD:
926 payload = raw_pkt + len;
928 * ARP packet is a special case on which the payload
929 * starts after the whole ARP header
931 if (fdir_input->flow.l2_flow.ether_type ==
932 rte_cpu_to_be_16(ETHER_TYPE_ARP))
933 payload += sizeof(struct arp_hdr);
934 set_idx = I40E_FLXPLD_L2_IDX;
937 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
941 /* fill the flexbytes to payload */
942 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
943 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
944 size = pf->fdir.flex_set[pit_idx].size;
947 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
949 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
950 (void)rte_memcpy(ptr,
951 &fdir_input->flow_ext.flexbytes[dst],
952 size * sizeof(uint16_t));
958 /* Construct the tx flags */
959 static inline uint64_t
960 i40e_build_ctob(uint32_t td_cmd,
965 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
966 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
967 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
968 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
969 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
973 * check the programming status descriptor in rx queue.
974 * done after Programming Flow Director is programmed on
978 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
980 volatile union i40e_rx_desc *rxdp;
987 rxdp = &rxq->rx_ring[rxq->rx_tail];
988 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
989 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
990 >> I40E_RXD_QW1_STATUS_SHIFT;
992 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
993 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
994 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
995 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
997 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
998 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1000 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1001 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1002 if (error == (0x1 <<
1003 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1004 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1005 " (FD_ID %u): programming status"
1007 rxdp->wb.qword0.hi_dword.fd_id);
1009 } else if (error == (0x1 <<
1010 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1011 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1012 " (FD_ID %u): programming status"
1014 rxdp->wb.qword0.hi_dword.fd_id);
1017 PMD_DRV_LOG(ERR, "invalid programming status"
1018 " reported, error = %u.", error);
1020 PMD_DRV_LOG(ERR, "unknown programming status"
1021 " reported, len = %d, id = %u.", len, id);
1022 rxdp->wb.qword1.status_error_len = 0;
1024 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1031 i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
1032 struct i40e_fdir_filter *filter)
1034 rte_memcpy(&filter->fdir, input, sizeof(struct rte_eth_fdir_filter));
1038 /* Check if there exists the flow director filter */
1039 static struct i40e_fdir_filter *
1040 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1041 const struct rte_eth_fdir_input *input)
1045 ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1049 return fdir_info->hash_map[ret];
1052 /* Add a flow director filter into the SW list */
1054 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1056 struct i40e_fdir_info *fdir_info = &pf->fdir;
1059 ret = rte_hash_add_key(fdir_info->hash_table,
1060 &filter->fdir.input);
1063 "Failed to insert fdir filter to hash table %d!",
1067 fdir_info->hash_map[ret] = filter;
1069 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1074 /* Delete a flow director filter from the SW list */
1076 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct rte_eth_fdir_input *input)
1078 struct i40e_fdir_info *fdir_info = &pf->fdir;
1079 struct i40e_fdir_filter *filter;
1082 ret = rte_hash_del_key(fdir_info->hash_table, input);
1085 "Failed to delete fdir filter to hash table %d!",
1089 filter = fdir_info->hash_map[ret];
1090 fdir_info->hash_map[ret] = NULL;
1092 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1099 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1100 * @pf: board private structure
1101 * @filter: fdir filter entry
1102 * @add: 0 - delete, 1 - add
1105 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1106 const struct rte_eth_fdir_filter *filter,
1109 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1110 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1111 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1112 enum i40e_filter_pctype pctype;
1113 struct i40e_fdir_info *fdir_info = &pf->fdir;
1114 struct i40e_fdir_filter *fdir_filter, *node;
1115 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1118 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1119 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1120 " check the mode in fdir_conf.");
1124 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1125 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1128 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1129 PMD_DRV_LOG(ERR, "Invalid queue ID");
1132 if (filter->input.flow_ext.is_vf &&
1133 filter->input.flow_ext.dst_id >= pf->vf_num) {
1134 PMD_DRV_LOG(ERR, "Invalid VF ID");
1138 /* Check if there is the filter in SW list */
1139 memset(&check_filter, 0, sizeof(check_filter));
1140 i40e_fdir_filter_convert(filter, &check_filter);
1141 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1144 "Conflict with existing flow director rules!");
1148 if (!add && !node) {
1150 "There's no corresponding flow firector filter!");
1154 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1156 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1158 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1162 if (hw->mac.type == I40E_MAC_X722) {
1163 /* get translated pctype value in fd pctype register */
1164 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1165 hw, I40E_GLQF_FD_PCTYPES(
1166 (int)i40e_flowtype_to_pctype(
1167 filter->input.flow_type)));
1169 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1171 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1173 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1179 fdir_filter = rte_zmalloc("fdir_filter",
1180 sizeof(*fdir_filter), 0);
1181 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1182 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1184 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1191 * i40e_fdir_filter_programming - Program a flow director filter rule.
1192 * Is done by Flow Director Programming Descriptor followed by packet
1193 * structure that contains the filter fields need to match.
1194 * @pf: board private structure
1196 * @filter: fdir filter entry
1197 * @add: 0 - delete, 1 - add
1200 i40e_fdir_filter_programming(struct i40e_pf *pf,
1201 enum i40e_filter_pctype pctype,
1202 const struct rte_eth_fdir_filter *filter,
1205 struct i40e_tx_queue *txq = pf->fdir.txq;
1206 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1207 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1208 volatile struct i40e_tx_desc *txdp;
1209 volatile struct i40e_filter_program_desc *fdirdp;
1214 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1215 fdirdp = (volatile struct i40e_filter_program_desc *)
1216 (&(txq->tx_ring[txq->tx_tail]));
1218 fdirdp->qindex_flex_ptype_vsi =
1219 rte_cpu_to_le_32((fdir_action->rx_queue <<
1220 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1221 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1223 fdirdp->qindex_flex_ptype_vsi |=
1224 rte_cpu_to_le_32((fdir_action->flex_off <<
1225 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1226 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1228 fdirdp->qindex_flex_ptype_vsi |=
1229 rte_cpu_to_le_32((pctype <<
1230 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1231 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1233 if (filter->input.flow_ext.is_vf)
1234 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1236 /* Use LAN VSI Id by default */
1237 vsi_id = pf->main_vsi->vsi_id;
1238 fdirdp->qindex_flex_ptype_vsi |=
1239 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1240 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1241 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1243 fdirdp->dtype_cmd_cntindex =
1244 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1247 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1248 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1249 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1251 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1252 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1253 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1255 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1256 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1257 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1258 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1259 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1260 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1262 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1263 " unsupported fdir behavior.");
1267 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1268 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1269 I40E_TXD_FLTR_QW1_DEST_MASK);
1271 fdirdp->dtype_cmd_cntindex |=
1272 rte_cpu_to_le_32((fdir_action->report_status<<
1273 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1274 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1276 fdirdp->dtype_cmd_cntindex |=
1277 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1278 fdirdp->dtype_cmd_cntindex |=
1280 ((uint32_t)pf->fdir.match_counter_index <<
1281 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1282 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1284 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1286 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1287 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1288 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1289 td_cmd = I40E_TX_DESC_CMD_EOP |
1290 I40E_TX_DESC_CMD_RS |
1291 I40E_TX_DESC_CMD_DUMMY;
1293 txdp->cmd_type_offset_bsz =
1294 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1296 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1297 if (txq->tx_tail >= txq->nb_tx_desc)
1299 /* Update the tx tail register */
1301 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1303 for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1304 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1305 if ((txdp->cmd_type_offset_bsz &
1306 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1307 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1310 if (i >= I40E_FDIR_WAIT_COUNT) {
1311 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1312 " time out to get DD on tx queue.");
1315 /* totally delay 10 ms to check programming status*/
1316 rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1317 if (i40e_check_fdir_programming_status(rxq) < 0) {
1318 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1319 " programming status reported.");
1327 * i40e_fdir_flush - clear all filters of Flow Director table
1328 * @pf: board private structure
1331 i40e_fdir_flush(struct rte_eth_dev *dev)
1333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1334 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1336 uint16_t guarant_cnt, best_cnt;
1339 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1340 I40E_WRITE_FLUSH(hw);
1342 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1343 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1344 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1345 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1348 if (i >= I40E_FDIR_FLUSH_RETRY) {
1349 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1352 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1353 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1354 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1355 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1356 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1357 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1358 if (guarant_cnt != 0 || best_cnt != 0) {
1359 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1362 PMD_DRV_LOG(INFO, "FD table Flush success.");
1367 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1368 struct rte_eth_flex_payload_cfg *flex_set,
1371 struct i40e_fdir_flex_pit *flex_pit;
1372 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1373 uint16_t src, dst, size, j, k;
1374 uint8_t i, layer_idx;
1376 for (layer_idx = I40E_FLXPLD_L2_IDX;
1377 layer_idx <= I40E_FLXPLD_L4_IDX;
1379 if (layer_idx == I40E_FLXPLD_L2_IDX)
1380 ptr->type = RTE_ETH_L2_PAYLOAD;
1381 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1382 ptr->type = RTE_ETH_L3_PAYLOAD;
1383 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1384 ptr->type = RTE_ETH_L4_PAYLOAD;
1386 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1387 flex_pit = &pf->fdir.flex_set[layer_idx *
1388 I40E_MAX_FLXPLD_FIED + i];
1389 if (flex_pit->size == 0)
1391 src = flex_pit->src_offset * sizeof(uint16_t);
1392 dst = flex_pit->dst_offset * sizeof(uint16_t);
1393 size = flex_pit->size * sizeof(uint16_t);
1394 for (j = src, k = dst; j < src + size; j++, k++)
1395 ptr->src_offset[k] = j;
1403 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1404 struct rte_eth_fdir_flex_mask *flex_mask,
1407 struct i40e_fdir_flex_mask *mask;
1408 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1409 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1412 uint16_t off_bytes, mask_tmp;
1414 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1415 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1417 mask = &pf->fdir.flex_mask[i];
1418 if (hw->mac.type == I40E_MAC_X722) {
1419 if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1422 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1425 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1426 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1427 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1428 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1429 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1431 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1432 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1435 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1436 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1437 mask_tmp = ~mask->bitmask[j].mask;
1438 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1439 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1441 ptr->flow_type = flow_type;
1448 * i40e_fdir_info_get - get information of Flow Director
1449 * @pf: ethernet device to get info from
1450 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1451 * the flow director information.
1454 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1456 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1457 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1458 uint16_t num_flex_set = 0;
1459 uint16_t num_flex_mask = 0;
1461 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1462 fdir->mode = RTE_FDIR_MODE_PERFECT;
1464 fdir->mode = RTE_FDIR_MODE_NONE;
1467 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1469 (uint32_t)hw->func_caps.fd_filters_best_effort;
1470 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1471 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1472 fdir->flex_payload_unit = sizeof(uint16_t);
1473 fdir->flex_bitmask_unit = sizeof(uint16_t);
1474 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1475 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1476 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1478 i40e_fdir_info_get_flex_set(pf,
1479 fdir->flex_conf.flex_set,
1481 i40e_fdir_info_get_flex_mask(pf,
1482 fdir->flex_conf.flex_mask,
1485 fdir->flex_conf.nb_payloads = num_flex_set;
1486 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1490 * i40e_fdir_stat_get - get statistics of Flow Director
1491 * @pf: ethernet device to get info from
1492 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1493 * the flow director statistics.
1496 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1499 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1502 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1504 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1505 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1507 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1508 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1512 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1513 struct rte_eth_fdir_filter_info *info)
1515 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1519 PMD_DRV_LOG(ERR, "Invalid pointer");
1523 switch (info->info_type) {
1524 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1525 ret = i40e_fdir_filter_inset_select(pf,
1526 &(info->info.input_set_conf));
1529 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1538 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1539 * @pf: board private structure
1540 * @filter_op:operation will be taken.
1541 * @arg: a pointer to specific structure corresponding to the filter_op
1544 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1545 enum rte_filter_op filter_op,
1548 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1551 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1554 if (filter_op == RTE_ETH_FILTER_NOP)
1557 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1560 switch (filter_op) {
1561 case RTE_ETH_FILTER_ADD:
1562 ret = i40e_add_del_fdir_filter(dev,
1563 (struct rte_eth_fdir_filter *)arg,
1566 case RTE_ETH_FILTER_DELETE:
1567 ret = i40e_add_del_fdir_filter(dev,
1568 (struct rte_eth_fdir_filter *)arg,
1571 case RTE_ETH_FILTER_FLUSH:
1572 ret = i40e_fdir_flush(dev);
1574 case RTE_ETH_FILTER_INFO:
1575 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1577 case RTE_ETH_FILTER_SET:
1578 ret = i40e_fdir_filter_set(dev,
1579 (struct rte_eth_fdir_filter_info *)arg);
1581 case RTE_ETH_FILTER_STATS:
1582 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1585 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1592 /* Restore flow director filter */
1594 i40e_fdir_filter_restore(struct i40e_pf *pf)
1596 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
1597 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
1598 struct i40e_fdir_filter *f;
1599 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1601 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
1602 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
1604 TAILQ_FOREACH(f, fdir_list, rules)
1605 i40e_add_del_fdir_filter(dev, &f->fdir, TRUE);
1607 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1609 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1610 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1612 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1613 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1615 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
1616 guarant_cnt, best_cnt);