4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
70 #define I40E_FDIR_IPv6_TC_OFFSET 20
72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
73 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
74 #define I40E_FDIR_UDP_DEFAULT_LEN 400
76 /* Wait time for fdir filter programming */
77 #define I40E_FDIR_MAX_WAIT_US 10000
79 /* Wait count and interval for fdir filter flush */
80 #define I40E_FDIR_FLUSH_RETRY 50
81 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
83 #define I40E_COUNTER_PF 2
84 /* Statistic counter index for one pf */
85 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
87 #define I40E_FDIR_FLOWS ( \
88 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
89 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
90 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
91 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
92 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
93 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
94 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
95 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
96 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
97 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
98 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
100 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
101 enum i40e_filter_pctype pctype,
102 const struct rte_eth_fdir_filter *filter,
104 static int i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
105 struct i40e_fdir_filter *filter);
106 static struct i40e_fdir_filter *
107 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
108 const struct rte_eth_fdir_input *input);
109 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
110 struct i40e_fdir_filter *filter);
113 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
115 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
116 struct i40e_hmc_obj_rxq rx_ctx;
117 int err = I40E_SUCCESS;
119 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
120 /* Init the RX queue in hardware */
121 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
123 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
124 rx_ctx.qlen = rxq->nb_rx_desc;
125 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
128 rx_ctx.dtype = i40e_header_split_none;
129 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
130 rx_ctx.rxmax = ETHER_MAX_LEN;
131 rx_ctx.tphrdesc_ena = 1;
132 rx_ctx.tphwdesc_ena = 1;
133 rx_ctx.tphdata_ena = 1;
134 rx_ctx.tphhead_ena = 1;
135 rx_ctx.lrxqthresh = 2;
141 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
142 if (err != I40E_SUCCESS) {
143 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
146 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
147 if (err != I40E_SUCCESS) {
148 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
151 rxq->qrx_tail = hw->hw_addr +
152 I40E_QRX_TAIL(rxq->vsi->base_queue);
155 /* Init the RX tail regieter. */
156 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
157 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
163 * i40e_fdir_setup - reserve and initialize the Flow Director resources
164 * @pf: board private structure
167 i40e_fdir_setup(struct i40e_pf *pf)
169 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
170 struct i40e_vsi *vsi;
171 int err = I40E_SUCCESS;
172 char z_name[RTE_MEMZONE_NAMESIZE];
173 const struct rte_memzone *mz = NULL;
174 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
176 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
177 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
178 return I40E_NOT_SUPPORTED;
181 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
182 " num_filters_best_effort = %u.",
183 hw->func_caps.fd_filters_guaranteed,
184 hw->func_caps.fd_filters_best_effort);
186 vsi = pf->fdir.fdir_vsi;
188 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
191 /* make new FDIR VSI */
192 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
194 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
195 return I40E_ERR_NO_AVAILABLE_VSI;
197 pf->fdir.fdir_vsi = vsi;
199 /*Fdir tx queue setup*/
200 err = i40e_fdir_setup_tx_resources(pf);
202 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
206 /*Fdir rx queue setup*/
207 err = i40e_fdir_setup_rx_resources(pf);
209 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
213 err = i40e_tx_queue_init(pf->fdir.txq);
215 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
219 /* need switch on before dev start*/
220 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
222 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
226 /* Init the rx queue in hardware */
227 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
229 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
233 /* switch on rx queue */
234 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
236 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
240 /* reserve memory for the fdir programming packet */
241 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
242 eth_dev->data->drv_name,
244 eth_dev->data->port_id);
245 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
247 PMD_DRV_LOG(ERR, "Cannot init memzone for "
248 "flow director program packet.");
249 err = I40E_ERR_NO_MEMORY;
252 pf->fdir.prg_pkt = mz->addr;
253 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
255 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
256 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
261 i40e_dev_rx_queue_release(pf->fdir.rxq);
264 i40e_dev_tx_queue_release(pf->fdir.txq);
267 i40e_vsi_release(vsi);
268 pf->fdir.fdir_vsi = NULL;
273 * i40e_fdir_teardown - release the Flow Director resources
274 * @pf: board private structure
277 i40e_fdir_teardown(struct i40e_pf *pf)
279 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
280 struct i40e_vsi *vsi;
282 vsi = pf->fdir.fdir_vsi;
285 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
287 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
288 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
290 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
291 i40e_dev_rx_queue_release(pf->fdir.rxq);
293 i40e_dev_tx_queue_release(pf->fdir.txq);
295 i40e_vsi_release(vsi);
296 pf->fdir.fdir_vsi = NULL;
299 /* check whether the flow director table in empty */
301 i40e_fdir_empty(struct i40e_hw *hw)
303 uint32_t guarant_cnt, best_cnt;
305 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
306 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
307 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
308 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
309 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
310 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
311 if (best_cnt + guarant_cnt > 0)
318 * Initialize the configuration about bytes stream extracted as flexible payload
322 i40e_init_flx_pld(struct i40e_pf *pf)
324 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
329 * Define the bytes stream extracted as flexible payload in
330 * field vector. By default, select 8 words from the beginning
331 * of payload as flexible payload.
333 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
334 index = i * I40E_MAX_FLXPLD_FIED;
335 pf->fdir.flex_set[index].src_offset = 0;
336 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
337 pf->fdir.flex_set[index].dst_offset = 0;
338 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
340 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
342 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
345 /* initialize the masks */
346 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
347 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
348 if (hw->mac.type == I40E_MAC_X722) {
349 if (!I40E_VALID_PCTYPE_X722(
350 (enum i40e_filter_pctype)pctype))
353 if (!I40E_VALID_PCTYPE(
354 (enum i40e_filter_pctype)pctype))
357 pf->fdir.flex_mask[pctype].word_mask = 0;
358 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
359 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
360 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
361 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
362 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
367 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
368 if ((flex_pit2).src_offset < \
369 (flex_pit1).src_offset + (flex_pit1).size) { \
370 PMD_DRV_LOG(ERR, "src_offset should be not" \
371 " less than than previous offset" \
372 " + previous FSIZE."); \
378 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
379 * and the flex_pit will be sorted by it's src_offset value
381 static inline uint16_t
382 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
383 struct i40e_fdir_flex_pit *flex_pit)
385 uint16_t src_tmp, size, num = 0;
386 uint16_t i, k, j = 0;
388 while (j < I40E_FDIR_MAX_FLEX_LEN) {
390 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
391 if (src_offset[j + 1] == src_offset[j] + 1)
396 src_tmp = src_offset[j] + 1 - size;
397 /* the flex_pit need to be sort by src_offset */
398 for (i = 0; i < num; i++) {
399 if (src_tmp < flex_pit[i].src_offset)
402 /* if insert required, move backward */
403 for (k = num; k > i; k--)
404 flex_pit[k] = flex_pit[k - 1];
406 flex_pit[i].dst_offset = j + 1 - size;
407 flex_pit[i].src_offset = src_tmp;
408 flex_pit[i].size = size;
415 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
417 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
419 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
422 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
423 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
424 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
429 memset(flex_pit, 0, sizeof(flex_pit));
430 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
431 if (num > I40E_MAX_FLXPLD_FIED) {
432 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
435 for (i = 0; i < num; i++) {
436 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
437 flex_pit[i].src_offset & 0x01) {
438 PMD_DRV_LOG(ERR, "flexpayload should be measured"
443 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
449 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
450 * arguments are valid
453 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
455 const struct rte_eth_flex_payload_cfg *flex_cfg;
456 const struct rte_eth_fdir_flex_mask *flex_mask;
463 PMD_DRV_LOG(INFO, "NULL pointer.");
466 /* check flexible payload setting configuration */
467 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
468 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
471 for (i = 0; i < conf->nb_payloads; i++) {
472 flex_cfg = &conf->flex_set[i];
473 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
474 PMD_DRV_LOG(ERR, "invalid payload type.");
477 ret = i40e_check_fdir_flex_payload(flex_cfg);
479 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
484 /* check flex mask setting configuration */
485 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
486 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
489 for (i = 0; i < conf->nb_flexmasks; i++) {
490 flex_mask = &conf->flex_mask[i];
491 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
492 PMD_DRV_LOG(WARNING, "invalid flow type.");
496 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
497 mask_tmp = I40E_WORD(flex_mask->mask[j],
498 flex_mask->mask[j + 1]);
499 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
501 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
502 PMD_DRV_LOG(ERR, " exceed maximal"
503 " number of bitmasks.");
513 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
514 * @pf: board private structure
515 * @cfg: the rule how bytes stream is extracted as flexible payload
518 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
519 const struct rte_eth_flex_payload_cfg *cfg)
521 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
522 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
524 uint16_t num, min_next_off; /* in words */
525 uint8_t field_idx = 0;
526 uint8_t layer_idx = 0;
529 if (cfg->type == RTE_ETH_L2_PAYLOAD)
530 layer_idx = I40E_FLXPLD_L2_IDX;
531 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
532 layer_idx = I40E_FLXPLD_L3_IDX;
533 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
534 layer_idx = I40E_FLXPLD_L4_IDX;
536 memset(flex_pit, 0, sizeof(flex_pit));
537 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
539 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
540 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
541 /* record the info in fdir structure */
542 pf->fdir.flex_set[field_idx].src_offset =
543 flex_pit[i].src_offset / sizeof(uint16_t);
544 pf->fdir.flex_set[field_idx].size =
545 flex_pit[i].size / sizeof(uint16_t);
546 pf->fdir.flex_set[field_idx].dst_offset =
547 flex_pit[i].dst_offset / sizeof(uint16_t);
548 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
549 pf->fdir.flex_set[field_idx].size,
550 pf->fdir.flex_set[field_idx].dst_offset);
552 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
554 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
555 pf->fdir.flex_set[field_idx].size;
557 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
558 /* set the non-used register obeying register's constrain */
559 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
560 NONUSE_FLX_PIT_DEST_OFF);
562 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
569 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
570 * @pf: board private structure
571 * @pctype: packet classify type
572 * @flex_masks: mask for flexible payload
575 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
576 enum i40e_filter_pctype pctype,
577 const struct rte_eth_fdir_flex_mask *mask_cfg)
579 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
580 struct i40e_fdir_flex_mask *flex_mask;
581 uint32_t flxinset, fd_mask;
583 uint8_t i, nb_bitmask = 0;
585 flex_mask = &pf->fdir.flex_mask[pctype];
586 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
587 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
588 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
589 if (mask_tmp != 0x0) {
590 flex_mask->word_mask |=
591 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
592 if (mask_tmp != UINT16_MAX) {
594 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
595 flex_mask->bitmask[nb_bitmask].offset =
596 i / sizeof(uint16_t);
601 /* write mask to hw */
602 flxinset = (flex_mask->word_mask <<
603 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
604 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
605 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
607 for (i = 0; i < nb_bitmask; i++) {
608 fd_mask = (flex_mask->bitmask[i].mask <<
609 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
610 I40E_PRTQF_FD_MSK_MASK_MASK;
611 fd_mask |= ((flex_mask->bitmask[i].offset +
612 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
613 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
614 I40E_PRTQF_FD_MSK_OFFSET_MASK;
615 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
620 * Configure flow director related setting
623 i40e_fdir_configure(struct rte_eth_dev *dev)
625 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
626 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 struct rte_eth_fdir_flex_conf *conf;
628 enum i40e_filter_pctype pctype;
634 * configuration need to be done before
635 * flow director filters are added
636 * If filters exist, flush them.
638 if (i40e_fdir_empty(hw) < 0) {
639 ret = i40e_fdir_flush(dev);
641 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
646 /* enable FDIR filter */
647 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
648 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
649 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
651 i40e_init_flx_pld(pf); /* set flex config to default value */
653 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
654 ret = i40e_check_fdir_flex_conf(conf);
656 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
659 /* configure flex payload */
660 for (i = 0; i < conf->nb_payloads; i++)
661 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
662 /* configure flex mask*/
663 for (i = 0; i < conf->nb_flexmasks; i++) {
664 if (hw->mac.type == I40E_MAC_X722) {
665 /* get translated pctype value in fd pctype register */
666 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
667 hw, I40E_GLQF_FD_PCTYPES(
668 (int)i40e_flowtype_to_pctype(
669 conf->flex_mask[i].flow_type)));
671 pctype = i40e_flowtype_to_pctype(
672 conf->flex_mask[i].flow_type);
674 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
681 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
682 unsigned char *raw_pkt,
685 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
686 uint16_t *ether_type;
687 uint8_t len = 2 * sizeof(struct ether_addr);
689 struct ipv6_hdr *ip6;
690 static const uint8_t next_proto[] = {
691 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
692 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
693 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
694 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
695 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
696 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
697 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
698 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
699 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
700 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
703 raw_pkt += 2 * sizeof(struct ether_addr);
704 if (vlan && fdir_input->flow_ext.vlan_tci) {
705 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
706 rte_memcpy(raw_pkt + sizeof(uint16_t),
707 &fdir_input->flow_ext.vlan_tci,
709 raw_pkt += sizeof(vlan_frame);
710 len += sizeof(vlan_frame);
712 ether_type = (uint16_t *)raw_pkt;
713 raw_pkt += sizeof(uint16_t);
714 len += sizeof(uint16_t);
716 switch (fdir_input->flow_type) {
717 case RTE_ETH_FLOW_L2_PAYLOAD:
718 *ether_type = fdir_input->flow.l2_flow.ether_type;
720 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
721 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
722 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
723 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
724 case RTE_ETH_FLOW_FRAG_IPV4:
725 ip = (struct ipv4_hdr *)raw_pkt;
727 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
728 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
729 /* set len to by default */
730 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
731 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
732 fdir_input->flow.ip4_flow.proto :
733 next_proto[fdir_input->flow_type];
734 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
735 fdir_input->flow.ip4_flow.ttl :
736 I40E_FDIR_IP_DEFAULT_TTL;
737 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
739 * The source and destination fields in the transmitted packet
740 * need to be presented in a reversed order with respect
741 * to the expected received packets.
743 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
744 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
745 len += sizeof(struct ipv4_hdr);
747 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
748 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
749 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
750 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
751 case RTE_ETH_FLOW_FRAG_IPV6:
752 ip6 = (struct ipv6_hdr *)raw_pkt;
754 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
756 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
757 (fdir_input->flow.ipv6_flow.tc <<
758 I40E_FDIR_IPv6_TC_OFFSET));
760 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
761 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
762 fdir_input->flow.ipv6_flow.proto :
763 next_proto[fdir_input->flow_type];
764 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
765 fdir_input->flow.ipv6_flow.hop_limits :
766 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
768 * The source and destination fields in the transmitted packet
769 * need to be presented in a reversed order with respect
770 * to the expected received packets.
772 rte_memcpy(&(ip6->src_addr),
773 &(fdir_input->flow.ipv6_flow.dst_ip),
775 rte_memcpy(&(ip6->dst_addr),
776 &(fdir_input->flow.ipv6_flow.src_ip),
778 len += sizeof(struct ipv6_hdr);
781 PMD_DRV_LOG(ERR, "unknown flow type %u.",
782 fdir_input->flow_type);
790 * i40e_fdir_construct_pkt - construct packet based on fields in input
791 * @pf: board private structure
792 * @fdir_input: input set of the flow director entry
793 * @raw_pkt: a packet to be constructed
796 i40e_fdir_construct_pkt(struct i40e_pf *pf,
797 const struct rte_eth_fdir_input *fdir_input,
798 unsigned char *raw_pkt)
800 unsigned char *payload, *ptr;
803 struct sctp_hdr *sctp;
804 uint8_t size, dst = 0;
805 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
808 /* fill the ethernet and IP head */
809 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
810 !!fdir_input->flow_ext.vlan_tci);
814 /* fill the L4 head */
815 switch (fdir_input->flow_type) {
816 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
817 udp = (struct udp_hdr *)(raw_pkt + len);
818 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
820 * The source and destination fields in the transmitted packet
821 * need to be presented in a reversed order with respect
822 * to the expected received packets.
824 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
825 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
826 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
829 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
830 tcp = (struct tcp_hdr *)(raw_pkt + len);
831 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
833 * The source and destination fields in the transmitted packet
834 * need to be presented in a reversed order with respect
835 * to the expected received packets.
837 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
838 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
839 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
842 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
843 sctp = (struct sctp_hdr *)(raw_pkt + len);
844 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
846 * The source and destination fields in the transmitted packet
847 * need to be presented in a reversed order with respect
848 * to the expected received packets.
850 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
851 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
852 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
855 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
856 case RTE_ETH_FLOW_FRAG_IPV4:
857 payload = raw_pkt + len;
858 set_idx = I40E_FLXPLD_L3_IDX;
861 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
862 udp = (struct udp_hdr *)(raw_pkt + len);
863 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
865 * The source and destination fields in the transmitted packet
866 * need to be presented in a reversed order with respect
867 * to the expected received packets.
869 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
870 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
871 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
874 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
875 tcp = (struct tcp_hdr *)(raw_pkt + len);
876 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
878 * The source and destination fields in the transmitted packet
879 * need to be presented in a reversed order with respect
880 * to the expected received packets.
882 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
883 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
884 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
887 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
888 sctp = (struct sctp_hdr *)(raw_pkt + len);
889 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
891 * The source and destination fields in the transmitted packet
892 * need to be presented in a reversed order with respect
893 * to the expected received packets.
895 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
896 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
897 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
900 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
901 case RTE_ETH_FLOW_FRAG_IPV6:
902 payload = raw_pkt + len;
903 set_idx = I40E_FLXPLD_L3_IDX;
905 case RTE_ETH_FLOW_L2_PAYLOAD:
906 payload = raw_pkt + len;
908 * ARP packet is a special case on which the payload
909 * starts after the whole ARP header
911 if (fdir_input->flow.l2_flow.ether_type ==
912 rte_cpu_to_be_16(ETHER_TYPE_ARP))
913 payload += sizeof(struct arp_hdr);
914 set_idx = I40E_FLXPLD_L2_IDX;
917 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
921 /* fill the flexbytes to payload */
922 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
923 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
924 size = pf->fdir.flex_set[pit_idx].size;
927 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
929 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
930 (void)rte_memcpy(ptr,
931 &fdir_input->flow_ext.flexbytes[dst],
932 size * sizeof(uint16_t));
938 /* Construct the tx flags */
939 static inline uint64_t
940 i40e_build_ctob(uint32_t td_cmd,
945 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
946 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
947 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
948 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
949 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
953 * check the programming status descriptor in rx queue.
954 * done after Programming Flow Director is programmed on
958 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
960 volatile union i40e_rx_desc *rxdp;
967 rxdp = &rxq->rx_ring[rxq->rx_tail];
968 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
969 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
970 >> I40E_RXD_QW1_STATUS_SHIFT;
972 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
973 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
974 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
975 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
977 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
978 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
980 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
981 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
983 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
984 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
985 " (FD_ID %u): programming status"
987 rxdp->wb.qword0.hi_dword.fd_id);
989 } else if (error == (0x1 <<
990 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
991 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
992 " (FD_ID %u): programming status"
994 rxdp->wb.qword0.hi_dword.fd_id);
997 PMD_DRV_LOG(ERR, "invalid programming status"
998 " reported, error = %u.", error);
1000 PMD_DRV_LOG(ERR, "unknown programming status"
1001 " reported, len = %d, id = %u.", len, id);
1002 rxdp->wb.qword1.status_error_len = 0;
1004 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1011 i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
1012 struct i40e_fdir_filter *filter)
1014 rte_memcpy(&filter->fdir, input, sizeof(struct rte_eth_fdir_filter));
1018 /* Check if there exists the flow director filter */
1019 static struct i40e_fdir_filter *
1020 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1021 const struct rte_eth_fdir_input *input)
1025 ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1029 return fdir_info->hash_map[ret];
1032 /* Add a flow director filter into the SW list */
1034 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1036 struct i40e_fdir_info *fdir_info = &pf->fdir;
1039 ret = rte_hash_add_key(fdir_info->hash_table,
1040 &filter->fdir.input);
1043 "Failed to insert fdir filter to hash table %d!",
1047 fdir_info->hash_map[ret] = filter;
1049 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1054 /* Delete a flow director filter from the SW list */
1056 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct rte_eth_fdir_input *input)
1058 struct i40e_fdir_info *fdir_info = &pf->fdir;
1059 struct i40e_fdir_filter *filter;
1062 ret = rte_hash_del_key(fdir_info->hash_table, input);
1065 "Failed to delete fdir filter to hash table %d!",
1069 filter = fdir_info->hash_map[ret];
1070 fdir_info->hash_map[ret] = NULL;
1072 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1079 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1080 * @pf: board private structure
1081 * @filter: fdir filter entry
1082 * @add: 0 - delete, 1 - add
1085 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1086 const struct rte_eth_fdir_filter *filter,
1089 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1091 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1092 enum i40e_filter_pctype pctype;
1093 struct i40e_fdir_info *fdir_info = &pf->fdir;
1094 struct i40e_fdir_filter *fdir_filter, *node;
1095 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1098 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1099 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1100 " check the mode in fdir_conf.");
1104 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1105 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1108 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1109 PMD_DRV_LOG(ERR, "Invalid queue ID");
1112 if (filter->input.flow_ext.is_vf &&
1113 filter->input.flow_ext.dst_id >= pf->vf_num) {
1114 PMD_DRV_LOG(ERR, "Invalid VF ID");
1118 /* Check if there is the filter in SW list */
1119 memset(&check_filter, 0, sizeof(check_filter));
1120 i40e_fdir_filter_convert(filter, &check_filter);
1121 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1124 "Conflict with existing flow director rules!");
1128 if (!add && !node) {
1130 "There's no corresponding flow firector filter!");
1134 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1136 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1138 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1142 if (hw->mac.type == I40E_MAC_X722) {
1143 /* get translated pctype value in fd pctype register */
1144 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1145 hw, I40E_GLQF_FD_PCTYPES(
1146 (int)i40e_flowtype_to_pctype(
1147 filter->input.flow_type)));
1149 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1151 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1153 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1159 fdir_filter = rte_zmalloc("fdir_filter",
1160 sizeof(*fdir_filter), 0);
1161 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1162 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1164 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1171 * i40e_fdir_filter_programming - Program a flow director filter rule.
1172 * Is done by Flow Director Programming Descriptor followed by packet
1173 * structure that contains the filter fields need to match.
1174 * @pf: board private structure
1176 * @filter: fdir filter entry
1177 * @add: 0 - delete, 1 - add
1180 i40e_fdir_filter_programming(struct i40e_pf *pf,
1181 enum i40e_filter_pctype pctype,
1182 const struct rte_eth_fdir_filter *filter,
1185 struct i40e_tx_queue *txq = pf->fdir.txq;
1186 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1187 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1188 volatile struct i40e_tx_desc *txdp;
1189 volatile struct i40e_filter_program_desc *fdirdp;
1194 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1195 fdirdp = (volatile struct i40e_filter_program_desc *)
1196 (&(txq->tx_ring[txq->tx_tail]));
1198 fdirdp->qindex_flex_ptype_vsi =
1199 rte_cpu_to_le_32((fdir_action->rx_queue <<
1200 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1201 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1203 fdirdp->qindex_flex_ptype_vsi |=
1204 rte_cpu_to_le_32((fdir_action->flex_off <<
1205 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1206 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1208 fdirdp->qindex_flex_ptype_vsi |=
1209 rte_cpu_to_le_32((pctype <<
1210 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1211 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1213 if (filter->input.flow_ext.is_vf)
1214 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1216 /* Use LAN VSI Id by default */
1217 vsi_id = pf->main_vsi->vsi_id;
1218 fdirdp->qindex_flex_ptype_vsi |=
1219 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1220 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1221 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1223 fdirdp->dtype_cmd_cntindex =
1224 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1227 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1228 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1229 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1231 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1232 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1233 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1235 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1236 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1237 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1238 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1239 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1240 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1242 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1243 " unsupported fdir behavior.");
1247 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1248 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1249 I40E_TXD_FLTR_QW1_DEST_MASK);
1251 fdirdp->dtype_cmd_cntindex |=
1252 rte_cpu_to_le_32((fdir_action->report_status<<
1253 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1254 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1256 fdirdp->dtype_cmd_cntindex |=
1257 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1258 fdirdp->dtype_cmd_cntindex |=
1260 ((uint32_t)pf->fdir.match_counter_index <<
1261 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1262 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1264 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1266 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1267 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1268 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1269 td_cmd = I40E_TX_DESC_CMD_EOP |
1270 I40E_TX_DESC_CMD_RS |
1271 I40E_TX_DESC_CMD_DUMMY;
1273 txdp->cmd_type_offset_bsz =
1274 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1276 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1277 if (txq->tx_tail >= txq->nb_tx_desc)
1279 /* Update the tx tail register */
1281 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1282 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1283 if ((txdp->cmd_type_offset_bsz &
1284 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1285 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1289 if (i >= I40E_FDIR_MAX_WAIT_US) {
1290 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1291 " time out to get DD on tx queue.");
1294 /* totally delay 10 ms to check programming status*/
1295 for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1296 if (i40e_check_fdir_programming_status(rxq) >= 0)
1301 "Failed to program FDIR filter: programming status reported.");
1306 * i40e_fdir_flush - clear all filters of Flow Director table
1307 * @pf: board private structure
1310 i40e_fdir_flush(struct rte_eth_dev *dev)
1312 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1313 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1315 uint16_t guarant_cnt, best_cnt;
1318 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1319 I40E_WRITE_FLUSH(hw);
1321 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1322 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1323 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1324 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1327 if (i >= I40E_FDIR_FLUSH_RETRY) {
1328 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1331 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1332 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1333 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1334 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1335 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1336 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1337 if (guarant_cnt != 0 || best_cnt != 0) {
1338 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1341 PMD_DRV_LOG(INFO, "FD table Flush success.");
1346 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1347 struct rte_eth_flex_payload_cfg *flex_set,
1350 struct i40e_fdir_flex_pit *flex_pit;
1351 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1352 uint16_t src, dst, size, j, k;
1353 uint8_t i, layer_idx;
1355 for (layer_idx = I40E_FLXPLD_L2_IDX;
1356 layer_idx <= I40E_FLXPLD_L4_IDX;
1358 if (layer_idx == I40E_FLXPLD_L2_IDX)
1359 ptr->type = RTE_ETH_L2_PAYLOAD;
1360 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1361 ptr->type = RTE_ETH_L3_PAYLOAD;
1362 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1363 ptr->type = RTE_ETH_L4_PAYLOAD;
1365 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1366 flex_pit = &pf->fdir.flex_set[layer_idx *
1367 I40E_MAX_FLXPLD_FIED + i];
1368 if (flex_pit->size == 0)
1370 src = flex_pit->src_offset * sizeof(uint16_t);
1371 dst = flex_pit->dst_offset * sizeof(uint16_t);
1372 size = flex_pit->size * sizeof(uint16_t);
1373 for (j = src, k = dst; j < src + size; j++, k++)
1374 ptr->src_offset[k] = j;
1382 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1383 struct rte_eth_fdir_flex_mask *flex_mask,
1386 struct i40e_fdir_flex_mask *mask;
1387 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1388 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1391 uint16_t off_bytes, mask_tmp;
1393 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1394 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1396 mask = &pf->fdir.flex_mask[i];
1397 if (hw->mac.type == I40E_MAC_X722) {
1398 if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1401 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1404 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1405 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1406 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1407 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1408 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1410 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1411 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1414 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1415 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1416 mask_tmp = ~mask->bitmask[j].mask;
1417 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1418 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1420 ptr->flow_type = flow_type;
1427 * i40e_fdir_info_get - get information of Flow Director
1428 * @pf: ethernet device to get info from
1429 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1430 * the flow director information.
1433 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1435 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1436 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1437 uint16_t num_flex_set = 0;
1438 uint16_t num_flex_mask = 0;
1440 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1441 fdir->mode = RTE_FDIR_MODE_PERFECT;
1443 fdir->mode = RTE_FDIR_MODE_NONE;
1446 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1448 (uint32_t)hw->func_caps.fd_filters_best_effort;
1449 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1450 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1451 fdir->flex_payload_unit = sizeof(uint16_t);
1452 fdir->flex_bitmask_unit = sizeof(uint16_t);
1453 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1454 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1455 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1457 i40e_fdir_info_get_flex_set(pf,
1458 fdir->flex_conf.flex_set,
1460 i40e_fdir_info_get_flex_mask(pf,
1461 fdir->flex_conf.flex_mask,
1464 fdir->flex_conf.nb_payloads = num_flex_set;
1465 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1469 * i40e_fdir_stat_get - get statistics of Flow Director
1470 * @pf: ethernet device to get info from
1471 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1472 * the flow director statistics.
1475 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1477 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1481 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1483 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1484 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1486 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1487 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1491 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1492 struct rte_eth_fdir_filter_info *info)
1494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1498 PMD_DRV_LOG(ERR, "Invalid pointer");
1502 switch (info->info_type) {
1503 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1504 ret = i40e_fdir_filter_inset_select(pf,
1505 &(info->info.input_set_conf));
1508 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1517 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1518 * @pf: board private structure
1519 * @filter_op:operation will be taken.
1520 * @arg: a pointer to specific structure corresponding to the filter_op
1523 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1524 enum rte_filter_op filter_op,
1527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1530 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1533 if (filter_op == RTE_ETH_FILTER_NOP)
1536 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1539 switch (filter_op) {
1540 case RTE_ETH_FILTER_ADD:
1541 ret = i40e_add_del_fdir_filter(dev,
1542 (struct rte_eth_fdir_filter *)arg,
1545 case RTE_ETH_FILTER_DELETE:
1546 ret = i40e_add_del_fdir_filter(dev,
1547 (struct rte_eth_fdir_filter *)arg,
1550 case RTE_ETH_FILTER_FLUSH:
1551 ret = i40e_fdir_flush(dev);
1553 case RTE_ETH_FILTER_INFO:
1554 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1556 case RTE_ETH_FILTER_SET:
1557 ret = i40e_fdir_filter_set(dev,
1558 (struct rte_eth_fdir_filter_info *)arg);
1560 case RTE_ETH_FILTER_STATS:
1561 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1564 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1571 /* Restore flow director filter */
1573 i40e_fdir_filter_restore(struct i40e_pf *pf)
1575 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
1576 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
1577 struct i40e_fdir_filter *f;
1578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1580 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
1581 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
1583 TAILQ_FOREACH(f, fdir_list, rules)
1584 i40e_add_del_fdir_filter(dev, &f->fdir, TRUE);
1586 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1588 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1589 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1591 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1592 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1594 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
1595 guarant_cnt, best_cnt);