drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "base/i40e_prototype.h"
  56 #include "i40e_ethdev.h"
  57 #include "i40e_rxtx.h"
  58
  59 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  60 #ifndef IPV6_ADDR_LEN
  61 #define IPV6_ADDR_LEN              16
  62 #endif
  63
  64 #define I40E_FDIR_PKT_LEN                   512
  65 #define I40E_FDIR_IP_DEFAULT_LEN            420
  66 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  70 #define I40E_FDIR_IPv6_TC_OFFSET            20
  71
  72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  73 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  74 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  75
  76 /* Wait count and interval for fdir filter programming */
  77 #define I40E_FDIR_WAIT_COUNT       10
  78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  79
  80 /* Wait count and interval for fdir filter flush */
  81 #define I40E_FDIR_FLUSH_RETRY       50
  82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  83
  84 #define I40E_COUNTER_PF           2
  85 /* Statistic counter index for one pf */
  86 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  87 #define I40E_MAX_FLX_SOURCE_OFF           480
  88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  89
  90 #define NONUSE_FLX_PIT_DEST_OFF 63
  91 #define NONUSE_FLX_PIT_FSIZE    1
  92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  93         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  94                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  95         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  96                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  97         ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
  98                         NONUSE_FLX_PIT_DEST_OFF : \
  99                         ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
 100                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
 101                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
 102
 103 #define I40E_FDIR_FLOWS ( \
 104         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 108         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 109         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 110         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 111         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 112         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 113         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 114         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 115
 116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 117
 118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 119                         enum i40e_filter_pctype pctype,
 120                         const struct rte_eth_fdir_filter *filter,
 121                         bool add);
 122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 123
 124 static int
 125 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 126 {
 127         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 128         struct i40e_hmc_obj_rxq rx_ctx;
 129         int err = I40E_SUCCESS;
 130
 131         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 132         /* Init the RX queue in hardware */
 133         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 134         rx_ctx.hbuff = 0;
 135         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 136         rx_ctx.qlen = rxq->nb_rx_desc;
 137 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 138         rx_ctx.dsize = 1;
 139 #endif
 140         rx_ctx.dtype = i40e_header_split_none;
 141         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 142         rx_ctx.rxmax = ETHER_MAX_LEN;
 143         rx_ctx.tphrdesc_ena = 1;
 144         rx_ctx.tphwdesc_ena = 1;
 145         rx_ctx.tphdata_ena = 1;
 146         rx_ctx.tphhead_ena = 1;
 147         rx_ctx.lrxqthresh = 2;
 148         rx_ctx.crcstrip = 0;
 149         rx_ctx.l2tsel = 1;
 150         rx_ctx.showiv = 0;
 151         rx_ctx.prefena = 1;
 152
 153         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 154         if (err != I40E_SUCCESS) {
 155                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 156                 return err;
 157         }
 158         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 159         if (err != I40E_SUCCESS) {
 160                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 161                 return err;
 162         }
 163         rxq->qrx_tail = hw->hw_addr +
 164                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 165
 166         rte_wmb();
 167         /* Init the RX tail regieter. */
 168         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 169         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 170
 171         return err;
 172 }
 173
 174 /*
 175  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 176  * @pf: board private structure
 177  */
 178 int
 179 i40e_fdir_setup(struct i40e_pf *pf)
 180 {
 181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 182         struct i40e_vsi *vsi;
 183         int err = I40E_SUCCESS;
 184         char z_name[RTE_MEMZONE_NAMESIZE];
 185         const struct rte_memzone *mz = NULL;
 186         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 187
 188         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 189                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 190                 return I40E_NOT_SUPPORTED;
 191         }
 192
 193         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 194                         " num_filters_best_effort = %u.",
 195                         hw->func_caps.fd_filters_guaranteed,
 196                         hw->func_caps.fd_filters_best_effort);
 197
 198         vsi = pf->fdir.fdir_vsi;
 199         if (vsi) {
 200                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 201                 return I40E_SUCCESS;
 202         }
 203         /* make new FDIR VSI */
 204         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 205         if (!vsi) {
 206                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 207                 return I40E_ERR_NO_AVAILABLE_VSI;
 208         }
 209         pf->fdir.fdir_vsi = vsi;
 210
 211         /*Fdir tx queue setup*/
 212         err = i40e_fdir_setup_tx_resources(pf);
 213         if (err) {
 214                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 215                 goto fail_setup_tx;
 216         }
 217
 218         /*Fdir rx queue setup*/
 219         err = i40e_fdir_setup_rx_resources(pf);
 220         if (err) {
 221                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 222                 goto fail_setup_rx;
 223         }
 224
 225         err = i40e_tx_queue_init(pf->fdir.txq);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 228                 goto fail_mem;
 229         }
 230
 231         /* need switch on before dev start*/
 232         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 233         if (err) {
 234                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 235                 goto fail_mem;
 236         }
 237
 238         /* Init the rx queue in hardware */
 239         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 240         if (err) {
 241                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 242                 goto fail_mem;
 243         }
 244
 245         /* switch on rx queue */
 246         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 247         if (err) {
 248                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 249                 goto fail_mem;
 250         }
 251
 252         /* reserve memory for the fdir programming packet */
 253         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 254                         eth_dev->driver->pci_drv.name,
 255                         I40E_FDIR_MZ_NAME,
 256                         eth_dev->data->port_id);
 257         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 258         if (!mz) {
 259                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 260                                  "flow director program packet.");
 261                 err = I40E_ERR_NO_MEMORY;
 262                 goto fail_mem;
 263         }
 264         pf->fdir.prg_pkt = mz->addr;
 265         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 266
 267         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 268         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 269                     vsi->base_queue);
 270         return I40E_SUCCESS;
 271
 272 fail_mem:
 273         i40e_dev_rx_queue_release(pf->fdir.rxq);
 274         pf->fdir.rxq = NULL;
 275 fail_setup_rx:
 276         i40e_dev_tx_queue_release(pf->fdir.txq);
 277         pf->fdir.txq = NULL;
 278 fail_setup_tx:
 279         i40e_vsi_release(vsi);
 280         pf->fdir.fdir_vsi = NULL;
 281         return err;
 282 }
 283
 284 /*
 285  * i40e_fdir_teardown - release the Flow Director resources
 286  * @pf: board private structure
 287  */
 288 void
 289 i40e_fdir_teardown(struct i40e_pf *pf)
 290 {
 291         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 292         struct i40e_vsi *vsi;
 293
 294         vsi = pf->fdir.fdir_vsi;
 295         if (!vsi)
 296                 return;
 297         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 298         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 299         i40e_dev_rx_queue_release(pf->fdir.rxq);
 300         pf->fdir.rxq = NULL;
 301         i40e_dev_tx_queue_release(pf->fdir.txq);
 302         pf->fdir.txq = NULL;
 303         i40e_vsi_release(vsi);
 304         pf->fdir.fdir_vsi = NULL;
 305 }
 306
 307 /* check whether the flow director table in empty */
 308 static inline int
 309 i40e_fdir_empty(struct i40e_hw *hw)
 310 {
 311         uint32_t guarant_cnt, best_cnt;
 312
 313         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 314                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 315                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 316         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 317                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 318                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 319         if (best_cnt + guarant_cnt > 0)
 320                 return -1;
 321
 322         return 0;
 323 }
 324
 325 /*
 326  * Initialize the configuration about bytes stream extracted as flexible payload
 327  * and mask setting
 328  */
 329 static inline void
 330 i40e_init_flx_pld(struct i40e_pf *pf)
 331 {
 332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 333         uint8_t pctype;
 334         int i, index;
 335
 336         /*
 337          * Define the bytes stream extracted as flexible payload in
 338          * field vector. By default, select 8 words from the beginning
 339          * of payload as flexible payload.
 340          */
 341         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 342                 index = i * I40E_MAX_FLXPLD_FIED;
 343                 pf->fdir.flex_set[index].src_offset = 0;
 344                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 345                 pf->fdir.flex_set[index].dst_offset = 0;
 346                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 347                 I40E_WRITE_REG(hw,
 348                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 349                 I40E_WRITE_REG(hw,
 350                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 351         }
 352
 353         /* initialize the masks */
 354         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 355              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 356                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))
 357                         continue;
 358                 pf->fdir.flex_mask[pctype].word_mask = 0;
 359                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 360                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 361                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 362                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 363                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 364                 }
 365         }
 366 }
 367
 368 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 369
 370 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 371         if ((flex_pit2).src_offset < \
 372                 (flex_pit1).src_offset + (flex_pit1).size) { \
 373                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 374                         " less than than previous offset" \
 375                         " + previous FSIZE."); \
 376                 return -EINVAL; \
 377         } \
 378 } while (0)
 379
 380 /*
 381  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 382  * and the flex_pit will be sorted by it's src_offset value
 383  */
 384 static inline uint16_t
 385 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 386                         struct i40e_fdir_flex_pit *flex_pit)
 387 {
 388         uint16_t src_tmp, size, num = 0;
 389         uint16_t i, k, j = 0;
 390
 391         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 392                 size = 1;
 393                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 394                         if (src_offset[j + 1] == src_offset[j] + 1)
 395                                 size++;
 396                         else
 397                                 break;
 398                 }
 399                 src_tmp = src_offset[j] + 1 - size;
 400                 /* the flex_pit need to be sort by src_offset */
 401                 for (i = 0; i < num; i++) {
 402                         if (src_tmp < flex_pit[i].src_offset)
 403                                 break;
 404                 }
 405                 /* if insert required, move backward */
 406                 for (k = num; k > i; k--)
 407                         flex_pit[k] = flex_pit[k - 1];
 408                 /* insert */
 409                 flex_pit[i].dst_offset = j + 1 - size;
 410                 flex_pit[i].src_offset = src_tmp;
 411                 flex_pit[i].size = size;
 412                 j++;
 413                 num++;
 414         }
 415         return num;
 416 }
 417
 418 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 419 static inline int
 420 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 421 {
 422         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 423         uint16_t num, i;
 424
 425         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 426                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 427                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 428                         return -EINVAL;
 429                 }
 430         }
 431
 432         memset(flex_pit, 0, sizeof(flex_pit));
 433         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 434         if (num > I40E_MAX_FLXPLD_FIED) {
 435                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 436                 return -EINVAL;
 437         }
 438         for (i = 0; i < num; i++) {
 439                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 440                         flex_pit[i].src_offset & 0x01) {
 441                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 442                                 " in word");
 443                         return -EINVAL;
 444                 }
 445                 if (i != num - 1)
 446                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 447         }
 448         return 0;
 449 }
 450
 451 /*
 452  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 453  * arguments are valid
 454  */
 455 static int
 456 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 457 {
 458         const struct rte_eth_flex_payload_cfg *flex_cfg;
 459         const struct rte_eth_fdir_flex_mask *flex_mask;
 460         uint16_t mask_tmp;
 461         uint8_t nb_bitmask;
 462         uint16_t i, j;
 463         int ret = 0;
 464
 465         if (conf == NULL) {
 466                 PMD_DRV_LOG(INFO, "NULL pointer.");
 467                 return -EINVAL;
 468         }
 469         /* check flexible payload setting configuration */
 470         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 471                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 472                 return -EINVAL;
 473         }
 474         for (i = 0; i < conf->nb_payloads; i++) {
 475                 flex_cfg = &conf->flex_set[i];
 476                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 477                         PMD_DRV_LOG(ERR, "invalid payload type.");
 478                         return -EINVAL;
 479                 }
 480                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 481                 if (ret < 0) {
 482                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 483                         return -EINVAL;
 484                 }
 485         }
 486
 487         /* check flex mask setting configuration */
 488         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 489                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 490                 return -EINVAL;
 491         }
 492         for (i = 0; i < conf->nb_flexmasks; i++) {
 493                 flex_mask = &conf->flex_mask[i];
 494                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 495                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 496                         return -EINVAL;
 497                 }
 498                 nb_bitmask = 0;
 499                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 500                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 501                                              flex_mask->mask[j + 1]);
 502                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 503                                 nb_bitmask++;
 504                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 505                                         PMD_DRV_LOG(ERR, " exceed maximal"
 506                                                 " number of bitmasks.");
 507                                         return -EINVAL;
 508                                 }
 509                         }
 510                 }
 511         }
 512         return 0;
 513 }
 514
 515 /*
 516  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 517  * @pf: board private structure
 518  * @cfg: the rule how bytes stream is extracted as flexible payload
 519  */
 520 static void
 521 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 522                          const struct rte_eth_flex_payload_cfg *cfg)
 523 {
 524         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 525         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 526         uint32_t flx_pit;
 527         uint16_t num, min_next_off;  /* in words */
 528         uint8_t field_idx = 0;
 529         uint8_t layer_idx = 0;
 530         uint16_t i;
 531
 532         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 533                 layer_idx = I40E_FLXPLD_L2_IDX;
 534         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 535                 layer_idx = I40E_FLXPLD_L3_IDX;
 536         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 537                 layer_idx = I40E_FLXPLD_L4_IDX;
 538
 539         memset(flex_pit, 0, sizeof(flex_pit));
 540         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 541
 542         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 543                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 544                 /* record the info in fdir structure */
 545                 pf->fdir.flex_set[field_idx].src_offset =
 546                         flex_pit[i].src_offset / sizeof(uint16_t);
 547                 pf->fdir.flex_set[field_idx].size =
 548                         flex_pit[i].size / sizeof(uint16_t);
 549                 pf->fdir.flex_set[field_idx].dst_offset =
 550                         flex_pit[i].dst_offset / sizeof(uint16_t);
 551                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 552                                 pf->fdir.flex_set[field_idx].size,
 553                                 pf->fdir.flex_set[field_idx].dst_offset);
 554
 555                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 556         }
 557         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 558                                 pf->fdir.flex_set[field_idx].size;
 559
 560         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 561                 /* set the non-used register obeying register's constrain */
 562                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 563                            NONUSE_FLX_PIT_DEST_OFF);
 564                 I40E_WRITE_REG(hw,
 565                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 566                         flx_pit);
 567                 min_next_off++;
 568         }
 569 }
 570
 571 /*
 572  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 573  * @pf: board private structure
 574  * @pctype: packet classify type
 575  * @flex_masks: mask for flexible payload
 576  */
 577 static void
 578 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 579                 enum i40e_filter_pctype pctype,
 580                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 581 {
 582         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 583         struct i40e_fdir_flex_mask *flex_mask;
 584         uint32_t flxinset, fd_mask;
 585         uint16_t mask_tmp;
 586         uint8_t i, nb_bitmask = 0;
 587
 588         flex_mask = &pf->fdir.flex_mask[pctype];
 589         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 590         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 591                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 592                 if (mask_tmp != 0x0) {
 593                         flex_mask->word_mask |=
 594                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 595                         if (mask_tmp != UINT16_MAX) {
 596                                 /* set bit mask */
 597                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 598                                 flex_mask->bitmask[nb_bitmask].offset =
 599                                         i / sizeof(uint16_t);
 600                                 nb_bitmask++;
 601                         }
 602                 }
 603         }
 604         /* write mask to hw */
 605         flxinset = (flex_mask->word_mask <<
 606                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 607                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 608         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 609
 610         for (i = 0; i < nb_bitmask; i++) {
 611                 fd_mask = (flex_mask->bitmask[i].mask <<
 612                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 613                         I40E_PRTQF_FD_MSK_MASK_MASK;
 614                 fd_mask |= ((flex_mask->bitmask[i].offset +
 615                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 616                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 617                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 618                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 619         }
 620 }
 621
 622 /*
 623  * Configure flow director related setting
 624  */
 625 int
 626 i40e_fdir_configure(struct rte_eth_dev *dev)
 627 {
 628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630         struct rte_eth_fdir_flex_conf *conf;
 631         enum i40e_filter_pctype pctype;
 632         uint32_t val;
 633         uint8_t i;
 634         int ret = 0;
 635
 636         /*
 637         * configuration need to be done before
 638         * flow director filters are added
 639         * If filters exist, flush them.
 640         */
 641         if (i40e_fdir_empty(hw) < 0) {
 642                 ret = i40e_fdir_flush(dev);
 643                 if (ret) {
 644                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 645                         return ret;
 646                 }
 647         }
 648
 649         /* enable FDIR filter */
 650         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 651         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 652         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 653
 654         i40e_init_flx_pld(pf); /* set flex config to default value */
 655
 656         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 657         ret = i40e_check_fdir_flex_conf(conf);
 658         if (ret < 0) {
 659                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 660                 return -EINVAL;
 661         }
 662         /* configure flex payload */
 663         for (i = 0; i < conf->nb_payloads; i++)
 664                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 665         /* configure flex mask*/
 666         for (i = 0; i < conf->nb_flexmasks; i++) {
 667                 pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);
 668                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 669         }
 670
 671         return ret;
 672 }
 673
 674 static inline int
 675 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 676                            unsigned char *raw_pkt,
 677                            bool vlan)
 678 {
 679         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 680         uint16_t *ether_type;
 681         uint8_t len = 2 * sizeof(struct ether_addr);
 682         struct ipv4_hdr *ip;
 683         struct ipv6_hdr *ip6;
 684         static const uint8_t next_proto[] = {
 685                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 686                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 687                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 688                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 689                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 690                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 691                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 692                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 693                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 694                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 695         };
 696
 697         raw_pkt += 2 * sizeof(struct ether_addr);
 698         if (vlan && fdir_input->flow_ext.vlan_tci) {
 699                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 700                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 701                            &fdir_input->flow_ext.vlan_tci,
 702                            sizeof(uint16_t));
 703                 raw_pkt += sizeof(vlan_frame);
 704                 len += sizeof(vlan_frame);
 705         }
 706         ether_type = (uint16_t *)raw_pkt;
 707         raw_pkt += sizeof(uint16_t);
 708         len += sizeof(uint16_t);
 709
 710         switch (fdir_input->flow_type) {
 711         case RTE_ETH_FLOW_L2_PAYLOAD:
 712                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 713                 break;
 714         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 715         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 716         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 717         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 718         case RTE_ETH_FLOW_FRAG_IPV4:
 719                 ip = (struct ipv4_hdr *)raw_pkt;
 720
 721                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 722                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 723                 /* set len to by default */
 724                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 725                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 726                                         fdir_input->flow.ip4_flow.proto :
 727                                         next_proto[fdir_input->flow_type];
 728                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 729                                         fdir_input->flow.ip4_flow.ttl :
 730                                         I40E_FDIR_IP_DEFAULT_TTL;
 731                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 732                 /*
 733                  * The source and destination fields in the transmitted packet
 734                  * need to be presented in a reversed order with respect
 735                  * to the expected received packets.
 736                  */
 737                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 738                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 739                 len += sizeof(struct ipv4_hdr);
 740                 break;
 741         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 742         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 743         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 744         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 745         case RTE_ETH_FLOW_FRAG_IPV6:
 746                 ip6 = (struct ipv6_hdr *)raw_pkt;
 747
 748                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 749                 ip6->vtc_flow =
 750                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 751                                          (fdir_input->flow.ipv6_flow.tc <<
 752                                           I40E_FDIR_IPv6_TC_OFFSET));
 753                 ip6->payload_len =
 754                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 755                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 756                                         fdir_input->flow.ipv6_flow.proto :
 757                                         next_proto[fdir_input->flow_type];
 758                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 759                                         fdir_input->flow.ipv6_flow.hop_limits :
 760                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 761                 /*
 762                  * The source and destination fields in the transmitted packet
 763                  * need to be presented in a reversed order with respect
 764                  * to the expected received packets.
 765                  */
 766                 rte_memcpy(&(ip6->src_addr),
 767                            &(fdir_input->flow.ipv6_flow.dst_ip),
 768                            IPV6_ADDR_LEN);
 769                 rte_memcpy(&(ip6->dst_addr),
 770                            &(fdir_input->flow.ipv6_flow.src_ip),
 771                            IPV6_ADDR_LEN);
 772                 len += sizeof(struct ipv6_hdr);
 773                 break;
 774         default:
 775                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 776                             fdir_input->flow_type);
 777                 return -1;
 778         }
 779         return len;
 780 }
 781
 782
 783 /*
 784  * i40e_fdir_construct_pkt - construct packet based on fields in input
 785  * @pf: board private structure
 786  * @fdir_input: input set of the flow director entry
 787  * @raw_pkt: a packet to be constructed
 788  */
 789 static int
 790 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 791                              const struct rte_eth_fdir_input *fdir_input,
 792                              unsigned char *raw_pkt)
 793 {
 794         unsigned char *payload, *ptr;
 795         struct udp_hdr *udp;
 796         struct tcp_hdr *tcp;
 797         struct sctp_hdr *sctp;
 798         uint8_t size, dst = 0;
 799         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 800         int len;
 801
 802         /* fill the ethernet and IP head */
 803         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 804                                          !!fdir_input->flow_ext.vlan_tci);
 805         if (len < 0)
 806                 return -EINVAL;
 807
 808         /* fill the L4 head */
 809         switch (fdir_input->flow_type) {
 810         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 811                 udp = (struct udp_hdr *)(raw_pkt + len);
 812                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 813                 /*
 814                  * The source and destination fields in the transmitted packet
 815                  * need to be presented in a reversed order with respect
 816                  * to the expected received packets.
 817                  */
 818                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 819                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 820                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 821                 break;
 822
 823         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 824                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 825                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 826                 /*
 827                  * The source and destination fields in the transmitted packet
 828                  * need to be presented in a reversed order with respect
 829                  * to the expected received packets.
 830                  */
 831                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 832                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 833                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 834                 break;
 835
 836         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 837                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 838                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 839                 /*
 840                  * The source and destination fields in the transmitted packet
 841                  * need to be presented in a reversed order with respect
 842                  * to the expected received packets.
 843                  */
 844                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 845                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 846                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 847                 break;
 848
 849         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 850         case RTE_ETH_FLOW_FRAG_IPV4:
 851                 payload = raw_pkt + len;
 852                 set_idx = I40E_FLXPLD_L3_IDX;
 853                 break;
 854
 855         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 856                 udp = (struct udp_hdr *)(raw_pkt + len);
 857                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 858                 /*
 859                  * The source and destination fields in the transmitted packet
 860                  * need to be presented in a reversed order with respect
 861                  * to the expected received packets.
 862                  */
 863                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 864                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 865                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 866                 break;
 867
 868         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 869                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 870                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 871                 /*
 872                  * The source and destination fields in the transmitted packet
 873                  * need to be presented in a reversed order with respect
 874                  * to the expected received packets.
 875                  */
 876                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 877                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 878                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 879                 break;
 880
 881         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 882                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 883                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 884                 /*
 885                  * The source and destination fields in the transmitted packet
 886                  * need to be presented in a reversed order with respect
 887                  * to the expected received packets.
 888                  */
 889                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 890                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 891                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 892                 break;
 893
 894         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 895         case RTE_ETH_FLOW_FRAG_IPV6:
 896                 payload = raw_pkt + len;
 897                 set_idx = I40E_FLXPLD_L3_IDX;
 898                 break;
 899         case RTE_ETH_FLOW_L2_PAYLOAD:
 900                 payload = raw_pkt + len;
 901                 /*
 902                  * ARP packet is a special case on which the payload
 903                  * starts after the whole ARP header
 904                  */
 905                 if (fdir_input->flow.l2_flow.ether_type ==
 906                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 907                         payload += sizeof(struct arp_hdr);
 908                 set_idx = I40E_FLXPLD_L2_IDX;
 909                 break;
 910         default:
 911                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 912                 return -EINVAL;
 913         }
 914
 915         /* fill the flexbytes to payload */
 916         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 917                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 918                 size = pf->fdir.flex_set[pit_idx].size;
 919                 if (size == 0)
 920                         continue;
 921                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 922                 ptr = payload +
 923                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 924                 (void)rte_memcpy(ptr,
 925                                  &fdir_input->flow_ext.flexbytes[dst],
 926                                  size * sizeof(uint16_t));
 927         }
 928
 929         return 0;
 930 }
 931
 932 /* Construct the tx flags */
 933 static inline uint64_t
 934 i40e_build_ctob(uint32_t td_cmd,
 935                 uint32_t td_offset,
 936                 unsigned int size,
 937                 uint32_t td_tag)
 938 {
 939         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 940                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 941                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 942                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 943                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 944 }
 945
 946 /*
 947  * check the programming status descriptor in rx queue.
 948  * done after Programming Flow Director is programmed on
 949  * tx queue
 950  */
 951 static inline int
 952 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 953 {
 954         volatile union i40e_rx_desc *rxdp;
 955         uint64_t qword1;
 956         uint32_t rx_status;
 957         uint32_t len, id;
 958         uint32_t error;
 959         int ret = 0;
 960
 961         rxdp = &rxq->rx_ring[rxq->rx_tail];
 962         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 963         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 964                         >> I40E_RXD_QW1_STATUS_SHIFT;
 965
 966         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 967                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 968                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 969                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 970
 971                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 972                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 973                         error = (qword1 &
 974                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 975                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 976                         if (error == (0x1 <<
 977                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 978                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 979                                             " (FD_ID %u): programming status"
 980                                             " reported.",
 981                                             rxdp->wb.qword0.hi_dword.fd_id);
 982                                 ret = -1;
 983                         } else if (error == (0x1 <<
 984                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 985                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 986                                             " (FD_ID %u): programming status"
 987                                             " reported.",
 988                                             rxdp->wb.qword0.hi_dword.fd_id);
 989                                 ret = -1;
 990                         } else
 991                                 PMD_DRV_LOG(ERR, "invalid programming status"
 992                                             " reported, error = %u.", error);
 993                 } else
 994                         PMD_DRV_LOG(ERR, "unknown programming status"
 995                                     " reported, len = %d, id = %u.", len, id);
 996                 rxdp->wb.qword1.status_error_len = 0;
 997                 rxq->rx_tail++;
 998                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 999                         rxq->rx_tail = 0;
1000         }
1001         return ret;
1002 }
1003
1004 /*
1005  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1006  * @pf: board private structure
1007  * @filter: fdir filter entry
1008  * @add: 0 - delete, 1 - add
1009  */
1010 static int
1011 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1012                             const struct rte_eth_fdir_filter *filter,
1013                             bool add)
1014 {
1015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1016         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1017         enum i40e_filter_pctype pctype;
1018         int ret = 0;
1019
1020         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1021                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1022                         " check the mode in fdir_conf.");
1023                 return -ENOTSUP;
1024         }
1025
1026         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1027                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1028                 return -EINVAL;
1029         }
1030         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1031                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1032                 return -EINVAL;
1033         }
1034         if (filter->input.flow_ext.is_vf &&
1035                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1036                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1037                 return -EINVAL;
1038         }
1039
1040         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1041
1042         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1043         if (ret < 0) {
1044                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1045                 return ret;
1046         }
1047         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1048         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1049         if (ret < 0) {
1050                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1051                             pctype);
1052                 return ret;
1053         }
1054         return ret;
1055 }
1056
1057 /*
1058  * i40e_fdir_filter_programming - Program a flow director filter rule.
1059  * Is done by Flow Director Programming Descriptor followed by packet
1060  * structure that contains the filter fields need to match.
1061  * @pf: board private structure
1062  * @pctype: pctype
1063  * @filter: fdir filter entry
1064  * @add: 0 - delete, 1 - add
1065  */
1066 static int
1067 i40e_fdir_filter_programming(struct i40e_pf *pf,
1068                         enum i40e_filter_pctype pctype,
1069                         const struct rte_eth_fdir_filter *filter,
1070                         bool add)
1071 {
1072         struct i40e_tx_queue *txq = pf->fdir.txq;
1073         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1074         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1075         volatile struct i40e_tx_desc *txdp;
1076         volatile struct i40e_filter_program_desc *fdirdp;
1077         uint32_t td_cmd;
1078         uint16_t vsi_id, i;
1079         uint8_t dest;
1080
1081         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1082         fdirdp = (volatile struct i40e_filter_program_desc *)
1083                         (&(txq->tx_ring[txq->tx_tail]));
1084
1085         fdirdp->qindex_flex_ptype_vsi =
1086                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1087                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1088                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1089
1090         fdirdp->qindex_flex_ptype_vsi |=
1091                         rte_cpu_to_le_32((fdir_action->flex_off <<
1092                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1093                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1094
1095         fdirdp->qindex_flex_ptype_vsi |=
1096                         rte_cpu_to_le_32((pctype <<
1097                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1098                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1099
1100         if (filter->input.flow_ext.is_vf)
1101                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1102         else
1103                 /* Use LAN VSI Id by default */
1104                 vsi_id = pf->main_vsi->vsi_id;
1105         fdirdp->qindex_flex_ptype_vsi |=
1106                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1107                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1108                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1109
1110         fdirdp->dtype_cmd_cntindex =
1111                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1112
1113         if (add)
1114                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1115                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1116                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1117         else
1118                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1119                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1120                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1121
1122         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1123                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1124         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1125                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1126         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1127                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1128         else {
1129                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1130                             " unsupported fdir behavior.");
1131                 return -EINVAL;
1132         }
1133
1134         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1135                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1136                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1137
1138         fdirdp->dtype_cmd_cntindex |=
1139                 rte_cpu_to_le_32((fdir_action->report_status<<
1140                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1141                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1142
1143         fdirdp->dtype_cmd_cntindex |=
1144                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1145         fdirdp->dtype_cmd_cntindex |=
1146                         rte_cpu_to_le_32(
1147                         ((uint32_t)pf->fdir.match_counter_index <<
1148                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1149                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1150
1151         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1152
1153         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1154         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1155         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1156         td_cmd = I40E_TX_DESC_CMD_EOP |
1157                  I40E_TX_DESC_CMD_RS  |
1158                  I40E_TX_DESC_CMD_DUMMY;
1159
1160         txdp->cmd_type_offset_bsz =
1161                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1162
1163         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1164         if (txq->tx_tail >= txq->nb_tx_desc)
1165                 txq->tx_tail = 0;
1166         /* Update the tx tail register */
1167         rte_wmb();
1168         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1169
1170         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1171                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1172                 if ((txdp->cmd_type_offset_bsz &
1173                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1174                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1175                         break;
1176         }
1177         if (i >= I40E_FDIR_WAIT_COUNT) {
1178                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1179                             " time out to get DD on tx queue.");
1180                 return -ETIMEDOUT;
1181         }
1182         /* totally delay 10 ms to check programming status*/
1183         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1184         if (i40e_check_fdir_programming_status(rxq) < 0) {
1185                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1186                             " programming status reported.");
1187                 return -ENOSYS;
1188         }
1189
1190         return 0;
1191 }
1192
1193 /*
1194  * i40e_fdir_flush - clear all filters of Flow Director table
1195  * @pf: board private structure
1196  */
1197 static int
1198 i40e_fdir_flush(struct rte_eth_dev *dev)
1199 {
1200         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1201         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1202         uint32_t reg;
1203         uint16_t guarant_cnt, best_cnt;
1204         uint16_t i;
1205
1206         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1207         I40E_WRITE_FLUSH(hw);
1208
1209         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1210                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1211                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1212                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1213                         break;
1214         }
1215         if (i >= I40E_FDIR_FLUSH_RETRY) {
1216                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1217                 return -ETIMEDOUT;
1218         }
1219         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1220                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1221                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1222         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1223                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1224                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1225         if (guarant_cnt != 0 || best_cnt != 0) {
1226                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1227                 return -ENOSYS;
1228         } else
1229                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1230         return 0;
1231 }
1232
1233 static inline void
1234 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1235                         struct rte_eth_flex_payload_cfg *flex_set,
1236                         uint16_t *num)
1237 {
1238         struct i40e_fdir_flex_pit *flex_pit;
1239         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1240         uint16_t src, dst, size, j, k;
1241         uint8_t i, layer_idx;
1242
1243         for (layer_idx = I40E_FLXPLD_L2_IDX;
1244              layer_idx <= I40E_FLXPLD_L4_IDX;
1245              layer_idx++) {
1246                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1247                         ptr->type = RTE_ETH_L2_PAYLOAD;
1248                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1249                         ptr->type = RTE_ETH_L3_PAYLOAD;
1250                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1251                         ptr->type = RTE_ETH_L4_PAYLOAD;
1252
1253                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1254                         flex_pit = &pf->fdir.flex_set[layer_idx *
1255                                 I40E_MAX_FLXPLD_FIED + i];
1256                         if (flex_pit->size == 0)
1257                                 continue;
1258                         src = flex_pit->src_offset * sizeof(uint16_t);
1259                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1260                         size = flex_pit->size * sizeof(uint16_t);
1261                         for (j = src, k = dst; j < src + size; j++, k++)
1262                                 ptr->src_offset[k] = j;
1263                 }
1264                 (*num)++;
1265                 ptr++;
1266         }
1267 }
1268
1269 static inline void
1270 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1271                         struct rte_eth_fdir_flex_mask *flex_mask,
1272                         uint16_t *num)
1273 {
1274         struct i40e_fdir_flex_mask *mask;
1275         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1276         uint16_t flow_type;
1277         uint8_t i, j;
1278         uint16_t off_bytes, mask_tmp;
1279
1280         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1281              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1282              i++) {
1283                 mask =  &pf->fdir.flex_mask[i];
1284                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1285                         continue;
1286                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1287                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1288                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1289                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1290                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1291                         } else {
1292                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1293                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1294                         }
1295                 }
1296                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1297                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1298                         mask_tmp = ~mask->bitmask[j].mask;
1299                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1300                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1301                 }
1302                 ptr->flow_type = flow_type;
1303                 ptr++;
1304                 (*num)++;
1305         }
1306 }
1307
1308 /*
1309  * i40e_fdir_info_get - get information of Flow Director
1310  * @pf: ethernet device to get info from
1311  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1312  *    the flow director information.
1313  */
1314 static void
1315 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1316 {
1317         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1318         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1319         uint16_t num_flex_set = 0;
1320         uint16_t num_flex_mask = 0;
1321
1322         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1323                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1324         else
1325                 fdir->mode = RTE_FDIR_MODE_NONE;
1326
1327         fdir->guarant_spc =
1328                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1329         fdir->best_spc =
1330                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1331         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1332         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1333         fdir->flex_payload_unit = sizeof(uint16_t);
1334         fdir->flex_bitmask_unit = sizeof(uint16_t);
1335         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1336         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1337         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1338
1339         i40e_fdir_info_get_flex_set(pf,
1340                                 fdir->flex_conf.flex_set,
1341                                 &num_flex_set);
1342         i40e_fdir_info_get_flex_mask(pf,
1343                                 fdir->flex_conf.flex_mask,
1344                                 &num_flex_mask);
1345
1346         fdir->flex_conf.nb_payloads = num_flex_set;
1347         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1348 }
1349
1350 /*
1351  * i40e_fdir_stat_get - get statistics of Flow Director
1352  * @pf: ethernet device to get info from
1353  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1354  *    the flow director statistics.
1355  */
1356 static void
1357 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1358 {
1359         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1360         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1361         uint32_t fdstat;
1362
1363         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1364         stat->guarant_cnt =
1365                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1366                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1367         stat->best_cnt =
1368                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1369                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1370 }
1371
1372 static int
1373 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1374                      struct rte_eth_fdir_filter_info *info)
1375 {
1376         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1377         int ret = 0;
1378
1379         if (!info) {
1380                 PMD_DRV_LOG(ERR, "Invalid pointer");
1381                 return -EFAULT;
1382         }
1383
1384         switch (info->info_type) {
1385         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1386                 ret = i40e_fdir_filter_inset_select(pf,
1387                                 &(info->info.input_set_conf));
1388                 break;
1389         default:
1390                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1391                             info->info_type);
1392                 return -EINVAL;
1393         }
1394
1395         return ret;
1396 }
1397
1398 /*
1399  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1400  * @pf: board private structure
1401  * @filter_op:operation will be taken.
1402  * @arg: a pointer to specific structure corresponding to the filter_op
1403  */
1404 int
1405 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1406                        enum rte_filter_op filter_op,
1407                        void *arg)
1408 {
1409         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1410         int ret = 0;
1411
1412         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1413                 return -ENOTSUP;
1414
1415         if (filter_op == RTE_ETH_FILTER_NOP)
1416                 return 0;
1417
1418         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1419                 return -EINVAL;
1420
1421         switch (filter_op) {
1422         case RTE_ETH_FILTER_ADD:
1423                 ret = i40e_add_del_fdir_filter(dev,
1424                         (struct rte_eth_fdir_filter *)arg,
1425                         TRUE);
1426                 break;
1427         case RTE_ETH_FILTER_DELETE:
1428                 ret = i40e_add_del_fdir_filter(dev,
1429                         (struct rte_eth_fdir_filter *)arg,
1430                         FALSE);
1431                 break;
1432         case RTE_ETH_FILTER_FLUSH:
1433                 ret = i40e_fdir_flush(dev);
1434                 break;
1435         case RTE_ETH_FILTER_INFO:
1436                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1437                 break;
1438         case RTE_ETH_FILTER_SET:
1439                 ret = i40e_fdir_filter_set(dev,
1440                         (struct rte_eth_fdir_filter_info *)arg);
1441                 break;
1442         case RTE_ETH_FILTER_STATS:
1443                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1444                 break;
1445         default:
1446                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1447                 ret = -EINVAL;
1448                 break;
1449         }
1450         return ret;
1451 }