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34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
71 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
72 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
73 #define I40E_FDIR_UDP_DEFAULT_LEN 400
75 /* Wait time for fdir filter programming */
76 #define I40E_FDIR_MAX_WAIT_US 10000
78 /* Wait count and interval for fdir filter flush */
79 #define I40E_FDIR_FLUSH_RETRY 50
80 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
82 #define I40E_COUNTER_PF 2
83 /* Statistic counter index for one pf */
84 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
86 #define I40E_FDIR_FLOWS ( \
87 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
88 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
89 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
90 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
91 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
92 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
93 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
94 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
95 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
96 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
97 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
99 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
100 enum i40e_filter_pctype pctype,
101 const struct rte_eth_fdir_filter *filter,
103 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
104 struct i40e_fdir_filter *filter);
105 static struct i40e_fdir_filter *
106 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
107 const struct i40e_fdir_input *input);
108 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
109 struct i40e_fdir_filter *filter);
111 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
112 enum i40e_filter_pctype pctype,
113 const struct i40e_fdir_filter_conf *filter,
117 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
119 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
120 struct i40e_hmc_obj_rxq rx_ctx;
121 int err = I40E_SUCCESS;
123 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
124 /* Init the RX queue in hardware */
125 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
127 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
128 rx_ctx.qlen = rxq->nb_rx_desc;
129 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
132 rx_ctx.dtype = i40e_header_split_none;
133 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
134 rx_ctx.rxmax = ETHER_MAX_LEN;
135 rx_ctx.tphrdesc_ena = 1;
136 rx_ctx.tphwdesc_ena = 1;
137 rx_ctx.tphdata_ena = 1;
138 rx_ctx.tphhead_ena = 1;
139 rx_ctx.lrxqthresh = 2;
145 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
146 if (err != I40E_SUCCESS) {
147 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
150 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
151 if (err != I40E_SUCCESS) {
152 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
155 rxq->qrx_tail = hw->hw_addr +
156 I40E_QRX_TAIL(rxq->vsi->base_queue);
159 /* Init the RX tail regieter. */
160 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
161 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
167 * i40e_fdir_setup - reserve and initialize the Flow Director resources
168 * @pf: board private structure
171 i40e_fdir_setup(struct i40e_pf *pf)
173 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
174 struct i40e_vsi *vsi;
175 int err = I40E_SUCCESS;
176 char z_name[RTE_MEMZONE_NAMESIZE];
177 const struct rte_memzone *mz = NULL;
178 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
180 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
181 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
182 return I40E_NOT_SUPPORTED;
185 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
186 " num_filters_best_effort = %u.",
187 hw->func_caps.fd_filters_guaranteed,
188 hw->func_caps.fd_filters_best_effort);
190 vsi = pf->fdir.fdir_vsi;
192 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
195 /* make new FDIR VSI */
196 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
198 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
199 return I40E_ERR_NO_AVAILABLE_VSI;
201 pf->fdir.fdir_vsi = vsi;
203 /*Fdir tx queue setup*/
204 err = i40e_fdir_setup_tx_resources(pf);
206 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
210 /*Fdir rx queue setup*/
211 err = i40e_fdir_setup_rx_resources(pf);
213 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
217 err = i40e_tx_queue_init(pf->fdir.txq);
219 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
223 /* need switch on before dev start*/
224 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
226 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
230 /* Init the rx queue in hardware */
231 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
233 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
237 /* switch on rx queue */
238 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
240 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
244 /* reserve memory for the fdir programming packet */
245 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
246 eth_dev->device->driver->name,
248 eth_dev->data->port_id);
249 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
251 PMD_DRV_LOG(ERR, "Cannot init memzone for "
252 "flow director program packet.");
253 err = I40E_ERR_NO_MEMORY;
256 pf->fdir.prg_pkt = mz->addr;
257 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
259 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
260 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
265 i40e_dev_rx_queue_release(pf->fdir.rxq);
268 i40e_dev_tx_queue_release(pf->fdir.txq);
271 i40e_vsi_release(vsi);
272 pf->fdir.fdir_vsi = NULL;
277 * i40e_fdir_teardown - release the Flow Director resources
278 * @pf: board private structure
281 i40e_fdir_teardown(struct i40e_pf *pf)
283 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
284 struct i40e_vsi *vsi;
286 vsi = pf->fdir.fdir_vsi;
289 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
291 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
292 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
294 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
295 i40e_dev_rx_queue_release(pf->fdir.rxq);
297 i40e_dev_tx_queue_release(pf->fdir.txq);
299 i40e_vsi_release(vsi);
300 pf->fdir.fdir_vsi = NULL;
303 /* check whether the flow director table in empty */
305 i40e_fdir_empty(struct i40e_hw *hw)
307 uint32_t guarant_cnt, best_cnt;
309 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
310 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
311 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
312 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
313 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
314 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
315 if (best_cnt + guarant_cnt > 0)
322 * Initialize the configuration about bytes stream extracted as flexible payload
326 i40e_init_flx_pld(struct i40e_pf *pf)
328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
334 * Define the bytes stream extracted as flexible payload in
335 * field vector. By default, select 8 words from the beginning
336 * of payload as flexible payload.
338 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
339 index = i * I40E_MAX_FLXPLD_FIED;
340 pf->fdir.flex_set[index].src_offset = 0;
341 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
342 pf->fdir.flex_set[index].dst_offset = 0;
343 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
345 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
347 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
350 /* initialize the masks */
351 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
352 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
353 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
355 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
357 pf->fdir.flex_mask[pctype].word_mask = 0;
358 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
359 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
360 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
361 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
362 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
367 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
368 if ((flex_pit2).src_offset < \
369 (flex_pit1).src_offset + (flex_pit1).size) { \
370 PMD_DRV_LOG(ERR, "src_offset should be not" \
371 " less than than previous offset" \
372 " + previous FSIZE."); \
378 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
379 * and the flex_pit will be sorted by it's src_offset value
381 static inline uint16_t
382 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
383 struct i40e_fdir_flex_pit *flex_pit)
385 uint16_t src_tmp, size, num = 0;
386 uint16_t i, k, j = 0;
388 while (j < I40E_FDIR_MAX_FLEX_LEN) {
390 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
391 if (src_offset[j + 1] == src_offset[j] + 1)
396 src_tmp = src_offset[j] + 1 - size;
397 /* the flex_pit need to be sort by src_offset */
398 for (i = 0; i < num; i++) {
399 if (src_tmp < flex_pit[i].src_offset)
402 /* if insert required, move backward */
403 for (k = num; k > i; k--)
404 flex_pit[k] = flex_pit[k - 1];
406 flex_pit[i].dst_offset = j + 1 - size;
407 flex_pit[i].src_offset = src_tmp;
408 flex_pit[i].size = size;
415 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
417 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
419 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
422 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
423 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
424 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
429 memset(flex_pit, 0, sizeof(flex_pit));
430 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
431 if (num > I40E_MAX_FLXPLD_FIED) {
432 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
435 for (i = 0; i < num; i++) {
436 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
437 flex_pit[i].src_offset & 0x01) {
438 PMD_DRV_LOG(ERR, "flexpayload should be measured"
443 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
449 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
450 * arguments are valid
453 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
454 const struct rte_eth_fdir_flex_conf *conf)
456 const struct rte_eth_flex_payload_cfg *flex_cfg;
457 const struct rte_eth_fdir_flex_mask *flex_mask;
462 enum i40e_filter_pctype pctype;
465 PMD_DRV_LOG(INFO, "NULL pointer.");
468 /* check flexible payload setting configuration */
469 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
470 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
473 for (i = 0; i < conf->nb_payloads; i++) {
474 flex_cfg = &conf->flex_set[i];
475 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
476 PMD_DRV_LOG(ERR, "invalid payload type.");
479 ret = i40e_check_fdir_flex_payload(flex_cfg);
481 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
486 /* check flex mask setting configuration */
487 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
488 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
491 for (i = 0; i < conf->nb_flexmasks; i++) {
492 flex_mask = &conf->flex_mask[i];
493 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
494 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
495 PMD_DRV_LOG(WARNING, "invalid flow type.");
499 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
500 mask_tmp = I40E_WORD(flex_mask->mask[j],
501 flex_mask->mask[j + 1]);
502 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
504 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
505 PMD_DRV_LOG(ERR, " exceed maximal"
506 " number of bitmasks.");
516 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
517 * @pf: board private structure
518 * @cfg: the rule how bytes stream is extracted as flexible payload
521 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
522 const struct rte_eth_flex_payload_cfg *cfg)
524 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
525 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
527 uint16_t num, min_next_off; /* in words */
528 uint8_t field_idx = 0;
529 uint8_t layer_idx = 0;
532 if (cfg->type == RTE_ETH_L2_PAYLOAD)
533 layer_idx = I40E_FLXPLD_L2_IDX;
534 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
535 layer_idx = I40E_FLXPLD_L3_IDX;
536 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
537 layer_idx = I40E_FLXPLD_L4_IDX;
539 memset(flex_pit, 0, sizeof(flex_pit));
540 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
542 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
543 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
544 /* record the info in fdir structure */
545 pf->fdir.flex_set[field_idx].src_offset =
546 flex_pit[i].src_offset / sizeof(uint16_t);
547 pf->fdir.flex_set[field_idx].size =
548 flex_pit[i].size / sizeof(uint16_t);
549 pf->fdir.flex_set[field_idx].dst_offset =
550 flex_pit[i].dst_offset / sizeof(uint16_t);
551 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
552 pf->fdir.flex_set[field_idx].size,
553 pf->fdir.flex_set[field_idx].dst_offset);
555 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
557 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
558 pf->fdir.flex_set[field_idx].size;
560 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
561 /* set the non-used register obeying register's constrain */
562 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
563 NONUSE_FLX_PIT_DEST_OFF);
565 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
572 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
573 * @pf: board private structure
574 * @pctype: packet classify type
575 * @flex_masks: mask for flexible payload
578 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
579 enum i40e_filter_pctype pctype,
580 const struct rte_eth_fdir_flex_mask *mask_cfg)
582 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
583 struct i40e_fdir_flex_mask *flex_mask;
584 uint32_t flxinset, fd_mask;
586 uint8_t i, nb_bitmask = 0;
588 flex_mask = &pf->fdir.flex_mask[pctype];
589 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
590 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
591 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
592 if (mask_tmp != 0x0) {
593 flex_mask->word_mask |=
594 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
595 if (mask_tmp != UINT16_MAX) {
597 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
598 flex_mask->bitmask[nb_bitmask].offset =
599 i / sizeof(uint16_t);
604 /* write mask to hw */
605 flxinset = (flex_mask->word_mask <<
606 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
607 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
608 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
610 for (i = 0; i < nb_bitmask; i++) {
611 fd_mask = (flex_mask->bitmask[i].mask <<
612 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
613 I40E_PRTQF_FD_MSK_MASK_MASK;
614 fd_mask |= ((flex_mask->bitmask[i].offset +
615 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
616 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
617 I40E_PRTQF_FD_MSK_OFFSET_MASK;
618 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
623 * Configure flow director related setting
626 i40e_fdir_configure(struct rte_eth_dev *dev)
628 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
629 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630 struct rte_eth_fdir_flex_conf *conf;
631 enum i40e_filter_pctype pctype;
637 * configuration need to be done before
638 * flow director filters are added
639 * If filters exist, flush them.
641 if (i40e_fdir_empty(hw) < 0) {
642 ret = i40e_fdir_flush(dev);
644 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
649 /* enable FDIR filter */
650 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
651 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
652 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
654 i40e_init_flx_pld(pf); /* set flex config to default value */
656 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
657 ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
659 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
662 /* configure flex payload */
663 for (i = 0; i < conf->nb_payloads; i++)
664 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
665 /* configure flex mask*/
666 for (i = 0; i < conf->nb_flexmasks; i++) {
667 if (hw->mac.type == I40E_MAC_X722) {
668 /* get translated pctype value in fd pctype register */
669 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
670 hw, I40E_GLQF_FD_PCTYPES(
671 (int)i40e_flowtype_to_pctype(pf->adapter,
672 conf->flex_mask[i].flow_type)));
674 pctype = i40e_flowtype_to_pctype(pf->adapter,
675 conf->flex_mask[i].flow_type);
677 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
684 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
685 unsigned char *raw_pkt,
688 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
689 uint16_t *ether_type;
690 uint8_t len = 2 * sizeof(struct ether_addr);
692 struct ipv6_hdr *ip6;
693 static const uint8_t next_proto[] = {
694 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
695 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
696 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
697 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
698 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
699 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
700 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
701 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
702 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
703 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
706 raw_pkt += 2 * sizeof(struct ether_addr);
707 if (vlan && fdir_input->flow_ext.vlan_tci) {
708 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
709 rte_memcpy(raw_pkt + sizeof(uint16_t),
710 &fdir_input->flow_ext.vlan_tci,
712 raw_pkt += sizeof(vlan_frame);
713 len += sizeof(vlan_frame);
715 ether_type = (uint16_t *)raw_pkt;
716 raw_pkt += sizeof(uint16_t);
717 len += sizeof(uint16_t);
719 switch (fdir_input->flow_type) {
720 case RTE_ETH_FLOW_L2_PAYLOAD:
721 *ether_type = fdir_input->flow.l2_flow.ether_type;
723 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
724 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
725 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
726 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
727 case RTE_ETH_FLOW_FRAG_IPV4:
728 ip = (struct ipv4_hdr *)raw_pkt;
730 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
731 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
732 /* set len to by default */
733 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
734 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
735 fdir_input->flow.ip4_flow.proto :
736 next_proto[fdir_input->flow_type];
737 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
738 fdir_input->flow.ip4_flow.ttl :
739 I40E_FDIR_IP_DEFAULT_TTL;
740 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
742 * The source and destination fields in the transmitted packet
743 * need to be presented in a reversed order with respect
744 * to the expected received packets.
746 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
747 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
748 len += sizeof(struct ipv4_hdr);
750 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
751 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
752 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
753 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
754 case RTE_ETH_FLOW_FRAG_IPV6:
755 ip6 = (struct ipv6_hdr *)raw_pkt;
757 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
759 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
760 (fdir_input->flow.ipv6_flow.tc <<
761 I40E_FDIR_IPv6_TC_OFFSET));
763 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
764 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
765 fdir_input->flow.ipv6_flow.proto :
766 next_proto[fdir_input->flow_type];
767 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
768 fdir_input->flow.ipv6_flow.hop_limits :
769 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
771 * The source and destination fields in the transmitted packet
772 * need to be presented in a reversed order with respect
773 * to the expected received packets.
775 rte_memcpy(&(ip6->src_addr),
776 &(fdir_input->flow.ipv6_flow.dst_ip),
778 rte_memcpy(&(ip6->dst_addr),
779 &(fdir_input->flow.ipv6_flow.src_ip),
781 len += sizeof(struct ipv6_hdr);
784 PMD_DRV_LOG(ERR, "unknown flow type %u.",
785 fdir_input->flow_type);
793 * i40e_fdir_construct_pkt - construct packet based on fields in input
794 * @pf: board private structure
795 * @fdir_input: input set of the flow director entry
796 * @raw_pkt: a packet to be constructed
799 i40e_fdir_construct_pkt(struct i40e_pf *pf,
800 const struct rte_eth_fdir_input *fdir_input,
801 unsigned char *raw_pkt)
803 unsigned char *payload, *ptr;
806 struct sctp_hdr *sctp;
807 uint8_t size, dst = 0;
808 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
811 /* fill the ethernet and IP head */
812 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
813 !!fdir_input->flow_ext.vlan_tci);
817 /* fill the L4 head */
818 switch (fdir_input->flow_type) {
819 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
820 udp = (struct udp_hdr *)(raw_pkt + len);
821 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
823 * The source and destination fields in the transmitted packet
824 * need to be presented in a reversed order with respect
825 * to the expected received packets.
827 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
828 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
829 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
832 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
833 tcp = (struct tcp_hdr *)(raw_pkt + len);
834 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
836 * The source and destination fields in the transmitted packet
837 * need to be presented in a reversed order with respect
838 * to the expected received packets.
840 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
841 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
842 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
845 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
846 sctp = (struct sctp_hdr *)(raw_pkt + len);
847 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
849 * The source and destination fields in the transmitted packet
850 * need to be presented in a reversed order with respect
851 * to the expected received packets.
853 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
854 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
855 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
858 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
859 case RTE_ETH_FLOW_FRAG_IPV4:
860 payload = raw_pkt + len;
861 set_idx = I40E_FLXPLD_L3_IDX;
864 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
865 udp = (struct udp_hdr *)(raw_pkt + len);
866 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
868 * The source and destination fields in the transmitted packet
869 * need to be presented in a reversed order with respect
870 * to the expected received packets.
872 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
873 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
874 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
877 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
878 tcp = (struct tcp_hdr *)(raw_pkt + len);
879 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
881 * The source and destination fields in the transmitted packet
882 * need to be presented in a reversed order with respect
883 * to the expected received packets.
885 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
886 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
887 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
890 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
891 sctp = (struct sctp_hdr *)(raw_pkt + len);
892 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
894 * The source and destination fields in the transmitted packet
895 * need to be presented in a reversed order with respect
896 * to the expected received packets.
898 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
899 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
900 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
903 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
904 case RTE_ETH_FLOW_FRAG_IPV6:
905 payload = raw_pkt + len;
906 set_idx = I40E_FLXPLD_L3_IDX;
908 case RTE_ETH_FLOW_L2_PAYLOAD:
909 payload = raw_pkt + len;
911 * ARP packet is a special case on which the payload
912 * starts after the whole ARP header
914 if (fdir_input->flow.l2_flow.ether_type ==
915 rte_cpu_to_be_16(ETHER_TYPE_ARP))
916 payload += sizeof(struct arp_hdr);
917 set_idx = I40E_FLXPLD_L2_IDX;
920 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
924 /* fill the flexbytes to payload */
925 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
926 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
927 size = pf->fdir.flex_set[pit_idx].size;
930 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
932 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
934 &fdir_input->flow_ext.flexbytes[dst],
935 size * sizeof(uint16_t));
942 i40e_flow_fdir_fill_eth_ip_head(const struct i40e_fdir_input *fdir_input,
943 unsigned char *raw_pkt,
946 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
947 uint16_t *ether_type;
948 uint8_t len = 2 * sizeof(struct ether_addr);
950 struct ipv6_hdr *ip6;
951 static const uint8_t next_proto[] = {
952 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
953 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
954 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
955 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
956 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
957 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
958 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
959 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
960 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
961 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
964 raw_pkt += 2 * sizeof(struct ether_addr);
965 if (vlan && fdir_input->flow_ext.vlan_tci) {
966 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
967 rte_memcpy(raw_pkt + sizeof(uint16_t),
968 &fdir_input->flow_ext.vlan_tci,
970 raw_pkt += sizeof(vlan_frame);
971 len += sizeof(vlan_frame);
973 ether_type = (uint16_t *)raw_pkt;
974 raw_pkt += sizeof(uint16_t);
975 len += sizeof(uint16_t);
977 switch (fdir_input->pctype) {
978 case I40E_FILTER_PCTYPE_L2_PAYLOAD:
979 *ether_type = fdir_input->flow.l2_flow.ether_type;
981 case I40E_FILTER_PCTYPE_NONF_IPV4_TCP:
982 case I40E_FILTER_PCTYPE_NONF_IPV4_UDP:
983 case I40E_FILTER_PCTYPE_NONF_IPV4_SCTP:
984 case I40E_FILTER_PCTYPE_NONF_IPV4_OTHER:
985 case I40E_FILTER_PCTYPE_FRAG_IPV4:
986 ip = (struct ipv4_hdr *)raw_pkt;
988 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
989 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
990 /* set len to by default */
991 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
992 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
993 fdir_input->flow.ip4_flow.proto :
994 next_proto[fdir_input->pctype];
995 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
996 fdir_input->flow.ip4_flow.ttl :
997 I40E_FDIR_IP_DEFAULT_TTL;
998 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
1000 * The source and destination fields in the transmitted packet
1001 * need to be presented in a reversed order with respect
1002 * to the expected received packets.
1004 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1005 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1006 len += sizeof(struct ipv4_hdr);
1008 case I40E_FILTER_PCTYPE_NONF_IPV6_TCP:
1009 case I40E_FILTER_PCTYPE_NONF_IPV6_UDP:
1010 case I40E_FILTER_PCTYPE_NONF_IPV6_SCTP:
1011 case I40E_FILTER_PCTYPE_NONF_IPV6_OTHER:
1012 case I40E_FILTER_PCTYPE_FRAG_IPV6:
1013 ip6 = (struct ipv6_hdr *)raw_pkt;
1015 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
1017 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1018 (fdir_input->flow.ipv6_flow.tc <<
1019 I40E_FDIR_IPv6_TC_OFFSET));
1021 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1022 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1023 fdir_input->flow.ipv6_flow.proto :
1024 next_proto[fdir_input->pctype];
1025 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1026 fdir_input->flow.ipv6_flow.hop_limits :
1027 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1029 * The source and destination fields in the transmitted packet
1030 * need to be presented in a reversed order with respect
1031 * to the expected received packets.
1033 rte_memcpy(&ip6->src_addr,
1034 &fdir_input->flow.ipv6_flow.dst_ip,
1036 rte_memcpy(&ip6->dst_addr,
1037 &fdir_input->flow.ipv6_flow.src_ip,
1039 len += sizeof(struct ipv6_hdr);
1042 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1043 fdir_input->pctype);
1050 * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1051 * @pf: board private structure
1052 * @fdir_input: input set of the flow director entry
1053 * @raw_pkt: a packet to be constructed
1056 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1057 const struct i40e_fdir_input *fdir_input,
1058 unsigned char *raw_pkt)
1060 unsigned char *payload, *ptr;
1061 struct udp_hdr *udp;
1062 struct tcp_hdr *tcp;
1063 struct sctp_hdr *sctp;
1064 uint8_t size, dst = 0;
1065 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1068 /* fill the ethernet and IP head */
1069 len = i40e_flow_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
1070 !!fdir_input->flow_ext.vlan_tci);
1074 /* fill the L4 head */
1075 switch (fdir_input->pctype) {
1076 case I40E_FILTER_PCTYPE_NONF_IPV4_UDP:
1077 udp = (struct udp_hdr *)(raw_pkt + len);
1078 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1080 * The source and destination fields in the transmitted packet
1081 * need to be presented in a reversed order with respect
1082 * to the expected received packets.
1084 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1085 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1086 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1089 case I40E_FILTER_PCTYPE_NONF_IPV4_TCP:
1090 tcp = (struct tcp_hdr *)(raw_pkt + len);
1091 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1093 * The source and destination fields in the transmitted packet
1094 * need to be presented in a reversed order with respect
1095 * to the expected received packets.
1097 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1098 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1099 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1102 case I40E_FILTER_PCTYPE_NONF_IPV4_SCTP:
1103 sctp = (struct sctp_hdr *)(raw_pkt + len);
1104 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1106 * The source and destination fields in the transmitted packet
1107 * need to be presented in a reversed order with respect
1108 * to the expected received packets.
1110 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1111 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1112 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1115 case I40E_FILTER_PCTYPE_NONF_IPV4_OTHER:
1116 case I40E_FILTER_PCTYPE_FRAG_IPV4:
1117 payload = raw_pkt + len;
1118 set_idx = I40E_FLXPLD_L3_IDX;
1121 case I40E_FILTER_PCTYPE_NONF_IPV6_UDP:
1122 udp = (struct udp_hdr *)(raw_pkt + len);
1123 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1125 * The source and destination fields in the transmitted packet
1126 * need to be presented in a reversed order with respect
1127 * to the expected received packets.
1129 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1130 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1131 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1134 case I40E_FILTER_PCTYPE_NONF_IPV6_TCP:
1135 tcp = (struct tcp_hdr *)(raw_pkt + len);
1136 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1138 * The source and destination fields in the transmitted packet
1139 * need to be presented in a reversed order with respect
1140 * to the expected received packets.
1142 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1143 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1144 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1147 case I40E_FILTER_PCTYPE_NONF_IPV6_SCTP:
1148 sctp = (struct sctp_hdr *)(raw_pkt + len);
1149 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1151 * The source and destination fields in the transmitted packet
1152 * need to be presented in a reversed order with respect
1153 * to the expected received packets.
1155 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1156 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1157 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1160 case I40E_FILTER_PCTYPE_NONF_IPV6_OTHER:
1161 case I40E_FILTER_PCTYPE_FRAG_IPV6:
1162 payload = raw_pkt + len;
1163 set_idx = I40E_FLXPLD_L3_IDX;
1165 case I40E_FILTER_PCTYPE_L2_PAYLOAD:
1166 payload = raw_pkt + len;
1168 * ARP packet is a special case on which the payload
1169 * starts after the whole ARP header
1171 if (fdir_input->flow.l2_flow.ether_type ==
1172 rte_cpu_to_be_16(ETHER_TYPE_ARP))
1173 payload += sizeof(struct arp_hdr);
1174 set_idx = I40E_FLXPLD_L2_IDX;
1177 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1181 /* fill the flexbytes to payload */
1182 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1183 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1184 size = pf->fdir.flex_set[pit_idx].size;
1187 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1189 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1190 (void)rte_memcpy(ptr,
1191 &fdir_input->flow_ext.flexbytes[dst],
1192 size * sizeof(uint16_t));
1198 /* Construct the tx flags */
1199 static inline uint64_t
1200 i40e_build_ctob(uint32_t td_cmd,
1205 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1206 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
1207 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1208 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1209 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
1213 * check the programming status descriptor in rx queue.
1214 * done after Programming Flow Director is programmed on
1218 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1220 volatile union i40e_rx_desc *rxdp;
1227 rxdp = &rxq->rx_ring[rxq->rx_tail];
1228 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1229 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1230 >> I40E_RXD_QW1_STATUS_SHIFT;
1232 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1233 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1234 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1235 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1237 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1238 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1240 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1241 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1242 if (error == (0x1 <<
1243 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1244 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1245 " (FD_ID %u): programming status"
1247 rxdp->wb.qword0.hi_dword.fd_id);
1249 } else if (error == (0x1 <<
1250 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1251 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1252 " (FD_ID %u): programming status"
1254 rxdp->wb.qword0.hi_dword.fd_id);
1257 PMD_DRV_LOG(ERR, "invalid programming status"
1258 " reported, error = %u.", error);
1260 PMD_DRV_LOG(ERR, "unknown programming status"
1261 " reported, len = %d, id = %u.", len, id);
1262 rxdp->wb.qword1.status_error_len = 0;
1264 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1271 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1272 struct i40e_fdir_filter *filter)
1274 rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1278 /* Check if there exists the flow director filter */
1279 static struct i40e_fdir_filter *
1280 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1281 const struct i40e_fdir_input *input)
1285 ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1289 return fdir_info->hash_map[ret];
1292 /* Add a flow director filter into the SW list */
1294 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1296 struct i40e_fdir_info *fdir_info = &pf->fdir;
1299 ret = rte_hash_add_key(fdir_info->hash_table,
1300 &filter->fdir.input);
1303 "Failed to insert fdir filter to hash table %d!",
1307 fdir_info->hash_map[ret] = filter;
1309 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1314 /* Delete a flow director filter from the SW list */
1316 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1318 struct i40e_fdir_info *fdir_info = &pf->fdir;
1319 struct i40e_fdir_filter *filter;
1322 ret = rte_hash_del_key(fdir_info->hash_table, input);
1325 "Failed to delete fdir filter to hash table %d!",
1329 filter = fdir_info->hash_map[ret];
1330 fdir_info->hash_map[ret] = NULL;
1332 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1339 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1340 * @pf: board private structure
1341 * @filter: fdir filter entry
1342 * @add: 0 - delete, 1 - add
1345 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1346 const struct rte_eth_fdir_filter *filter,
1349 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1351 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1352 enum i40e_filter_pctype pctype;
1355 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1356 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1357 " check the mode in fdir_conf.");
1361 pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1362 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1363 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1366 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1367 PMD_DRV_LOG(ERR, "Invalid queue ID");
1370 if (filter->input.flow_ext.is_vf &&
1371 filter->input.flow_ext.dst_id >= pf->vf_num) {
1372 PMD_DRV_LOG(ERR, "Invalid VF ID");
1376 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1378 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1380 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1384 if (hw->mac.type == I40E_MAC_X722) {
1385 /* get translated pctype value in fd pctype register */
1386 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1387 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1390 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1392 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1401 * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1402 * @pf: board private structure
1403 * @filter: fdir filter entry
1404 * @add: 0 - delete, 1 - add
1407 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1408 const struct i40e_fdir_filter_conf *filter,
1411 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1413 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1414 enum i40e_filter_pctype pctype;
1415 struct i40e_fdir_info *fdir_info = &pf->fdir;
1416 struct i40e_fdir_filter *fdir_filter, *node;
1417 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1420 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1421 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1425 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1426 PMD_DRV_LOG(ERR, "Invalid queue ID");
1429 if (filter->input.flow_ext.is_vf &&
1430 filter->input.flow_ext.dst_id >= pf->vf_num) {
1431 PMD_DRV_LOG(ERR, "Invalid VF ID");
1435 /* Check if there is the filter in SW list */
1436 memset(&check_filter, 0, sizeof(check_filter));
1437 i40e_fdir_filter_convert(filter, &check_filter);
1438 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1441 "Conflict with existing flow director rules!");
1445 if (!add && !node) {
1447 "There's no corresponding flow firector filter!");
1451 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1453 ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1455 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1459 if (hw->mac.type == I40E_MAC_X722) {
1460 /* get translated pctype value in fd pctype register */
1461 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1462 hw, I40E_GLQF_FD_PCTYPES(
1463 (int)filter->input.pctype));
1465 pctype = filter->input.pctype;
1467 ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1469 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1475 fdir_filter = rte_zmalloc("fdir_filter",
1476 sizeof(*fdir_filter), 0);
1477 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1478 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1480 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1487 * i40e_fdir_filter_programming - Program a flow director filter rule.
1488 * Is done by Flow Director Programming Descriptor followed by packet
1489 * structure that contains the filter fields need to match.
1490 * @pf: board private structure
1492 * @filter: fdir filter entry
1493 * @add: 0 - delete, 1 - add
1496 i40e_fdir_filter_programming(struct i40e_pf *pf,
1497 enum i40e_filter_pctype pctype,
1498 const struct rte_eth_fdir_filter *filter,
1501 struct i40e_tx_queue *txq = pf->fdir.txq;
1502 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1503 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1504 volatile struct i40e_tx_desc *txdp;
1505 volatile struct i40e_filter_program_desc *fdirdp;
1510 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1511 fdirdp = (volatile struct i40e_filter_program_desc *)
1512 (&(txq->tx_ring[txq->tx_tail]));
1514 fdirdp->qindex_flex_ptype_vsi =
1515 rte_cpu_to_le_32((fdir_action->rx_queue <<
1516 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1517 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1519 fdirdp->qindex_flex_ptype_vsi |=
1520 rte_cpu_to_le_32((fdir_action->flex_off <<
1521 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1522 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1524 fdirdp->qindex_flex_ptype_vsi |=
1525 rte_cpu_to_le_32((pctype <<
1526 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1527 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1529 if (filter->input.flow_ext.is_vf)
1530 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1532 /* Use LAN VSI Id by default */
1533 vsi_id = pf->main_vsi->vsi_id;
1534 fdirdp->qindex_flex_ptype_vsi |=
1535 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1536 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1537 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1539 fdirdp->dtype_cmd_cntindex =
1540 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1543 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1544 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1545 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1547 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1548 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1549 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1551 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1552 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1553 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1554 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1555 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1556 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1558 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1559 " unsupported fdir behavior.");
1563 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1564 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1565 I40E_TXD_FLTR_QW1_DEST_MASK);
1567 fdirdp->dtype_cmd_cntindex |=
1568 rte_cpu_to_le_32((fdir_action->report_status<<
1569 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1570 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1572 fdirdp->dtype_cmd_cntindex |=
1573 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1574 fdirdp->dtype_cmd_cntindex |=
1576 ((uint32_t)pf->fdir.match_counter_index <<
1577 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1578 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1580 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1582 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1583 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1584 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1585 td_cmd = I40E_TX_DESC_CMD_EOP |
1586 I40E_TX_DESC_CMD_RS |
1587 I40E_TX_DESC_CMD_DUMMY;
1589 txdp->cmd_type_offset_bsz =
1590 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1592 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1593 if (txq->tx_tail >= txq->nb_tx_desc)
1595 /* Update the tx tail register */
1597 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1598 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1599 if ((txdp->cmd_type_offset_bsz &
1600 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1601 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1605 if (i >= I40E_FDIR_MAX_WAIT_US) {
1606 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1607 " time out to get DD on tx queue.");
1610 /* totally delay 10 ms to check programming status*/
1611 for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1612 if (i40e_check_fdir_programming_status(rxq) >= 0)
1617 "Failed to program FDIR filter: programming status reported.");
1622 * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1623 * Is done by Flow Director Programming Descriptor followed by packet
1624 * structure that contains the filter fields need to match.
1625 * @pf: board private structure
1627 * @filter: fdir filter entry
1628 * @add: 0 - delete, 1 - add
1631 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1632 enum i40e_filter_pctype pctype,
1633 const struct i40e_fdir_filter_conf *filter,
1636 struct i40e_tx_queue *txq = pf->fdir.txq;
1637 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1638 const struct i40e_fdir_action *fdir_action = &filter->action;
1639 volatile struct i40e_tx_desc *txdp;
1640 volatile struct i40e_filter_program_desc *fdirdp;
1645 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1646 fdirdp = (volatile struct i40e_filter_program_desc *)
1647 (&txq->tx_ring[txq->tx_tail]);
1649 fdirdp->qindex_flex_ptype_vsi =
1650 rte_cpu_to_le_32((fdir_action->rx_queue <<
1651 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1652 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1654 fdirdp->qindex_flex_ptype_vsi |=
1655 rte_cpu_to_le_32((fdir_action->flex_off <<
1656 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1657 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1659 fdirdp->qindex_flex_ptype_vsi |=
1660 rte_cpu_to_le_32((pctype <<
1661 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1662 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1664 if (filter->input.flow_ext.is_vf)
1665 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1667 /* Use LAN VSI Id by default */
1668 vsi_id = pf->main_vsi->vsi_id;
1669 fdirdp->qindex_flex_ptype_vsi |=
1670 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1671 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1672 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1674 fdirdp->dtype_cmd_cntindex =
1675 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1678 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1679 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1680 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1682 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1683 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1684 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1686 if (fdir_action->behavior == I40E_FDIR_REJECT)
1687 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1688 else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1689 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1690 else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1691 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1693 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1697 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1698 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1699 I40E_TXD_FLTR_QW1_DEST_MASK);
1701 fdirdp->dtype_cmd_cntindex |=
1702 rte_cpu_to_le_32((fdir_action->report_status <<
1703 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1704 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1706 fdirdp->dtype_cmd_cntindex |=
1707 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1708 fdirdp->dtype_cmd_cntindex |=
1710 ((uint32_t)pf->fdir.match_counter_index <<
1711 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1712 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1714 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1716 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1717 txdp = &txq->tx_ring[txq->tx_tail + 1];
1718 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1719 td_cmd = I40E_TX_DESC_CMD_EOP |
1720 I40E_TX_DESC_CMD_RS |
1721 I40E_TX_DESC_CMD_DUMMY;
1723 txdp->cmd_type_offset_bsz =
1724 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1726 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1727 if (txq->tx_tail >= txq->nb_tx_desc)
1729 /* Update the tx tail register */
1731 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1732 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1733 if ((txdp->cmd_type_offset_bsz &
1734 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1735 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1739 if (i >= I40E_FDIR_MAX_WAIT_US) {
1741 "Failed to program FDIR filter: time out to get DD on tx queue.");
1744 /* totally delay 10 ms to check programming status*/
1745 rte_delay_us(I40E_FDIR_MAX_WAIT_US);
1746 if (i40e_check_fdir_programming_status(rxq) < 0) {
1748 "Failed to program FDIR filter: programming status reported.");
1756 * i40e_fdir_flush - clear all filters of Flow Director table
1757 * @pf: board private structure
1760 i40e_fdir_flush(struct rte_eth_dev *dev)
1762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1763 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1765 uint16_t guarant_cnt, best_cnt;
1768 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1769 I40E_WRITE_FLUSH(hw);
1771 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1772 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1773 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1774 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1777 if (i >= I40E_FDIR_FLUSH_RETRY) {
1778 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1781 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1782 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1783 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1784 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1785 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1786 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1787 if (guarant_cnt != 0 || best_cnt != 0) {
1788 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1791 PMD_DRV_LOG(INFO, "FD table Flush success.");
1796 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1797 struct rte_eth_flex_payload_cfg *flex_set,
1800 struct i40e_fdir_flex_pit *flex_pit;
1801 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1802 uint16_t src, dst, size, j, k;
1803 uint8_t i, layer_idx;
1805 for (layer_idx = I40E_FLXPLD_L2_IDX;
1806 layer_idx <= I40E_FLXPLD_L4_IDX;
1808 if (layer_idx == I40E_FLXPLD_L2_IDX)
1809 ptr->type = RTE_ETH_L2_PAYLOAD;
1810 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1811 ptr->type = RTE_ETH_L3_PAYLOAD;
1812 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1813 ptr->type = RTE_ETH_L4_PAYLOAD;
1815 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1816 flex_pit = &pf->fdir.flex_set[layer_idx *
1817 I40E_MAX_FLXPLD_FIED + i];
1818 if (flex_pit->size == 0)
1820 src = flex_pit->src_offset * sizeof(uint16_t);
1821 dst = flex_pit->dst_offset * sizeof(uint16_t);
1822 size = flex_pit->size * sizeof(uint16_t);
1823 for (j = src, k = dst; j < src + size; j++, k++)
1824 ptr->src_offset[k] = j;
1832 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1833 struct rte_eth_fdir_flex_mask *flex_mask,
1836 struct i40e_fdir_flex_mask *mask;
1837 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1840 uint16_t off_bytes, mask_tmp;
1842 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1843 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1845 mask = &pf->fdir.flex_mask[i];
1846 flow_type = i40e_pctype_to_flowtype(pf->adapter,
1847 (enum i40e_filter_pctype)i);
1848 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
1851 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1852 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1853 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1854 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1856 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1857 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1860 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1861 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1862 mask_tmp = ~mask->bitmask[j].mask;
1863 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1864 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1866 ptr->flow_type = flow_type;
1873 * i40e_fdir_info_get - get information of Flow Director
1874 * @pf: ethernet device to get info from
1875 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1876 * the flow director information.
1879 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1882 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1883 uint16_t num_flex_set = 0;
1884 uint16_t num_flex_mask = 0;
1886 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1887 fdir->mode = RTE_FDIR_MODE_PERFECT;
1889 fdir->mode = RTE_FDIR_MODE_NONE;
1892 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1894 (uint32_t)hw->func_caps.fd_filters_best_effort;
1895 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1896 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1897 fdir->flex_payload_unit = sizeof(uint16_t);
1898 fdir->flex_bitmask_unit = sizeof(uint16_t);
1899 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1900 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1901 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1903 i40e_fdir_info_get_flex_set(pf,
1904 fdir->flex_conf.flex_set,
1906 i40e_fdir_info_get_flex_mask(pf,
1907 fdir->flex_conf.flex_mask,
1910 fdir->flex_conf.nb_payloads = num_flex_set;
1911 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1915 * i40e_fdir_stat_get - get statistics of Flow Director
1916 * @pf: ethernet device to get info from
1917 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1918 * the flow director statistics.
1921 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1923 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1924 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1927 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1929 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1930 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1932 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1933 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1937 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1938 struct rte_eth_fdir_filter_info *info)
1940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1944 PMD_DRV_LOG(ERR, "Invalid pointer");
1948 switch (info->info_type) {
1949 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1950 ret = i40e_fdir_filter_inset_select(pf,
1951 &(info->info.input_set_conf));
1954 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1963 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1964 * @pf: board private structure
1965 * @filter_op:operation will be taken.
1966 * @arg: a pointer to specific structure corresponding to the filter_op
1969 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1970 enum rte_filter_op filter_op,
1973 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1976 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1979 if (filter_op == RTE_ETH_FILTER_NOP)
1982 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1985 switch (filter_op) {
1986 case RTE_ETH_FILTER_ADD:
1987 ret = i40e_add_del_fdir_filter(dev,
1988 (struct rte_eth_fdir_filter *)arg,
1991 case RTE_ETH_FILTER_DELETE:
1992 ret = i40e_add_del_fdir_filter(dev,
1993 (struct rte_eth_fdir_filter *)arg,
1996 case RTE_ETH_FILTER_FLUSH:
1997 ret = i40e_fdir_flush(dev);
1999 case RTE_ETH_FILTER_INFO:
2000 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2002 case RTE_ETH_FILTER_SET:
2003 ret = i40e_fdir_filter_set(dev,
2004 (struct rte_eth_fdir_filter_info *)arg);
2006 case RTE_ETH_FILTER_STATS:
2007 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2010 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2017 /* Restore flow director filter */
2019 i40e_fdir_filter_restore(struct i40e_pf *pf)
2021 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2022 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2023 struct i40e_fdir_filter *f;
2024 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2026 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
2027 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
2029 TAILQ_FOREACH(f, fdir_list, rules)
2030 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2032 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2034 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2035 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2037 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2038 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2040 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
2041 guarant_cnt, best_cnt);