1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
16 #include <rte_memzone.h>
17 #include <rte_malloc.h>
23 #include <rte_hash_crc.h>
24 #include <rte_bitmap.h>
26 #include "i40e_logs.h"
27 #include "base/i40e_type.h"
28 #include "base/i40e_prototype.h"
29 #include "i40e_ethdev.h"
30 #include "i40e_rxtx.h"
32 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
34 #define IPV6_ADDR_LEN 16
38 #define IPPROTO_L2TP 115
41 #define I40E_FDIR_PKT_LEN 512
42 #define I40E_FDIR_IP_DEFAULT_LEN 420
43 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
44 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
45 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
46 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
48 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
49 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
50 #define I40E_FDIR_UDP_DEFAULT_LEN 400
51 #define I40E_FDIR_GTP_DEFAULT_LEN 384
52 #define I40E_FDIR_INNER_IP_DEFAULT_LEN 384
53 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN 344
55 #define I40E_FDIR_GTPC_DST_PORT 2123
56 #define I40E_FDIR_GTPU_DST_PORT 2152
57 #define I40E_FDIR_GTP_VER_FLAG_0X30 0x30
58 #define I40E_FDIR_GTP_VER_FLAG_0X32 0x32
59 #define I40E_FDIR_GTP_MSG_TYPE_0X01 0x01
60 #define I40E_FDIR_GTP_MSG_TYPE_0XFF 0xFF
62 #define I40E_FDIR_ESP_DST_PORT 4500
64 /* Wait time for fdir filter programming */
65 #define I40E_FDIR_MAX_WAIT_US 10000
67 /* Wait count and interval for fdir filter flush */
68 #define I40E_FDIR_FLUSH_RETRY 50
69 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
71 #define I40E_COUNTER_PF 2
72 /* Statistic counter index for one pf */
73 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
75 #define I40E_FDIR_FLOWS ( \
76 (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
77 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
78 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
79 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
80 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
81 (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
82 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
83 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
84 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
85 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
86 (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
88 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
89 enum i40e_filter_pctype pctype,
90 const struct rte_eth_fdir_filter *filter,
92 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
93 struct i40e_fdir_filter *filter);
94 static struct i40e_fdir_filter *
95 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
96 const struct i40e_fdir_input *input);
97 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
98 struct i40e_fdir_filter *filter);
100 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
101 enum i40e_filter_pctype pctype,
102 const struct i40e_fdir_filter_conf *filter,
103 bool add, bool wait_status);
106 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
108 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
109 struct i40e_hmc_obj_rxq rx_ctx;
110 int err = I40E_SUCCESS;
112 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
113 /* Init the RX queue in hardware */
114 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
116 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
117 rx_ctx.qlen = rxq->nb_rx_desc;
118 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
121 rx_ctx.dtype = i40e_header_split_none;
122 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
123 rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
124 rx_ctx.tphrdesc_ena = 1;
125 rx_ctx.tphwdesc_ena = 1;
126 rx_ctx.tphdata_ena = 1;
127 rx_ctx.tphhead_ena = 1;
128 rx_ctx.lrxqthresh = 2;
134 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
135 if (err != I40E_SUCCESS) {
136 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
139 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
140 if (err != I40E_SUCCESS) {
141 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
144 rxq->qrx_tail = hw->hw_addr +
145 I40E_QRX_TAIL(rxq->vsi->base_queue);
148 /* Init the RX tail regieter. */
149 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
155 * i40e_fdir_setup - reserve and initialize the Flow Director resources
156 * @pf: board private structure
159 i40e_fdir_setup(struct i40e_pf *pf)
161 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
162 struct i40e_vsi *vsi;
163 int err = I40E_SUCCESS;
164 char z_name[RTE_MEMZONE_NAMESIZE];
165 const struct rte_memzone *mz = NULL;
166 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
169 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
170 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
171 return I40E_NOT_SUPPORTED;
174 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
175 " num_filters_best_effort = %u.",
176 hw->func_caps.fd_filters_guaranteed,
177 hw->func_caps.fd_filters_best_effort);
179 vsi = pf->fdir.fdir_vsi;
181 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
185 /* make new FDIR VSI */
186 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
188 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
189 return I40E_ERR_NO_AVAILABLE_VSI;
191 pf->fdir.fdir_vsi = vsi;
193 /*Fdir tx queue setup*/
194 err = i40e_fdir_setup_tx_resources(pf);
196 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
200 /*Fdir rx queue setup*/
201 err = i40e_fdir_setup_rx_resources(pf);
203 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
207 err = i40e_tx_queue_init(pf->fdir.txq);
209 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
213 /* need switch on before dev start*/
214 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
216 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
220 /* Init the rx queue in hardware */
221 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
223 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
227 /* switch on rx queue */
228 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
230 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
234 /* reserve memory for the fdir programming packet */
235 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
236 eth_dev->device->driver->name,
238 eth_dev->data->port_id);
239 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN *
240 I40E_FDIR_PRG_PKT_CNT, SOCKET_ID_ANY);
242 PMD_DRV_LOG(ERR, "Cannot init memzone for "
243 "flow director program packet.");
244 err = I40E_ERR_NO_MEMORY;
248 for (i = 0; i < I40E_FDIR_PRG_PKT_CNT; i++) {
249 pf->fdir.prg_pkt[i] = (uint8_t *)mz->addr +
250 I40E_FDIR_PKT_LEN * i;
251 pf->fdir.dma_addr[i] = mz->iova +
252 I40E_FDIR_PKT_LEN * i;
255 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
256 pf->fdir.fdir_actual_cnt = 0;
257 pf->fdir.fdir_guarantee_free_space =
258 pf->fdir.fdir_guarantee_total_space;
260 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
265 i40e_dev_rx_queue_release(pf->fdir.rxq);
268 i40e_dev_tx_queue_release(pf->fdir.txq);
271 i40e_vsi_release(vsi);
272 pf->fdir.fdir_vsi = NULL;
277 * i40e_fdir_teardown - release the Flow Director resources
278 * @pf: board private structure
281 i40e_fdir_teardown(struct i40e_pf *pf)
283 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
284 struct i40e_vsi *vsi;
285 struct rte_eth_dev *dev = pf->adapter->eth_dev;
287 vsi = pf->fdir.fdir_vsi;
290 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
292 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
293 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
295 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
296 i40e_dev_rx_queue_release(pf->fdir.rxq);
297 rte_eth_dma_zone_free(dev, "fdir_rx_ring", pf->fdir.rxq->queue_id);
299 i40e_dev_tx_queue_release(pf->fdir.txq);
300 rte_eth_dma_zone_free(dev, "fdir_tx_ring", pf->fdir.txq->queue_id);
302 i40e_vsi_release(vsi);
303 pf->fdir.fdir_vsi = NULL;
306 /* check whether the flow director table in empty */
308 i40e_fdir_empty(struct i40e_hw *hw)
310 uint32_t guarant_cnt, best_cnt;
312 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
313 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
314 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
315 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
316 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
317 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
318 if (best_cnt + guarant_cnt > 0)
325 * Initialize the configuration about bytes stream extracted as flexible payload
329 i40e_init_flx_pld(struct i40e_pf *pf)
331 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
337 * Define the bytes stream extracted as flexible payload in
338 * field vector. By default, select 8 words from the beginning
339 * of payload as flexible payload.
341 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
342 index = i * I40E_MAX_FLXPLD_FIED;
343 pf->fdir.flex_set[index].src_offset = 0;
344 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
345 pf->fdir.flex_set[index].dst_offset = 0;
346 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
348 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
350 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
353 /* initialize the masks */
354 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
355 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
356 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
358 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
360 pf->fdir.flex_mask[pctype].word_mask = 0;
361 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
362 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
363 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
364 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
365 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
370 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
371 if ((flex_pit2).src_offset < \
372 (flex_pit1).src_offset + (flex_pit1).size) { \
373 PMD_DRV_LOG(ERR, "src_offset should be not" \
374 " less than than previous offset" \
375 " + previous FSIZE."); \
381 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
382 * and the flex_pit will be sorted by it's src_offset value
384 static inline uint16_t
385 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
386 struct i40e_fdir_flex_pit *flex_pit)
388 uint16_t src_tmp, size, num = 0;
389 uint16_t i, k, j = 0;
391 while (j < I40E_FDIR_MAX_FLEX_LEN) {
393 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
394 if (src_offset[j + 1] == src_offset[j] + 1)
399 src_tmp = src_offset[j] + 1 - size;
400 /* the flex_pit need to be sort by src_offset */
401 for (i = 0; i < num; i++) {
402 if (src_tmp < flex_pit[i].src_offset)
405 /* if insert required, move backward */
406 for (k = num; k > i; k--)
407 flex_pit[k] = flex_pit[k - 1];
409 flex_pit[i].dst_offset = j + 1 - size;
410 flex_pit[i].src_offset = src_tmp;
411 flex_pit[i].size = size;
418 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
420 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
422 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
425 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
426 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
427 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
432 memset(flex_pit, 0, sizeof(flex_pit));
433 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
434 if (num > I40E_MAX_FLXPLD_FIED) {
435 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
438 for (i = 0; i < num; i++) {
439 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
440 flex_pit[i].src_offset & 0x01) {
441 PMD_DRV_LOG(ERR, "flexpayload should be measured"
446 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
452 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
453 * arguments are valid
456 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
457 const struct rte_eth_fdir_flex_conf *conf)
459 const struct rte_eth_flex_payload_cfg *flex_cfg;
460 const struct rte_eth_fdir_flex_mask *flex_mask;
465 enum i40e_filter_pctype pctype;
468 PMD_DRV_LOG(INFO, "NULL pointer.");
471 /* check flexible payload setting configuration */
472 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
473 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
476 for (i = 0; i < conf->nb_payloads; i++) {
477 flex_cfg = &conf->flex_set[i];
478 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
479 PMD_DRV_LOG(ERR, "invalid payload type.");
482 ret = i40e_check_fdir_flex_payload(flex_cfg);
484 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
489 /* check flex mask setting configuration */
490 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
491 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
494 for (i = 0; i < conf->nb_flexmasks; i++) {
495 flex_mask = &conf->flex_mask[i];
496 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
497 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
498 PMD_DRV_LOG(WARNING, "invalid flow type.");
502 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
503 mask_tmp = I40E_WORD(flex_mask->mask[j],
504 flex_mask->mask[j + 1]);
505 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
507 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
508 PMD_DRV_LOG(ERR, " exceed maximal"
509 " number of bitmasks.");
519 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
520 * @pf: board private structure
521 * @cfg: the rule how bytes stream is extracted as flexible payload
524 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
525 const struct rte_eth_flex_payload_cfg *cfg)
527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
528 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
529 uint32_t flx_pit, flx_ort;
530 uint16_t num, min_next_off; /* in words */
531 uint8_t field_idx = 0;
532 uint8_t layer_idx = 0;
535 if (cfg->type == RTE_ETH_L2_PAYLOAD)
536 layer_idx = I40E_FLXPLD_L2_IDX;
537 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
538 layer_idx = I40E_FLXPLD_L3_IDX;
539 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
540 layer_idx = I40E_FLXPLD_L4_IDX;
542 memset(flex_pit, 0, sizeof(flex_pit));
543 num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
547 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
548 (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
549 (layer_idx * I40E_MAX_FLXPLD_FIED);
550 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
553 for (i = 0; i < num; i++) {
554 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
555 /* record the info in fdir structure */
556 pf->fdir.flex_set[field_idx].src_offset =
557 flex_pit[i].src_offset / sizeof(uint16_t);
558 pf->fdir.flex_set[field_idx].size =
559 flex_pit[i].size / sizeof(uint16_t);
560 pf->fdir.flex_set[field_idx].dst_offset =
561 flex_pit[i].dst_offset / sizeof(uint16_t);
562 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
563 pf->fdir.flex_set[field_idx].size,
564 pf->fdir.flex_set[field_idx].dst_offset);
566 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
568 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
569 pf->fdir.flex_set[field_idx].size;
571 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
572 /* set the non-used register obeying register's constrain */
573 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
574 NONUSE_FLX_PIT_DEST_OFF);
576 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
583 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
584 * @pf: board private structure
585 * @pctype: packet classify type
586 * @flex_masks: mask for flexible payload
589 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
590 enum i40e_filter_pctype pctype,
591 const struct rte_eth_fdir_flex_mask *mask_cfg)
593 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
594 struct i40e_fdir_flex_mask *flex_mask;
595 uint32_t flxinset, fd_mask;
597 uint8_t i, nb_bitmask = 0;
599 flex_mask = &pf->fdir.flex_mask[pctype];
600 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
601 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
602 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
603 if (mask_tmp != 0x0) {
604 flex_mask->word_mask |=
605 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
606 if (mask_tmp != UINT16_MAX) {
608 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
609 flex_mask->bitmask[nb_bitmask].offset =
610 i / sizeof(uint16_t);
615 /* write mask to hw */
616 flxinset = (flex_mask->word_mask <<
617 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
618 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
619 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
621 for (i = 0; i < nb_bitmask; i++) {
622 fd_mask = (flex_mask->bitmask[i].mask <<
623 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
624 I40E_PRTQF_FD_MSK_MASK_MASK;
625 fd_mask |= ((flex_mask->bitmask[i].offset +
626 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
627 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
628 I40E_PRTQF_FD_MSK_OFFSET_MASK;
629 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
634 * Enable/disable flow director RX processing in vector routines.
637 i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on)
641 for (i = 0; i < dev->data->nb_rx_queues; i++) {
642 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
645 rxq->fdir_enabled = on;
647 PMD_DRV_LOG(DEBUG, "Flow Director processing on RX set to %d", on);
651 * Configure flow director related setting
654 i40e_fdir_configure(struct rte_eth_dev *dev)
656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
658 struct rte_eth_fdir_flex_conf *conf;
659 enum i40e_filter_pctype pctype;
665 * configuration need to be done before
666 * flow director filters are added
667 * If filters exist, flush them.
669 if (i40e_fdir_empty(hw) < 0) {
670 ret = i40e_fdir_flush(dev);
672 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
677 /* enable FDIR filter */
678 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
679 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
680 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
682 i40e_init_flx_pld(pf); /* set flex config to default value */
684 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
685 ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
687 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
691 if (!pf->support_multi_driver) {
692 /* configure flex payload */
693 for (i = 0; i < conf->nb_payloads; i++)
694 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
695 /* configure flex mask*/
696 for (i = 0; i < conf->nb_flexmasks; i++) {
697 if (hw->mac.type == I40E_MAC_X722) {
698 /* get pctype value in fd pctype register */
699 pctype = (enum i40e_filter_pctype)
701 I40E_GLQF_FD_PCTYPES(
702 (int)i40e_flowtype_to_pctype(
704 conf->flex_mask[i].flow_type)));
706 pctype = i40e_flowtype_to_pctype(pf->adapter,
707 conf->flex_mask[i].flow_type);
710 i40e_set_flex_mask_on_pctype(pf, pctype,
711 &conf->flex_mask[i]);
714 PMD_DRV_LOG(ERR, "Not support flexible payload.");
717 /* Enable FDIR processing in RX routines */
718 i40e_fdir_rx_proc_enable(dev, 1);
724 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
725 unsigned char *raw_pkt,
728 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
729 uint16_t *ether_type;
730 uint8_t len = 2 * sizeof(struct rte_ether_addr);
731 struct rte_ipv4_hdr *ip;
732 struct rte_ipv6_hdr *ip6;
733 static const uint8_t next_proto[] = {
734 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
735 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
736 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
737 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
738 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
739 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
740 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
741 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
742 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
743 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
746 raw_pkt += 2 * sizeof(struct rte_ether_addr);
747 if (vlan && fdir_input->flow_ext.vlan_tci) {
748 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
749 rte_memcpy(raw_pkt + sizeof(uint16_t),
750 &fdir_input->flow_ext.vlan_tci,
752 raw_pkt += sizeof(vlan_frame);
753 len += sizeof(vlan_frame);
755 ether_type = (uint16_t *)raw_pkt;
756 raw_pkt += sizeof(uint16_t);
757 len += sizeof(uint16_t);
759 switch (fdir_input->flow_type) {
760 case RTE_ETH_FLOW_L2_PAYLOAD:
761 *ether_type = fdir_input->flow.l2_flow.ether_type;
763 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
764 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
765 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
766 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
767 case RTE_ETH_FLOW_FRAG_IPV4:
768 ip = (struct rte_ipv4_hdr *)raw_pkt;
770 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
771 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
772 /* set len to by default */
773 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
774 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
775 fdir_input->flow.ip4_flow.proto :
776 next_proto[fdir_input->flow_type];
777 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
778 fdir_input->flow.ip4_flow.ttl :
779 I40E_FDIR_IP_DEFAULT_TTL;
780 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
782 * The source and destination fields in the transmitted packet
783 * need to be presented in a reversed order with respect
784 * to the expected received packets.
786 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
787 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
788 len += sizeof(struct rte_ipv4_hdr);
790 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
791 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
792 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
793 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
794 case RTE_ETH_FLOW_FRAG_IPV6:
795 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
797 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
799 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
800 (fdir_input->flow.ipv6_flow.tc <<
801 I40E_FDIR_IPv6_TC_OFFSET));
803 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
804 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
805 fdir_input->flow.ipv6_flow.proto :
806 next_proto[fdir_input->flow_type];
807 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
808 fdir_input->flow.ipv6_flow.hop_limits :
809 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
811 * The source and destination fields in the transmitted packet
812 * need to be presented in a reversed order with respect
813 * to the expected received packets.
815 rte_memcpy(&(ip6->src_addr),
816 &(fdir_input->flow.ipv6_flow.dst_ip),
818 rte_memcpy(&(ip6->dst_addr),
819 &(fdir_input->flow.ipv6_flow.src_ip),
821 len += sizeof(struct rte_ipv6_hdr);
824 PMD_DRV_LOG(ERR, "unknown flow type %u.",
825 fdir_input->flow_type);
833 * i40e_fdir_construct_pkt - construct packet based on fields in input
834 * @pf: board private structure
835 * @fdir_input: input set of the flow director entry
836 * @raw_pkt: a packet to be constructed
839 i40e_fdir_construct_pkt(struct i40e_pf *pf,
840 const struct rte_eth_fdir_input *fdir_input,
841 unsigned char *raw_pkt)
843 unsigned char *payload, *ptr;
844 struct rte_udp_hdr *udp;
845 struct rte_tcp_hdr *tcp;
846 struct rte_sctp_hdr *sctp;
847 uint8_t size, dst = 0;
848 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
851 /* fill the ethernet and IP head */
852 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
853 !!fdir_input->flow_ext.vlan_tci);
857 /* fill the L4 head */
858 switch (fdir_input->flow_type) {
859 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
860 udp = (struct rte_udp_hdr *)(raw_pkt + len);
861 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
863 * The source and destination fields in the transmitted packet
864 * need to be presented in a reversed order with respect
865 * to the expected received packets.
867 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
868 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
869 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
872 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
873 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
874 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
876 * The source and destination fields in the transmitted packet
877 * need to be presented in a reversed order with respect
878 * to the expected received packets.
880 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
881 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
882 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
885 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
886 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
887 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
889 * The source and destination fields in the transmitted packet
890 * need to be presented in a reversed order with respect
891 * to the expected received packets.
893 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
894 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
895 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
898 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
899 case RTE_ETH_FLOW_FRAG_IPV4:
900 payload = raw_pkt + len;
901 set_idx = I40E_FLXPLD_L3_IDX;
904 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
905 udp = (struct rte_udp_hdr *)(raw_pkt + len);
906 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
908 * The source and destination fields in the transmitted packet
909 * need to be presented in a reversed order with respect
910 * to the expected received packets.
912 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
913 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
914 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
917 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
918 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
919 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
921 * The source and destination fields in the transmitted packet
922 * need to be presented in a reversed order with respect
923 * to the expected received packets.
925 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
926 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
927 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
930 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
931 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
932 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
934 * The source and destination fields in the transmitted packet
935 * need to be presented in a reversed order with respect
936 * to the expected received packets.
938 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
939 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
940 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
943 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
944 case RTE_ETH_FLOW_FRAG_IPV6:
945 payload = raw_pkt + len;
946 set_idx = I40E_FLXPLD_L3_IDX;
948 case RTE_ETH_FLOW_L2_PAYLOAD:
949 payload = raw_pkt + len;
951 * ARP packet is a special case on which the payload
952 * starts after the whole ARP header
954 if (fdir_input->flow.l2_flow.ether_type ==
955 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
956 payload += sizeof(struct rte_arp_hdr);
957 set_idx = I40E_FLXPLD_L2_IDX;
960 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
964 /* fill the flexbytes to payload */
965 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
966 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
967 size = pf->fdir.flex_set[pit_idx].size;
970 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
972 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
974 &fdir_input->flow_ext.flexbytes[dst],
975 size * sizeof(uint16_t));
981 static struct i40e_customized_pctype *
982 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
984 struct i40e_customized_pctype *cus_pctype;
985 enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
987 for (; i < I40E_CUSTOMIZED_MAX; i++) {
988 cus_pctype = &pf->customized_pctype[i];
989 if (pctype == cus_pctype->pctype)
996 fill_ip6_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
997 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
999 struct rte_ipv6_hdr *ip6;
1001 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
1003 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
1004 ip6->vtc_flow = rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1005 (fdir_input->flow.ipv6_flow.tc << I40E_FDIR_IPv6_TC_OFFSET));
1006 ip6->payload_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1007 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1008 fdir_input->flow.ipv6_flow.proto : next_proto;
1009 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1010 fdir_input->flow.ipv6_flow.hop_limits :
1011 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1013 * The source and destination fields in the transmitted packet
1014 * need to be presented in a reversed order with respect
1015 * to the expected received packets.
1017 rte_memcpy(&ip6->src_addr, &fdir_input->flow.ipv6_flow.dst_ip,
1019 rte_memcpy(&ip6->dst_addr, &fdir_input->flow.ipv6_flow.src_ip,
1021 len += sizeof(struct rte_ipv6_hdr);
1027 fill_ip4_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
1028 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
1030 struct rte_ipv4_hdr *ip4;
1032 ip4 = (struct rte_ipv4_hdr *)raw_pkt;
1034 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
1035 ip4->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1036 /* set len to by default */
1037 ip4->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
1038 ip4->time_to_live = fdir_input->flow.ip4_flow.ttl ?
1039 fdir_input->flow.ip4_flow.ttl :
1040 I40E_FDIR_IP_DEFAULT_TTL;
1041 ip4->type_of_service = fdir_input->flow.ip4_flow.tos;
1042 ip4->next_proto_id = fdir_input->flow.ip4_flow.proto ?
1043 fdir_input->flow.ip4_flow.proto : next_proto;
1045 * The source and destination fields in the transmitted packet
1046 * need to be presented in a reversed order with respect
1047 * to the expected received packets.
1049 ip4->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1050 ip4->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1051 len += sizeof(struct rte_ipv4_hdr);
1057 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
1058 const struct i40e_fdir_input *fdir_input,
1059 unsigned char *raw_pkt,
1062 struct i40e_customized_pctype *cus_pctype = NULL;
1063 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
1064 uint16_t *ether_type;
1065 uint8_t len = 2 * sizeof(struct rte_ether_addr);
1066 uint8_t pctype = fdir_input->pctype;
1067 bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
1068 static const uint8_t next_proto[] = {
1069 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
1070 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
1071 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
1072 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
1073 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
1074 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
1075 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
1076 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
1077 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
1078 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
1081 rte_memcpy(raw_pkt, &fdir_input->flow.l2_flow.dst,
1082 sizeof(struct rte_ether_addr));
1083 rte_memcpy(raw_pkt + sizeof(struct rte_ether_addr),
1084 &fdir_input->flow.l2_flow.src,
1085 sizeof(struct rte_ether_addr));
1086 raw_pkt += 2 * sizeof(struct rte_ether_addr);
1088 if (vlan && fdir_input->flow_ext.vlan_tci) {
1089 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
1090 rte_memcpy(raw_pkt + sizeof(uint16_t),
1091 &fdir_input->flow_ext.vlan_tci,
1093 raw_pkt += sizeof(vlan_frame);
1094 len += sizeof(vlan_frame);
1096 ether_type = (uint16_t *)raw_pkt;
1097 raw_pkt += sizeof(uint16_t);
1098 len += sizeof(uint16_t);
1100 if (is_customized_pctype) {
1101 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1103 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1104 fdir_input->pctype);
1109 if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1110 *ether_type = fdir_input->flow.l2_flow.ether_type;
1111 else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
1112 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
1113 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
1114 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1115 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
1116 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1117 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1118 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1119 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1120 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6 ||
1121 is_customized_pctype) {
1122 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
1123 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
1124 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
1125 pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1126 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1127 len = fill_ip4_head(fdir_input, raw_pkt,
1128 next_proto[pctype], len, ether_type);
1129 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1130 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1131 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1132 pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1133 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1134 len = fill_ip6_head(fdir_input, raw_pkt,
1135 next_proto[pctype], len,
1137 } else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1138 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1139 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1140 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1141 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
1143 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3) {
1144 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_L2TP,
1146 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1147 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_ESP,
1149 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1150 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
1152 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1153 len = fill_ip4_head(fdir_input, raw_pkt, IPPROTO_UDP,
1155 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6)
1156 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_ESP,
1158 else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP)
1159 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_UDP,
1161 else if (cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3)
1162 len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_L2TP,
1165 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1173 * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1174 * @pf: board private structure
1175 * @fdir_input: input set of the flow director entry
1176 * @raw_pkt: a packet to be constructed
1179 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1180 const struct i40e_fdir_input *fdir_input,
1181 unsigned char *raw_pkt)
1183 unsigned char *payload = NULL;
1185 struct rte_udp_hdr *udp;
1186 struct rte_tcp_hdr *tcp;
1187 struct rte_sctp_hdr *sctp;
1188 struct rte_flow_item_gtp *gtp;
1189 struct rte_ipv4_hdr *gtp_ipv4;
1190 struct rte_ipv6_hdr *gtp_ipv6;
1191 struct rte_flow_item_l2tpv3oip *l2tpv3oip;
1192 struct rte_flow_item_esp *esp;
1193 struct rte_ipv4_hdr *esp_ipv4;
1194 struct rte_ipv6_hdr *esp_ipv6;
1196 uint8_t size, dst = 0;
1197 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1199 uint8_t pctype = fdir_input->pctype;
1200 struct i40e_customized_pctype *cus_pctype;
1202 /* raw pcket template - just copy contents of the raw packet */
1203 if (fdir_input->flow_ext.pkt_template) {
1204 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
1205 fdir_input->flow.raw_flow.length);
1209 /* fill the ethernet and IP head */
1210 len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
1211 !!fdir_input->flow_ext.vlan_tci);
1215 /* fill the L4 head */
1216 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
1217 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1218 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1220 * The source and destination fields in the transmitted packet
1221 * need to be presented in a reversed order with respect
1222 * to the expected received packets.
1224 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1225 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1226 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1227 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
1228 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1229 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1231 * The source and destination fields in the transmitted packet
1232 * need to be presented in a reversed order with respect
1233 * to the expected received packets.
1235 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1236 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1237 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1238 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
1239 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1240 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1242 * The source and destination fields in the transmitted packet
1243 * need to be presented in a reversed order with respect
1244 * to the expected received packets.
1246 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1247 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1248 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1249 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1250 pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1251 payload = raw_pkt + len;
1252 set_idx = I40E_FLXPLD_L3_IDX;
1253 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1254 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1255 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1257 * The source and destination fields in the transmitted packet
1258 * need to be presented in a reversed order with respect
1259 * to the expected received packets.
1261 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1262 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1263 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1264 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1265 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1266 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1268 * The source and destination fields in the transmitted packet
1269 * need to be presented in a reversed order with respect
1270 * to the expected received packets.
1272 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1273 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1274 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1275 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1276 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1277 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1279 * The source and destination fields in the transmitted packet
1280 * need to be presented in a reversed order with respect
1281 * to the expected received packets.
1283 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1284 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1285 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1286 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1287 pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1288 payload = raw_pkt + len;
1289 set_idx = I40E_FLXPLD_L3_IDX;
1290 } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1291 payload = raw_pkt + len;
1293 * ARP packet is a special case on which the payload
1294 * starts after the whole ARP header
1296 if (fdir_input->flow.l2_flow.ether_type ==
1297 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
1298 payload += sizeof(struct rte_arp_hdr);
1299 set_idx = I40E_FLXPLD_L2_IDX;
1300 } else if (fdir_input->flow_ext.customized_pctype) {
1301 /* If customized pctype is used */
1302 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1303 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1304 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1305 cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1306 cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1307 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1309 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1311 gtp = (struct rte_flow_item_gtp *)
1312 ((unsigned char *)udp +
1313 sizeof(struct rte_udp_hdr));
1315 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1316 gtp->teid = fdir_input->flow.gtp_flow.teid;
1317 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1319 /* GTP-C message type is not supported. */
1320 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1322 rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1323 gtp->v_pt_rsv_flags =
1324 I40E_FDIR_GTP_VER_FLAG_0X32;
1327 rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1328 gtp->v_pt_rsv_flags =
1329 I40E_FDIR_GTP_VER_FLAG_0X30;
1332 if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1333 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1334 gtp_ipv4 = (struct rte_ipv4_hdr *)
1335 ((unsigned char *)gtp +
1336 sizeof(struct rte_flow_item_gtp));
1337 gtp_ipv4->version_ihl =
1338 I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1339 gtp_ipv4->next_proto_id = IPPROTO_IP;
1340 gtp_ipv4->total_length =
1342 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1343 payload = (unsigned char *)gtp_ipv4 +
1344 sizeof(struct rte_ipv4_hdr);
1345 } else if (cus_pctype->index ==
1346 I40E_CUSTOMIZED_GTPU_IPV6) {
1347 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1348 gtp_ipv6 = (struct rte_ipv6_hdr *)
1349 ((unsigned char *)gtp +
1350 sizeof(struct rte_flow_item_gtp));
1351 gtp_ipv6->vtc_flow =
1353 I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1354 (0 << I40E_FDIR_IPv6_TC_OFFSET));
1355 gtp_ipv6->proto = IPPROTO_NONE;
1356 gtp_ipv6->payload_len =
1358 I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1359 gtp_ipv6->hop_limits =
1360 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1361 payload = (unsigned char *)gtp_ipv6 +
1362 sizeof(struct rte_ipv6_hdr);
1364 payload = (unsigned char *)gtp +
1365 sizeof(struct rte_flow_item_gtp);
1366 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3 ||
1367 cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3) {
1368 l2tpv3oip = (struct rte_flow_item_l2tpv3oip *)(raw_pkt
1371 if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3)
1372 l2tpv3oip->session_id =
1373 fdir_input->flow.ip4_l2tpv3oip_flow.session_id;
1375 l2tpv3oip->session_id =
1376 fdir_input->flow.ip6_l2tpv3oip_flow.session_id;
1377 payload = (unsigned char *)l2tpv3oip +
1378 sizeof(struct rte_flow_item_l2tpv3oip);
1379 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4 ||
1380 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6 ||
1381 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP ||
1382 cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1383 if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1384 esp_ipv4 = (struct rte_ipv4_hdr *)
1386 esp = (struct rte_flow_item_esp *)esp_ipv4;
1388 fdir_input->flow.esp_ipv4_flow.spi;
1389 payload = (unsigned char *)esp +
1390 sizeof(struct rte_esp_hdr);
1391 len += sizeof(struct rte_esp_hdr);
1392 } else if (cus_pctype->index ==
1393 I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1394 esp_ipv4 = (struct rte_ipv4_hdr *)
1396 udp = (struct rte_udp_hdr *)esp_ipv4;
1397 udp->dst_port = rte_cpu_to_be_16
1398 (I40E_FDIR_ESP_DST_PORT);
1400 udp->dgram_len = rte_cpu_to_be_16
1401 (I40E_FDIR_UDP_DEFAULT_LEN);
1402 esp = (struct rte_flow_item_esp *)
1403 ((unsigned char *)esp_ipv4 +
1404 sizeof(struct rte_udp_hdr));
1406 fdir_input->flow.esp_ipv4_udp_flow.spi;
1407 payload = (unsigned char *)esp +
1408 sizeof(struct rte_esp_hdr);
1409 len += sizeof(struct rte_udp_hdr) +
1410 sizeof(struct rte_esp_hdr);
1411 } else if (cus_pctype->index ==
1412 I40E_CUSTOMIZED_ESP_IPV6) {
1413 esp_ipv6 = (struct rte_ipv6_hdr *)
1415 esp = (struct rte_flow_item_esp *)esp_ipv6;
1417 fdir_input->flow.esp_ipv6_flow.spi;
1418 payload = (unsigned char *)esp +
1419 sizeof(struct rte_esp_hdr);
1420 len += sizeof(struct rte_esp_hdr);
1421 } else if (cus_pctype->index ==
1422 I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1423 esp_ipv6 = (struct rte_ipv6_hdr *)
1425 udp = (struct rte_udp_hdr *)esp_ipv6;
1426 udp->dst_port = rte_cpu_to_be_16
1427 (I40E_FDIR_ESP_DST_PORT);
1429 udp->dgram_len = rte_cpu_to_be_16
1430 (I40E_FDIR_UDP_DEFAULT_LEN);
1431 esp = (struct rte_flow_item_esp *)
1432 ((unsigned char *)esp_ipv6 +
1433 sizeof(struct rte_udp_hdr));
1435 fdir_input->flow.esp_ipv6_udp_flow.spi;
1436 payload = (unsigned char *)esp +
1437 sizeof(struct rte_esp_hdr);
1438 len += sizeof(struct rte_udp_hdr) +
1439 sizeof(struct rte_esp_hdr);
1443 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1447 /* fill the flexbytes to payload */
1448 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1449 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1450 size = pf->fdir.flex_set[pit_idx].size;
1453 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1455 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1456 (void)rte_memcpy(ptr,
1457 &fdir_input->flow_ext.flexbytes[dst],
1458 size * sizeof(uint16_t));
1464 /* Construct the tx flags */
1465 static inline uint64_t
1466 i40e_build_ctob(uint32_t td_cmd,
1471 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1472 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
1473 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1474 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1475 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
1479 * check the programming status descriptor in rx queue.
1480 * done after Programming Flow Director is programmed on
1484 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1486 volatile union i40e_rx_desc *rxdp;
1493 rxdp = &rxq->rx_ring[rxq->rx_tail];
1494 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1495 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1496 >> I40E_RXD_QW1_STATUS_SHIFT;
1498 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1499 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1500 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1501 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1503 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1504 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1506 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1507 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1508 if (error == (0x1 <<
1509 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1510 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1511 " (FD_ID %u): programming status"
1513 rxdp->wb.qword0.hi_dword.fd_id);
1515 } else if (error == (0x1 <<
1516 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1517 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1518 " (FD_ID %u): programming status"
1520 rxdp->wb.qword0.hi_dword.fd_id);
1523 PMD_DRV_LOG(ERR, "invalid programming status"
1524 " reported, error = %u.", error);
1526 PMD_DRV_LOG(INFO, "unknown programming status"
1527 " reported, len = %d, id = %u.", len, id);
1528 rxdp->wb.qword1.status_error_len = 0;
1530 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1532 if (rxq->rx_tail == 0)
1533 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1535 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1542 i40e_fdir_programming_status_cleanup(struct i40e_rx_queue *rxq)
1544 uint16_t retry_count = 0;
1546 /* capture the previous error report(if any) from rx ring */
1547 while ((i40e_check_fdir_programming_status(rxq) < 0) &&
1548 (++retry_count < I40E_FDIR_NUM_RX_DESC))
1549 PMD_DRV_LOG(INFO, "error report captured.");
1553 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1554 struct i40e_fdir_filter *filter)
1556 rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1557 if (input->input.flow_ext.pkt_template) {
1558 filter->fdir.input.flow.raw_flow.packet = NULL;
1559 filter->fdir.input.flow.raw_flow.length =
1560 rte_hash_crc(input->input.flow.raw_flow.packet,
1561 input->input.flow.raw_flow.length,
1562 input->input.flow.raw_flow.pctype);
1567 /* Check if there exists the flow director filter */
1568 static struct i40e_fdir_filter *
1569 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1570 const struct i40e_fdir_input *input)
1574 if (input->flow_ext.pkt_template)
1575 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1576 (const void *)input,
1577 input->flow.raw_flow.length);
1579 ret = rte_hash_lookup(fdir_info->hash_table,
1580 (const void *)input);
1584 return fdir_info->hash_map[ret];
1587 /* Add a flow director filter into the SW list */
1589 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1591 struct i40e_fdir_info *fdir_info = &pf->fdir;
1592 struct i40e_fdir_filter *hash_filter;
1595 if (filter->fdir.input.flow_ext.pkt_template)
1596 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1597 &filter->fdir.input,
1598 filter->fdir.input.flow.raw_flow.length);
1600 ret = rte_hash_add_key(fdir_info->hash_table,
1601 &filter->fdir.input);
1604 "Failed to insert fdir filter to hash table %d!",
1609 if (fdir_info->hash_map[ret])
1612 hash_filter = &fdir_info->fdir_filter_array[ret];
1613 rte_memcpy(hash_filter, filter, sizeof(*filter));
1614 fdir_info->hash_map[ret] = hash_filter;
1615 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, hash_filter, rules);
1620 /* Delete a flow director filter from the SW list */
1622 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1624 struct i40e_fdir_info *fdir_info = &pf->fdir;
1625 struct i40e_fdir_filter *filter;
1628 if (input->flow_ext.pkt_template)
1629 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1631 input->flow.raw_flow.length);
1633 ret = rte_hash_del_key(fdir_info->hash_table, input);
1636 "Failed to delete fdir filter to hash table %d!",
1640 filter = fdir_info->hash_map[ret];
1641 fdir_info->hash_map[ret] = NULL;
1643 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1649 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info)
1651 struct rte_flow *flow = NULL;
1657 if (fdir_info->fdir_actual_cnt >=
1658 fdir_info->fdir_space_size) {
1659 PMD_DRV_LOG(ERR, "Fdir space full");
1663 ret = rte_bitmap_scan(fdir_info->fdir_flow_pool.bitmap, &pos,
1666 /* normally this won't happen as the fdir_actual_cnt should be
1667 * same with the number of the set bits in fdir_flow_pool,
1668 * but anyway handle this error condition here for safe
1671 PMD_DRV_LOG(ERR, "fdir_actual_cnt out of sync");
1675 i = rte_bsf64(slab);
1677 rte_bitmap_clear(fdir_info->fdir_flow_pool.bitmap, pos);
1678 flow = &fdir_info->fdir_flow_pool.pool[pos].flow;
1680 memset(flow, 0, sizeof(struct rte_flow));
1686 i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info,
1687 struct rte_flow *flow)
1689 struct i40e_fdir_entry *f;
1691 f = FLOW_TO_FLOW_BITMAP(flow);
1692 rte_bitmap_set(fdir_info->fdir_flow_pool.bitmap, f->idx);
1696 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1697 * @pf: board private structure
1698 * @filter: fdir filter entry
1699 * @add: 0 - delete, 1 - add
1702 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1703 const struct rte_eth_fdir_filter *filter,
1706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt[0];
1709 enum i40e_filter_pctype pctype;
1712 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1713 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1714 " check the mode in fdir_conf.");
1718 pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1719 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1720 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1723 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1724 PMD_DRV_LOG(ERR, "Invalid queue ID");
1727 if (filter->input.flow_ext.is_vf &&
1728 filter->input.flow_ext.dst_id >= pf->vf_num) {
1729 PMD_DRV_LOG(ERR, "Invalid VF ID");
1733 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1735 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1737 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1741 if (hw->mac.type == I40E_MAC_X722) {
1742 /* get translated pctype value in fd pctype register */
1743 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1744 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1747 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1749 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1757 static inline unsigned char *
1758 i40e_find_available_buffer(struct rte_eth_dev *dev)
1760 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1761 struct i40e_fdir_info *fdir_info = &pf->fdir;
1762 struct i40e_tx_queue *txq = pf->fdir.txq;
1764 /* no available buffer
1765 * search for more available buffers from the current
1766 * descriptor, until an unavailable one
1768 if (fdir_info->txq_available_buf_count <= 0) {
1770 volatile struct i40e_tx_desc *tmp_txdp;
1772 tmp_tail = txq->tx_tail;
1773 tmp_txdp = &txq->tx_ring[tmp_tail + 1];
1776 if ((tmp_txdp->cmd_type_offset_bsz &
1777 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1778 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1779 fdir_info->txq_available_buf_count++;
1784 if (tmp_tail >= txq->nb_tx_desc)
1786 } while (tmp_tail != txq->tx_tail);
1789 if (fdir_info->txq_available_buf_count > 0)
1790 fdir_info->txq_available_buf_count--;
1793 return (unsigned char *)fdir_info->prg_pkt[txq->tx_tail >> 1];
1797 * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1798 * @pf: board private structure
1799 * @filter: fdir filter entry
1800 * @add: 0 - delete, 1 - add
1803 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1804 const struct i40e_fdir_filter_conf *filter,
1807 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1808 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1809 unsigned char *pkt = NULL;
1810 enum i40e_filter_pctype pctype;
1811 struct i40e_fdir_info *fdir_info = &pf->fdir;
1812 struct i40e_fdir_filter *node;
1813 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1814 bool wait_status = true;
1817 if (pf->fdir.fdir_vsi == NULL) {
1818 PMD_DRV_LOG(ERR, "FDIR is not enabled");
1822 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1823 PMD_DRV_LOG(ERR, "Invalid queue ID");
1826 if (filter->input.flow_ext.is_vf &&
1827 filter->input.flow_ext.dst_id >= pf->vf_num) {
1828 PMD_DRV_LOG(ERR, "Invalid VF ID");
1831 if (filter->input.flow_ext.pkt_template) {
1832 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1833 !filter->input.flow.raw_flow.packet) {
1834 PMD_DRV_LOG(ERR, "Invalid raw packet template"
1835 " flow filter parameters!");
1838 pctype = filter->input.flow.raw_flow.pctype;
1840 pctype = filter->input.pctype;
1843 /* Check if there is the filter in SW list */
1844 memset(&check_filter, 0, sizeof(check_filter));
1845 i40e_fdir_filter_convert(filter, &check_filter);
1848 ret = i40e_sw_fdir_filter_insert(pf, &check_filter);
1851 "Conflict with existing flow director rules!");
1855 if (fdir_info->fdir_invalprio == 1 &&
1856 fdir_info->fdir_guarantee_free_space > 0)
1857 wait_status = false;
1859 node = i40e_sw_fdir_filter_lookup(fdir_info,
1860 &check_filter.fdir.input);
1863 "There's no corresponding flow firector filter!");
1867 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1870 "Error deleting fdir rule from hash table!");
1874 if (fdir_info->fdir_invalprio == 1)
1875 wait_status = false;
1878 /* find a buffer to store the pkt */
1879 pkt = i40e_find_available_buffer(dev);
1883 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1884 ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1886 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1890 if (hw->mac.type == I40E_MAC_X722) {
1891 /* get translated pctype value in fd pctype register */
1892 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1893 hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1896 ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add,
1899 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1905 fdir_info->fdir_actual_cnt++;
1906 if (fdir_info->fdir_invalprio == 1 &&
1907 fdir_info->fdir_guarantee_free_space > 0)
1908 fdir_info->fdir_guarantee_free_space--;
1910 fdir_info->fdir_actual_cnt--;
1911 if (fdir_info->fdir_invalprio == 1 &&
1912 fdir_info->fdir_guarantee_free_space <
1913 fdir_info->fdir_guarantee_total_space)
1914 fdir_info->fdir_guarantee_free_space++;
1922 i40e_sw_fdir_filter_del(pf, &check_filter.fdir.input);
1924 i40e_sw_fdir_filter_insert(pf, &check_filter);
1930 * i40e_fdir_filter_programming - Program a flow director filter rule.
1931 * Is done by Flow Director Programming Descriptor followed by packet
1932 * structure that contains the filter fields need to match.
1933 * @pf: board private structure
1935 * @filter: fdir filter entry
1936 * @add: 0 - delete, 1 - add
1939 i40e_fdir_filter_programming(struct i40e_pf *pf,
1940 enum i40e_filter_pctype pctype,
1941 const struct rte_eth_fdir_filter *filter,
1944 struct i40e_tx_queue *txq = pf->fdir.txq;
1945 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1946 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1947 volatile struct i40e_tx_desc *txdp;
1948 volatile struct i40e_filter_program_desc *fdirdp;
1953 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1954 fdirdp = (volatile struct i40e_filter_program_desc *)
1955 (&(txq->tx_ring[txq->tx_tail]));
1957 fdirdp->qindex_flex_ptype_vsi =
1958 rte_cpu_to_le_32((fdir_action->rx_queue <<
1959 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1960 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1962 fdirdp->qindex_flex_ptype_vsi |=
1963 rte_cpu_to_le_32((fdir_action->flex_off <<
1964 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1965 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1967 fdirdp->qindex_flex_ptype_vsi |=
1968 rte_cpu_to_le_32((pctype <<
1969 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1970 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1972 if (filter->input.flow_ext.is_vf)
1973 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1975 /* Use LAN VSI Id by default */
1976 vsi_id = pf->main_vsi->vsi_id;
1977 fdirdp->qindex_flex_ptype_vsi |=
1978 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1979 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1980 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1982 fdirdp->dtype_cmd_cntindex =
1983 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1986 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1987 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1988 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1990 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1991 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1992 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1994 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1995 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1996 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1997 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1998 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1999 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
2001 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
2002 " unsupported fdir behavior.");
2006 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
2007 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
2008 I40E_TXD_FLTR_QW1_DEST_MASK);
2010 fdirdp->dtype_cmd_cntindex |=
2011 rte_cpu_to_le_32((fdir_action->report_status<<
2012 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
2013 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
2015 fdirdp->dtype_cmd_cntindex |=
2016 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
2017 fdirdp->dtype_cmd_cntindex |=
2019 ((uint32_t)pf->fdir.match_counter_index <<
2020 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2021 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
2023 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
2025 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
2026 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
2027 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr[0]);
2028 td_cmd = I40E_TX_DESC_CMD_EOP |
2029 I40E_TX_DESC_CMD_RS |
2030 I40E_TX_DESC_CMD_DUMMY;
2032 txdp->cmd_type_offset_bsz =
2033 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
2035 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
2036 if (txq->tx_tail >= txq->nb_tx_desc)
2038 /* Update the tx tail register */
2040 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2041 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
2042 if ((txdp->cmd_type_offset_bsz &
2043 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
2044 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
2048 if (i >= I40E_FDIR_MAX_WAIT_US) {
2049 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
2050 " time out to get DD on tx queue.");
2053 /* totally delay 10 ms to check programming status*/
2054 for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
2055 if (i40e_check_fdir_programming_status(rxq) >= 0)
2060 "Failed to program FDIR filter: programming status reported.");
2065 * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
2066 * Is done by Flow Director Programming Descriptor followed by packet
2067 * structure that contains the filter fields need to match.
2068 * @pf: board private structure
2070 * @filter: fdir filter entry
2071 * @add: 0 - delete, 1 - add
2074 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
2075 enum i40e_filter_pctype pctype,
2076 const struct i40e_fdir_filter_conf *filter,
2077 bool add, bool wait_status)
2079 struct i40e_tx_queue *txq = pf->fdir.txq;
2080 struct i40e_rx_queue *rxq = pf->fdir.rxq;
2081 const struct i40e_fdir_action *fdir_action = &filter->action;
2082 volatile struct i40e_tx_desc *txdp;
2083 volatile struct i40e_filter_program_desc *fdirdp;
2089 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
2090 fdirdp = (volatile struct i40e_filter_program_desc *)
2091 (&txq->tx_ring[txq->tx_tail]);
2093 fdirdp->qindex_flex_ptype_vsi =
2094 rte_cpu_to_le_32((fdir_action->rx_queue <<
2095 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2096 I40E_TXD_FLTR_QW0_QINDEX_MASK);
2098 fdirdp->qindex_flex_ptype_vsi |=
2099 rte_cpu_to_le_32((fdir_action->flex_off <<
2100 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
2101 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
2103 fdirdp->qindex_flex_ptype_vsi |=
2104 rte_cpu_to_le_32((pctype <<
2105 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
2106 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
2108 if (filter->input.flow_ext.is_vf)
2109 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
2111 /* Use LAN VSI Id by default */
2112 vsi_id = pf->main_vsi->vsi_id;
2113 fdirdp->qindex_flex_ptype_vsi |=
2114 rte_cpu_to_le_32(((uint32_t)vsi_id <<
2115 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
2116 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
2118 fdirdp->dtype_cmd_cntindex =
2119 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
2122 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
2123 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2124 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2126 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
2127 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2128 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2130 if (fdir_action->behavior == I40E_FDIR_REJECT)
2131 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
2132 else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
2133 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
2134 else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
2135 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
2137 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
2141 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
2142 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
2143 I40E_TXD_FLTR_QW1_DEST_MASK);
2145 fdirdp->dtype_cmd_cntindex |=
2146 rte_cpu_to_le_32((fdir_action->report_status <<
2147 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
2148 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
2150 fdirdp->dtype_cmd_cntindex |=
2151 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
2152 fdirdp->dtype_cmd_cntindex |=
2154 ((uint32_t)pf->fdir.match_counter_index <<
2155 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2156 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
2158 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
2160 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
2161 txdp = &txq->tx_ring[txq->tx_tail + 1];
2162 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr[txq->tx_tail >> 1]);
2164 td_cmd = I40E_TX_DESC_CMD_EOP |
2165 I40E_TX_DESC_CMD_RS |
2166 I40E_TX_DESC_CMD_DUMMY;
2168 txdp->cmd_type_offset_bsz =
2169 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
2171 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
2172 if (txq->tx_tail >= txq->nb_tx_desc)
2174 /* Update the tx tail register */
2177 /* fdir program rx queue cleanup */
2178 i40e_fdir_programming_status_cleanup(rxq);
2180 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2183 for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
2184 if ((txdp->cmd_type_offset_bsz &
2185 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
2186 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
2190 if (i >= I40E_FDIR_MAX_WAIT_US) {
2192 "Failed to program FDIR filter: time out to get DD on tx queue.");
2195 /* totally delay 10 ms to check programming status*/
2196 rte_delay_us(I40E_FDIR_MAX_WAIT_US);
2197 if (i40e_check_fdir_programming_status(rxq) < 0) {
2199 "Failed to program FDIR filter: programming status reported.");
2208 * i40e_fdir_flush - clear all filters of Flow Director table
2209 * @pf: board private structure
2212 i40e_fdir_flush(struct rte_eth_dev *dev)
2214 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2215 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2217 uint16_t guarant_cnt, best_cnt;
2220 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
2221 I40E_WRITE_FLUSH(hw);
2223 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
2224 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
2225 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
2226 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
2229 if (i >= I40E_FDIR_FLUSH_RETRY) {
2230 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
2233 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2234 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2235 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2236 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2237 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2238 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2239 if (guarant_cnt != 0 || best_cnt != 0) {
2240 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
2243 PMD_DRV_LOG(INFO, "FD table Flush success.");
2248 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
2249 struct rte_eth_flex_payload_cfg *flex_set,
2252 struct i40e_fdir_flex_pit *flex_pit;
2253 struct rte_eth_flex_payload_cfg *ptr = flex_set;
2254 uint16_t src, dst, size, j, k;
2255 uint8_t i, layer_idx;
2257 for (layer_idx = I40E_FLXPLD_L2_IDX;
2258 layer_idx <= I40E_FLXPLD_L4_IDX;
2260 if (layer_idx == I40E_FLXPLD_L2_IDX)
2261 ptr->type = RTE_ETH_L2_PAYLOAD;
2262 else if (layer_idx == I40E_FLXPLD_L3_IDX)
2263 ptr->type = RTE_ETH_L3_PAYLOAD;
2264 else if (layer_idx == I40E_FLXPLD_L4_IDX)
2265 ptr->type = RTE_ETH_L4_PAYLOAD;
2267 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
2268 flex_pit = &pf->fdir.flex_set[layer_idx *
2269 I40E_MAX_FLXPLD_FIED + i];
2270 if (flex_pit->size == 0)
2272 src = flex_pit->src_offset * sizeof(uint16_t);
2273 dst = flex_pit->dst_offset * sizeof(uint16_t);
2274 size = flex_pit->size * sizeof(uint16_t);
2275 for (j = src, k = dst; j < src + size; j++, k++)
2276 ptr->src_offset[k] = j;
2284 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
2285 struct rte_eth_fdir_flex_mask *flex_mask,
2288 struct i40e_fdir_flex_mask *mask;
2289 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
2292 uint16_t off_bytes, mask_tmp;
2294 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2295 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
2297 mask = &pf->fdir.flex_mask[i];
2298 flow_type = i40e_pctype_to_flowtype(pf->adapter,
2299 (enum i40e_filter_pctype)i);
2300 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
2303 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
2304 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
2305 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
2306 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
2308 ptr->mask[j * sizeof(uint16_t)] = 0x0;
2309 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
2312 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
2313 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
2314 mask_tmp = ~mask->bitmask[j].mask;
2315 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
2316 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
2318 ptr->flow_type = flow_type;
2325 * i40e_fdir_info_get - get information of Flow Director
2326 * @pf: ethernet device to get info from
2327 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
2328 * the flow director information.
2331 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2334 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2335 uint16_t num_flex_set = 0;
2336 uint16_t num_flex_mask = 0;
2339 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2340 fdir->mode = RTE_FDIR_MODE_PERFECT;
2342 fdir->mode = RTE_FDIR_MODE_NONE;
2345 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2347 (uint32_t)hw->func_caps.fd_filters_best_effort;
2348 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2349 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2350 for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2351 fdir->flow_types_mask[i] = 0ULL;
2352 fdir->flex_payload_unit = sizeof(uint16_t);
2353 fdir->flex_bitmask_unit = sizeof(uint16_t);
2354 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2355 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2356 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2358 i40e_fdir_info_get_flex_set(pf,
2359 fdir->flex_conf.flex_set,
2361 i40e_fdir_info_get_flex_mask(pf,
2362 fdir->flex_conf.flex_mask,
2365 fdir->flex_conf.nb_payloads = num_flex_set;
2366 fdir->flex_conf.nb_flexmasks = num_flex_mask;
2370 * i40e_fdir_stat_get - get statistics of Flow Director
2371 * @pf: ethernet device to get info from
2372 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2373 * the flow director statistics.
2376 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2378 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2379 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2382 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2384 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2385 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2387 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2388 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2392 i40e_fdir_filter_set(struct rte_eth_dev *dev,
2393 struct rte_eth_fdir_filter_info *info)
2395 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2399 PMD_DRV_LOG(ERR, "Invalid pointer");
2403 switch (info->info_type) {
2404 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
2405 ret = i40e_fdir_filter_inset_select(pf,
2406 &(info->info.input_set_conf));
2409 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
2418 * i40e_fdir_ctrl_func - deal with all operations on flow director.
2419 * @pf: board private structure
2420 * @filter_op:operation will be taken.
2421 * @arg: a pointer to specific structure corresponding to the filter_op
2424 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
2425 enum rte_filter_op filter_op,
2428 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2431 if ((pf->flags & I40E_FLAG_FDIR) == 0)
2434 if (filter_op == RTE_ETH_FILTER_NOP)
2437 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2440 switch (filter_op) {
2441 case RTE_ETH_FILTER_ADD:
2442 ret = i40e_add_del_fdir_filter(dev,
2443 (struct rte_eth_fdir_filter *)arg,
2446 case RTE_ETH_FILTER_DELETE:
2447 ret = i40e_add_del_fdir_filter(dev,
2448 (struct rte_eth_fdir_filter *)arg,
2451 case RTE_ETH_FILTER_FLUSH:
2452 ret = i40e_fdir_flush(dev);
2454 case RTE_ETH_FILTER_INFO:
2455 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2457 case RTE_ETH_FILTER_SET:
2458 ret = i40e_fdir_filter_set(dev,
2459 (struct rte_eth_fdir_filter_info *)arg);
2461 case RTE_ETH_FILTER_STATS:
2462 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2465 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2472 /* Restore flow director filter */
2474 i40e_fdir_filter_restore(struct i40e_pf *pf)
2476 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2477 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2478 struct i40e_fdir_filter *f;
2479 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2481 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
2482 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
2484 TAILQ_FOREACH(f, fdir_list, rules)
2485 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2487 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2489 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2490 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2492 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2493 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2495 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d",
2496 guarant_cnt, best_cnt);