drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_log.h>
  16 #include <rte_malloc.h>
  17 #include <rte_eth_ctrl.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_item *pattern,
  57                                         struct rte_flow_error *error,
  58                                         struct i40e_fdir_filter_conf *filter);
  59 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  60                                        const struct rte_flow_action *actions,
  61                                        struct rte_flow_error *error,
  62                                        struct i40e_fdir_filter_conf *filter);
  63 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  64                                  const struct rte_flow_action *actions,
  65                                  struct rte_flow_error *error,
  66                                  struct i40e_tunnel_filter_conf *filter);
  67 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  68                                 struct rte_flow_error *error);
  69 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  70                                     const struct rte_flow_attr *attr,
  71                                     const struct rte_flow_item pattern[],
  72                                     const struct rte_flow_action actions[],
  73                                     struct rte_flow_error *error,
  74                                     union i40e_filter_t *filter);
  75 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  76                                        const struct rte_flow_attr *attr,
  77                                        const struct rte_flow_item pattern[],
  78                                        const struct rte_flow_action actions[],
  79                                        struct rte_flow_error *error,
  80                                        union i40e_filter_t *filter);
  81 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  82                                         const struct rte_flow_attr *attr,
  83                                         const struct rte_flow_item pattern[],
  84                                         const struct rte_flow_action actions[],
  85                                         struct rte_flow_error *error,
  86                                         union i40e_filter_t *filter);
  87 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  88                                         const struct rte_flow_attr *attr,
  89                                         const struct rte_flow_item pattern[],
  90                                         const struct rte_flow_action actions[],
  91                                         struct rte_flow_error *error,
  92                                         union i40e_filter_t *filter);
  93 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  94                                        const struct rte_flow_attr *attr,
  95                                        const struct rte_flow_item pattern[],
  96                                        const struct rte_flow_action actions[],
  97                                        struct rte_flow_error *error,
  98                                        union i40e_filter_t *filter);
  99 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 100                                       const struct rte_flow_attr *attr,
 101                                       const struct rte_flow_item pattern[],
 102                                       const struct rte_flow_action actions[],
 103                                       struct rte_flow_error *error,
 104                                       union i40e_filter_t *filter);
 105 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 106                                       struct i40e_ethertype_filter *filter);
 107 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 108                                            struct i40e_tunnel_filter *filter);
 109 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 110 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 112 static int
 113 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 114 static int
 115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 116                               const struct rte_flow_attr *attr,
 117                               const struct rte_flow_item pattern[],
 118                               const struct rte_flow_action actions[],
 119                               struct rte_flow_error *error,
 120                               union i40e_filter_t *filter);
 121 static int
 122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 123                               const struct rte_flow_item *pattern,
 124                               struct rte_flow_error *error,
 125                               struct i40e_tunnel_filter_conf *filter);
 126
 127 const struct rte_flow_ops i40e_flow_ops = {
 128         .validate = i40e_flow_validate,
 129         .create = i40e_flow_create,
 130         .destroy = i40e_flow_destroy,
 131         .flush = i40e_flow_flush,
 132 };
 133
 134 union i40e_filter_t cons_filter;
 135 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 136
 137 /* Pattern matched ethertype filter */
 138 static enum rte_flow_item_type pattern_ethertype[] = {
 139         RTE_FLOW_ITEM_TYPE_ETH,
 140         RTE_FLOW_ITEM_TYPE_END,
 141 };
 142
 143 /* Pattern matched flow director filter */
 144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 145         RTE_FLOW_ITEM_TYPE_ETH,
 146         RTE_FLOW_ITEM_TYPE_IPV4,
 147         RTE_FLOW_ITEM_TYPE_END,
 148 };
 149
 150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 151         RTE_FLOW_ITEM_TYPE_ETH,
 152         RTE_FLOW_ITEM_TYPE_IPV4,
 153         RTE_FLOW_ITEM_TYPE_UDP,
 154         RTE_FLOW_ITEM_TYPE_END,
 155 };
 156
 157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 158         RTE_FLOW_ITEM_TYPE_ETH,
 159         RTE_FLOW_ITEM_TYPE_IPV4,
 160         RTE_FLOW_ITEM_TYPE_TCP,
 161         RTE_FLOW_ITEM_TYPE_END,
 162 };
 163
 164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 165         RTE_FLOW_ITEM_TYPE_ETH,
 166         RTE_FLOW_ITEM_TYPE_IPV4,
 167         RTE_FLOW_ITEM_TYPE_SCTP,
 168         RTE_FLOW_ITEM_TYPE_END,
 169 };
 170
 171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 172         RTE_FLOW_ITEM_TYPE_ETH,
 173         RTE_FLOW_ITEM_TYPE_IPV4,
 174         RTE_FLOW_ITEM_TYPE_UDP,
 175         RTE_FLOW_ITEM_TYPE_GTPC,
 176         RTE_FLOW_ITEM_TYPE_END,
 177 };
 178
 179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 180         RTE_FLOW_ITEM_TYPE_ETH,
 181         RTE_FLOW_ITEM_TYPE_IPV4,
 182         RTE_FLOW_ITEM_TYPE_UDP,
 183         RTE_FLOW_ITEM_TYPE_GTPU,
 184         RTE_FLOW_ITEM_TYPE_END,
 185 };
 186
 187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 188         RTE_FLOW_ITEM_TYPE_ETH,
 189         RTE_FLOW_ITEM_TYPE_IPV4,
 190         RTE_FLOW_ITEM_TYPE_UDP,
 191         RTE_FLOW_ITEM_TYPE_GTPU,
 192         RTE_FLOW_ITEM_TYPE_IPV4,
 193         RTE_FLOW_ITEM_TYPE_END,
 194 };
 195
 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 197         RTE_FLOW_ITEM_TYPE_ETH,
 198         RTE_FLOW_ITEM_TYPE_IPV4,
 199         RTE_FLOW_ITEM_TYPE_UDP,
 200         RTE_FLOW_ITEM_TYPE_GTPU,
 201         RTE_FLOW_ITEM_TYPE_IPV6,
 202         RTE_FLOW_ITEM_TYPE_END,
 203 };
 204
 205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 206         RTE_FLOW_ITEM_TYPE_ETH,
 207         RTE_FLOW_ITEM_TYPE_IPV6,
 208         RTE_FLOW_ITEM_TYPE_END,
 209 };
 210
 211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 212         RTE_FLOW_ITEM_TYPE_ETH,
 213         RTE_FLOW_ITEM_TYPE_IPV6,
 214         RTE_FLOW_ITEM_TYPE_UDP,
 215         RTE_FLOW_ITEM_TYPE_END,
 216 };
 217
 218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 219         RTE_FLOW_ITEM_TYPE_ETH,
 220         RTE_FLOW_ITEM_TYPE_IPV6,
 221         RTE_FLOW_ITEM_TYPE_TCP,
 222         RTE_FLOW_ITEM_TYPE_END,
 223 };
 224
 225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 226         RTE_FLOW_ITEM_TYPE_ETH,
 227         RTE_FLOW_ITEM_TYPE_IPV6,
 228         RTE_FLOW_ITEM_TYPE_SCTP,
 229         RTE_FLOW_ITEM_TYPE_END,
 230 };
 231
 232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 233         RTE_FLOW_ITEM_TYPE_ETH,
 234         RTE_FLOW_ITEM_TYPE_IPV6,
 235         RTE_FLOW_ITEM_TYPE_UDP,
 236         RTE_FLOW_ITEM_TYPE_GTPC,
 237         RTE_FLOW_ITEM_TYPE_END,
 238 };
 239
 240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 241         RTE_FLOW_ITEM_TYPE_ETH,
 242         RTE_FLOW_ITEM_TYPE_IPV6,
 243         RTE_FLOW_ITEM_TYPE_UDP,
 244         RTE_FLOW_ITEM_TYPE_GTPU,
 245         RTE_FLOW_ITEM_TYPE_END,
 246 };
 247
 248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 249         RTE_FLOW_ITEM_TYPE_ETH,
 250         RTE_FLOW_ITEM_TYPE_IPV6,
 251         RTE_FLOW_ITEM_TYPE_UDP,
 252         RTE_FLOW_ITEM_TYPE_GTPU,
 253         RTE_FLOW_ITEM_TYPE_IPV4,
 254         RTE_FLOW_ITEM_TYPE_END,
 255 };
 256
 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 258         RTE_FLOW_ITEM_TYPE_ETH,
 259         RTE_FLOW_ITEM_TYPE_IPV6,
 260         RTE_FLOW_ITEM_TYPE_UDP,
 261         RTE_FLOW_ITEM_TYPE_GTPU,
 262         RTE_FLOW_ITEM_TYPE_IPV6,
 263         RTE_FLOW_ITEM_TYPE_END,
 264 };
 265
 266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 267         RTE_FLOW_ITEM_TYPE_ETH,
 268         RTE_FLOW_ITEM_TYPE_RAW,
 269         RTE_FLOW_ITEM_TYPE_END,
 270 };
 271
 272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 273         RTE_FLOW_ITEM_TYPE_ETH,
 274         RTE_FLOW_ITEM_TYPE_RAW,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_END,
 277 };
 278
 279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 280         RTE_FLOW_ITEM_TYPE_ETH,
 281         RTE_FLOW_ITEM_TYPE_RAW,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_END,
 285 };
 286
 287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 288         RTE_FLOW_ITEM_TYPE_ETH,
 289         RTE_FLOW_ITEM_TYPE_IPV4,
 290         RTE_FLOW_ITEM_TYPE_RAW,
 291         RTE_FLOW_ITEM_TYPE_END,
 292 };
 293
 294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 295         RTE_FLOW_ITEM_TYPE_ETH,
 296         RTE_FLOW_ITEM_TYPE_IPV4,
 297         RTE_FLOW_ITEM_TYPE_RAW,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_END,
 300 };
 301
 302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 303         RTE_FLOW_ITEM_TYPE_ETH,
 304         RTE_FLOW_ITEM_TYPE_IPV4,
 305         RTE_FLOW_ITEM_TYPE_RAW,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_END,
 309 };
 310
 311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 312         RTE_FLOW_ITEM_TYPE_ETH,
 313         RTE_FLOW_ITEM_TYPE_IPV4,
 314         RTE_FLOW_ITEM_TYPE_UDP,
 315         RTE_FLOW_ITEM_TYPE_RAW,
 316         RTE_FLOW_ITEM_TYPE_END,
 317 };
 318
 319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 320         RTE_FLOW_ITEM_TYPE_ETH,
 321         RTE_FLOW_ITEM_TYPE_IPV4,
 322         RTE_FLOW_ITEM_TYPE_UDP,
 323         RTE_FLOW_ITEM_TYPE_RAW,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_END,
 326 };
 327
 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 329         RTE_FLOW_ITEM_TYPE_ETH,
 330         RTE_FLOW_ITEM_TYPE_IPV4,
 331         RTE_FLOW_ITEM_TYPE_UDP,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_END,
 336 };
 337
 338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 339         RTE_FLOW_ITEM_TYPE_ETH,
 340         RTE_FLOW_ITEM_TYPE_IPV4,
 341         RTE_FLOW_ITEM_TYPE_TCP,
 342         RTE_FLOW_ITEM_TYPE_RAW,
 343         RTE_FLOW_ITEM_TYPE_END,
 344 };
 345
 346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 347         RTE_FLOW_ITEM_TYPE_ETH,
 348         RTE_FLOW_ITEM_TYPE_IPV4,
 349         RTE_FLOW_ITEM_TYPE_TCP,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_TCP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_END,
 363 };
 364
 365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 366         RTE_FLOW_ITEM_TYPE_ETH,
 367         RTE_FLOW_ITEM_TYPE_IPV4,
 368         RTE_FLOW_ITEM_TYPE_SCTP,
 369         RTE_FLOW_ITEM_TYPE_RAW,
 370         RTE_FLOW_ITEM_TYPE_END,
 371 };
 372
 373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 374         RTE_FLOW_ITEM_TYPE_ETH,
 375         RTE_FLOW_ITEM_TYPE_IPV4,
 376         RTE_FLOW_ITEM_TYPE_SCTP,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_SCTP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_END,
 390 };
 391
 392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 393         RTE_FLOW_ITEM_TYPE_ETH,
 394         RTE_FLOW_ITEM_TYPE_IPV6,
 395         RTE_FLOW_ITEM_TYPE_RAW,
 396         RTE_FLOW_ITEM_TYPE_END,
 397 };
 398
 399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 400         RTE_FLOW_ITEM_TYPE_ETH,
 401         RTE_FLOW_ITEM_TYPE_IPV6,
 402         RTE_FLOW_ITEM_TYPE_RAW,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_END,
 405 };
 406
 407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 408         RTE_FLOW_ITEM_TYPE_ETH,
 409         RTE_FLOW_ITEM_TYPE_IPV6,
 410         RTE_FLOW_ITEM_TYPE_RAW,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_END,
 414 };
 415
 416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 417         RTE_FLOW_ITEM_TYPE_ETH,
 418         RTE_FLOW_ITEM_TYPE_IPV6,
 419         RTE_FLOW_ITEM_TYPE_UDP,
 420         RTE_FLOW_ITEM_TYPE_RAW,
 421         RTE_FLOW_ITEM_TYPE_END,
 422 };
 423
 424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 425         RTE_FLOW_ITEM_TYPE_ETH,
 426         RTE_FLOW_ITEM_TYPE_IPV6,
 427         RTE_FLOW_ITEM_TYPE_UDP,
 428         RTE_FLOW_ITEM_TYPE_RAW,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_END,
 431 };
 432
 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 434         RTE_FLOW_ITEM_TYPE_ETH,
 435         RTE_FLOW_ITEM_TYPE_IPV6,
 436         RTE_FLOW_ITEM_TYPE_UDP,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_END,
 441 };
 442
 443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 444         RTE_FLOW_ITEM_TYPE_ETH,
 445         RTE_FLOW_ITEM_TYPE_IPV6,
 446         RTE_FLOW_ITEM_TYPE_TCP,
 447         RTE_FLOW_ITEM_TYPE_RAW,
 448         RTE_FLOW_ITEM_TYPE_END,
 449 };
 450
 451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 452         RTE_FLOW_ITEM_TYPE_ETH,
 453         RTE_FLOW_ITEM_TYPE_IPV6,
 454         RTE_FLOW_ITEM_TYPE_TCP,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_TCP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_END,
 468 };
 469
 470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 471         RTE_FLOW_ITEM_TYPE_ETH,
 472         RTE_FLOW_ITEM_TYPE_IPV6,
 473         RTE_FLOW_ITEM_TYPE_SCTP,
 474         RTE_FLOW_ITEM_TYPE_RAW,
 475         RTE_FLOW_ITEM_TYPE_END,
 476 };
 477
 478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 479         RTE_FLOW_ITEM_TYPE_ETH,
 480         RTE_FLOW_ITEM_TYPE_IPV6,
 481         RTE_FLOW_ITEM_TYPE_SCTP,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_SCTP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_END,
 495 };
 496
 497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 498         RTE_FLOW_ITEM_TYPE_ETH,
 499         RTE_FLOW_ITEM_TYPE_VLAN,
 500         RTE_FLOW_ITEM_TYPE_END,
 501 };
 502
 503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 504         RTE_FLOW_ITEM_TYPE_ETH,
 505         RTE_FLOW_ITEM_TYPE_VLAN,
 506         RTE_FLOW_ITEM_TYPE_IPV4,
 507         RTE_FLOW_ITEM_TYPE_END,
 508 };
 509
 510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 511         RTE_FLOW_ITEM_TYPE_ETH,
 512         RTE_FLOW_ITEM_TYPE_VLAN,
 513         RTE_FLOW_ITEM_TYPE_IPV4,
 514         RTE_FLOW_ITEM_TYPE_UDP,
 515         RTE_FLOW_ITEM_TYPE_END,
 516 };
 517
 518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 519         RTE_FLOW_ITEM_TYPE_ETH,
 520         RTE_FLOW_ITEM_TYPE_VLAN,
 521         RTE_FLOW_ITEM_TYPE_IPV4,
 522         RTE_FLOW_ITEM_TYPE_TCP,
 523         RTE_FLOW_ITEM_TYPE_END,
 524 };
 525
 526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 527         RTE_FLOW_ITEM_TYPE_ETH,
 528         RTE_FLOW_ITEM_TYPE_VLAN,
 529         RTE_FLOW_ITEM_TYPE_IPV4,
 530         RTE_FLOW_ITEM_TYPE_SCTP,
 531         RTE_FLOW_ITEM_TYPE_END,
 532 };
 533
 534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 535         RTE_FLOW_ITEM_TYPE_ETH,
 536         RTE_FLOW_ITEM_TYPE_VLAN,
 537         RTE_FLOW_ITEM_TYPE_IPV6,
 538         RTE_FLOW_ITEM_TYPE_END,
 539 };
 540
 541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 542         RTE_FLOW_ITEM_TYPE_ETH,
 543         RTE_FLOW_ITEM_TYPE_VLAN,
 544         RTE_FLOW_ITEM_TYPE_IPV6,
 545         RTE_FLOW_ITEM_TYPE_UDP,
 546         RTE_FLOW_ITEM_TYPE_END,
 547 };
 548
 549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 550         RTE_FLOW_ITEM_TYPE_ETH,
 551         RTE_FLOW_ITEM_TYPE_VLAN,
 552         RTE_FLOW_ITEM_TYPE_IPV6,
 553         RTE_FLOW_ITEM_TYPE_TCP,
 554         RTE_FLOW_ITEM_TYPE_END,
 555 };
 556
 557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 558         RTE_FLOW_ITEM_TYPE_ETH,
 559         RTE_FLOW_ITEM_TYPE_VLAN,
 560         RTE_FLOW_ITEM_TYPE_IPV6,
 561         RTE_FLOW_ITEM_TYPE_SCTP,
 562         RTE_FLOW_ITEM_TYPE_END,
 563 };
 564
 565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 566         RTE_FLOW_ITEM_TYPE_ETH,
 567         RTE_FLOW_ITEM_TYPE_VLAN,
 568         RTE_FLOW_ITEM_TYPE_RAW,
 569         RTE_FLOW_ITEM_TYPE_END,
 570 };
 571
 572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 573         RTE_FLOW_ITEM_TYPE_ETH,
 574         RTE_FLOW_ITEM_TYPE_VLAN,
 575         RTE_FLOW_ITEM_TYPE_RAW,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_END,
 578 };
 579
 580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 581         RTE_FLOW_ITEM_TYPE_ETH,
 582         RTE_FLOW_ITEM_TYPE_VLAN,
 583         RTE_FLOW_ITEM_TYPE_RAW,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_END,
 587 };
 588
 589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 590         RTE_FLOW_ITEM_TYPE_ETH,
 591         RTE_FLOW_ITEM_TYPE_VLAN,
 592         RTE_FLOW_ITEM_TYPE_IPV4,
 593         RTE_FLOW_ITEM_TYPE_RAW,
 594         RTE_FLOW_ITEM_TYPE_END,
 595 };
 596
 597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 598         RTE_FLOW_ITEM_TYPE_ETH,
 599         RTE_FLOW_ITEM_TYPE_VLAN,
 600         RTE_FLOW_ITEM_TYPE_IPV4,
 601         RTE_FLOW_ITEM_TYPE_RAW,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_END,
 604 };
 605
 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 607         RTE_FLOW_ITEM_TYPE_ETH,
 608         RTE_FLOW_ITEM_TYPE_VLAN,
 609         RTE_FLOW_ITEM_TYPE_IPV4,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_END,
 614 };
 615
 616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 617         RTE_FLOW_ITEM_TYPE_ETH,
 618         RTE_FLOW_ITEM_TYPE_VLAN,
 619         RTE_FLOW_ITEM_TYPE_IPV4,
 620         RTE_FLOW_ITEM_TYPE_UDP,
 621         RTE_FLOW_ITEM_TYPE_RAW,
 622         RTE_FLOW_ITEM_TYPE_END,
 623 };
 624
 625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 626         RTE_FLOW_ITEM_TYPE_ETH,
 627         RTE_FLOW_ITEM_TYPE_VLAN,
 628         RTE_FLOW_ITEM_TYPE_IPV4,
 629         RTE_FLOW_ITEM_TYPE_UDP,
 630         RTE_FLOW_ITEM_TYPE_RAW,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_END,
 633 };
 634
 635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 636         RTE_FLOW_ITEM_TYPE_ETH,
 637         RTE_FLOW_ITEM_TYPE_VLAN,
 638         RTE_FLOW_ITEM_TYPE_IPV4,
 639         RTE_FLOW_ITEM_TYPE_UDP,
 640         RTE_FLOW_ITEM_TYPE_RAW,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_END,
 644 };
 645
 646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 647         RTE_FLOW_ITEM_TYPE_ETH,
 648         RTE_FLOW_ITEM_TYPE_VLAN,
 649         RTE_FLOW_ITEM_TYPE_IPV4,
 650         RTE_FLOW_ITEM_TYPE_TCP,
 651         RTE_FLOW_ITEM_TYPE_RAW,
 652         RTE_FLOW_ITEM_TYPE_END,
 653 };
 654
 655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 656         RTE_FLOW_ITEM_TYPE_ETH,
 657         RTE_FLOW_ITEM_TYPE_VLAN,
 658         RTE_FLOW_ITEM_TYPE_IPV4,
 659         RTE_FLOW_ITEM_TYPE_TCP,
 660         RTE_FLOW_ITEM_TYPE_RAW,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_END,
 663 };
 664
 665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 666         RTE_FLOW_ITEM_TYPE_ETH,
 667         RTE_FLOW_ITEM_TYPE_VLAN,
 668         RTE_FLOW_ITEM_TYPE_IPV4,
 669         RTE_FLOW_ITEM_TYPE_TCP,
 670         RTE_FLOW_ITEM_TYPE_RAW,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_END,
 674 };
 675
 676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 677         RTE_FLOW_ITEM_TYPE_ETH,
 678         RTE_FLOW_ITEM_TYPE_VLAN,
 679         RTE_FLOW_ITEM_TYPE_IPV4,
 680         RTE_FLOW_ITEM_TYPE_SCTP,
 681         RTE_FLOW_ITEM_TYPE_RAW,
 682         RTE_FLOW_ITEM_TYPE_END,
 683 };
 684
 685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 686         RTE_FLOW_ITEM_TYPE_ETH,
 687         RTE_FLOW_ITEM_TYPE_VLAN,
 688         RTE_FLOW_ITEM_TYPE_IPV4,
 689         RTE_FLOW_ITEM_TYPE_SCTP,
 690         RTE_FLOW_ITEM_TYPE_RAW,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_END,
 693 };
 694
 695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 696         RTE_FLOW_ITEM_TYPE_ETH,
 697         RTE_FLOW_ITEM_TYPE_VLAN,
 698         RTE_FLOW_ITEM_TYPE_IPV4,
 699         RTE_FLOW_ITEM_TYPE_SCTP,
 700         RTE_FLOW_ITEM_TYPE_RAW,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_END,
 704 };
 705
 706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 707         RTE_FLOW_ITEM_TYPE_ETH,
 708         RTE_FLOW_ITEM_TYPE_VLAN,
 709         RTE_FLOW_ITEM_TYPE_IPV6,
 710         RTE_FLOW_ITEM_TYPE_RAW,
 711         RTE_FLOW_ITEM_TYPE_END,
 712 };
 713
 714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 715         RTE_FLOW_ITEM_TYPE_ETH,
 716         RTE_FLOW_ITEM_TYPE_VLAN,
 717         RTE_FLOW_ITEM_TYPE_IPV6,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_END,
 721 };
 722
 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 724         RTE_FLOW_ITEM_TYPE_ETH,
 725         RTE_FLOW_ITEM_TYPE_VLAN,
 726         RTE_FLOW_ITEM_TYPE_IPV6,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_END,
 731 };
 732
 733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 734         RTE_FLOW_ITEM_TYPE_ETH,
 735         RTE_FLOW_ITEM_TYPE_VLAN,
 736         RTE_FLOW_ITEM_TYPE_IPV6,
 737         RTE_FLOW_ITEM_TYPE_UDP,
 738         RTE_FLOW_ITEM_TYPE_RAW,
 739         RTE_FLOW_ITEM_TYPE_END,
 740 };
 741
 742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 743         RTE_FLOW_ITEM_TYPE_ETH,
 744         RTE_FLOW_ITEM_TYPE_VLAN,
 745         RTE_FLOW_ITEM_TYPE_IPV6,
 746         RTE_FLOW_ITEM_TYPE_UDP,
 747         RTE_FLOW_ITEM_TYPE_RAW,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_END,
 750 };
 751
 752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 753         RTE_FLOW_ITEM_TYPE_ETH,
 754         RTE_FLOW_ITEM_TYPE_VLAN,
 755         RTE_FLOW_ITEM_TYPE_IPV6,
 756         RTE_FLOW_ITEM_TYPE_UDP,
 757         RTE_FLOW_ITEM_TYPE_RAW,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_END,
 761 };
 762
 763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 764         RTE_FLOW_ITEM_TYPE_ETH,
 765         RTE_FLOW_ITEM_TYPE_VLAN,
 766         RTE_FLOW_ITEM_TYPE_IPV6,
 767         RTE_FLOW_ITEM_TYPE_TCP,
 768         RTE_FLOW_ITEM_TYPE_RAW,
 769         RTE_FLOW_ITEM_TYPE_END,
 770 };
 771
 772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 773         RTE_FLOW_ITEM_TYPE_ETH,
 774         RTE_FLOW_ITEM_TYPE_VLAN,
 775         RTE_FLOW_ITEM_TYPE_IPV6,
 776         RTE_FLOW_ITEM_TYPE_TCP,
 777         RTE_FLOW_ITEM_TYPE_RAW,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_END,
 780 };
 781
 782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 783         RTE_FLOW_ITEM_TYPE_ETH,
 784         RTE_FLOW_ITEM_TYPE_VLAN,
 785         RTE_FLOW_ITEM_TYPE_IPV6,
 786         RTE_FLOW_ITEM_TYPE_TCP,
 787         RTE_FLOW_ITEM_TYPE_RAW,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_END,
 791 };
 792
 793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 794         RTE_FLOW_ITEM_TYPE_ETH,
 795         RTE_FLOW_ITEM_TYPE_VLAN,
 796         RTE_FLOW_ITEM_TYPE_IPV6,
 797         RTE_FLOW_ITEM_TYPE_SCTP,
 798         RTE_FLOW_ITEM_TYPE_RAW,
 799         RTE_FLOW_ITEM_TYPE_END,
 800 };
 801
 802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 803         RTE_FLOW_ITEM_TYPE_ETH,
 804         RTE_FLOW_ITEM_TYPE_VLAN,
 805         RTE_FLOW_ITEM_TYPE_IPV6,
 806         RTE_FLOW_ITEM_TYPE_SCTP,
 807         RTE_FLOW_ITEM_TYPE_RAW,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_END,
 810 };
 811
 812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 813         RTE_FLOW_ITEM_TYPE_ETH,
 814         RTE_FLOW_ITEM_TYPE_VLAN,
 815         RTE_FLOW_ITEM_TYPE_IPV6,
 816         RTE_FLOW_ITEM_TYPE_SCTP,
 817         RTE_FLOW_ITEM_TYPE_RAW,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_END,
 821 };
 822
 823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 824         RTE_FLOW_ITEM_TYPE_ETH,
 825         RTE_FLOW_ITEM_TYPE_IPV4,
 826         RTE_FLOW_ITEM_TYPE_VF,
 827         RTE_FLOW_ITEM_TYPE_END,
 828 };
 829
 830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 831         RTE_FLOW_ITEM_TYPE_ETH,
 832         RTE_FLOW_ITEM_TYPE_IPV4,
 833         RTE_FLOW_ITEM_TYPE_UDP,
 834         RTE_FLOW_ITEM_TYPE_VF,
 835         RTE_FLOW_ITEM_TYPE_END,
 836 };
 837
 838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 839         RTE_FLOW_ITEM_TYPE_ETH,
 840         RTE_FLOW_ITEM_TYPE_IPV4,
 841         RTE_FLOW_ITEM_TYPE_TCP,
 842         RTE_FLOW_ITEM_TYPE_VF,
 843         RTE_FLOW_ITEM_TYPE_END,
 844 };
 845
 846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 847         RTE_FLOW_ITEM_TYPE_ETH,
 848         RTE_FLOW_ITEM_TYPE_IPV4,
 849         RTE_FLOW_ITEM_TYPE_SCTP,
 850         RTE_FLOW_ITEM_TYPE_VF,
 851         RTE_FLOW_ITEM_TYPE_END,
 852 };
 853
 854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 855         RTE_FLOW_ITEM_TYPE_ETH,
 856         RTE_FLOW_ITEM_TYPE_IPV6,
 857         RTE_FLOW_ITEM_TYPE_VF,
 858         RTE_FLOW_ITEM_TYPE_END,
 859 };
 860
 861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 862         RTE_FLOW_ITEM_TYPE_ETH,
 863         RTE_FLOW_ITEM_TYPE_IPV6,
 864         RTE_FLOW_ITEM_TYPE_UDP,
 865         RTE_FLOW_ITEM_TYPE_VF,
 866         RTE_FLOW_ITEM_TYPE_END,
 867 };
 868
 869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 870         RTE_FLOW_ITEM_TYPE_ETH,
 871         RTE_FLOW_ITEM_TYPE_IPV6,
 872         RTE_FLOW_ITEM_TYPE_TCP,
 873         RTE_FLOW_ITEM_TYPE_VF,
 874         RTE_FLOW_ITEM_TYPE_END,
 875 };
 876
 877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 878         RTE_FLOW_ITEM_TYPE_ETH,
 879         RTE_FLOW_ITEM_TYPE_IPV6,
 880         RTE_FLOW_ITEM_TYPE_SCTP,
 881         RTE_FLOW_ITEM_TYPE_VF,
 882         RTE_FLOW_ITEM_TYPE_END,
 883 };
 884
 885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 886         RTE_FLOW_ITEM_TYPE_ETH,
 887         RTE_FLOW_ITEM_TYPE_RAW,
 888         RTE_FLOW_ITEM_TYPE_VF,
 889         RTE_FLOW_ITEM_TYPE_END,
 890 };
 891
 892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 893         RTE_FLOW_ITEM_TYPE_ETH,
 894         RTE_FLOW_ITEM_TYPE_RAW,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_VF,
 897         RTE_FLOW_ITEM_TYPE_END,
 898 };
 899
 900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 901         RTE_FLOW_ITEM_TYPE_ETH,
 902         RTE_FLOW_ITEM_TYPE_RAW,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_VF,
 906         RTE_FLOW_ITEM_TYPE_END,
 907 };
 908
 909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 910         RTE_FLOW_ITEM_TYPE_ETH,
 911         RTE_FLOW_ITEM_TYPE_IPV4,
 912         RTE_FLOW_ITEM_TYPE_RAW,
 913         RTE_FLOW_ITEM_TYPE_VF,
 914         RTE_FLOW_ITEM_TYPE_END,
 915 };
 916
 917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 918         RTE_FLOW_ITEM_TYPE_ETH,
 919         RTE_FLOW_ITEM_TYPE_IPV4,
 920         RTE_FLOW_ITEM_TYPE_RAW,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_VF,
 923         RTE_FLOW_ITEM_TYPE_END,
 924 };
 925
 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 927         RTE_FLOW_ITEM_TYPE_ETH,
 928         RTE_FLOW_ITEM_TYPE_IPV4,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_VF,
 933         RTE_FLOW_ITEM_TYPE_END,
 934 };
 935
 936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 937         RTE_FLOW_ITEM_TYPE_ETH,
 938         RTE_FLOW_ITEM_TYPE_IPV4,
 939         RTE_FLOW_ITEM_TYPE_UDP,
 940         RTE_FLOW_ITEM_TYPE_RAW,
 941         RTE_FLOW_ITEM_TYPE_VF,
 942         RTE_FLOW_ITEM_TYPE_END,
 943 };
 944
 945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 946         RTE_FLOW_ITEM_TYPE_ETH,
 947         RTE_FLOW_ITEM_TYPE_IPV4,
 948         RTE_FLOW_ITEM_TYPE_UDP,
 949         RTE_FLOW_ITEM_TYPE_RAW,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_VF,
 952         RTE_FLOW_ITEM_TYPE_END,
 953 };
 954
 955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 956         RTE_FLOW_ITEM_TYPE_ETH,
 957         RTE_FLOW_ITEM_TYPE_IPV4,
 958         RTE_FLOW_ITEM_TYPE_UDP,
 959         RTE_FLOW_ITEM_TYPE_RAW,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_VF,
 963         RTE_FLOW_ITEM_TYPE_END,
 964 };
 965
 966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 967         RTE_FLOW_ITEM_TYPE_ETH,
 968         RTE_FLOW_ITEM_TYPE_IPV4,
 969         RTE_FLOW_ITEM_TYPE_TCP,
 970         RTE_FLOW_ITEM_TYPE_RAW,
 971         RTE_FLOW_ITEM_TYPE_VF,
 972         RTE_FLOW_ITEM_TYPE_END,
 973 };
 974
 975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 976         RTE_FLOW_ITEM_TYPE_ETH,
 977         RTE_FLOW_ITEM_TYPE_IPV4,
 978         RTE_FLOW_ITEM_TYPE_TCP,
 979         RTE_FLOW_ITEM_TYPE_RAW,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_VF,
 982         RTE_FLOW_ITEM_TYPE_END,
 983 };
 984
 985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 986         RTE_FLOW_ITEM_TYPE_ETH,
 987         RTE_FLOW_ITEM_TYPE_IPV4,
 988         RTE_FLOW_ITEM_TYPE_TCP,
 989         RTE_FLOW_ITEM_TYPE_RAW,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_VF,
 993         RTE_FLOW_ITEM_TYPE_END,
 994 };
 995
 996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 997         RTE_FLOW_ITEM_TYPE_ETH,
 998         RTE_FLOW_ITEM_TYPE_IPV4,
 999         RTE_FLOW_ITEM_TYPE_SCTP,
1000         RTE_FLOW_ITEM_TYPE_RAW,
1001         RTE_FLOW_ITEM_TYPE_VF,
1002         RTE_FLOW_ITEM_TYPE_END,
1003 };
1004
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006         RTE_FLOW_ITEM_TYPE_ETH,
1007         RTE_FLOW_ITEM_TYPE_IPV4,
1008         RTE_FLOW_ITEM_TYPE_SCTP,
1009         RTE_FLOW_ITEM_TYPE_RAW,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_VF,
1012         RTE_FLOW_ITEM_TYPE_END,
1013 };
1014
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016         RTE_FLOW_ITEM_TYPE_ETH,
1017         RTE_FLOW_ITEM_TYPE_IPV4,
1018         RTE_FLOW_ITEM_TYPE_SCTP,
1019         RTE_FLOW_ITEM_TYPE_RAW,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_VF,
1023         RTE_FLOW_ITEM_TYPE_END,
1024 };
1025
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027         RTE_FLOW_ITEM_TYPE_ETH,
1028         RTE_FLOW_ITEM_TYPE_IPV6,
1029         RTE_FLOW_ITEM_TYPE_RAW,
1030         RTE_FLOW_ITEM_TYPE_VF,
1031         RTE_FLOW_ITEM_TYPE_END,
1032 };
1033
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035         RTE_FLOW_ITEM_TYPE_ETH,
1036         RTE_FLOW_ITEM_TYPE_IPV6,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_VF,
1040         RTE_FLOW_ITEM_TYPE_END,
1041 };
1042
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044         RTE_FLOW_ITEM_TYPE_ETH,
1045         RTE_FLOW_ITEM_TYPE_IPV6,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_VF,
1050         RTE_FLOW_ITEM_TYPE_END,
1051 };
1052
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054         RTE_FLOW_ITEM_TYPE_ETH,
1055         RTE_FLOW_ITEM_TYPE_IPV6,
1056         RTE_FLOW_ITEM_TYPE_UDP,
1057         RTE_FLOW_ITEM_TYPE_RAW,
1058         RTE_FLOW_ITEM_TYPE_VF,
1059         RTE_FLOW_ITEM_TYPE_END,
1060 };
1061
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063         RTE_FLOW_ITEM_TYPE_ETH,
1064         RTE_FLOW_ITEM_TYPE_IPV6,
1065         RTE_FLOW_ITEM_TYPE_UDP,
1066         RTE_FLOW_ITEM_TYPE_RAW,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_VF,
1069         RTE_FLOW_ITEM_TYPE_END,
1070 };
1071
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073         RTE_FLOW_ITEM_TYPE_ETH,
1074         RTE_FLOW_ITEM_TYPE_IPV6,
1075         RTE_FLOW_ITEM_TYPE_UDP,
1076         RTE_FLOW_ITEM_TYPE_RAW,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_VF,
1080         RTE_FLOW_ITEM_TYPE_END,
1081 };
1082
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084         RTE_FLOW_ITEM_TYPE_ETH,
1085         RTE_FLOW_ITEM_TYPE_IPV6,
1086         RTE_FLOW_ITEM_TYPE_TCP,
1087         RTE_FLOW_ITEM_TYPE_RAW,
1088         RTE_FLOW_ITEM_TYPE_VF,
1089         RTE_FLOW_ITEM_TYPE_END,
1090 };
1091
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093         RTE_FLOW_ITEM_TYPE_ETH,
1094         RTE_FLOW_ITEM_TYPE_IPV6,
1095         RTE_FLOW_ITEM_TYPE_TCP,
1096         RTE_FLOW_ITEM_TYPE_RAW,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_VF,
1099         RTE_FLOW_ITEM_TYPE_END,
1100 };
1101
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103         RTE_FLOW_ITEM_TYPE_ETH,
1104         RTE_FLOW_ITEM_TYPE_IPV6,
1105         RTE_FLOW_ITEM_TYPE_TCP,
1106         RTE_FLOW_ITEM_TYPE_RAW,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_VF,
1110         RTE_FLOW_ITEM_TYPE_END,
1111 };
1112
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114         RTE_FLOW_ITEM_TYPE_ETH,
1115         RTE_FLOW_ITEM_TYPE_IPV6,
1116         RTE_FLOW_ITEM_TYPE_SCTP,
1117         RTE_FLOW_ITEM_TYPE_RAW,
1118         RTE_FLOW_ITEM_TYPE_VF,
1119         RTE_FLOW_ITEM_TYPE_END,
1120 };
1121
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123         RTE_FLOW_ITEM_TYPE_ETH,
1124         RTE_FLOW_ITEM_TYPE_IPV6,
1125         RTE_FLOW_ITEM_TYPE_SCTP,
1126         RTE_FLOW_ITEM_TYPE_RAW,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_VF,
1129         RTE_FLOW_ITEM_TYPE_END,
1130 };
1131
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133         RTE_FLOW_ITEM_TYPE_ETH,
1134         RTE_FLOW_ITEM_TYPE_IPV6,
1135         RTE_FLOW_ITEM_TYPE_SCTP,
1136         RTE_FLOW_ITEM_TYPE_RAW,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_VF,
1140         RTE_FLOW_ITEM_TYPE_END,
1141 };
1142
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144         RTE_FLOW_ITEM_TYPE_ETH,
1145         RTE_FLOW_ITEM_TYPE_VLAN,
1146         RTE_FLOW_ITEM_TYPE_VF,
1147         RTE_FLOW_ITEM_TYPE_END,
1148 };
1149
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151         RTE_FLOW_ITEM_TYPE_ETH,
1152         RTE_FLOW_ITEM_TYPE_VLAN,
1153         RTE_FLOW_ITEM_TYPE_IPV4,
1154         RTE_FLOW_ITEM_TYPE_VF,
1155         RTE_FLOW_ITEM_TYPE_END,
1156 };
1157
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159         RTE_FLOW_ITEM_TYPE_ETH,
1160         RTE_FLOW_ITEM_TYPE_VLAN,
1161         RTE_FLOW_ITEM_TYPE_IPV4,
1162         RTE_FLOW_ITEM_TYPE_UDP,
1163         RTE_FLOW_ITEM_TYPE_VF,
1164         RTE_FLOW_ITEM_TYPE_END,
1165 };
1166
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168         RTE_FLOW_ITEM_TYPE_ETH,
1169         RTE_FLOW_ITEM_TYPE_VLAN,
1170         RTE_FLOW_ITEM_TYPE_IPV4,
1171         RTE_FLOW_ITEM_TYPE_TCP,
1172         RTE_FLOW_ITEM_TYPE_VF,
1173         RTE_FLOW_ITEM_TYPE_END,
1174 };
1175
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177         RTE_FLOW_ITEM_TYPE_ETH,
1178         RTE_FLOW_ITEM_TYPE_VLAN,
1179         RTE_FLOW_ITEM_TYPE_IPV4,
1180         RTE_FLOW_ITEM_TYPE_SCTP,
1181         RTE_FLOW_ITEM_TYPE_VF,
1182         RTE_FLOW_ITEM_TYPE_END,
1183 };
1184
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186         RTE_FLOW_ITEM_TYPE_ETH,
1187         RTE_FLOW_ITEM_TYPE_VLAN,
1188         RTE_FLOW_ITEM_TYPE_IPV6,
1189         RTE_FLOW_ITEM_TYPE_VF,
1190         RTE_FLOW_ITEM_TYPE_END,
1191 };
1192
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194         RTE_FLOW_ITEM_TYPE_ETH,
1195         RTE_FLOW_ITEM_TYPE_VLAN,
1196         RTE_FLOW_ITEM_TYPE_IPV6,
1197         RTE_FLOW_ITEM_TYPE_UDP,
1198         RTE_FLOW_ITEM_TYPE_VF,
1199         RTE_FLOW_ITEM_TYPE_END,
1200 };
1201
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203         RTE_FLOW_ITEM_TYPE_ETH,
1204         RTE_FLOW_ITEM_TYPE_VLAN,
1205         RTE_FLOW_ITEM_TYPE_IPV6,
1206         RTE_FLOW_ITEM_TYPE_TCP,
1207         RTE_FLOW_ITEM_TYPE_VF,
1208         RTE_FLOW_ITEM_TYPE_END,
1209 };
1210
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212         RTE_FLOW_ITEM_TYPE_ETH,
1213         RTE_FLOW_ITEM_TYPE_VLAN,
1214         RTE_FLOW_ITEM_TYPE_IPV6,
1215         RTE_FLOW_ITEM_TYPE_SCTP,
1216         RTE_FLOW_ITEM_TYPE_VF,
1217         RTE_FLOW_ITEM_TYPE_END,
1218 };
1219
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221         RTE_FLOW_ITEM_TYPE_ETH,
1222         RTE_FLOW_ITEM_TYPE_VLAN,
1223         RTE_FLOW_ITEM_TYPE_RAW,
1224         RTE_FLOW_ITEM_TYPE_VF,
1225         RTE_FLOW_ITEM_TYPE_END,
1226 };
1227
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229         RTE_FLOW_ITEM_TYPE_ETH,
1230         RTE_FLOW_ITEM_TYPE_VLAN,
1231         RTE_FLOW_ITEM_TYPE_RAW,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_VF,
1234         RTE_FLOW_ITEM_TYPE_END,
1235 };
1236
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238         RTE_FLOW_ITEM_TYPE_ETH,
1239         RTE_FLOW_ITEM_TYPE_VLAN,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_VF,
1244         RTE_FLOW_ITEM_TYPE_END,
1245 };
1246
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248         RTE_FLOW_ITEM_TYPE_ETH,
1249         RTE_FLOW_ITEM_TYPE_VLAN,
1250         RTE_FLOW_ITEM_TYPE_IPV4,
1251         RTE_FLOW_ITEM_TYPE_RAW,
1252         RTE_FLOW_ITEM_TYPE_VF,
1253         RTE_FLOW_ITEM_TYPE_END,
1254 };
1255
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257         RTE_FLOW_ITEM_TYPE_ETH,
1258         RTE_FLOW_ITEM_TYPE_VLAN,
1259         RTE_FLOW_ITEM_TYPE_IPV4,
1260         RTE_FLOW_ITEM_TYPE_RAW,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_VF,
1263         RTE_FLOW_ITEM_TYPE_END,
1264 };
1265
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267         RTE_FLOW_ITEM_TYPE_ETH,
1268         RTE_FLOW_ITEM_TYPE_VLAN,
1269         RTE_FLOW_ITEM_TYPE_IPV4,
1270         RTE_FLOW_ITEM_TYPE_RAW,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_VF,
1274         RTE_FLOW_ITEM_TYPE_END,
1275 };
1276
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278         RTE_FLOW_ITEM_TYPE_ETH,
1279         RTE_FLOW_ITEM_TYPE_VLAN,
1280         RTE_FLOW_ITEM_TYPE_IPV4,
1281         RTE_FLOW_ITEM_TYPE_UDP,
1282         RTE_FLOW_ITEM_TYPE_RAW,
1283         RTE_FLOW_ITEM_TYPE_VF,
1284         RTE_FLOW_ITEM_TYPE_END,
1285 };
1286
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288         RTE_FLOW_ITEM_TYPE_ETH,
1289         RTE_FLOW_ITEM_TYPE_VLAN,
1290         RTE_FLOW_ITEM_TYPE_IPV4,
1291         RTE_FLOW_ITEM_TYPE_UDP,
1292         RTE_FLOW_ITEM_TYPE_RAW,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_VF,
1295         RTE_FLOW_ITEM_TYPE_END,
1296 };
1297
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299         RTE_FLOW_ITEM_TYPE_ETH,
1300         RTE_FLOW_ITEM_TYPE_VLAN,
1301         RTE_FLOW_ITEM_TYPE_IPV4,
1302         RTE_FLOW_ITEM_TYPE_UDP,
1303         RTE_FLOW_ITEM_TYPE_RAW,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_VF,
1307         RTE_FLOW_ITEM_TYPE_END,
1308 };
1309
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311         RTE_FLOW_ITEM_TYPE_ETH,
1312         RTE_FLOW_ITEM_TYPE_VLAN,
1313         RTE_FLOW_ITEM_TYPE_IPV4,
1314         RTE_FLOW_ITEM_TYPE_TCP,
1315         RTE_FLOW_ITEM_TYPE_RAW,
1316         RTE_FLOW_ITEM_TYPE_VF,
1317         RTE_FLOW_ITEM_TYPE_END,
1318 };
1319
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321         RTE_FLOW_ITEM_TYPE_ETH,
1322         RTE_FLOW_ITEM_TYPE_VLAN,
1323         RTE_FLOW_ITEM_TYPE_IPV4,
1324         RTE_FLOW_ITEM_TYPE_TCP,
1325         RTE_FLOW_ITEM_TYPE_RAW,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_VF,
1328         RTE_FLOW_ITEM_TYPE_END,
1329 };
1330
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332         RTE_FLOW_ITEM_TYPE_ETH,
1333         RTE_FLOW_ITEM_TYPE_VLAN,
1334         RTE_FLOW_ITEM_TYPE_IPV4,
1335         RTE_FLOW_ITEM_TYPE_TCP,
1336         RTE_FLOW_ITEM_TYPE_RAW,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_VF,
1340         RTE_FLOW_ITEM_TYPE_END,
1341 };
1342
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344         RTE_FLOW_ITEM_TYPE_ETH,
1345         RTE_FLOW_ITEM_TYPE_VLAN,
1346         RTE_FLOW_ITEM_TYPE_IPV4,
1347         RTE_FLOW_ITEM_TYPE_SCTP,
1348         RTE_FLOW_ITEM_TYPE_RAW,
1349         RTE_FLOW_ITEM_TYPE_VF,
1350         RTE_FLOW_ITEM_TYPE_END,
1351 };
1352
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354         RTE_FLOW_ITEM_TYPE_ETH,
1355         RTE_FLOW_ITEM_TYPE_VLAN,
1356         RTE_FLOW_ITEM_TYPE_IPV4,
1357         RTE_FLOW_ITEM_TYPE_SCTP,
1358         RTE_FLOW_ITEM_TYPE_RAW,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_VF,
1361         RTE_FLOW_ITEM_TYPE_END,
1362 };
1363
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365         RTE_FLOW_ITEM_TYPE_ETH,
1366         RTE_FLOW_ITEM_TYPE_VLAN,
1367         RTE_FLOW_ITEM_TYPE_IPV4,
1368         RTE_FLOW_ITEM_TYPE_SCTP,
1369         RTE_FLOW_ITEM_TYPE_RAW,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_VF,
1373         RTE_FLOW_ITEM_TYPE_END,
1374 };
1375
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377         RTE_FLOW_ITEM_TYPE_ETH,
1378         RTE_FLOW_ITEM_TYPE_VLAN,
1379         RTE_FLOW_ITEM_TYPE_IPV6,
1380         RTE_FLOW_ITEM_TYPE_RAW,
1381         RTE_FLOW_ITEM_TYPE_VF,
1382         RTE_FLOW_ITEM_TYPE_END,
1383 };
1384
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386         RTE_FLOW_ITEM_TYPE_ETH,
1387         RTE_FLOW_ITEM_TYPE_VLAN,
1388         RTE_FLOW_ITEM_TYPE_IPV6,
1389         RTE_FLOW_ITEM_TYPE_RAW,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_VF,
1392         RTE_FLOW_ITEM_TYPE_END,
1393 };
1394
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396         RTE_FLOW_ITEM_TYPE_ETH,
1397         RTE_FLOW_ITEM_TYPE_VLAN,
1398         RTE_FLOW_ITEM_TYPE_IPV6,
1399         RTE_FLOW_ITEM_TYPE_RAW,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_VF,
1403         RTE_FLOW_ITEM_TYPE_END,
1404 };
1405
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407         RTE_FLOW_ITEM_TYPE_ETH,
1408         RTE_FLOW_ITEM_TYPE_VLAN,
1409         RTE_FLOW_ITEM_TYPE_IPV6,
1410         RTE_FLOW_ITEM_TYPE_UDP,
1411         RTE_FLOW_ITEM_TYPE_RAW,
1412         RTE_FLOW_ITEM_TYPE_VF,
1413         RTE_FLOW_ITEM_TYPE_END,
1414 };
1415
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417         RTE_FLOW_ITEM_TYPE_ETH,
1418         RTE_FLOW_ITEM_TYPE_VLAN,
1419         RTE_FLOW_ITEM_TYPE_IPV6,
1420         RTE_FLOW_ITEM_TYPE_UDP,
1421         RTE_FLOW_ITEM_TYPE_RAW,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_VF,
1424         RTE_FLOW_ITEM_TYPE_END,
1425 };
1426
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428         RTE_FLOW_ITEM_TYPE_ETH,
1429         RTE_FLOW_ITEM_TYPE_VLAN,
1430         RTE_FLOW_ITEM_TYPE_IPV6,
1431         RTE_FLOW_ITEM_TYPE_UDP,
1432         RTE_FLOW_ITEM_TYPE_RAW,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_VF,
1436         RTE_FLOW_ITEM_TYPE_END,
1437 };
1438
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440         RTE_FLOW_ITEM_TYPE_ETH,
1441         RTE_FLOW_ITEM_TYPE_VLAN,
1442         RTE_FLOW_ITEM_TYPE_IPV6,
1443         RTE_FLOW_ITEM_TYPE_TCP,
1444         RTE_FLOW_ITEM_TYPE_RAW,
1445         RTE_FLOW_ITEM_TYPE_VF,
1446         RTE_FLOW_ITEM_TYPE_END,
1447 };
1448
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450         RTE_FLOW_ITEM_TYPE_ETH,
1451         RTE_FLOW_ITEM_TYPE_VLAN,
1452         RTE_FLOW_ITEM_TYPE_IPV6,
1453         RTE_FLOW_ITEM_TYPE_TCP,
1454         RTE_FLOW_ITEM_TYPE_RAW,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_VF,
1457         RTE_FLOW_ITEM_TYPE_END,
1458 };
1459
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461         RTE_FLOW_ITEM_TYPE_ETH,
1462         RTE_FLOW_ITEM_TYPE_VLAN,
1463         RTE_FLOW_ITEM_TYPE_IPV6,
1464         RTE_FLOW_ITEM_TYPE_TCP,
1465         RTE_FLOW_ITEM_TYPE_RAW,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_VF,
1469         RTE_FLOW_ITEM_TYPE_END,
1470 };
1471
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473         RTE_FLOW_ITEM_TYPE_ETH,
1474         RTE_FLOW_ITEM_TYPE_VLAN,
1475         RTE_FLOW_ITEM_TYPE_IPV6,
1476         RTE_FLOW_ITEM_TYPE_SCTP,
1477         RTE_FLOW_ITEM_TYPE_RAW,
1478         RTE_FLOW_ITEM_TYPE_VF,
1479         RTE_FLOW_ITEM_TYPE_END,
1480 };
1481
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483         RTE_FLOW_ITEM_TYPE_ETH,
1484         RTE_FLOW_ITEM_TYPE_VLAN,
1485         RTE_FLOW_ITEM_TYPE_IPV6,
1486         RTE_FLOW_ITEM_TYPE_SCTP,
1487         RTE_FLOW_ITEM_TYPE_RAW,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_VF,
1490         RTE_FLOW_ITEM_TYPE_END,
1491 };
1492
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494         RTE_FLOW_ITEM_TYPE_ETH,
1495         RTE_FLOW_ITEM_TYPE_VLAN,
1496         RTE_FLOW_ITEM_TYPE_IPV6,
1497         RTE_FLOW_ITEM_TYPE_SCTP,
1498         RTE_FLOW_ITEM_TYPE_RAW,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_VF,
1502         RTE_FLOW_ITEM_TYPE_END,
1503 };
1504
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507         RTE_FLOW_ITEM_TYPE_ETH,
1508         RTE_FLOW_ITEM_TYPE_IPV4,
1509         RTE_FLOW_ITEM_TYPE_UDP,
1510         RTE_FLOW_ITEM_TYPE_VXLAN,
1511         RTE_FLOW_ITEM_TYPE_ETH,
1512         RTE_FLOW_ITEM_TYPE_END,
1513 };
1514
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516         RTE_FLOW_ITEM_TYPE_ETH,
1517         RTE_FLOW_ITEM_TYPE_IPV6,
1518         RTE_FLOW_ITEM_TYPE_UDP,
1519         RTE_FLOW_ITEM_TYPE_VXLAN,
1520         RTE_FLOW_ITEM_TYPE_ETH,
1521         RTE_FLOW_ITEM_TYPE_END,
1522 };
1523
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525         RTE_FLOW_ITEM_TYPE_ETH,
1526         RTE_FLOW_ITEM_TYPE_IPV4,
1527         RTE_FLOW_ITEM_TYPE_UDP,
1528         RTE_FLOW_ITEM_TYPE_VXLAN,
1529         RTE_FLOW_ITEM_TYPE_ETH,
1530         RTE_FLOW_ITEM_TYPE_VLAN,
1531         RTE_FLOW_ITEM_TYPE_END,
1532 };
1533
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535         RTE_FLOW_ITEM_TYPE_ETH,
1536         RTE_FLOW_ITEM_TYPE_IPV6,
1537         RTE_FLOW_ITEM_TYPE_UDP,
1538         RTE_FLOW_ITEM_TYPE_VXLAN,
1539         RTE_FLOW_ITEM_TYPE_ETH,
1540         RTE_FLOW_ITEM_TYPE_VLAN,
1541         RTE_FLOW_ITEM_TYPE_END,
1542 };
1543
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545         RTE_FLOW_ITEM_TYPE_ETH,
1546         RTE_FLOW_ITEM_TYPE_IPV4,
1547         RTE_FLOW_ITEM_TYPE_NVGRE,
1548         RTE_FLOW_ITEM_TYPE_ETH,
1549         RTE_FLOW_ITEM_TYPE_END,
1550 };
1551
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553         RTE_FLOW_ITEM_TYPE_ETH,
1554         RTE_FLOW_ITEM_TYPE_IPV6,
1555         RTE_FLOW_ITEM_TYPE_NVGRE,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_END,
1558 };
1559
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561         RTE_FLOW_ITEM_TYPE_ETH,
1562         RTE_FLOW_ITEM_TYPE_IPV4,
1563         RTE_FLOW_ITEM_TYPE_NVGRE,
1564         RTE_FLOW_ITEM_TYPE_ETH,
1565         RTE_FLOW_ITEM_TYPE_VLAN,
1566         RTE_FLOW_ITEM_TYPE_END,
1567 };
1568
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570         RTE_FLOW_ITEM_TYPE_ETH,
1571         RTE_FLOW_ITEM_TYPE_IPV6,
1572         RTE_FLOW_ITEM_TYPE_NVGRE,
1573         RTE_FLOW_ITEM_TYPE_ETH,
1574         RTE_FLOW_ITEM_TYPE_VLAN,
1575         RTE_FLOW_ITEM_TYPE_END,
1576 };
1577
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579         RTE_FLOW_ITEM_TYPE_ETH,
1580         RTE_FLOW_ITEM_TYPE_IPV4,
1581         RTE_FLOW_ITEM_TYPE_UDP,
1582         RTE_FLOW_ITEM_TYPE_MPLS,
1583         RTE_FLOW_ITEM_TYPE_END,
1584 };
1585
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587         RTE_FLOW_ITEM_TYPE_ETH,
1588         RTE_FLOW_ITEM_TYPE_IPV6,
1589         RTE_FLOW_ITEM_TYPE_UDP,
1590         RTE_FLOW_ITEM_TYPE_MPLS,
1591         RTE_FLOW_ITEM_TYPE_END,
1592 };
1593
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595         RTE_FLOW_ITEM_TYPE_ETH,
1596         RTE_FLOW_ITEM_TYPE_IPV4,
1597         RTE_FLOW_ITEM_TYPE_GRE,
1598         RTE_FLOW_ITEM_TYPE_MPLS,
1599         RTE_FLOW_ITEM_TYPE_END,
1600 };
1601
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603         RTE_FLOW_ITEM_TYPE_ETH,
1604         RTE_FLOW_ITEM_TYPE_IPV6,
1605         RTE_FLOW_ITEM_TYPE_GRE,
1606         RTE_FLOW_ITEM_TYPE_MPLS,
1607         RTE_FLOW_ITEM_TYPE_END,
1608 };
1609
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611         RTE_FLOW_ITEM_TYPE_ETH,
1612         RTE_FLOW_ITEM_TYPE_VLAN,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_END,
1615 };
1616
1617 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1618         /* Ethertype */
1619         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1620         /* FDIR - support default flow type without flexible payload*/
1621         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1622         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1638         /* FDIR - support default flow type with flexible payload */
1639         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1640         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1666         /* FDIR - support single vlan input set */
1667         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1703         /* FDIR - support VF item */
1704         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1775         /* VXLAN */
1776         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1777         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1780         /* NVGRE */
1781         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1782         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1785         /* MPLSoUDP & MPLSoGRE */
1786         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1787         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1790         /* GTP-C & GTP-U */
1791         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1792         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1795         /* QINQ */
1796         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1797 };
1798
1799 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1800         do {                                                            \
1801                 act = actions + index;                                  \
1802                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1803                         index++;                                        \
1804                         act = actions + index;                          \
1805                 }                                                       \
1806         } while (0)
1807
1808 /* Find the first VOID or non-VOID item pointer */
1809 static const struct rte_flow_item *
1810 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1811 {
1812         bool is_find;
1813
1814         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1815                 if (is_void)
1816                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1817                 else
1818                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1819                 if (is_find)
1820                         break;
1821                 item++;
1822         }
1823         return item;
1824 }
1825
1826 /* Skip all VOID items of the pattern */
1827 static void
1828 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1829                             const struct rte_flow_item *pattern)
1830 {
1831         uint32_t cpy_count = 0;
1832         const struct rte_flow_item *pb = pattern, *pe = pattern;
1833
1834         for (;;) {
1835                 /* Find a non-void item first */
1836                 pb = i40e_find_first_item(pb, false);
1837                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1838                         pe = pb;
1839                         break;
1840                 }
1841
1842                 /* Find a void item */
1843                 pe = i40e_find_first_item(pb + 1, true);
1844
1845                 cpy_count = pe - pb;
1846                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1847
1848                 items += cpy_count;
1849
1850                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1851                         pb = pe;
1852                         break;
1853                 }
1854
1855                 pb = pe + 1;
1856         }
1857         /* Copy the END item. */
1858         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1859 }
1860
1861 /* Check if the pattern matches a supported item type array */
1862 static bool
1863 i40e_match_pattern(enum rte_flow_item_type *item_array,
1864                    struct rte_flow_item *pattern)
1865 {
1866         struct rte_flow_item *item = pattern;
1867
1868         while ((*item_array == item->type) &&
1869                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1870                 item_array++;
1871                 item++;
1872         }
1873
1874         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1875                 item->type == RTE_FLOW_ITEM_TYPE_END);
1876 }
1877
1878 /* Find if there's parse filter function matched */
1879 static parse_filter_t
1880 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1881 {
1882         parse_filter_t parse_filter = NULL;
1883         uint8_t i = *idx;
1884
1885         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1886                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1887                                         pattern)) {
1888                         parse_filter = i40e_supported_patterns[i].parse_filter;
1889                         break;
1890                 }
1891         }
1892
1893         *idx = ++i;
1894
1895         return parse_filter;
1896 }
1897
1898 /* Parse attributes */
1899 static int
1900 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1901                      struct rte_flow_error *error)
1902 {
1903         /* Must be input direction */
1904         if (!attr->ingress) {
1905                 rte_flow_error_set(error, EINVAL,
1906                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1907                                    attr, "Only support ingress.");
1908                 return -rte_errno;
1909         }
1910
1911         /* Not supported */
1912         if (attr->egress) {
1913                 rte_flow_error_set(error, EINVAL,
1914                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1915                                    attr, "Not support egress.");
1916                 return -rte_errno;
1917         }
1918
1919         /* Not supported */
1920         if (attr->priority) {
1921                 rte_flow_error_set(error, EINVAL,
1922                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1923                                    attr, "Not support priority.");
1924                 return -rte_errno;
1925         }
1926
1927         /* Not supported */
1928         if (attr->group) {
1929                 rte_flow_error_set(error, EINVAL,
1930                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1931                                    attr, "Not support group.");
1932                 return -rte_errno;
1933         }
1934
1935         return 0;
1936 }
1937
1938 static uint16_t
1939 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         int qinq = dev->data->dev_conf.rxmode.offloads &
1943                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1944         uint64_t reg_r = 0;
1945         uint16_t reg_id;
1946         uint16_t tpid;
1947
1948         if (qinq)
1949                 reg_id = 2;
1950         else
1951                 reg_id = 3;
1952
1953         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1954                                     &reg_r, NULL);
1955
1956         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1957
1958         return tpid;
1959 }
1960
1961 /* 1. Last in item should be NULL as range is not supported.
1962  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1963  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1964  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1965  *    FF:FF:FF:FF:FF:FF
1966  * 5. Ether_type mask should be 0xFFFF.
1967  */
1968 static int
1969 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1970                                   const struct rte_flow_item *pattern,
1971                                   struct rte_flow_error *error,
1972                                   struct rte_eth_ethertype_filter *filter)
1973 {
1974         const struct rte_flow_item *item = pattern;
1975         const struct rte_flow_item_eth *eth_spec;
1976         const struct rte_flow_item_eth *eth_mask;
1977         enum rte_flow_item_type item_type;
1978         uint16_t outer_tpid;
1979
1980         outer_tpid = i40e_get_outer_vlan(dev);
1981
1982         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1983                 if (item->last) {
1984                         rte_flow_error_set(error, EINVAL,
1985                                            RTE_FLOW_ERROR_TYPE_ITEM,
1986                                            item,
1987                                            "Not support range");
1988                         return -rte_errno;
1989                 }
1990                 item_type = item->type;
1991                 switch (item_type) {
1992                 case RTE_FLOW_ITEM_TYPE_ETH:
1993                         eth_spec = item->spec;
1994                         eth_mask = item->mask;
1995                         /* Get the MAC info. */
1996                         if (!eth_spec || !eth_mask) {
1997                                 rte_flow_error_set(error, EINVAL,
1998                                                    RTE_FLOW_ERROR_TYPE_ITEM,
1999                                                    item,
2000                                                    "NULL ETH spec/mask");
2001                                 return -rte_errno;
2002                         }
2003
2004                         /* Mask bits of source MAC address must be full of 0.
2005                          * Mask bits of destination MAC address must be full
2006                          * of 1 or full of 0.
2007                          */
2008                         if (!is_zero_ether_addr(&eth_mask->src) ||
2009                             (!is_zero_ether_addr(&eth_mask->dst) &&
2010                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2011                                 rte_flow_error_set(error, EINVAL,
2012                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2013                                                    item,
2014                                                    "Invalid MAC_addr mask");
2015                                 return -rte_errno;
2016                         }
2017
2018                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2019                                 rte_flow_error_set(error, EINVAL,
2020                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2021                                                    item,
2022                                                    "Invalid ethertype mask");
2023                                 return -rte_errno;
2024                         }
2025
2026                         /* If mask bits of destination MAC address
2027                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2028                          */
2029                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2030                                 filter->mac_addr = eth_spec->dst;
2031                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2032                         } else {
2033                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2034                         }
2035                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2036
2037                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2038                             filter->ether_type == ETHER_TYPE_IPv6 ||
2039                             filter->ether_type == ETHER_TYPE_LLDP ||
2040                             filter->ether_type == outer_tpid) {
2041                                 rte_flow_error_set(error, EINVAL,
2042                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2043                                                    item,
2044                                                    "Unsupported ether_type in"
2045                                                    " control packet filter.");
2046                                 return -rte_errno;
2047                         }
2048                         break;
2049                 default:
2050                         break;
2051                 }
2052         }
2053
2054         return 0;
2055 }
2056
2057 /* Ethertype action only supports QUEUE or DROP. */
2058 static int
2059 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2060                                  const struct rte_flow_action *actions,
2061                                  struct rte_flow_error *error,
2062                                  struct rte_eth_ethertype_filter *filter)
2063 {
2064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2065         const struct rte_flow_action *act;
2066         const struct rte_flow_action_queue *act_q;
2067         uint32_t index = 0;
2068
2069         /* Check if the first non-void action is QUEUE or DROP. */
2070         NEXT_ITEM_OF_ACTION(act, actions, index);
2071         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2072             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2073                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2074                                    act, "Not supported action.");
2075                 return -rte_errno;
2076         }
2077
2078         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2079                 act_q = act->conf;
2080                 filter->queue = act_q->index;
2081                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2082                         rte_flow_error_set(error, EINVAL,
2083                                            RTE_FLOW_ERROR_TYPE_ACTION,
2084                                            act, "Invalid queue ID for"
2085                                            " ethertype_filter.");
2086                         return -rte_errno;
2087                 }
2088         } else {
2089                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2090         }
2091
2092         /* Check if the next non-void item is END */
2093         index++;
2094         NEXT_ITEM_OF_ACTION(act, actions, index);
2095         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2096                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2097                                    act, "Not supported action.");
2098                 return -rte_errno;
2099         }
2100
2101         return 0;
2102 }
2103
2104 static int
2105 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2106                                  const struct rte_flow_attr *attr,
2107                                  const struct rte_flow_item pattern[],
2108                                  const struct rte_flow_action actions[],
2109                                  struct rte_flow_error *error,
2110                                  union i40e_filter_t *filter)
2111 {
2112         struct rte_eth_ethertype_filter *ethertype_filter =
2113                 &filter->ethertype_filter;
2114         int ret;
2115
2116         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2117                                                 ethertype_filter);
2118         if (ret)
2119                 return ret;
2120
2121         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2122                                                ethertype_filter);
2123         if (ret)
2124                 return ret;
2125
2126         ret = i40e_flow_parse_attr(attr, error);
2127         if (ret)
2128                 return ret;
2129
2130         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2131
2132         return ret;
2133 }
2134
2135 static int
2136 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2137                          const struct rte_flow_item_raw *raw_spec,
2138                          struct rte_flow_error *error)
2139 {
2140         if (!raw_spec->relative) {
2141                 rte_flow_error_set(error, EINVAL,
2142                                    RTE_FLOW_ERROR_TYPE_ITEM,
2143                                    item,
2144                                    "Relative should be 1.");
2145                 return -rte_errno;
2146         }
2147
2148         if (raw_spec->offset % sizeof(uint16_t)) {
2149                 rte_flow_error_set(error, EINVAL,
2150                                    RTE_FLOW_ERROR_TYPE_ITEM,
2151                                    item,
2152                                    "Offset should be even.");
2153                 return -rte_errno;
2154         }
2155
2156         if (raw_spec->search || raw_spec->limit) {
2157                 rte_flow_error_set(error, EINVAL,
2158                                    RTE_FLOW_ERROR_TYPE_ITEM,
2159                                    item,
2160                                    "search or limit is not supported.");
2161                 return -rte_errno;
2162         }
2163
2164         if (raw_spec->offset < 0) {
2165                 rte_flow_error_set(error, EINVAL,
2166                                    RTE_FLOW_ERROR_TYPE_ITEM,
2167                                    item,
2168                                    "Offset should be non-negative.");
2169                 return -rte_errno;
2170         }
2171         return 0;
2172 }
2173
2174 static int
2175 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2176                          struct i40e_fdir_flex_pit *flex_pit,
2177                          enum i40e_flxpld_layer_idx layer_idx,
2178                          uint8_t raw_id)
2179 {
2180         uint8_t field_idx;
2181
2182         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2183         /* Check if the configuration is conflicted */
2184         if (pf->fdir.flex_pit_flag[layer_idx] &&
2185             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2186              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2187              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2188                 return -1;
2189
2190         /* Check if the configuration exists. */
2191         if (pf->fdir.flex_pit_flag[layer_idx] &&
2192             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2193              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2194              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2195                 return 1;
2196
2197         pf->fdir.flex_set[field_idx].src_offset =
2198                 flex_pit->src_offset;
2199         pf->fdir.flex_set[field_idx].size =
2200                 flex_pit->size;
2201         pf->fdir.flex_set[field_idx].dst_offset =
2202                 flex_pit->dst_offset;
2203
2204         return 0;
2205 }
2206
2207 static int
2208 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2209                           enum i40e_filter_pctype pctype,
2210                           uint8_t *mask)
2211 {
2212         struct i40e_fdir_flex_mask flex_mask;
2213         uint16_t mask_tmp;
2214         uint8_t i, nb_bitmask = 0;
2215
2216         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2217         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2218                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2219                 if (mask_tmp) {
2220                         flex_mask.word_mask |=
2221                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2222                         if (mask_tmp != UINT16_MAX) {
2223                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2224                                 flex_mask.bitmask[nb_bitmask].offset =
2225                                         i / sizeof(uint16_t);
2226                                 nb_bitmask++;
2227                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2228                                         return -1;
2229                         }
2230                 }
2231         }
2232         flex_mask.nb_bitmask = nb_bitmask;
2233
2234         if (pf->fdir.flex_mask_flag[pctype] &&
2235             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2236                     sizeof(struct i40e_fdir_flex_mask))))
2237                 return -2;
2238         else if (pf->fdir.flex_mask_flag[pctype] &&
2239                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2240                           sizeof(struct i40e_fdir_flex_mask))))
2241                 return 1;
2242
2243         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2244                sizeof(struct i40e_fdir_flex_mask));
2245         return 0;
2246 }
2247
2248 static void
2249 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2250                             enum i40e_flxpld_layer_idx layer_idx,
2251                             uint8_t raw_id)
2252 {
2253         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2254         uint32_t flx_pit, flx_ort;
2255         uint8_t field_idx;
2256         uint16_t min_next_off = 0;  /* in words */
2257         uint8_t i;
2258
2259         if (raw_id) {
2260                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2261                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2262                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2263                 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2264                 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
2265         }
2266
2267         /* Set flex pit */
2268         for (i = 0; i < raw_id; i++) {
2269                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2270                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2271                                      pf->fdir.flex_set[field_idx].size,
2272                                      pf->fdir.flex_set[field_idx].dst_offset);
2273
2274                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2275                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2276                         pf->fdir.flex_set[field_idx].size;
2277         }
2278
2279         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2280                 /* set the non-used register obeying register's constrain */
2281                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2282                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2283                                      NONUSE_FLX_PIT_DEST_OFF);
2284                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2285                 min_next_off++;
2286         }
2287
2288         pf->fdir.flex_pit_flag[layer_idx] = 1;
2289 }
2290
2291 static void
2292 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2293                             enum i40e_filter_pctype pctype)
2294 {
2295         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2296         struct i40e_fdir_flex_mask *flex_mask;
2297         uint32_t flxinset, fd_mask;
2298         uint8_t i;
2299
2300         /* Set flex mask */
2301         flex_mask = &pf->fdir.flex_mask[pctype];
2302         flxinset = (flex_mask->word_mask <<
2303                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2304                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2305         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2306
2307         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2308                 fd_mask = (flex_mask->bitmask[i].mask <<
2309                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2310                         I40E_PRTQF_FD_MSK_MASK_MASK;
2311                 fd_mask |= ((flex_mask->bitmask[i].offset +
2312                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2313                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2314                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2315                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2316         }
2317
2318         pf->fdir.flex_mask_flag[pctype] = 1;
2319 }
2320
2321 static int
2322 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2323                          enum i40e_filter_pctype pctype,
2324                          uint64_t input_set)
2325 {
2326         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2327         uint64_t inset_reg = 0;
2328         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2329         int i, num;
2330
2331         /* Check if the input set is valid */
2332         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2333                                     input_set) != 0) {
2334                 PMD_DRV_LOG(ERR, "Invalid input set");
2335                 return -EINVAL;
2336         }
2337
2338         /* Check if the configuration is conflicted */
2339         if (pf->fdir.inset_flag[pctype] &&
2340             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2341                 return -1;
2342
2343         if (pf->fdir.inset_flag[pctype] &&
2344             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2345                 return 0;
2346
2347         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2348                                            I40E_INSET_MASK_NUM_REG);
2349         if (num < 0)
2350                 return -EINVAL;
2351
2352         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2353
2354         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2355                              (uint32_t)(inset_reg & UINT32_MAX));
2356         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2357                              (uint32_t)((inset_reg >>
2358                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2359
2360         for (i = 0; i < num; i++)
2361                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2362                                      mask_reg[i]);
2363
2364         /*clear unused mask registers of the pctype */
2365         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2366                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2367         I40E_WRITE_FLUSH(hw);
2368
2369         pf->fdir.input_set[pctype] = input_set;
2370         pf->fdir.inset_flag[pctype] = 1;
2371         return 0;
2372 }
2373
2374 static uint8_t
2375 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2376                                 enum rte_flow_item_type item_type,
2377                                 struct i40e_fdir_filter_conf *filter)
2378 {
2379         struct i40e_customized_pctype *cus_pctype = NULL;
2380
2381         switch (item_type) {
2382         case RTE_FLOW_ITEM_TYPE_GTPC:
2383                 cus_pctype = i40e_find_customized_pctype(pf,
2384                                                          I40E_CUSTOMIZED_GTPC);
2385                 break;
2386         case RTE_FLOW_ITEM_TYPE_GTPU:
2387                 if (!filter->input.flow_ext.inner_ip)
2388                         cus_pctype = i40e_find_customized_pctype(pf,
2389                                                          I40E_CUSTOMIZED_GTPU);
2390                 else if (filter->input.flow_ext.iip_type ==
2391                          I40E_FDIR_IPTYPE_IPV4)
2392                         cus_pctype = i40e_find_customized_pctype(pf,
2393                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2394                 else if (filter->input.flow_ext.iip_type ==
2395                          I40E_FDIR_IPTYPE_IPV6)
2396                         cus_pctype = i40e_find_customized_pctype(pf,
2397                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2398                 break;
2399         default:
2400                 PMD_DRV_LOG(ERR, "Unsupported item type");
2401                 break;
2402         }
2403
2404         if (cus_pctype)
2405                 return cus_pctype->pctype;
2406
2407         return I40E_FILTER_PCTYPE_INVALID;
2408 }
2409
2410 /* 1. Last in item should be NULL as range is not supported.
2411  * 2. Supported patterns: refer to array i40e_supported_patterns.
2412  * 3. Default supported flow type and input set: refer to array
2413  *    valid_fdir_inset_table in i40e_ethdev.c.
2414  * 4. Mask of fields which need to be matched should be
2415  *    filled with 1.
2416  * 5. Mask of fields which needn't to be matched should be
2417  *    filled with 0.
2418  * 6. GTP profile supports GTPv1 only.
2419  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2420  */
2421 static int
2422 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2423                              const struct rte_flow_item *pattern,
2424                              struct rte_flow_error *error,
2425                              struct i40e_fdir_filter_conf *filter)
2426 {
2427         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2428         const struct rte_flow_item *item = pattern;
2429         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2430         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2431         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2432         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2433         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2434         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2435         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2436         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2437         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2438         const struct rte_flow_item_vf *vf_spec;
2439
2440         uint8_t pctype = 0;
2441         uint64_t input_set = I40E_INSET_NONE;
2442         uint16_t frag_off;
2443         enum rte_flow_item_type item_type;
2444         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2445         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2446         uint32_t i, j;
2447         uint8_t  ipv6_addr_mask[16] = {
2448                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2449                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2450         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2451         uint8_t raw_id = 0;
2452         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2453         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2454         struct i40e_fdir_flex_pit flex_pit;
2455         uint8_t next_dst_off = 0;
2456         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2457         uint16_t flex_size;
2458         bool cfg_flex_pit = true;
2459         bool cfg_flex_msk = true;
2460         uint16_t outer_tpid;
2461         uint16_t ether_type;
2462         uint32_t vtc_flow_cpu;
2463         bool outer_ip = true;
2464         int ret;
2465
2466         memset(off_arr, 0, sizeof(off_arr));
2467         memset(len_arr, 0, sizeof(len_arr));
2468         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2469         outer_tpid = i40e_get_outer_vlan(dev);
2470         filter->input.flow_ext.customized_pctype = false;
2471         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2472                 if (item->last) {
2473                         rte_flow_error_set(error, EINVAL,
2474                                            RTE_FLOW_ERROR_TYPE_ITEM,
2475                                            item,
2476                                            "Not support range");
2477                         return -rte_errno;
2478                 }
2479                 item_type = item->type;
2480                 switch (item_type) {
2481                 case RTE_FLOW_ITEM_TYPE_ETH:
2482                         eth_spec = item->spec;
2483                         eth_mask = item->mask;
2484
2485                         if (eth_spec && eth_mask) {
2486                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2487                                     !is_zero_ether_addr(&eth_mask->dst)) {
2488                                         rte_flow_error_set(error, EINVAL,
2489                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2490                                                       item,
2491                                                       "Invalid MAC_addr mask.");
2492                                         return -rte_errno;
2493                                 }
2494
2495                                 if ((eth_mask->type & UINT16_MAX) ==
2496                                     UINT16_MAX) {
2497                                         input_set |= I40E_INSET_LAST_ETHER_TYPE;
2498                                         filter->input.flow.l2_flow.ether_type =
2499                                                 eth_spec->type;
2500                                 }
2501
2502                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2503                                 if (ether_type == ETHER_TYPE_IPv4 ||
2504                                     ether_type == ETHER_TYPE_IPv6 ||
2505                                     ether_type == ETHER_TYPE_ARP ||
2506                                     ether_type == outer_tpid) {
2507                                         rte_flow_error_set(error, EINVAL,
2508                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2509                                                      item,
2510                                                      "Unsupported ether_type.");
2511                                         return -rte_errno;
2512                                 }
2513                         }
2514
2515                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2516                         layer_idx = I40E_FLXPLD_L2_IDX;
2517
2518                         break;
2519                 case RTE_FLOW_ITEM_TYPE_VLAN:
2520                         vlan_spec = item->spec;
2521                         vlan_mask = item->mask;
2522                         if (vlan_spec && vlan_mask) {
2523                                 if (vlan_mask->tci ==
2524                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2525                                         input_set |= I40E_INSET_VLAN_INNER;
2526                                         filter->input.flow_ext.vlan_tci =
2527                                                 vlan_spec->tci;
2528                                 }
2529                         }
2530
2531                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2532                         layer_idx = I40E_FLXPLD_L2_IDX;
2533
2534                         break;
2535                 case RTE_FLOW_ITEM_TYPE_IPV4:
2536                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2537                         ipv4_spec = item->spec;
2538                         ipv4_mask = item->mask;
2539                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2540                         layer_idx = I40E_FLXPLD_L3_IDX;
2541
2542                         if (ipv4_spec && ipv4_mask && outer_ip) {
2543                                 /* Check IPv4 mask and update input set */
2544                                 if (ipv4_mask->hdr.version_ihl ||
2545                                     ipv4_mask->hdr.total_length ||
2546                                     ipv4_mask->hdr.packet_id ||
2547                                     ipv4_mask->hdr.fragment_offset ||
2548                                     ipv4_mask->hdr.hdr_checksum) {
2549                                         rte_flow_error_set(error, EINVAL,
2550                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2551                                                    item,
2552                                                    "Invalid IPv4 mask.");
2553                                         return -rte_errno;
2554                                 }
2555
2556                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2557                                         input_set |= I40E_INSET_IPV4_SRC;
2558                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2559                                         input_set |= I40E_INSET_IPV4_DST;
2560                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2561                                         input_set |= I40E_INSET_IPV4_TOS;
2562                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2563                                         input_set |= I40E_INSET_IPV4_TTL;
2564                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2565                                         input_set |= I40E_INSET_IPV4_PROTO;
2566
2567                                 /* Check if it is fragment. */
2568                                 frag_off = ipv4_spec->hdr.fragment_offset;
2569                                 frag_off = rte_be_to_cpu_16(frag_off);
2570                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2571                                     frag_off & IPV4_HDR_MF_FLAG)
2572                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2573
2574                                 /* Get the filter info */
2575                                 filter->input.flow.ip4_flow.proto =
2576                                         ipv4_spec->hdr.next_proto_id;
2577                                 filter->input.flow.ip4_flow.tos =
2578                                         ipv4_spec->hdr.type_of_service;
2579                                 filter->input.flow.ip4_flow.ttl =
2580                                         ipv4_spec->hdr.time_to_live;
2581                                 filter->input.flow.ip4_flow.src_ip =
2582                                         ipv4_spec->hdr.src_addr;
2583                                 filter->input.flow.ip4_flow.dst_ip =
2584                                         ipv4_spec->hdr.dst_addr;
2585                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2586                                 filter->input.flow_ext.inner_ip = true;
2587                                 filter->input.flow_ext.iip_type =
2588                                         I40E_FDIR_IPTYPE_IPV4;
2589                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2590                                 rte_flow_error_set(error, EINVAL,
2591                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2592                                                    item,
2593                                                    "Invalid inner IPv4 mask.");
2594                                 return -rte_errno;
2595                         }
2596
2597                         if (outer_ip)
2598                                 outer_ip = false;
2599
2600                         break;
2601                 case RTE_FLOW_ITEM_TYPE_IPV6:
2602                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2603                         ipv6_spec = item->spec;
2604                         ipv6_mask = item->mask;
2605                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2606                         layer_idx = I40E_FLXPLD_L3_IDX;
2607
2608                         if (ipv6_spec && ipv6_mask && outer_ip) {
2609                                 /* Check IPv6 mask and update input set */
2610                                 if (ipv6_mask->hdr.payload_len) {
2611                                         rte_flow_error_set(error, EINVAL,
2612                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2613                                                    item,
2614                                                    "Invalid IPv6 mask");
2615                                         return -rte_errno;
2616                                 }
2617
2618                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2619                                             ipv6_addr_mask,
2620                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2621                                         input_set |= I40E_INSET_IPV6_SRC;
2622                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2623                                             ipv6_addr_mask,
2624                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2625                                         input_set |= I40E_INSET_IPV6_DST;
2626
2627                                 if ((ipv6_mask->hdr.vtc_flow &
2628                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2629                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2630                                         input_set |= I40E_INSET_IPV6_TC;
2631                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2632                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2633                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2634                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2635
2636                                 /* Get filter info */
2637                                 vtc_flow_cpu =
2638                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2639                                 filter->input.flow.ipv6_flow.tc =
2640                                         (uint8_t)(vtc_flow_cpu >>
2641                                                   I40E_FDIR_IPv6_TC_OFFSET);
2642                                 filter->input.flow.ipv6_flow.proto =
2643                                         ipv6_spec->hdr.proto;
2644                                 filter->input.flow.ipv6_flow.hop_limits =
2645                                         ipv6_spec->hdr.hop_limits;
2646
2647                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2648                                            ipv6_spec->hdr.src_addr, 16);
2649                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2650                                            ipv6_spec->hdr.dst_addr, 16);
2651
2652                                 /* Check if it is fragment. */
2653                                 if (ipv6_spec->hdr.proto ==
2654                                     I40E_IPV6_FRAG_HEADER)
2655                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2656                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2657                                 filter->input.flow_ext.inner_ip = true;
2658                                 filter->input.flow_ext.iip_type =
2659                                         I40E_FDIR_IPTYPE_IPV6;
2660                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2661                                 rte_flow_error_set(error, EINVAL,
2662                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2663                                                    item,
2664                                                    "Invalid inner IPv6 mask");
2665                                 return -rte_errno;
2666                         }
2667
2668                         if (outer_ip)
2669                                 outer_ip = false;
2670                         break;
2671                 case RTE_FLOW_ITEM_TYPE_TCP:
2672                         tcp_spec = item->spec;
2673                         tcp_mask = item->mask;
2674
2675                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2676                                 pctype =
2677                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2678                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2679                                 pctype =
2680                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2681                         if (tcp_spec && tcp_mask) {
2682                                 /* Check TCP mask and update input set */
2683                                 if (tcp_mask->hdr.sent_seq ||
2684                                     tcp_mask->hdr.recv_ack ||
2685                                     tcp_mask->hdr.data_off ||
2686                                     tcp_mask->hdr.tcp_flags ||
2687                                     tcp_mask->hdr.rx_win ||
2688                                     tcp_mask->hdr.cksum ||
2689                                     tcp_mask->hdr.tcp_urp) {
2690                                         rte_flow_error_set(error, EINVAL,
2691                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2692                                                    item,
2693                                                    "Invalid TCP mask");
2694                                         return -rte_errno;
2695                                 }
2696
2697                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2698                                         input_set |= I40E_INSET_SRC_PORT;
2699                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2700                                         input_set |= I40E_INSET_DST_PORT;
2701
2702                                 /* Get filter info */
2703                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2704                                         filter->input.flow.tcp4_flow.src_port =
2705                                                 tcp_spec->hdr.src_port;
2706                                         filter->input.flow.tcp4_flow.dst_port =
2707                                                 tcp_spec->hdr.dst_port;
2708                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2709                                         filter->input.flow.tcp6_flow.src_port =
2710                                                 tcp_spec->hdr.src_port;
2711                                         filter->input.flow.tcp6_flow.dst_port =
2712                                                 tcp_spec->hdr.dst_port;
2713                                 }
2714                         }
2715
2716                         layer_idx = I40E_FLXPLD_L4_IDX;
2717
2718                         break;
2719                 case RTE_FLOW_ITEM_TYPE_UDP:
2720                         udp_spec = item->spec;
2721                         udp_mask = item->mask;
2722
2723                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2724                                 pctype =
2725                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2726                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2727                                 pctype =
2728                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2729
2730                         if (udp_spec && udp_mask) {
2731                                 /* Check UDP mask and update input set*/
2732                                 if (udp_mask->hdr.dgram_len ||
2733                                     udp_mask->hdr.dgram_cksum) {
2734                                         rte_flow_error_set(error, EINVAL,
2735                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2736                                                    item,
2737                                                    "Invalid UDP mask");
2738                                         return -rte_errno;
2739                                 }
2740
2741                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2742                                         input_set |= I40E_INSET_SRC_PORT;
2743                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2744                                         input_set |= I40E_INSET_DST_PORT;
2745
2746                                 /* Get filter info */
2747                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2748                                         filter->input.flow.udp4_flow.src_port =
2749                                                 udp_spec->hdr.src_port;
2750                                         filter->input.flow.udp4_flow.dst_port =
2751                                                 udp_spec->hdr.dst_port;
2752                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2753                                         filter->input.flow.udp6_flow.src_port =
2754                                                 udp_spec->hdr.src_port;
2755                                         filter->input.flow.udp6_flow.dst_port =
2756                                                 udp_spec->hdr.dst_port;
2757                                 }
2758                         }
2759
2760                         layer_idx = I40E_FLXPLD_L4_IDX;
2761
2762                         break;
2763                 case RTE_FLOW_ITEM_TYPE_GTPC:
2764                 case RTE_FLOW_ITEM_TYPE_GTPU:
2765                         if (!pf->gtp_support) {
2766                                 rte_flow_error_set(error, EINVAL,
2767                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2768                                                    item,
2769                                                    "Unsupported protocol");
2770                                 return -rte_errno;
2771                         }
2772
2773                         gtp_spec = item->spec;
2774                         gtp_mask = item->mask;
2775
2776                         if (gtp_spec && gtp_mask) {
2777                                 if (gtp_mask->v_pt_rsv_flags ||
2778                                     gtp_mask->msg_type ||
2779                                     gtp_mask->msg_len ||
2780                                     gtp_mask->teid != UINT32_MAX) {
2781                                         rte_flow_error_set(error, EINVAL,
2782                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2783                                                    item,
2784                                                    "Invalid GTP mask");
2785                                         return -rte_errno;
2786                                 }
2787
2788                                 filter->input.flow.gtp_flow.teid =
2789                                         gtp_spec->teid;
2790                                 filter->input.flow_ext.customized_pctype = true;
2791                                 cus_proto = item_type;
2792                         }
2793                         break;
2794                 case RTE_FLOW_ITEM_TYPE_SCTP:
2795                         sctp_spec = item->spec;
2796                         sctp_mask = item->mask;
2797
2798                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2799                                 pctype =
2800                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2801                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2802                                 pctype =
2803                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2804
2805                         if (sctp_spec && sctp_mask) {
2806                                 /* Check SCTP mask and update input set */
2807                                 if (sctp_mask->hdr.cksum) {
2808                                         rte_flow_error_set(error, EINVAL,
2809                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2810                                                    item,
2811                                                    "Invalid UDP mask");
2812                                         return -rte_errno;
2813                                 }
2814
2815                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2816                                         input_set |= I40E_INSET_SRC_PORT;
2817                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2818                                         input_set |= I40E_INSET_DST_PORT;
2819                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2820                                         input_set |= I40E_INSET_SCTP_VT;
2821
2822                                 /* Get filter info */
2823                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2824                                         filter->input.flow.sctp4_flow.src_port =
2825                                                 sctp_spec->hdr.src_port;
2826                                         filter->input.flow.sctp4_flow.dst_port =
2827                                                 sctp_spec->hdr.dst_port;
2828                                         filter->input.flow.sctp4_flow.verify_tag
2829                                                 = sctp_spec->hdr.tag;
2830                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2831                                         filter->input.flow.sctp6_flow.src_port =
2832                                                 sctp_spec->hdr.src_port;
2833                                         filter->input.flow.sctp6_flow.dst_port =
2834                                                 sctp_spec->hdr.dst_port;
2835                                         filter->input.flow.sctp6_flow.verify_tag
2836                                                 = sctp_spec->hdr.tag;
2837                                 }
2838                         }
2839
2840                         layer_idx = I40E_FLXPLD_L4_IDX;
2841
2842                         break;
2843                 case RTE_FLOW_ITEM_TYPE_RAW:
2844                         raw_spec = item->spec;
2845                         raw_mask = item->mask;
2846
2847                         if (!raw_spec || !raw_mask) {
2848                                 rte_flow_error_set(error, EINVAL,
2849                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2850                                                    item,
2851                                                    "NULL RAW spec/mask");
2852                                 return -rte_errno;
2853                         }
2854
2855                         if (pf->support_multi_driver) {
2856                                 rte_flow_error_set(error, ENOTSUP,
2857                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2858                                                    item,
2859                                                    "Unsupported flexible payload.");
2860                                 return -rte_errno;
2861                         }
2862
2863                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2864                         if (ret < 0)
2865                                 return ret;
2866
2867                         off_arr[raw_id] = raw_spec->offset;
2868                         len_arr[raw_id] = raw_spec->length;
2869
2870                         flex_size = 0;
2871                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2872                         flex_pit.size =
2873                                 raw_spec->length / sizeof(uint16_t);
2874                         flex_pit.dst_offset =
2875                                 next_dst_off / sizeof(uint16_t);
2876
2877                         for (i = 0; i <= raw_id; i++) {
2878                                 if (i == raw_id)
2879                                         flex_pit.src_offset +=
2880                                                 raw_spec->offset /
2881                                                 sizeof(uint16_t);
2882                                 else
2883                                         flex_pit.src_offset +=
2884                                                 (off_arr[i] + len_arr[i]) /
2885                                                 sizeof(uint16_t);
2886                                 flex_size += len_arr[i];
2887                         }
2888                         if (((flex_pit.src_offset + flex_pit.size) >=
2889                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2890                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2891                                 rte_flow_error_set(error, EINVAL,
2892                                            RTE_FLOW_ERROR_TYPE_ITEM,
2893                                            item,
2894                                            "Exceeds maxmial payload limit.");
2895                                 return -rte_errno;
2896                         }
2897
2898                         /* Store flex pit to SW */
2899                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2900                                                        layer_idx, raw_id);
2901                         if (ret < 0) {
2902                                 rte_flow_error_set(error, EINVAL,
2903                                    RTE_FLOW_ERROR_TYPE_ITEM,
2904                                    item,
2905                                    "Conflict with the first flexible rule.");
2906                                 return -rte_errno;
2907                         } else if (ret > 0)
2908                                 cfg_flex_pit = false;
2909
2910                         for (i = 0; i < raw_spec->length; i++) {
2911                                 j = i + next_dst_off;
2912                                 filter->input.flow_ext.flexbytes[j] =
2913                                         raw_spec->pattern[i];
2914                                 flex_mask[j] = raw_mask->pattern[i];
2915                         }
2916
2917                         next_dst_off += raw_spec->length;
2918                         raw_id++;
2919                         break;
2920                 case RTE_FLOW_ITEM_TYPE_VF:
2921                         vf_spec = item->spec;
2922                         filter->input.flow_ext.is_vf = 1;
2923                         filter->input.flow_ext.dst_id = vf_spec->id;
2924                         if (filter->input.flow_ext.is_vf &&
2925                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2926                                 rte_flow_error_set(error, EINVAL,
2927                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2928                                                    item,
2929                                                    "Invalid VF ID for FDIR.");
2930                                 return -rte_errno;
2931                         }
2932                         break;
2933                 default:
2934                         break;
2935                 }
2936         }
2937
2938         /* Get customized pctype value */
2939         if (filter->input.flow_ext.customized_pctype) {
2940                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2941                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2942                         rte_flow_error_set(error, EINVAL,
2943                                            RTE_FLOW_ERROR_TYPE_ITEM,
2944                                            item,
2945                                            "Unsupported pctype");
2946                         return -rte_errno;
2947                 }
2948         }
2949
2950         /* If customized pctype is not used, set fdir configuration.*/
2951         if (!filter->input.flow_ext.customized_pctype) {
2952                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2953                 if (ret == -1) {
2954                         rte_flow_error_set(error, EINVAL,
2955                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2956                                            "Conflict with the first rule's input set.");
2957                         return -rte_errno;
2958                 } else if (ret == -EINVAL) {
2959                         rte_flow_error_set(error, EINVAL,
2960                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2961                                            "Invalid pattern mask.");
2962                         return -rte_errno;
2963                 }
2964
2965                 /* Store flex mask to SW */
2966                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2967                 if (ret == -1) {
2968                         rte_flow_error_set(error, EINVAL,
2969                                            RTE_FLOW_ERROR_TYPE_ITEM,
2970                                            item,
2971                                            "Exceed maximal number of bitmasks");
2972                         return -rte_errno;
2973                 } else if (ret == -2) {
2974                         rte_flow_error_set(error, EINVAL,
2975                                            RTE_FLOW_ERROR_TYPE_ITEM,
2976                                            item,
2977                                            "Conflict with the first flexible rule");
2978                         return -rte_errno;
2979                 } else if (ret > 0)
2980                         cfg_flex_msk = false;
2981
2982                 if (cfg_flex_pit)
2983                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2984
2985                 if (cfg_flex_msk)
2986                         i40e_flow_set_fdir_flex_msk(pf, pctype);
2987         }
2988
2989         filter->input.pctype = pctype;
2990
2991         return 0;
2992 }
2993
2994 /* Parse to get the action info of a FDIR filter.
2995  * FDIR action supports QUEUE or (QUEUE + MARK).
2996  */
2997 static int
2998 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2999                             const struct rte_flow_action *actions,
3000                             struct rte_flow_error *error,
3001                             struct i40e_fdir_filter_conf *filter)
3002 {
3003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3004         const struct rte_flow_action *act;
3005         const struct rte_flow_action_queue *act_q;
3006         const struct rte_flow_action_mark *mark_spec;
3007         uint32_t index = 0;
3008
3009         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3010         NEXT_ITEM_OF_ACTION(act, actions, index);
3011         switch (act->type) {
3012         case RTE_FLOW_ACTION_TYPE_QUEUE:
3013                 act_q = act->conf;
3014                 filter->action.rx_queue = act_q->index;
3015                 if ((!filter->input.flow_ext.is_vf &&
3016                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3017                     (filter->input.flow_ext.is_vf &&
3018                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3019                         rte_flow_error_set(error, EINVAL,
3020                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3021                                            "Invalid queue ID for FDIR.");
3022                         return -rte_errno;
3023                 }
3024                 filter->action.behavior = I40E_FDIR_ACCEPT;
3025                 break;
3026         case RTE_FLOW_ACTION_TYPE_DROP:
3027                 filter->action.behavior = I40E_FDIR_REJECT;
3028                 break;
3029         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3030                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3031                 break;
3032         default:
3033                 rte_flow_error_set(error, EINVAL,
3034                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3035                                    "Invalid action.");
3036                 return -rte_errno;
3037         }
3038
3039         /* Check if the next non-void item is MARK or FLAG or END. */
3040         index++;
3041         NEXT_ITEM_OF_ACTION(act, actions, index);
3042         switch (act->type) {
3043         case RTE_FLOW_ACTION_TYPE_MARK:
3044                 mark_spec = act->conf;
3045                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3046                 filter->soft_id = mark_spec->id;
3047                 break;
3048         case RTE_FLOW_ACTION_TYPE_FLAG:
3049                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3050                 break;
3051         case RTE_FLOW_ACTION_TYPE_END:
3052                 return 0;
3053         default:
3054                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3055                                    act, "Invalid action.");
3056                 return -rte_errno;
3057         }
3058
3059         /* Check if the next non-void item is END */
3060         index++;
3061         NEXT_ITEM_OF_ACTION(act, actions, index);
3062         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3063                 rte_flow_error_set(error, EINVAL,
3064                                    RTE_FLOW_ERROR_TYPE_ACTION,
3065                                    act, "Invalid action.");
3066                 return -rte_errno;
3067         }
3068
3069         return 0;
3070 }
3071
3072 static int
3073 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3074                             const struct rte_flow_attr *attr,
3075                             const struct rte_flow_item pattern[],
3076                             const struct rte_flow_action actions[],
3077                             struct rte_flow_error *error,
3078                             union i40e_filter_t *filter)
3079 {
3080         struct i40e_fdir_filter_conf *fdir_filter =
3081                 &filter->fdir_filter;
3082         int ret;
3083
3084         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3085         if (ret)
3086                 return ret;
3087
3088         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3089         if (ret)
3090                 return ret;
3091
3092         ret = i40e_flow_parse_attr(attr, error);
3093         if (ret)
3094                 return ret;
3095
3096         cons_filter_type = RTE_ETH_FILTER_FDIR;
3097
3098         if (dev->data->dev_conf.fdir_conf.mode !=
3099             RTE_FDIR_MODE_PERFECT) {
3100                 rte_flow_error_set(error, ENOTSUP,
3101                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3102                                    NULL,
3103                                    "Check the mode in fdir_conf.");
3104                 return -rte_errno;
3105         }
3106
3107         return 0;
3108 }
3109
3110 /* Parse to get the action info of a tunnel filter
3111  * Tunnel action only supports PF, VF and QUEUE.
3112  */
3113 static int
3114 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3115                               const struct rte_flow_action *actions,
3116                               struct rte_flow_error *error,
3117                               struct i40e_tunnel_filter_conf *filter)
3118 {
3119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3120         const struct rte_flow_action *act;
3121         const struct rte_flow_action_queue *act_q;
3122         const struct rte_flow_action_vf *act_vf;
3123         uint32_t index = 0;
3124
3125         /* Check if the first non-void action is PF or VF. */
3126         NEXT_ITEM_OF_ACTION(act, actions, index);
3127         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3128             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3129                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3130                                    act, "Not supported action.");
3131                 return -rte_errno;
3132         }
3133
3134         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3135                 act_vf = act->conf;
3136                 filter->vf_id = act_vf->id;
3137                 filter->is_to_vf = 1;
3138                 if (filter->vf_id >= pf->vf_num) {
3139                         rte_flow_error_set(error, EINVAL,
3140                                    RTE_FLOW_ERROR_TYPE_ACTION,
3141                                    act, "Invalid VF ID for tunnel filter");
3142                         return -rte_errno;
3143                 }
3144         }
3145
3146         /* Check if the next non-void item is QUEUE */
3147         index++;
3148         NEXT_ITEM_OF_ACTION(act, actions, index);
3149         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3150                 act_q = act->conf;
3151                 filter->queue_id = act_q->index;
3152                 if ((!filter->is_to_vf) &&
3153                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3154                         rte_flow_error_set(error, EINVAL,
3155                                    RTE_FLOW_ERROR_TYPE_ACTION,
3156                                    act, "Invalid queue ID for tunnel filter");
3157                         return -rte_errno;
3158                 } else if (filter->is_to_vf &&
3159                            (filter->queue_id >= pf->vf_nb_qps)) {
3160                         rte_flow_error_set(error, EINVAL,
3161                                    RTE_FLOW_ERROR_TYPE_ACTION,
3162                                    act, "Invalid queue ID for tunnel filter");
3163                         return -rte_errno;
3164                 }
3165         }
3166
3167         /* Check if the next non-void item is END */
3168         index++;
3169         NEXT_ITEM_OF_ACTION(act, actions, index);
3170         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3171                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3172                                    act, "Not supported action.");
3173                 return -rte_errno;
3174         }
3175
3176         return 0;
3177 }
3178
3179 static uint16_t i40e_supported_tunnel_filter_types[] = {
3180         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3181         ETH_TUNNEL_FILTER_IVLAN,
3182         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3183         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3184         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3185         ETH_TUNNEL_FILTER_IMAC,
3186         ETH_TUNNEL_FILTER_IMAC,
3187 };
3188
3189 static int
3190 i40e_check_tunnel_filter_type(uint8_t filter_type)
3191 {
3192         uint8_t i;
3193
3194         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3195                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3196                         return 0;
3197         }
3198
3199         return -1;
3200 }
3201
3202 /* 1. Last in item should be NULL as range is not supported.
3203  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3204  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3205  * 3. Mask of fields which need to be matched should be
3206  *    filled with 1.
3207  * 4. Mask of fields which needn't to be matched should be
3208  *    filled with 0.
3209  */
3210 static int
3211 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3212                               const struct rte_flow_item *pattern,
3213                               struct rte_flow_error *error,
3214                               struct i40e_tunnel_filter_conf *filter)
3215 {
3216         const struct rte_flow_item *item = pattern;
3217         const struct rte_flow_item_eth *eth_spec;
3218         const struct rte_flow_item_eth *eth_mask;
3219         const struct rte_flow_item_vxlan *vxlan_spec;
3220         const struct rte_flow_item_vxlan *vxlan_mask;
3221         const struct rte_flow_item_vlan *vlan_spec;
3222         const struct rte_flow_item_vlan *vlan_mask;
3223         uint8_t filter_type = 0;
3224         bool is_vni_masked = 0;
3225         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3226         enum rte_flow_item_type item_type;
3227         bool vxlan_flag = 0;
3228         uint32_t tenant_id_be = 0;
3229         int ret;
3230
3231         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3232                 if (item->last) {
3233                         rte_flow_error_set(error, EINVAL,
3234                                            RTE_FLOW_ERROR_TYPE_ITEM,
3235                                            item,
3236                                            "Not support range");
3237                         return -rte_errno;
3238                 }
3239                 item_type = item->type;
3240                 switch (item_type) {
3241                 case RTE_FLOW_ITEM_TYPE_ETH:
3242                         eth_spec = item->spec;
3243                         eth_mask = item->mask;
3244
3245                         /* Check if ETH item is used for place holder.
3246                          * If yes, both spec and mask should be NULL.
3247                          * If no, both spec and mask shouldn't be NULL.
3248                          */
3249                         if ((!eth_spec && eth_mask) ||
3250                             (eth_spec && !eth_mask)) {
3251                                 rte_flow_error_set(error, EINVAL,
3252                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3253                                                    item,
3254                                                    "Invalid ether spec/mask");
3255                                 return -rte_errno;
3256                         }
3257
3258                         if (eth_spec && eth_mask) {
3259                                 /* DST address of inner MAC shouldn't be masked.
3260                                  * SRC address of Inner MAC should be masked.
3261                                  */
3262                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3263                                     !is_zero_ether_addr(&eth_mask->src) ||
3264                                     eth_mask->type) {
3265                                         rte_flow_error_set(error, EINVAL,
3266                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3267                                                    item,
3268                                                    "Invalid ether spec/mask");
3269                                         return -rte_errno;
3270                                 }
3271
3272                                 if (!vxlan_flag) {
3273                                         rte_memcpy(&filter->outer_mac,
3274                                                    &eth_spec->dst,
3275                                                    ETHER_ADDR_LEN);
3276                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3277                                 } else {
3278                                         rte_memcpy(&filter->inner_mac,
3279                                                    &eth_spec->dst,
3280                                                    ETHER_ADDR_LEN);
3281                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3282                                 }
3283                         }
3284                         break;
3285                 case RTE_FLOW_ITEM_TYPE_VLAN:
3286                         vlan_spec = item->spec;
3287                         vlan_mask = item->mask;
3288                         if (!(vlan_spec && vlan_mask)) {
3289                                 rte_flow_error_set(error, EINVAL,
3290                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3291                                                    item,
3292                                                    "Invalid vlan item");
3293                                 return -rte_errno;
3294                         }
3295
3296                         if (vlan_spec && vlan_mask) {
3297                                 if (vlan_mask->tci ==
3298                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3299                                         filter->inner_vlan =
3300                                               rte_be_to_cpu_16(vlan_spec->tci) &
3301                                               I40E_TCI_MASK;
3302                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3303                         }
3304                         break;
3305                 case RTE_FLOW_ITEM_TYPE_IPV4:
3306                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3307                         /* IPv4 is used to describe protocol,
3308                          * spec and mask should be NULL.
3309                          */
3310                         if (item->spec || item->mask) {
3311                                 rte_flow_error_set(error, EINVAL,
3312                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3313                                                    item,
3314                                                    "Invalid IPv4 item");
3315                                 return -rte_errno;
3316                         }
3317                         break;
3318                 case RTE_FLOW_ITEM_TYPE_IPV6:
3319                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3320                         /* IPv6 is used to describe protocol,
3321                          * spec and mask should be NULL.
3322                          */
3323                         if (item->spec || item->mask) {
3324                                 rte_flow_error_set(error, EINVAL,
3325                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3326                                                    item,
3327                                                    "Invalid IPv6 item");
3328                                 return -rte_errno;
3329                         }
3330                         break;
3331                 case RTE_FLOW_ITEM_TYPE_UDP:
3332                         /* UDP is used to describe protocol,
3333                          * spec and mask should be NULL.
3334                          */
3335                         if (item->spec || item->mask) {
3336                                 rte_flow_error_set(error, EINVAL,
3337                                            RTE_FLOW_ERROR_TYPE_ITEM,
3338                                            item,
3339                                            "Invalid UDP item");
3340                                 return -rte_errno;
3341                         }
3342                         break;
3343                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3344                         vxlan_spec = item->spec;
3345                         vxlan_mask = item->mask;
3346                         /* Check if VXLAN item is used to describe protocol.
3347                          * If yes, both spec and mask should be NULL.
3348                          * If no, both spec and mask shouldn't be NULL.
3349                          */
3350                         if ((!vxlan_spec && vxlan_mask) ||
3351                             (vxlan_spec && !vxlan_mask)) {
3352                                 rte_flow_error_set(error, EINVAL,
3353                                            RTE_FLOW_ERROR_TYPE_ITEM,
3354                                            item,
3355                                            "Invalid VXLAN item");
3356                                 return -rte_errno;
3357                         }
3358
3359                         /* Check if VNI is masked. */
3360                         if (vxlan_spec && vxlan_mask) {
3361                                 is_vni_masked =
3362                                         !!memcmp(vxlan_mask->vni, vni_mask,
3363                                                  RTE_DIM(vni_mask));
3364                                 if (is_vni_masked) {
3365                                         rte_flow_error_set(error, EINVAL,
3366                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3367                                                    item,
3368                                                    "Invalid VNI mask");
3369                                         return -rte_errno;
3370                                 }
3371
3372                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3373                                            vxlan_spec->vni, 3);
3374                                 filter->tenant_id =
3375                                         rte_be_to_cpu_32(tenant_id_be);
3376                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3377                         }
3378
3379                         vxlan_flag = 1;
3380                         break;
3381                 default:
3382                         break;
3383                 }
3384         }
3385
3386         ret = i40e_check_tunnel_filter_type(filter_type);
3387         if (ret < 0) {
3388                 rte_flow_error_set(error, EINVAL,
3389                                    RTE_FLOW_ERROR_TYPE_ITEM,
3390                                    NULL,
3391                                    "Invalid filter type");
3392                 return -rte_errno;
3393         }
3394         filter->filter_type = filter_type;
3395
3396         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3397
3398         return 0;
3399 }
3400
3401 static int
3402 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3403                              const struct rte_flow_attr *attr,
3404                              const struct rte_flow_item pattern[],
3405                              const struct rte_flow_action actions[],
3406                              struct rte_flow_error *error,
3407                              union i40e_filter_t *filter)
3408 {
3409         struct i40e_tunnel_filter_conf *tunnel_filter =
3410                 &filter->consistent_tunnel_filter;
3411         int ret;
3412
3413         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3414                                             error, tunnel_filter);
3415         if (ret)
3416                 return ret;
3417
3418         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3419         if (ret)
3420                 return ret;
3421
3422         ret = i40e_flow_parse_attr(attr, error);
3423         if (ret)
3424                 return ret;
3425
3426         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3427
3428         return ret;
3429 }
3430
3431 /* 1. Last in item should be NULL as range is not supported.
3432  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3433  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3434  * 3. Mask of fields which need to be matched should be
3435  *    filled with 1.
3436  * 4. Mask of fields which needn't to be matched should be
3437  *    filled with 0.
3438  */
3439 static int
3440 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3441                               const struct rte_flow_item *pattern,
3442                               struct rte_flow_error *error,
3443                               struct i40e_tunnel_filter_conf *filter)
3444 {
3445         const struct rte_flow_item *item = pattern;
3446         const struct rte_flow_item_eth *eth_spec;
3447         const struct rte_flow_item_eth *eth_mask;
3448         const struct rte_flow_item_nvgre *nvgre_spec;
3449         const struct rte_flow_item_nvgre *nvgre_mask;
3450         const struct rte_flow_item_vlan *vlan_spec;
3451         const struct rte_flow_item_vlan *vlan_mask;
3452         enum rte_flow_item_type item_type;
3453         uint8_t filter_type = 0;
3454         bool is_tni_masked = 0;
3455         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3456         bool nvgre_flag = 0;
3457         uint32_t tenant_id_be = 0;
3458         int ret;
3459
3460         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3461                 if (item->last) {
3462                         rte_flow_error_set(error, EINVAL,
3463                                            RTE_FLOW_ERROR_TYPE_ITEM,
3464                                            item,
3465                                            "Not support range");
3466                         return -rte_errno;
3467                 }
3468                 item_type = item->type;
3469                 switch (item_type) {
3470                 case RTE_FLOW_ITEM_TYPE_ETH:
3471                         eth_spec = item->spec;
3472                         eth_mask = item->mask;
3473
3474                         /* Check if ETH item is used for place holder.
3475                          * If yes, both spec and mask should be NULL.
3476                          * If no, both spec and mask shouldn't be NULL.
3477                          */
3478                         if ((!eth_spec && eth_mask) ||
3479                             (eth_spec && !eth_mask)) {
3480                                 rte_flow_error_set(error, EINVAL,
3481                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3482                                                    item,
3483                                                    "Invalid ether spec/mask");
3484                                 return -rte_errno;
3485                         }
3486
3487                         if (eth_spec && eth_mask) {
3488                                 /* DST address of inner MAC shouldn't be masked.
3489                                  * SRC address of Inner MAC should be masked.
3490                                  */
3491                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3492                                     !is_zero_ether_addr(&eth_mask->src) ||
3493                                     eth_mask->type) {
3494                                         rte_flow_error_set(error, EINVAL,
3495                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3496                                                    item,
3497                                                    "Invalid ether spec/mask");
3498                                         return -rte_errno;
3499                                 }
3500
3501                                 if (!nvgre_flag) {
3502                                         rte_memcpy(&filter->outer_mac,
3503                                                    &eth_spec->dst,
3504                                                    ETHER_ADDR_LEN);
3505                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3506                                 } else {
3507                                         rte_memcpy(&filter->inner_mac,
3508                                                    &eth_spec->dst,
3509                                                    ETHER_ADDR_LEN);
3510                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3511                                 }
3512                         }
3513
3514                         break;
3515                 case RTE_FLOW_ITEM_TYPE_VLAN:
3516                         vlan_spec = item->spec;
3517                         vlan_mask = item->mask;
3518                         if (!(vlan_spec && vlan_mask)) {
3519                                 rte_flow_error_set(error, EINVAL,
3520                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3521                                                    item,
3522                                                    "Invalid vlan item");
3523                                 return -rte_errno;
3524                         }
3525
3526                         if (vlan_spec && vlan_mask) {
3527                                 if (vlan_mask->tci ==
3528                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3529                                         filter->inner_vlan =
3530                                               rte_be_to_cpu_16(vlan_spec->tci) &
3531                                               I40E_TCI_MASK;
3532                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3533                         }
3534                         break;
3535                 case RTE_FLOW_ITEM_TYPE_IPV4:
3536                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3537                         /* IPv4 is used to describe protocol,
3538                          * spec and mask should be NULL.
3539                          */
3540                         if (item->spec || item->mask) {
3541                                 rte_flow_error_set(error, EINVAL,
3542                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3543                                                    item,
3544                                                    "Invalid IPv4 item");
3545                                 return -rte_errno;
3546                         }
3547                         break;
3548                 case RTE_FLOW_ITEM_TYPE_IPV6:
3549                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3550                         /* IPv6 is used to describe protocol,
3551                          * spec and mask should be NULL.
3552                          */
3553                         if (item->spec || item->mask) {
3554                                 rte_flow_error_set(error, EINVAL,
3555                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3556                                                    item,
3557                                                    "Invalid IPv6 item");
3558                                 return -rte_errno;
3559                         }
3560                         break;
3561                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3562                         nvgre_spec = item->spec;
3563                         nvgre_mask = item->mask;
3564                         /* Check if NVGRE item is used to describe protocol.
3565                          * If yes, both spec and mask should be NULL.
3566                          * If no, both spec and mask shouldn't be NULL.
3567                          */
3568                         if ((!nvgre_spec && nvgre_mask) ||
3569                             (nvgre_spec && !nvgre_mask)) {
3570                                 rte_flow_error_set(error, EINVAL,
3571                                            RTE_FLOW_ERROR_TYPE_ITEM,
3572                                            item,
3573                                            "Invalid NVGRE item");
3574                                 return -rte_errno;
3575                         }
3576
3577                         if (nvgre_spec && nvgre_mask) {
3578                                 is_tni_masked =
3579                                         !!memcmp(nvgre_mask->tni, tni_mask,
3580                                                  RTE_DIM(tni_mask));
3581                                 if (is_tni_masked) {
3582                                         rte_flow_error_set(error, EINVAL,
3583                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3584                                                        item,
3585                                                        "Invalid TNI mask");
3586                                         return -rte_errno;
3587                                 }
3588                                 if (nvgre_mask->protocol &&
3589                                         nvgre_mask->protocol != 0xFFFF) {
3590                                         rte_flow_error_set(error, EINVAL,
3591                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3592                                                 item,
3593                                                 "Invalid NVGRE item");
3594                                         return -rte_errno;
3595                                 }
3596                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3597                                         nvgre_mask->c_k_s_rsvd0_ver !=
3598                                         rte_cpu_to_be_16(0xFFFF)) {
3599                                         rte_flow_error_set(error, EINVAL,
3600                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3601                                                    item,
3602                                                    "Invalid NVGRE item");
3603                                         return -rte_errno;
3604                                 }
3605                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3606                                         rte_cpu_to_be_16(0x2000) &&
3607                                         nvgre_mask->c_k_s_rsvd0_ver) {
3608                                         rte_flow_error_set(error, EINVAL,
3609                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3610                                                    item,
3611                                                    "Invalid NVGRE item");
3612                                         return -rte_errno;
3613                                 }
3614                                 if (nvgre_mask->protocol &&
3615                                         nvgre_spec->protocol !=
3616                                         rte_cpu_to_be_16(0x6558)) {
3617                                         rte_flow_error_set(error, EINVAL,
3618                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3619                                                    item,
3620                                                    "Invalid NVGRE item");
3621                                         return -rte_errno;
3622                                 }
3623                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3624                                            nvgre_spec->tni, 3);
3625                                 filter->tenant_id =
3626                                         rte_be_to_cpu_32(tenant_id_be);
3627                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3628                         }
3629
3630                         nvgre_flag = 1;
3631                         break;
3632                 default:
3633                         break;
3634                 }
3635         }
3636
3637         ret = i40e_check_tunnel_filter_type(filter_type);
3638         if (ret < 0) {
3639                 rte_flow_error_set(error, EINVAL,
3640                                    RTE_FLOW_ERROR_TYPE_ITEM,
3641                                    NULL,
3642                                    "Invalid filter type");
3643                 return -rte_errno;
3644         }
3645         filter->filter_type = filter_type;
3646
3647         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3648
3649         return 0;
3650 }
3651
3652 static int
3653 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3654                              const struct rte_flow_attr *attr,
3655                              const struct rte_flow_item pattern[],
3656                              const struct rte_flow_action actions[],
3657                              struct rte_flow_error *error,
3658                              union i40e_filter_t *filter)
3659 {
3660         struct i40e_tunnel_filter_conf *tunnel_filter =
3661                 &filter->consistent_tunnel_filter;
3662         int ret;
3663
3664         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3665                                             error, tunnel_filter);
3666         if (ret)
3667                 return ret;
3668
3669         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3670         if (ret)
3671                 return ret;
3672
3673         ret = i40e_flow_parse_attr(attr, error);
3674         if (ret)
3675                 return ret;
3676
3677         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3678
3679         return ret;
3680 }
3681
3682 /* 1. Last in item should be NULL as range is not supported.
3683  * 2. Supported filter types: MPLS label.
3684  * 3. Mask of fields which need to be matched should be
3685  *    filled with 1.
3686  * 4. Mask of fields which needn't to be matched should be
3687  *    filled with 0.
3688  */
3689 static int
3690 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3691                              const struct rte_flow_item *pattern,
3692                              struct rte_flow_error *error,
3693                              struct i40e_tunnel_filter_conf *filter)
3694 {
3695         const struct rte_flow_item *item = pattern;
3696         const struct rte_flow_item_mpls *mpls_spec;
3697         const struct rte_flow_item_mpls *mpls_mask;
3698         enum rte_flow_item_type item_type;
3699         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3700         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3701         uint32_t label_be = 0;
3702
3703         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3704                 if (item->last) {
3705                         rte_flow_error_set(error, EINVAL,
3706                                            RTE_FLOW_ERROR_TYPE_ITEM,
3707                                            item,
3708                                            "Not support range");
3709                         return -rte_errno;
3710                 }
3711                 item_type = item->type;
3712                 switch (item_type) {
3713                 case RTE_FLOW_ITEM_TYPE_ETH:
3714                         if (item->spec || item->mask) {
3715                                 rte_flow_error_set(error, EINVAL,
3716                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3717                                                    item,
3718                                                    "Invalid ETH item");
3719                                 return -rte_errno;
3720                         }
3721                         break;
3722                 case RTE_FLOW_ITEM_TYPE_IPV4:
3723                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3724                         /* IPv4 is used to describe protocol,
3725                          * spec and mask should be NULL.
3726                          */
3727                         if (item->spec || item->mask) {
3728                                 rte_flow_error_set(error, EINVAL,
3729                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3730                                                    item,
3731                                                    "Invalid IPv4 item");
3732                                 return -rte_errno;
3733                         }
3734                         break;
3735                 case RTE_FLOW_ITEM_TYPE_IPV6:
3736                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3737                         /* IPv6 is used to describe protocol,
3738                          * spec and mask should be NULL.
3739                          */
3740                         if (item->spec || item->mask) {
3741                                 rte_flow_error_set(error, EINVAL,
3742                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3743                                                    item,
3744                                                    "Invalid IPv6 item");
3745                                 return -rte_errno;
3746                         }
3747                         break;
3748                 case RTE_FLOW_ITEM_TYPE_UDP:
3749                         /* UDP is used to describe protocol,
3750                          * spec and mask should be NULL.
3751                          */
3752                         if (item->spec || item->mask) {
3753                                 rte_flow_error_set(error, EINVAL,
3754                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3755                                                    item,
3756                                                    "Invalid UDP item");
3757                                 return -rte_errno;
3758                         }
3759                         is_mplsoudp = 1;
3760                         break;
3761                 case RTE_FLOW_ITEM_TYPE_GRE:
3762                         /* GRE is used to describe protocol,
3763                          * spec and mask should be NULL.
3764                          */
3765                         if (item->spec || item->mask) {
3766                                 rte_flow_error_set(error, EINVAL,
3767                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3768                                                    item,
3769                                                    "Invalid GRE item");
3770                                 return -rte_errno;
3771                         }
3772                         break;
3773                 case RTE_FLOW_ITEM_TYPE_MPLS:
3774                         mpls_spec = item->spec;
3775                         mpls_mask = item->mask;
3776
3777                         if (!mpls_spec || !mpls_mask) {
3778                                 rte_flow_error_set(error, EINVAL,
3779                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3780                                                    item,
3781                                                    "Invalid MPLS item");
3782                                 return -rte_errno;
3783                         }
3784
3785                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3786                                 rte_flow_error_set(error, EINVAL,
3787                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3788                                                    item,
3789                                                    "Invalid MPLS label mask");
3790                                 return -rte_errno;
3791                         }
3792                         rte_memcpy(((uint8_t *)&label_be + 1),
3793                                    mpls_spec->label_tc_s, 3);
3794                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3795                         break;
3796                 default:
3797                         break;
3798                 }
3799         }
3800
3801         if (is_mplsoudp)
3802                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3803         else
3804                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3805
3806         return 0;
3807 }
3808
3809 static int
3810 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3811                             const struct rte_flow_attr *attr,
3812                             const struct rte_flow_item pattern[],
3813                             const struct rte_flow_action actions[],
3814                             struct rte_flow_error *error,
3815                             union i40e_filter_t *filter)
3816 {
3817         struct i40e_tunnel_filter_conf *tunnel_filter =
3818                 &filter->consistent_tunnel_filter;
3819         int ret;
3820
3821         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3822                                            error, tunnel_filter);
3823         if (ret)
3824                 return ret;
3825
3826         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3827         if (ret)
3828                 return ret;
3829
3830         ret = i40e_flow_parse_attr(attr, error);
3831         if (ret)
3832                 return ret;
3833
3834         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3835
3836         return ret;
3837 }
3838
3839 /* 1. Last in item should be NULL as range is not supported.
3840  * 2. Supported filter types: GTP TEID.
3841  * 3. Mask of fields which need to be matched should be
3842  *    filled with 1.
3843  * 4. Mask of fields which needn't to be matched should be
3844  *    filled with 0.
3845  * 5. GTP profile supports GTPv1 only.
3846  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3847  */
3848 static int
3849 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3850                             const struct rte_flow_item *pattern,
3851                             struct rte_flow_error *error,
3852                             struct i40e_tunnel_filter_conf *filter)
3853 {
3854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3855         const struct rte_flow_item *item = pattern;
3856         const struct rte_flow_item_gtp *gtp_spec;
3857         const struct rte_flow_item_gtp *gtp_mask;
3858         enum rte_flow_item_type item_type;
3859
3860         if (!pf->gtp_support) {
3861                 rte_flow_error_set(error, EINVAL,
3862                                    RTE_FLOW_ERROR_TYPE_ITEM,
3863                                    item,
3864                                    "GTP is not supported by default.");
3865                 return -rte_errno;
3866         }
3867
3868         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3869                 if (item->last) {
3870                         rte_flow_error_set(error, EINVAL,
3871                                            RTE_FLOW_ERROR_TYPE_ITEM,
3872                                            item,
3873                                            "Not support range");
3874                         return -rte_errno;
3875                 }
3876                 item_type = item->type;
3877                 switch (item_type) {
3878                 case RTE_FLOW_ITEM_TYPE_ETH:
3879                         if (item->spec || item->mask) {
3880                                 rte_flow_error_set(error, EINVAL,
3881                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3882                                                    item,
3883                                                    "Invalid ETH item");
3884                                 return -rte_errno;
3885                         }
3886                         break;
3887                 case RTE_FLOW_ITEM_TYPE_IPV4:
3888                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3889                         /* IPv4 is used to describe protocol,
3890                          * spec and mask should be NULL.
3891                          */
3892                         if (item->spec || item->mask) {
3893                                 rte_flow_error_set(error, EINVAL,
3894                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3895                                                    item,
3896                                                    "Invalid IPv4 item");
3897                                 return -rte_errno;
3898                         }
3899                         break;
3900                 case RTE_FLOW_ITEM_TYPE_UDP:
3901                         if (item->spec || item->mask) {
3902                                 rte_flow_error_set(error, EINVAL,
3903                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3904                                                    item,
3905                                                    "Invalid UDP item");
3906                                 return -rte_errno;
3907                         }
3908                         break;
3909                 case RTE_FLOW_ITEM_TYPE_GTPC:
3910                 case RTE_FLOW_ITEM_TYPE_GTPU:
3911                         gtp_spec = item->spec;
3912                         gtp_mask = item->mask;
3913
3914                         if (!gtp_spec || !gtp_mask) {
3915                                 rte_flow_error_set(error, EINVAL,
3916                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3917                                                    item,
3918                                                    "Invalid GTP item");
3919                                 return -rte_errno;
3920                         }
3921
3922                         if (gtp_mask->v_pt_rsv_flags ||
3923                             gtp_mask->msg_type ||
3924                             gtp_mask->msg_len ||
3925                             gtp_mask->teid != UINT32_MAX) {
3926                                 rte_flow_error_set(error, EINVAL,
3927                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3928                                                    item,
3929                                                    "Invalid GTP mask");
3930                                 return -rte_errno;
3931                         }
3932
3933                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3934                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3935                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3936                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3937
3938                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3939
3940                         break;
3941                 default:
3942                         break;
3943                 }
3944         }
3945
3946         return 0;
3947 }
3948
3949 static int
3950 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3951                            const struct rte_flow_attr *attr,
3952                            const struct rte_flow_item pattern[],
3953                            const struct rte_flow_action actions[],
3954                            struct rte_flow_error *error,
3955                            union i40e_filter_t *filter)
3956 {
3957         struct i40e_tunnel_filter_conf *tunnel_filter =
3958                 &filter->consistent_tunnel_filter;
3959         int ret;
3960
3961         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3962                                           error, tunnel_filter);
3963         if (ret)
3964                 return ret;
3965
3966         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3967         if (ret)
3968                 return ret;
3969
3970         ret = i40e_flow_parse_attr(attr, error);
3971         if (ret)
3972                 return ret;
3973
3974         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3975
3976         return ret;
3977 }
3978
3979 /* 1. Last in item should be NULL as range is not supported.
3980  * 2. Supported filter types: QINQ.
3981  * 3. Mask of fields which need to be matched should be
3982  *    filled with 1.
3983  * 4. Mask of fields which needn't to be matched should be
3984  *    filled with 0.
3985  */
3986 static int
3987 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3988                               const struct rte_flow_item *pattern,
3989                               struct rte_flow_error *error,
3990                               struct i40e_tunnel_filter_conf *filter)
3991 {
3992         const struct rte_flow_item *item = pattern;
3993         const struct rte_flow_item_vlan *vlan_spec = NULL;
3994         const struct rte_flow_item_vlan *vlan_mask = NULL;
3995         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3996         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3997         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3998         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3999
4000         enum rte_flow_item_type item_type;
4001         bool vlan_flag = 0;
4002
4003         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4004                 if (item->last) {
4005                         rte_flow_error_set(error, EINVAL,
4006                                            RTE_FLOW_ERROR_TYPE_ITEM,
4007                                            item,
4008                                            "Not support range");
4009                         return -rte_errno;
4010                 }
4011                 item_type = item->type;
4012                 switch (item_type) {
4013                 case RTE_FLOW_ITEM_TYPE_ETH:
4014                         if (item->spec || item->mask) {
4015                                 rte_flow_error_set(error, EINVAL,
4016                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4017                                                    item,
4018                                                    "Invalid ETH item");
4019                                 return -rte_errno;
4020                         }
4021                         break;
4022                 case RTE_FLOW_ITEM_TYPE_VLAN:
4023                         vlan_spec = item->spec;
4024                         vlan_mask = item->mask;
4025
4026                         if (!(vlan_spec && vlan_mask)) {
4027                                 rte_flow_error_set(error, EINVAL,
4028                                            RTE_FLOW_ERROR_TYPE_ITEM,
4029                                            item,
4030                                            "Invalid vlan item");
4031                                 return -rte_errno;
4032                         }
4033
4034                         if (!vlan_flag) {
4035                                 o_vlan_spec = vlan_spec;
4036                                 o_vlan_mask = vlan_mask;
4037                                 vlan_flag = 1;
4038                         } else {
4039                                 i_vlan_spec = vlan_spec;
4040                                 i_vlan_mask = vlan_mask;
4041                                 vlan_flag = 0;
4042                         }
4043                         break;
4044
4045                 default:
4046                         break;
4047                 }
4048         }
4049
4050         /* Get filter specification */
4051         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4052                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4053                         (i_vlan_mask != NULL) &&
4054                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4055                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4056                         & I40E_TCI_MASK;
4057                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4058                         & I40E_TCI_MASK;
4059         } else {
4060                         rte_flow_error_set(error, EINVAL,
4061                                            RTE_FLOW_ERROR_TYPE_ITEM,
4062                                            NULL,
4063                                            "Invalid filter type");
4064                         return -rte_errno;
4065         }
4066
4067         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4068         return 0;
4069 }
4070
4071 static int
4072 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4073                               const struct rte_flow_attr *attr,
4074                               const struct rte_flow_item pattern[],
4075                               const struct rte_flow_action actions[],
4076                               struct rte_flow_error *error,
4077                               union i40e_filter_t *filter)
4078 {
4079         struct i40e_tunnel_filter_conf *tunnel_filter =
4080                 &filter->consistent_tunnel_filter;
4081         int ret;
4082
4083         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4084                                              error, tunnel_filter);
4085         if (ret)
4086                 return ret;
4087
4088         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4089         if (ret)
4090                 return ret;
4091
4092         ret = i40e_flow_parse_attr(attr, error);
4093         if (ret)
4094                 return ret;
4095
4096         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4097
4098         return ret;
4099 }
4100
4101 /**
4102  * This function is used to do configuration i40e existing RSS with rte_flow.
4103  * It also enable queue region configuration using flow API for i40e.
4104  * pattern can be used indicate what parameters will be include in flow,
4105  * like user_priority or flowtype for queue region or HASH function for RSS.
4106  * Action is used to transmit parameter like queue index and HASH
4107  * function for RSS, or flowtype for queue region configuration.
4108  * For example:
4109  * pattern:
4110  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4111  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4112  * Case 3: none, indicate RSS related will be parsed in action.
4113  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4114  * So, pattern choice is depened on the purpose of configuration of
4115  * that flow.
4116  * action:
4117  * action RSS will be uaed to transmit valid parameter with
4118  * struct rte_flow_action_rss for all the 3 case.
4119  */
4120 static int
4121 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4122                              const struct rte_flow_item *pattern,
4123                              struct rte_flow_error *error,
4124                              uint8_t *action_flag,
4125                              struct i40e_queue_regions *info)
4126 {
4127         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4128         const struct rte_flow_item *item = pattern;
4129         enum rte_flow_item_type item_type;
4130
4131         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4132                 return 0;
4133
4134         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4135                 if (item->last) {
4136                         rte_flow_error_set(error, EINVAL,
4137                                            RTE_FLOW_ERROR_TYPE_ITEM,
4138                                            item,
4139                                            "Not support range");
4140                         return -rte_errno;
4141                 }
4142                 item_type = item->type;
4143                 switch (item_type) {
4144                 case RTE_FLOW_ITEM_TYPE_ETH:
4145                         *action_flag = 1;
4146                         break;
4147                 case RTE_FLOW_ITEM_TYPE_VLAN:
4148                         vlan_spec = item->spec;
4149                         vlan_mask = item->mask;
4150                         if (vlan_spec && vlan_mask) {
4151                                 if (vlan_mask->tci ==
4152                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4153                                         info->region[0].user_priority[0] =
4154                                                 (rte_be_to_cpu_16(
4155                                                 vlan_spec->tci) >> 13) & 0x7;
4156                                         info->region[0].user_priority_num = 1;
4157                                         info->queue_region_number = 1;
4158                                         *action_flag = 0;
4159                                 }
4160                         }
4161                         break;
4162                 default:
4163                         rte_flow_error_set(error, EINVAL,
4164                                         RTE_FLOW_ERROR_TYPE_ITEM,
4165                                         item,
4166                                         "Not support range");
4167                         return -rte_errno;
4168                 }
4169         }
4170
4171         return 0;
4172 }
4173
4174 static int
4175 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4176                             const struct rte_flow_action *actions,
4177                             struct rte_flow_error *error,
4178                             uint8_t action_flag,
4179                             struct i40e_queue_regions *conf_info,
4180                             union i40e_filter_t *filter)
4181 {
4182         const struct rte_flow_action *act;
4183         const struct rte_flow_action_rss *rss;
4184         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4185         struct i40e_queue_regions *info = &pf->queue_region;
4186         struct i40e_rte_flow_rss_conf *rss_config =
4187                         &filter->rss_conf;
4188         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4189         uint16_t i, j, n, tmp;
4190         uint32_t index = 0;
4191         uint64_t hf_bit = 1;
4192
4193         NEXT_ITEM_OF_ACTION(act, actions, index);
4194         rss = act->conf;
4195
4196         /**
4197          * rss only supports forwarding,
4198          * check if the first not void action is RSS.
4199          */
4200         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4201                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4202                 rte_flow_error_set(error, EINVAL,
4203                         RTE_FLOW_ERROR_TYPE_ACTION,
4204                         act, "Not supported action.");
4205                 return -rte_errno;
4206         }
4207
4208         if (action_flag) {
4209                 for (n = 0; n < 64; n++) {
4210                         if (rss->rss_conf->rss_hf & (hf_bit << n)) {
4211                                 conf_info->region[0].hw_flowtype[0] = n;
4212                                 conf_info->region[0].flowtype_num = 1;
4213                                 conf_info->queue_region_number = 1;
4214                                 break;
4215                         }
4216                 }
4217         }
4218
4219         for (n = 0; n < conf_info->queue_region_number; n++) {
4220                 if (conf_info->region[n].user_priority_num ||
4221                                 conf_info->region[n].flowtype_num) {
4222                         if (!((rte_is_power_of_2(rss->num)) &&
4223                                         rss->num <= 64)) {
4224                                 PMD_DRV_LOG(ERR, "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4225                                 "total number of queues do not exceed the VSI allocation");
4226                                 return -rte_errno;
4227                         }
4228
4229                         if (conf_info->region[n].user_priority[n] >=
4230                                         I40E_MAX_USER_PRIORITY) {
4231                                 PMD_DRV_LOG(ERR, "the user priority max index is 7");
4232                                 return -rte_errno;
4233                         }
4234
4235                         if (conf_info->region[n].hw_flowtype[n] >=
4236                                         I40E_FILTER_PCTYPE_MAX) {
4237                                 PMD_DRV_LOG(ERR, "the hw_flowtype or PCTYPE max index is 63");
4238                                 return -rte_errno;
4239                         }
4240
4241                         if (rss_info->num < rss->num ||
4242                                 rss->queue[0] < rss_info->queue[0] ||
4243                                 (rss->queue[0] + rss->num >
4244                                         rss_info->num + rss_info->queue[0])) {
4245                                 rte_flow_error_set(error, EINVAL,
4246                                         RTE_FLOW_ERROR_TYPE_ACTION,
4247                                         act,
4248                                         "no valid queues");
4249                                 return -rte_errno;
4250                         }
4251
4252                         for (i = 0; i < info->queue_region_number; i++) {
4253                                 if (info->region[i].queue_num == rss->num &&
4254                                         info->region[i].queue_start_index ==
4255                                                 rss->queue[0])
4256                                         break;
4257                         }
4258
4259                         if (i == info->queue_region_number) {
4260                                 if (i > I40E_REGION_MAX_INDEX) {
4261                                         PMD_DRV_LOG(ERR, "the queue region max index is 7");
4262                                         return -rte_errno;
4263                                 }
4264
4265                                 info->region[i].queue_num =
4266                                         rss->num;
4267                                 info->region[i].queue_start_index =
4268                                         rss->queue[0];
4269                                 info->region[i].region_id =
4270                                         info->queue_region_number;
4271
4272                                 j = info->region[i].user_priority_num;
4273                                 tmp = conf_info->region[n].user_priority[0];
4274                                 if (conf_info->region[n].user_priority_num) {
4275                                         info->region[i].user_priority[j] = tmp;
4276                                         info->region[i].user_priority_num++;
4277                                 }
4278
4279                                 j = info->region[i].flowtype_num;
4280                                 tmp = conf_info->region[n].hw_flowtype[0];
4281                                 if (conf_info->region[n].flowtype_num) {
4282                                         info->region[i].hw_flowtype[j] = tmp;
4283                                         info->region[i].flowtype_num++;
4284                                 }
4285                                 info->queue_region_number++;
4286                         } else {
4287                                 j = info->region[i].user_priority_num;
4288                                 tmp = conf_info->region[n].user_priority[0];
4289                                 if (conf_info->region[n].user_priority_num) {
4290                                         info->region[i].user_priority[j] = tmp;
4291                                         info->region[i].user_priority_num++;
4292                                 }
4293
4294                                 j = info->region[i].flowtype_num;
4295                                 tmp = conf_info->region[n].hw_flowtype[0];
4296                                 if (conf_info->region[n].flowtype_num) {
4297                                         info->region[i].hw_flowtype[j] = tmp;
4298                                         info->region[i].flowtype_num++;
4299                                 }
4300                         }
4301                 }
4302
4303                 rss_config->queue_region_conf = TRUE;
4304         }
4305
4306         if (rss_config->queue_region_conf)
4307                 return 0;
4308
4309         if (!rss || !rss->num) {
4310                 rte_flow_error_set(error, EINVAL,
4311                                 RTE_FLOW_ERROR_TYPE_ACTION,
4312                                 act,
4313                                 "no valid queues");
4314                 return -rte_errno;
4315         }
4316
4317         for (n = 0; n < rss->num; n++) {
4318                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4319                         rte_flow_error_set(error, EINVAL,
4320                                    RTE_FLOW_ERROR_TYPE_ACTION,
4321                                    act,
4322                                    "queue id > max number of queues");
4323                         return -rte_errno;
4324                 }
4325         }
4326         if (rss->rss_conf)
4327                 rss_config->rss_conf = *rss->rss_conf;
4328         else
4329                 rss_config->rss_conf.rss_hf =
4330                         pf->adapter->flow_types_mask;
4331
4332         for (n = 0; n < rss->num; ++n)
4333                 rss_config->queue[n] = rss->queue[n];
4334         rss_config->num = rss->num;
4335         index++;
4336
4337         /* check if the next not void action is END */
4338         NEXT_ITEM_OF_ACTION(act, actions, index);
4339         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4340                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4341                 rte_flow_error_set(error, EINVAL,
4342                         RTE_FLOW_ERROR_TYPE_ACTION,
4343                         act, "Not supported action.");
4344                 return -rte_errno;
4345         }
4346         rss_config->queue_region_conf = FALSE;
4347
4348         return 0;
4349 }
4350
4351 static int
4352 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4353                         const struct rte_flow_attr *attr,
4354                         const struct rte_flow_item pattern[],
4355                         const struct rte_flow_action actions[],
4356                         union i40e_filter_t *filter,
4357                         struct rte_flow_error *error)
4358 {
4359         int ret;
4360         struct i40e_queue_regions info;
4361         uint8_t action_flag = 0;
4362
4363         memset(&info, 0, sizeof(struct i40e_queue_regions));
4364
4365         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4366                                         error, &action_flag, &info);
4367         if (ret)
4368                 return ret;
4369
4370         ret = i40e_flow_parse_rss_action(dev, actions, error,
4371                                         action_flag, &info, filter);
4372         if (ret)
4373                 return ret;
4374
4375         ret = i40e_flow_parse_attr(attr, error);
4376         if (ret)
4377                 return ret;
4378
4379         cons_filter_type = RTE_ETH_FILTER_HASH;
4380
4381         return 0;
4382 }
4383
4384 static int
4385 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4386                 struct i40e_rte_flow_rss_conf *conf)
4387 {
4388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4390         int ret;
4391
4392         if (conf->queue_region_conf) {
4393                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4394                 conf->queue_region_conf = 0;
4395         } else {
4396                 ret = i40e_config_rss_filter(pf, conf, 1);
4397         }
4398         return ret;
4399 }
4400
4401 static int
4402 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4403                 struct i40e_rte_flow_rss_conf *conf)
4404 {
4405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407
4408         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4409
4410         i40e_config_rss_filter(pf, conf, 0);
4411         return 0;
4412 }
4413
4414 static int
4415 i40e_flow_validate(struct rte_eth_dev *dev,
4416                    const struct rte_flow_attr *attr,
4417                    const struct rte_flow_item pattern[],
4418                    const struct rte_flow_action actions[],
4419                    struct rte_flow_error *error)
4420 {
4421         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4422         parse_filter_t parse_filter;
4423         uint32_t item_num = 0; /* non-void item number of pattern*/
4424         uint32_t i = 0;
4425         bool flag = false;
4426         int ret = I40E_NOT_SUPPORTED;
4427
4428         if (!pattern) {
4429                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4430                                    NULL, "NULL pattern.");
4431                 return -rte_errno;
4432         }
4433
4434         if (!actions) {
4435                 rte_flow_error_set(error, EINVAL,
4436                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4437                                    NULL, "NULL action.");
4438                 return -rte_errno;
4439         }
4440
4441         if (!attr) {
4442                 rte_flow_error_set(error, EINVAL,
4443                                    RTE_FLOW_ERROR_TYPE_ATTR,
4444                                    NULL, "NULL attribute.");
4445                 return -rte_errno;
4446         }
4447
4448         memset(&cons_filter, 0, sizeof(cons_filter));
4449
4450         /* Get the non-void item of action */
4451         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4452                 i++;
4453
4454         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4455                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4456                                         actions, &cons_filter, error);
4457                 return ret;
4458         }
4459
4460         i = 0;
4461         /* Get the non-void item number of pattern */
4462         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4463                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4464                         item_num++;
4465                 i++;
4466         }
4467         item_num++;
4468
4469         items = rte_zmalloc("i40e_pattern",
4470                             item_num * sizeof(struct rte_flow_item), 0);
4471         if (!items) {
4472                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4473                                    NULL, "No memory for PMD internal items.");
4474                 return -ENOMEM;
4475         }
4476
4477         i40e_pattern_skip_void_item(items, pattern);
4478
4479         i = 0;
4480         do {
4481                 parse_filter = i40e_find_parse_filter_func(items, &i);
4482                 if (!parse_filter && !flag) {
4483                         rte_flow_error_set(error, EINVAL,
4484                                            RTE_FLOW_ERROR_TYPE_ITEM,
4485                                            pattern, "Unsupported pattern");
4486                         rte_free(items);
4487                         return -rte_errno;
4488                 }
4489                 if (parse_filter)
4490                         ret = parse_filter(dev, attr, items, actions,
4491                                            error, &cons_filter);
4492                 flag = true;
4493         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4494
4495         rte_free(items);
4496
4497         return ret;
4498 }
4499
4500 static struct rte_flow *
4501 i40e_flow_create(struct rte_eth_dev *dev,
4502                  const struct rte_flow_attr *attr,
4503                  const struct rte_flow_item pattern[],
4504                  const struct rte_flow_action actions[],
4505                  struct rte_flow_error *error)
4506 {
4507         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4508         struct rte_flow *flow;
4509         int ret;
4510
4511         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4512         if (!flow) {
4513                 rte_flow_error_set(error, ENOMEM,
4514                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4515                                    "Failed to allocate memory");
4516                 return flow;
4517         }
4518
4519         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4520         if (ret < 0)
4521                 return NULL;
4522
4523         switch (cons_filter_type) {
4524         case RTE_ETH_FILTER_ETHERTYPE:
4525                 ret = i40e_ethertype_filter_set(pf,
4526                                         &cons_filter.ethertype_filter, 1);
4527                 if (ret)
4528                         goto free_flow;
4529                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4530                                         i40e_ethertype_filter_list);
4531                 break;
4532         case RTE_ETH_FILTER_FDIR:
4533                 ret = i40e_flow_add_del_fdir_filter(dev,
4534                                        &cons_filter.fdir_filter, 1);
4535                 if (ret)
4536                         goto free_flow;
4537                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4538                                         i40e_fdir_filter_list);
4539                 break;
4540         case RTE_ETH_FILTER_TUNNEL:
4541                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4542                             &cons_filter.consistent_tunnel_filter, 1);
4543                 if (ret)
4544                         goto free_flow;
4545                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4546                                         i40e_tunnel_filter_list);
4547                 break;
4548         case RTE_ETH_FILTER_HASH:
4549                 ret = i40e_config_rss_filter_set(dev,
4550                             &cons_filter.rss_conf);
4551                 if (ret)
4552                         goto free_flow;
4553                 flow->rule = &pf->rss_info;
4554                 break;
4555         default:
4556                 goto free_flow;
4557         }
4558
4559         flow->filter_type = cons_filter_type;
4560         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4561         return flow;
4562
4563 free_flow:
4564         rte_flow_error_set(error, -ret,
4565                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4566                            "Failed to create flow.");
4567         rte_free(flow);
4568         return NULL;
4569 }
4570
4571 static int
4572 i40e_flow_destroy(struct rte_eth_dev *dev,
4573                   struct rte_flow *flow,
4574                   struct rte_flow_error *error)
4575 {
4576         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4577         enum rte_filter_type filter_type = flow->filter_type;
4578         int ret = 0;
4579
4580         switch (filter_type) {
4581         case RTE_ETH_FILTER_ETHERTYPE:
4582                 ret = i40e_flow_destroy_ethertype_filter(pf,
4583                          (struct i40e_ethertype_filter *)flow->rule);
4584                 break;
4585         case RTE_ETH_FILTER_TUNNEL:
4586                 ret = i40e_flow_destroy_tunnel_filter(pf,
4587                               (struct i40e_tunnel_filter *)flow->rule);
4588                 break;
4589         case RTE_ETH_FILTER_FDIR:
4590                 ret = i40e_flow_add_del_fdir_filter(dev,
4591                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4592                 break;
4593         case RTE_ETH_FILTER_HASH:
4594                 ret = i40e_config_rss_filter_del(dev,
4595                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4596                 break;
4597         default:
4598                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4599                             filter_type);
4600                 ret = -EINVAL;
4601                 break;
4602         }
4603
4604         if (!ret) {
4605                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4606                 rte_free(flow);
4607         } else
4608                 rte_flow_error_set(error, -ret,
4609                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4610                                    "Failed to destroy flow.");
4611
4612         return ret;
4613 }
4614
4615 static int
4616 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4617                                    struct i40e_ethertype_filter *filter)
4618 {
4619         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4620         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4621         struct i40e_ethertype_filter *node;
4622         struct i40e_control_filter_stats stats;
4623         uint16_t flags = 0;
4624         int ret = 0;
4625
4626         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4627                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4628         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4629                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4630         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4631
4632         memset(&stats, 0, sizeof(stats));
4633         ret = i40e_aq_add_rem_control_packet_filter(hw,
4634                                     filter->input.mac_addr.addr_bytes,
4635                                     filter->input.ether_type,
4636                                     flags, pf->main_vsi->seid,
4637                                     filter->queue, 0, &stats, NULL);
4638         if (ret < 0)
4639                 return ret;
4640
4641         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4642         if (!node)
4643                 return -EINVAL;
4644
4645         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4646
4647         return ret;
4648 }
4649
4650 static int
4651 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4652                                 struct i40e_tunnel_filter *filter)
4653 {
4654         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4655         struct i40e_vsi *vsi;
4656         struct i40e_pf_vf *vf;
4657         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4658         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4659         struct i40e_tunnel_filter *node;
4660         bool big_buffer = 0;
4661         int ret = 0;
4662
4663         memset(&cld_filter, 0, sizeof(cld_filter));
4664         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4665                         (struct ether_addr *)&cld_filter.element.outer_mac);
4666         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4667                         (struct ether_addr *)&cld_filter.element.inner_mac);
4668         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4669         cld_filter.element.flags = filter->input.flags;
4670         cld_filter.element.tenant_id = filter->input.tenant_id;
4671         cld_filter.element.queue_number = filter->queue;
4672         rte_memcpy(cld_filter.general_fields,
4673                    filter->input.general_fields,
4674                    sizeof(cld_filter.general_fields));
4675
4676         if (!filter->is_to_vf)
4677                 vsi = pf->main_vsi;
4678         else {
4679                 vf = &pf->vfs[filter->vf_id];
4680                 vsi = vf->vsi;
4681         }
4682
4683         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4684             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4685             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4686             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4687             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4688             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4689                 big_buffer = 1;
4690
4691         if (big_buffer)
4692                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4693                                                               &cld_filter, 1);
4694         else
4695                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4696                                                    &cld_filter.element, 1);
4697         if (ret < 0)
4698                 return -ENOTSUP;
4699
4700         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4701         if (!node)
4702                 return -EINVAL;
4703
4704         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4705
4706         return ret;
4707 }
4708
4709 static int
4710 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4711 {
4712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4713         int ret;
4714
4715         ret = i40e_flow_flush_fdir_filter(pf);
4716         if (ret) {
4717                 rte_flow_error_set(error, -ret,
4718                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4719                                    "Failed to flush FDIR flows.");
4720                 return -rte_errno;
4721         }
4722
4723         ret = i40e_flow_flush_ethertype_filter(pf);
4724         if (ret) {
4725                 rte_flow_error_set(error, -ret,
4726                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4727                                    "Failed to ethertype flush flows.");
4728                 return -rte_errno;
4729         }
4730
4731         ret = i40e_flow_flush_tunnel_filter(pf);
4732         if (ret) {
4733                 rte_flow_error_set(error, -ret,
4734                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4735                                    "Failed to flush tunnel flows.");
4736                 return -rte_errno;
4737         }
4738
4739         ret = i40e_flow_flush_rss_filter(dev);
4740         if (ret) {
4741                 rte_flow_error_set(error, -ret,
4742                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4743                                    "Failed to flush rss flows.");
4744                 return -rte_errno;
4745         }
4746
4747         return ret;
4748 }
4749
4750 static int
4751 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4752 {
4753         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4754         struct i40e_fdir_info *fdir_info = &pf->fdir;
4755         struct i40e_fdir_filter *fdir_filter;
4756         enum i40e_filter_pctype pctype;
4757         struct rte_flow *flow;
4758         void *temp;
4759         int ret;
4760
4761         ret = i40e_fdir_flush(dev);
4762         if (!ret) {
4763                 /* Delete FDIR filters in FDIR list. */
4764                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4765                         ret = i40e_sw_fdir_filter_del(pf,
4766                                                       &fdir_filter->fdir.input);
4767                         if (ret < 0)
4768                                 return ret;
4769                 }
4770
4771                 /* Delete FDIR flows in flow list. */
4772                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4773                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4774                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4775                                 rte_free(flow);
4776                         }
4777                 }
4778
4779                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4780                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4781                         pf->fdir.inset_flag[pctype] = 0;
4782         }
4783
4784         return ret;
4785 }
4786
4787 /* Flush all ethertype filters */
4788 static int
4789 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4790 {
4791         struct i40e_ethertype_filter_list
4792                 *ethertype_list = &pf->ethertype.ethertype_list;
4793         struct i40e_ethertype_filter *filter;
4794         struct rte_flow *flow;
4795         void *temp;
4796         int ret = 0;
4797
4798         while ((filter = TAILQ_FIRST(ethertype_list))) {
4799                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4800                 if (ret)
4801                         return ret;
4802         }
4803
4804         /* Delete ethertype flows in flow list. */
4805         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4806                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4807                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4808                         rte_free(flow);
4809                 }
4810         }
4811
4812         return ret;
4813 }
4814
4815 /* Flush all tunnel filters */
4816 static int
4817 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4818 {
4819         struct i40e_tunnel_filter_list
4820                 *tunnel_list = &pf->tunnel.tunnel_list;
4821         struct i40e_tunnel_filter *filter;
4822         struct rte_flow *flow;
4823         void *temp;
4824         int ret = 0;
4825
4826         while ((filter = TAILQ_FIRST(tunnel_list))) {
4827                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4828                 if (ret)
4829                         return ret;
4830         }
4831
4832         /* Delete tunnel flows in flow list. */
4833         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4834                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4835                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4836                         rte_free(flow);
4837                 }
4838         }
4839
4840         return ret;
4841 }
4842
4843 /* remove the rss filter */
4844 static int
4845 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4846 {
4847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4848         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850         int32_t ret = -EINVAL;
4851
4852         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4853
4854         if (rss_info->num)
4855                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
4856         return ret;
4857 }