1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_eth_ctrl.h>
18 #include <rte_tailq.h>
19 #include <rte_flow_driver.h>
21 #include "i40e_logs.h"
22 #include "base/i40e_type.h"
23 #include "base/i40e_prototype.h"
24 #include "i40e_ethdev.h"
26 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
27 #define I40E_IPV6_FRAG_HEADER 44
28 #define I40E_TENANT_ARRAY_NUM 3
29 #define I40E_TCI_MASK 0xFFFF
31 static int i40e_flow_validate(struct rte_eth_dev *dev,
32 const struct rte_flow_attr *attr,
33 const struct rte_flow_item pattern[],
34 const struct rte_flow_action actions[],
35 struct rte_flow_error *error);
36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
37 const struct rte_flow_attr *attr,
38 const struct rte_flow_item pattern[],
39 const struct rte_flow_action actions[],
40 struct rte_flow_error *error);
41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
42 struct rte_flow *flow,
43 struct rte_flow_error *error);
44 static int i40e_flow_flush(struct rte_eth_dev *dev,
45 struct rte_flow_error *error);
47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
48 const struct rte_flow_item *pattern,
49 struct rte_flow_error *error,
50 struct rte_eth_ethertype_filter *filter);
51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
52 const struct rte_flow_action *actions,
53 struct rte_flow_error *error,
54 struct rte_eth_ethertype_filter *filter);
55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
56 const struct rte_flow_item *pattern,
57 struct rte_flow_error *error,
58 struct i40e_fdir_filter_conf *filter);
59 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
60 const struct rte_flow_action *actions,
61 struct rte_flow_error *error,
62 struct i40e_fdir_filter_conf *filter);
63 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
64 const struct rte_flow_action *actions,
65 struct rte_flow_error *error,
66 struct i40e_tunnel_filter_conf *filter);
67 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
68 struct rte_flow_error *error);
69 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
70 const struct rte_flow_attr *attr,
71 const struct rte_flow_item pattern[],
72 const struct rte_flow_action actions[],
73 struct rte_flow_error *error,
74 union i40e_filter_t *filter);
75 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
76 const struct rte_flow_attr *attr,
77 const struct rte_flow_item pattern[],
78 const struct rte_flow_action actions[],
79 struct rte_flow_error *error,
80 union i40e_filter_t *filter);
81 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
82 const struct rte_flow_attr *attr,
83 const struct rte_flow_item pattern[],
84 const struct rte_flow_action actions[],
85 struct rte_flow_error *error,
86 union i40e_filter_t *filter);
87 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
88 const struct rte_flow_attr *attr,
89 const struct rte_flow_item pattern[],
90 const struct rte_flow_action actions[],
91 struct rte_flow_error *error,
92 union i40e_filter_t *filter);
93 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
94 const struct rte_flow_attr *attr,
95 const struct rte_flow_item pattern[],
96 const struct rte_flow_action actions[],
97 struct rte_flow_error *error,
98 union i40e_filter_t *filter);
99 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
100 const struct rte_flow_attr *attr,
101 const struct rte_flow_item pattern[],
102 const struct rte_flow_action actions[],
103 struct rte_flow_error *error,
104 union i40e_filter_t *filter);
105 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
106 struct i40e_ethertype_filter *filter);
107 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
108 struct i40e_tunnel_filter *filter);
109 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
110 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
111 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
113 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
116 const struct rte_flow_attr *attr,
117 const struct rte_flow_item pattern[],
118 const struct rte_flow_action actions[],
119 struct rte_flow_error *error,
120 union i40e_filter_t *filter);
122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
123 const struct rte_flow_item *pattern,
124 struct rte_flow_error *error,
125 struct i40e_tunnel_filter_conf *filter);
127 const struct rte_flow_ops i40e_flow_ops = {
128 .validate = i40e_flow_validate,
129 .create = i40e_flow_create,
130 .destroy = i40e_flow_destroy,
131 .flush = i40e_flow_flush,
134 union i40e_filter_t cons_filter;
135 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
137 /* Pattern matched ethertype filter */
138 static enum rte_flow_item_type pattern_ethertype[] = {
139 RTE_FLOW_ITEM_TYPE_ETH,
140 RTE_FLOW_ITEM_TYPE_END,
143 /* Pattern matched flow director filter */
144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
145 RTE_FLOW_ITEM_TYPE_ETH,
146 RTE_FLOW_ITEM_TYPE_IPV4,
147 RTE_FLOW_ITEM_TYPE_END,
150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
151 RTE_FLOW_ITEM_TYPE_ETH,
152 RTE_FLOW_ITEM_TYPE_IPV4,
153 RTE_FLOW_ITEM_TYPE_UDP,
154 RTE_FLOW_ITEM_TYPE_END,
157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
158 RTE_FLOW_ITEM_TYPE_ETH,
159 RTE_FLOW_ITEM_TYPE_IPV4,
160 RTE_FLOW_ITEM_TYPE_TCP,
161 RTE_FLOW_ITEM_TYPE_END,
164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
165 RTE_FLOW_ITEM_TYPE_ETH,
166 RTE_FLOW_ITEM_TYPE_IPV4,
167 RTE_FLOW_ITEM_TYPE_SCTP,
168 RTE_FLOW_ITEM_TYPE_END,
171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
172 RTE_FLOW_ITEM_TYPE_ETH,
173 RTE_FLOW_ITEM_TYPE_IPV4,
174 RTE_FLOW_ITEM_TYPE_UDP,
175 RTE_FLOW_ITEM_TYPE_GTPC,
176 RTE_FLOW_ITEM_TYPE_END,
179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
180 RTE_FLOW_ITEM_TYPE_ETH,
181 RTE_FLOW_ITEM_TYPE_IPV4,
182 RTE_FLOW_ITEM_TYPE_UDP,
183 RTE_FLOW_ITEM_TYPE_GTPU,
184 RTE_FLOW_ITEM_TYPE_END,
187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
188 RTE_FLOW_ITEM_TYPE_ETH,
189 RTE_FLOW_ITEM_TYPE_IPV4,
190 RTE_FLOW_ITEM_TYPE_UDP,
191 RTE_FLOW_ITEM_TYPE_GTPU,
192 RTE_FLOW_ITEM_TYPE_IPV4,
193 RTE_FLOW_ITEM_TYPE_END,
196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
197 RTE_FLOW_ITEM_TYPE_ETH,
198 RTE_FLOW_ITEM_TYPE_IPV4,
199 RTE_FLOW_ITEM_TYPE_UDP,
200 RTE_FLOW_ITEM_TYPE_GTPU,
201 RTE_FLOW_ITEM_TYPE_IPV6,
202 RTE_FLOW_ITEM_TYPE_END,
205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
206 RTE_FLOW_ITEM_TYPE_ETH,
207 RTE_FLOW_ITEM_TYPE_IPV6,
208 RTE_FLOW_ITEM_TYPE_END,
211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
212 RTE_FLOW_ITEM_TYPE_ETH,
213 RTE_FLOW_ITEM_TYPE_IPV6,
214 RTE_FLOW_ITEM_TYPE_UDP,
215 RTE_FLOW_ITEM_TYPE_END,
218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
219 RTE_FLOW_ITEM_TYPE_ETH,
220 RTE_FLOW_ITEM_TYPE_IPV6,
221 RTE_FLOW_ITEM_TYPE_TCP,
222 RTE_FLOW_ITEM_TYPE_END,
225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
226 RTE_FLOW_ITEM_TYPE_ETH,
227 RTE_FLOW_ITEM_TYPE_IPV6,
228 RTE_FLOW_ITEM_TYPE_SCTP,
229 RTE_FLOW_ITEM_TYPE_END,
232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
233 RTE_FLOW_ITEM_TYPE_ETH,
234 RTE_FLOW_ITEM_TYPE_IPV6,
235 RTE_FLOW_ITEM_TYPE_UDP,
236 RTE_FLOW_ITEM_TYPE_GTPC,
237 RTE_FLOW_ITEM_TYPE_END,
240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
241 RTE_FLOW_ITEM_TYPE_ETH,
242 RTE_FLOW_ITEM_TYPE_IPV6,
243 RTE_FLOW_ITEM_TYPE_UDP,
244 RTE_FLOW_ITEM_TYPE_GTPU,
245 RTE_FLOW_ITEM_TYPE_END,
248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
249 RTE_FLOW_ITEM_TYPE_ETH,
250 RTE_FLOW_ITEM_TYPE_IPV6,
251 RTE_FLOW_ITEM_TYPE_UDP,
252 RTE_FLOW_ITEM_TYPE_GTPU,
253 RTE_FLOW_ITEM_TYPE_IPV4,
254 RTE_FLOW_ITEM_TYPE_END,
257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
258 RTE_FLOW_ITEM_TYPE_ETH,
259 RTE_FLOW_ITEM_TYPE_IPV6,
260 RTE_FLOW_ITEM_TYPE_UDP,
261 RTE_FLOW_ITEM_TYPE_GTPU,
262 RTE_FLOW_ITEM_TYPE_IPV6,
263 RTE_FLOW_ITEM_TYPE_END,
266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
267 RTE_FLOW_ITEM_TYPE_ETH,
268 RTE_FLOW_ITEM_TYPE_RAW,
269 RTE_FLOW_ITEM_TYPE_END,
272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
273 RTE_FLOW_ITEM_TYPE_ETH,
274 RTE_FLOW_ITEM_TYPE_RAW,
275 RTE_FLOW_ITEM_TYPE_RAW,
276 RTE_FLOW_ITEM_TYPE_END,
279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
280 RTE_FLOW_ITEM_TYPE_ETH,
281 RTE_FLOW_ITEM_TYPE_RAW,
282 RTE_FLOW_ITEM_TYPE_RAW,
283 RTE_FLOW_ITEM_TYPE_RAW,
284 RTE_FLOW_ITEM_TYPE_END,
287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
288 RTE_FLOW_ITEM_TYPE_ETH,
289 RTE_FLOW_ITEM_TYPE_IPV4,
290 RTE_FLOW_ITEM_TYPE_RAW,
291 RTE_FLOW_ITEM_TYPE_END,
294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
295 RTE_FLOW_ITEM_TYPE_ETH,
296 RTE_FLOW_ITEM_TYPE_IPV4,
297 RTE_FLOW_ITEM_TYPE_RAW,
298 RTE_FLOW_ITEM_TYPE_RAW,
299 RTE_FLOW_ITEM_TYPE_END,
302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
303 RTE_FLOW_ITEM_TYPE_ETH,
304 RTE_FLOW_ITEM_TYPE_IPV4,
305 RTE_FLOW_ITEM_TYPE_RAW,
306 RTE_FLOW_ITEM_TYPE_RAW,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_END,
311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
312 RTE_FLOW_ITEM_TYPE_ETH,
313 RTE_FLOW_ITEM_TYPE_IPV4,
314 RTE_FLOW_ITEM_TYPE_UDP,
315 RTE_FLOW_ITEM_TYPE_RAW,
316 RTE_FLOW_ITEM_TYPE_END,
319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
320 RTE_FLOW_ITEM_TYPE_ETH,
321 RTE_FLOW_ITEM_TYPE_IPV4,
322 RTE_FLOW_ITEM_TYPE_UDP,
323 RTE_FLOW_ITEM_TYPE_RAW,
324 RTE_FLOW_ITEM_TYPE_RAW,
325 RTE_FLOW_ITEM_TYPE_END,
328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
329 RTE_FLOW_ITEM_TYPE_ETH,
330 RTE_FLOW_ITEM_TYPE_IPV4,
331 RTE_FLOW_ITEM_TYPE_UDP,
332 RTE_FLOW_ITEM_TYPE_RAW,
333 RTE_FLOW_ITEM_TYPE_RAW,
334 RTE_FLOW_ITEM_TYPE_RAW,
335 RTE_FLOW_ITEM_TYPE_END,
338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
339 RTE_FLOW_ITEM_TYPE_ETH,
340 RTE_FLOW_ITEM_TYPE_IPV4,
341 RTE_FLOW_ITEM_TYPE_TCP,
342 RTE_FLOW_ITEM_TYPE_RAW,
343 RTE_FLOW_ITEM_TYPE_END,
346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
347 RTE_FLOW_ITEM_TYPE_ETH,
348 RTE_FLOW_ITEM_TYPE_IPV4,
349 RTE_FLOW_ITEM_TYPE_TCP,
350 RTE_FLOW_ITEM_TYPE_RAW,
351 RTE_FLOW_ITEM_TYPE_RAW,
352 RTE_FLOW_ITEM_TYPE_END,
355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
356 RTE_FLOW_ITEM_TYPE_ETH,
357 RTE_FLOW_ITEM_TYPE_IPV4,
358 RTE_FLOW_ITEM_TYPE_TCP,
359 RTE_FLOW_ITEM_TYPE_RAW,
360 RTE_FLOW_ITEM_TYPE_RAW,
361 RTE_FLOW_ITEM_TYPE_RAW,
362 RTE_FLOW_ITEM_TYPE_END,
365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
366 RTE_FLOW_ITEM_TYPE_ETH,
367 RTE_FLOW_ITEM_TYPE_IPV4,
368 RTE_FLOW_ITEM_TYPE_SCTP,
369 RTE_FLOW_ITEM_TYPE_RAW,
370 RTE_FLOW_ITEM_TYPE_END,
373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
374 RTE_FLOW_ITEM_TYPE_ETH,
375 RTE_FLOW_ITEM_TYPE_IPV4,
376 RTE_FLOW_ITEM_TYPE_SCTP,
377 RTE_FLOW_ITEM_TYPE_RAW,
378 RTE_FLOW_ITEM_TYPE_RAW,
379 RTE_FLOW_ITEM_TYPE_END,
382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
383 RTE_FLOW_ITEM_TYPE_ETH,
384 RTE_FLOW_ITEM_TYPE_IPV4,
385 RTE_FLOW_ITEM_TYPE_SCTP,
386 RTE_FLOW_ITEM_TYPE_RAW,
387 RTE_FLOW_ITEM_TYPE_RAW,
388 RTE_FLOW_ITEM_TYPE_RAW,
389 RTE_FLOW_ITEM_TYPE_END,
392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
393 RTE_FLOW_ITEM_TYPE_ETH,
394 RTE_FLOW_ITEM_TYPE_IPV6,
395 RTE_FLOW_ITEM_TYPE_RAW,
396 RTE_FLOW_ITEM_TYPE_END,
399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
400 RTE_FLOW_ITEM_TYPE_ETH,
401 RTE_FLOW_ITEM_TYPE_IPV6,
402 RTE_FLOW_ITEM_TYPE_RAW,
403 RTE_FLOW_ITEM_TYPE_RAW,
404 RTE_FLOW_ITEM_TYPE_END,
407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
408 RTE_FLOW_ITEM_TYPE_ETH,
409 RTE_FLOW_ITEM_TYPE_IPV6,
410 RTE_FLOW_ITEM_TYPE_RAW,
411 RTE_FLOW_ITEM_TYPE_RAW,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_END,
416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
417 RTE_FLOW_ITEM_TYPE_ETH,
418 RTE_FLOW_ITEM_TYPE_IPV6,
419 RTE_FLOW_ITEM_TYPE_UDP,
420 RTE_FLOW_ITEM_TYPE_RAW,
421 RTE_FLOW_ITEM_TYPE_END,
424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
425 RTE_FLOW_ITEM_TYPE_ETH,
426 RTE_FLOW_ITEM_TYPE_IPV6,
427 RTE_FLOW_ITEM_TYPE_UDP,
428 RTE_FLOW_ITEM_TYPE_RAW,
429 RTE_FLOW_ITEM_TYPE_RAW,
430 RTE_FLOW_ITEM_TYPE_END,
433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
434 RTE_FLOW_ITEM_TYPE_ETH,
435 RTE_FLOW_ITEM_TYPE_IPV6,
436 RTE_FLOW_ITEM_TYPE_UDP,
437 RTE_FLOW_ITEM_TYPE_RAW,
438 RTE_FLOW_ITEM_TYPE_RAW,
439 RTE_FLOW_ITEM_TYPE_RAW,
440 RTE_FLOW_ITEM_TYPE_END,
443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
444 RTE_FLOW_ITEM_TYPE_ETH,
445 RTE_FLOW_ITEM_TYPE_IPV6,
446 RTE_FLOW_ITEM_TYPE_TCP,
447 RTE_FLOW_ITEM_TYPE_RAW,
448 RTE_FLOW_ITEM_TYPE_END,
451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
452 RTE_FLOW_ITEM_TYPE_ETH,
453 RTE_FLOW_ITEM_TYPE_IPV6,
454 RTE_FLOW_ITEM_TYPE_TCP,
455 RTE_FLOW_ITEM_TYPE_RAW,
456 RTE_FLOW_ITEM_TYPE_RAW,
457 RTE_FLOW_ITEM_TYPE_END,
460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
461 RTE_FLOW_ITEM_TYPE_ETH,
462 RTE_FLOW_ITEM_TYPE_IPV6,
463 RTE_FLOW_ITEM_TYPE_TCP,
464 RTE_FLOW_ITEM_TYPE_RAW,
465 RTE_FLOW_ITEM_TYPE_RAW,
466 RTE_FLOW_ITEM_TYPE_RAW,
467 RTE_FLOW_ITEM_TYPE_END,
470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
471 RTE_FLOW_ITEM_TYPE_ETH,
472 RTE_FLOW_ITEM_TYPE_IPV6,
473 RTE_FLOW_ITEM_TYPE_SCTP,
474 RTE_FLOW_ITEM_TYPE_RAW,
475 RTE_FLOW_ITEM_TYPE_END,
478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
479 RTE_FLOW_ITEM_TYPE_ETH,
480 RTE_FLOW_ITEM_TYPE_IPV6,
481 RTE_FLOW_ITEM_TYPE_SCTP,
482 RTE_FLOW_ITEM_TYPE_RAW,
483 RTE_FLOW_ITEM_TYPE_RAW,
484 RTE_FLOW_ITEM_TYPE_END,
487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
488 RTE_FLOW_ITEM_TYPE_ETH,
489 RTE_FLOW_ITEM_TYPE_IPV6,
490 RTE_FLOW_ITEM_TYPE_SCTP,
491 RTE_FLOW_ITEM_TYPE_RAW,
492 RTE_FLOW_ITEM_TYPE_RAW,
493 RTE_FLOW_ITEM_TYPE_RAW,
494 RTE_FLOW_ITEM_TYPE_END,
497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
498 RTE_FLOW_ITEM_TYPE_ETH,
499 RTE_FLOW_ITEM_TYPE_VLAN,
500 RTE_FLOW_ITEM_TYPE_END,
503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
504 RTE_FLOW_ITEM_TYPE_ETH,
505 RTE_FLOW_ITEM_TYPE_VLAN,
506 RTE_FLOW_ITEM_TYPE_IPV4,
507 RTE_FLOW_ITEM_TYPE_END,
510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
511 RTE_FLOW_ITEM_TYPE_ETH,
512 RTE_FLOW_ITEM_TYPE_VLAN,
513 RTE_FLOW_ITEM_TYPE_IPV4,
514 RTE_FLOW_ITEM_TYPE_UDP,
515 RTE_FLOW_ITEM_TYPE_END,
518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
519 RTE_FLOW_ITEM_TYPE_ETH,
520 RTE_FLOW_ITEM_TYPE_VLAN,
521 RTE_FLOW_ITEM_TYPE_IPV4,
522 RTE_FLOW_ITEM_TYPE_TCP,
523 RTE_FLOW_ITEM_TYPE_END,
526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
527 RTE_FLOW_ITEM_TYPE_ETH,
528 RTE_FLOW_ITEM_TYPE_VLAN,
529 RTE_FLOW_ITEM_TYPE_IPV4,
530 RTE_FLOW_ITEM_TYPE_SCTP,
531 RTE_FLOW_ITEM_TYPE_END,
534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
535 RTE_FLOW_ITEM_TYPE_ETH,
536 RTE_FLOW_ITEM_TYPE_VLAN,
537 RTE_FLOW_ITEM_TYPE_IPV6,
538 RTE_FLOW_ITEM_TYPE_END,
541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
542 RTE_FLOW_ITEM_TYPE_ETH,
543 RTE_FLOW_ITEM_TYPE_VLAN,
544 RTE_FLOW_ITEM_TYPE_IPV6,
545 RTE_FLOW_ITEM_TYPE_UDP,
546 RTE_FLOW_ITEM_TYPE_END,
549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
550 RTE_FLOW_ITEM_TYPE_ETH,
551 RTE_FLOW_ITEM_TYPE_VLAN,
552 RTE_FLOW_ITEM_TYPE_IPV6,
553 RTE_FLOW_ITEM_TYPE_TCP,
554 RTE_FLOW_ITEM_TYPE_END,
557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
558 RTE_FLOW_ITEM_TYPE_ETH,
559 RTE_FLOW_ITEM_TYPE_VLAN,
560 RTE_FLOW_ITEM_TYPE_IPV6,
561 RTE_FLOW_ITEM_TYPE_SCTP,
562 RTE_FLOW_ITEM_TYPE_END,
565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
566 RTE_FLOW_ITEM_TYPE_ETH,
567 RTE_FLOW_ITEM_TYPE_VLAN,
568 RTE_FLOW_ITEM_TYPE_RAW,
569 RTE_FLOW_ITEM_TYPE_END,
572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
573 RTE_FLOW_ITEM_TYPE_ETH,
574 RTE_FLOW_ITEM_TYPE_VLAN,
575 RTE_FLOW_ITEM_TYPE_RAW,
576 RTE_FLOW_ITEM_TYPE_RAW,
577 RTE_FLOW_ITEM_TYPE_END,
580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
581 RTE_FLOW_ITEM_TYPE_ETH,
582 RTE_FLOW_ITEM_TYPE_VLAN,
583 RTE_FLOW_ITEM_TYPE_RAW,
584 RTE_FLOW_ITEM_TYPE_RAW,
585 RTE_FLOW_ITEM_TYPE_RAW,
586 RTE_FLOW_ITEM_TYPE_END,
589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
590 RTE_FLOW_ITEM_TYPE_ETH,
591 RTE_FLOW_ITEM_TYPE_VLAN,
592 RTE_FLOW_ITEM_TYPE_IPV4,
593 RTE_FLOW_ITEM_TYPE_RAW,
594 RTE_FLOW_ITEM_TYPE_END,
597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
598 RTE_FLOW_ITEM_TYPE_ETH,
599 RTE_FLOW_ITEM_TYPE_VLAN,
600 RTE_FLOW_ITEM_TYPE_IPV4,
601 RTE_FLOW_ITEM_TYPE_RAW,
602 RTE_FLOW_ITEM_TYPE_RAW,
603 RTE_FLOW_ITEM_TYPE_END,
606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
607 RTE_FLOW_ITEM_TYPE_ETH,
608 RTE_FLOW_ITEM_TYPE_VLAN,
609 RTE_FLOW_ITEM_TYPE_IPV4,
610 RTE_FLOW_ITEM_TYPE_RAW,
611 RTE_FLOW_ITEM_TYPE_RAW,
612 RTE_FLOW_ITEM_TYPE_RAW,
613 RTE_FLOW_ITEM_TYPE_END,
616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
617 RTE_FLOW_ITEM_TYPE_ETH,
618 RTE_FLOW_ITEM_TYPE_VLAN,
619 RTE_FLOW_ITEM_TYPE_IPV4,
620 RTE_FLOW_ITEM_TYPE_UDP,
621 RTE_FLOW_ITEM_TYPE_RAW,
622 RTE_FLOW_ITEM_TYPE_END,
625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
626 RTE_FLOW_ITEM_TYPE_ETH,
627 RTE_FLOW_ITEM_TYPE_VLAN,
628 RTE_FLOW_ITEM_TYPE_IPV4,
629 RTE_FLOW_ITEM_TYPE_UDP,
630 RTE_FLOW_ITEM_TYPE_RAW,
631 RTE_FLOW_ITEM_TYPE_RAW,
632 RTE_FLOW_ITEM_TYPE_END,
635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
636 RTE_FLOW_ITEM_TYPE_ETH,
637 RTE_FLOW_ITEM_TYPE_VLAN,
638 RTE_FLOW_ITEM_TYPE_IPV4,
639 RTE_FLOW_ITEM_TYPE_UDP,
640 RTE_FLOW_ITEM_TYPE_RAW,
641 RTE_FLOW_ITEM_TYPE_RAW,
642 RTE_FLOW_ITEM_TYPE_RAW,
643 RTE_FLOW_ITEM_TYPE_END,
646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
647 RTE_FLOW_ITEM_TYPE_ETH,
648 RTE_FLOW_ITEM_TYPE_VLAN,
649 RTE_FLOW_ITEM_TYPE_IPV4,
650 RTE_FLOW_ITEM_TYPE_TCP,
651 RTE_FLOW_ITEM_TYPE_RAW,
652 RTE_FLOW_ITEM_TYPE_END,
655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
656 RTE_FLOW_ITEM_TYPE_ETH,
657 RTE_FLOW_ITEM_TYPE_VLAN,
658 RTE_FLOW_ITEM_TYPE_IPV4,
659 RTE_FLOW_ITEM_TYPE_TCP,
660 RTE_FLOW_ITEM_TYPE_RAW,
661 RTE_FLOW_ITEM_TYPE_RAW,
662 RTE_FLOW_ITEM_TYPE_END,
665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
666 RTE_FLOW_ITEM_TYPE_ETH,
667 RTE_FLOW_ITEM_TYPE_VLAN,
668 RTE_FLOW_ITEM_TYPE_IPV4,
669 RTE_FLOW_ITEM_TYPE_TCP,
670 RTE_FLOW_ITEM_TYPE_RAW,
671 RTE_FLOW_ITEM_TYPE_RAW,
672 RTE_FLOW_ITEM_TYPE_RAW,
673 RTE_FLOW_ITEM_TYPE_END,
676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
677 RTE_FLOW_ITEM_TYPE_ETH,
678 RTE_FLOW_ITEM_TYPE_VLAN,
679 RTE_FLOW_ITEM_TYPE_IPV4,
680 RTE_FLOW_ITEM_TYPE_SCTP,
681 RTE_FLOW_ITEM_TYPE_RAW,
682 RTE_FLOW_ITEM_TYPE_END,
685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
686 RTE_FLOW_ITEM_TYPE_ETH,
687 RTE_FLOW_ITEM_TYPE_VLAN,
688 RTE_FLOW_ITEM_TYPE_IPV4,
689 RTE_FLOW_ITEM_TYPE_SCTP,
690 RTE_FLOW_ITEM_TYPE_RAW,
691 RTE_FLOW_ITEM_TYPE_RAW,
692 RTE_FLOW_ITEM_TYPE_END,
695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
696 RTE_FLOW_ITEM_TYPE_ETH,
697 RTE_FLOW_ITEM_TYPE_VLAN,
698 RTE_FLOW_ITEM_TYPE_IPV4,
699 RTE_FLOW_ITEM_TYPE_SCTP,
700 RTE_FLOW_ITEM_TYPE_RAW,
701 RTE_FLOW_ITEM_TYPE_RAW,
702 RTE_FLOW_ITEM_TYPE_RAW,
703 RTE_FLOW_ITEM_TYPE_END,
706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
707 RTE_FLOW_ITEM_TYPE_ETH,
708 RTE_FLOW_ITEM_TYPE_VLAN,
709 RTE_FLOW_ITEM_TYPE_IPV6,
710 RTE_FLOW_ITEM_TYPE_RAW,
711 RTE_FLOW_ITEM_TYPE_END,
714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
715 RTE_FLOW_ITEM_TYPE_ETH,
716 RTE_FLOW_ITEM_TYPE_VLAN,
717 RTE_FLOW_ITEM_TYPE_IPV6,
718 RTE_FLOW_ITEM_TYPE_RAW,
719 RTE_FLOW_ITEM_TYPE_RAW,
720 RTE_FLOW_ITEM_TYPE_END,
723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
724 RTE_FLOW_ITEM_TYPE_ETH,
725 RTE_FLOW_ITEM_TYPE_VLAN,
726 RTE_FLOW_ITEM_TYPE_IPV6,
727 RTE_FLOW_ITEM_TYPE_RAW,
728 RTE_FLOW_ITEM_TYPE_RAW,
729 RTE_FLOW_ITEM_TYPE_RAW,
730 RTE_FLOW_ITEM_TYPE_END,
733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
734 RTE_FLOW_ITEM_TYPE_ETH,
735 RTE_FLOW_ITEM_TYPE_VLAN,
736 RTE_FLOW_ITEM_TYPE_IPV6,
737 RTE_FLOW_ITEM_TYPE_UDP,
738 RTE_FLOW_ITEM_TYPE_RAW,
739 RTE_FLOW_ITEM_TYPE_END,
742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
743 RTE_FLOW_ITEM_TYPE_ETH,
744 RTE_FLOW_ITEM_TYPE_VLAN,
745 RTE_FLOW_ITEM_TYPE_IPV6,
746 RTE_FLOW_ITEM_TYPE_UDP,
747 RTE_FLOW_ITEM_TYPE_RAW,
748 RTE_FLOW_ITEM_TYPE_RAW,
749 RTE_FLOW_ITEM_TYPE_END,
752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
753 RTE_FLOW_ITEM_TYPE_ETH,
754 RTE_FLOW_ITEM_TYPE_VLAN,
755 RTE_FLOW_ITEM_TYPE_IPV6,
756 RTE_FLOW_ITEM_TYPE_UDP,
757 RTE_FLOW_ITEM_TYPE_RAW,
758 RTE_FLOW_ITEM_TYPE_RAW,
759 RTE_FLOW_ITEM_TYPE_RAW,
760 RTE_FLOW_ITEM_TYPE_END,
763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
764 RTE_FLOW_ITEM_TYPE_ETH,
765 RTE_FLOW_ITEM_TYPE_VLAN,
766 RTE_FLOW_ITEM_TYPE_IPV6,
767 RTE_FLOW_ITEM_TYPE_TCP,
768 RTE_FLOW_ITEM_TYPE_RAW,
769 RTE_FLOW_ITEM_TYPE_END,
772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
773 RTE_FLOW_ITEM_TYPE_ETH,
774 RTE_FLOW_ITEM_TYPE_VLAN,
775 RTE_FLOW_ITEM_TYPE_IPV6,
776 RTE_FLOW_ITEM_TYPE_TCP,
777 RTE_FLOW_ITEM_TYPE_RAW,
778 RTE_FLOW_ITEM_TYPE_RAW,
779 RTE_FLOW_ITEM_TYPE_END,
782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
783 RTE_FLOW_ITEM_TYPE_ETH,
784 RTE_FLOW_ITEM_TYPE_VLAN,
785 RTE_FLOW_ITEM_TYPE_IPV6,
786 RTE_FLOW_ITEM_TYPE_TCP,
787 RTE_FLOW_ITEM_TYPE_RAW,
788 RTE_FLOW_ITEM_TYPE_RAW,
789 RTE_FLOW_ITEM_TYPE_RAW,
790 RTE_FLOW_ITEM_TYPE_END,
793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
794 RTE_FLOW_ITEM_TYPE_ETH,
795 RTE_FLOW_ITEM_TYPE_VLAN,
796 RTE_FLOW_ITEM_TYPE_IPV6,
797 RTE_FLOW_ITEM_TYPE_SCTP,
798 RTE_FLOW_ITEM_TYPE_RAW,
799 RTE_FLOW_ITEM_TYPE_END,
802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
803 RTE_FLOW_ITEM_TYPE_ETH,
804 RTE_FLOW_ITEM_TYPE_VLAN,
805 RTE_FLOW_ITEM_TYPE_IPV6,
806 RTE_FLOW_ITEM_TYPE_SCTP,
807 RTE_FLOW_ITEM_TYPE_RAW,
808 RTE_FLOW_ITEM_TYPE_RAW,
809 RTE_FLOW_ITEM_TYPE_END,
812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
813 RTE_FLOW_ITEM_TYPE_ETH,
814 RTE_FLOW_ITEM_TYPE_VLAN,
815 RTE_FLOW_ITEM_TYPE_IPV6,
816 RTE_FLOW_ITEM_TYPE_SCTP,
817 RTE_FLOW_ITEM_TYPE_RAW,
818 RTE_FLOW_ITEM_TYPE_RAW,
819 RTE_FLOW_ITEM_TYPE_RAW,
820 RTE_FLOW_ITEM_TYPE_END,
823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
824 RTE_FLOW_ITEM_TYPE_ETH,
825 RTE_FLOW_ITEM_TYPE_IPV4,
826 RTE_FLOW_ITEM_TYPE_VF,
827 RTE_FLOW_ITEM_TYPE_END,
830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
831 RTE_FLOW_ITEM_TYPE_ETH,
832 RTE_FLOW_ITEM_TYPE_IPV4,
833 RTE_FLOW_ITEM_TYPE_UDP,
834 RTE_FLOW_ITEM_TYPE_VF,
835 RTE_FLOW_ITEM_TYPE_END,
838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
839 RTE_FLOW_ITEM_TYPE_ETH,
840 RTE_FLOW_ITEM_TYPE_IPV4,
841 RTE_FLOW_ITEM_TYPE_TCP,
842 RTE_FLOW_ITEM_TYPE_VF,
843 RTE_FLOW_ITEM_TYPE_END,
846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
847 RTE_FLOW_ITEM_TYPE_ETH,
848 RTE_FLOW_ITEM_TYPE_IPV4,
849 RTE_FLOW_ITEM_TYPE_SCTP,
850 RTE_FLOW_ITEM_TYPE_VF,
851 RTE_FLOW_ITEM_TYPE_END,
854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
855 RTE_FLOW_ITEM_TYPE_ETH,
856 RTE_FLOW_ITEM_TYPE_IPV6,
857 RTE_FLOW_ITEM_TYPE_VF,
858 RTE_FLOW_ITEM_TYPE_END,
861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
862 RTE_FLOW_ITEM_TYPE_ETH,
863 RTE_FLOW_ITEM_TYPE_IPV6,
864 RTE_FLOW_ITEM_TYPE_UDP,
865 RTE_FLOW_ITEM_TYPE_VF,
866 RTE_FLOW_ITEM_TYPE_END,
869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
870 RTE_FLOW_ITEM_TYPE_ETH,
871 RTE_FLOW_ITEM_TYPE_IPV6,
872 RTE_FLOW_ITEM_TYPE_TCP,
873 RTE_FLOW_ITEM_TYPE_VF,
874 RTE_FLOW_ITEM_TYPE_END,
877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
878 RTE_FLOW_ITEM_TYPE_ETH,
879 RTE_FLOW_ITEM_TYPE_IPV6,
880 RTE_FLOW_ITEM_TYPE_SCTP,
881 RTE_FLOW_ITEM_TYPE_VF,
882 RTE_FLOW_ITEM_TYPE_END,
885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
886 RTE_FLOW_ITEM_TYPE_ETH,
887 RTE_FLOW_ITEM_TYPE_RAW,
888 RTE_FLOW_ITEM_TYPE_VF,
889 RTE_FLOW_ITEM_TYPE_END,
892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
893 RTE_FLOW_ITEM_TYPE_ETH,
894 RTE_FLOW_ITEM_TYPE_RAW,
895 RTE_FLOW_ITEM_TYPE_RAW,
896 RTE_FLOW_ITEM_TYPE_VF,
897 RTE_FLOW_ITEM_TYPE_END,
900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
901 RTE_FLOW_ITEM_TYPE_ETH,
902 RTE_FLOW_ITEM_TYPE_RAW,
903 RTE_FLOW_ITEM_TYPE_RAW,
904 RTE_FLOW_ITEM_TYPE_RAW,
905 RTE_FLOW_ITEM_TYPE_VF,
906 RTE_FLOW_ITEM_TYPE_END,
909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
910 RTE_FLOW_ITEM_TYPE_ETH,
911 RTE_FLOW_ITEM_TYPE_IPV4,
912 RTE_FLOW_ITEM_TYPE_RAW,
913 RTE_FLOW_ITEM_TYPE_VF,
914 RTE_FLOW_ITEM_TYPE_END,
917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
918 RTE_FLOW_ITEM_TYPE_ETH,
919 RTE_FLOW_ITEM_TYPE_IPV4,
920 RTE_FLOW_ITEM_TYPE_RAW,
921 RTE_FLOW_ITEM_TYPE_RAW,
922 RTE_FLOW_ITEM_TYPE_VF,
923 RTE_FLOW_ITEM_TYPE_END,
926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
927 RTE_FLOW_ITEM_TYPE_ETH,
928 RTE_FLOW_ITEM_TYPE_IPV4,
929 RTE_FLOW_ITEM_TYPE_RAW,
930 RTE_FLOW_ITEM_TYPE_RAW,
931 RTE_FLOW_ITEM_TYPE_RAW,
932 RTE_FLOW_ITEM_TYPE_VF,
933 RTE_FLOW_ITEM_TYPE_END,
936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
937 RTE_FLOW_ITEM_TYPE_ETH,
938 RTE_FLOW_ITEM_TYPE_IPV4,
939 RTE_FLOW_ITEM_TYPE_UDP,
940 RTE_FLOW_ITEM_TYPE_RAW,
941 RTE_FLOW_ITEM_TYPE_VF,
942 RTE_FLOW_ITEM_TYPE_END,
945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
946 RTE_FLOW_ITEM_TYPE_ETH,
947 RTE_FLOW_ITEM_TYPE_IPV4,
948 RTE_FLOW_ITEM_TYPE_UDP,
949 RTE_FLOW_ITEM_TYPE_RAW,
950 RTE_FLOW_ITEM_TYPE_RAW,
951 RTE_FLOW_ITEM_TYPE_VF,
952 RTE_FLOW_ITEM_TYPE_END,
955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
956 RTE_FLOW_ITEM_TYPE_ETH,
957 RTE_FLOW_ITEM_TYPE_IPV4,
958 RTE_FLOW_ITEM_TYPE_UDP,
959 RTE_FLOW_ITEM_TYPE_RAW,
960 RTE_FLOW_ITEM_TYPE_RAW,
961 RTE_FLOW_ITEM_TYPE_RAW,
962 RTE_FLOW_ITEM_TYPE_VF,
963 RTE_FLOW_ITEM_TYPE_END,
966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
967 RTE_FLOW_ITEM_TYPE_ETH,
968 RTE_FLOW_ITEM_TYPE_IPV4,
969 RTE_FLOW_ITEM_TYPE_TCP,
970 RTE_FLOW_ITEM_TYPE_RAW,
971 RTE_FLOW_ITEM_TYPE_VF,
972 RTE_FLOW_ITEM_TYPE_END,
975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
976 RTE_FLOW_ITEM_TYPE_ETH,
977 RTE_FLOW_ITEM_TYPE_IPV4,
978 RTE_FLOW_ITEM_TYPE_TCP,
979 RTE_FLOW_ITEM_TYPE_RAW,
980 RTE_FLOW_ITEM_TYPE_RAW,
981 RTE_FLOW_ITEM_TYPE_VF,
982 RTE_FLOW_ITEM_TYPE_END,
985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
986 RTE_FLOW_ITEM_TYPE_ETH,
987 RTE_FLOW_ITEM_TYPE_IPV4,
988 RTE_FLOW_ITEM_TYPE_TCP,
989 RTE_FLOW_ITEM_TYPE_RAW,
990 RTE_FLOW_ITEM_TYPE_RAW,
991 RTE_FLOW_ITEM_TYPE_RAW,
992 RTE_FLOW_ITEM_TYPE_VF,
993 RTE_FLOW_ITEM_TYPE_END,
996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
997 RTE_FLOW_ITEM_TYPE_ETH,
998 RTE_FLOW_ITEM_TYPE_IPV4,
999 RTE_FLOW_ITEM_TYPE_SCTP,
1000 RTE_FLOW_ITEM_TYPE_RAW,
1001 RTE_FLOW_ITEM_TYPE_VF,
1002 RTE_FLOW_ITEM_TYPE_END,
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006 RTE_FLOW_ITEM_TYPE_ETH,
1007 RTE_FLOW_ITEM_TYPE_IPV4,
1008 RTE_FLOW_ITEM_TYPE_SCTP,
1009 RTE_FLOW_ITEM_TYPE_RAW,
1010 RTE_FLOW_ITEM_TYPE_RAW,
1011 RTE_FLOW_ITEM_TYPE_VF,
1012 RTE_FLOW_ITEM_TYPE_END,
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016 RTE_FLOW_ITEM_TYPE_ETH,
1017 RTE_FLOW_ITEM_TYPE_IPV4,
1018 RTE_FLOW_ITEM_TYPE_SCTP,
1019 RTE_FLOW_ITEM_TYPE_RAW,
1020 RTE_FLOW_ITEM_TYPE_RAW,
1021 RTE_FLOW_ITEM_TYPE_RAW,
1022 RTE_FLOW_ITEM_TYPE_VF,
1023 RTE_FLOW_ITEM_TYPE_END,
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027 RTE_FLOW_ITEM_TYPE_ETH,
1028 RTE_FLOW_ITEM_TYPE_IPV6,
1029 RTE_FLOW_ITEM_TYPE_RAW,
1030 RTE_FLOW_ITEM_TYPE_VF,
1031 RTE_FLOW_ITEM_TYPE_END,
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035 RTE_FLOW_ITEM_TYPE_ETH,
1036 RTE_FLOW_ITEM_TYPE_IPV6,
1037 RTE_FLOW_ITEM_TYPE_RAW,
1038 RTE_FLOW_ITEM_TYPE_RAW,
1039 RTE_FLOW_ITEM_TYPE_VF,
1040 RTE_FLOW_ITEM_TYPE_END,
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044 RTE_FLOW_ITEM_TYPE_ETH,
1045 RTE_FLOW_ITEM_TYPE_IPV6,
1046 RTE_FLOW_ITEM_TYPE_RAW,
1047 RTE_FLOW_ITEM_TYPE_RAW,
1048 RTE_FLOW_ITEM_TYPE_RAW,
1049 RTE_FLOW_ITEM_TYPE_VF,
1050 RTE_FLOW_ITEM_TYPE_END,
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054 RTE_FLOW_ITEM_TYPE_ETH,
1055 RTE_FLOW_ITEM_TYPE_IPV6,
1056 RTE_FLOW_ITEM_TYPE_UDP,
1057 RTE_FLOW_ITEM_TYPE_RAW,
1058 RTE_FLOW_ITEM_TYPE_VF,
1059 RTE_FLOW_ITEM_TYPE_END,
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063 RTE_FLOW_ITEM_TYPE_ETH,
1064 RTE_FLOW_ITEM_TYPE_IPV6,
1065 RTE_FLOW_ITEM_TYPE_UDP,
1066 RTE_FLOW_ITEM_TYPE_RAW,
1067 RTE_FLOW_ITEM_TYPE_RAW,
1068 RTE_FLOW_ITEM_TYPE_VF,
1069 RTE_FLOW_ITEM_TYPE_END,
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073 RTE_FLOW_ITEM_TYPE_ETH,
1074 RTE_FLOW_ITEM_TYPE_IPV6,
1075 RTE_FLOW_ITEM_TYPE_UDP,
1076 RTE_FLOW_ITEM_TYPE_RAW,
1077 RTE_FLOW_ITEM_TYPE_RAW,
1078 RTE_FLOW_ITEM_TYPE_RAW,
1079 RTE_FLOW_ITEM_TYPE_VF,
1080 RTE_FLOW_ITEM_TYPE_END,
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084 RTE_FLOW_ITEM_TYPE_ETH,
1085 RTE_FLOW_ITEM_TYPE_IPV6,
1086 RTE_FLOW_ITEM_TYPE_TCP,
1087 RTE_FLOW_ITEM_TYPE_RAW,
1088 RTE_FLOW_ITEM_TYPE_VF,
1089 RTE_FLOW_ITEM_TYPE_END,
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093 RTE_FLOW_ITEM_TYPE_ETH,
1094 RTE_FLOW_ITEM_TYPE_IPV6,
1095 RTE_FLOW_ITEM_TYPE_TCP,
1096 RTE_FLOW_ITEM_TYPE_RAW,
1097 RTE_FLOW_ITEM_TYPE_RAW,
1098 RTE_FLOW_ITEM_TYPE_VF,
1099 RTE_FLOW_ITEM_TYPE_END,
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103 RTE_FLOW_ITEM_TYPE_ETH,
1104 RTE_FLOW_ITEM_TYPE_IPV6,
1105 RTE_FLOW_ITEM_TYPE_TCP,
1106 RTE_FLOW_ITEM_TYPE_RAW,
1107 RTE_FLOW_ITEM_TYPE_RAW,
1108 RTE_FLOW_ITEM_TYPE_RAW,
1109 RTE_FLOW_ITEM_TYPE_VF,
1110 RTE_FLOW_ITEM_TYPE_END,
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114 RTE_FLOW_ITEM_TYPE_ETH,
1115 RTE_FLOW_ITEM_TYPE_IPV6,
1116 RTE_FLOW_ITEM_TYPE_SCTP,
1117 RTE_FLOW_ITEM_TYPE_RAW,
1118 RTE_FLOW_ITEM_TYPE_VF,
1119 RTE_FLOW_ITEM_TYPE_END,
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123 RTE_FLOW_ITEM_TYPE_ETH,
1124 RTE_FLOW_ITEM_TYPE_IPV6,
1125 RTE_FLOW_ITEM_TYPE_SCTP,
1126 RTE_FLOW_ITEM_TYPE_RAW,
1127 RTE_FLOW_ITEM_TYPE_RAW,
1128 RTE_FLOW_ITEM_TYPE_VF,
1129 RTE_FLOW_ITEM_TYPE_END,
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133 RTE_FLOW_ITEM_TYPE_ETH,
1134 RTE_FLOW_ITEM_TYPE_IPV6,
1135 RTE_FLOW_ITEM_TYPE_SCTP,
1136 RTE_FLOW_ITEM_TYPE_RAW,
1137 RTE_FLOW_ITEM_TYPE_RAW,
1138 RTE_FLOW_ITEM_TYPE_RAW,
1139 RTE_FLOW_ITEM_TYPE_VF,
1140 RTE_FLOW_ITEM_TYPE_END,
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144 RTE_FLOW_ITEM_TYPE_ETH,
1145 RTE_FLOW_ITEM_TYPE_VLAN,
1146 RTE_FLOW_ITEM_TYPE_VF,
1147 RTE_FLOW_ITEM_TYPE_END,
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151 RTE_FLOW_ITEM_TYPE_ETH,
1152 RTE_FLOW_ITEM_TYPE_VLAN,
1153 RTE_FLOW_ITEM_TYPE_IPV4,
1154 RTE_FLOW_ITEM_TYPE_VF,
1155 RTE_FLOW_ITEM_TYPE_END,
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159 RTE_FLOW_ITEM_TYPE_ETH,
1160 RTE_FLOW_ITEM_TYPE_VLAN,
1161 RTE_FLOW_ITEM_TYPE_IPV4,
1162 RTE_FLOW_ITEM_TYPE_UDP,
1163 RTE_FLOW_ITEM_TYPE_VF,
1164 RTE_FLOW_ITEM_TYPE_END,
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168 RTE_FLOW_ITEM_TYPE_ETH,
1169 RTE_FLOW_ITEM_TYPE_VLAN,
1170 RTE_FLOW_ITEM_TYPE_IPV4,
1171 RTE_FLOW_ITEM_TYPE_TCP,
1172 RTE_FLOW_ITEM_TYPE_VF,
1173 RTE_FLOW_ITEM_TYPE_END,
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177 RTE_FLOW_ITEM_TYPE_ETH,
1178 RTE_FLOW_ITEM_TYPE_VLAN,
1179 RTE_FLOW_ITEM_TYPE_IPV4,
1180 RTE_FLOW_ITEM_TYPE_SCTP,
1181 RTE_FLOW_ITEM_TYPE_VF,
1182 RTE_FLOW_ITEM_TYPE_END,
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186 RTE_FLOW_ITEM_TYPE_ETH,
1187 RTE_FLOW_ITEM_TYPE_VLAN,
1188 RTE_FLOW_ITEM_TYPE_IPV6,
1189 RTE_FLOW_ITEM_TYPE_VF,
1190 RTE_FLOW_ITEM_TYPE_END,
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194 RTE_FLOW_ITEM_TYPE_ETH,
1195 RTE_FLOW_ITEM_TYPE_VLAN,
1196 RTE_FLOW_ITEM_TYPE_IPV6,
1197 RTE_FLOW_ITEM_TYPE_UDP,
1198 RTE_FLOW_ITEM_TYPE_VF,
1199 RTE_FLOW_ITEM_TYPE_END,
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203 RTE_FLOW_ITEM_TYPE_ETH,
1204 RTE_FLOW_ITEM_TYPE_VLAN,
1205 RTE_FLOW_ITEM_TYPE_IPV6,
1206 RTE_FLOW_ITEM_TYPE_TCP,
1207 RTE_FLOW_ITEM_TYPE_VF,
1208 RTE_FLOW_ITEM_TYPE_END,
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212 RTE_FLOW_ITEM_TYPE_ETH,
1213 RTE_FLOW_ITEM_TYPE_VLAN,
1214 RTE_FLOW_ITEM_TYPE_IPV6,
1215 RTE_FLOW_ITEM_TYPE_SCTP,
1216 RTE_FLOW_ITEM_TYPE_VF,
1217 RTE_FLOW_ITEM_TYPE_END,
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221 RTE_FLOW_ITEM_TYPE_ETH,
1222 RTE_FLOW_ITEM_TYPE_VLAN,
1223 RTE_FLOW_ITEM_TYPE_RAW,
1224 RTE_FLOW_ITEM_TYPE_VF,
1225 RTE_FLOW_ITEM_TYPE_END,
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229 RTE_FLOW_ITEM_TYPE_ETH,
1230 RTE_FLOW_ITEM_TYPE_VLAN,
1231 RTE_FLOW_ITEM_TYPE_RAW,
1232 RTE_FLOW_ITEM_TYPE_RAW,
1233 RTE_FLOW_ITEM_TYPE_VF,
1234 RTE_FLOW_ITEM_TYPE_END,
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238 RTE_FLOW_ITEM_TYPE_ETH,
1239 RTE_FLOW_ITEM_TYPE_VLAN,
1240 RTE_FLOW_ITEM_TYPE_RAW,
1241 RTE_FLOW_ITEM_TYPE_RAW,
1242 RTE_FLOW_ITEM_TYPE_RAW,
1243 RTE_FLOW_ITEM_TYPE_VF,
1244 RTE_FLOW_ITEM_TYPE_END,
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248 RTE_FLOW_ITEM_TYPE_ETH,
1249 RTE_FLOW_ITEM_TYPE_VLAN,
1250 RTE_FLOW_ITEM_TYPE_IPV4,
1251 RTE_FLOW_ITEM_TYPE_RAW,
1252 RTE_FLOW_ITEM_TYPE_VF,
1253 RTE_FLOW_ITEM_TYPE_END,
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257 RTE_FLOW_ITEM_TYPE_ETH,
1258 RTE_FLOW_ITEM_TYPE_VLAN,
1259 RTE_FLOW_ITEM_TYPE_IPV4,
1260 RTE_FLOW_ITEM_TYPE_RAW,
1261 RTE_FLOW_ITEM_TYPE_RAW,
1262 RTE_FLOW_ITEM_TYPE_VF,
1263 RTE_FLOW_ITEM_TYPE_END,
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267 RTE_FLOW_ITEM_TYPE_ETH,
1268 RTE_FLOW_ITEM_TYPE_VLAN,
1269 RTE_FLOW_ITEM_TYPE_IPV4,
1270 RTE_FLOW_ITEM_TYPE_RAW,
1271 RTE_FLOW_ITEM_TYPE_RAW,
1272 RTE_FLOW_ITEM_TYPE_RAW,
1273 RTE_FLOW_ITEM_TYPE_VF,
1274 RTE_FLOW_ITEM_TYPE_END,
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278 RTE_FLOW_ITEM_TYPE_ETH,
1279 RTE_FLOW_ITEM_TYPE_VLAN,
1280 RTE_FLOW_ITEM_TYPE_IPV4,
1281 RTE_FLOW_ITEM_TYPE_UDP,
1282 RTE_FLOW_ITEM_TYPE_RAW,
1283 RTE_FLOW_ITEM_TYPE_VF,
1284 RTE_FLOW_ITEM_TYPE_END,
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288 RTE_FLOW_ITEM_TYPE_ETH,
1289 RTE_FLOW_ITEM_TYPE_VLAN,
1290 RTE_FLOW_ITEM_TYPE_IPV4,
1291 RTE_FLOW_ITEM_TYPE_UDP,
1292 RTE_FLOW_ITEM_TYPE_RAW,
1293 RTE_FLOW_ITEM_TYPE_RAW,
1294 RTE_FLOW_ITEM_TYPE_VF,
1295 RTE_FLOW_ITEM_TYPE_END,
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299 RTE_FLOW_ITEM_TYPE_ETH,
1300 RTE_FLOW_ITEM_TYPE_VLAN,
1301 RTE_FLOW_ITEM_TYPE_IPV4,
1302 RTE_FLOW_ITEM_TYPE_UDP,
1303 RTE_FLOW_ITEM_TYPE_RAW,
1304 RTE_FLOW_ITEM_TYPE_RAW,
1305 RTE_FLOW_ITEM_TYPE_RAW,
1306 RTE_FLOW_ITEM_TYPE_VF,
1307 RTE_FLOW_ITEM_TYPE_END,
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311 RTE_FLOW_ITEM_TYPE_ETH,
1312 RTE_FLOW_ITEM_TYPE_VLAN,
1313 RTE_FLOW_ITEM_TYPE_IPV4,
1314 RTE_FLOW_ITEM_TYPE_TCP,
1315 RTE_FLOW_ITEM_TYPE_RAW,
1316 RTE_FLOW_ITEM_TYPE_VF,
1317 RTE_FLOW_ITEM_TYPE_END,
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321 RTE_FLOW_ITEM_TYPE_ETH,
1322 RTE_FLOW_ITEM_TYPE_VLAN,
1323 RTE_FLOW_ITEM_TYPE_IPV4,
1324 RTE_FLOW_ITEM_TYPE_TCP,
1325 RTE_FLOW_ITEM_TYPE_RAW,
1326 RTE_FLOW_ITEM_TYPE_RAW,
1327 RTE_FLOW_ITEM_TYPE_VF,
1328 RTE_FLOW_ITEM_TYPE_END,
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332 RTE_FLOW_ITEM_TYPE_ETH,
1333 RTE_FLOW_ITEM_TYPE_VLAN,
1334 RTE_FLOW_ITEM_TYPE_IPV4,
1335 RTE_FLOW_ITEM_TYPE_TCP,
1336 RTE_FLOW_ITEM_TYPE_RAW,
1337 RTE_FLOW_ITEM_TYPE_RAW,
1338 RTE_FLOW_ITEM_TYPE_RAW,
1339 RTE_FLOW_ITEM_TYPE_VF,
1340 RTE_FLOW_ITEM_TYPE_END,
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344 RTE_FLOW_ITEM_TYPE_ETH,
1345 RTE_FLOW_ITEM_TYPE_VLAN,
1346 RTE_FLOW_ITEM_TYPE_IPV4,
1347 RTE_FLOW_ITEM_TYPE_SCTP,
1348 RTE_FLOW_ITEM_TYPE_RAW,
1349 RTE_FLOW_ITEM_TYPE_VF,
1350 RTE_FLOW_ITEM_TYPE_END,
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354 RTE_FLOW_ITEM_TYPE_ETH,
1355 RTE_FLOW_ITEM_TYPE_VLAN,
1356 RTE_FLOW_ITEM_TYPE_IPV4,
1357 RTE_FLOW_ITEM_TYPE_SCTP,
1358 RTE_FLOW_ITEM_TYPE_RAW,
1359 RTE_FLOW_ITEM_TYPE_RAW,
1360 RTE_FLOW_ITEM_TYPE_VF,
1361 RTE_FLOW_ITEM_TYPE_END,
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365 RTE_FLOW_ITEM_TYPE_ETH,
1366 RTE_FLOW_ITEM_TYPE_VLAN,
1367 RTE_FLOW_ITEM_TYPE_IPV4,
1368 RTE_FLOW_ITEM_TYPE_SCTP,
1369 RTE_FLOW_ITEM_TYPE_RAW,
1370 RTE_FLOW_ITEM_TYPE_RAW,
1371 RTE_FLOW_ITEM_TYPE_RAW,
1372 RTE_FLOW_ITEM_TYPE_VF,
1373 RTE_FLOW_ITEM_TYPE_END,
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377 RTE_FLOW_ITEM_TYPE_ETH,
1378 RTE_FLOW_ITEM_TYPE_VLAN,
1379 RTE_FLOW_ITEM_TYPE_IPV6,
1380 RTE_FLOW_ITEM_TYPE_RAW,
1381 RTE_FLOW_ITEM_TYPE_VF,
1382 RTE_FLOW_ITEM_TYPE_END,
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386 RTE_FLOW_ITEM_TYPE_ETH,
1387 RTE_FLOW_ITEM_TYPE_VLAN,
1388 RTE_FLOW_ITEM_TYPE_IPV6,
1389 RTE_FLOW_ITEM_TYPE_RAW,
1390 RTE_FLOW_ITEM_TYPE_RAW,
1391 RTE_FLOW_ITEM_TYPE_VF,
1392 RTE_FLOW_ITEM_TYPE_END,
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396 RTE_FLOW_ITEM_TYPE_ETH,
1397 RTE_FLOW_ITEM_TYPE_VLAN,
1398 RTE_FLOW_ITEM_TYPE_IPV6,
1399 RTE_FLOW_ITEM_TYPE_RAW,
1400 RTE_FLOW_ITEM_TYPE_RAW,
1401 RTE_FLOW_ITEM_TYPE_RAW,
1402 RTE_FLOW_ITEM_TYPE_VF,
1403 RTE_FLOW_ITEM_TYPE_END,
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407 RTE_FLOW_ITEM_TYPE_ETH,
1408 RTE_FLOW_ITEM_TYPE_VLAN,
1409 RTE_FLOW_ITEM_TYPE_IPV6,
1410 RTE_FLOW_ITEM_TYPE_UDP,
1411 RTE_FLOW_ITEM_TYPE_RAW,
1412 RTE_FLOW_ITEM_TYPE_VF,
1413 RTE_FLOW_ITEM_TYPE_END,
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417 RTE_FLOW_ITEM_TYPE_ETH,
1418 RTE_FLOW_ITEM_TYPE_VLAN,
1419 RTE_FLOW_ITEM_TYPE_IPV6,
1420 RTE_FLOW_ITEM_TYPE_UDP,
1421 RTE_FLOW_ITEM_TYPE_RAW,
1422 RTE_FLOW_ITEM_TYPE_RAW,
1423 RTE_FLOW_ITEM_TYPE_VF,
1424 RTE_FLOW_ITEM_TYPE_END,
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428 RTE_FLOW_ITEM_TYPE_ETH,
1429 RTE_FLOW_ITEM_TYPE_VLAN,
1430 RTE_FLOW_ITEM_TYPE_IPV6,
1431 RTE_FLOW_ITEM_TYPE_UDP,
1432 RTE_FLOW_ITEM_TYPE_RAW,
1433 RTE_FLOW_ITEM_TYPE_RAW,
1434 RTE_FLOW_ITEM_TYPE_RAW,
1435 RTE_FLOW_ITEM_TYPE_VF,
1436 RTE_FLOW_ITEM_TYPE_END,
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440 RTE_FLOW_ITEM_TYPE_ETH,
1441 RTE_FLOW_ITEM_TYPE_VLAN,
1442 RTE_FLOW_ITEM_TYPE_IPV6,
1443 RTE_FLOW_ITEM_TYPE_TCP,
1444 RTE_FLOW_ITEM_TYPE_RAW,
1445 RTE_FLOW_ITEM_TYPE_VF,
1446 RTE_FLOW_ITEM_TYPE_END,
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450 RTE_FLOW_ITEM_TYPE_ETH,
1451 RTE_FLOW_ITEM_TYPE_VLAN,
1452 RTE_FLOW_ITEM_TYPE_IPV6,
1453 RTE_FLOW_ITEM_TYPE_TCP,
1454 RTE_FLOW_ITEM_TYPE_RAW,
1455 RTE_FLOW_ITEM_TYPE_RAW,
1456 RTE_FLOW_ITEM_TYPE_VF,
1457 RTE_FLOW_ITEM_TYPE_END,
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461 RTE_FLOW_ITEM_TYPE_ETH,
1462 RTE_FLOW_ITEM_TYPE_VLAN,
1463 RTE_FLOW_ITEM_TYPE_IPV6,
1464 RTE_FLOW_ITEM_TYPE_TCP,
1465 RTE_FLOW_ITEM_TYPE_RAW,
1466 RTE_FLOW_ITEM_TYPE_RAW,
1467 RTE_FLOW_ITEM_TYPE_RAW,
1468 RTE_FLOW_ITEM_TYPE_VF,
1469 RTE_FLOW_ITEM_TYPE_END,
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473 RTE_FLOW_ITEM_TYPE_ETH,
1474 RTE_FLOW_ITEM_TYPE_VLAN,
1475 RTE_FLOW_ITEM_TYPE_IPV6,
1476 RTE_FLOW_ITEM_TYPE_SCTP,
1477 RTE_FLOW_ITEM_TYPE_RAW,
1478 RTE_FLOW_ITEM_TYPE_VF,
1479 RTE_FLOW_ITEM_TYPE_END,
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483 RTE_FLOW_ITEM_TYPE_ETH,
1484 RTE_FLOW_ITEM_TYPE_VLAN,
1485 RTE_FLOW_ITEM_TYPE_IPV6,
1486 RTE_FLOW_ITEM_TYPE_SCTP,
1487 RTE_FLOW_ITEM_TYPE_RAW,
1488 RTE_FLOW_ITEM_TYPE_RAW,
1489 RTE_FLOW_ITEM_TYPE_VF,
1490 RTE_FLOW_ITEM_TYPE_END,
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494 RTE_FLOW_ITEM_TYPE_ETH,
1495 RTE_FLOW_ITEM_TYPE_VLAN,
1496 RTE_FLOW_ITEM_TYPE_IPV6,
1497 RTE_FLOW_ITEM_TYPE_SCTP,
1498 RTE_FLOW_ITEM_TYPE_RAW,
1499 RTE_FLOW_ITEM_TYPE_RAW,
1500 RTE_FLOW_ITEM_TYPE_RAW,
1501 RTE_FLOW_ITEM_TYPE_VF,
1502 RTE_FLOW_ITEM_TYPE_END,
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507 RTE_FLOW_ITEM_TYPE_ETH,
1508 RTE_FLOW_ITEM_TYPE_IPV4,
1509 RTE_FLOW_ITEM_TYPE_UDP,
1510 RTE_FLOW_ITEM_TYPE_VXLAN,
1511 RTE_FLOW_ITEM_TYPE_ETH,
1512 RTE_FLOW_ITEM_TYPE_END,
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516 RTE_FLOW_ITEM_TYPE_ETH,
1517 RTE_FLOW_ITEM_TYPE_IPV6,
1518 RTE_FLOW_ITEM_TYPE_UDP,
1519 RTE_FLOW_ITEM_TYPE_VXLAN,
1520 RTE_FLOW_ITEM_TYPE_ETH,
1521 RTE_FLOW_ITEM_TYPE_END,
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525 RTE_FLOW_ITEM_TYPE_ETH,
1526 RTE_FLOW_ITEM_TYPE_IPV4,
1527 RTE_FLOW_ITEM_TYPE_UDP,
1528 RTE_FLOW_ITEM_TYPE_VXLAN,
1529 RTE_FLOW_ITEM_TYPE_ETH,
1530 RTE_FLOW_ITEM_TYPE_VLAN,
1531 RTE_FLOW_ITEM_TYPE_END,
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535 RTE_FLOW_ITEM_TYPE_ETH,
1536 RTE_FLOW_ITEM_TYPE_IPV6,
1537 RTE_FLOW_ITEM_TYPE_UDP,
1538 RTE_FLOW_ITEM_TYPE_VXLAN,
1539 RTE_FLOW_ITEM_TYPE_ETH,
1540 RTE_FLOW_ITEM_TYPE_VLAN,
1541 RTE_FLOW_ITEM_TYPE_END,
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545 RTE_FLOW_ITEM_TYPE_ETH,
1546 RTE_FLOW_ITEM_TYPE_IPV4,
1547 RTE_FLOW_ITEM_TYPE_NVGRE,
1548 RTE_FLOW_ITEM_TYPE_ETH,
1549 RTE_FLOW_ITEM_TYPE_END,
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553 RTE_FLOW_ITEM_TYPE_ETH,
1554 RTE_FLOW_ITEM_TYPE_IPV6,
1555 RTE_FLOW_ITEM_TYPE_NVGRE,
1556 RTE_FLOW_ITEM_TYPE_ETH,
1557 RTE_FLOW_ITEM_TYPE_END,
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561 RTE_FLOW_ITEM_TYPE_ETH,
1562 RTE_FLOW_ITEM_TYPE_IPV4,
1563 RTE_FLOW_ITEM_TYPE_NVGRE,
1564 RTE_FLOW_ITEM_TYPE_ETH,
1565 RTE_FLOW_ITEM_TYPE_VLAN,
1566 RTE_FLOW_ITEM_TYPE_END,
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570 RTE_FLOW_ITEM_TYPE_ETH,
1571 RTE_FLOW_ITEM_TYPE_IPV6,
1572 RTE_FLOW_ITEM_TYPE_NVGRE,
1573 RTE_FLOW_ITEM_TYPE_ETH,
1574 RTE_FLOW_ITEM_TYPE_VLAN,
1575 RTE_FLOW_ITEM_TYPE_END,
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579 RTE_FLOW_ITEM_TYPE_ETH,
1580 RTE_FLOW_ITEM_TYPE_IPV4,
1581 RTE_FLOW_ITEM_TYPE_UDP,
1582 RTE_FLOW_ITEM_TYPE_MPLS,
1583 RTE_FLOW_ITEM_TYPE_END,
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587 RTE_FLOW_ITEM_TYPE_ETH,
1588 RTE_FLOW_ITEM_TYPE_IPV6,
1589 RTE_FLOW_ITEM_TYPE_UDP,
1590 RTE_FLOW_ITEM_TYPE_MPLS,
1591 RTE_FLOW_ITEM_TYPE_END,
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595 RTE_FLOW_ITEM_TYPE_ETH,
1596 RTE_FLOW_ITEM_TYPE_IPV4,
1597 RTE_FLOW_ITEM_TYPE_GRE,
1598 RTE_FLOW_ITEM_TYPE_MPLS,
1599 RTE_FLOW_ITEM_TYPE_END,
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603 RTE_FLOW_ITEM_TYPE_ETH,
1604 RTE_FLOW_ITEM_TYPE_IPV6,
1605 RTE_FLOW_ITEM_TYPE_GRE,
1606 RTE_FLOW_ITEM_TYPE_MPLS,
1607 RTE_FLOW_ITEM_TYPE_END,
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611 RTE_FLOW_ITEM_TYPE_ETH,
1612 RTE_FLOW_ITEM_TYPE_VLAN,
1613 RTE_FLOW_ITEM_TYPE_VLAN,
1614 RTE_FLOW_ITEM_TYPE_END,
1617 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1619 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1620 /* FDIR - support default flow type without flexible payload*/
1621 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1622 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1623 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1624 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1625 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1626 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1627 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1628 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1629 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1630 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1631 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1632 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1633 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1634 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1635 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1636 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1637 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1638 /* FDIR - support default flow type with flexible payload */
1639 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1640 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1641 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1642 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1643 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1644 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1645 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1646 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1647 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1648 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1649 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1650 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1651 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1652 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1653 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1654 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1655 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1656 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1657 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1658 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1659 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1660 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1661 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1662 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1663 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1664 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1665 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1666 /* FDIR - support single vlan input set */
1667 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1668 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1669 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1703 /* FDIR - support VF item */
1704 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1705 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1729 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1730 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1731 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1732 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1751 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1752 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1776 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1777 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1778 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1779 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1781 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1782 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1783 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1784 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1785 /* MPLSoUDP & MPLSoGRE */
1786 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1787 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1788 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1789 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1791 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1792 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1793 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1794 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1796 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1799 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1801 act = actions + index; \
1802 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1804 act = actions + index; \
1808 /* Find the first VOID or non-VOID item pointer */
1809 static const struct rte_flow_item *
1810 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1814 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1816 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1818 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1826 /* Skip all VOID items of the pattern */
1828 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1829 const struct rte_flow_item *pattern)
1831 uint32_t cpy_count = 0;
1832 const struct rte_flow_item *pb = pattern, *pe = pattern;
1835 /* Find a non-void item first */
1836 pb = i40e_find_first_item(pb, false);
1837 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1842 /* Find a void item */
1843 pe = i40e_find_first_item(pb + 1, true);
1845 cpy_count = pe - pb;
1846 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1850 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1857 /* Copy the END item. */
1858 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1861 /* Check if the pattern matches a supported item type array */
1863 i40e_match_pattern(enum rte_flow_item_type *item_array,
1864 struct rte_flow_item *pattern)
1866 struct rte_flow_item *item = pattern;
1868 while ((*item_array == item->type) &&
1869 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1874 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1875 item->type == RTE_FLOW_ITEM_TYPE_END);
1878 /* Find if there's parse filter function matched */
1879 static parse_filter_t
1880 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1882 parse_filter_t parse_filter = NULL;
1885 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1886 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1888 parse_filter = i40e_supported_patterns[i].parse_filter;
1895 return parse_filter;
1898 /* Parse attributes */
1900 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1901 struct rte_flow_error *error)
1903 /* Must be input direction */
1904 if (!attr->ingress) {
1905 rte_flow_error_set(error, EINVAL,
1906 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1907 attr, "Only support ingress.");
1913 rte_flow_error_set(error, EINVAL,
1914 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1915 attr, "Not support egress.");
1920 if (attr->priority) {
1921 rte_flow_error_set(error, EINVAL,
1922 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1923 attr, "Not support priority.");
1929 rte_flow_error_set(error, EINVAL,
1930 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1931 attr, "Not support group.");
1939 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1952 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1955 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1960 /* 1. Last in item should be NULL as range is not supported.
1961 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1962 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1963 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1965 * 5. Ether_type mask should be 0xFFFF.
1968 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1969 const struct rte_flow_item *pattern,
1970 struct rte_flow_error *error,
1971 struct rte_eth_ethertype_filter *filter)
1973 const struct rte_flow_item *item = pattern;
1974 const struct rte_flow_item_eth *eth_spec;
1975 const struct rte_flow_item_eth *eth_mask;
1976 enum rte_flow_item_type item_type;
1977 uint16_t outer_tpid;
1979 outer_tpid = i40e_get_outer_vlan(dev);
1981 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1983 rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ITEM,
1986 "Not support range");
1989 item_type = item->type;
1990 switch (item_type) {
1991 case RTE_FLOW_ITEM_TYPE_ETH:
1992 eth_spec = item->spec;
1993 eth_mask = item->mask;
1994 /* Get the MAC info. */
1995 if (!eth_spec || !eth_mask) {
1996 rte_flow_error_set(error, EINVAL,
1997 RTE_FLOW_ERROR_TYPE_ITEM,
1999 "NULL ETH spec/mask");
2003 /* Mask bits of source MAC address must be full of 0.
2004 * Mask bits of destination MAC address must be full
2005 * of 1 or full of 0.
2007 if (!is_zero_ether_addr(ð_mask->src) ||
2008 (!is_zero_ether_addr(ð_mask->dst) &&
2009 !is_broadcast_ether_addr(ð_mask->dst))) {
2010 rte_flow_error_set(error, EINVAL,
2011 RTE_FLOW_ERROR_TYPE_ITEM,
2013 "Invalid MAC_addr mask");
2017 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2018 rte_flow_error_set(error, EINVAL,
2019 RTE_FLOW_ERROR_TYPE_ITEM,
2021 "Invalid ethertype mask");
2025 /* If mask bits of destination MAC address
2026 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2028 if (is_broadcast_ether_addr(ð_mask->dst)) {
2029 filter->mac_addr = eth_spec->dst;
2030 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2032 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2034 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2036 if (filter->ether_type == ETHER_TYPE_IPv4 ||
2037 filter->ether_type == ETHER_TYPE_IPv6 ||
2038 filter->ether_type == ETHER_TYPE_LLDP ||
2039 filter->ether_type == outer_tpid) {
2040 rte_flow_error_set(error, EINVAL,
2041 RTE_FLOW_ERROR_TYPE_ITEM,
2043 "Unsupported ether_type in"
2044 " control packet filter.");
2056 /* Ethertype action only supports QUEUE or DROP. */
2058 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2059 const struct rte_flow_action *actions,
2060 struct rte_flow_error *error,
2061 struct rte_eth_ethertype_filter *filter)
2063 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064 const struct rte_flow_action *act;
2065 const struct rte_flow_action_queue *act_q;
2068 /* Check if the first non-void action is QUEUE or DROP. */
2069 NEXT_ITEM_OF_ACTION(act, actions, index);
2070 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2071 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2072 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2073 act, "Not supported action.");
2077 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2079 filter->queue = act_q->index;
2080 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2081 rte_flow_error_set(error, EINVAL,
2082 RTE_FLOW_ERROR_TYPE_ACTION,
2083 act, "Invalid queue ID for"
2084 " ethertype_filter.");
2088 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2091 /* Check if the next non-void item is END */
2093 NEXT_ITEM_OF_ACTION(act, actions, index);
2094 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2095 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2096 act, "Not supported action.");
2104 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2105 const struct rte_flow_attr *attr,
2106 const struct rte_flow_item pattern[],
2107 const struct rte_flow_action actions[],
2108 struct rte_flow_error *error,
2109 union i40e_filter_t *filter)
2111 struct rte_eth_ethertype_filter *ethertype_filter =
2112 &filter->ethertype_filter;
2115 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2120 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2125 ret = i40e_flow_parse_attr(attr, error);
2129 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2135 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2136 const struct rte_flow_item_raw *raw_spec,
2137 struct rte_flow_error *error)
2139 if (!raw_spec->relative) {
2140 rte_flow_error_set(error, EINVAL,
2141 RTE_FLOW_ERROR_TYPE_ITEM,
2143 "Relative should be 1.");
2147 if (raw_spec->offset % sizeof(uint16_t)) {
2148 rte_flow_error_set(error, EINVAL,
2149 RTE_FLOW_ERROR_TYPE_ITEM,
2151 "Offset should be even.");
2155 if (raw_spec->search || raw_spec->limit) {
2156 rte_flow_error_set(error, EINVAL,
2157 RTE_FLOW_ERROR_TYPE_ITEM,
2159 "search or limit is not supported.");
2163 if (raw_spec->offset < 0) {
2164 rte_flow_error_set(error, EINVAL,
2165 RTE_FLOW_ERROR_TYPE_ITEM,
2167 "Offset should be non-negative.");
2174 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2175 struct i40e_fdir_flex_pit *flex_pit,
2176 enum i40e_flxpld_layer_idx layer_idx,
2181 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2182 /* Check if the configuration is conflicted */
2183 if (pf->fdir.flex_pit_flag[layer_idx] &&
2184 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2185 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2186 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2189 /* Check if the configuration exists. */
2190 if (pf->fdir.flex_pit_flag[layer_idx] &&
2191 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2192 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2193 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2196 pf->fdir.flex_set[field_idx].src_offset =
2197 flex_pit->src_offset;
2198 pf->fdir.flex_set[field_idx].size =
2200 pf->fdir.flex_set[field_idx].dst_offset =
2201 flex_pit->dst_offset;
2207 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2208 enum i40e_filter_pctype pctype,
2211 struct i40e_fdir_flex_mask flex_mask;
2213 uint8_t i, nb_bitmask = 0;
2215 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2216 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2217 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2219 flex_mask.word_mask |=
2220 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2221 if (mask_tmp != UINT16_MAX) {
2222 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2223 flex_mask.bitmask[nb_bitmask].offset =
2224 i / sizeof(uint16_t);
2226 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2231 flex_mask.nb_bitmask = nb_bitmask;
2233 if (pf->fdir.flex_mask_flag[pctype] &&
2234 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2235 sizeof(struct i40e_fdir_flex_mask))))
2237 else if (pf->fdir.flex_mask_flag[pctype] &&
2238 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2239 sizeof(struct i40e_fdir_flex_mask))))
2242 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2243 sizeof(struct i40e_fdir_flex_mask));
2248 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2249 enum i40e_flxpld_layer_idx layer_idx,
2252 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2253 uint32_t flx_pit, flx_ort;
2255 uint16_t min_next_off = 0; /* in words */
2259 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2260 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2261 (layer_idx * I40E_MAX_FLXPLD_FIED);
2262 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2263 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
2267 for (i = 0; i < raw_id; i++) {
2268 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2269 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2270 pf->fdir.flex_set[field_idx].size,
2271 pf->fdir.flex_set[field_idx].dst_offset);
2273 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2274 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2275 pf->fdir.flex_set[field_idx].size;
2278 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2279 /* set the non-used register obeying register's constrain */
2280 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2281 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2282 NONUSE_FLX_PIT_DEST_OFF);
2283 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2287 pf->fdir.flex_pit_flag[layer_idx] = 1;
2291 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2292 enum i40e_filter_pctype pctype)
2294 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2295 struct i40e_fdir_flex_mask *flex_mask;
2296 uint32_t flxinset, fd_mask;
2300 flex_mask = &pf->fdir.flex_mask[pctype];
2301 flxinset = (flex_mask->word_mask <<
2302 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2303 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2304 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2306 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2307 fd_mask = (flex_mask->bitmask[i].mask <<
2308 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2309 I40E_PRTQF_FD_MSK_MASK_MASK;
2310 fd_mask |= ((flex_mask->bitmask[i].offset +
2311 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2312 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2313 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2314 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2317 pf->fdir.flex_mask_flag[pctype] = 1;
2321 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2322 enum i40e_filter_pctype pctype,
2325 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2326 uint64_t inset_reg = 0;
2327 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2330 /* Check if the input set is valid */
2331 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2333 PMD_DRV_LOG(ERR, "Invalid input set");
2337 /* Check if the configuration is conflicted */
2338 if (pf->fdir.inset_flag[pctype] &&
2339 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2342 if (pf->fdir.inset_flag[pctype] &&
2343 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2346 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2347 I40E_INSET_MASK_NUM_REG);
2351 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2353 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2354 (uint32_t)(inset_reg & UINT32_MAX));
2355 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2356 (uint32_t)((inset_reg >>
2357 I40E_32_BIT_WIDTH) & UINT32_MAX));
2359 for (i = 0; i < num; i++)
2360 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2363 /*clear unused mask registers of the pctype */
2364 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2365 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2366 I40E_WRITE_FLUSH(hw);
2368 pf->fdir.input_set[pctype] = input_set;
2369 pf->fdir.inset_flag[pctype] = 1;
2374 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2375 enum rte_flow_item_type item_type,
2376 struct i40e_fdir_filter_conf *filter)
2378 struct i40e_customized_pctype *cus_pctype = NULL;
2380 switch (item_type) {
2381 case RTE_FLOW_ITEM_TYPE_GTPC:
2382 cus_pctype = i40e_find_customized_pctype(pf,
2383 I40E_CUSTOMIZED_GTPC);
2385 case RTE_FLOW_ITEM_TYPE_GTPU:
2386 if (!filter->input.flow_ext.inner_ip)
2387 cus_pctype = i40e_find_customized_pctype(pf,
2388 I40E_CUSTOMIZED_GTPU);
2389 else if (filter->input.flow_ext.iip_type ==
2390 I40E_FDIR_IPTYPE_IPV4)
2391 cus_pctype = i40e_find_customized_pctype(pf,
2392 I40E_CUSTOMIZED_GTPU_IPV4);
2393 else if (filter->input.flow_ext.iip_type ==
2394 I40E_FDIR_IPTYPE_IPV6)
2395 cus_pctype = i40e_find_customized_pctype(pf,
2396 I40E_CUSTOMIZED_GTPU_IPV6);
2399 PMD_DRV_LOG(ERR, "Unsupported item type");
2404 return cus_pctype->pctype;
2406 return I40E_FILTER_PCTYPE_INVALID;
2409 /* 1. Last in item should be NULL as range is not supported.
2410 * 2. Supported patterns: refer to array i40e_supported_patterns.
2411 * 3. Default supported flow type and input set: refer to array
2412 * valid_fdir_inset_table in i40e_ethdev.c.
2413 * 4. Mask of fields which need to be matched should be
2415 * 5. Mask of fields which needn't to be matched should be
2417 * 6. GTP profile supports GTPv1 only.
2418 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2421 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2422 const struct rte_flow_item *pattern,
2423 struct rte_flow_error *error,
2424 struct i40e_fdir_filter_conf *filter)
2426 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2427 const struct rte_flow_item *item = pattern;
2428 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2429 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2430 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2431 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2432 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2433 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2434 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2435 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2436 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2437 const struct rte_flow_item_vf *vf_spec;
2440 uint64_t input_set = I40E_INSET_NONE;
2442 enum rte_flow_item_type item_type;
2443 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2444 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2446 uint8_t ipv6_addr_mask[16] = {
2447 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2448 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2449 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2451 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2452 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2453 struct i40e_fdir_flex_pit flex_pit;
2454 uint8_t next_dst_off = 0;
2455 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2457 bool cfg_flex_pit = true;
2458 bool cfg_flex_msk = true;
2459 uint16_t outer_tpid;
2460 uint16_t ether_type;
2461 uint32_t vtc_flow_cpu;
2462 bool outer_ip = true;
2465 memset(off_arr, 0, sizeof(off_arr));
2466 memset(len_arr, 0, sizeof(len_arr));
2467 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2468 outer_tpid = i40e_get_outer_vlan(dev);
2469 filter->input.flow_ext.customized_pctype = false;
2470 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2472 rte_flow_error_set(error, EINVAL,
2473 RTE_FLOW_ERROR_TYPE_ITEM,
2475 "Not support range");
2478 item_type = item->type;
2479 switch (item_type) {
2480 case RTE_FLOW_ITEM_TYPE_ETH:
2481 eth_spec = item->spec;
2482 eth_mask = item->mask;
2484 if (eth_spec && eth_mask) {
2485 if (!is_zero_ether_addr(ð_mask->src) ||
2486 !is_zero_ether_addr(ð_mask->dst)) {
2487 rte_flow_error_set(error, EINVAL,
2488 RTE_FLOW_ERROR_TYPE_ITEM,
2490 "Invalid MAC_addr mask.");
2494 if ((eth_mask->type & UINT16_MAX) ==
2496 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2497 filter->input.flow.l2_flow.ether_type =
2501 ether_type = rte_be_to_cpu_16(eth_spec->type);
2502 if (ether_type == ETHER_TYPE_IPv4 ||
2503 ether_type == ETHER_TYPE_IPv6 ||
2504 ether_type == ETHER_TYPE_ARP ||
2505 ether_type == outer_tpid) {
2506 rte_flow_error_set(error, EINVAL,
2507 RTE_FLOW_ERROR_TYPE_ITEM,
2509 "Unsupported ether_type.");
2514 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2515 layer_idx = I40E_FLXPLD_L2_IDX;
2518 case RTE_FLOW_ITEM_TYPE_VLAN:
2519 vlan_spec = item->spec;
2520 vlan_mask = item->mask;
2521 if (vlan_spec && vlan_mask) {
2522 if (vlan_mask->tci ==
2523 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2524 input_set |= I40E_INSET_VLAN_INNER;
2525 filter->input.flow_ext.vlan_tci =
2530 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2531 layer_idx = I40E_FLXPLD_L2_IDX;
2534 case RTE_FLOW_ITEM_TYPE_IPV4:
2535 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2536 ipv4_spec = item->spec;
2537 ipv4_mask = item->mask;
2538 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2539 layer_idx = I40E_FLXPLD_L3_IDX;
2541 if (ipv4_spec && ipv4_mask && outer_ip) {
2542 /* Check IPv4 mask and update input set */
2543 if (ipv4_mask->hdr.version_ihl ||
2544 ipv4_mask->hdr.total_length ||
2545 ipv4_mask->hdr.packet_id ||
2546 ipv4_mask->hdr.fragment_offset ||
2547 ipv4_mask->hdr.hdr_checksum) {
2548 rte_flow_error_set(error, EINVAL,
2549 RTE_FLOW_ERROR_TYPE_ITEM,
2551 "Invalid IPv4 mask.");
2555 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2556 input_set |= I40E_INSET_IPV4_SRC;
2557 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2558 input_set |= I40E_INSET_IPV4_DST;
2559 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2560 input_set |= I40E_INSET_IPV4_TOS;
2561 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2562 input_set |= I40E_INSET_IPV4_TTL;
2563 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2564 input_set |= I40E_INSET_IPV4_PROTO;
2566 /* Check if it is fragment. */
2567 frag_off = ipv4_spec->hdr.fragment_offset;
2568 frag_off = rte_be_to_cpu_16(frag_off);
2569 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2570 frag_off & IPV4_HDR_MF_FLAG)
2571 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2573 /* Get the filter info */
2574 filter->input.flow.ip4_flow.proto =
2575 ipv4_spec->hdr.next_proto_id;
2576 filter->input.flow.ip4_flow.tos =
2577 ipv4_spec->hdr.type_of_service;
2578 filter->input.flow.ip4_flow.ttl =
2579 ipv4_spec->hdr.time_to_live;
2580 filter->input.flow.ip4_flow.src_ip =
2581 ipv4_spec->hdr.src_addr;
2582 filter->input.flow.ip4_flow.dst_ip =
2583 ipv4_spec->hdr.dst_addr;
2584 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2585 filter->input.flow_ext.inner_ip = true;
2586 filter->input.flow_ext.iip_type =
2587 I40E_FDIR_IPTYPE_IPV4;
2588 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2589 rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM,
2592 "Invalid inner IPv4 mask.");
2600 case RTE_FLOW_ITEM_TYPE_IPV6:
2601 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2602 ipv6_spec = item->spec;
2603 ipv6_mask = item->mask;
2604 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2605 layer_idx = I40E_FLXPLD_L3_IDX;
2607 if (ipv6_spec && ipv6_mask && outer_ip) {
2608 /* Check IPv6 mask and update input set */
2609 if (ipv6_mask->hdr.payload_len) {
2610 rte_flow_error_set(error, EINVAL,
2611 RTE_FLOW_ERROR_TYPE_ITEM,
2613 "Invalid IPv6 mask");
2617 if (!memcmp(ipv6_mask->hdr.src_addr,
2619 RTE_DIM(ipv6_mask->hdr.src_addr)))
2620 input_set |= I40E_INSET_IPV6_SRC;
2621 if (!memcmp(ipv6_mask->hdr.dst_addr,
2623 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2624 input_set |= I40E_INSET_IPV6_DST;
2626 if ((ipv6_mask->hdr.vtc_flow &
2627 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2628 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2629 input_set |= I40E_INSET_IPV6_TC;
2630 if (ipv6_mask->hdr.proto == UINT8_MAX)
2631 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2632 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2633 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2635 /* Get filter info */
2637 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2638 filter->input.flow.ipv6_flow.tc =
2639 (uint8_t)(vtc_flow_cpu >>
2640 I40E_FDIR_IPv6_TC_OFFSET);
2641 filter->input.flow.ipv6_flow.proto =
2642 ipv6_spec->hdr.proto;
2643 filter->input.flow.ipv6_flow.hop_limits =
2644 ipv6_spec->hdr.hop_limits;
2646 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2647 ipv6_spec->hdr.src_addr, 16);
2648 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2649 ipv6_spec->hdr.dst_addr, 16);
2651 /* Check if it is fragment. */
2652 if (ipv6_spec->hdr.proto ==
2653 I40E_IPV6_FRAG_HEADER)
2654 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2655 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2656 filter->input.flow_ext.inner_ip = true;
2657 filter->input.flow_ext.iip_type =
2658 I40E_FDIR_IPTYPE_IPV6;
2659 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2660 rte_flow_error_set(error, EINVAL,
2661 RTE_FLOW_ERROR_TYPE_ITEM,
2663 "Invalid inner IPv6 mask");
2670 case RTE_FLOW_ITEM_TYPE_TCP:
2671 tcp_spec = item->spec;
2672 tcp_mask = item->mask;
2674 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2676 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2677 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2679 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2680 if (tcp_spec && tcp_mask) {
2681 /* Check TCP mask and update input set */
2682 if (tcp_mask->hdr.sent_seq ||
2683 tcp_mask->hdr.recv_ack ||
2684 tcp_mask->hdr.data_off ||
2685 tcp_mask->hdr.tcp_flags ||
2686 tcp_mask->hdr.rx_win ||
2687 tcp_mask->hdr.cksum ||
2688 tcp_mask->hdr.tcp_urp) {
2689 rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ITEM,
2692 "Invalid TCP mask");
2696 if (tcp_mask->hdr.src_port == UINT16_MAX)
2697 input_set |= I40E_INSET_SRC_PORT;
2698 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2699 input_set |= I40E_INSET_DST_PORT;
2701 /* Get filter info */
2702 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2703 filter->input.flow.tcp4_flow.src_port =
2704 tcp_spec->hdr.src_port;
2705 filter->input.flow.tcp4_flow.dst_port =
2706 tcp_spec->hdr.dst_port;
2707 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2708 filter->input.flow.tcp6_flow.src_port =
2709 tcp_spec->hdr.src_port;
2710 filter->input.flow.tcp6_flow.dst_port =
2711 tcp_spec->hdr.dst_port;
2715 layer_idx = I40E_FLXPLD_L4_IDX;
2718 case RTE_FLOW_ITEM_TYPE_UDP:
2719 udp_spec = item->spec;
2720 udp_mask = item->mask;
2722 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2724 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2725 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2727 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2729 if (udp_spec && udp_mask) {
2730 /* Check UDP mask and update input set*/
2731 if (udp_mask->hdr.dgram_len ||
2732 udp_mask->hdr.dgram_cksum) {
2733 rte_flow_error_set(error, EINVAL,
2734 RTE_FLOW_ERROR_TYPE_ITEM,
2736 "Invalid UDP mask");
2740 if (udp_mask->hdr.src_port == UINT16_MAX)
2741 input_set |= I40E_INSET_SRC_PORT;
2742 if (udp_mask->hdr.dst_port == UINT16_MAX)
2743 input_set |= I40E_INSET_DST_PORT;
2745 /* Get filter info */
2746 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2747 filter->input.flow.udp4_flow.src_port =
2748 udp_spec->hdr.src_port;
2749 filter->input.flow.udp4_flow.dst_port =
2750 udp_spec->hdr.dst_port;
2751 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2752 filter->input.flow.udp6_flow.src_port =
2753 udp_spec->hdr.src_port;
2754 filter->input.flow.udp6_flow.dst_port =
2755 udp_spec->hdr.dst_port;
2759 layer_idx = I40E_FLXPLD_L4_IDX;
2762 case RTE_FLOW_ITEM_TYPE_GTPC:
2763 case RTE_FLOW_ITEM_TYPE_GTPU:
2764 if (!pf->gtp_support) {
2765 rte_flow_error_set(error, EINVAL,
2766 RTE_FLOW_ERROR_TYPE_ITEM,
2768 "Unsupported protocol");
2772 gtp_spec = item->spec;
2773 gtp_mask = item->mask;
2775 if (gtp_spec && gtp_mask) {
2776 if (gtp_mask->v_pt_rsv_flags ||
2777 gtp_mask->msg_type ||
2778 gtp_mask->msg_len ||
2779 gtp_mask->teid != UINT32_MAX) {
2780 rte_flow_error_set(error, EINVAL,
2781 RTE_FLOW_ERROR_TYPE_ITEM,
2783 "Invalid GTP mask");
2787 filter->input.flow.gtp_flow.teid =
2789 filter->input.flow_ext.customized_pctype = true;
2790 cus_proto = item_type;
2793 case RTE_FLOW_ITEM_TYPE_SCTP:
2794 sctp_spec = item->spec;
2795 sctp_mask = item->mask;
2797 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2799 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2800 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2802 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2804 if (sctp_spec && sctp_mask) {
2805 /* Check SCTP mask and update input set */
2806 if (sctp_mask->hdr.cksum) {
2807 rte_flow_error_set(error, EINVAL,
2808 RTE_FLOW_ERROR_TYPE_ITEM,
2810 "Invalid UDP mask");
2814 if (sctp_mask->hdr.src_port == UINT16_MAX)
2815 input_set |= I40E_INSET_SRC_PORT;
2816 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2817 input_set |= I40E_INSET_DST_PORT;
2818 if (sctp_mask->hdr.tag == UINT32_MAX)
2819 input_set |= I40E_INSET_SCTP_VT;
2821 /* Get filter info */
2822 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2823 filter->input.flow.sctp4_flow.src_port =
2824 sctp_spec->hdr.src_port;
2825 filter->input.flow.sctp4_flow.dst_port =
2826 sctp_spec->hdr.dst_port;
2827 filter->input.flow.sctp4_flow.verify_tag
2828 = sctp_spec->hdr.tag;
2829 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2830 filter->input.flow.sctp6_flow.src_port =
2831 sctp_spec->hdr.src_port;
2832 filter->input.flow.sctp6_flow.dst_port =
2833 sctp_spec->hdr.dst_port;
2834 filter->input.flow.sctp6_flow.verify_tag
2835 = sctp_spec->hdr.tag;
2839 layer_idx = I40E_FLXPLD_L4_IDX;
2842 case RTE_FLOW_ITEM_TYPE_RAW:
2843 raw_spec = item->spec;
2844 raw_mask = item->mask;
2846 if (!raw_spec || !raw_mask) {
2847 rte_flow_error_set(error, EINVAL,
2848 RTE_FLOW_ERROR_TYPE_ITEM,
2850 "NULL RAW spec/mask");
2854 if (pf->support_multi_driver) {
2855 rte_flow_error_set(error, ENOTSUP,
2856 RTE_FLOW_ERROR_TYPE_ITEM,
2858 "Unsupported flexible payload.");
2862 ret = i40e_flow_check_raw_item(item, raw_spec, error);
2866 off_arr[raw_id] = raw_spec->offset;
2867 len_arr[raw_id] = raw_spec->length;
2870 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2872 raw_spec->length / sizeof(uint16_t);
2873 flex_pit.dst_offset =
2874 next_dst_off / sizeof(uint16_t);
2876 for (i = 0; i <= raw_id; i++) {
2878 flex_pit.src_offset +=
2882 flex_pit.src_offset +=
2883 (off_arr[i] + len_arr[i]) /
2885 flex_size += len_arr[i];
2887 if (((flex_pit.src_offset + flex_pit.size) >=
2888 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2889 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2890 rte_flow_error_set(error, EINVAL,
2891 RTE_FLOW_ERROR_TYPE_ITEM,
2893 "Exceeds maxmial payload limit.");
2897 /* Store flex pit to SW */
2898 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2901 rte_flow_error_set(error, EINVAL,
2902 RTE_FLOW_ERROR_TYPE_ITEM,
2904 "Conflict with the first flexible rule.");
2907 cfg_flex_pit = false;
2909 for (i = 0; i < raw_spec->length; i++) {
2910 j = i + next_dst_off;
2911 filter->input.flow_ext.flexbytes[j] =
2912 raw_spec->pattern[i];
2913 flex_mask[j] = raw_mask->pattern[i];
2916 next_dst_off += raw_spec->length;
2919 case RTE_FLOW_ITEM_TYPE_VF:
2920 vf_spec = item->spec;
2921 filter->input.flow_ext.is_vf = 1;
2922 filter->input.flow_ext.dst_id = vf_spec->id;
2923 if (filter->input.flow_ext.is_vf &&
2924 filter->input.flow_ext.dst_id >= pf->vf_num) {
2925 rte_flow_error_set(error, EINVAL,
2926 RTE_FLOW_ERROR_TYPE_ITEM,
2928 "Invalid VF ID for FDIR.");
2937 /* Get customized pctype value */
2938 if (filter->input.flow_ext.customized_pctype) {
2939 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2940 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2941 rte_flow_error_set(error, EINVAL,
2942 RTE_FLOW_ERROR_TYPE_ITEM,
2944 "Unsupported pctype");
2949 /* If customized pctype is not used, set fdir configuration.*/
2950 if (!filter->input.flow_ext.customized_pctype) {
2951 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2953 rte_flow_error_set(error, EINVAL,
2954 RTE_FLOW_ERROR_TYPE_ITEM, item,
2955 "Conflict with the first rule's input set.");
2957 } else if (ret == -EINVAL) {
2958 rte_flow_error_set(error, EINVAL,
2959 RTE_FLOW_ERROR_TYPE_ITEM, item,
2960 "Invalid pattern mask.");
2964 /* Store flex mask to SW */
2965 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2967 rte_flow_error_set(error, EINVAL,
2968 RTE_FLOW_ERROR_TYPE_ITEM,
2970 "Exceed maximal number of bitmasks");
2972 } else if (ret == -2) {
2973 rte_flow_error_set(error, EINVAL,
2974 RTE_FLOW_ERROR_TYPE_ITEM,
2976 "Conflict with the first flexible rule");
2979 cfg_flex_msk = false;
2982 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2985 i40e_flow_set_fdir_flex_msk(pf, pctype);
2988 filter->input.pctype = pctype;
2993 /* Parse to get the action info of a FDIR filter.
2994 * FDIR action supports QUEUE or (QUEUE + MARK).
2997 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2998 const struct rte_flow_action *actions,
2999 struct rte_flow_error *error,
3000 struct i40e_fdir_filter_conf *filter)
3002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3003 const struct rte_flow_action *act;
3004 const struct rte_flow_action_queue *act_q;
3005 const struct rte_flow_action_mark *mark_spec;
3008 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3009 NEXT_ITEM_OF_ACTION(act, actions, index);
3010 switch (act->type) {
3011 case RTE_FLOW_ACTION_TYPE_QUEUE:
3013 filter->action.rx_queue = act_q->index;
3014 if ((!filter->input.flow_ext.is_vf &&
3015 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3016 (filter->input.flow_ext.is_vf &&
3017 filter->action.rx_queue >= pf->vf_nb_qps)) {
3018 rte_flow_error_set(error, EINVAL,
3019 RTE_FLOW_ERROR_TYPE_ACTION, act,
3020 "Invalid queue ID for FDIR.");
3023 filter->action.behavior = I40E_FDIR_ACCEPT;
3025 case RTE_FLOW_ACTION_TYPE_DROP:
3026 filter->action.behavior = I40E_FDIR_REJECT;
3028 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3029 filter->action.behavior = I40E_FDIR_PASSTHRU;
3032 rte_flow_error_set(error, EINVAL,
3033 RTE_FLOW_ERROR_TYPE_ACTION, act,
3038 /* Check if the next non-void item is MARK or FLAG or END. */
3040 NEXT_ITEM_OF_ACTION(act, actions, index);
3041 switch (act->type) {
3042 case RTE_FLOW_ACTION_TYPE_MARK:
3043 mark_spec = act->conf;
3044 filter->action.report_status = I40E_FDIR_REPORT_ID;
3045 filter->soft_id = mark_spec->id;
3047 case RTE_FLOW_ACTION_TYPE_FLAG:
3048 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3050 case RTE_FLOW_ACTION_TYPE_END:
3053 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3054 act, "Invalid action.");
3058 /* Check if the next non-void item is END */
3060 NEXT_ITEM_OF_ACTION(act, actions, index);
3061 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3062 rte_flow_error_set(error, EINVAL,
3063 RTE_FLOW_ERROR_TYPE_ACTION,
3064 act, "Invalid action.");
3072 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3073 const struct rte_flow_attr *attr,
3074 const struct rte_flow_item pattern[],
3075 const struct rte_flow_action actions[],
3076 struct rte_flow_error *error,
3077 union i40e_filter_t *filter)
3079 struct i40e_fdir_filter_conf *fdir_filter =
3080 &filter->fdir_filter;
3083 ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3087 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3091 ret = i40e_flow_parse_attr(attr, error);
3095 cons_filter_type = RTE_ETH_FILTER_FDIR;
3097 if (dev->data->dev_conf.fdir_conf.mode !=
3098 RTE_FDIR_MODE_PERFECT) {
3099 rte_flow_error_set(error, ENOTSUP,
3100 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3102 "Check the mode in fdir_conf.");
3109 /* Parse to get the action info of a tunnel filter
3110 * Tunnel action only supports PF, VF and QUEUE.
3113 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3114 const struct rte_flow_action *actions,
3115 struct rte_flow_error *error,
3116 struct i40e_tunnel_filter_conf *filter)
3118 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119 const struct rte_flow_action *act;
3120 const struct rte_flow_action_queue *act_q;
3121 const struct rte_flow_action_vf *act_vf;
3124 /* Check if the first non-void action is PF or VF. */
3125 NEXT_ITEM_OF_ACTION(act, actions, index);
3126 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3127 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3128 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3129 act, "Not supported action.");
3133 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3135 filter->vf_id = act_vf->id;
3136 filter->is_to_vf = 1;
3137 if (filter->vf_id >= pf->vf_num) {
3138 rte_flow_error_set(error, EINVAL,
3139 RTE_FLOW_ERROR_TYPE_ACTION,
3140 act, "Invalid VF ID for tunnel filter");
3145 /* Check if the next non-void item is QUEUE */
3147 NEXT_ITEM_OF_ACTION(act, actions, index);
3148 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3150 filter->queue_id = act_q->index;
3151 if ((!filter->is_to_vf) &&
3152 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3153 rte_flow_error_set(error, EINVAL,
3154 RTE_FLOW_ERROR_TYPE_ACTION,
3155 act, "Invalid queue ID for tunnel filter");
3157 } else if (filter->is_to_vf &&
3158 (filter->queue_id >= pf->vf_nb_qps)) {
3159 rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION,
3161 act, "Invalid queue ID for tunnel filter");
3166 /* Check if the next non-void item is END */
3168 NEXT_ITEM_OF_ACTION(act, actions, index);
3169 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3170 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3171 act, "Not supported action.");
3178 static uint16_t i40e_supported_tunnel_filter_types[] = {
3179 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3180 ETH_TUNNEL_FILTER_IVLAN,
3181 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3182 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3183 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3184 ETH_TUNNEL_FILTER_IMAC,
3185 ETH_TUNNEL_FILTER_IMAC,
3189 i40e_check_tunnel_filter_type(uint8_t filter_type)
3193 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3194 if (filter_type == i40e_supported_tunnel_filter_types[i])
3201 /* 1. Last in item should be NULL as range is not supported.
3202 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3203 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3204 * 3. Mask of fields which need to be matched should be
3206 * 4. Mask of fields which needn't to be matched should be
3210 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3211 const struct rte_flow_item *pattern,
3212 struct rte_flow_error *error,
3213 struct i40e_tunnel_filter_conf *filter)
3215 const struct rte_flow_item *item = pattern;
3216 const struct rte_flow_item_eth *eth_spec;
3217 const struct rte_flow_item_eth *eth_mask;
3218 const struct rte_flow_item_vxlan *vxlan_spec;
3219 const struct rte_flow_item_vxlan *vxlan_mask;
3220 const struct rte_flow_item_vlan *vlan_spec;
3221 const struct rte_flow_item_vlan *vlan_mask;
3222 uint8_t filter_type = 0;
3223 bool is_vni_masked = 0;
3224 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3225 enum rte_flow_item_type item_type;
3226 bool vxlan_flag = 0;
3227 uint32_t tenant_id_be = 0;
3230 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3232 rte_flow_error_set(error, EINVAL,
3233 RTE_FLOW_ERROR_TYPE_ITEM,
3235 "Not support range");
3238 item_type = item->type;
3239 switch (item_type) {
3240 case RTE_FLOW_ITEM_TYPE_ETH:
3241 eth_spec = item->spec;
3242 eth_mask = item->mask;
3244 /* Check if ETH item is used for place holder.
3245 * If yes, both spec and mask should be NULL.
3246 * If no, both spec and mask shouldn't be NULL.
3248 if ((!eth_spec && eth_mask) ||
3249 (eth_spec && !eth_mask)) {
3250 rte_flow_error_set(error, EINVAL,
3251 RTE_FLOW_ERROR_TYPE_ITEM,
3253 "Invalid ether spec/mask");
3257 if (eth_spec && eth_mask) {
3258 /* DST address of inner MAC shouldn't be masked.
3259 * SRC address of Inner MAC should be masked.
3261 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3262 !is_zero_ether_addr(ð_mask->src) ||
3264 rte_flow_error_set(error, EINVAL,
3265 RTE_FLOW_ERROR_TYPE_ITEM,
3267 "Invalid ether spec/mask");
3272 rte_memcpy(&filter->outer_mac,
3275 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3277 rte_memcpy(&filter->inner_mac,
3280 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3284 case RTE_FLOW_ITEM_TYPE_VLAN:
3285 vlan_spec = item->spec;
3286 vlan_mask = item->mask;
3287 if (!(vlan_spec && vlan_mask)) {
3288 rte_flow_error_set(error, EINVAL,
3289 RTE_FLOW_ERROR_TYPE_ITEM,
3291 "Invalid vlan item");
3295 if (vlan_spec && vlan_mask) {
3296 if (vlan_mask->tci ==
3297 rte_cpu_to_be_16(I40E_TCI_MASK))
3298 filter->inner_vlan =
3299 rte_be_to_cpu_16(vlan_spec->tci) &
3301 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3304 case RTE_FLOW_ITEM_TYPE_IPV4:
3305 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3306 /* IPv4 is used to describe protocol,
3307 * spec and mask should be NULL.
3309 if (item->spec || item->mask) {
3310 rte_flow_error_set(error, EINVAL,
3311 RTE_FLOW_ERROR_TYPE_ITEM,
3313 "Invalid IPv4 item");
3317 case RTE_FLOW_ITEM_TYPE_IPV6:
3318 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3319 /* IPv6 is used to describe protocol,
3320 * spec and mask should be NULL.
3322 if (item->spec || item->mask) {
3323 rte_flow_error_set(error, EINVAL,
3324 RTE_FLOW_ERROR_TYPE_ITEM,
3326 "Invalid IPv6 item");
3330 case RTE_FLOW_ITEM_TYPE_UDP:
3331 /* UDP is used to describe protocol,
3332 * spec and mask should be NULL.
3334 if (item->spec || item->mask) {
3335 rte_flow_error_set(error, EINVAL,
3336 RTE_FLOW_ERROR_TYPE_ITEM,
3338 "Invalid UDP item");
3342 case RTE_FLOW_ITEM_TYPE_VXLAN:
3343 vxlan_spec = item->spec;
3344 vxlan_mask = item->mask;
3345 /* Check if VXLAN item is used to describe protocol.
3346 * If yes, both spec and mask should be NULL.
3347 * If no, both spec and mask shouldn't be NULL.
3349 if ((!vxlan_spec && vxlan_mask) ||
3350 (vxlan_spec && !vxlan_mask)) {
3351 rte_flow_error_set(error, EINVAL,
3352 RTE_FLOW_ERROR_TYPE_ITEM,
3354 "Invalid VXLAN item");
3358 /* Check if VNI is masked. */
3359 if (vxlan_spec && vxlan_mask) {
3361 !!memcmp(vxlan_mask->vni, vni_mask,
3363 if (is_vni_masked) {
3364 rte_flow_error_set(error, EINVAL,
3365 RTE_FLOW_ERROR_TYPE_ITEM,
3367 "Invalid VNI mask");
3371 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3372 vxlan_spec->vni, 3);
3374 rte_be_to_cpu_32(tenant_id_be);
3375 filter_type |= ETH_TUNNEL_FILTER_TENID;
3385 ret = i40e_check_tunnel_filter_type(filter_type);
3387 rte_flow_error_set(error, EINVAL,
3388 RTE_FLOW_ERROR_TYPE_ITEM,
3390 "Invalid filter type");
3393 filter->filter_type = filter_type;
3395 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3401 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3402 const struct rte_flow_attr *attr,
3403 const struct rte_flow_item pattern[],
3404 const struct rte_flow_action actions[],
3405 struct rte_flow_error *error,
3406 union i40e_filter_t *filter)
3408 struct i40e_tunnel_filter_conf *tunnel_filter =
3409 &filter->consistent_tunnel_filter;
3412 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3413 error, tunnel_filter);
3417 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3421 ret = i40e_flow_parse_attr(attr, error);
3425 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3430 /* 1. Last in item should be NULL as range is not supported.
3431 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3432 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3433 * 3. Mask of fields which need to be matched should be
3435 * 4. Mask of fields which needn't to be matched should be
3439 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3440 const struct rte_flow_item *pattern,
3441 struct rte_flow_error *error,
3442 struct i40e_tunnel_filter_conf *filter)
3444 const struct rte_flow_item *item = pattern;
3445 const struct rte_flow_item_eth *eth_spec;
3446 const struct rte_flow_item_eth *eth_mask;
3447 const struct rte_flow_item_nvgre *nvgre_spec;
3448 const struct rte_flow_item_nvgre *nvgre_mask;
3449 const struct rte_flow_item_vlan *vlan_spec;
3450 const struct rte_flow_item_vlan *vlan_mask;
3451 enum rte_flow_item_type item_type;
3452 uint8_t filter_type = 0;
3453 bool is_tni_masked = 0;
3454 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3455 bool nvgre_flag = 0;
3456 uint32_t tenant_id_be = 0;
3459 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3461 rte_flow_error_set(error, EINVAL,
3462 RTE_FLOW_ERROR_TYPE_ITEM,
3464 "Not support range");
3467 item_type = item->type;
3468 switch (item_type) {
3469 case RTE_FLOW_ITEM_TYPE_ETH:
3470 eth_spec = item->spec;
3471 eth_mask = item->mask;
3473 /* Check if ETH item is used for place holder.
3474 * If yes, both spec and mask should be NULL.
3475 * If no, both spec and mask shouldn't be NULL.
3477 if ((!eth_spec && eth_mask) ||
3478 (eth_spec && !eth_mask)) {
3479 rte_flow_error_set(error, EINVAL,
3480 RTE_FLOW_ERROR_TYPE_ITEM,
3482 "Invalid ether spec/mask");
3486 if (eth_spec && eth_mask) {
3487 /* DST address of inner MAC shouldn't be masked.
3488 * SRC address of Inner MAC should be masked.
3490 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3491 !is_zero_ether_addr(ð_mask->src) ||
3493 rte_flow_error_set(error, EINVAL,
3494 RTE_FLOW_ERROR_TYPE_ITEM,
3496 "Invalid ether spec/mask");
3501 rte_memcpy(&filter->outer_mac,
3504 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3506 rte_memcpy(&filter->inner_mac,
3509 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3514 case RTE_FLOW_ITEM_TYPE_VLAN:
3515 vlan_spec = item->spec;
3516 vlan_mask = item->mask;
3517 if (!(vlan_spec && vlan_mask)) {
3518 rte_flow_error_set(error, EINVAL,
3519 RTE_FLOW_ERROR_TYPE_ITEM,
3521 "Invalid vlan item");
3525 if (vlan_spec && vlan_mask) {
3526 if (vlan_mask->tci ==
3527 rte_cpu_to_be_16(I40E_TCI_MASK))
3528 filter->inner_vlan =
3529 rte_be_to_cpu_16(vlan_spec->tci) &
3531 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3534 case RTE_FLOW_ITEM_TYPE_IPV4:
3535 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3536 /* IPv4 is used to describe protocol,
3537 * spec and mask should be NULL.
3539 if (item->spec || item->mask) {
3540 rte_flow_error_set(error, EINVAL,
3541 RTE_FLOW_ERROR_TYPE_ITEM,
3543 "Invalid IPv4 item");
3547 case RTE_FLOW_ITEM_TYPE_IPV6:
3548 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3549 /* IPv6 is used to describe protocol,
3550 * spec and mask should be NULL.
3552 if (item->spec || item->mask) {
3553 rte_flow_error_set(error, EINVAL,
3554 RTE_FLOW_ERROR_TYPE_ITEM,
3556 "Invalid IPv6 item");
3560 case RTE_FLOW_ITEM_TYPE_NVGRE:
3561 nvgre_spec = item->spec;
3562 nvgre_mask = item->mask;
3563 /* Check if NVGRE item is used to describe protocol.
3564 * If yes, both spec and mask should be NULL.
3565 * If no, both spec and mask shouldn't be NULL.
3567 if ((!nvgre_spec && nvgre_mask) ||
3568 (nvgre_spec && !nvgre_mask)) {
3569 rte_flow_error_set(error, EINVAL,
3570 RTE_FLOW_ERROR_TYPE_ITEM,
3572 "Invalid NVGRE item");
3576 if (nvgre_spec && nvgre_mask) {
3578 !!memcmp(nvgre_mask->tni, tni_mask,
3580 if (is_tni_masked) {
3581 rte_flow_error_set(error, EINVAL,
3582 RTE_FLOW_ERROR_TYPE_ITEM,
3584 "Invalid TNI mask");
3587 if (nvgre_mask->protocol &&
3588 nvgre_mask->protocol != 0xFFFF) {
3589 rte_flow_error_set(error, EINVAL,
3590 RTE_FLOW_ERROR_TYPE_ITEM,
3592 "Invalid NVGRE item");
3595 if (nvgre_mask->c_k_s_rsvd0_ver &&
3596 nvgre_mask->c_k_s_rsvd0_ver !=
3597 rte_cpu_to_be_16(0xFFFF)) {
3598 rte_flow_error_set(error, EINVAL,
3599 RTE_FLOW_ERROR_TYPE_ITEM,
3601 "Invalid NVGRE item");
3604 if (nvgre_spec->c_k_s_rsvd0_ver !=
3605 rte_cpu_to_be_16(0x2000) &&
3606 nvgre_mask->c_k_s_rsvd0_ver) {
3607 rte_flow_error_set(error, EINVAL,
3608 RTE_FLOW_ERROR_TYPE_ITEM,
3610 "Invalid NVGRE item");
3613 if (nvgre_mask->protocol &&
3614 nvgre_spec->protocol !=
3615 rte_cpu_to_be_16(0x6558)) {
3616 rte_flow_error_set(error, EINVAL,
3617 RTE_FLOW_ERROR_TYPE_ITEM,
3619 "Invalid NVGRE item");
3622 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3623 nvgre_spec->tni, 3);
3625 rte_be_to_cpu_32(tenant_id_be);
3626 filter_type |= ETH_TUNNEL_FILTER_TENID;
3636 ret = i40e_check_tunnel_filter_type(filter_type);
3638 rte_flow_error_set(error, EINVAL,
3639 RTE_FLOW_ERROR_TYPE_ITEM,
3641 "Invalid filter type");
3644 filter->filter_type = filter_type;
3646 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3652 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3653 const struct rte_flow_attr *attr,
3654 const struct rte_flow_item pattern[],
3655 const struct rte_flow_action actions[],
3656 struct rte_flow_error *error,
3657 union i40e_filter_t *filter)
3659 struct i40e_tunnel_filter_conf *tunnel_filter =
3660 &filter->consistent_tunnel_filter;
3663 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3664 error, tunnel_filter);
3668 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3672 ret = i40e_flow_parse_attr(attr, error);
3676 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3681 /* 1. Last in item should be NULL as range is not supported.
3682 * 2. Supported filter types: MPLS label.
3683 * 3. Mask of fields which need to be matched should be
3685 * 4. Mask of fields which needn't to be matched should be
3689 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3690 const struct rte_flow_item *pattern,
3691 struct rte_flow_error *error,
3692 struct i40e_tunnel_filter_conf *filter)
3694 const struct rte_flow_item *item = pattern;
3695 const struct rte_flow_item_mpls *mpls_spec;
3696 const struct rte_flow_item_mpls *mpls_mask;
3697 enum rte_flow_item_type item_type;
3698 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3699 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3700 uint32_t label_be = 0;
3702 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3704 rte_flow_error_set(error, EINVAL,
3705 RTE_FLOW_ERROR_TYPE_ITEM,
3707 "Not support range");
3710 item_type = item->type;
3711 switch (item_type) {
3712 case RTE_FLOW_ITEM_TYPE_ETH:
3713 if (item->spec || item->mask) {
3714 rte_flow_error_set(error, EINVAL,
3715 RTE_FLOW_ERROR_TYPE_ITEM,
3717 "Invalid ETH item");
3721 case RTE_FLOW_ITEM_TYPE_IPV4:
3722 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3723 /* IPv4 is used to describe protocol,
3724 * spec and mask should be NULL.
3726 if (item->spec || item->mask) {
3727 rte_flow_error_set(error, EINVAL,
3728 RTE_FLOW_ERROR_TYPE_ITEM,
3730 "Invalid IPv4 item");
3734 case RTE_FLOW_ITEM_TYPE_IPV6:
3735 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3736 /* IPv6 is used to describe protocol,
3737 * spec and mask should be NULL.
3739 if (item->spec || item->mask) {
3740 rte_flow_error_set(error, EINVAL,
3741 RTE_FLOW_ERROR_TYPE_ITEM,
3743 "Invalid IPv6 item");
3747 case RTE_FLOW_ITEM_TYPE_UDP:
3748 /* UDP is used to describe protocol,
3749 * spec and mask should be NULL.
3751 if (item->spec || item->mask) {
3752 rte_flow_error_set(error, EINVAL,
3753 RTE_FLOW_ERROR_TYPE_ITEM,
3755 "Invalid UDP item");
3760 case RTE_FLOW_ITEM_TYPE_GRE:
3761 /* GRE is used to describe protocol,
3762 * spec and mask should be NULL.
3764 if (item->spec || item->mask) {
3765 rte_flow_error_set(error, EINVAL,
3766 RTE_FLOW_ERROR_TYPE_ITEM,
3768 "Invalid GRE item");
3772 case RTE_FLOW_ITEM_TYPE_MPLS:
3773 mpls_spec = item->spec;
3774 mpls_mask = item->mask;
3776 if (!mpls_spec || !mpls_mask) {
3777 rte_flow_error_set(error, EINVAL,
3778 RTE_FLOW_ERROR_TYPE_ITEM,
3780 "Invalid MPLS item");
3784 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3785 rte_flow_error_set(error, EINVAL,
3786 RTE_FLOW_ERROR_TYPE_ITEM,
3788 "Invalid MPLS label mask");
3791 rte_memcpy(((uint8_t *)&label_be + 1),
3792 mpls_spec->label_tc_s, 3);
3793 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3801 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3803 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3809 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3810 const struct rte_flow_attr *attr,
3811 const struct rte_flow_item pattern[],
3812 const struct rte_flow_action actions[],
3813 struct rte_flow_error *error,
3814 union i40e_filter_t *filter)
3816 struct i40e_tunnel_filter_conf *tunnel_filter =
3817 &filter->consistent_tunnel_filter;
3820 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3821 error, tunnel_filter);
3825 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3829 ret = i40e_flow_parse_attr(attr, error);
3833 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3838 /* 1. Last in item should be NULL as range is not supported.
3839 * 2. Supported filter types: GTP TEID.
3840 * 3. Mask of fields which need to be matched should be
3842 * 4. Mask of fields which needn't to be matched should be
3844 * 5. GTP profile supports GTPv1 only.
3845 * 6. GTP-C response message ('source_port' = 2123) is not supported.
3848 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3849 const struct rte_flow_item *pattern,
3850 struct rte_flow_error *error,
3851 struct i40e_tunnel_filter_conf *filter)
3853 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3854 const struct rte_flow_item *item = pattern;
3855 const struct rte_flow_item_gtp *gtp_spec;
3856 const struct rte_flow_item_gtp *gtp_mask;
3857 enum rte_flow_item_type item_type;
3859 if (!pf->gtp_support) {
3860 rte_flow_error_set(error, EINVAL,
3861 RTE_FLOW_ERROR_TYPE_ITEM,
3863 "GTP is not supported by default.");
3867 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3869 rte_flow_error_set(error, EINVAL,
3870 RTE_FLOW_ERROR_TYPE_ITEM,
3872 "Not support range");
3875 item_type = item->type;
3876 switch (item_type) {
3877 case RTE_FLOW_ITEM_TYPE_ETH:
3878 if (item->spec || item->mask) {
3879 rte_flow_error_set(error, EINVAL,
3880 RTE_FLOW_ERROR_TYPE_ITEM,
3882 "Invalid ETH item");
3886 case RTE_FLOW_ITEM_TYPE_IPV4:
3887 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3888 /* IPv4 is used to describe protocol,
3889 * spec and mask should be NULL.
3891 if (item->spec || item->mask) {
3892 rte_flow_error_set(error, EINVAL,
3893 RTE_FLOW_ERROR_TYPE_ITEM,
3895 "Invalid IPv4 item");
3899 case RTE_FLOW_ITEM_TYPE_UDP:
3900 if (item->spec || item->mask) {
3901 rte_flow_error_set(error, EINVAL,
3902 RTE_FLOW_ERROR_TYPE_ITEM,
3904 "Invalid UDP item");
3908 case RTE_FLOW_ITEM_TYPE_GTPC:
3909 case RTE_FLOW_ITEM_TYPE_GTPU:
3910 gtp_spec = item->spec;
3911 gtp_mask = item->mask;
3913 if (!gtp_spec || !gtp_mask) {
3914 rte_flow_error_set(error, EINVAL,
3915 RTE_FLOW_ERROR_TYPE_ITEM,
3917 "Invalid GTP item");
3921 if (gtp_mask->v_pt_rsv_flags ||
3922 gtp_mask->msg_type ||
3923 gtp_mask->msg_len ||
3924 gtp_mask->teid != UINT32_MAX) {
3925 rte_flow_error_set(error, EINVAL,
3926 RTE_FLOW_ERROR_TYPE_ITEM,
3928 "Invalid GTP mask");
3932 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3933 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3934 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3935 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3937 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3949 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3950 const struct rte_flow_attr *attr,
3951 const struct rte_flow_item pattern[],
3952 const struct rte_flow_action actions[],
3953 struct rte_flow_error *error,
3954 union i40e_filter_t *filter)
3956 struct i40e_tunnel_filter_conf *tunnel_filter =
3957 &filter->consistent_tunnel_filter;
3960 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3961 error, tunnel_filter);
3965 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3969 ret = i40e_flow_parse_attr(attr, error);
3973 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3978 /* 1. Last in item should be NULL as range is not supported.
3979 * 2. Supported filter types: QINQ.
3980 * 3. Mask of fields which need to be matched should be
3982 * 4. Mask of fields which needn't to be matched should be
3986 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3987 const struct rte_flow_item *pattern,
3988 struct rte_flow_error *error,
3989 struct i40e_tunnel_filter_conf *filter)
3991 const struct rte_flow_item *item = pattern;
3992 const struct rte_flow_item_vlan *vlan_spec = NULL;
3993 const struct rte_flow_item_vlan *vlan_mask = NULL;
3994 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3995 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3996 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3997 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3999 enum rte_flow_item_type item_type;
4002 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4004 rte_flow_error_set(error, EINVAL,
4005 RTE_FLOW_ERROR_TYPE_ITEM,
4007 "Not support range");
4010 item_type = item->type;
4011 switch (item_type) {
4012 case RTE_FLOW_ITEM_TYPE_ETH:
4013 if (item->spec || item->mask) {
4014 rte_flow_error_set(error, EINVAL,
4015 RTE_FLOW_ERROR_TYPE_ITEM,
4017 "Invalid ETH item");
4021 case RTE_FLOW_ITEM_TYPE_VLAN:
4022 vlan_spec = item->spec;
4023 vlan_mask = item->mask;
4025 if (!(vlan_spec && vlan_mask)) {
4026 rte_flow_error_set(error, EINVAL,
4027 RTE_FLOW_ERROR_TYPE_ITEM,
4029 "Invalid vlan item");
4034 o_vlan_spec = vlan_spec;
4035 o_vlan_mask = vlan_mask;
4038 i_vlan_spec = vlan_spec;
4039 i_vlan_mask = vlan_mask;
4049 /* Get filter specification */
4050 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4051 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4052 (i_vlan_mask != NULL) &&
4053 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4054 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4056 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4059 rte_flow_error_set(error, EINVAL,
4060 RTE_FLOW_ERROR_TYPE_ITEM,
4062 "Invalid filter type");
4066 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4071 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4072 const struct rte_flow_attr *attr,
4073 const struct rte_flow_item pattern[],
4074 const struct rte_flow_action actions[],
4075 struct rte_flow_error *error,
4076 union i40e_filter_t *filter)
4078 struct i40e_tunnel_filter_conf *tunnel_filter =
4079 &filter->consistent_tunnel_filter;
4082 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4083 error, tunnel_filter);
4087 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4091 ret = i40e_flow_parse_attr(attr, error);
4095 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4101 * This function is used to do configuration i40e existing RSS with rte_flow.
4102 * It also enable queue region configuration using flow API for i40e.
4103 * pattern can be used indicate what parameters will be include in flow,
4104 * like user_priority or flowtype for queue region or HASH function for RSS.
4105 * Action is used to transmit parameter like queue index and HASH
4106 * function for RSS, or flowtype for queue region configuration.
4109 * Case 1: only ETH, indicate flowtype for queue region will be parsed.
4110 * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4111 * Case 3: none, indicate RSS related will be parsed in action.
4112 * Any pattern other the ETH or VLAN will be treated as invalid except END.
4113 * So, pattern choice is depened on the purpose of configuration of
4116 * action RSS will be uaed to transmit valid parameter with
4117 * struct rte_flow_action_rss for all the 3 case.
4120 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4121 const struct rte_flow_item *pattern,
4122 struct rte_flow_error *error,
4123 uint8_t *action_flag,
4124 struct i40e_queue_regions *info)
4126 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4127 const struct rte_flow_item *item = pattern;
4128 enum rte_flow_item_type item_type;
4130 if (item->type == RTE_FLOW_ITEM_TYPE_END)
4133 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4135 rte_flow_error_set(error, EINVAL,
4136 RTE_FLOW_ERROR_TYPE_ITEM,
4138 "Not support range");
4141 item_type = item->type;
4142 switch (item_type) {
4143 case RTE_FLOW_ITEM_TYPE_ETH:
4146 case RTE_FLOW_ITEM_TYPE_VLAN:
4147 vlan_spec = item->spec;
4148 vlan_mask = item->mask;
4149 if (vlan_spec && vlan_mask) {
4150 if (vlan_mask->tci ==
4151 rte_cpu_to_be_16(I40E_TCI_MASK)) {
4152 info->region[0].user_priority[0] =
4153 (vlan_spec->tci >> 13) & 0x7;
4154 info->region[0].user_priority_num = 1;
4155 info->queue_region_number = 1;
4161 rte_flow_error_set(error, EINVAL,
4162 RTE_FLOW_ERROR_TYPE_ITEM,
4164 "Not support range");
4173 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4174 const struct rte_flow_action *actions,
4175 struct rte_flow_error *error,
4176 uint8_t action_flag,
4177 struct i40e_queue_regions *conf_info,
4178 union i40e_filter_t *filter)
4180 const struct rte_flow_action *act;
4181 const struct rte_flow_action_rss *rss;
4182 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4183 struct i40e_queue_regions *info = &pf->queue_region;
4184 struct i40e_rte_flow_rss_conf *rss_config =
4186 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4187 uint16_t i, j, n, tmp;
4189 uint64_t hf_bit = 1;
4191 NEXT_ITEM_OF_ACTION(act, actions, index);
4195 * rss only supports forwarding,
4196 * check if the first not void action is RSS.
4198 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4199 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4200 rte_flow_error_set(error, EINVAL,
4201 RTE_FLOW_ERROR_TYPE_ACTION,
4202 act, "Not supported action.");
4207 for (n = 0; n < 64; n++) {
4208 if (rss->rss_conf->rss_hf & (hf_bit << n)) {
4209 conf_info->region[0].hw_flowtype[0] = n;
4210 conf_info->region[0].flowtype_num = 1;
4211 conf_info->queue_region_number = 1;
4217 for (n = 0; n < conf_info->queue_region_number; n++) {
4218 if (conf_info->region[n].user_priority_num ||
4219 conf_info->region[n].flowtype_num) {
4220 if (!((rte_is_power_of_2(rss->num)) &&
4222 PMD_DRV_LOG(ERR, "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4223 "total number of queues do not exceed the VSI allocation");
4227 if (conf_info->region[n].user_priority[n] >=
4228 I40E_MAX_USER_PRIORITY) {
4229 PMD_DRV_LOG(ERR, "the user priority max index is 7");
4233 if (conf_info->region[n].hw_flowtype[n] >=
4234 I40E_FILTER_PCTYPE_MAX) {
4235 PMD_DRV_LOG(ERR, "the hw_flowtype or PCTYPE max index is 63");
4239 if (rss_info->num < rss->num ||
4240 rss_info->queue[0] < rss->queue[0] ||
4241 (rss->queue[0] + rss->num >
4242 rss_info->num + rss_info->queue[0])) {
4243 rte_flow_error_set(error, EINVAL,
4244 RTE_FLOW_ERROR_TYPE_ACTION,
4250 for (i = 0; i < info->queue_region_number; i++) {
4251 if (info->region[i].queue_num == rss->num &&
4252 info->region[i].queue_start_index ==
4257 if (i == info->queue_region_number) {
4258 if (i > I40E_REGION_MAX_INDEX) {
4259 PMD_DRV_LOG(ERR, "the queue region max index is 7");
4263 info->region[i].queue_num =
4265 info->region[i].queue_start_index =
4267 info->region[i].region_id =
4268 info->queue_region_number;
4270 j = info->region[i].user_priority_num;
4271 tmp = conf_info->region[n].user_priority[0];
4272 if (conf_info->region[n].user_priority_num) {
4273 info->region[i].user_priority[j] = tmp;
4274 info->region[i].user_priority_num++;
4277 j = info->region[i].flowtype_num;
4278 tmp = conf_info->region[n].hw_flowtype[0];
4279 if (conf_info->region[n].flowtype_num) {
4280 info->region[i].hw_flowtype[j] = tmp;
4281 info->region[i].flowtype_num++;
4283 info->queue_region_number++;
4285 j = info->region[i].user_priority_num;
4286 tmp = conf_info->region[n].user_priority[0];
4287 if (conf_info->region[n].user_priority_num) {
4288 info->region[i].user_priority[j] = tmp;
4289 info->region[i].user_priority_num++;
4292 j = info->region[i].flowtype_num;
4293 tmp = conf_info->region[n].hw_flowtype[0];
4294 if (conf_info->region[n].flowtype_num) {
4295 info->region[i].hw_flowtype[j] = tmp;
4296 info->region[i].flowtype_num++;
4301 rss_config->queue_region_conf = TRUE;
4304 if (rss_config->queue_region_conf)
4307 if (!rss || !rss->num) {
4308 rte_flow_error_set(error, EINVAL,
4309 RTE_FLOW_ERROR_TYPE_ACTION,
4315 for (n = 0; n < rss->num; n++) {
4316 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4317 rte_flow_error_set(error, EINVAL,
4318 RTE_FLOW_ERROR_TYPE_ACTION,
4320 "queue id > max number of queues");
4325 rss_config->rss_conf = *rss->rss_conf;
4327 rss_config->rss_conf.rss_hf =
4328 pf->adapter->flow_types_mask;
4330 for (n = 0; n < rss->num; ++n)
4331 rss_config->queue[n] = rss->queue[n];
4332 rss_config->num = rss->num;
4335 /* check if the next not void action is END */
4336 NEXT_ITEM_OF_ACTION(act, actions, index);
4337 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4338 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4339 rte_flow_error_set(error, EINVAL,
4340 RTE_FLOW_ERROR_TYPE_ACTION,
4341 act, "Not supported action.");
4344 rss_config->queue_region_conf = FALSE;
4350 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4351 const struct rte_flow_attr *attr,
4352 const struct rte_flow_item pattern[],
4353 const struct rte_flow_action actions[],
4354 union i40e_filter_t *filter,
4355 struct rte_flow_error *error)
4358 struct i40e_queue_regions info;
4359 uint8_t action_flag = 0;
4361 memset(&info, 0, sizeof(struct i40e_queue_regions));
4363 ret = i40e_flow_parse_rss_pattern(dev, pattern,
4364 error, &action_flag, &info);
4368 ret = i40e_flow_parse_rss_action(dev, actions, error,
4369 action_flag, &info, filter);
4373 ret = i40e_flow_parse_attr(attr, error);
4377 cons_filter_type = RTE_ETH_FILTER_HASH;
4383 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4384 struct i40e_rte_flow_rss_conf *conf)
4386 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4387 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389 if (conf->queue_region_conf) {
4390 i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4391 conf->queue_region_conf = 0;
4393 i40e_config_rss_filter(pf, conf, 1);
4399 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4400 struct i40e_rte_flow_rss_conf *conf)
4402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4407 i40e_config_rss_filter(pf, conf, 0);
4412 i40e_flow_validate(struct rte_eth_dev *dev,
4413 const struct rte_flow_attr *attr,
4414 const struct rte_flow_item pattern[],
4415 const struct rte_flow_action actions[],
4416 struct rte_flow_error *error)
4418 struct rte_flow_item *items; /* internal pattern w/o VOID items */
4419 parse_filter_t parse_filter;
4420 uint32_t item_num = 0; /* non-void item number of pattern*/
4423 int ret = I40E_NOT_SUPPORTED;
4426 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4427 NULL, "NULL pattern.");
4432 rte_flow_error_set(error, EINVAL,
4433 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4434 NULL, "NULL action.");
4439 rte_flow_error_set(error, EINVAL,
4440 RTE_FLOW_ERROR_TYPE_ATTR,
4441 NULL, "NULL attribute.");
4445 memset(&cons_filter, 0, sizeof(cons_filter));
4447 /* Get the non-void item of action */
4448 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4451 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4452 ret = i40e_parse_rss_filter(dev, attr, pattern,
4453 actions, &cons_filter, error);
4458 /* Get the non-void item number of pattern */
4459 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4460 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4466 items = rte_zmalloc("i40e_pattern",
4467 item_num * sizeof(struct rte_flow_item), 0);
4469 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4470 NULL, "No memory for PMD internal items.");
4474 i40e_pattern_skip_void_item(items, pattern);
4478 parse_filter = i40e_find_parse_filter_func(items, &i);
4479 if (!parse_filter && !flag) {
4480 rte_flow_error_set(error, EINVAL,
4481 RTE_FLOW_ERROR_TYPE_ITEM,
4482 pattern, "Unsupported pattern");
4487 ret = parse_filter(dev, attr, items, actions,
4488 error, &cons_filter);
4490 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4497 static struct rte_flow *
4498 i40e_flow_create(struct rte_eth_dev *dev,
4499 const struct rte_flow_attr *attr,
4500 const struct rte_flow_item pattern[],
4501 const struct rte_flow_action actions[],
4502 struct rte_flow_error *error)
4504 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4505 struct rte_flow *flow;
4508 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4510 rte_flow_error_set(error, ENOMEM,
4511 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4512 "Failed to allocate memory");
4516 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4520 switch (cons_filter_type) {
4521 case RTE_ETH_FILTER_ETHERTYPE:
4522 ret = i40e_ethertype_filter_set(pf,
4523 &cons_filter.ethertype_filter, 1);
4526 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4527 i40e_ethertype_filter_list);
4529 case RTE_ETH_FILTER_FDIR:
4530 ret = i40e_flow_add_del_fdir_filter(dev,
4531 &cons_filter.fdir_filter, 1);
4534 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4535 i40e_fdir_filter_list);
4537 case RTE_ETH_FILTER_TUNNEL:
4538 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4539 &cons_filter.consistent_tunnel_filter, 1);
4542 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4543 i40e_tunnel_filter_list);
4545 case RTE_ETH_FILTER_HASH:
4546 ret = i40e_config_rss_filter_set(dev,
4547 &cons_filter.rss_conf);
4548 flow->rule = &pf->rss_info;
4554 flow->filter_type = cons_filter_type;
4555 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4559 rte_flow_error_set(error, -ret,
4560 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4561 "Failed to create flow.");
4567 i40e_flow_destroy(struct rte_eth_dev *dev,
4568 struct rte_flow *flow,
4569 struct rte_flow_error *error)
4571 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4572 enum rte_filter_type filter_type = flow->filter_type;
4575 switch (filter_type) {
4576 case RTE_ETH_FILTER_ETHERTYPE:
4577 ret = i40e_flow_destroy_ethertype_filter(pf,
4578 (struct i40e_ethertype_filter *)flow->rule);
4580 case RTE_ETH_FILTER_TUNNEL:
4581 ret = i40e_flow_destroy_tunnel_filter(pf,
4582 (struct i40e_tunnel_filter *)flow->rule);
4584 case RTE_ETH_FILTER_FDIR:
4585 ret = i40e_flow_add_del_fdir_filter(dev,
4586 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4588 case RTE_ETH_FILTER_HASH:
4589 ret = i40e_config_rss_filter_del(dev,
4590 (struct i40e_rte_flow_rss_conf *)flow->rule);
4593 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4600 TAILQ_REMOVE(&pf->flow_list, flow, node);
4603 rte_flow_error_set(error, -ret,
4604 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4605 "Failed to destroy flow.");
4611 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4612 struct i40e_ethertype_filter *filter)
4614 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4615 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4616 struct i40e_ethertype_filter *node;
4617 struct i40e_control_filter_stats stats;
4621 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4622 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4623 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4624 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4625 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4627 memset(&stats, 0, sizeof(stats));
4628 ret = i40e_aq_add_rem_control_packet_filter(hw,
4629 filter->input.mac_addr.addr_bytes,
4630 filter->input.ether_type,
4631 flags, pf->main_vsi->seid,
4632 filter->queue, 0, &stats, NULL);
4636 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4640 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4646 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4647 struct i40e_tunnel_filter *filter)
4649 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4650 struct i40e_vsi *vsi;
4651 struct i40e_pf_vf *vf;
4652 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4653 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4654 struct i40e_tunnel_filter *node;
4655 bool big_buffer = 0;
4658 memset(&cld_filter, 0, sizeof(cld_filter));
4659 ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4660 (struct ether_addr *)&cld_filter.element.outer_mac);
4661 ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4662 (struct ether_addr *)&cld_filter.element.inner_mac);
4663 cld_filter.element.inner_vlan = filter->input.inner_vlan;
4664 cld_filter.element.flags = filter->input.flags;
4665 cld_filter.element.tenant_id = filter->input.tenant_id;
4666 cld_filter.element.queue_number = filter->queue;
4667 rte_memcpy(cld_filter.general_fields,
4668 filter->input.general_fields,
4669 sizeof(cld_filter.general_fields));
4671 if (!filter->is_to_vf)
4674 vf = &pf->vfs[filter->vf_id];
4678 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4679 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4680 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4681 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4682 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4683 I40E_AQC_ADD_CLOUD_FILTER_0X10))
4687 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4690 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4691 &cld_filter.element, 1);
4695 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4699 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4705 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4710 ret = i40e_flow_flush_fdir_filter(pf);
4712 rte_flow_error_set(error, -ret,
4713 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4714 "Failed to flush FDIR flows.");
4718 ret = i40e_flow_flush_ethertype_filter(pf);
4720 rte_flow_error_set(error, -ret,
4721 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4722 "Failed to ethertype flush flows.");
4726 ret = i40e_flow_flush_tunnel_filter(pf);
4728 rte_flow_error_set(error, -ret,
4729 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4730 "Failed to flush tunnel flows.");
4734 ret = i40e_flow_flush_rss_filter(dev);
4736 rte_flow_error_set(error, -ret,
4737 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4738 "Failed to flush rss flows.");
4746 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4748 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4749 struct i40e_fdir_info *fdir_info = &pf->fdir;
4750 struct i40e_fdir_filter *fdir_filter;
4751 enum i40e_filter_pctype pctype;
4752 struct rte_flow *flow;
4756 ret = i40e_fdir_flush(dev);
4758 /* Delete FDIR filters in FDIR list. */
4759 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4760 ret = i40e_sw_fdir_filter_del(pf,
4761 &fdir_filter->fdir.input);
4766 /* Delete FDIR flows in flow list. */
4767 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4768 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4769 TAILQ_REMOVE(&pf->flow_list, flow, node);
4774 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4775 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4776 pf->fdir.inset_flag[pctype] = 0;
4782 /* Flush all ethertype filters */
4784 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4786 struct i40e_ethertype_filter_list
4787 *ethertype_list = &pf->ethertype.ethertype_list;
4788 struct i40e_ethertype_filter *filter;
4789 struct rte_flow *flow;
4793 while ((filter = TAILQ_FIRST(ethertype_list))) {
4794 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4799 /* Delete ethertype flows in flow list. */
4800 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4801 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4802 TAILQ_REMOVE(&pf->flow_list, flow, node);
4810 /* Flush all tunnel filters */
4812 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4814 struct i40e_tunnel_filter_list
4815 *tunnel_list = &pf->tunnel.tunnel_list;
4816 struct i40e_tunnel_filter *filter;
4817 struct rte_flow *flow;
4821 while ((filter = TAILQ_FIRST(tunnel_list))) {
4822 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4827 /* Delete tunnel flows in flow list. */
4828 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4829 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4830 TAILQ_REMOVE(&pf->flow_list, flow, node);
4838 /* remove the rss filter */
4840 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4842 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4843 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 int32_t ret = -EINVAL;
4847 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4850 ret = i40e_config_rss_filter(pf, rss_info, FALSE);