1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
13 #include <rte_debug.h>
14 #include <rte_ether.h>
15 #include <rte_ethdev_driver.h>
17 #include <rte_malloc.h>
18 #include <rte_tailq.h>
19 #include <rte_flow_driver.h>
21 #include "i40e_logs.h"
22 #include "base/i40e_type.h"
23 #include "base/i40e_prototype.h"
24 #include "i40e_ethdev.h"
26 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
27 #define I40E_IPV6_FRAG_HEADER 44
28 #define I40E_TENANT_ARRAY_NUM 3
29 #define I40E_TCI_MASK 0xFFFF
31 static int i40e_flow_validate(struct rte_eth_dev *dev,
32 const struct rte_flow_attr *attr,
33 const struct rte_flow_item pattern[],
34 const struct rte_flow_action actions[],
35 struct rte_flow_error *error);
36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
37 const struct rte_flow_attr *attr,
38 const struct rte_flow_item pattern[],
39 const struct rte_flow_action actions[],
40 struct rte_flow_error *error);
41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
42 struct rte_flow *flow,
43 struct rte_flow_error *error);
44 static int i40e_flow_flush(struct rte_eth_dev *dev,
45 struct rte_flow_error *error);
47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
48 const struct rte_flow_item *pattern,
49 struct rte_flow_error *error,
50 struct rte_eth_ethertype_filter *filter);
51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
52 const struct rte_flow_action *actions,
53 struct rte_flow_error *error,
54 struct rte_eth_ethertype_filter *filter);
55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
56 const struct rte_flow_attr *attr,
57 const struct rte_flow_item *pattern,
58 struct rte_flow_error *error,
59 struct i40e_fdir_filter_conf *filter);
60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
61 const struct rte_flow_action *actions,
62 struct rte_flow_error *error,
63 struct i40e_fdir_filter_conf *filter);
64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
65 const struct rte_flow_action *actions,
66 struct rte_flow_error *error,
67 struct i40e_tunnel_filter_conf *filter);
68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
69 struct rte_flow_error *error);
70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
71 const struct rte_flow_attr *attr,
72 const struct rte_flow_item pattern[],
73 const struct rte_flow_action actions[],
74 struct rte_flow_error *error,
75 union i40e_filter_t *filter);
76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
77 const struct rte_flow_attr *attr,
78 const struct rte_flow_item pattern[],
79 const struct rte_flow_action actions[],
80 struct rte_flow_error *error,
81 union i40e_filter_t *filter);
82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
83 const struct rte_flow_attr *attr,
84 const struct rte_flow_item pattern[],
85 const struct rte_flow_action actions[],
86 struct rte_flow_error *error,
87 union i40e_filter_t *filter);
88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
89 const struct rte_flow_attr *attr,
90 const struct rte_flow_item pattern[],
91 const struct rte_flow_action actions[],
92 struct rte_flow_error *error,
93 union i40e_filter_t *filter);
94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
95 const struct rte_flow_attr *attr,
96 const struct rte_flow_item pattern[],
97 const struct rte_flow_action actions[],
98 struct rte_flow_error *error,
99 union i40e_filter_t *filter);
100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
101 const struct rte_flow_attr *attr,
102 const struct rte_flow_item pattern[],
103 const struct rte_flow_action actions[],
104 struct rte_flow_error *error,
105 union i40e_filter_t *filter);
106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
107 struct i40e_ethertype_filter *filter);
108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
109 struct i40e_tunnel_filter *filter);
110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
114 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
116 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
117 const struct rte_flow_attr *attr,
118 const struct rte_flow_item pattern[],
119 const struct rte_flow_action actions[],
120 struct rte_flow_error *error,
121 union i40e_filter_t *filter);
123 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
124 const struct rte_flow_item *pattern,
125 struct rte_flow_error *error,
126 struct i40e_tunnel_filter_conf *filter);
128 const struct rte_flow_ops i40e_flow_ops = {
129 .validate = i40e_flow_validate,
130 .create = i40e_flow_create,
131 .destroy = i40e_flow_destroy,
132 .flush = i40e_flow_flush,
135 static union i40e_filter_t cons_filter;
136 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
138 /* Pattern matched ethertype filter */
139 static enum rte_flow_item_type pattern_ethertype[] = {
140 RTE_FLOW_ITEM_TYPE_ETH,
141 RTE_FLOW_ITEM_TYPE_END,
144 /* Pattern matched flow director filter */
145 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
146 RTE_FLOW_ITEM_TYPE_ETH,
147 RTE_FLOW_ITEM_TYPE_IPV4,
148 RTE_FLOW_ITEM_TYPE_END,
151 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
152 RTE_FLOW_ITEM_TYPE_ETH,
153 RTE_FLOW_ITEM_TYPE_IPV4,
154 RTE_FLOW_ITEM_TYPE_UDP,
155 RTE_FLOW_ITEM_TYPE_END,
158 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
159 RTE_FLOW_ITEM_TYPE_ETH,
160 RTE_FLOW_ITEM_TYPE_IPV4,
161 RTE_FLOW_ITEM_TYPE_TCP,
162 RTE_FLOW_ITEM_TYPE_END,
165 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
166 RTE_FLOW_ITEM_TYPE_ETH,
167 RTE_FLOW_ITEM_TYPE_IPV4,
168 RTE_FLOW_ITEM_TYPE_SCTP,
169 RTE_FLOW_ITEM_TYPE_END,
172 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
173 RTE_FLOW_ITEM_TYPE_ETH,
174 RTE_FLOW_ITEM_TYPE_IPV4,
175 RTE_FLOW_ITEM_TYPE_UDP,
176 RTE_FLOW_ITEM_TYPE_GTPC,
177 RTE_FLOW_ITEM_TYPE_END,
180 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
181 RTE_FLOW_ITEM_TYPE_ETH,
182 RTE_FLOW_ITEM_TYPE_IPV4,
183 RTE_FLOW_ITEM_TYPE_UDP,
184 RTE_FLOW_ITEM_TYPE_GTPU,
185 RTE_FLOW_ITEM_TYPE_END,
188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
189 RTE_FLOW_ITEM_TYPE_ETH,
190 RTE_FLOW_ITEM_TYPE_IPV4,
191 RTE_FLOW_ITEM_TYPE_UDP,
192 RTE_FLOW_ITEM_TYPE_GTPU,
193 RTE_FLOW_ITEM_TYPE_IPV4,
194 RTE_FLOW_ITEM_TYPE_END,
197 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
198 RTE_FLOW_ITEM_TYPE_ETH,
199 RTE_FLOW_ITEM_TYPE_IPV4,
200 RTE_FLOW_ITEM_TYPE_UDP,
201 RTE_FLOW_ITEM_TYPE_GTPU,
202 RTE_FLOW_ITEM_TYPE_IPV6,
203 RTE_FLOW_ITEM_TYPE_END,
206 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
207 RTE_FLOW_ITEM_TYPE_ETH,
208 RTE_FLOW_ITEM_TYPE_IPV6,
209 RTE_FLOW_ITEM_TYPE_END,
212 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
213 RTE_FLOW_ITEM_TYPE_ETH,
214 RTE_FLOW_ITEM_TYPE_IPV6,
215 RTE_FLOW_ITEM_TYPE_UDP,
216 RTE_FLOW_ITEM_TYPE_END,
219 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
220 RTE_FLOW_ITEM_TYPE_ETH,
221 RTE_FLOW_ITEM_TYPE_IPV6,
222 RTE_FLOW_ITEM_TYPE_TCP,
223 RTE_FLOW_ITEM_TYPE_END,
226 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
227 RTE_FLOW_ITEM_TYPE_ETH,
228 RTE_FLOW_ITEM_TYPE_IPV6,
229 RTE_FLOW_ITEM_TYPE_SCTP,
230 RTE_FLOW_ITEM_TYPE_END,
233 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
234 RTE_FLOW_ITEM_TYPE_ETH,
235 RTE_FLOW_ITEM_TYPE_IPV6,
236 RTE_FLOW_ITEM_TYPE_UDP,
237 RTE_FLOW_ITEM_TYPE_GTPC,
238 RTE_FLOW_ITEM_TYPE_END,
241 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
242 RTE_FLOW_ITEM_TYPE_ETH,
243 RTE_FLOW_ITEM_TYPE_IPV6,
244 RTE_FLOW_ITEM_TYPE_UDP,
245 RTE_FLOW_ITEM_TYPE_GTPU,
246 RTE_FLOW_ITEM_TYPE_END,
249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
250 RTE_FLOW_ITEM_TYPE_ETH,
251 RTE_FLOW_ITEM_TYPE_IPV6,
252 RTE_FLOW_ITEM_TYPE_UDP,
253 RTE_FLOW_ITEM_TYPE_GTPU,
254 RTE_FLOW_ITEM_TYPE_IPV4,
255 RTE_FLOW_ITEM_TYPE_END,
258 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
259 RTE_FLOW_ITEM_TYPE_ETH,
260 RTE_FLOW_ITEM_TYPE_IPV6,
261 RTE_FLOW_ITEM_TYPE_UDP,
262 RTE_FLOW_ITEM_TYPE_GTPU,
263 RTE_FLOW_ITEM_TYPE_IPV6,
264 RTE_FLOW_ITEM_TYPE_END,
267 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
268 RTE_FLOW_ITEM_TYPE_ETH,
269 RTE_FLOW_ITEM_TYPE_RAW,
270 RTE_FLOW_ITEM_TYPE_END,
273 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
274 RTE_FLOW_ITEM_TYPE_ETH,
275 RTE_FLOW_ITEM_TYPE_RAW,
276 RTE_FLOW_ITEM_TYPE_RAW,
277 RTE_FLOW_ITEM_TYPE_END,
280 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
281 RTE_FLOW_ITEM_TYPE_ETH,
282 RTE_FLOW_ITEM_TYPE_RAW,
283 RTE_FLOW_ITEM_TYPE_RAW,
284 RTE_FLOW_ITEM_TYPE_RAW,
285 RTE_FLOW_ITEM_TYPE_END,
288 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
289 RTE_FLOW_ITEM_TYPE_ETH,
290 RTE_FLOW_ITEM_TYPE_IPV4,
291 RTE_FLOW_ITEM_TYPE_RAW,
292 RTE_FLOW_ITEM_TYPE_END,
295 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
296 RTE_FLOW_ITEM_TYPE_ETH,
297 RTE_FLOW_ITEM_TYPE_IPV4,
298 RTE_FLOW_ITEM_TYPE_RAW,
299 RTE_FLOW_ITEM_TYPE_RAW,
300 RTE_FLOW_ITEM_TYPE_END,
303 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
304 RTE_FLOW_ITEM_TYPE_ETH,
305 RTE_FLOW_ITEM_TYPE_IPV4,
306 RTE_FLOW_ITEM_TYPE_RAW,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_RAW,
309 RTE_FLOW_ITEM_TYPE_END,
312 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
313 RTE_FLOW_ITEM_TYPE_ETH,
314 RTE_FLOW_ITEM_TYPE_IPV4,
315 RTE_FLOW_ITEM_TYPE_UDP,
316 RTE_FLOW_ITEM_TYPE_RAW,
317 RTE_FLOW_ITEM_TYPE_END,
320 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
321 RTE_FLOW_ITEM_TYPE_ETH,
322 RTE_FLOW_ITEM_TYPE_IPV4,
323 RTE_FLOW_ITEM_TYPE_UDP,
324 RTE_FLOW_ITEM_TYPE_RAW,
325 RTE_FLOW_ITEM_TYPE_RAW,
326 RTE_FLOW_ITEM_TYPE_END,
329 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
330 RTE_FLOW_ITEM_TYPE_ETH,
331 RTE_FLOW_ITEM_TYPE_IPV4,
332 RTE_FLOW_ITEM_TYPE_UDP,
333 RTE_FLOW_ITEM_TYPE_RAW,
334 RTE_FLOW_ITEM_TYPE_RAW,
335 RTE_FLOW_ITEM_TYPE_RAW,
336 RTE_FLOW_ITEM_TYPE_END,
339 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
340 RTE_FLOW_ITEM_TYPE_ETH,
341 RTE_FLOW_ITEM_TYPE_IPV4,
342 RTE_FLOW_ITEM_TYPE_TCP,
343 RTE_FLOW_ITEM_TYPE_RAW,
344 RTE_FLOW_ITEM_TYPE_END,
347 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
348 RTE_FLOW_ITEM_TYPE_ETH,
349 RTE_FLOW_ITEM_TYPE_IPV4,
350 RTE_FLOW_ITEM_TYPE_TCP,
351 RTE_FLOW_ITEM_TYPE_RAW,
352 RTE_FLOW_ITEM_TYPE_RAW,
353 RTE_FLOW_ITEM_TYPE_END,
356 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
357 RTE_FLOW_ITEM_TYPE_ETH,
358 RTE_FLOW_ITEM_TYPE_IPV4,
359 RTE_FLOW_ITEM_TYPE_TCP,
360 RTE_FLOW_ITEM_TYPE_RAW,
361 RTE_FLOW_ITEM_TYPE_RAW,
362 RTE_FLOW_ITEM_TYPE_RAW,
363 RTE_FLOW_ITEM_TYPE_END,
366 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
367 RTE_FLOW_ITEM_TYPE_ETH,
368 RTE_FLOW_ITEM_TYPE_IPV4,
369 RTE_FLOW_ITEM_TYPE_SCTP,
370 RTE_FLOW_ITEM_TYPE_RAW,
371 RTE_FLOW_ITEM_TYPE_END,
374 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
375 RTE_FLOW_ITEM_TYPE_ETH,
376 RTE_FLOW_ITEM_TYPE_IPV4,
377 RTE_FLOW_ITEM_TYPE_SCTP,
378 RTE_FLOW_ITEM_TYPE_RAW,
379 RTE_FLOW_ITEM_TYPE_RAW,
380 RTE_FLOW_ITEM_TYPE_END,
383 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
384 RTE_FLOW_ITEM_TYPE_ETH,
385 RTE_FLOW_ITEM_TYPE_IPV4,
386 RTE_FLOW_ITEM_TYPE_SCTP,
387 RTE_FLOW_ITEM_TYPE_RAW,
388 RTE_FLOW_ITEM_TYPE_RAW,
389 RTE_FLOW_ITEM_TYPE_RAW,
390 RTE_FLOW_ITEM_TYPE_END,
393 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
394 RTE_FLOW_ITEM_TYPE_ETH,
395 RTE_FLOW_ITEM_TYPE_IPV6,
396 RTE_FLOW_ITEM_TYPE_RAW,
397 RTE_FLOW_ITEM_TYPE_END,
400 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
401 RTE_FLOW_ITEM_TYPE_ETH,
402 RTE_FLOW_ITEM_TYPE_IPV6,
403 RTE_FLOW_ITEM_TYPE_RAW,
404 RTE_FLOW_ITEM_TYPE_RAW,
405 RTE_FLOW_ITEM_TYPE_END,
408 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
409 RTE_FLOW_ITEM_TYPE_ETH,
410 RTE_FLOW_ITEM_TYPE_IPV6,
411 RTE_FLOW_ITEM_TYPE_RAW,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_RAW,
414 RTE_FLOW_ITEM_TYPE_END,
417 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
418 RTE_FLOW_ITEM_TYPE_ETH,
419 RTE_FLOW_ITEM_TYPE_IPV6,
420 RTE_FLOW_ITEM_TYPE_UDP,
421 RTE_FLOW_ITEM_TYPE_RAW,
422 RTE_FLOW_ITEM_TYPE_END,
425 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
426 RTE_FLOW_ITEM_TYPE_ETH,
427 RTE_FLOW_ITEM_TYPE_IPV6,
428 RTE_FLOW_ITEM_TYPE_UDP,
429 RTE_FLOW_ITEM_TYPE_RAW,
430 RTE_FLOW_ITEM_TYPE_RAW,
431 RTE_FLOW_ITEM_TYPE_END,
434 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
435 RTE_FLOW_ITEM_TYPE_ETH,
436 RTE_FLOW_ITEM_TYPE_IPV6,
437 RTE_FLOW_ITEM_TYPE_UDP,
438 RTE_FLOW_ITEM_TYPE_RAW,
439 RTE_FLOW_ITEM_TYPE_RAW,
440 RTE_FLOW_ITEM_TYPE_RAW,
441 RTE_FLOW_ITEM_TYPE_END,
444 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
445 RTE_FLOW_ITEM_TYPE_ETH,
446 RTE_FLOW_ITEM_TYPE_IPV6,
447 RTE_FLOW_ITEM_TYPE_TCP,
448 RTE_FLOW_ITEM_TYPE_RAW,
449 RTE_FLOW_ITEM_TYPE_END,
452 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
453 RTE_FLOW_ITEM_TYPE_ETH,
454 RTE_FLOW_ITEM_TYPE_IPV6,
455 RTE_FLOW_ITEM_TYPE_TCP,
456 RTE_FLOW_ITEM_TYPE_RAW,
457 RTE_FLOW_ITEM_TYPE_RAW,
458 RTE_FLOW_ITEM_TYPE_END,
461 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
462 RTE_FLOW_ITEM_TYPE_ETH,
463 RTE_FLOW_ITEM_TYPE_IPV6,
464 RTE_FLOW_ITEM_TYPE_TCP,
465 RTE_FLOW_ITEM_TYPE_RAW,
466 RTE_FLOW_ITEM_TYPE_RAW,
467 RTE_FLOW_ITEM_TYPE_RAW,
468 RTE_FLOW_ITEM_TYPE_END,
471 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
472 RTE_FLOW_ITEM_TYPE_ETH,
473 RTE_FLOW_ITEM_TYPE_IPV6,
474 RTE_FLOW_ITEM_TYPE_SCTP,
475 RTE_FLOW_ITEM_TYPE_RAW,
476 RTE_FLOW_ITEM_TYPE_END,
479 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
480 RTE_FLOW_ITEM_TYPE_ETH,
481 RTE_FLOW_ITEM_TYPE_IPV6,
482 RTE_FLOW_ITEM_TYPE_SCTP,
483 RTE_FLOW_ITEM_TYPE_RAW,
484 RTE_FLOW_ITEM_TYPE_RAW,
485 RTE_FLOW_ITEM_TYPE_END,
488 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
489 RTE_FLOW_ITEM_TYPE_ETH,
490 RTE_FLOW_ITEM_TYPE_IPV6,
491 RTE_FLOW_ITEM_TYPE_SCTP,
492 RTE_FLOW_ITEM_TYPE_RAW,
493 RTE_FLOW_ITEM_TYPE_RAW,
494 RTE_FLOW_ITEM_TYPE_RAW,
495 RTE_FLOW_ITEM_TYPE_END,
498 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
499 RTE_FLOW_ITEM_TYPE_ETH,
500 RTE_FLOW_ITEM_TYPE_VLAN,
501 RTE_FLOW_ITEM_TYPE_END,
504 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
505 RTE_FLOW_ITEM_TYPE_ETH,
506 RTE_FLOW_ITEM_TYPE_VLAN,
507 RTE_FLOW_ITEM_TYPE_IPV4,
508 RTE_FLOW_ITEM_TYPE_END,
511 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
512 RTE_FLOW_ITEM_TYPE_ETH,
513 RTE_FLOW_ITEM_TYPE_VLAN,
514 RTE_FLOW_ITEM_TYPE_IPV4,
515 RTE_FLOW_ITEM_TYPE_UDP,
516 RTE_FLOW_ITEM_TYPE_END,
519 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
520 RTE_FLOW_ITEM_TYPE_ETH,
521 RTE_FLOW_ITEM_TYPE_VLAN,
522 RTE_FLOW_ITEM_TYPE_IPV4,
523 RTE_FLOW_ITEM_TYPE_TCP,
524 RTE_FLOW_ITEM_TYPE_END,
527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
528 RTE_FLOW_ITEM_TYPE_ETH,
529 RTE_FLOW_ITEM_TYPE_VLAN,
530 RTE_FLOW_ITEM_TYPE_IPV4,
531 RTE_FLOW_ITEM_TYPE_SCTP,
532 RTE_FLOW_ITEM_TYPE_END,
535 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
536 RTE_FLOW_ITEM_TYPE_ETH,
537 RTE_FLOW_ITEM_TYPE_VLAN,
538 RTE_FLOW_ITEM_TYPE_IPV6,
539 RTE_FLOW_ITEM_TYPE_END,
542 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
543 RTE_FLOW_ITEM_TYPE_ETH,
544 RTE_FLOW_ITEM_TYPE_VLAN,
545 RTE_FLOW_ITEM_TYPE_IPV6,
546 RTE_FLOW_ITEM_TYPE_UDP,
547 RTE_FLOW_ITEM_TYPE_END,
550 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
551 RTE_FLOW_ITEM_TYPE_ETH,
552 RTE_FLOW_ITEM_TYPE_VLAN,
553 RTE_FLOW_ITEM_TYPE_IPV6,
554 RTE_FLOW_ITEM_TYPE_TCP,
555 RTE_FLOW_ITEM_TYPE_END,
558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
559 RTE_FLOW_ITEM_TYPE_ETH,
560 RTE_FLOW_ITEM_TYPE_VLAN,
561 RTE_FLOW_ITEM_TYPE_IPV6,
562 RTE_FLOW_ITEM_TYPE_SCTP,
563 RTE_FLOW_ITEM_TYPE_END,
566 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
567 RTE_FLOW_ITEM_TYPE_ETH,
568 RTE_FLOW_ITEM_TYPE_VLAN,
569 RTE_FLOW_ITEM_TYPE_RAW,
570 RTE_FLOW_ITEM_TYPE_END,
573 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
574 RTE_FLOW_ITEM_TYPE_ETH,
575 RTE_FLOW_ITEM_TYPE_VLAN,
576 RTE_FLOW_ITEM_TYPE_RAW,
577 RTE_FLOW_ITEM_TYPE_RAW,
578 RTE_FLOW_ITEM_TYPE_END,
581 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
582 RTE_FLOW_ITEM_TYPE_ETH,
583 RTE_FLOW_ITEM_TYPE_VLAN,
584 RTE_FLOW_ITEM_TYPE_RAW,
585 RTE_FLOW_ITEM_TYPE_RAW,
586 RTE_FLOW_ITEM_TYPE_RAW,
587 RTE_FLOW_ITEM_TYPE_END,
590 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
591 RTE_FLOW_ITEM_TYPE_ETH,
592 RTE_FLOW_ITEM_TYPE_VLAN,
593 RTE_FLOW_ITEM_TYPE_IPV4,
594 RTE_FLOW_ITEM_TYPE_RAW,
595 RTE_FLOW_ITEM_TYPE_END,
598 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
599 RTE_FLOW_ITEM_TYPE_ETH,
600 RTE_FLOW_ITEM_TYPE_VLAN,
601 RTE_FLOW_ITEM_TYPE_IPV4,
602 RTE_FLOW_ITEM_TYPE_RAW,
603 RTE_FLOW_ITEM_TYPE_RAW,
604 RTE_FLOW_ITEM_TYPE_END,
607 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
608 RTE_FLOW_ITEM_TYPE_ETH,
609 RTE_FLOW_ITEM_TYPE_VLAN,
610 RTE_FLOW_ITEM_TYPE_IPV4,
611 RTE_FLOW_ITEM_TYPE_RAW,
612 RTE_FLOW_ITEM_TYPE_RAW,
613 RTE_FLOW_ITEM_TYPE_RAW,
614 RTE_FLOW_ITEM_TYPE_END,
617 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
618 RTE_FLOW_ITEM_TYPE_ETH,
619 RTE_FLOW_ITEM_TYPE_VLAN,
620 RTE_FLOW_ITEM_TYPE_IPV4,
621 RTE_FLOW_ITEM_TYPE_UDP,
622 RTE_FLOW_ITEM_TYPE_RAW,
623 RTE_FLOW_ITEM_TYPE_END,
626 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
627 RTE_FLOW_ITEM_TYPE_ETH,
628 RTE_FLOW_ITEM_TYPE_VLAN,
629 RTE_FLOW_ITEM_TYPE_IPV4,
630 RTE_FLOW_ITEM_TYPE_UDP,
631 RTE_FLOW_ITEM_TYPE_RAW,
632 RTE_FLOW_ITEM_TYPE_RAW,
633 RTE_FLOW_ITEM_TYPE_END,
636 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
637 RTE_FLOW_ITEM_TYPE_ETH,
638 RTE_FLOW_ITEM_TYPE_VLAN,
639 RTE_FLOW_ITEM_TYPE_IPV4,
640 RTE_FLOW_ITEM_TYPE_UDP,
641 RTE_FLOW_ITEM_TYPE_RAW,
642 RTE_FLOW_ITEM_TYPE_RAW,
643 RTE_FLOW_ITEM_TYPE_RAW,
644 RTE_FLOW_ITEM_TYPE_END,
647 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
648 RTE_FLOW_ITEM_TYPE_ETH,
649 RTE_FLOW_ITEM_TYPE_VLAN,
650 RTE_FLOW_ITEM_TYPE_IPV4,
651 RTE_FLOW_ITEM_TYPE_TCP,
652 RTE_FLOW_ITEM_TYPE_RAW,
653 RTE_FLOW_ITEM_TYPE_END,
656 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
657 RTE_FLOW_ITEM_TYPE_ETH,
658 RTE_FLOW_ITEM_TYPE_VLAN,
659 RTE_FLOW_ITEM_TYPE_IPV4,
660 RTE_FLOW_ITEM_TYPE_TCP,
661 RTE_FLOW_ITEM_TYPE_RAW,
662 RTE_FLOW_ITEM_TYPE_RAW,
663 RTE_FLOW_ITEM_TYPE_END,
666 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
667 RTE_FLOW_ITEM_TYPE_ETH,
668 RTE_FLOW_ITEM_TYPE_VLAN,
669 RTE_FLOW_ITEM_TYPE_IPV4,
670 RTE_FLOW_ITEM_TYPE_TCP,
671 RTE_FLOW_ITEM_TYPE_RAW,
672 RTE_FLOW_ITEM_TYPE_RAW,
673 RTE_FLOW_ITEM_TYPE_RAW,
674 RTE_FLOW_ITEM_TYPE_END,
677 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
678 RTE_FLOW_ITEM_TYPE_ETH,
679 RTE_FLOW_ITEM_TYPE_VLAN,
680 RTE_FLOW_ITEM_TYPE_IPV4,
681 RTE_FLOW_ITEM_TYPE_SCTP,
682 RTE_FLOW_ITEM_TYPE_RAW,
683 RTE_FLOW_ITEM_TYPE_END,
686 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
687 RTE_FLOW_ITEM_TYPE_ETH,
688 RTE_FLOW_ITEM_TYPE_VLAN,
689 RTE_FLOW_ITEM_TYPE_IPV4,
690 RTE_FLOW_ITEM_TYPE_SCTP,
691 RTE_FLOW_ITEM_TYPE_RAW,
692 RTE_FLOW_ITEM_TYPE_RAW,
693 RTE_FLOW_ITEM_TYPE_END,
696 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
697 RTE_FLOW_ITEM_TYPE_ETH,
698 RTE_FLOW_ITEM_TYPE_VLAN,
699 RTE_FLOW_ITEM_TYPE_IPV4,
700 RTE_FLOW_ITEM_TYPE_SCTP,
701 RTE_FLOW_ITEM_TYPE_RAW,
702 RTE_FLOW_ITEM_TYPE_RAW,
703 RTE_FLOW_ITEM_TYPE_RAW,
704 RTE_FLOW_ITEM_TYPE_END,
707 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
708 RTE_FLOW_ITEM_TYPE_ETH,
709 RTE_FLOW_ITEM_TYPE_VLAN,
710 RTE_FLOW_ITEM_TYPE_IPV6,
711 RTE_FLOW_ITEM_TYPE_RAW,
712 RTE_FLOW_ITEM_TYPE_END,
715 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
716 RTE_FLOW_ITEM_TYPE_ETH,
717 RTE_FLOW_ITEM_TYPE_VLAN,
718 RTE_FLOW_ITEM_TYPE_IPV6,
719 RTE_FLOW_ITEM_TYPE_RAW,
720 RTE_FLOW_ITEM_TYPE_RAW,
721 RTE_FLOW_ITEM_TYPE_END,
724 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
725 RTE_FLOW_ITEM_TYPE_ETH,
726 RTE_FLOW_ITEM_TYPE_VLAN,
727 RTE_FLOW_ITEM_TYPE_IPV6,
728 RTE_FLOW_ITEM_TYPE_RAW,
729 RTE_FLOW_ITEM_TYPE_RAW,
730 RTE_FLOW_ITEM_TYPE_RAW,
731 RTE_FLOW_ITEM_TYPE_END,
734 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
735 RTE_FLOW_ITEM_TYPE_ETH,
736 RTE_FLOW_ITEM_TYPE_VLAN,
737 RTE_FLOW_ITEM_TYPE_IPV6,
738 RTE_FLOW_ITEM_TYPE_UDP,
739 RTE_FLOW_ITEM_TYPE_RAW,
740 RTE_FLOW_ITEM_TYPE_END,
743 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
744 RTE_FLOW_ITEM_TYPE_ETH,
745 RTE_FLOW_ITEM_TYPE_VLAN,
746 RTE_FLOW_ITEM_TYPE_IPV6,
747 RTE_FLOW_ITEM_TYPE_UDP,
748 RTE_FLOW_ITEM_TYPE_RAW,
749 RTE_FLOW_ITEM_TYPE_RAW,
750 RTE_FLOW_ITEM_TYPE_END,
753 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
754 RTE_FLOW_ITEM_TYPE_ETH,
755 RTE_FLOW_ITEM_TYPE_VLAN,
756 RTE_FLOW_ITEM_TYPE_IPV6,
757 RTE_FLOW_ITEM_TYPE_UDP,
758 RTE_FLOW_ITEM_TYPE_RAW,
759 RTE_FLOW_ITEM_TYPE_RAW,
760 RTE_FLOW_ITEM_TYPE_RAW,
761 RTE_FLOW_ITEM_TYPE_END,
764 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
765 RTE_FLOW_ITEM_TYPE_ETH,
766 RTE_FLOW_ITEM_TYPE_VLAN,
767 RTE_FLOW_ITEM_TYPE_IPV6,
768 RTE_FLOW_ITEM_TYPE_TCP,
769 RTE_FLOW_ITEM_TYPE_RAW,
770 RTE_FLOW_ITEM_TYPE_END,
773 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
774 RTE_FLOW_ITEM_TYPE_ETH,
775 RTE_FLOW_ITEM_TYPE_VLAN,
776 RTE_FLOW_ITEM_TYPE_IPV6,
777 RTE_FLOW_ITEM_TYPE_TCP,
778 RTE_FLOW_ITEM_TYPE_RAW,
779 RTE_FLOW_ITEM_TYPE_RAW,
780 RTE_FLOW_ITEM_TYPE_END,
783 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
784 RTE_FLOW_ITEM_TYPE_ETH,
785 RTE_FLOW_ITEM_TYPE_VLAN,
786 RTE_FLOW_ITEM_TYPE_IPV6,
787 RTE_FLOW_ITEM_TYPE_TCP,
788 RTE_FLOW_ITEM_TYPE_RAW,
789 RTE_FLOW_ITEM_TYPE_RAW,
790 RTE_FLOW_ITEM_TYPE_RAW,
791 RTE_FLOW_ITEM_TYPE_END,
794 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
795 RTE_FLOW_ITEM_TYPE_ETH,
796 RTE_FLOW_ITEM_TYPE_VLAN,
797 RTE_FLOW_ITEM_TYPE_IPV6,
798 RTE_FLOW_ITEM_TYPE_SCTP,
799 RTE_FLOW_ITEM_TYPE_RAW,
800 RTE_FLOW_ITEM_TYPE_END,
803 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
804 RTE_FLOW_ITEM_TYPE_ETH,
805 RTE_FLOW_ITEM_TYPE_VLAN,
806 RTE_FLOW_ITEM_TYPE_IPV6,
807 RTE_FLOW_ITEM_TYPE_SCTP,
808 RTE_FLOW_ITEM_TYPE_RAW,
809 RTE_FLOW_ITEM_TYPE_RAW,
810 RTE_FLOW_ITEM_TYPE_END,
813 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
814 RTE_FLOW_ITEM_TYPE_ETH,
815 RTE_FLOW_ITEM_TYPE_VLAN,
816 RTE_FLOW_ITEM_TYPE_IPV6,
817 RTE_FLOW_ITEM_TYPE_SCTP,
818 RTE_FLOW_ITEM_TYPE_RAW,
819 RTE_FLOW_ITEM_TYPE_RAW,
820 RTE_FLOW_ITEM_TYPE_RAW,
821 RTE_FLOW_ITEM_TYPE_END,
824 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
825 RTE_FLOW_ITEM_TYPE_ETH,
826 RTE_FLOW_ITEM_TYPE_IPV4,
827 RTE_FLOW_ITEM_TYPE_VF,
828 RTE_FLOW_ITEM_TYPE_END,
831 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
832 RTE_FLOW_ITEM_TYPE_ETH,
833 RTE_FLOW_ITEM_TYPE_IPV4,
834 RTE_FLOW_ITEM_TYPE_UDP,
835 RTE_FLOW_ITEM_TYPE_VF,
836 RTE_FLOW_ITEM_TYPE_END,
839 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
840 RTE_FLOW_ITEM_TYPE_ETH,
841 RTE_FLOW_ITEM_TYPE_IPV4,
842 RTE_FLOW_ITEM_TYPE_TCP,
843 RTE_FLOW_ITEM_TYPE_VF,
844 RTE_FLOW_ITEM_TYPE_END,
847 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
848 RTE_FLOW_ITEM_TYPE_ETH,
849 RTE_FLOW_ITEM_TYPE_IPV4,
850 RTE_FLOW_ITEM_TYPE_SCTP,
851 RTE_FLOW_ITEM_TYPE_VF,
852 RTE_FLOW_ITEM_TYPE_END,
855 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
856 RTE_FLOW_ITEM_TYPE_ETH,
857 RTE_FLOW_ITEM_TYPE_IPV6,
858 RTE_FLOW_ITEM_TYPE_VF,
859 RTE_FLOW_ITEM_TYPE_END,
862 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
863 RTE_FLOW_ITEM_TYPE_ETH,
864 RTE_FLOW_ITEM_TYPE_IPV6,
865 RTE_FLOW_ITEM_TYPE_UDP,
866 RTE_FLOW_ITEM_TYPE_VF,
867 RTE_FLOW_ITEM_TYPE_END,
870 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
871 RTE_FLOW_ITEM_TYPE_ETH,
872 RTE_FLOW_ITEM_TYPE_IPV6,
873 RTE_FLOW_ITEM_TYPE_TCP,
874 RTE_FLOW_ITEM_TYPE_VF,
875 RTE_FLOW_ITEM_TYPE_END,
878 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
879 RTE_FLOW_ITEM_TYPE_ETH,
880 RTE_FLOW_ITEM_TYPE_IPV6,
881 RTE_FLOW_ITEM_TYPE_SCTP,
882 RTE_FLOW_ITEM_TYPE_VF,
883 RTE_FLOW_ITEM_TYPE_END,
886 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
887 RTE_FLOW_ITEM_TYPE_ETH,
888 RTE_FLOW_ITEM_TYPE_RAW,
889 RTE_FLOW_ITEM_TYPE_VF,
890 RTE_FLOW_ITEM_TYPE_END,
893 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
894 RTE_FLOW_ITEM_TYPE_ETH,
895 RTE_FLOW_ITEM_TYPE_RAW,
896 RTE_FLOW_ITEM_TYPE_RAW,
897 RTE_FLOW_ITEM_TYPE_VF,
898 RTE_FLOW_ITEM_TYPE_END,
901 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
902 RTE_FLOW_ITEM_TYPE_ETH,
903 RTE_FLOW_ITEM_TYPE_RAW,
904 RTE_FLOW_ITEM_TYPE_RAW,
905 RTE_FLOW_ITEM_TYPE_RAW,
906 RTE_FLOW_ITEM_TYPE_VF,
907 RTE_FLOW_ITEM_TYPE_END,
910 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
911 RTE_FLOW_ITEM_TYPE_ETH,
912 RTE_FLOW_ITEM_TYPE_IPV4,
913 RTE_FLOW_ITEM_TYPE_RAW,
914 RTE_FLOW_ITEM_TYPE_VF,
915 RTE_FLOW_ITEM_TYPE_END,
918 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
919 RTE_FLOW_ITEM_TYPE_ETH,
920 RTE_FLOW_ITEM_TYPE_IPV4,
921 RTE_FLOW_ITEM_TYPE_RAW,
922 RTE_FLOW_ITEM_TYPE_RAW,
923 RTE_FLOW_ITEM_TYPE_VF,
924 RTE_FLOW_ITEM_TYPE_END,
927 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
928 RTE_FLOW_ITEM_TYPE_ETH,
929 RTE_FLOW_ITEM_TYPE_IPV4,
930 RTE_FLOW_ITEM_TYPE_RAW,
931 RTE_FLOW_ITEM_TYPE_RAW,
932 RTE_FLOW_ITEM_TYPE_RAW,
933 RTE_FLOW_ITEM_TYPE_VF,
934 RTE_FLOW_ITEM_TYPE_END,
937 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
938 RTE_FLOW_ITEM_TYPE_ETH,
939 RTE_FLOW_ITEM_TYPE_IPV4,
940 RTE_FLOW_ITEM_TYPE_UDP,
941 RTE_FLOW_ITEM_TYPE_RAW,
942 RTE_FLOW_ITEM_TYPE_VF,
943 RTE_FLOW_ITEM_TYPE_END,
946 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
947 RTE_FLOW_ITEM_TYPE_ETH,
948 RTE_FLOW_ITEM_TYPE_IPV4,
949 RTE_FLOW_ITEM_TYPE_UDP,
950 RTE_FLOW_ITEM_TYPE_RAW,
951 RTE_FLOW_ITEM_TYPE_RAW,
952 RTE_FLOW_ITEM_TYPE_VF,
953 RTE_FLOW_ITEM_TYPE_END,
956 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
957 RTE_FLOW_ITEM_TYPE_ETH,
958 RTE_FLOW_ITEM_TYPE_IPV4,
959 RTE_FLOW_ITEM_TYPE_UDP,
960 RTE_FLOW_ITEM_TYPE_RAW,
961 RTE_FLOW_ITEM_TYPE_RAW,
962 RTE_FLOW_ITEM_TYPE_RAW,
963 RTE_FLOW_ITEM_TYPE_VF,
964 RTE_FLOW_ITEM_TYPE_END,
967 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
968 RTE_FLOW_ITEM_TYPE_ETH,
969 RTE_FLOW_ITEM_TYPE_IPV4,
970 RTE_FLOW_ITEM_TYPE_TCP,
971 RTE_FLOW_ITEM_TYPE_RAW,
972 RTE_FLOW_ITEM_TYPE_VF,
973 RTE_FLOW_ITEM_TYPE_END,
976 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
977 RTE_FLOW_ITEM_TYPE_ETH,
978 RTE_FLOW_ITEM_TYPE_IPV4,
979 RTE_FLOW_ITEM_TYPE_TCP,
980 RTE_FLOW_ITEM_TYPE_RAW,
981 RTE_FLOW_ITEM_TYPE_RAW,
982 RTE_FLOW_ITEM_TYPE_VF,
983 RTE_FLOW_ITEM_TYPE_END,
986 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
987 RTE_FLOW_ITEM_TYPE_ETH,
988 RTE_FLOW_ITEM_TYPE_IPV4,
989 RTE_FLOW_ITEM_TYPE_TCP,
990 RTE_FLOW_ITEM_TYPE_RAW,
991 RTE_FLOW_ITEM_TYPE_RAW,
992 RTE_FLOW_ITEM_TYPE_RAW,
993 RTE_FLOW_ITEM_TYPE_VF,
994 RTE_FLOW_ITEM_TYPE_END,
997 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
998 RTE_FLOW_ITEM_TYPE_ETH,
999 RTE_FLOW_ITEM_TYPE_IPV4,
1000 RTE_FLOW_ITEM_TYPE_SCTP,
1001 RTE_FLOW_ITEM_TYPE_RAW,
1002 RTE_FLOW_ITEM_TYPE_VF,
1003 RTE_FLOW_ITEM_TYPE_END,
1006 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1007 RTE_FLOW_ITEM_TYPE_ETH,
1008 RTE_FLOW_ITEM_TYPE_IPV4,
1009 RTE_FLOW_ITEM_TYPE_SCTP,
1010 RTE_FLOW_ITEM_TYPE_RAW,
1011 RTE_FLOW_ITEM_TYPE_RAW,
1012 RTE_FLOW_ITEM_TYPE_VF,
1013 RTE_FLOW_ITEM_TYPE_END,
1016 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1017 RTE_FLOW_ITEM_TYPE_ETH,
1018 RTE_FLOW_ITEM_TYPE_IPV4,
1019 RTE_FLOW_ITEM_TYPE_SCTP,
1020 RTE_FLOW_ITEM_TYPE_RAW,
1021 RTE_FLOW_ITEM_TYPE_RAW,
1022 RTE_FLOW_ITEM_TYPE_RAW,
1023 RTE_FLOW_ITEM_TYPE_VF,
1024 RTE_FLOW_ITEM_TYPE_END,
1027 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1028 RTE_FLOW_ITEM_TYPE_ETH,
1029 RTE_FLOW_ITEM_TYPE_IPV6,
1030 RTE_FLOW_ITEM_TYPE_RAW,
1031 RTE_FLOW_ITEM_TYPE_VF,
1032 RTE_FLOW_ITEM_TYPE_END,
1035 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1036 RTE_FLOW_ITEM_TYPE_ETH,
1037 RTE_FLOW_ITEM_TYPE_IPV6,
1038 RTE_FLOW_ITEM_TYPE_RAW,
1039 RTE_FLOW_ITEM_TYPE_RAW,
1040 RTE_FLOW_ITEM_TYPE_VF,
1041 RTE_FLOW_ITEM_TYPE_END,
1044 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1045 RTE_FLOW_ITEM_TYPE_ETH,
1046 RTE_FLOW_ITEM_TYPE_IPV6,
1047 RTE_FLOW_ITEM_TYPE_RAW,
1048 RTE_FLOW_ITEM_TYPE_RAW,
1049 RTE_FLOW_ITEM_TYPE_RAW,
1050 RTE_FLOW_ITEM_TYPE_VF,
1051 RTE_FLOW_ITEM_TYPE_END,
1054 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1055 RTE_FLOW_ITEM_TYPE_ETH,
1056 RTE_FLOW_ITEM_TYPE_IPV6,
1057 RTE_FLOW_ITEM_TYPE_UDP,
1058 RTE_FLOW_ITEM_TYPE_RAW,
1059 RTE_FLOW_ITEM_TYPE_VF,
1060 RTE_FLOW_ITEM_TYPE_END,
1063 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1064 RTE_FLOW_ITEM_TYPE_ETH,
1065 RTE_FLOW_ITEM_TYPE_IPV6,
1066 RTE_FLOW_ITEM_TYPE_UDP,
1067 RTE_FLOW_ITEM_TYPE_RAW,
1068 RTE_FLOW_ITEM_TYPE_RAW,
1069 RTE_FLOW_ITEM_TYPE_VF,
1070 RTE_FLOW_ITEM_TYPE_END,
1073 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1074 RTE_FLOW_ITEM_TYPE_ETH,
1075 RTE_FLOW_ITEM_TYPE_IPV6,
1076 RTE_FLOW_ITEM_TYPE_UDP,
1077 RTE_FLOW_ITEM_TYPE_RAW,
1078 RTE_FLOW_ITEM_TYPE_RAW,
1079 RTE_FLOW_ITEM_TYPE_RAW,
1080 RTE_FLOW_ITEM_TYPE_VF,
1081 RTE_FLOW_ITEM_TYPE_END,
1084 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1085 RTE_FLOW_ITEM_TYPE_ETH,
1086 RTE_FLOW_ITEM_TYPE_IPV6,
1087 RTE_FLOW_ITEM_TYPE_TCP,
1088 RTE_FLOW_ITEM_TYPE_RAW,
1089 RTE_FLOW_ITEM_TYPE_VF,
1090 RTE_FLOW_ITEM_TYPE_END,
1093 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1094 RTE_FLOW_ITEM_TYPE_ETH,
1095 RTE_FLOW_ITEM_TYPE_IPV6,
1096 RTE_FLOW_ITEM_TYPE_TCP,
1097 RTE_FLOW_ITEM_TYPE_RAW,
1098 RTE_FLOW_ITEM_TYPE_RAW,
1099 RTE_FLOW_ITEM_TYPE_VF,
1100 RTE_FLOW_ITEM_TYPE_END,
1103 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1104 RTE_FLOW_ITEM_TYPE_ETH,
1105 RTE_FLOW_ITEM_TYPE_IPV6,
1106 RTE_FLOW_ITEM_TYPE_TCP,
1107 RTE_FLOW_ITEM_TYPE_RAW,
1108 RTE_FLOW_ITEM_TYPE_RAW,
1109 RTE_FLOW_ITEM_TYPE_RAW,
1110 RTE_FLOW_ITEM_TYPE_VF,
1111 RTE_FLOW_ITEM_TYPE_END,
1114 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1115 RTE_FLOW_ITEM_TYPE_ETH,
1116 RTE_FLOW_ITEM_TYPE_IPV6,
1117 RTE_FLOW_ITEM_TYPE_SCTP,
1118 RTE_FLOW_ITEM_TYPE_RAW,
1119 RTE_FLOW_ITEM_TYPE_VF,
1120 RTE_FLOW_ITEM_TYPE_END,
1123 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1124 RTE_FLOW_ITEM_TYPE_ETH,
1125 RTE_FLOW_ITEM_TYPE_IPV6,
1126 RTE_FLOW_ITEM_TYPE_SCTP,
1127 RTE_FLOW_ITEM_TYPE_RAW,
1128 RTE_FLOW_ITEM_TYPE_RAW,
1129 RTE_FLOW_ITEM_TYPE_VF,
1130 RTE_FLOW_ITEM_TYPE_END,
1133 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1134 RTE_FLOW_ITEM_TYPE_ETH,
1135 RTE_FLOW_ITEM_TYPE_IPV6,
1136 RTE_FLOW_ITEM_TYPE_SCTP,
1137 RTE_FLOW_ITEM_TYPE_RAW,
1138 RTE_FLOW_ITEM_TYPE_RAW,
1139 RTE_FLOW_ITEM_TYPE_RAW,
1140 RTE_FLOW_ITEM_TYPE_VF,
1141 RTE_FLOW_ITEM_TYPE_END,
1144 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1145 RTE_FLOW_ITEM_TYPE_ETH,
1146 RTE_FLOW_ITEM_TYPE_VLAN,
1147 RTE_FLOW_ITEM_TYPE_VF,
1148 RTE_FLOW_ITEM_TYPE_END,
1151 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1152 RTE_FLOW_ITEM_TYPE_ETH,
1153 RTE_FLOW_ITEM_TYPE_VLAN,
1154 RTE_FLOW_ITEM_TYPE_IPV4,
1155 RTE_FLOW_ITEM_TYPE_VF,
1156 RTE_FLOW_ITEM_TYPE_END,
1159 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1160 RTE_FLOW_ITEM_TYPE_ETH,
1161 RTE_FLOW_ITEM_TYPE_VLAN,
1162 RTE_FLOW_ITEM_TYPE_IPV4,
1163 RTE_FLOW_ITEM_TYPE_UDP,
1164 RTE_FLOW_ITEM_TYPE_VF,
1165 RTE_FLOW_ITEM_TYPE_END,
1168 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1169 RTE_FLOW_ITEM_TYPE_ETH,
1170 RTE_FLOW_ITEM_TYPE_VLAN,
1171 RTE_FLOW_ITEM_TYPE_IPV4,
1172 RTE_FLOW_ITEM_TYPE_TCP,
1173 RTE_FLOW_ITEM_TYPE_VF,
1174 RTE_FLOW_ITEM_TYPE_END,
1177 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1178 RTE_FLOW_ITEM_TYPE_ETH,
1179 RTE_FLOW_ITEM_TYPE_VLAN,
1180 RTE_FLOW_ITEM_TYPE_IPV4,
1181 RTE_FLOW_ITEM_TYPE_SCTP,
1182 RTE_FLOW_ITEM_TYPE_VF,
1183 RTE_FLOW_ITEM_TYPE_END,
1186 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1187 RTE_FLOW_ITEM_TYPE_ETH,
1188 RTE_FLOW_ITEM_TYPE_VLAN,
1189 RTE_FLOW_ITEM_TYPE_IPV6,
1190 RTE_FLOW_ITEM_TYPE_VF,
1191 RTE_FLOW_ITEM_TYPE_END,
1194 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1195 RTE_FLOW_ITEM_TYPE_ETH,
1196 RTE_FLOW_ITEM_TYPE_VLAN,
1197 RTE_FLOW_ITEM_TYPE_IPV6,
1198 RTE_FLOW_ITEM_TYPE_UDP,
1199 RTE_FLOW_ITEM_TYPE_VF,
1200 RTE_FLOW_ITEM_TYPE_END,
1203 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1204 RTE_FLOW_ITEM_TYPE_ETH,
1205 RTE_FLOW_ITEM_TYPE_VLAN,
1206 RTE_FLOW_ITEM_TYPE_IPV6,
1207 RTE_FLOW_ITEM_TYPE_TCP,
1208 RTE_FLOW_ITEM_TYPE_VF,
1209 RTE_FLOW_ITEM_TYPE_END,
1212 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1213 RTE_FLOW_ITEM_TYPE_ETH,
1214 RTE_FLOW_ITEM_TYPE_VLAN,
1215 RTE_FLOW_ITEM_TYPE_IPV6,
1216 RTE_FLOW_ITEM_TYPE_SCTP,
1217 RTE_FLOW_ITEM_TYPE_VF,
1218 RTE_FLOW_ITEM_TYPE_END,
1221 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1222 RTE_FLOW_ITEM_TYPE_ETH,
1223 RTE_FLOW_ITEM_TYPE_VLAN,
1224 RTE_FLOW_ITEM_TYPE_RAW,
1225 RTE_FLOW_ITEM_TYPE_VF,
1226 RTE_FLOW_ITEM_TYPE_END,
1229 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1230 RTE_FLOW_ITEM_TYPE_ETH,
1231 RTE_FLOW_ITEM_TYPE_VLAN,
1232 RTE_FLOW_ITEM_TYPE_RAW,
1233 RTE_FLOW_ITEM_TYPE_RAW,
1234 RTE_FLOW_ITEM_TYPE_VF,
1235 RTE_FLOW_ITEM_TYPE_END,
1238 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1239 RTE_FLOW_ITEM_TYPE_ETH,
1240 RTE_FLOW_ITEM_TYPE_VLAN,
1241 RTE_FLOW_ITEM_TYPE_RAW,
1242 RTE_FLOW_ITEM_TYPE_RAW,
1243 RTE_FLOW_ITEM_TYPE_RAW,
1244 RTE_FLOW_ITEM_TYPE_VF,
1245 RTE_FLOW_ITEM_TYPE_END,
1248 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1249 RTE_FLOW_ITEM_TYPE_ETH,
1250 RTE_FLOW_ITEM_TYPE_VLAN,
1251 RTE_FLOW_ITEM_TYPE_IPV4,
1252 RTE_FLOW_ITEM_TYPE_RAW,
1253 RTE_FLOW_ITEM_TYPE_VF,
1254 RTE_FLOW_ITEM_TYPE_END,
1257 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1258 RTE_FLOW_ITEM_TYPE_ETH,
1259 RTE_FLOW_ITEM_TYPE_VLAN,
1260 RTE_FLOW_ITEM_TYPE_IPV4,
1261 RTE_FLOW_ITEM_TYPE_RAW,
1262 RTE_FLOW_ITEM_TYPE_RAW,
1263 RTE_FLOW_ITEM_TYPE_VF,
1264 RTE_FLOW_ITEM_TYPE_END,
1267 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1268 RTE_FLOW_ITEM_TYPE_ETH,
1269 RTE_FLOW_ITEM_TYPE_VLAN,
1270 RTE_FLOW_ITEM_TYPE_IPV4,
1271 RTE_FLOW_ITEM_TYPE_RAW,
1272 RTE_FLOW_ITEM_TYPE_RAW,
1273 RTE_FLOW_ITEM_TYPE_RAW,
1274 RTE_FLOW_ITEM_TYPE_VF,
1275 RTE_FLOW_ITEM_TYPE_END,
1278 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1279 RTE_FLOW_ITEM_TYPE_ETH,
1280 RTE_FLOW_ITEM_TYPE_VLAN,
1281 RTE_FLOW_ITEM_TYPE_IPV4,
1282 RTE_FLOW_ITEM_TYPE_UDP,
1283 RTE_FLOW_ITEM_TYPE_RAW,
1284 RTE_FLOW_ITEM_TYPE_VF,
1285 RTE_FLOW_ITEM_TYPE_END,
1288 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1289 RTE_FLOW_ITEM_TYPE_ETH,
1290 RTE_FLOW_ITEM_TYPE_VLAN,
1291 RTE_FLOW_ITEM_TYPE_IPV4,
1292 RTE_FLOW_ITEM_TYPE_UDP,
1293 RTE_FLOW_ITEM_TYPE_RAW,
1294 RTE_FLOW_ITEM_TYPE_RAW,
1295 RTE_FLOW_ITEM_TYPE_VF,
1296 RTE_FLOW_ITEM_TYPE_END,
1299 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1300 RTE_FLOW_ITEM_TYPE_ETH,
1301 RTE_FLOW_ITEM_TYPE_VLAN,
1302 RTE_FLOW_ITEM_TYPE_IPV4,
1303 RTE_FLOW_ITEM_TYPE_UDP,
1304 RTE_FLOW_ITEM_TYPE_RAW,
1305 RTE_FLOW_ITEM_TYPE_RAW,
1306 RTE_FLOW_ITEM_TYPE_RAW,
1307 RTE_FLOW_ITEM_TYPE_VF,
1308 RTE_FLOW_ITEM_TYPE_END,
1311 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1312 RTE_FLOW_ITEM_TYPE_ETH,
1313 RTE_FLOW_ITEM_TYPE_VLAN,
1314 RTE_FLOW_ITEM_TYPE_IPV4,
1315 RTE_FLOW_ITEM_TYPE_TCP,
1316 RTE_FLOW_ITEM_TYPE_RAW,
1317 RTE_FLOW_ITEM_TYPE_VF,
1318 RTE_FLOW_ITEM_TYPE_END,
1321 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1322 RTE_FLOW_ITEM_TYPE_ETH,
1323 RTE_FLOW_ITEM_TYPE_VLAN,
1324 RTE_FLOW_ITEM_TYPE_IPV4,
1325 RTE_FLOW_ITEM_TYPE_TCP,
1326 RTE_FLOW_ITEM_TYPE_RAW,
1327 RTE_FLOW_ITEM_TYPE_RAW,
1328 RTE_FLOW_ITEM_TYPE_VF,
1329 RTE_FLOW_ITEM_TYPE_END,
1332 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1333 RTE_FLOW_ITEM_TYPE_ETH,
1334 RTE_FLOW_ITEM_TYPE_VLAN,
1335 RTE_FLOW_ITEM_TYPE_IPV4,
1336 RTE_FLOW_ITEM_TYPE_TCP,
1337 RTE_FLOW_ITEM_TYPE_RAW,
1338 RTE_FLOW_ITEM_TYPE_RAW,
1339 RTE_FLOW_ITEM_TYPE_RAW,
1340 RTE_FLOW_ITEM_TYPE_VF,
1341 RTE_FLOW_ITEM_TYPE_END,
1344 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1345 RTE_FLOW_ITEM_TYPE_ETH,
1346 RTE_FLOW_ITEM_TYPE_VLAN,
1347 RTE_FLOW_ITEM_TYPE_IPV4,
1348 RTE_FLOW_ITEM_TYPE_SCTP,
1349 RTE_FLOW_ITEM_TYPE_RAW,
1350 RTE_FLOW_ITEM_TYPE_VF,
1351 RTE_FLOW_ITEM_TYPE_END,
1354 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1355 RTE_FLOW_ITEM_TYPE_ETH,
1356 RTE_FLOW_ITEM_TYPE_VLAN,
1357 RTE_FLOW_ITEM_TYPE_IPV4,
1358 RTE_FLOW_ITEM_TYPE_SCTP,
1359 RTE_FLOW_ITEM_TYPE_RAW,
1360 RTE_FLOW_ITEM_TYPE_RAW,
1361 RTE_FLOW_ITEM_TYPE_VF,
1362 RTE_FLOW_ITEM_TYPE_END,
1365 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1366 RTE_FLOW_ITEM_TYPE_ETH,
1367 RTE_FLOW_ITEM_TYPE_VLAN,
1368 RTE_FLOW_ITEM_TYPE_IPV4,
1369 RTE_FLOW_ITEM_TYPE_SCTP,
1370 RTE_FLOW_ITEM_TYPE_RAW,
1371 RTE_FLOW_ITEM_TYPE_RAW,
1372 RTE_FLOW_ITEM_TYPE_RAW,
1373 RTE_FLOW_ITEM_TYPE_VF,
1374 RTE_FLOW_ITEM_TYPE_END,
1377 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1378 RTE_FLOW_ITEM_TYPE_ETH,
1379 RTE_FLOW_ITEM_TYPE_VLAN,
1380 RTE_FLOW_ITEM_TYPE_IPV6,
1381 RTE_FLOW_ITEM_TYPE_RAW,
1382 RTE_FLOW_ITEM_TYPE_VF,
1383 RTE_FLOW_ITEM_TYPE_END,
1386 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1387 RTE_FLOW_ITEM_TYPE_ETH,
1388 RTE_FLOW_ITEM_TYPE_VLAN,
1389 RTE_FLOW_ITEM_TYPE_IPV6,
1390 RTE_FLOW_ITEM_TYPE_RAW,
1391 RTE_FLOW_ITEM_TYPE_RAW,
1392 RTE_FLOW_ITEM_TYPE_VF,
1393 RTE_FLOW_ITEM_TYPE_END,
1396 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1397 RTE_FLOW_ITEM_TYPE_ETH,
1398 RTE_FLOW_ITEM_TYPE_VLAN,
1399 RTE_FLOW_ITEM_TYPE_IPV6,
1400 RTE_FLOW_ITEM_TYPE_RAW,
1401 RTE_FLOW_ITEM_TYPE_RAW,
1402 RTE_FLOW_ITEM_TYPE_RAW,
1403 RTE_FLOW_ITEM_TYPE_VF,
1404 RTE_FLOW_ITEM_TYPE_END,
1407 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1408 RTE_FLOW_ITEM_TYPE_ETH,
1409 RTE_FLOW_ITEM_TYPE_VLAN,
1410 RTE_FLOW_ITEM_TYPE_IPV6,
1411 RTE_FLOW_ITEM_TYPE_UDP,
1412 RTE_FLOW_ITEM_TYPE_RAW,
1413 RTE_FLOW_ITEM_TYPE_VF,
1414 RTE_FLOW_ITEM_TYPE_END,
1417 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1418 RTE_FLOW_ITEM_TYPE_ETH,
1419 RTE_FLOW_ITEM_TYPE_VLAN,
1420 RTE_FLOW_ITEM_TYPE_IPV6,
1421 RTE_FLOW_ITEM_TYPE_UDP,
1422 RTE_FLOW_ITEM_TYPE_RAW,
1423 RTE_FLOW_ITEM_TYPE_RAW,
1424 RTE_FLOW_ITEM_TYPE_VF,
1425 RTE_FLOW_ITEM_TYPE_END,
1428 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1429 RTE_FLOW_ITEM_TYPE_ETH,
1430 RTE_FLOW_ITEM_TYPE_VLAN,
1431 RTE_FLOW_ITEM_TYPE_IPV6,
1432 RTE_FLOW_ITEM_TYPE_UDP,
1433 RTE_FLOW_ITEM_TYPE_RAW,
1434 RTE_FLOW_ITEM_TYPE_RAW,
1435 RTE_FLOW_ITEM_TYPE_RAW,
1436 RTE_FLOW_ITEM_TYPE_VF,
1437 RTE_FLOW_ITEM_TYPE_END,
1440 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1441 RTE_FLOW_ITEM_TYPE_ETH,
1442 RTE_FLOW_ITEM_TYPE_VLAN,
1443 RTE_FLOW_ITEM_TYPE_IPV6,
1444 RTE_FLOW_ITEM_TYPE_TCP,
1445 RTE_FLOW_ITEM_TYPE_RAW,
1446 RTE_FLOW_ITEM_TYPE_VF,
1447 RTE_FLOW_ITEM_TYPE_END,
1450 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1451 RTE_FLOW_ITEM_TYPE_ETH,
1452 RTE_FLOW_ITEM_TYPE_VLAN,
1453 RTE_FLOW_ITEM_TYPE_IPV6,
1454 RTE_FLOW_ITEM_TYPE_TCP,
1455 RTE_FLOW_ITEM_TYPE_RAW,
1456 RTE_FLOW_ITEM_TYPE_RAW,
1457 RTE_FLOW_ITEM_TYPE_VF,
1458 RTE_FLOW_ITEM_TYPE_END,
1461 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1462 RTE_FLOW_ITEM_TYPE_ETH,
1463 RTE_FLOW_ITEM_TYPE_VLAN,
1464 RTE_FLOW_ITEM_TYPE_IPV6,
1465 RTE_FLOW_ITEM_TYPE_TCP,
1466 RTE_FLOW_ITEM_TYPE_RAW,
1467 RTE_FLOW_ITEM_TYPE_RAW,
1468 RTE_FLOW_ITEM_TYPE_RAW,
1469 RTE_FLOW_ITEM_TYPE_VF,
1470 RTE_FLOW_ITEM_TYPE_END,
1473 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1474 RTE_FLOW_ITEM_TYPE_ETH,
1475 RTE_FLOW_ITEM_TYPE_VLAN,
1476 RTE_FLOW_ITEM_TYPE_IPV6,
1477 RTE_FLOW_ITEM_TYPE_SCTP,
1478 RTE_FLOW_ITEM_TYPE_RAW,
1479 RTE_FLOW_ITEM_TYPE_VF,
1480 RTE_FLOW_ITEM_TYPE_END,
1483 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1484 RTE_FLOW_ITEM_TYPE_ETH,
1485 RTE_FLOW_ITEM_TYPE_VLAN,
1486 RTE_FLOW_ITEM_TYPE_IPV6,
1487 RTE_FLOW_ITEM_TYPE_SCTP,
1488 RTE_FLOW_ITEM_TYPE_RAW,
1489 RTE_FLOW_ITEM_TYPE_RAW,
1490 RTE_FLOW_ITEM_TYPE_VF,
1491 RTE_FLOW_ITEM_TYPE_END,
1494 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1495 RTE_FLOW_ITEM_TYPE_ETH,
1496 RTE_FLOW_ITEM_TYPE_VLAN,
1497 RTE_FLOW_ITEM_TYPE_IPV6,
1498 RTE_FLOW_ITEM_TYPE_SCTP,
1499 RTE_FLOW_ITEM_TYPE_RAW,
1500 RTE_FLOW_ITEM_TYPE_RAW,
1501 RTE_FLOW_ITEM_TYPE_RAW,
1502 RTE_FLOW_ITEM_TYPE_VF,
1503 RTE_FLOW_ITEM_TYPE_END,
1506 /* Pattern matched tunnel filter */
1507 static enum rte_flow_item_type pattern_vxlan_1[] = {
1508 RTE_FLOW_ITEM_TYPE_ETH,
1509 RTE_FLOW_ITEM_TYPE_IPV4,
1510 RTE_FLOW_ITEM_TYPE_UDP,
1511 RTE_FLOW_ITEM_TYPE_VXLAN,
1512 RTE_FLOW_ITEM_TYPE_ETH,
1513 RTE_FLOW_ITEM_TYPE_END,
1516 static enum rte_flow_item_type pattern_vxlan_2[] = {
1517 RTE_FLOW_ITEM_TYPE_ETH,
1518 RTE_FLOW_ITEM_TYPE_IPV6,
1519 RTE_FLOW_ITEM_TYPE_UDP,
1520 RTE_FLOW_ITEM_TYPE_VXLAN,
1521 RTE_FLOW_ITEM_TYPE_ETH,
1522 RTE_FLOW_ITEM_TYPE_END,
1525 static enum rte_flow_item_type pattern_vxlan_3[] = {
1526 RTE_FLOW_ITEM_TYPE_ETH,
1527 RTE_FLOW_ITEM_TYPE_IPV4,
1528 RTE_FLOW_ITEM_TYPE_UDP,
1529 RTE_FLOW_ITEM_TYPE_VXLAN,
1530 RTE_FLOW_ITEM_TYPE_ETH,
1531 RTE_FLOW_ITEM_TYPE_VLAN,
1532 RTE_FLOW_ITEM_TYPE_END,
1535 static enum rte_flow_item_type pattern_vxlan_4[] = {
1536 RTE_FLOW_ITEM_TYPE_ETH,
1537 RTE_FLOW_ITEM_TYPE_IPV6,
1538 RTE_FLOW_ITEM_TYPE_UDP,
1539 RTE_FLOW_ITEM_TYPE_VXLAN,
1540 RTE_FLOW_ITEM_TYPE_ETH,
1541 RTE_FLOW_ITEM_TYPE_VLAN,
1542 RTE_FLOW_ITEM_TYPE_END,
1545 static enum rte_flow_item_type pattern_nvgre_1[] = {
1546 RTE_FLOW_ITEM_TYPE_ETH,
1547 RTE_FLOW_ITEM_TYPE_IPV4,
1548 RTE_FLOW_ITEM_TYPE_NVGRE,
1549 RTE_FLOW_ITEM_TYPE_ETH,
1550 RTE_FLOW_ITEM_TYPE_END,
1553 static enum rte_flow_item_type pattern_nvgre_2[] = {
1554 RTE_FLOW_ITEM_TYPE_ETH,
1555 RTE_FLOW_ITEM_TYPE_IPV6,
1556 RTE_FLOW_ITEM_TYPE_NVGRE,
1557 RTE_FLOW_ITEM_TYPE_ETH,
1558 RTE_FLOW_ITEM_TYPE_END,
1561 static enum rte_flow_item_type pattern_nvgre_3[] = {
1562 RTE_FLOW_ITEM_TYPE_ETH,
1563 RTE_FLOW_ITEM_TYPE_IPV4,
1564 RTE_FLOW_ITEM_TYPE_NVGRE,
1565 RTE_FLOW_ITEM_TYPE_ETH,
1566 RTE_FLOW_ITEM_TYPE_VLAN,
1567 RTE_FLOW_ITEM_TYPE_END,
1570 static enum rte_flow_item_type pattern_nvgre_4[] = {
1571 RTE_FLOW_ITEM_TYPE_ETH,
1572 RTE_FLOW_ITEM_TYPE_IPV6,
1573 RTE_FLOW_ITEM_TYPE_NVGRE,
1574 RTE_FLOW_ITEM_TYPE_ETH,
1575 RTE_FLOW_ITEM_TYPE_VLAN,
1576 RTE_FLOW_ITEM_TYPE_END,
1579 static enum rte_flow_item_type pattern_mpls_1[] = {
1580 RTE_FLOW_ITEM_TYPE_ETH,
1581 RTE_FLOW_ITEM_TYPE_IPV4,
1582 RTE_FLOW_ITEM_TYPE_UDP,
1583 RTE_FLOW_ITEM_TYPE_MPLS,
1584 RTE_FLOW_ITEM_TYPE_END,
1587 static enum rte_flow_item_type pattern_mpls_2[] = {
1588 RTE_FLOW_ITEM_TYPE_ETH,
1589 RTE_FLOW_ITEM_TYPE_IPV6,
1590 RTE_FLOW_ITEM_TYPE_UDP,
1591 RTE_FLOW_ITEM_TYPE_MPLS,
1592 RTE_FLOW_ITEM_TYPE_END,
1595 static enum rte_flow_item_type pattern_mpls_3[] = {
1596 RTE_FLOW_ITEM_TYPE_ETH,
1597 RTE_FLOW_ITEM_TYPE_IPV4,
1598 RTE_FLOW_ITEM_TYPE_GRE,
1599 RTE_FLOW_ITEM_TYPE_MPLS,
1600 RTE_FLOW_ITEM_TYPE_END,
1603 static enum rte_flow_item_type pattern_mpls_4[] = {
1604 RTE_FLOW_ITEM_TYPE_ETH,
1605 RTE_FLOW_ITEM_TYPE_IPV6,
1606 RTE_FLOW_ITEM_TYPE_GRE,
1607 RTE_FLOW_ITEM_TYPE_MPLS,
1608 RTE_FLOW_ITEM_TYPE_END,
1611 static enum rte_flow_item_type pattern_qinq_1[] = {
1612 RTE_FLOW_ITEM_TYPE_ETH,
1613 RTE_FLOW_ITEM_TYPE_VLAN,
1614 RTE_FLOW_ITEM_TYPE_VLAN,
1615 RTE_FLOW_ITEM_TYPE_END,
1618 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1620 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1621 /* FDIR - support default flow type without flexible payload*/
1622 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1623 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1624 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1625 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1626 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1627 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1628 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1629 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1630 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1631 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1632 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1633 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1634 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1635 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1636 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1637 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1638 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1639 /* FDIR - support default flow type with flexible payload */
1640 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1641 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1642 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1643 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1644 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1645 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1646 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1647 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1648 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1649 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1650 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1651 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1652 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1653 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1654 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1655 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1656 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1657 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1658 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1659 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1660 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1661 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1662 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1663 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1664 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1665 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1666 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1667 /* FDIR - support single vlan input set */
1668 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1669 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1703 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1704 /* FDIR - support VF item */
1705 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1729 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1730 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1731 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1732 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1751 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1752 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1768 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1769 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1775 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1777 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1778 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1779 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1780 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1782 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1783 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1784 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1785 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1786 /* MPLSoUDP & MPLSoGRE */
1787 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1788 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1789 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1790 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1792 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1793 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1794 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1795 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1797 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1800 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1802 act = actions + index; \
1803 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1805 act = actions + index; \
1809 /* Find the first VOID or non-VOID item pointer */
1810 static const struct rte_flow_item *
1811 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1815 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1817 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1819 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1827 /* Skip all VOID items of the pattern */
1829 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1830 const struct rte_flow_item *pattern)
1832 uint32_t cpy_count = 0;
1833 const struct rte_flow_item *pb = pattern, *pe = pattern;
1836 /* Find a non-void item first */
1837 pb = i40e_find_first_item(pb, false);
1838 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1843 /* Find a void item */
1844 pe = i40e_find_first_item(pb + 1, true);
1846 cpy_count = pe - pb;
1847 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1851 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1858 /* Copy the END item. */
1859 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1862 /* Check if the pattern matches a supported item type array */
1864 i40e_match_pattern(enum rte_flow_item_type *item_array,
1865 struct rte_flow_item *pattern)
1867 struct rte_flow_item *item = pattern;
1869 while ((*item_array == item->type) &&
1870 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1875 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1876 item->type == RTE_FLOW_ITEM_TYPE_END);
1879 /* Find if there's parse filter function matched */
1880 static parse_filter_t
1881 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1883 parse_filter_t parse_filter = NULL;
1886 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1887 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1889 parse_filter = i40e_supported_patterns[i].parse_filter;
1896 return parse_filter;
1899 /* Parse attributes */
1901 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1902 struct rte_flow_error *error)
1904 /* Must be input direction */
1905 if (!attr->ingress) {
1906 rte_flow_error_set(error, EINVAL,
1907 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1908 attr, "Only support ingress.");
1914 rte_flow_error_set(error, EINVAL,
1915 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1916 attr, "Not support egress.");
1921 if (attr->priority) {
1922 rte_flow_error_set(error, EINVAL,
1923 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1924 attr, "Not support priority.");
1930 rte_flow_error_set(error, EINVAL,
1931 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1932 attr, "Not support group.");
1940 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943 int qinq = dev->data->dev_conf.rxmode.offloads &
1944 DEV_RX_OFFLOAD_VLAN_EXTEND;
1954 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1957 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1962 /* 1. Last in item should be NULL as range is not supported.
1963 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1964 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1965 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1967 * 5. Ether_type mask should be 0xFFFF.
1970 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1971 const struct rte_flow_item *pattern,
1972 struct rte_flow_error *error,
1973 struct rte_eth_ethertype_filter *filter)
1975 const struct rte_flow_item *item = pattern;
1976 const struct rte_flow_item_eth *eth_spec;
1977 const struct rte_flow_item_eth *eth_mask;
1978 enum rte_flow_item_type item_type;
1979 uint16_t outer_tpid;
1981 outer_tpid = i40e_get_outer_vlan(dev);
1983 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1985 rte_flow_error_set(error, EINVAL,
1986 RTE_FLOW_ERROR_TYPE_ITEM,
1988 "Not support range");
1991 item_type = item->type;
1992 switch (item_type) {
1993 case RTE_FLOW_ITEM_TYPE_ETH:
1994 eth_spec = item->spec;
1995 eth_mask = item->mask;
1996 /* Get the MAC info. */
1997 if (!eth_spec || !eth_mask) {
1998 rte_flow_error_set(error, EINVAL,
1999 RTE_FLOW_ERROR_TYPE_ITEM,
2001 "NULL ETH spec/mask");
2005 /* Mask bits of source MAC address must be full of 0.
2006 * Mask bits of destination MAC address must be full
2007 * of 1 or full of 0.
2009 if (!rte_is_zero_ether_addr(ð_mask->src) ||
2010 (!rte_is_zero_ether_addr(ð_mask->dst) &&
2011 !rte_is_broadcast_ether_addr(ð_mask->dst))) {
2012 rte_flow_error_set(error, EINVAL,
2013 RTE_FLOW_ERROR_TYPE_ITEM,
2015 "Invalid MAC_addr mask");
2019 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2020 rte_flow_error_set(error, EINVAL,
2021 RTE_FLOW_ERROR_TYPE_ITEM,
2023 "Invalid ethertype mask");
2027 /* If mask bits of destination MAC address
2028 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2030 if (rte_is_broadcast_ether_addr(ð_mask->dst)) {
2031 filter->mac_addr = eth_spec->dst;
2032 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2034 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2036 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2038 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2039 filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2040 filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2041 filter->ether_type == outer_tpid) {
2042 rte_flow_error_set(error, EINVAL,
2043 RTE_FLOW_ERROR_TYPE_ITEM,
2045 "Unsupported ether_type in"
2046 " control packet filter.");
2058 /* Ethertype action only supports QUEUE or DROP. */
2060 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2061 const struct rte_flow_action *actions,
2062 struct rte_flow_error *error,
2063 struct rte_eth_ethertype_filter *filter)
2065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066 const struct rte_flow_action *act;
2067 const struct rte_flow_action_queue *act_q;
2070 /* Check if the first non-void action is QUEUE or DROP. */
2071 NEXT_ITEM_OF_ACTION(act, actions, index);
2072 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2073 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2074 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2075 act, "Not supported action.");
2079 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2081 filter->queue = act_q->index;
2082 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2083 rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION,
2085 act, "Invalid queue ID for"
2086 " ethertype_filter.");
2090 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2093 /* Check if the next non-void item is END */
2095 NEXT_ITEM_OF_ACTION(act, actions, index);
2096 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2097 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2098 act, "Not supported action.");
2106 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2107 const struct rte_flow_attr *attr,
2108 const struct rte_flow_item pattern[],
2109 const struct rte_flow_action actions[],
2110 struct rte_flow_error *error,
2111 union i40e_filter_t *filter)
2113 struct rte_eth_ethertype_filter *ethertype_filter =
2114 &filter->ethertype_filter;
2117 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2122 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2127 ret = i40e_flow_parse_attr(attr, error);
2131 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2137 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2138 const struct rte_flow_item_raw *raw_spec,
2139 struct rte_flow_error *error)
2141 if (!raw_spec->relative) {
2142 rte_flow_error_set(error, EINVAL,
2143 RTE_FLOW_ERROR_TYPE_ITEM,
2145 "Relative should be 1.");
2149 if (raw_spec->offset % sizeof(uint16_t)) {
2150 rte_flow_error_set(error, EINVAL,
2151 RTE_FLOW_ERROR_TYPE_ITEM,
2153 "Offset should be even.");
2157 if (raw_spec->search || raw_spec->limit) {
2158 rte_flow_error_set(error, EINVAL,
2159 RTE_FLOW_ERROR_TYPE_ITEM,
2161 "search or limit is not supported.");
2165 if (raw_spec->offset < 0) {
2166 rte_flow_error_set(error, EINVAL,
2167 RTE_FLOW_ERROR_TYPE_ITEM,
2169 "Offset should be non-negative.");
2176 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2177 struct i40e_fdir_flex_pit *flex_pit,
2178 enum i40e_flxpld_layer_idx layer_idx,
2183 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2184 /* Check if the configuration is conflicted */
2185 if (pf->fdir.flex_pit_flag[layer_idx] &&
2186 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2187 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2188 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2191 /* Check if the configuration exists. */
2192 if (pf->fdir.flex_pit_flag[layer_idx] &&
2193 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2194 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2195 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2198 pf->fdir.flex_set[field_idx].src_offset =
2199 flex_pit->src_offset;
2200 pf->fdir.flex_set[field_idx].size =
2202 pf->fdir.flex_set[field_idx].dst_offset =
2203 flex_pit->dst_offset;
2209 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2210 enum i40e_filter_pctype pctype,
2213 struct i40e_fdir_flex_mask flex_mask;
2215 uint8_t i, nb_bitmask = 0;
2217 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2218 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2219 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2221 flex_mask.word_mask |=
2222 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2223 if (mask_tmp != UINT16_MAX) {
2224 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2225 flex_mask.bitmask[nb_bitmask].offset =
2226 i / sizeof(uint16_t);
2228 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2233 flex_mask.nb_bitmask = nb_bitmask;
2235 if (pf->fdir.flex_mask_flag[pctype] &&
2236 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2237 sizeof(struct i40e_fdir_flex_mask))))
2239 else if (pf->fdir.flex_mask_flag[pctype] &&
2240 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2241 sizeof(struct i40e_fdir_flex_mask))))
2244 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2245 sizeof(struct i40e_fdir_flex_mask));
2250 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2251 enum i40e_flxpld_layer_idx layer_idx,
2254 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2255 uint32_t flx_pit, flx_ort;
2257 uint16_t min_next_off = 0; /* in words */
2261 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2262 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2263 (layer_idx * I40E_MAX_FLXPLD_FIED);
2264 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2268 for (i = 0; i < raw_id; i++) {
2269 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2270 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2271 pf->fdir.flex_set[field_idx].size,
2272 pf->fdir.flex_set[field_idx].dst_offset);
2274 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2275 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2276 pf->fdir.flex_set[field_idx].size;
2279 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2280 /* set the non-used register obeying register's constrain */
2281 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2282 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2283 NONUSE_FLX_PIT_DEST_OFF);
2284 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2288 pf->fdir.flex_pit_flag[layer_idx] = 1;
2292 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2293 enum i40e_filter_pctype pctype)
2295 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2296 struct i40e_fdir_flex_mask *flex_mask;
2297 uint32_t flxinset, fd_mask;
2301 flex_mask = &pf->fdir.flex_mask[pctype];
2302 flxinset = (flex_mask->word_mask <<
2303 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2304 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2305 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2307 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2308 fd_mask = (flex_mask->bitmask[i].mask <<
2309 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2310 I40E_PRTQF_FD_MSK_MASK_MASK;
2311 fd_mask |= ((flex_mask->bitmask[i].offset +
2312 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2313 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2314 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2315 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2318 pf->fdir.flex_mask_flag[pctype] = 1;
2322 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2323 enum i40e_filter_pctype pctype,
2326 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2327 uint64_t inset_reg = 0;
2328 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2331 /* Check if the input set is valid */
2332 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2334 PMD_DRV_LOG(ERR, "Invalid input set");
2338 /* Check if the configuration is conflicted */
2339 if (pf->fdir.inset_flag[pctype] &&
2340 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2343 if (pf->fdir.inset_flag[pctype] &&
2344 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2347 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2348 I40E_INSET_MASK_NUM_REG);
2352 if (pf->support_multi_driver) {
2353 for (i = 0; i < num; i++)
2354 if (i40e_read_rx_ctl(hw,
2355 I40E_GLQF_FD_MSK(i, pctype)) !=
2357 PMD_DRV_LOG(ERR, "Input set setting is not"
2359 " `support-multi-driver`"
2363 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2364 if (i40e_read_rx_ctl(hw,
2365 I40E_GLQF_FD_MSK(i, pctype)) != 0) {
2366 PMD_DRV_LOG(ERR, "Input set setting is not"
2368 " `support-multi-driver`"
2374 for (i = 0; i < num; i++)
2375 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2377 /*clear unused mask registers of the pctype */
2378 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2379 i40e_check_write_reg(hw,
2380 I40E_GLQF_FD_MSK(i, pctype), 0);
2383 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2385 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2386 (uint32_t)(inset_reg & UINT32_MAX));
2387 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2388 (uint32_t)((inset_reg >>
2389 I40E_32_BIT_WIDTH) & UINT32_MAX));
2391 I40E_WRITE_FLUSH(hw);
2393 pf->fdir.input_set[pctype] = input_set;
2394 pf->fdir.inset_flag[pctype] = 1;
2399 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2400 enum rte_flow_item_type item_type,
2401 struct i40e_fdir_filter_conf *filter)
2403 struct i40e_customized_pctype *cus_pctype = NULL;
2405 switch (item_type) {
2406 case RTE_FLOW_ITEM_TYPE_GTPC:
2407 cus_pctype = i40e_find_customized_pctype(pf,
2408 I40E_CUSTOMIZED_GTPC);
2410 case RTE_FLOW_ITEM_TYPE_GTPU:
2411 if (!filter->input.flow_ext.inner_ip)
2412 cus_pctype = i40e_find_customized_pctype(pf,
2413 I40E_CUSTOMIZED_GTPU);
2414 else if (filter->input.flow_ext.iip_type ==
2415 I40E_FDIR_IPTYPE_IPV4)
2416 cus_pctype = i40e_find_customized_pctype(pf,
2417 I40E_CUSTOMIZED_GTPU_IPV4);
2418 else if (filter->input.flow_ext.iip_type ==
2419 I40E_FDIR_IPTYPE_IPV6)
2420 cus_pctype = i40e_find_customized_pctype(pf,
2421 I40E_CUSTOMIZED_GTPU_IPV6);
2424 PMD_DRV_LOG(ERR, "Unsupported item type");
2428 if (cus_pctype && cus_pctype->valid)
2429 return cus_pctype->pctype;
2431 return I40E_FILTER_PCTYPE_INVALID;
2434 /* 1. Last in item should be NULL as range is not supported.
2435 * 2. Supported patterns: refer to array i40e_supported_patterns.
2436 * 3. Default supported flow type and input set: refer to array
2437 * valid_fdir_inset_table in i40e_ethdev.c.
2438 * 4. Mask of fields which need to be matched should be
2440 * 5. Mask of fields which needn't to be matched should be
2442 * 6. GTP profile supports GTPv1 only.
2443 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2446 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2447 const struct rte_flow_attr *attr,
2448 const struct rte_flow_item *pattern,
2449 struct rte_flow_error *error,
2450 struct i40e_fdir_filter_conf *filter)
2452 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2453 const struct rte_flow_item *item = pattern;
2454 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2455 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2456 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2457 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2458 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2459 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2460 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2461 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2462 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2463 const struct rte_flow_item_vf *vf_spec;
2466 uint64_t input_set = I40E_INSET_NONE;
2468 enum rte_flow_item_type item_type;
2469 enum rte_flow_item_type next_type;
2470 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2471 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2473 uint8_t ipv6_addr_mask[16] = {
2474 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2475 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2476 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2478 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2479 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2480 struct i40e_fdir_flex_pit flex_pit;
2481 uint8_t next_dst_off = 0;
2482 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2484 bool cfg_flex_pit = true;
2485 bool cfg_flex_msk = true;
2486 uint16_t outer_tpid;
2487 uint16_t ether_type;
2488 uint32_t vtc_flow_cpu;
2489 bool outer_ip = true;
2492 memset(off_arr, 0, sizeof(off_arr));
2493 memset(len_arr, 0, sizeof(len_arr));
2494 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2495 outer_tpid = i40e_get_outer_vlan(dev);
2496 filter->input.flow_ext.customized_pctype = false;
2497 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2499 rte_flow_error_set(error, EINVAL,
2500 RTE_FLOW_ERROR_TYPE_ITEM,
2502 "Not support range");
2505 item_type = item->type;
2506 switch (item_type) {
2507 case RTE_FLOW_ITEM_TYPE_ETH:
2508 eth_spec = item->spec;
2509 eth_mask = item->mask;
2510 next_type = (item + 1)->type;
2512 if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2513 (!eth_spec || !eth_mask)) {
2514 rte_flow_error_set(error, EINVAL,
2515 RTE_FLOW_ERROR_TYPE_ITEM,
2517 "NULL eth spec/mask.");
2521 if (eth_spec && eth_mask) {
2522 if (!rte_is_zero_ether_addr(ð_mask->src) ||
2523 !rte_is_zero_ether_addr(ð_mask->dst)) {
2524 rte_flow_error_set(error, EINVAL,
2525 RTE_FLOW_ERROR_TYPE_ITEM,
2527 "Invalid MAC_addr mask.");
2531 if (eth_spec && eth_mask && eth_mask->type) {
2532 if (eth_mask->type != RTE_BE16(0xffff)) {
2533 rte_flow_error_set(error, EINVAL,
2534 RTE_FLOW_ERROR_TYPE_ITEM,
2536 "Invalid type mask.");
2540 ether_type = rte_be_to_cpu_16(eth_spec->type);
2542 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2543 ether_type == RTE_ETHER_TYPE_IPV4 ||
2544 ether_type == RTE_ETHER_TYPE_IPV6 ||
2545 ether_type == RTE_ETHER_TYPE_ARP ||
2546 ether_type == outer_tpid) {
2547 rte_flow_error_set(error, EINVAL,
2548 RTE_FLOW_ERROR_TYPE_ITEM,
2550 "Unsupported ether_type.");
2553 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2554 filter->input.flow.l2_flow.ether_type =
2558 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2559 layer_idx = I40E_FLXPLD_L2_IDX;
2562 case RTE_FLOW_ITEM_TYPE_VLAN:
2563 vlan_spec = item->spec;
2564 vlan_mask = item->mask;
2566 RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2567 if (vlan_spec && vlan_mask) {
2568 if (vlan_mask->tci ==
2569 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2570 input_set |= I40E_INSET_VLAN_INNER;
2571 filter->input.flow_ext.vlan_tci =
2575 if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2576 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2577 rte_flow_error_set(error, EINVAL,
2578 RTE_FLOW_ERROR_TYPE_ITEM,
2580 "Invalid inner_type"
2586 rte_be_to_cpu_16(vlan_spec->inner_type);
2588 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2589 ether_type == RTE_ETHER_TYPE_IPV6 ||
2590 ether_type == RTE_ETHER_TYPE_ARP ||
2591 ether_type == outer_tpid) {
2592 rte_flow_error_set(error, EINVAL,
2593 RTE_FLOW_ERROR_TYPE_ITEM,
2595 "Unsupported inner_type.");
2598 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2599 filter->input.flow.l2_flow.ether_type =
2600 vlan_spec->inner_type;
2603 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2604 layer_idx = I40E_FLXPLD_L2_IDX;
2607 case RTE_FLOW_ITEM_TYPE_IPV4:
2608 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2609 ipv4_spec = item->spec;
2610 ipv4_mask = item->mask;
2611 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2612 layer_idx = I40E_FLXPLD_L3_IDX;
2614 if (ipv4_spec && ipv4_mask && outer_ip) {
2615 /* Check IPv4 mask and update input set */
2616 if (ipv4_mask->hdr.version_ihl ||
2617 ipv4_mask->hdr.total_length ||
2618 ipv4_mask->hdr.packet_id ||
2619 ipv4_mask->hdr.fragment_offset ||
2620 ipv4_mask->hdr.hdr_checksum) {
2621 rte_flow_error_set(error, EINVAL,
2622 RTE_FLOW_ERROR_TYPE_ITEM,
2624 "Invalid IPv4 mask.");
2628 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2629 input_set |= I40E_INSET_IPV4_SRC;
2630 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2631 input_set |= I40E_INSET_IPV4_DST;
2632 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2633 input_set |= I40E_INSET_IPV4_TOS;
2634 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2635 input_set |= I40E_INSET_IPV4_TTL;
2636 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2637 input_set |= I40E_INSET_IPV4_PROTO;
2639 /* Check if it is fragment. */
2640 frag_off = ipv4_spec->hdr.fragment_offset;
2641 frag_off = rte_be_to_cpu_16(frag_off);
2642 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2643 frag_off & RTE_IPV4_HDR_MF_FLAG)
2644 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2646 /* Get the filter info */
2647 filter->input.flow.ip4_flow.proto =
2648 ipv4_spec->hdr.next_proto_id;
2649 filter->input.flow.ip4_flow.tos =
2650 ipv4_spec->hdr.type_of_service;
2651 filter->input.flow.ip4_flow.ttl =
2652 ipv4_spec->hdr.time_to_live;
2653 filter->input.flow.ip4_flow.src_ip =
2654 ipv4_spec->hdr.src_addr;
2655 filter->input.flow.ip4_flow.dst_ip =
2656 ipv4_spec->hdr.dst_addr;
2657 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2658 filter->input.flow_ext.inner_ip = true;
2659 filter->input.flow_ext.iip_type =
2660 I40E_FDIR_IPTYPE_IPV4;
2661 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2662 rte_flow_error_set(error, EINVAL,
2663 RTE_FLOW_ERROR_TYPE_ITEM,
2665 "Invalid inner IPv4 mask.");
2673 case RTE_FLOW_ITEM_TYPE_IPV6:
2674 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2675 ipv6_spec = item->spec;
2676 ipv6_mask = item->mask;
2677 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2678 layer_idx = I40E_FLXPLD_L3_IDX;
2680 if (ipv6_spec && ipv6_mask && outer_ip) {
2681 /* Check IPv6 mask and update input set */
2682 if (ipv6_mask->hdr.payload_len) {
2683 rte_flow_error_set(error, EINVAL,
2684 RTE_FLOW_ERROR_TYPE_ITEM,
2686 "Invalid IPv6 mask");
2690 if (!memcmp(ipv6_mask->hdr.src_addr,
2692 RTE_DIM(ipv6_mask->hdr.src_addr)))
2693 input_set |= I40E_INSET_IPV6_SRC;
2694 if (!memcmp(ipv6_mask->hdr.dst_addr,
2696 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2697 input_set |= I40E_INSET_IPV6_DST;
2699 if ((ipv6_mask->hdr.vtc_flow &
2700 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2701 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2702 input_set |= I40E_INSET_IPV6_TC;
2703 if (ipv6_mask->hdr.proto == UINT8_MAX)
2704 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2705 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2706 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2708 /* Get filter info */
2710 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2711 filter->input.flow.ipv6_flow.tc =
2712 (uint8_t)(vtc_flow_cpu >>
2713 I40E_FDIR_IPv6_TC_OFFSET);
2714 filter->input.flow.ipv6_flow.proto =
2715 ipv6_spec->hdr.proto;
2716 filter->input.flow.ipv6_flow.hop_limits =
2717 ipv6_spec->hdr.hop_limits;
2719 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2720 ipv6_spec->hdr.src_addr, 16);
2721 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2722 ipv6_spec->hdr.dst_addr, 16);
2724 /* Check if it is fragment. */
2725 if (ipv6_spec->hdr.proto ==
2726 I40E_IPV6_FRAG_HEADER)
2727 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2728 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2729 filter->input.flow_ext.inner_ip = true;
2730 filter->input.flow_ext.iip_type =
2731 I40E_FDIR_IPTYPE_IPV6;
2732 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2733 rte_flow_error_set(error, EINVAL,
2734 RTE_FLOW_ERROR_TYPE_ITEM,
2736 "Invalid inner IPv6 mask");
2743 case RTE_FLOW_ITEM_TYPE_TCP:
2744 tcp_spec = item->spec;
2745 tcp_mask = item->mask;
2747 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2749 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2750 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2752 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2753 if (tcp_spec && tcp_mask) {
2754 /* Check TCP mask and update input set */
2755 if (tcp_mask->hdr.sent_seq ||
2756 tcp_mask->hdr.recv_ack ||
2757 tcp_mask->hdr.data_off ||
2758 tcp_mask->hdr.tcp_flags ||
2759 tcp_mask->hdr.rx_win ||
2760 tcp_mask->hdr.cksum ||
2761 tcp_mask->hdr.tcp_urp) {
2762 rte_flow_error_set(error, EINVAL,
2763 RTE_FLOW_ERROR_TYPE_ITEM,
2765 "Invalid TCP mask");
2769 if (tcp_mask->hdr.src_port == UINT16_MAX)
2770 input_set |= I40E_INSET_SRC_PORT;
2771 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2772 input_set |= I40E_INSET_DST_PORT;
2774 /* Get filter info */
2775 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2776 filter->input.flow.tcp4_flow.src_port =
2777 tcp_spec->hdr.src_port;
2778 filter->input.flow.tcp4_flow.dst_port =
2779 tcp_spec->hdr.dst_port;
2780 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2781 filter->input.flow.tcp6_flow.src_port =
2782 tcp_spec->hdr.src_port;
2783 filter->input.flow.tcp6_flow.dst_port =
2784 tcp_spec->hdr.dst_port;
2788 layer_idx = I40E_FLXPLD_L4_IDX;
2791 case RTE_FLOW_ITEM_TYPE_UDP:
2792 udp_spec = item->spec;
2793 udp_mask = item->mask;
2795 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2797 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2798 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2800 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2802 if (udp_spec && udp_mask) {
2803 /* Check UDP mask and update input set*/
2804 if (udp_mask->hdr.dgram_len ||
2805 udp_mask->hdr.dgram_cksum) {
2806 rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ITEM,
2809 "Invalid UDP mask");
2813 if (udp_mask->hdr.src_port == UINT16_MAX)
2814 input_set |= I40E_INSET_SRC_PORT;
2815 if (udp_mask->hdr.dst_port == UINT16_MAX)
2816 input_set |= I40E_INSET_DST_PORT;
2818 /* Get filter info */
2819 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2820 filter->input.flow.udp4_flow.src_port =
2821 udp_spec->hdr.src_port;
2822 filter->input.flow.udp4_flow.dst_port =
2823 udp_spec->hdr.dst_port;
2824 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2825 filter->input.flow.udp6_flow.src_port =
2826 udp_spec->hdr.src_port;
2827 filter->input.flow.udp6_flow.dst_port =
2828 udp_spec->hdr.dst_port;
2832 layer_idx = I40E_FLXPLD_L4_IDX;
2835 case RTE_FLOW_ITEM_TYPE_GTPC:
2836 case RTE_FLOW_ITEM_TYPE_GTPU:
2837 if (!pf->gtp_support) {
2838 rte_flow_error_set(error, EINVAL,
2839 RTE_FLOW_ERROR_TYPE_ITEM,
2841 "Unsupported protocol");
2845 gtp_spec = item->spec;
2846 gtp_mask = item->mask;
2848 if (gtp_spec && gtp_mask) {
2849 if (gtp_mask->v_pt_rsv_flags ||
2850 gtp_mask->msg_type ||
2851 gtp_mask->msg_len ||
2852 gtp_mask->teid != UINT32_MAX) {
2853 rte_flow_error_set(error, EINVAL,
2854 RTE_FLOW_ERROR_TYPE_ITEM,
2856 "Invalid GTP mask");
2860 filter->input.flow.gtp_flow.teid =
2862 filter->input.flow_ext.customized_pctype = true;
2863 cus_proto = item_type;
2866 case RTE_FLOW_ITEM_TYPE_SCTP:
2867 sctp_spec = item->spec;
2868 sctp_mask = item->mask;
2870 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2872 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2873 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2875 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2877 if (sctp_spec && sctp_mask) {
2878 /* Check SCTP mask and update input set */
2879 if (sctp_mask->hdr.cksum) {
2880 rte_flow_error_set(error, EINVAL,
2881 RTE_FLOW_ERROR_TYPE_ITEM,
2883 "Invalid UDP mask");
2887 if (sctp_mask->hdr.src_port == UINT16_MAX)
2888 input_set |= I40E_INSET_SRC_PORT;
2889 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2890 input_set |= I40E_INSET_DST_PORT;
2891 if (sctp_mask->hdr.tag == UINT32_MAX)
2892 input_set |= I40E_INSET_SCTP_VT;
2894 /* Get filter info */
2895 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2896 filter->input.flow.sctp4_flow.src_port =
2897 sctp_spec->hdr.src_port;
2898 filter->input.flow.sctp4_flow.dst_port =
2899 sctp_spec->hdr.dst_port;
2900 filter->input.flow.sctp4_flow.verify_tag
2901 = sctp_spec->hdr.tag;
2902 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2903 filter->input.flow.sctp6_flow.src_port =
2904 sctp_spec->hdr.src_port;
2905 filter->input.flow.sctp6_flow.dst_port =
2906 sctp_spec->hdr.dst_port;
2907 filter->input.flow.sctp6_flow.verify_tag
2908 = sctp_spec->hdr.tag;
2912 layer_idx = I40E_FLXPLD_L4_IDX;
2915 case RTE_FLOW_ITEM_TYPE_RAW:
2916 raw_spec = item->spec;
2917 raw_mask = item->mask;
2919 if (!raw_spec || !raw_mask) {
2920 rte_flow_error_set(error, EINVAL,
2921 RTE_FLOW_ERROR_TYPE_ITEM,
2923 "NULL RAW spec/mask");
2927 if (pf->support_multi_driver) {
2928 rte_flow_error_set(error, ENOTSUP,
2929 RTE_FLOW_ERROR_TYPE_ITEM,
2931 "Unsupported flexible payload.");
2935 ret = i40e_flow_check_raw_item(item, raw_spec, error);
2939 off_arr[raw_id] = raw_spec->offset;
2940 len_arr[raw_id] = raw_spec->length;
2943 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2945 raw_spec->length / sizeof(uint16_t);
2946 flex_pit.dst_offset =
2947 next_dst_off / sizeof(uint16_t);
2949 for (i = 0; i <= raw_id; i++) {
2951 flex_pit.src_offset +=
2955 flex_pit.src_offset +=
2956 (off_arr[i] + len_arr[i]) /
2958 flex_size += len_arr[i];
2960 if (((flex_pit.src_offset + flex_pit.size) >=
2961 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2962 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2963 rte_flow_error_set(error, EINVAL,
2964 RTE_FLOW_ERROR_TYPE_ITEM,
2966 "Exceeds maxmial payload limit.");
2970 /* Store flex pit to SW */
2971 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2974 rte_flow_error_set(error, EINVAL,
2975 RTE_FLOW_ERROR_TYPE_ITEM,
2977 "Conflict with the first flexible rule.");
2980 cfg_flex_pit = false;
2982 for (i = 0; i < raw_spec->length; i++) {
2983 j = i + next_dst_off;
2984 filter->input.flow_ext.flexbytes[j] =
2985 raw_spec->pattern[i];
2986 flex_mask[j] = raw_mask->pattern[i];
2989 next_dst_off += raw_spec->length;
2992 case RTE_FLOW_ITEM_TYPE_VF:
2993 vf_spec = item->spec;
2994 if (!attr->transfer) {
2995 rte_flow_error_set(error, ENOTSUP,
2996 RTE_FLOW_ERROR_TYPE_ITEM,
2998 "Matching VF traffic"
2999 " without affecting it"
3000 " (transfer attribute)"
3004 filter->input.flow_ext.is_vf = 1;
3005 filter->input.flow_ext.dst_id = vf_spec->id;
3006 if (filter->input.flow_ext.is_vf &&
3007 filter->input.flow_ext.dst_id >= pf->vf_num) {
3008 rte_flow_error_set(error, EINVAL,
3009 RTE_FLOW_ERROR_TYPE_ITEM,
3011 "Invalid VF ID for FDIR.");
3020 /* Get customized pctype value */
3021 if (filter->input.flow_ext.customized_pctype) {
3022 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
3023 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3024 rte_flow_error_set(error, EINVAL,
3025 RTE_FLOW_ERROR_TYPE_ITEM,
3027 "Unsupported pctype");
3032 /* If customized pctype is not used, set fdir configuration.*/
3033 if (!filter->input.flow_ext.customized_pctype) {
3034 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3036 rte_flow_error_set(error, EINVAL,
3037 RTE_FLOW_ERROR_TYPE_ITEM, item,
3038 "Conflict with the first rule's input set.");
3040 } else if (ret == -EINVAL) {
3041 rte_flow_error_set(error, EINVAL,
3042 RTE_FLOW_ERROR_TYPE_ITEM, item,
3043 "Invalid pattern mask.");
3047 /* Store flex mask to SW */
3048 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3050 rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ITEM,
3053 "Exceed maximal number of bitmasks");
3055 } else if (ret == -2) {
3056 rte_flow_error_set(error, EINVAL,
3057 RTE_FLOW_ERROR_TYPE_ITEM,
3059 "Conflict with the first flexible rule");
3062 cfg_flex_msk = false;
3065 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3068 i40e_flow_set_fdir_flex_msk(pf, pctype);
3071 filter->input.pctype = pctype;
3076 /* Parse to get the action info of a FDIR filter.
3077 * FDIR action supports QUEUE or (QUEUE + MARK).
3080 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3081 const struct rte_flow_action *actions,
3082 struct rte_flow_error *error,
3083 struct i40e_fdir_filter_conf *filter)
3085 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3086 const struct rte_flow_action *act;
3087 const struct rte_flow_action_queue *act_q;
3088 const struct rte_flow_action_mark *mark_spec = NULL;
3091 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3092 NEXT_ITEM_OF_ACTION(act, actions, index);
3093 switch (act->type) {
3094 case RTE_FLOW_ACTION_TYPE_QUEUE:
3096 filter->action.rx_queue = act_q->index;
3097 if ((!filter->input.flow_ext.is_vf &&
3098 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3099 (filter->input.flow_ext.is_vf &&
3100 filter->action.rx_queue >= pf->vf_nb_qps)) {
3101 rte_flow_error_set(error, EINVAL,
3102 RTE_FLOW_ERROR_TYPE_ACTION, act,
3103 "Invalid queue ID for FDIR.");
3106 filter->action.behavior = I40E_FDIR_ACCEPT;
3108 case RTE_FLOW_ACTION_TYPE_DROP:
3109 filter->action.behavior = I40E_FDIR_REJECT;
3111 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3112 filter->action.behavior = I40E_FDIR_PASSTHRU;
3114 case RTE_FLOW_ACTION_TYPE_MARK:
3115 filter->action.behavior = I40E_FDIR_PASSTHRU;
3116 mark_spec = act->conf;
3117 filter->action.report_status = I40E_FDIR_REPORT_ID;
3118 filter->soft_id = mark_spec->id;
3121 rte_flow_error_set(error, EINVAL,
3122 RTE_FLOW_ERROR_TYPE_ACTION, act,
3127 /* Check if the next non-void item is MARK or FLAG or END. */
3129 NEXT_ITEM_OF_ACTION(act, actions, index);
3130 switch (act->type) {
3131 case RTE_FLOW_ACTION_TYPE_MARK:
3133 /* Double MARK actions requested */
3134 rte_flow_error_set(error, EINVAL,
3135 RTE_FLOW_ERROR_TYPE_ACTION, act,
3139 mark_spec = act->conf;
3140 filter->action.report_status = I40E_FDIR_REPORT_ID;
3141 filter->soft_id = mark_spec->id;
3143 case RTE_FLOW_ACTION_TYPE_FLAG:
3145 /* MARK + FLAG not supported */
3146 rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION, act,
3151 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3153 case RTE_FLOW_ACTION_TYPE_RSS:
3154 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3155 /* RSS filter won't be next if FDIR did not pass thru */
3156 rte_flow_error_set(error, EINVAL,
3157 RTE_FLOW_ERROR_TYPE_ACTION, act,
3162 case RTE_FLOW_ACTION_TYPE_END:
3165 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3166 act, "Invalid action.");
3170 /* Check if the next non-void item is END */
3172 NEXT_ITEM_OF_ACTION(act, actions, index);
3173 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3174 rte_flow_error_set(error, EINVAL,
3175 RTE_FLOW_ERROR_TYPE_ACTION,
3176 act, "Invalid action.");
3184 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3185 const struct rte_flow_attr *attr,
3186 const struct rte_flow_item pattern[],
3187 const struct rte_flow_action actions[],
3188 struct rte_flow_error *error,
3189 union i40e_filter_t *filter)
3191 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3192 struct i40e_fdir_filter_conf *fdir_filter =
3193 &filter->fdir_filter;
3196 ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3201 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3205 ret = i40e_flow_parse_attr(attr, error);
3209 cons_filter_type = RTE_ETH_FILTER_FDIR;
3211 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT ||
3212 pf->fdir.fdir_vsi == NULL) {
3213 /* Enable fdir when fdir flow is added at first time. */
3214 ret = i40e_fdir_setup(pf);
3215 if (ret != I40E_SUCCESS) {
3216 rte_flow_error_set(error, ENOTSUP,
3217 RTE_FLOW_ERROR_TYPE_HANDLE,
3218 NULL, "Failed to setup fdir.");
3221 ret = i40e_fdir_configure(dev);
3223 rte_flow_error_set(error, ENOTSUP,
3224 RTE_FLOW_ERROR_TYPE_HANDLE,
3225 NULL, "Failed to configure fdir.");
3229 dev->data->dev_conf.fdir_conf.mode = RTE_FDIR_MODE_PERFECT;
3234 i40e_fdir_teardown(pf);
3238 /* Parse to get the action info of a tunnel filter
3239 * Tunnel action only supports PF, VF and QUEUE.
3242 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3243 const struct rte_flow_action *actions,
3244 struct rte_flow_error *error,
3245 struct i40e_tunnel_filter_conf *filter)
3247 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3248 const struct rte_flow_action *act;
3249 const struct rte_flow_action_queue *act_q;
3250 const struct rte_flow_action_vf *act_vf;
3253 /* Check if the first non-void action is PF or VF. */
3254 NEXT_ITEM_OF_ACTION(act, actions, index);
3255 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3256 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3257 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3258 act, "Not supported action.");
3262 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3264 filter->vf_id = act_vf->id;
3265 filter->is_to_vf = 1;
3266 if (filter->vf_id >= pf->vf_num) {
3267 rte_flow_error_set(error, EINVAL,
3268 RTE_FLOW_ERROR_TYPE_ACTION,
3269 act, "Invalid VF ID for tunnel filter");
3274 /* Check if the next non-void item is QUEUE */
3276 NEXT_ITEM_OF_ACTION(act, actions, index);
3277 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3279 filter->queue_id = act_q->index;
3280 if ((!filter->is_to_vf) &&
3281 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3282 rte_flow_error_set(error, EINVAL,
3283 RTE_FLOW_ERROR_TYPE_ACTION,
3284 act, "Invalid queue ID for tunnel filter");
3286 } else if (filter->is_to_vf &&
3287 (filter->queue_id >= pf->vf_nb_qps)) {
3288 rte_flow_error_set(error, EINVAL,
3289 RTE_FLOW_ERROR_TYPE_ACTION,
3290 act, "Invalid queue ID for tunnel filter");
3295 /* Check if the next non-void item is END */
3297 NEXT_ITEM_OF_ACTION(act, actions, index);
3298 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3299 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3300 act, "Not supported action.");
3307 static uint16_t i40e_supported_tunnel_filter_types[] = {
3308 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3309 ETH_TUNNEL_FILTER_IVLAN,
3310 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3311 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3312 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3313 ETH_TUNNEL_FILTER_IMAC,
3314 ETH_TUNNEL_FILTER_IMAC,
3318 i40e_check_tunnel_filter_type(uint8_t filter_type)
3322 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3323 if (filter_type == i40e_supported_tunnel_filter_types[i])
3330 /* 1. Last in item should be NULL as range is not supported.
3331 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3332 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3333 * 3. Mask of fields which need to be matched should be
3335 * 4. Mask of fields which needn't to be matched should be
3339 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3340 const struct rte_flow_item *pattern,
3341 struct rte_flow_error *error,
3342 struct i40e_tunnel_filter_conf *filter)
3344 const struct rte_flow_item *item = pattern;
3345 const struct rte_flow_item_eth *eth_spec;
3346 const struct rte_flow_item_eth *eth_mask;
3347 const struct rte_flow_item_vxlan *vxlan_spec;
3348 const struct rte_flow_item_vxlan *vxlan_mask;
3349 const struct rte_flow_item_vlan *vlan_spec;
3350 const struct rte_flow_item_vlan *vlan_mask;
3351 uint8_t filter_type = 0;
3352 bool is_vni_masked = 0;
3353 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3354 enum rte_flow_item_type item_type;
3355 bool vxlan_flag = 0;
3356 uint32_t tenant_id_be = 0;
3359 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3361 rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ITEM,
3364 "Not support range");
3367 item_type = item->type;
3368 switch (item_type) {
3369 case RTE_FLOW_ITEM_TYPE_ETH:
3370 eth_spec = item->spec;
3371 eth_mask = item->mask;
3373 /* Check if ETH item is used for place holder.
3374 * If yes, both spec and mask should be NULL.
3375 * If no, both spec and mask shouldn't be NULL.
3377 if ((!eth_spec && eth_mask) ||
3378 (eth_spec && !eth_mask)) {
3379 rte_flow_error_set(error, EINVAL,
3380 RTE_FLOW_ERROR_TYPE_ITEM,
3382 "Invalid ether spec/mask");
3386 if (eth_spec && eth_mask) {
3387 /* DST address of inner MAC shouldn't be masked.
3388 * SRC address of Inner MAC should be masked.
3390 if (!rte_is_broadcast_ether_addr(ð_mask->dst) ||
3391 !rte_is_zero_ether_addr(ð_mask->src) ||
3393 rte_flow_error_set(error, EINVAL,
3394 RTE_FLOW_ERROR_TYPE_ITEM,
3396 "Invalid ether spec/mask");
3401 rte_memcpy(&filter->outer_mac,
3403 RTE_ETHER_ADDR_LEN);
3404 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3406 rte_memcpy(&filter->inner_mac,
3408 RTE_ETHER_ADDR_LEN);
3409 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3413 case RTE_FLOW_ITEM_TYPE_VLAN:
3414 vlan_spec = item->spec;
3415 vlan_mask = item->mask;
3416 if (!(vlan_spec && vlan_mask) ||
3417 vlan_mask->inner_type) {
3418 rte_flow_error_set(error, EINVAL,
3419 RTE_FLOW_ERROR_TYPE_ITEM,
3421 "Invalid vlan item");
3425 if (vlan_spec && vlan_mask) {
3426 if (vlan_mask->tci ==
3427 rte_cpu_to_be_16(I40E_TCI_MASK))
3428 filter->inner_vlan =
3429 rte_be_to_cpu_16(vlan_spec->tci) &
3431 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3434 case RTE_FLOW_ITEM_TYPE_IPV4:
3435 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3436 /* IPv4 is used to describe protocol,
3437 * spec and mask should be NULL.
3439 if (item->spec || item->mask) {
3440 rte_flow_error_set(error, EINVAL,
3441 RTE_FLOW_ERROR_TYPE_ITEM,
3443 "Invalid IPv4 item");
3447 case RTE_FLOW_ITEM_TYPE_IPV6:
3448 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3449 /* IPv6 is used to describe protocol,
3450 * spec and mask should be NULL.
3452 if (item->spec || item->mask) {
3453 rte_flow_error_set(error, EINVAL,
3454 RTE_FLOW_ERROR_TYPE_ITEM,
3456 "Invalid IPv6 item");
3460 case RTE_FLOW_ITEM_TYPE_UDP:
3461 /* UDP is used to describe protocol,
3462 * spec and mask should be NULL.
3464 if (item->spec || item->mask) {
3465 rte_flow_error_set(error, EINVAL,
3466 RTE_FLOW_ERROR_TYPE_ITEM,
3468 "Invalid UDP item");
3472 case RTE_FLOW_ITEM_TYPE_VXLAN:
3473 vxlan_spec = item->spec;
3474 vxlan_mask = item->mask;
3475 /* Check if VXLAN item is used to describe protocol.
3476 * If yes, both spec and mask should be NULL.
3477 * If no, both spec and mask shouldn't be NULL.
3479 if ((!vxlan_spec && vxlan_mask) ||
3480 (vxlan_spec && !vxlan_mask)) {
3481 rte_flow_error_set(error, EINVAL,
3482 RTE_FLOW_ERROR_TYPE_ITEM,
3484 "Invalid VXLAN item");
3488 /* Check if VNI is masked. */
3489 if (vxlan_spec && vxlan_mask) {
3491 !!memcmp(vxlan_mask->vni, vni_mask,
3493 if (is_vni_masked) {
3494 rte_flow_error_set(error, EINVAL,
3495 RTE_FLOW_ERROR_TYPE_ITEM,
3497 "Invalid VNI mask");
3501 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3502 vxlan_spec->vni, 3);
3504 rte_be_to_cpu_32(tenant_id_be);
3505 filter_type |= ETH_TUNNEL_FILTER_TENID;
3515 ret = i40e_check_tunnel_filter_type(filter_type);
3517 rte_flow_error_set(error, EINVAL,
3518 RTE_FLOW_ERROR_TYPE_ITEM,
3520 "Invalid filter type");
3523 filter->filter_type = filter_type;
3525 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3531 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3532 const struct rte_flow_attr *attr,
3533 const struct rte_flow_item pattern[],
3534 const struct rte_flow_action actions[],
3535 struct rte_flow_error *error,
3536 union i40e_filter_t *filter)
3538 struct i40e_tunnel_filter_conf *tunnel_filter =
3539 &filter->consistent_tunnel_filter;
3542 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3543 error, tunnel_filter);
3547 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3551 ret = i40e_flow_parse_attr(attr, error);
3555 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3560 /* 1. Last in item should be NULL as range is not supported.
3561 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3562 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3563 * 3. Mask of fields which need to be matched should be
3565 * 4. Mask of fields which needn't to be matched should be
3569 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3570 const struct rte_flow_item *pattern,
3571 struct rte_flow_error *error,
3572 struct i40e_tunnel_filter_conf *filter)
3574 const struct rte_flow_item *item = pattern;
3575 const struct rte_flow_item_eth *eth_spec;
3576 const struct rte_flow_item_eth *eth_mask;
3577 const struct rte_flow_item_nvgre *nvgre_spec;
3578 const struct rte_flow_item_nvgre *nvgre_mask;
3579 const struct rte_flow_item_vlan *vlan_spec;
3580 const struct rte_flow_item_vlan *vlan_mask;
3581 enum rte_flow_item_type item_type;
3582 uint8_t filter_type = 0;
3583 bool is_tni_masked = 0;
3584 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3585 bool nvgre_flag = 0;
3586 uint32_t tenant_id_be = 0;
3589 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3591 rte_flow_error_set(error, EINVAL,
3592 RTE_FLOW_ERROR_TYPE_ITEM,
3594 "Not support range");
3597 item_type = item->type;
3598 switch (item_type) {
3599 case RTE_FLOW_ITEM_TYPE_ETH:
3600 eth_spec = item->spec;
3601 eth_mask = item->mask;
3603 /* Check if ETH item is used for place holder.
3604 * If yes, both spec and mask should be NULL.
3605 * If no, both spec and mask shouldn't be NULL.
3607 if ((!eth_spec && eth_mask) ||
3608 (eth_spec && !eth_mask)) {
3609 rte_flow_error_set(error, EINVAL,
3610 RTE_FLOW_ERROR_TYPE_ITEM,
3612 "Invalid ether spec/mask");
3616 if (eth_spec && eth_mask) {
3617 /* DST address of inner MAC shouldn't be masked.
3618 * SRC address of Inner MAC should be masked.
3620 if (!rte_is_broadcast_ether_addr(ð_mask->dst) ||
3621 !rte_is_zero_ether_addr(ð_mask->src) ||
3623 rte_flow_error_set(error, EINVAL,
3624 RTE_FLOW_ERROR_TYPE_ITEM,
3626 "Invalid ether spec/mask");
3631 rte_memcpy(&filter->outer_mac,
3633 RTE_ETHER_ADDR_LEN);
3634 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3636 rte_memcpy(&filter->inner_mac,
3638 RTE_ETHER_ADDR_LEN);
3639 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3644 case RTE_FLOW_ITEM_TYPE_VLAN:
3645 vlan_spec = item->spec;
3646 vlan_mask = item->mask;
3647 if (!(vlan_spec && vlan_mask) ||
3648 vlan_mask->inner_type) {
3649 rte_flow_error_set(error, EINVAL,
3650 RTE_FLOW_ERROR_TYPE_ITEM,
3652 "Invalid vlan item");
3656 if (vlan_spec && vlan_mask) {
3657 if (vlan_mask->tci ==
3658 rte_cpu_to_be_16(I40E_TCI_MASK))
3659 filter->inner_vlan =
3660 rte_be_to_cpu_16(vlan_spec->tci) &
3662 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3665 case RTE_FLOW_ITEM_TYPE_IPV4:
3666 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3667 /* IPv4 is used to describe protocol,
3668 * spec and mask should be NULL.
3670 if (item->spec || item->mask) {
3671 rte_flow_error_set(error, EINVAL,
3672 RTE_FLOW_ERROR_TYPE_ITEM,
3674 "Invalid IPv4 item");
3678 case RTE_FLOW_ITEM_TYPE_IPV6:
3679 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3680 /* IPv6 is used to describe protocol,
3681 * spec and mask should be NULL.
3683 if (item->spec || item->mask) {
3684 rte_flow_error_set(error, EINVAL,
3685 RTE_FLOW_ERROR_TYPE_ITEM,
3687 "Invalid IPv6 item");
3691 case RTE_FLOW_ITEM_TYPE_NVGRE:
3692 nvgre_spec = item->spec;
3693 nvgre_mask = item->mask;
3694 /* Check if NVGRE item is used to describe protocol.
3695 * If yes, both spec and mask should be NULL.
3696 * If no, both spec and mask shouldn't be NULL.
3698 if ((!nvgre_spec && nvgre_mask) ||
3699 (nvgre_spec && !nvgre_mask)) {
3700 rte_flow_error_set(error, EINVAL,
3701 RTE_FLOW_ERROR_TYPE_ITEM,
3703 "Invalid NVGRE item");
3707 if (nvgre_spec && nvgre_mask) {
3709 !!memcmp(nvgre_mask->tni, tni_mask,
3711 if (is_tni_masked) {
3712 rte_flow_error_set(error, EINVAL,
3713 RTE_FLOW_ERROR_TYPE_ITEM,
3715 "Invalid TNI mask");
3718 if (nvgre_mask->protocol &&
3719 nvgre_mask->protocol != 0xFFFF) {
3720 rte_flow_error_set(error, EINVAL,
3721 RTE_FLOW_ERROR_TYPE_ITEM,
3723 "Invalid NVGRE item");
3726 if (nvgre_mask->c_k_s_rsvd0_ver &&
3727 nvgre_mask->c_k_s_rsvd0_ver !=
3728 rte_cpu_to_be_16(0xFFFF)) {
3729 rte_flow_error_set(error, EINVAL,
3730 RTE_FLOW_ERROR_TYPE_ITEM,
3732 "Invalid NVGRE item");
3735 if (nvgre_spec->c_k_s_rsvd0_ver !=
3736 rte_cpu_to_be_16(0x2000) &&
3737 nvgre_mask->c_k_s_rsvd0_ver) {
3738 rte_flow_error_set(error, EINVAL,
3739 RTE_FLOW_ERROR_TYPE_ITEM,
3741 "Invalid NVGRE item");
3744 if (nvgre_mask->protocol &&
3745 nvgre_spec->protocol !=
3746 rte_cpu_to_be_16(0x6558)) {
3747 rte_flow_error_set(error, EINVAL,
3748 RTE_FLOW_ERROR_TYPE_ITEM,
3750 "Invalid NVGRE item");
3753 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3754 nvgre_spec->tni, 3);
3756 rte_be_to_cpu_32(tenant_id_be);
3757 filter_type |= ETH_TUNNEL_FILTER_TENID;
3767 ret = i40e_check_tunnel_filter_type(filter_type);
3769 rte_flow_error_set(error, EINVAL,
3770 RTE_FLOW_ERROR_TYPE_ITEM,
3772 "Invalid filter type");
3775 filter->filter_type = filter_type;
3777 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3783 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3784 const struct rte_flow_attr *attr,
3785 const struct rte_flow_item pattern[],
3786 const struct rte_flow_action actions[],
3787 struct rte_flow_error *error,
3788 union i40e_filter_t *filter)
3790 struct i40e_tunnel_filter_conf *tunnel_filter =
3791 &filter->consistent_tunnel_filter;
3794 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3795 error, tunnel_filter);
3799 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3803 ret = i40e_flow_parse_attr(attr, error);
3807 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3812 /* 1. Last in item should be NULL as range is not supported.
3813 * 2. Supported filter types: MPLS label.
3814 * 3. Mask of fields which need to be matched should be
3816 * 4. Mask of fields which needn't to be matched should be
3820 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3821 const struct rte_flow_item *pattern,
3822 struct rte_flow_error *error,
3823 struct i40e_tunnel_filter_conf *filter)
3825 const struct rte_flow_item *item = pattern;
3826 const struct rte_flow_item_mpls *mpls_spec;
3827 const struct rte_flow_item_mpls *mpls_mask;
3828 enum rte_flow_item_type item_type;
3829 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3830 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3831 uint32_t label_be = 0;
3833 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3835 rte_flow_error_set(error, EINVAL,
3836 RTE_FLOW_ERROR_TYPE_ITEM,
3838 "Not support range");
3841 item_type = item->type;
3842 switch (item_type) {
3843 case RTE_FLOW_ITEM_TYPE_ETH:
3844 if (item->spec || item->mask) {
3845 rte_flow_error_set(error, EINVAL,
3846 RTE_FLOW_ERROR_TYPE_ITEM,
3848 "Invalid ETH item");
3852 case RTE_FLOW_ITEM_TYPE_IPV4:
3853 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3854 /* IPv4 is used to describe protocol,
3855 * spec and mask should be NULL.
3857 if (item->spec || item->mask) {
3858 rte_flow_error_set(error, EINVAL,
3859 RTE_FLOW_ERROR_TYPE_ITEM,
3861 "Invalid IPv4 item");
3865 case RTE_FLOW_ITEM_TYPE_IPV6:
3866 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3867 /* IPv6 is used to describe protocol,
3868 * spec and mask should be NULL.
3870 if (item->spec || item->mask) {
3871 rte_flow_error_set(error, EINVAL,
3872 RTE_FLOW_ERROR_TYPE_ITEM,
3874 "Invalid IPv6 item");
3878 case RTE_FLOW_ITEM_TYPE_UDP:
3879 /* UDP is used to describe protocol,
3880 * spec and mask should be NULL.
3882 if (item->spec || item->mask) {
3883 rte_flow_error_set(error, EINVAL,
3884 RTE_FLOW_ERROR_TYPE_ITEM,
3886 "Invalid UDP item");
3891 case RTE_FLOW_ITEM_TYPE_GRE:
3892 /* GRE is used to describe protocol,
3893 * spec and mask should be NULL.
3895 if (item->spec || item->mask) {
3896 rte_flow_error_set(error, EINVAL,
3897 RTE_FLOW_ERROR_TYPE_ITEM,
3899 "Invalid GRE item");
3903 case RTE_FLOW_ITEM_TYPE_MPLS:
3904 mpls_spec = item->spec;
3905 mpls_mask = item->mask;
3907 if (!mpls_spec || !mpls_mask) {
3908 rte_flow_error_set(error, EINVAL,
3909 RTE_FLOW_ERROR_TYPE_ITEM,
3911 "Invalid MPLS item");
3915 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3916 rte_flow_error_set(error, EINVAL,
3917 RTE_FLOW_ERROR_TYPE_ITEM,
3919 "Invalid MPLS label mask");
3922 rte_memcpy(((uint8_t *)&label_be + 1),
3923 mpls_spec->label_tc_s, 3);
3924 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3932 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3934 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3940 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3941 const struct rte_flow_attr *attr,
3942 const struct rte_flow_item pattern[],
3943 const struct rte_flow_action actions[],
3944 struct rte_flow_error *error,
3945 union i40e_filter_t *filter)
3947 struct i40e_tunnel_filter_conf *tunnel_filter =
3948 &filter->consistent_tunnel_filter;
3951 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3952 error, tunnel_filter);
3956 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3960 ret = i40e_flow_parse_attr(attr, error);
3964 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3969 /* 1. Last in item should be NULL as range is not supported.
3970 * 2. Supported filter types: GTP TEID.
3971 * 3. Mask of fields which need to be matched should be
3973 * 4. Mask of fields which needn't to be matched should be
3975 * 5. GTP profile supports GTPv1 only.
3976 * 6. GTP-C response message ('source_port' = 2123) is not supported.
3979 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3980 const struct rte_flow_item *pattern,
3981 struct rte_flow_error *error,
3982 struct i40e_tunnel_filter_conf *filter)
3984 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3985 const struct rte_flow_item *item = pattern;
3986 const struct rte_flow_item_gtp *gtp_spec;
3987 const struct rte_flow_item_gtp *gtp_mask;
3988 enum rte_flow_item_type item_type;
3990 if (!pf->gtp_support) {
3991 rte_flow_error_set(error, EINVAL,
3992 RTE_FLOW_ERROR_TYPE_ITEM,
3994 "GTP is not supported by default.");
3998 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4000 rte_flow_error_set(error, EINVAL,
4001 RTE_FLOW_ERROR_TYPE_ITEM,
4003 "Not support range");
4006 item_type = item->type;
4007 switch (item_type) {
4008 case RTE_FLOW_ITEM_TYPE_ETH:
4009 if (item->spec || item->mask) {
4010 rte_flow_error_set(error, EINVAL,
4011 RTE_FLOW_ERROR_TYPE_ITEM,
4013 "Invalid ETH item");
4017 case RTE_FLOW_ITEM_TYPE_IPV4:
4018 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4019 /* IPv4 is used to describe protocol,
4020 * spec and mask should be NULL.
4022 if (item->spec || item->mask) {
4023 rte_flow_error_set(error, EINVAL,
4024 RTE_FLOW_ERROR_TYPE_ITEM,
4026 "Invalid IPv4 item");
4030 case RTE_FLOW_ITEM_TYPE_UDP:
4031 if (item->spec || item->mask) {
4032 rte_flow_error_set(error, EINVAL,
4033 RTE_FLOW_ERROR_TYPE_ITEM,
4035 "Invalid UDP item");
4039 case RTE_FLOW_ITEM_TYPE_GTPC:
4040 case RTE_FLOW_ITEM_TYPE_GTPU:
4041 gtp_spec = item->spec;
4042 gtp_mask = item->mask;
4044 if (!gtp_spec || !gtp_mask) {
4045 rte_flow_error_set(error, EINVAL,
4046 RTE_FLOW_ERROR_TYPE_ITEM,
4048 "Invalid GTP item");
4052 if (gtp_mask->v_pt_rsv_flags ||
4053 gtp_mask->msg_type ||
4054 gtp_mask->msg_len ||
4055 gtp_mask->teid != UINT32_MAX) {
4056 rte_flow_error_set(error, EINVAL,
4057 RTE_FLOW_ERROR_TYPE_ITEM,
4059 "Invalid GTP mask");
4063 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4064 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4065 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4066 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4068 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4080 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4081 const struct rte_flow_attr *attr,
4082 const struct rte_flow_item pattern[],
4083 const struct rte_flow_action actions[],
4084 struct rte_flow_error *error,
4085 union i40e_filter_t *filter)
4087 struct i40e_tunnel_filter_conf *tunnel_filter =
4088 &filter->consistent_tunnel_filter;
4091 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4092 error, tunnel_filter);
4096 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4100 ret = i40e_flow_parse_attr(attr, error);
4104 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4109 /* 1. Last in item should be NULL as range is not supported.
4110 * 2. Supported filter types: QINQ.
4111 * 3. Mask of fields which need to be matched should be
4113 * 4. Mask of fields which needn't to be matched should be
4117 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4118 const struct rte_flow_item *pattern,
4119 struct rte_flow_error *error,
4120 struct i40e_tunnel_filter_conf *filter)
4122 const struct rte_flow_item *item = pattern;
4123 const struct rte_flow_item_vlan *vlan_spec = NULL;
4124 const struct rte_flow_item_vlan *vlan_mask = NULL;
4125 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4126 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4127 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4128 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4130 enum rte_flow_item_type item_type;
4133 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4135 rte_flow_error_set(error, EINVAL,
4136 RTE_FLOW_ERROR_TYPE_ITEM,
4138 "Not support range");
4141 item_type = item->type;
4142 switch (item_type) {
4143 case RTE_FLOW_ITEM_TYPE_ETH:
4144 if (item->spec || item->mask) {
4145 rte_flow_error_set(error, EINVAL,
4146 RTE_FLOW_ERROR_TYPE_ITEM,
4148 "Invalid ETH item");
4152 case RTE_FLOW_ITEM_TYPE_VLAN:
4153 vlan_spec = item->spec;
4154 vlan_mask = item->mask;
4156 if (!(vlan_spec && vlan_mask) ||
4157 vlan_mask->inner_type) {
4158 rte_flow_error_set(error, EINVAL,
4159 RTE_FLOW_ERROR_TYPE_ITEM,
4161 "Invalid vlan item");
4166 o_vlan_spec = vlan_spec;
4167 o_vlan_mask = vlan_mask;
4170 i_vlan_spec = vlan_spec;
4171 i_vlan_mask = vlan_mask;
4181 /* Get filter specification */
4182 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4183 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4184 (i_vlan_mask != NULL) &&
4185 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4186 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4188 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4191 rte_flow_error_set(error, EINVAL,
4192 RTE_FLOW_ERROR_TYPE_ITEM,
4194 "Invalid filter type");
4198 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4203 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4204 const struct rte_flow_attr *attr,
4205 const struct rte_flow_item pattern[],
4206 const struct rte_flow_action actions[],
4207 struct rte_flow_error *error,
4208 union i40e_filter_t *filter)
4210 struct i40e_tunnel_filter_conf *tunnel_filter =
4211 &filter->consistent_tunnel_filter;
4214 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4215 error, tunnel_filter);
4219 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4223 ret = i40e_flow_parse_attr(attr, error);
4227 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4233 * This function is used to do configuration i40e existing RSS with rte_flow.
4234 * It also enable queue region configuration using flow API for i40e.
4235 * pattern can be used indicate what parameters will be include in flow,
4236 * like user_priority or flowtype for queue region or HASH function for RSS.
4237 * Action is used to transmit parameter like queue index and HASH
4238 * function for RSS, or flowtype for queue region configuration.
4241 * Case 1: only ETH, indicate flowtype for queue region will be parsed.
4242 * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4243 * Case 3: none, indicate RSS related will be parsed in action.
4244 * Any pattern other the ETH or VLAN will be treated as invalid except END.
4245 * So, pattern choice is depened on the purpose of configuration of
4248 * action RSS will be uaed to transmit valid parameter with
4249 * struct rte_flow_action_rss for all the 3 case.
4252 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4253 const struct rte_flow_item *pattern,
4254 struct rte_flow_error *error,
4255 uint8_t *action_flag,
4256 struct i40e_queue_regions *info)
4258 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4259 const struct rte_flow_item *item = pattern;
4260 enum rte_flow_item_type item_type;
4262 if (item->type == RTE_FLOW_ITEM_TYPE_END)
4265 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4267 rte_flow_error_set(error, EINVAL,
4268 RTE_FLOW_ERROR_TYPE_ITEM,
4270 "Not support range");
4273 item_type = item->type;
4274 switch (item_type) {
4275 case RTE_FLOW_ITEM_TYPE_ETH:
4278 case RTE_FLOW_ITEM_TYPE_VLAN:
4279 vlan_spec = item->spec;
4280 vlan_mask = item->mask;
4281 if (vlan_spec && vlan_mask) {
4282 if (vlan_mask->tci ==
4283 rte_cpu_to_be_16(I40E_TCI_MASK)) {
4284 info->region[0].user_priority[0] =
4286 vlan_spec->tci) >> 13) & 0x7;
4287 info->region[0].user_priority_num = 1;
4288 info->queue_region_number = 1;
4294 rte_flow_error_set(error, EINVAL,
4295 RTE_FLOW_ERROR_TYPE_ITEM,
4297 "Not support range");
4306 * This function is used to parse rss queue index, total queue number and
4307 * hash functions, If the purpose of this configuration is for queue region
4308 * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4309 * In queue region configuration, it also need to parse hardware flowtype
4310 * and user_priority from configuration, it will also cheeck the validity
4311 * of these parameters. For example, The queue region sizes should
4312 * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4313 * hw_flowtype or PCTYPE max index should be 63, the user priority
4314 * max index should be 7, and so on. And also, queue index should be
4315 * continuous sequence and queue region index should be part of rss
4316 * queue index for this port.
4319 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4320 const struct rte_flow_action *actions,
4321 struct rte_flow_error *error,
4322 uint8_t action_flag,
4323 struct i40e_queue_regions *conf_info,
4324 union i40e_filter_t *filter)
4326 const struct rte_flow_action *act;
4327 const struct rte_flow_action_rss *rss;
4328 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4329 struct i40e_queue_regions *info = &pf->queue_region;
4330 struct i40e_rte_flow_rss_conf *rss_config =
4332 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4333 uint16_t i, j, n, tmp;
4335 uint64_t hf_bit = 1;
4337 NEXT_ITEM_OF_ACTION(act, actions, index);
4341 * rss only supports forwarding,
4342 * check if the first not void action is RSS.
4344 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4345 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4346 rte_flow_error_set(error, EINVAL,
4347 RTE_FLOW_ERROR_TYPE_ACTION,
4348 act, "Not supported action.");
4353 for (n = 0; n < 64; n++) {
4354 if (rss->types & (hf_bit << n)) {
4355 conf_info->region[0].hw_flowtype[0] = n;
4356 conf_info->region[0].flowtype_num = 1;
4357 conf_info->queue_region_number = 1;
4364 * Do some queue region related parameters check
4365 * in order to keep queue index for queue region to be
4366 * continuous sequence and also to be part of RSS
4367 * queue index for this port.
4369 if (conf_info->queue_region_number) {
4370 for (i = 0; i < rss->queue_num; i++) {
4371 for (j = 0; j < rss_info->conf.queue_num; j++) {
4372 if (rss->queue[i] == rss_info->conf.queue[j])
4375 if (j == rss_info->conf.queue_num) {
4376 rte_flow_error_set(error, EINVAL,
4377 RTE_FLOW_ERROR_TYPE_ACTION,
4384 for (i = 0; i < rss->queue_num - 1; i++) {
4385 if (rss->queue[i + 1] != rss->queue[i] + 1) {
4386 rte_flow_error_set(error, EINVAL,
4387 RTE_FLOW_ERROR_TYPE_ACTION,
4395 /* Parse queue region related parameters from configuration */
4396 for (n = 0; n < conf_info->queue_region_number; n++) {
4397 if (conf_info->region[n].user_priority_num ||
4398 conf_info->region[n].flowtype_num) {
4399 if (!((rte_is_power_of_2(rss->queue_num)) &&
4400 rss->queue_num <= 64)) {
4401 rte_flow_error_set(error, EINVAL,
4402 RTE_FLOW_ERROR_TYPE_ACTION,
4404 "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4405 "total number of queues do not exceed the VSI allocation");
4409 if (conf_info->region[n].user_priority[n] >=
4410 I40E_MAX_USER_PRIORITY) {
4411 rte_flow_error_set(error, EINVAL,
4412 RTE_FLOW_ERROR_TYPE_ACTION,
4414 "the user priority max index is 7");
4418 if (conf_info->region[n].hw_flowtype[n] >=
4419 I40E_FILTER_PCTYPE_MAX) {
4420 rte_flow_error_set(error, EINVAL,
4421 RTE_FLOW_ERROR_TYPE_ACTION,
4423 "the hw_flowtype or PCTYPE max index is 63");
4427 for (i = 0; i < info->queue_region_number; i++) {
4428 if (info->region[i].queue_num ==
4430 info->region[i].queue_start_index ==
4435 if (i == info->queue_region_number) {
4436 if (i > I40E_REGION_MAX_INDEX) {
4437 rte_flow_error_set(error, EINVAL,
4438 RTE_FLOW_ERROR_TYPE_ACTION,
4440 "the queue region max index is 7");
4444 info->region[i].queue_num =
4446 info->region[i].queue_start_index =
4448 info->region[i].region_id =
4449 info->queue_region_number;
4451 j = info->region[i].user_priority_num;
4452 tmp = conf_info->region[n].user_priority[0];
4453 if (conf_info->region[n].user_priority_num) {
4454 info->region[i].user_priority[j] = tmp;
4455 info->region[i].user_priority_num++;
4458 j = info->region[i].flowtype_num;
4459 tmp = conf_info->region[n].hw_flowtype[0];
4460 if (conf_info->region[n].flowtype_num) {
4461 info->region[i].hw_flowtype[j] = tmp;
4462 info->region[i].flowtype_num++;
4464 info->queue_region_number++;
4466 j = info->region[i].user_priority_num;
4467 tmp = conf_info->region[n].user_priority[0];
4468 if (conf_info->region[n].user_priority_num) {
4469 info->region[i].user_priority[j] = tmp;
4470 info->region[i].user_priority_num++;
4473 j = info->region[i].flowtype_num;
4474 tmp = conf_info->region[n].hw_flowtype[0];
4475 if (conf_info->region[n].flowtype_num) {
4476 info->region[i].hw_flowtype[j] = tmp;
4477 info->region[i].flowtype_num++;
4482 rss_config->queue_region_conf = TRUE;
4486 * Return function if this flow is used for queue region configuration
4488 if (rss_config->queue_region_conf)
4491 if (!rss || !rss->queue_num) {
4492 rte_flow_error_set(error, EINVAL,
4493 RTE_FLOW_ERROR_TYPE_ACTION,
4499 for (n = 0; n < rss->queue_num; n++) {
4500 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4501 rte_flow_error_set(error, EINVAL,
4502 RTE_FLOW_ERROR_TYPE_ACTION,
4504 "queue id > max number of queues");
4509 if (rss_info->conf.queue_num) {
4510 rte_flow_error_set(error, EINVAL,
4511 RTE_FLOW_ERROR_TYPE_ACTION,
4513 "rss only allow one valid rule");
4517 /* Parse RSS related parameters from configuration */
4518 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4519 return rte_flow_error_set
4520 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4521 "non-default RSS hash functions are not supported");
4523 return rte_flow_error_set
4524 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4525 "a nonzero RSS encapsulation level is not supported");
4526 if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4527 return rte_flow_error_set
4528 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4529 "RSS hash key too large");
4530 if (rss->queue_num > RTE_DIM(rss_config->queue))
4531 return rte_flow_error_set
4532 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4533 "too many queues for RSS context");
4534 if (i40e_rss_conf_init(rss_config, rss))
4535 return rte_flow_error_set
4536 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4537 "RSS context initialization failure");
4541 /* check if the next not void action is END */
4542 NEXT_ITEM_OF_ACTION(act, actions, index);
4543 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4544 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4545 rte_flow_error_set(error, EINVAL,
4546 RTE_FLOW_ERROR_TYPE_ACTION,
4547 act, "Not supported action.");
4550 rss_config->queue_region_conf = FALSE;
4556 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4557 const struct rte_flow_attr *attr,
4558 const struct rte_flow_item pattern[],
4559 const struct rte_flow_action actions[],
4560 union i40e_filter_t *filter,
4561 struct rte_flow_error *error)
4564 struct i40e_queue_regions info;
4565 uint8_t action_flag = 0;
4567 memset(&info, 0, sizeof(struct i40e_queue_regions));
4569 ret = i40e_flow_parse_rss_pattern(dev, pattern,
4570 error, &action_flag, &info);
4574 ret = i40e_flow_parse_rss_action(dev, actions, error,
4575 action_flag, &info, filter);
4579 ret = i40e_flow_parse_attr(attr, error);
4583 cons_filter_type = RTE_ETH_FILTER_HASH;
4589 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4590 struct i40e_rte_flow_rss_conf *conf)
4592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596 if (conf->queue_region_conf) {
4597 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4598 conf->queue_region_conf = 0;
4600 ret = i40e_config_rss_filter(pf, conf, 1);
4606 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4607 struct i40e_rte_flow_rss_conf *conf)
4609 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4614 i40e_config_rss_filter(pf, conf, 0);
4619 i40e_flow_validate(struct rte_eth_dev *dev,
4620 const struct rte_flow_attr *attr,
4621 const struct rte_flow_item pattern[],
4622 const struct rte_flow_action actions[],
4623 struct rte_flow_error *error)
4625 struct rte_flow_item *items; /* internal pattern w/o VOID items */
4626 parse_filter_t parse_filter;
4627 uint32_t item_num = 0; /* non-void item number of pattern*/
4630 int ret = I40E_NOT_SUPPORTED;
4633 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4634 NULL, "NULL pattern.");
4639 rte_flow_error_set(error, EINVAL,
4640 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4641 NULL, "NULL action.");
4646 rte_flow_error_set(error, EINVAL,
4647 RTE_FLOW_ERROR_TYPE_ATTR,
4648 NULL, "NULL attribute.");
4652 memset(&cons_filter, 0, sizeof(cons_filter));
4654 /* Get the non-void item of action */
4655 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4658 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4659 ret = i40e_parse_rss_filter(dev, attr, pattern,
4660 actions, &cons_filter, error);
4665 /* Get the non-void item number of pattern */
4666 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4667 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4673 items = rte_zmalloc("i40e_pattern",
4674 item_num * sizeof(struct rte_flow_item), 0);
4676 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4677 NULL, "No memory for PMD internal items.");
4681 i40e_pattern_skip_void_item(items, pattern);
4685 parse_filter = i40e_find_parse_filter_func(items, &i);
4686 if (!parse_filter && !flag) {
4687 rte_flow_error_set(error, EINVAL,
4688 RTE_FLOW_ERROR_TYPE_ITEM,
4689 pattern, "Unsupported pattern");
4694 ret = parse_filter(dev, attr, items, actions,
4695 error, &cons_filter);
4697 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4704 static struct rte_flow *
4705 i40e_flow_create(struct rte_eth_dev *dev,
4706 const struct rte_flow_attr *attr,
4707 const struct rte_flow_item pattern[],
4708 const struct rte_flow_action actions[],
4709 struct rte_flow_error *error)
4711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4712 struct rte_flow *flow;
4715 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4717 rte_flow_error_set(error, ENOMEM,
4718 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4719 "Failed to allocate memory");
4723 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4727 switch (cons_filter_type) {
4728 case RTE_ETH_FILTER_ETHERTYPE:
4729 ret = i40e_ethertype_filter_set(pf,
4730 &cons_filter.ethertype_filter, 1);
4733 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4734 i40e_ethertype_filter_list);
4736 case RTE_ETH_FILTER_FDIR:
4737 ret = i40e_flow_add_del_fdir_filter(dev,
4738 &cons_filter.fdir_filter, 1);
4741 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4742 i40e_fdir_filter_list);
4744 case RTE_ETH_FILTER_TUNNEL:
4745 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4746 &cons_filter.consistent_tunnel_filter, 1);
4749 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4750 i40e_tunnel_filter_list);
4752 case RTE_ETH_FILTER_HASH:
4753 ret = i40e_config_rss_filter_set(dev,
4754 &cons_filter.rss_conf);
4757 flow->rule = &pf->rss_info;
4763 flow->filter_type = cons_filter_type;
4764 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4768 rte_flow_error_set(error, -ret,
4769 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4770 "Failed to create flow.");
4776 i40e_flow_destroy(struct rte_eth_dev *dev,
4777 struct rte_flow *flow,
4778 struct rte_flow_error *error)
4780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4781 enum rte_filter_type filter_type = flow->filter_type;
4784 switch (filter_type) {
4785 case RTE_ETH_FILTER_ETHERTYPE:
4786 ret = i40e_flow_destroy_ethertype_filter(pf,
4787 (struct i40e_ethertype_filter *)flow->rule);
4789 case RTE_ETH_FILTER_TUNNEL:
4790 ret = i40e_flow_destroy_tunnel_filter(pf,
4791 (struct i40e_tunnel_filter *)flow->rule);
4793 case RTE_ETH_FILTER_FDIR:
4794 ret = i40e_flow_add_del_fdir_filter(dev,
4795 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4797 /* If the last flow is destroyed, disable fdir. */
4798 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) {
4799 i40e_fdir_teardown(pf);
4800 dev->data->dev_conf.fdir_conf.mode =
4802 i40e_fdir_rx_proc_enable(dev, 0);
4805 case RTE_ETH_FILTER_HASH:
4806 ret = i40e_config_rss_filter_del(dev,
4807 (struct i40e_rte_flow_rss_conf *)flow->rule);
4810 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4817 TAILQ_REMOVE(&pf->flow_list, flow, node);
4820 rte_flow_error_set(error, -ret,
4821 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4822 "Failed to destroy flow.");
4828 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4829 struct i40e_ethertype_filter *filter)
4831 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4832 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4833 struct i40e_ethertype_filter *node;
4834 struct i40e_control_filter_stats stats;
4838 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4839 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4840 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4841 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4842 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4844 memset(&stats, 0, sizeof(stats));
4845 ret = i40e_aq_add_rem_control_packet_filter(hw,
4846 filter->input.mac_addr.addr_bytes,
4847 filter->input.ether_type,
4848 flags, pf->main_vsi->seid,
4849 filter->queue, 0, &stats, NULL);
4853 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4857 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4863 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4864 struct i40e_tunnel_filter *filter)
4866 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4867 struct i40e_vsi *vsi;
4868 struct i40e_pf_vf *vf;
4869 struct i40e_aqc_cloud_filters_element_bb cld_filter;
4870 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4871 struct i40e_tunnel_filter *node;
4872 bool big_buffer = 0;
4875 memset(&cld_filter, 0, sizeof(cld_filter));
4876 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
4877 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
4878 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
4879 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
4880 cld_filter.element.inner_vlan = filter->input.inner_vlan;
4881 cld_filter.element.flags = filter->input.flags;
4882 cld_filter.element.tenant_id = filter->input.tenant_id;
4883 cld_filter.element.queue_number = filter->queue;
4884 rte_memcpy(cld_filter.general_fields,
4885 filter->input.general_fields,
4886 sizeof(cld_filter.general_fields));
4888 if (!filter->is_to_vf)
4891 vf = &pf->vfs[filter->vf_id];
4895 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4896 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4897 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4898 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4899 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4900 I40E_AQC_ADD_CLOUD_FILTER_0X10))
4904 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
4907 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
4908 &cld_filter.element, 1);
4912 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4916 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4922 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4924 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4927 ret = i40e_flow_flush_fdir_filter(pf);
4929 rte_flow_error_set(error, -ret,
4930 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4931 "Failed to flush FDIR flows.");
4935 ret = i40e_flow_flush_ethertype_filter(pf);
4937 rte_flow_error_set(error, -ret,
4938 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4939 "Failed to ethertype flush flows.");
4943 ret = i40e_flow_flush_tunnel_filter(pf);
4945 rte_flow_error_set(error, -ret,
4946 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4947 "Failed to flush tunnel flows.");
4951 ret = i40e_flow_flush_rss_filter(dev);
4953 rte_flow_error_set(error, -ret,
4954 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4955 "Failed to flush rss flows.");
4959 /* Disable FDIR processing as all FDIR rules are now flushed */
4960 i40e_fdir_rx_proc_enable(dev, 0);
4966 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4968 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4969 struct i40e_fdir_info *fdir_info = &pf->fdir;
4970 struct i40e_fdir_filter *fdir_filter;
4971 enum i40e_filter_pctype pctype;
4972 struct rte_flow *flow;
4976 ret = i40e_fdir_flush(dev);
4978 /* Delete FDIR filters in FDIR list. */
4979 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4980 ret = i40e_sw_fdir_filter_del(pf,
4981 &fdir_filter->fdir.input);
4986 /* Delete FDIR flows in flow list. */
4987 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4988 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4989 TAILQ_REMOVE(&pf->flow_list, flow, node);
4994 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4995 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4996 pf->fdir.inset_flag[pctype] = 0;
4999 i40e_fdir_teardown(pf);
5004 /* Flush all ethertype filters */
5006 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
5008 struct i40e_ethertype_filter_list
5009 *ethertype_list = &pf->ethertype.ethertype_list;
5010 struct i40e_ethertype_filter *filter;
5011 struct rte_flow *flow;
5015 while ((filter = TAILQ_FIRST(ethertype_list))) {
5016 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
5021 /* Delete ethertype flows in flow list. */
5022 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5023 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
5024 TAILQ_REMOVE(&pf->flow_list, flow, node);
5032 /* Flush all tunnel filters */
5034 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5036 struct i40e_tunnel_filter_list
5037 *tunnel_list = &pf->tunnel.tunnel_list;
5038 struct i40e_tunnel_filter *filter;
5039 struct rte_flow *flow;
5043 while ((filter = TAILQ_FIRST(tunnel_list))) {
5044 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5049 /* Delete tunnel flows in flow list. */
5050 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5051 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5052 TAILQ_REMOVE(&pf->flow_list, flow, node);
5060 /* remove the rss filter */
5062 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5064 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5065 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
5066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067 int32_t ret = -EINVAL;
5069 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5071 if (rss_info->conf.queue_num)
5072 ret = i40e_config_rss_filter(pf, rss_info, FALSE);