drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_attr *attr,
  57                                         const struct rte_flow_item *pattern,
  58                                         struct rte_flow_error *error,
  59                                         struct i40e_fdir_filter_conf *filter);
  60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  61                                        const struct rte_flow_action *actions,
  62                                        struct rte_flow_error *error,
  63                                        struct i40e_fdir_filter_conf *filter);
  64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  65                                  const struct rte_flow_action *actions,
  66                                  struct rte_flow_error *error,
  67                                  struct i40e_tunnel_filter_conf *filter);
  68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  69                                 struct rte_flow_error *error);
  70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  71                                     const struct rte_flow_attr *attr,
  72                                     const struct rte_flow_item pattern[],
  73                                     const struct rte_flow_action actions[],
  74                                     struct rte_flow_error *error,
  75                                     union i40e_filter_t *filter);
  76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  77                                        const struct rte_flow_attr *attr,
  78                                        const struct rte_flow_item pattern[],
  79                                        const struct rte_flow_action actions[],
  80                                        struct rte_flow_error *error,
  81                                        union i40e_filter_t *filter);
  82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  83                                         const struct rte_flow_attr *attr,
  84                                         const struct rte_flow_item pattern[],
  85                                         const struct rte_flow_action actions[],
  86                                         struct rte_flow_error *error,
  87                                         union i40e_filter_t *filter);
  88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  89                                         const struct rte_flow_attr *attr,
  90                                         const struct rte_flow_item pattern[],
  91                                         const struct rte_flow_action actions[],
  92                                         struct rte_flow_error *error,
  93                                         union i40e_filter_t *filter);
  94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  95                                        const struct rte_flow_attr *attr,
  96                                        const struct rte_flow_item pattern[],
  97                                        const struct rte_flow_action actions[],
  98                                        struct rte_flow_error *error,
  99                                        union i40e_filter_t *filter);
 100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 101                                       const struct rte_flow_attr *attr,
 102                                       const struct rte_flow_item pattern[],
 103                                       const struct rte_flow_action actions[],
 104                                       struct rte_flow_error *error,
 105                                       union i40e_filter_t *filter);
 106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 107                                       struct i40e_ethertype_filter *filter);
 108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 109                                            struct i40e_tunnel_filter *filter);
 110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 113 static int i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 114 static int
 115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 116                               const struct rte_flow_attr *attr,
 117                               const struct rte_flow_item pattern[],
 118                               const struct rte_flow_action actions[],
 119                               struct rte_flow_error *error,
 120                               union i40e_filter_t *filter);
 121 static int
 122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 123                               const struct rte_flow_item *pattern,
 124                               struct rte_flow_error *error,
 125                               struct i40e_tunnel_filter_conf *filter);
 126
 127 const struct rte_flow_ops i40e_flow_ops = {
 128         .validate = i40e_flow_validate,
 129         .create = i40e_flow_create,
 130         .destroy = i40e_flow_destroy,
 131         .flush = i40e_flow_flush,
 132 };
 133
 134 static union i40e_filter_t cons_filter;
 135 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 136
 137 /* Pattern matched ethertype filter */
 138 static enum rte_flow_item_type pattern_ethertype[] = {
 139         RTE_FLOW_ITEM_TYPE_ETH,
 140         RTE_FLOW_ITEM_TYPE_END,
 141 };
 142
 143 /* Pattern matched flow director filter */
 144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 145         RTE_FLOW_ITEM_TYPE_ETH,
 146         RTE_FLOW_ITEM_TYPE_IPV4,
 147         RTE_FLOW_ITEM_TYPE_END,
 148 };
 149
 150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 151         RTE_FLOW_ITEM_TYPE_ETH,
 152         RTE_FLOW_ITEM_TYPE_IPV4,
 153         RTE_FLOW_ITEM_TYPE_UDP,
 154         RTE_FLOW_ITEM_TYPE_END,
 155 };
 156
 157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 158         RTE_FLOW_ITEM_TYPE_ETH,
 159         RTE_FLOW_ITEM_TYPE_IPV4,
 160         RTE_FLOW_ITEM_TYPE_TCP,
 161         RTE_FLOW_ITEM_TYPE_END,
 162 };
 163
 164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 165         RTE_FLOW_ITEM_TYPE_ETH,
 166         RTE_FLOW_ITEM_TYPE_IPV4,
 167         RTE_FLOW_ITEM_TYPE_SCTP,
 168         RTE_FLOW_ITEM_TYPE_END,
 169 };
 170
 171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 172         RTE_FLOW_ITEM_TYPE_ETH,
 173         RTE_FLOW_ITEM_TYPE_IPV4,
 174         RTE_FLOW_ITEM_TYPE_UDP,
 175         RTE_FLOW_ITEM_TYPE_GTPC,
 176         RTE_FLOW_ITEM_TYPE_END,
 177 };
 178
 179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 180         RTE_FLOW_ITEM_TYPE_ETH,
 181         RTE_FLOW_ITEM_TYPE_IPV4,
 182         RTE_FLOW_ITEM_TYPE_UDP,
 183         RTE_FLOW_ITEM_TYPE_GTPU,
 184         RTE_FLOW_ITEM_TYPE_END,
 185 };
 186
 187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 188         RTE_FLOW_ITEM_TYPE_ETH,
 189         RTE_FLOW_ITEM_TYPE_IPV4,
 190         RTE_FLOW_ITEM_TYPE_UDP,
 191         RTE_FLOW_ITEM_TYPE_GTPU,
 192         RTE_FLOW_ITEM_TYPE_IPV4,
 193         RTE_FLOW_ITEM_TYPE_END,
 194 };
 195
 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 197         RTE_FLOW_ITEM_TYPE_ETH,
 198         RTE_FLOW_ITEM_TYPE_IPV4,
 199         RTE_FLOW_ITEM_TYPE_UDP,
 200         RTE_FLOW_ITEM_TYPE_GTPU,
 201         RTE_FLOW_ITEM_TYPE_IPV6,
 202         RTE_FLOW_ITEM_TYPE_END,
 203 };
 204
 205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 206         RTE_FLOW_ITEM_TYPE_ETH,
 207         RTE_FLOW_ITEM_TYPE_IPV6,
 208         RTE_FLOW_ITEM_TYPE_END,
 209 };
 210
 211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 212         RTE_FLOW_ITEM_TYPE_ETH,
 213         RTE_FLOW_ITEM_TYPE_IPV6,
 214         RTE_FLOW_ITEM_TYPE_UDP,
 215         RTE_FLOW_ITEM_TYPE_END,
 216 };
 217
 218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 219         RTE_FLOW_ITEM_TYPE_ETH,
 220         RTE_FLOW_ITEM_TYPE_IPV6,
 221         RTE_FLOW_ITEM_TYPE_TCP,
 222         RTE_FLOW_ITEM_TYPE_END,
 223 };
 224
 225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 226         RTE_FLOW_ITEM_TYPE_ETH,
 227         RTE_FLOW_ITEM_TYPE_IPV6,
 228         RTE_FLOW_ITEM_TYPE_SCTP,
 229         RTE_FLOW_ITEM_TYPE_END,
 230 };
 231
 232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 233         RTE_FLOW_ITEM_TYPE_ETH,
 234         RTE_FLOW_ITEM_TYPE_IPV6,
 235         RTE_FLOW_ITEM_TYPE_UDP,
 236         RTE_FLOW_ITEM_TYPE_GTPC,
 237         RTE_FLOW_ITEM_TYPE_END,
 238 };
 239
 240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 241         RTE_FLOW_ITEM_TYPE_ETH,
 242         RTE_FLOW_ITEM_TYPE_IPV6,
 243         RTE_FLOW_ITEM_TYPE_UDP,
 244         RTE_FLOW_ITEM_TYPE_GTPU,
 245         RTE_FLOW_ITEM_TYPE_END,
 246 };
 247
 248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 249         RTE_FLOW_ITEM_TYPE_ETH,
 250         RTE_FLOW_ITEM_TYPE_IPV6,
 251         RTE_FLOW_ITEM_TYPE_UDP,
 252         RTE_FLOW_ITEM_TYPE_GTPU,
 253         RTE_FLOW_ITEM_TYPE_IPV4,
 254         RTE_FLOW_ITEM_TYPE_END,
 255 };
 256
 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 258         RTE_FLOW_ITEM_TYPE_ETH,
 259         RTE_FLOW_ITEM_TYPE_IPV6,
 260         RTE_FLOW_ITEM_TYPE_UDP,
 261         RTE_FLOW_ITEM_TYPE_GTPU,
 262         RTE_FLOW_ITEM_TYPE_IPV6,
 263         RTE_FLOW_ITEM_TYPE_END,
 264 };
 265
 266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 267         RTE_FLOW_ITEM_TYPE_ETH,
 268         RTE_FLOW_ITEM_TYPE_RAW,
 269         RTE_FLOW_ITEM_TYPE_END,
 270 };
 271
 272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 273         RTE_FLOW_ITEM_TYPE_ETH,
 274         RTE_FLOW_ITEM_TYPE_RAW,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_END,
 277 };
 278
 279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 280         RTE_FLOW_ITEM_TYPE_ETH,
 281         RTE_FLOW_ITEM_TYPE_RAW,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_END,
 285 };
 286
 287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 288         RTE_FLOW_ITEM_TYPE_ETH,
 289         RTE_FLOW_ITEM_TYPE_IPV4,
 290         RTE_FLOW_ITEM_TYPE_RAW,
 291         RTE_FLOW_ITEM_TYPE_END,
 292 };
 293
 294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 295         RTE_FLOW_ITEM_TYPE_ETH,
 296         RTE_FLOW_ITEM_TYPE_IPV4,
 297         RTE_FLOW_ITEM_TYPE_RAW,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_END,
 300 };
 301
 302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 303         RTE_FLOW_ITEM_TYPE_ETH,
 304         RTE_FLOW_ITEM_TYPE_IPV4,
 305         RTE_FLOW_ITEM_TYPE_RAW,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_END,
 309 };
 310
 311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 312         RTE_FLOW_ITEM_TYPE_ETH,
 313         RTE_FLOW_ITEM_TYPE_IPV4,
 314         RTE_FLOW_ITEM_TYPE_UDP,
 315         RTE_FLOW_ITEM_TYPE_RAW,
 316         RTE_FLOW_ITEM_TYPE_END,
 317 };
 318
 319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 320         RTE_FLOW_ITEM_TYPE_ETH,
 321         RTE_FLOW_ITEM_TYPE_IPV4,
 322         RTE_FLOW_ITEM_TYPE_UDP,
 323         RTE_FLOW_ITEM_TYPE_RAW,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_END,
 326 };
 327
 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 329         RTE_FLOW_ITEM_TYPE_ETH,
 330         RTE_FLOW_ITEM_TYPE_IPV4,
 331         RTE_FLOW_ITEM_TYPE_UDP,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_END,
 336 };
 337
 338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 339         RTE_FLOW_ITEM_TYPE_ETH,
 340         RTE_FLOW_ITEM_TYPE_IPV4,
 341         RTE_FLOW_ITEM_TYPE_TCP,
 342         RTE_FLOW_ITEM_TYPE_RAW,
 343         RTE_FLOW_ITEM_TYPE_END,
 344 };
 345
 346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 347         RTE_FLOW_ITEM_TYPE_ETH,
 348         RTE_FLOW_ITEM_TYPE_IPV4,
 349         RTE_FLOW_ITEM_TYPE_TCP,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_TCP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_END,
 363 };
 364
 365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 366         RTE_FLOW_ITEM_TYPE_ETH,
 367         RTE_FLOW_ITEM_TYPE_IPV4,
 368         RTE_FLOW_ITEM_TYPE_SCTP,
 369         RTE_FLOW_ITEM_TYPE_RAW,
 370         RTE_FLOW_ITEM_TYPE_END,
 371 };
 372
 373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 374         RTE_FLOW_ITEM_TYPE_ETH,
 375         RTE_FLOW_ITEM_TYPE_IPV4,
 376         RTE_FLOW_ITEM_TYPE_SCTP,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_SCTP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_END,
 390 };
 391
 392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 393         RTE_FLOW_ITEM_TYPE_ETH,
 394         RTE_FLOW_ITEM_TYPE_IPV6,
 395         RTE_FLOW_ITEM_TYPE_RAW,
 396         RTE_FLOW_ITEM_TYPE_END,
 397 };
 398
 399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 400         RTE_FLOW_ITEM_TYPE_ETH,
 401         RTE_FLOW_ITEM_TYPE_IPV6,
 402         RTE_FLOW_ITEM_TYPE_RAW,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_END,
 405 };
 406
 407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 408         RTE_FLOW_ITEM_TYPE_ETH,
 409         RTE_FLOW_ITEM_TYPE_IPV6,
 410         RTE_FLOW_ITEM_TYPE_RAW,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_END,
 414 };
 415
 416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 417         RTE_FLOW_ITEM_TYPE_ETH,
 418         RTE_FLOW_ITEM_TYPE_IPV6,
 419         RTE_FLOW_ITEM_TYPE_UDP,
 420         RTE_FLOW_ITEM_TYPE_RAW,
 421         RTE_FLOW_ITEM_TYPE_END,
 422 };
 423
 424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 425         RTE_FLOW_ITEM_TYPE_ETH,
 426         RTE_FLOW_ITEM_TYPE_IPV6,
 427         RTE_FLOW_ITEM_TYPE_UDP,
 428         RTE_FLOW_ITEM_TYPE_RAW,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_END,
 431 };
 432
 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 434         RTE_FLOW_ITEM_TYPE_ETH,
 435         RTE_FLOW_ITEM_TYPE_IPV6,
 436         RTE_FLOW_ITEM_TYPE_UDP,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_END,
 441 };
 442
 443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 444         RTE_FLOW_ITEM_TYPE_ETH,
 445         RTE_FLOW_ITEM_TYPE_IPV6,
 446         RTE_FLOW_ITEM_TYPE_TCP,
 447         RTE_FLOW_ITEM_TYPE_RAW,
 448         RTE_FLOW_ITEM_TYPE_END,
 449 };
 450
 451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 452         RTE_FLOW_ITEM_TYPE_ETH,
 453         RTE_FLOW_ITEM_TYPE_IPV6,
 454         RTE_FLOW_ITEM_TYPE_TCP,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_TCP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_END,
 468 };
 469
 470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 471         RTE_FLOW_ITEM_TYPE_ETH,
 472         RTE_FLOW_ITEM_TYPE_IPV6,
 473         RTE_FLOW_ITEM_TYPE_SCTP,
 474         RTE_FLOW_ITEM_TYPE_RAW,
 475         RTE_FLOW_ITEM_TYPE_END,
 476 };
 477
 478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 479         RTE_FLOW_ITEM_TYPE_ETH,
 480         RTE_FLOW_ITEM_TYPE_IPV6,
 481         RTE_FLOW_ITEM_TYPE_SCTP,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_SCTP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_END,
 495 };
 496
 497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 498         RTE_FLOW_ITEM_TYPE_ETH,
 499         RTE_FLOW_ITEM_TYPE_VLAN,
 500         RTE_FLOW_ITEM_TYPE_END,
 501 };
 502
 503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 504         RTE_FLOW_ITEM_TYPE_ETH,
 505         RTE_FLOW_ITEM_TYPE_VLAN,
 506         RTE_FLOW_ITEM_TYPE_IPV4,
 507         RTE_FLOW_ITEM_TYPE_END,
 508 };
 509
 510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 511         RTE_FLOW_ITEM_TYPE_ETH,
 512         RTE_FLOW_ITEM_TYPE_VLAN,
 513         RTE_FLOW_ITEM_TYPE_IPV4,
 514         RTE_FLOW_ITEM_TYPE_UDP,
 515         RTE_FLOW_ITEM_TYPE_END,
 516 };
 517
 518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 519         RTE_FLOW_ITEM_TYPE_ETH,
 520         RTE_FLOW_ITEM_TYPE_VLAN,
 521         RTE_FLOW_ITEM_TYPE_IPV4,
 522         RTE_FLOW_ITEM_TYPE_TCP,
 523         RTE_FLOW_ITEM_TYPE_END,
 524 };
 525
 526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 527         RTE_FLOW_ITEM_TYPE_ETH,
 528         RTE_FLOW_ITEM_TYPE_VLAN,
 529         RTE_FLOW_ITEM_TYPE_IPV4,
 530         RTE_FLOW_ITEM_TYPE_SCTP,
 531         RTE_FLOW_ITEM_TYPE_END,
 532 };
 533
 534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 535         RTE_FLOW_ITEM_TYPE_ETH,
 536         RTE_FLOW_ITEM_TYPE_VLAN,
 537         RTE_FLOW_ITEM_TYPE_IPV6,
 538         RTE_FLOW_ITEM_TYPE_END,
 539 };
 540
 541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 542         RTE_FLOW_ITEM_TYPE_ETH,
 543         RTE_FLOW_ITEM_TYPE_VLAN,
 544         RTE_FLOW_ITEM_TYPE_IPV6,
 545         RTE_FLOW_ITEM_TYPE_UDP,
 546         RTE_FLOW_ITEM_TYPE_END,
 547 };
 548
 549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 550         RTE_FLOW_ITEM_TYPE_ETH,
 551         RTE_FLOW_ITEM_TYPE_VLAN,
 552         RTE_FLOW_ITEM_TYPE_IPV6,
 553         RTE_FLOW_ITEM_TYPE_TCP,
 554         RTE_FLOW_ITEM_TYPE_END,
 555 };
 556
 557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 558         RTE_FLOW_ITEM_TYPE_ETH,
 559         RTE_FLOW_ITEM_TYPE_VLAN,
 560         RTE_FLOW_ITEM_TYPE_IPV6,
 561         RTE_FLOW_ITEM_TYPE_SCTP,
 562         RTE_FLOW_ITEM_TYPE_END,
 563 };
 564
 565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 566         RTE_FLOW_ITEM_TYPE_ETH,
 567         RTE_FLOW_ITEM_TYPE_VLAN,
 568         RTE_FLOW_ITEM_TYPE_RAW,
 569         RTE_FLOW_ITEM_TYPE_END,
 570 };
 571
 572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 573         RTE_FLOW_ITEM_TYPE_ETH,
 574         RTE_FLOW_ITEM_TYPE_VLAN,
 575         RTE_FLOW_ITEM_TYPE_RAW,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_END,
 578 };
 579
 580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 581         RTE_FLOW_ITEM_TYPE_ETH,
 582         RTE_FLOW_ITEM_TYPE_VLAN,
 583         RTE_FLOW_ITEM_TYPE_RAW,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_END,
 587 };
 588
 589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 590         RTE_FLOW_ITEM_TYPE_ETH,
 591         RTE_FLOW_ITEM_TYPE_VLAN,
 592         RTE_FLOW_ITEM_TYPE_IPV4,
 593         RTE_FLOW_ITEM_TYPE_RAW,
 594         RTE_FLOW_ITEM_TYPE_END,
 595 };
 596
 597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 598         RTE_FLOW_ITEM_TYPE_ETH,
 599         RTE_FLOW_ITEM_TYPE_VLAN,
 600         RTE_FLOW_ITEM_TYPE_IPV4,
 601         RTE_FLOW_ITEM_TYPE_RAW,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_END,
 604 };
 605
 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 607         RTE_FLOW_ITEM_TYPE_ETH,
 608         RTE_FLOW_ITEM_TYPE_VLAN,
 609         RTE_FLOW_ITEM_TYPE_IPV4,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_END,
 614 };
 615
 616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 617         RTE_FLOW_ITEM_TYPE_ETH,
 618         RTE_FLOW_ITEM_TYPE_VLAN,
 619         RTE_FLOW_ITEM_TYPE_IPV4,
 620         RTE_FLOW_ITEM_TYPE_UDP,
 621         RTE_FLOW_ITEM_TYPE_RAW,
 622         RTE_FLOW_ITEM_TYPE_END,
 623 };
 624
 625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 626         RTE_FLOW_ITEM_TYPE_ETH,
 627         RTE_FLOW_ITEM_TYPE_VLAN,
 628         RTE_FLOW_ITEM_TYPE_IPV4,
 629         RTE_FLOW_ITEM_TYPE_UDP,
 630         RTE_FLOW_ITEM_TYPE_RAW,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_END,
 633 };
 634
 635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 636         RTE_FLOW_ITEM_TYPE_ETH,
 637         RTE_FLOW_ITEM_TYPE_VLAN,
 638         RTE_FLOW_ITEM_TYPE_IPV4,
 639         RTE_FLOW_ITEM_TYPE_UDP,
 640         RTE_FLOW_ITEM_TYPE_RAW,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_END,
 644 };
 645
 646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 647         RTE_FLOW_ITEM_TYPE_ETH,
 648         RTE_FLOW_ITEM_TYPE_VLAN,
 649         RTE_FLOW_ITEM_TYPE_IPV4,
 650         RTE_FLOW_ITEM_TYPE_TCP,
 651         RTE_FLOW_ITEM_TYPE_RAW,
 652         RTE_FLOW_ITEM_TYPE_END,
 653 };
 654
 655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 656         RTE_FLOW_ITEM_TYPE_ETH,
 657         RTE_FLOW_ITEM_TYPE_VLAN,
 658         RTE_FLOW_ITEM_TYPE_IPV4,
 659         RTE_FLOW_ITEM_TYPE_TCP,
 660         RTE_FLOW_ITEM_TYPE_RAW,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_END,
 663 };
 664
 665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 666         RTE_FLOW_ITEM_TYPE_ETH,
 667         RTE_FLOW_ITEM_TYPE_VLAN,
 668         RTE_FLOW_ITEM_TYPE_IPV4,
 669         RTE_FLOW_ITEM_TYPE_TCP,
 670         RTE_FLOW_ITEM_TYPE_RAW,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_END,
 674 };
 675
 676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 677         RTE_FLOW_ITEM_TYPE_ETH,
 678         RTE_FLOW_ITEM_TYPE_VLAN,
 679         RTE_FLOW_ITEM_TYPE_IPV4,
 680         RTE_FLOW_ITEM_TYPE_SCTP,
 681         RTE_FLOW_ITEM_TYPE_RAW,
 682         RTE_FLOW_ITEM_TYPE_END,
 683 };
 684
 685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 686         RTE_FLOW_ITEM_TYPE_ETH,
 687         RTE_FLOW_ITEM_TYPE_VLAN,
 688         RTE_FLOW_ITEM_TYPE_IPV4,
 689         RTE_FLOW_ITEM_TYPE_SCTP,
 690         RTE_FLOW_ITEM_TYPE_RAW,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_END,
 693 };
 694
 695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 696         RTE_FLOW_ITEM_TYPE_ETH,
 697         RTE_FLOW_ITEM_TYPE_VLAN,
 698         RTE_FLOW_ITEM_TYPE_IPV4,
 699         RTE_FLOW_ITEM_TYPE_SCTP,
 700         RTE_FLOW_ITEM_TYPE_RAW,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_END,
 704 };
 705
 706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 707         RTE_FLOW_ITEM_TYPE_ETH,
 708         RTE_FLOW_ITEM_TYPE_VLAN,
 709         RTE_FLOW_ITEM_TYPE_IPV6,
 710         RTE_FLOW_ITEM_TYPE_RAW,
 711         RTE_FLOW_ITEM_TYPE_END,
 712 };
 713
 714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 715         RTE_FLOW_ITEM_TYPE_ETH,
 716         RTE_FLOW_ITEM_TYPE_VLAN,
 717         RTE_FLOW_ITEM_TYPE_IPV6,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_END,
 721 };
 722
 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 724         RTE_FLOW_ITEM_TYPE_ETH,
 725         RTE_FLOW_ITEM_TYPE_VLAN,
 726         RTE_FLOW_ITEM_TYPE_IPV6,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_END,
 731 };
 732
 733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 734         RTE_FLOW_ITEM_TYPE_ETH,
 735         RTE_FLOW_ITEM_TYPE_VLAN,
 736         RTE_FLOW_ITEM_TYPE_IPV6,
 737         RTE_FLOW_ITEM_TYPE_UDP,
 738         RTE_FLOW_ITEM_TYPE_RAW,
 739         RTE_FLOW_ITEM_TYPE_END,
 740 };
 741
 742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 743         RTE_FLOW_ITEM_TYPE_ETH,
 744         RTE_FLOW_ITEM_TYPE_VLAN,
 745         RTE_FLOW_ITEM_TYPE_IPV6,
 746         RTE_FLOW_ITEM_TYPE_UDP,
 747         RTE_FLOW_ITEM_TYPE_RAW,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_END,
 750 };
 751
 752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 753         RTE_FLOW_ITEM_TYPE_ETH,
 754         RTE_FLOW_ITEM_TYPE_VLAN,
 755         RTE_FLOW_ITEM_TYPE_IPV6,
 756         RTE_FLOW_ITEM_TYPE_UDP,
 757         RTE_FLOW_ITEM_TYPE_RAW,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_END,
 761 };
 762
 763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 764         RTE_FLOW_ITEM_TYPE_ETH,
 765         RTE_FLOW_ITEM_TYPE_VLAN,
 766         RTE_FLOW_ITEM_TYPE_IPV6,
 767         RTE_FLOW_ITEM_TYPE_TCP,
 768         RTE_FLOW_ITEM_TYPE_RAW,
 769         RTE_FLOW_ITEM_TYPE_END,
 770 };
 771
 772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 773         RTE_FLOW_ITEM_TYPE_ETH,
 774         RTE_FLOW_ITEM_TYPE_VLAN,
 775         RTE_FLOW_ITEM_TYPE_IPV6,
 776         RTE_FLOW_ITEM_TYPE_TCP,
 777         RTE_FLOW_ITEM_TYPE_RAW,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_END,
 780 };
 781
 782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 783         RTE_FLOW_ITEM_TYPE_ETH,
 784         RTE_FLOW_ITEM_TYPE_VLAN,
 785         RTE_FLOW_ITEM_TYPE_IPV6,
 786         RTE_FLOW_ITEM_TYPE_TCP,
 787         RTE_FLOW_ITEM_TYPE_RAW,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_END,
 791 };
 792
 793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 794         RTE_FLOW_ITEM_TYPE_ETH,
 795         RTE_FLOW_ITEM_TYPE_VLAN,
 796         RTE_FLOW_ITEM_TYPE_IPV6,
 797         RTE_FLOW_ITEM_TYPE_SCTP,
 798         RTE_FLOW_ITEM_TYPE_RAW,
 799         RTE_FLOW_ITEM_TYPE_END,
 800 };
 801
 802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 803         RTE_FLOW_ITEM_TYPE_ETH,
 804         RTE_FLOW_ITEM_TYPE_VLAN,
 805         RTE_FLOW_ITEM_TYPE_IPV6,
 806         RTE_FLOW_ITEM_TYPE_SCTP,
 807         RTE_FLOW_ITEM_TYPE_RAW,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_END,
 810 };
 811
 812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 813         RTE_FLOW_ITEM_TYPE_ETH,
 814         RTE_FLOW_ITEM_TYPE_VLAN,
 815         RTE_FLOW_ITEM_TYPE_IPV6,
 816         RTE_FLOW_ITEM_TYPE_SCTP,
 817         RTE_FLOW_ITEM_TYPE_RAW,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_END,
 821 };
 822
 823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 824         RTE_FLOW_ITEM_TYPE_ETH,
 825         RTE_FLOW_ITEM_TYPE_IPV4,
 826         RTE_FLOW_ITEM_TYPE_VF,
 827         RTE_FLOW_ITEM_TYPE_END,
 828 };
 829
 830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 831         RTE_FLOW_ITEM_TYPE_ETH,
 832         RTE_FLOW_ITEM_TYPE_IPV4,
 833         RTE_FLOW_ITEM_TYPE_UDP,
 834         RTE_FLOW_ITEM_TYPE_VF,
 835         RTE_FLOW_ITEM_TYPE_END,
 836 };
 837
 838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 839         RTE_FLOW_ITEM_TYPE_ETH,
 840         RTE_FLOW_ITEM_TYPE_IPV4,
 841         RTE_FLOW_ITEM_TYPE_TCP,
 842         RTE_FLOW_ITEM_TYPE_VF,
 843         RTE_FLOW_ITEM_TYPE_END,
 844 };
 845
 846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 847         RTE_FLOW_ITEM_TYPE_ETH,
 848         RTE_FLOW_ITEM_TYPE_IPV4,
 849         RTE_FLOW_ITEM_TYPE_SCTP,
 850         RTE_FLOW_ITEM_TYPE_VF,
 851         RTE_FLOW_ITEM_TYPE_END,
 852 };
 853
 854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 855         RTE_FLOW_ITEM_TYPE_ETH,
 856         RTE_FLOW_ITEM_TYPE_IPV6,
 857         RTE_FLOW_ITEM_TYPE_VF,
 858         RTE_FLOW_ITEM_TYPE_END,
 859 };
 860
 861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 862         RTE_FLOW_ITEM_TYPE_ETH,
 863         RTE_FLOW_ITEM_TYPE_IPV6,
 864         RTE_FLOW_ITEM_TYPE_UDP,
 865         RTE_FLOW_ITEM_TYPE_VF,
 866         RTE_FLOW_ITEM_TYPE_END,
 867 };
 868
 869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 870         RTE_FLOW_ITEM_TYPE_ETH,
 871         RTE_FLOW_ITEM_TYPE_IPV6,
 872         RTE_FLOW_ITEM_TYPE_TCP,
 873         RTE_FLOW_ITEM_TYPE_VF,
 874         RTE_FLOW_ITEM_TYPE_END,
 875 };
 876
 877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 878         RTE_FLOW_ITEM_TYPE_ETH,
 879         RTE_FLOW_ITEM_TYPE_IPV6,
 880         RTE_FLOW_ITEM_TYPE_SCTP,
 881         RTE_FLOW_ITEM_TYPE_VF,
 882         RTE_FLOW_ITEM_TYPE_END,
 883 };
 884
 885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 886         RTE_FLOW_ITEM_TYPE_ETH,
 887         RTE_FLOW_ITEM_TYPE_RAW,
 888         RTE_FLOW_ITEM_TYPE_VF,
 889         RTE_FLOW_ITEM_TYPE_END,
 890 };
 891
 892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 893         RTE_FLOW_ITEM_TYPE_ETH,
 894         RTE_FLOW_ITEM_TYPE_RAW,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_VF,
 897         RTE_FLOW_ITEM_TYPE_END,
 898 };
 899
 900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 901         RTE_FLOW_ITEM_TYPE_ETH,
 902         RTE_FLOW_ITEM_TYPE_RAW,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_VF,
 906         RTE_FLOW_ITEM_TYPE_END,
 907 };
 908
 909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 910         RTE_FLOW_ITEM_TYPE_ETH,
 911         RTE_FLOW_ITEM_TYPE_IPV4,
 912         RTE_FLOW_ITEM_TYPE_RAW,
 913         RTE_FLOW_ITEM_TYPE_VF,
 914         RTE_FLOW_ITEM_TYPE_END,
 915 };
 916
 917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 918         RTE_FLOW_ITEM_TYPE_ETH,
 919         RTE_FLOW_ITEM_TYPE_IPV4,
 920         RTE_FLOW_ITEM_TYPE_RAW,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_VF,
 923         RTE_FLOW_ITEM_TYPE_END,
 924 };
 925
 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 927         RTE_FLOW_ITEM_TYPE_ETH,
 928         RTE_FLOW_ITEM_TYPE_IPV4,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_VF,
 933         RTE_FLOW_ITEM_TYPE_END,
 934 };
 935
 936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 937         RTE_FLOW_ITEM_TYPE_ETH,
 938         RTE_FLOW_ITEM_TYPE_IPV4,
 939         RTE_FLOW_ITEM_TYPE_UDP,
 940         RTE_FLOW_ITEM_TYPE_RAW,
 941         RTE_FLOW_ITEM_TYPE_VF,
 942         RTE_FLOW_ITEM_TYPE_END,
 943 };
 944
 945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 946         RTE_FLOW_ITEM_TYPE_ETH,
 947         RTE_FLOW_ITEM_TYPE_IPV4,
 948         RTE_FLOW_ITEM_TYPE_UDP,
 949         RTE_FLOW_ITEM_TYPE_RAW,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_VF,
 952         RTE_FLOW_ITEM_TYPE_END,
 953 };
 954
 955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 956         RTE_FLOW_ITEM_TYPE_ETH,
 957         RTE_FLOW_ITEM_TYPE_IPV4,
 958         RTE_FLOW_ITEM_TYPE_UDP,
 959         RTE_FLOW_ITEM_TYPE_RAW,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_VF,
 963         RTE_FLOW_ITEM_TYPE_END,
 964 };
 965
 966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 967         RTE_FLOW_ITEM_TYPE_ETH,
 968         RTE_FLOW_ITEM_TYPE_IPV4,
 969         RTE_FLOW_ITEM_TYPE_TCP,
 970         RTE_FLOW_ITEM_TYPE_RAW,
 971         RTE_FLOW_ITEM_TYPE_VF,
 972         RTE_FLOW_ITEM_TYPE_END,
 973 };
 974
 975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 976         RTE_FLOW_ITEM_TYPE_ETH,
 977         RTE_FLOW_ITEM_TYPE_IPV4,
 978         RTE_FLOW_ITEM_TYPE_TCP,
 979         RTE_FLOW_ITEM_TYPE_RAW,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_VF,
 982         RTE_FLOW_ITEM_TYPE_END,
 983 };
 984
 985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 986         RTE_FLOW_ITEM_TYPE_ETH,
 987         RTE_FLOW_ITEM_TYPE_IPV4,
 988         RTE_FLOW_ITEM_TYPE_TCP,
 989         RTE_FLOW_ITEM_TYPE_RAW,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_VF,
 993         RTE_FLOW_ITEM_TYPE_END,
 994 };
 995
 996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 997         RTE_FLOW_ITEM_TYPE_ETH,
 998         RTE_FLOW_ITEM_TYPE_IPV4,
 999         RTE_FLOW_ITEM_TYPE_SCTP,
1000         RTE_FLOW_ITEM_TYPE_RAW,
1001         RTE_FLOW_ITEM_TYPE_VF,
1002         RTE_FLOW_ITEM_TYPE_END,
1003 };
1004
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006         RTE_FLOW_ITEM_TYPE_ETH,
1007         RTE_FLOW_ITEM_TYPE_IPV4,
1008         RTE_FLOW_ITEM_TYPE_SCTP,
1009         RTE_FLOW_ITEM_TYPE_RAW,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_VF,
1012         RTE_FLOW_ITEM_TYPE_END,
1013 };
1014
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016         RTE_FLOW_ITEM_TYPE_ETH,
1017         RTE_FLOW_ITEM_TYPE_IPV4,
1018         RTE_FLOW_ITEM_TYPE_SCTP,
1019         RTE_FLOW_ITEM_TYPE_RAW,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_VF,
1023         RTE_FLOW_ITEM_TYPE_END,
1024 };
1025
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027         RTE_FLOW_ITEM_TYPE_ETH,
1028         RTE_FLOW_ITEM_TYPE_IPV6,
1029         RTE_FLOW_ITEM_TYPE_RAW,
1030         RTE_FLOW_ITEM_TYPE_VF,
1031         RTE_FLOW_ITEM_TYPE_END,
1032 };
1033
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035         RTE_FLOW_ITEM_TYPE_ETH,
1036         RTE_FLOW_ITEM_TYPE_IPV6,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_VF,
1040         RTE_FLOW_ITEM_TYPE_END,
1041 };
1042
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044         RTE_FLOW_ITEM_TYPE_ETH,
1045         RTE_FLOW_ITEM_TYPE_IPV6,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_VF,
1050         RTE_FLOW_ITEM_TYPE_END,
1051 };
1052
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054         RTE_FLOW_ITEM_TYPE_ETH,
1055         RTE_FLOW_ITEM_TYPE_IPV6,
1056         RTE_FLOW_ITEM_TYPE_UDP,
1057         RTE_FLOW_ITEM_TYPE_RAW,
1058         RTE_FLOW_ITEM_TYPE_VF,
1059         RTE_FLOW_ITEM_TYPE_END,
1060 };
1061
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063         RTE_FLOW_ITEM_TYPE_ETH,
1064         RTE_FLOW_ITEM_TYPE_IPV6,
1065         RTE_FLOW_ITEM_TYPE_UDP,
1066         RTE_FLOW_ITEM_TYPE_RAW,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_VF,
1069         RTE_FLOW_ITEM_TYPE_END,
1070 };
1071
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073         RTE_FLOW_ITEM_TYPE_ETH,
1074         RTE_FLOW_ITEM_TYPE_IPV6,
1075         RTE_FLOW_ITEM_TYPE_UDP,
1076         RTE_FLOW_ITEM_TYPE_RAW,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_VF,
1080         RTE_FLOW_ITEM_TYPE_END,
1081 };
1082
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084         RTE_FLOW_ITEM_TYPE_ETH,
1085         RTE_FLOW_ITEM_TYPE_IPV6,
1086         RTE_FLOW_ITEM_TYPE_TCP,
1087         RTE_FLOW_ITEM_TYPE_RAW,
1088         RTE_FLOW_ITEM_TYPE_VF,
1089         RTE_FLOW_ITEM_TYPE_END,
1090 };
1091
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093         RTE_FLOW_ITEM_TYPE_ETH,
1094         RTE_FLOW_ITEM_TYPE_IPV6,
1095         RTE_FLOW_ITEM_TYPE_TCP,
1096         RTE_FLOW_ITEM_TYPE_RAW,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_VF,
1099         RTE_FLOW_ITEM_TYPE_END,
1100 };
1101
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103         RTE_FLOW_ITEM_TYPE_ETH,
1104         RTE_FLOW_ITEM_TYPE_IPV6,
1105         RTE_FLOW_ITEM_TYPE_TCP,
1106         RTE_FLOW_ITEM_TYPE_RAW,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_VF,
1110         RTE_FLOW_ITEM_TYPE_END,
1111 };
1112
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114         RTE_FLOW_ITEM_TYPE_ETH,
1115         RTE_FLOW_ITEM_TYPE_IPV6,
1116         RTE_FLOW_ITEM_TYPE_SCTP,
1117         RTE_FLOW_ITEM_TYPE_RAW,
1118         RTE_FLOW_ITEM_TYPE_VF,
1119         RTE_FLOW_ITEM_TYPE_END,
1120 };
1121
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123         RTE_FLOW_ITEM_TYPE_ETH,
1124         RTE_FLOW_ITEM_TYPE_IPV6,
1125         RTE_FLOW_ITEM_TYPE_SCTP,
1126         RTE_FLOW_ITEM_TYPE_RAW,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_VF,
1129         RTE_FLOW_ITEM_TYPE_END,
1130 };
1131
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133         RTE_FLOW_ITEM_TYPE_ETH,
1134         RTE_FLOW_ITEM_TYPE_IPV6,
1135         RTE_FLOW_ITEM_TYPE_SCTP,
1136         RTE_FLOW_ITEM_TYPE_RAW,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_VF,
1140         RTE_FLOW_ITEM_TYPE_END,
1141 };
1142
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144         RTE_FLOW_ITEM_TYPE_ETH,
1145         RTE_FLOW_ITEM_TYPE_VLAN,
1146         RTE_FLOW_ITEM_TYPE_VF,
1147         RTE_FLOW_ITEM_TYPE_END,
1148 };
1149
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151         RTE_FLOW_ITEM_TYPE_ETH,
1152         RTE_FLOW_ITEM_TYPE_VLAN,
1153         RTE_FLOW_ITEM_TYPE_IPV4,
1154         RTE_FLOW_ITEM_TYPE_VF,
1155         RTE_FLOW_ITEM_TYPE_END,
1156 };
1157
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159         RTE_FLOW_ITEM_TYPE_ETH,
1160         RTE_FLOW_ITEM_TYPE_VLAN,
1161         RTE_FLOW_ITEM_TYPE_IPV4,
1162         RTE_FLOW_ITEM_TYPE_UDP,
1163         RTE_FLOW_ITEM_TYPE_VF,
1164         RTE_FLOW_ITEM_TYPE_END,
1165 };
1166
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168         RTE_FLOW_ITEM_TYPE_ETH,
1169         RTE_FLOW_ITEM_TYPE_VLAN,
1170         RTE_FLOW_ITEM_TYPE_IPV4,
1171         RTE_FLOW_ITEM_TYPE_TCP,
1172         RTE_FLOW_ITEM_TYPE_VF,
1173         RTE_FLOW_ITEM_TYPE_END,
1174 };
1175
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177         RTE_FLOW_ITEM_TYPE_ETH,
1178         RTE_FLOW_ITEM_TYPE_VLAN,
1179         RTE_FLOW_ITEM_TYPE_IPV4,
1180         RTE_FLOW_ITEM_TYPE_SCTP,
1181         RTE_FLOW_ITEM_TYPE_VF,
1182         RTE_FLOW_ITEM_TYPE_END,
1183 };
1184
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186         RTE_FLOW_ITEM_TYPE_ETH,
1187         RTE_FLOW_ITEM_TYPE_VLAN,
1188         RTE_FLOW_ITEM_TYPE_IPV6,
1189         RTE_FLOW_ITEM_TYPE_VF,
1190         RTE_FLOW_ITEM_TYPE_END,
1191 };
1192
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194         RTE_FLOW_ITEM_TYPE_ETH,
1195         RTE_FLOW_ITEM_TYPE_VLAN,
1196         RTE_FLOW_ITEM_TYPE_IPV6,
1197         RTE_FLOW_ITEM_TYPE_UDP,
1198         RTE_FLOW_ITEM_TYPE_VF,
1199         RTE_FLOW_ITEM_TYPE_END,
1200 };
1201
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203         RTE_FLOW_ITEM_TYPE_ETH,
1204         RTE_FLOW_ITEM_TYPE_VLAN,
1205         RTE_FLOW_ITEM_TYPE_IPV6,
1206         RTE_FLOW_ITEM_TYPE_TCP,
1207         RTE_FLOW_ITEM_TYPE_VF,
1208         RTE_FLOW_ITEM_TYPE_END,
1209 };
1210
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212         RTE_FLOW_ITEM_TYPE_ETH,
1213         RTE_FLOW_ITEM_TYPE_VLAN,
1214         RTE_FLOW_ITEM_TYPE_IPV6,
1215         RTE_FLOW_ITEM_TYPE_SCTP,
1216         RTE_FLOW_ITEM_TYPE_VF,
1217         RTE_FLOW_ITEM_TYPE_END,
1218 };
1219
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221         RTE_FLOW_ITEM_TYPE_ETH,
1222         RTE_FLOW_ITEM_TYPE_VLAN,
1223         RTE_FLOW_ITEM_TYPE_RAW,
1224         RTE_FLOW_ITEM_TYPE_VF,
1225         RTE_FLOW_ITEM_TYPE_END,
1226 };
1227
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229         RTE_FLOW_ITEM_TYPE_ETH,
1230         RTE_FLOW_ITEM_TYPE_VLAN,
1231         RTE_FLOW_ITEM_TYPE_RAW,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_VF,
1234         RTE_FLOW_ITEM_TYPE_END,
1235 };
1236
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238         RTE_FLOW_ITEM_TYPE_ETH,
1239         RTE_FLOW_ITEM_TYPE_VLAN,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_VF,
1244         RTE_FLOW_ITEM_TYPE_END,
1245 };
1246
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248         RTE_FLOW_ITEM_TYPE_ETH,
1249         RTE_FLOW_ITEM_TYPE_VLAN,
1250         RTE_FLOW_ITEM_TYPE_IPV4,
1251         RTE_FLOW_ITEM_TYPE_RAW,
1252         RTE_FLOW_ITEM_TYPE_VF,
1253         RTE_FLOW_ITEM_TYPE_END,
1254 };
1255
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257         RTE_FLOW_ITEM_TYPE_ETH,
1258         RTE_FLOW_ITEM_TYPE_VLAN,
1259         RTE_FLOW_ITEM_TYPE_IPV4,
1260         RTE_FLOW_ITEM_TYPE_RAW,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_VF,
1263         RTE_FLOW_ITEM_TYPE_END,
1264 };
1265
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267         RTE_FLOW_ITEM_TYPE_ETH,
1268         RTE_FLOW_ITEM_TYPE_VLAN,
1269         RTE_FLOW_ITEM_TYPE_IPV4,
1270         RTE_FLOW_ITEM_TYPE_RAW,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_VF,
1274         RTE_FLOW_ITEM_TYPE_END,
1275 };
1276
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278         RTE_FLOW_ITEM_TYPE_ETH,
1279         RTE_FLOW_ITEM_TYPE_VLAN,
1280         RTE_FLOW_ITEM_TYPE_IPV4,
1281         RTE_FLOW_ITEM_TYPE_UDP,
1282         RTE_FLOW_ITEM_TYPE_RAW,
1283         RTE_FLOW_ITEM_TYPE_VF,
1284         RTE_FLOW_ITEM_TYPE_END,
1285 };
1286
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288         RTE_FLOW_ITEM_TYPE_ETH,
1289         RTE_FLOW_ITEM_TYPE_VLAN,
1290         RTE_FLOW_ITEM_TYPE_IPV4,
1291         RTE_FLOW_ITEM_TYPE_UDP,
1292         RTE_FLOW_ITEM_TYPE_RAW,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_VF,
1295         RTE_FLOW_ITEM_TYPE_END,
1296 };
1297
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299         RTE_FLOW_ITEM_TYPE_ETH,
1300         RTE_FLOW_ITEM_TYPE_VLAN,
1301         RTE_FLOW_ITEM_TYPE_IPV4,
1302         RTE_FLOW_ITEM_TYPE_UDP,
1303         RTE_FLOW_ITEM_TYPE_RAW,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_VF,
1307         RTE_FLOW_ITEM_TYPE_END,
1308 };
1309
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311         RTE_FLOW_ITEM_TYPE_ETH,
1312         RTE_FLOW_ITEM_TYPE_VLAN,
1313         RTE_FLOW_ITEM_TYPE_IPV4,
1314         RTE_FLOW_ITEM_TYPE_TCP,
1315         RTE_FLOW_ITEM_TYPE_RAW,
1316         RTE_FLOW_ITEM_TYPE_VF,
1317         RTE_FLOW_ITEM_TYPE_END,
1318 };
1319
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321         RTE_FLOW_ITEM_TYPE_ETH,
1322         RTE_FLOW_ITEM_TYPE_VLAN,
1323         RTE_FLOW_ITEM_TYPE_IPV4,
1324         RTE_FLOW_ITEM_TYPE_TCP,
1325         RTE_FLOW_ITEM_TYPE_RAW,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_VF,
1328         RTE_FLOW_ITEM_TYPE_END,
1329 };
1330
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332         RTE_FLOW_ITEM_TYPE_ETH,
1333         RTE_FLOW_ITEM_TYPE_VLAN,
1334         RTE_FLOW_ITEM_TYPE_IPV4,
1335         RTE_FLOW_ITEM_TYPE_TCP,
1336         RTE_FLOW_ITEM_TYPE_RAW,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_VF,
1340         RTE_FLOW_ITEM_TYPE_END,
1341 };
1342
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344         RTE_FLOW_ITEM_TYPE_ETH,
1345         RTE_FLOW_ITEM_TYPE_VLAN,
1346         RTE_FLOW_ITEM_TYPE_IPV4,
1347         RTE_FLOW_ITEM_TYPE_SCTP,
1348         RTE_FLOW_ITEM_TYPE_RAW,
1349         RTE_FLOW_ITEM_TYPE_VF,
1350         RTE_FLOW_ITEM_TYPE_END,
1351 };
1352
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354         RTE_FLOW_ITEM_TYPE_ETH,
1355         RTE_FLOW_ITEM_TYPE_VLAN,
1356         RTE_FLOW_ITEM_TYPE_IPV4,
1357         RTE_FLOW_ITEM_TYPE_SCTP,
1358         RTE_FLOW_ITEM_TYPE_RAW,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_VF,
1361         RTE_FLOW_ITEM_TYPE_END,
1362 };
1363
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365         RTE_FLOW_ITEM_TYPE_ETH,
1366         RTE_FLOW_ITEM_TYPE_VLAN,
1367         RTE_FLOW_ITEM_TYPE_IPV4,
1368         RTE_FLOW_ITEM_TYPE_SCTP,
1369         RTE_FLOW_ITEM_TYPE_RAW,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_VF,
1373         RTE_FLOW_ITEM_TYPE_END,
1374 };
1375
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377         RTE_FLOW_ITEM_TYPE_ETH,
1378         RTE_FLOW_ITEM_TYPE_VLAN,
1379         RTE_FLOW_ITEM_TYPE_IPV6,
1380         RTE_FLOW_ITEM_TYPE_RAW,
1381         RTE_FLOW_ITEM_TYPE_VF,
1382         RTE_FLOW_ITEM_TYPE_END,
1383 };
1384
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386         RTE_FLOW_ITEM_TYPE_ETH,
1387         RTE_FLOW_ITEM_TYPE_VLAN,
1388         RTE_FLOW_ITEM_TYPE_IPV6,
1389         RTE_FLOW_ITEM_TYPE_RAW,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_VF,
1392         RTE_FLOW_ITEM_TYPE_END,
1393 };
1394
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396         RTE_FLOW_ITEM_TYPE_ETH,
1397         RTE_FLOW_ITEM_TYPE_VLAN,
1398         RTE_FLOW_ITEM_TYPE_IPV6,
1399         RTE_FLOW_ITEM_TYPE_RAW,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_VF,
1403         RTE_FLOW_ITEM_TYPE_END,
1404 };
1405
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407         RTE_FLOW_ITEM_TYPE_ETH,
1408         RTE_FLOW_ITEM_TYPE_VLAN,
1409         RTE_FLOW_ITEM_TYPE_IPV6,
1410         RTE_FLOW_ITEM_TYPE_UDP,
1411         RTE_FLOW_ITEM_TYPE_RAW,
1412         RTE_FLOW_ITEM_TYPE_VF,
1413         RTE_FLOW_ITEM_TYPE_END,
1414 };
1415
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417         RTE_FLOW_ITEM_TYPE_ETH,
1418         RTE_FLOW_ITEM_TYPE_VLAN,
1419         RTE_FLOW_ITEM_TYPE_IPV6,
1420         RTE_FLOW_ITEM_TYPE_UDP,
1421         RTE_FLOW_ITEM_TYPE_RAW,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_VF,
1424         RTE_FLOW_ITEM_TYPE_END,
1425 };
1426
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428         RTE_FLOW_ITEM_TYPE_ETH,
1429         RTE_FLOW_ITEM_TYPE_VLAN,
1430         RTE_FLOW_ITEM_TYPE_IPV6,
1431         RTE_FLOW_ITEM_TYPE_UDP,
1432         RTE_FLOW_ITEM_TYPE_RAW,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_VF,
1436         RTE_FLOW_ITEM_TYPE_END,
1437 };
1438
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440         RTE_FLOW_ITEM_TYPE_ETH,
1441         RTE_FLOW_ITEM_TYPE_VLAN,
1442         RTE_FLOW_ITEM_TYPE_IPV6,
1443         RTE_FLOW_ITEM_TYPE_TCP,
1444         RTE_FLOW_ITEM_TYPE_RAW,
1445         RTE_FLOW_ITEM_TYPE_VF,
1446         RTE_FLOW_ITEM_TYPE_END,
1447 };
1448
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450         RTE_FLOW_ITEM_TYPE_ETH,
1451         RTE_FLOW_ITEM_TYPE_VLAN,
1452         RTE_FLOW_ITEM_TYPE_IPV6,
1453         RTE_FLOW_ITEM_TYPE_TCP,
1454         RTE_FLOW_ITEM_TYPE_RAW,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_VF,
1457         RTE_FLOW_ITEM_TYPE_END,
1458 };
1459
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461         RTE_FLOW_ITEM_TYPE_ETH,
1462         RTE_FLOW_ITEM_TYPE_VLAN,
1463         RTE_FLOW_ITEM_TYPE_IPV6,
1464         RTE_FLOW_ITEM_TYPE_TCP,
1465         RTE_FLOW_ITEM_TYPE_RAW,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_VF,
1469         RTE_FLOW_ITEM_TYPE_END,
1470 };
1471
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473         RTE_FLOW_ITEM_TYPE_ETH,
1474         RTE_FLOW_ITEM_TYPE_VLAN,
1475         RTE_FLOW_ITEM_TYPE_IPV6,
1476         RTE_FLOW_ITEM_TYPE_SCTP,
1477         RTE_FLOW_ITEM_TYPE_RAW,
1478         RTE_FLOW_ITEM_TYPE_VF,
1479         RTE_FLOW_ITEM_TYPE_END,
1480 };
1481
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483         RTE_FLOW_ITEM_TYPE_ETH,
1484         RTE_FLOW_ITEM_TYPE_VLAN,
1485         RTE_FLOW_ITEM_TYPE_IPV6,
1486         RTE_FLOW_ITEM_TYPE_SCTP,
1487         RTE_FLOW_ITEM_TYPE_RAW,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_VF,
1490         RTE_FLOW_ITEM_TYPE_END,
1491 };
1492
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494         RTE_FLOW_ITEM_TYPE_ETH,
1495         RTE_FLOW_ITEM_TYPE_VLAN,
1496         RTE_FLOW_ITEM_TYPE_IPV6,
1497         RTE_FLOW_ITEM_TYPE_SCTP,
1498         RTE_FLOW_ITEM_TYPE_RAW,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_VF,
1502         RTE_FLOW_ITEM_TYPE_END,
1503 };
1504
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507         RTE_FLOW_ITEM_TYPE_ETH,
1508         RTE_FLOW_ITEM_TYPE_IPV4,
1509         RTE_FLOW_ITEM_TYPE_UDP,
1510         RTE_FLOW_ITEM_TYPE_VXLAN,
1511         RTE_FLOW_ITEM_TYPE_ETH,
1512         RTE_FLOW_ITEM_TYPE_END,
1513 };
1514
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516         RTE_FLOW_ITEM_TYPE_ETH,
1517         RTE_FLOW_ITEM_TYPE_IPV6,
1518         RTE_FLOW_ITEM_TYPE_UDP,
1519         RTE_FLOW_ITEM_TYPE_VXLAN,
1520         RTE_FLOW_ITEM_TYPE_ETH,
1521         RTE_FLOW_ITEM_TYPE_END,
1522 };
1523
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525         RTE_FLOW_ITEM_TYPE_ETH,
1526         RTE_FLOW_ITEM_TYPE_IPV4,
1527         RTE_FLOW_ITEM_TYPE_UDP,
1528         RTE_FLOW_ITEM_TYPE_VXLAN,
1529         RTE_FLOW_ITEM_TYPE_ETH,
1530         RTE_FLOW_ITEM_TYPE_VLAN,
1531         RTE_FLOW_ITEM_TYPE_END,
1532 };
1533
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535         RTE_FLOW_ITEM_TYPE_ETH,
1536         RTE_FLOW_ITEM_TYPE_IPV6,
1537         RTE_FLOW_ITEM_TYPE_UDP,
1538         RTE_FLOW_ITEM_TYPE_VXLAN,
1539         RTE_FLOW_ITEM_TYPE_ETH,
1540         RTE_FLOW_ITEM_TYPE_VLAN,
1541         RTE_FLOW_ITEM_TYPE_END,
1542 };
1543
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545         RTE_FLOW_ITEM_TYPE_ETH,
1546         RTE_FLOW_ITEM_TYPE_IPV4,
1547         RTE_FLOW_ITEM_TYPE_NVGRE,
1548         RTE_FLOW_ITEM_TYPE_ETH,
1549         RTE_FLOW_ITEM_TYPE_END,
1550 };
1551
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553         RTE_FLOW_ITEM_TYPE_ETH,
1554         RTE_FLOW_ITEM_TYPE_IPV6,
1555         RTE_FLOW_ITEM_TYPE_NVGRE,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_END,
1558 };
1559
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561         RTE_FLOW_ITEM_TYPE_ETH,
1562         RTE_FLOW_ITEM_TYPE_IPV4,
1563         RTE_FLOW_ITEM_TYPE_NVGRE,
1564         RTE_FLOW_ITEM_TYPE_ETH,
1565         RTE_FLOW_ITEM_TYPE_VLAN,
1566         RTE_FLOW_ITEM_TYPE_END,
1567 };
1568
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570         RTE_FLOW_ITEM_TYPE_ETH,
1571         RTE_FLOW_ITEM_TYPE_IPV6,
1572         RTE_FLOW_ITEM_TYPE_NVGRE,
1573         RTE_FLOW_ITEM_TYPE_ETH,
1574         RTE_FLOW_ITEM_TYPE_VLAN,
1575         RTE_FLOW_ITEM_TYPE_END,
1576 };
1577
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579         RTE_FLOW_ITEM_TYPE_ETH,
1580         RTE_FLOW_ITEM_TYPE_IPV4,
1581         RTE_FLOW_ITEM_TYPE_UDP,
1582         RTE_FLOW_ITEM_TYPE_MPLS,
1583         RTE_FLOW_ITEM_TYPE_END,
1584 };
1585
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587         RTE_FLOW_ITEM_TYPE_ETH,
1588         RTE_FLOW_ITEM_TYPE_IPV6,
1589         RTE_FLOW_ITEM_TYPE_UDP,
1590         RTE_FLOW_ITEM_TYPE_MPLS,
1591         RTE_FLOW_ITEM_TYPE_END,
1592 };
1593
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595         RTE_FLOW_ITEM_TYPE_ETH,
1596         RTE_FLOW_ITEM_TYPE_IPV4,
1597         RTE_FLOW_ITEM_TYPE_GRE,
1598         RTE_FLOW_ITEM_TYPE_MPLS,
1599         RTE_FLOW_ITEM_TYPE_END,
1600 };
1601
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603         RTE_FLOW_ITEM_TYPE_ETH,
1604         RTE_FLOW_ITEM_TYPE_IPV6,
1605         RTE_FLOW_ITEM_TYPE_GRE,
1606         RTE_FLOW_ITEM_TYPE_MPLS,
1607         RTE_FLOW_ITEM_TYPE_END,
1608 };
1609
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611         RTE_FLOW_ITEM_TYPE_ETH,
1612         RTE_FLOW_ITEM_TYPE_VLAN,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_END,
1615 };
1616
1617 static enum rte_flow_item_type pattern_fdir_ipv4_l2tpv3oip[] = {
1618         RTE_FLOW_ITEM_TYPE_ETH,
1619         RTE_FLOW_ITEM_TYPE_IPV4,
1620         RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1621         RTE_FLOW_ITEM_TYPE_END,
1622 };
1623
1624 static enum rte_flow_item_type pattern_fdir_ipv6_l2tpv3oip[] = {
1625         RTE_FLOW_ITEM_TYPE_ETH,
1626         RTE_FLOW_ITEM_TYPE_IPV6,
1627         RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1628         RTE_FLOW_ITEM_TYPE_END,
1629 };
1630
1631 static enum rte_flow_item_type pattern_fdir_ipv4_esp[] = {
1632         RTE_FLOW_ITEM_TYPE_ETH,
1633         RTE_FLOW_ITEM_TYPE_IPV4,
1634         RTE_FLOW_ITEM_TYPE_ESP,
1635         RTE_FLOW_ITEM_TYPE_END,
1636 };
1637
1638 static enum rte_flow_item_type pattern_fdir_ipv6_esp[] = {
1639         RTE_FLOW_ITEM_TYPE_ETH,
1640         RTE_FLOW_ITEM_TYPE_IPV6,
1641         RTE_FLOW_ITEM_TYPE_ESP,
1642         RTE_FLOW_ITEM_TYPE_END,
1643 };
1644
1645 static enum rte_flow_item_type pattern_fdir_ipv4_udp_esp[] = {
1646         RTE_FLOW_ITEM_TYPE_ETH,
1647         RTE_FLOW_ITEM_TYPE_IPV4,
1648         RTE_FLOW_ITEM_TYPE_UDP,
1649         RTE_FLOW_ITEM_TYPE_ESP,
1650         RTE_FLOW_ITEM_TYPE_END,
1651 };
1652
1653 static enum rte_flow_item_type pattern_fdir_ipv6_udp_esp[] = {
1654         RTE_FLOW_ITEM_TYPE_ETH,
1655         RTE_FLOW_ITEM_TYPE_IPV6,
1656         RTE_FLOW_ITEM_TYPE_UDP,
1657         RTE_FLOW_ITEM_TYPE_ESP,
1658         RTE_FLOW_ITEM_TYPE_END,
1659 };
1660
1661 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1662         /* Ethertype */
1663         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1664         /* FDIR - support default flow type without flexible payload*/
1665         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1667         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_ipv4_esp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_ipv4_udp_esp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_ipv6_esp, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_ipv6_udp_esp, i40e_flow_parse_fdir_filter },
1686         /* FDIR - support default flow type with flexible payload */
1687         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1704         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1714         /* FDIR - support single vlan input set */
1715         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1751         /* FDIR - support VF item */
1752         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1776         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1777         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1778         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1779         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1780         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1781         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1782         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1783         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1784         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1785         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1786         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1787         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1788         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1789         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1790         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1791         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1792         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1793         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1794         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1795         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1796         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1797         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1798         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1799         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1800         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1801         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1802         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1803         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1804         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1805         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1806         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1807         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1808         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1809         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1810         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1811         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1812         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1813         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1814         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1815         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1816         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1817         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1818         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1819         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1820         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1821         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1822         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1823         /* VXLAN */
1824         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1825         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1826         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1827         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1828         /* NVGRE */
1829         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1830         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1831         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1832         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1833         /* MPLSoUDP & MPLSoGRE */
1834         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1835         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1836         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1837         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1838         /* GTP-C & GTP-U */
1839         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1840         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1841         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1842         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1843         /* QINQ */
1844         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1845         /* L2TPv3 over IP */
1846         { pattern_fdir_ipv4_l2tpv3oip, i40e_flow_parse_fdir_filter },
1847         { pattern_fdir_ipv6_l2tpv3oip, i40e_flow_parse_fdir_filter },
1848 };
1849
1850 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1851         do {                                                            \
1852                 act = actions + index;                                  \
1853                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1854                         index++;                                        \
1855                         act = actions + index;                          \
1856                 }                                                       \
1857         } while (0)
1858
1859 /* Find the first VOID or non-VOID item pointer */
1860 static const struct rte_flow_item *
1861 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1862 {
1863         bool is_find;
1864
1865         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1866                 if (is_void)
1867                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1868                 else
1869                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1870                 if (is_find)
1871                         break;
1872                 item++;
1873         }
1874         return item;
1875 }
1876
1877 /* Skip all VOID items of the pattern */
1878 static void
1879 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1880                             const struct rte_flow_item *pattern)
1881 {
1882         uint32_t cpy_count = 0;
1883         const struct rte_flow_item *pb = pattern, *pe = pattern;
1884
1885         for (;;) {
1886                 /* Find a non-void item first */
1887                 pb = i40e_find_first_item(pb, false);
1888                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1889                         pe = pb;
1890                         break;
1891                 }
1892
1893                 /* Find a void item */
1894                 pe = i40e_find_first_item(pb + 1, true);
1895
1896                 cpy_count = pe - pb;
1897                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1898
1899                 items += cpy_count;
1900
1901                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1902                         pb = pe;
1903                         break;
1904                 }
1905
1906                 pb = pe + 1;
1907         }
1908         /* Copy the END item. */
1909         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1910 }
1911
1912 /* Check if the pattern matches a supported item type array */
1913 static bool
1914 i40e_match_pattern(enum rte_flow_item_type *item_array,
1915                    struct rte_flow_item *pattern)
1916 {
1917         struct rte_flow_item *item = pattern;
1918
1919         while ((*item_array == item->type) &&
1920                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1921                 item_array++;
1922                 item++;
1923         }
1924
1925         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1926                 item->type == RTE_FLOW_ITEM_TYPE_END);
1927 }
1928
1929 /* Find if there's parse filter function matched */
1930 static parse_filter_t
1931 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1932 {
1933         parse_filter_t parse_filter = NULL;
1934         uint8_t i = *idx;
1935
1936         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1937                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1938                                         pattern)) {
1939                         parse_filter = i40e_supported_patterns[i].parse_filter;
1940                         break;
1941                 }
1942         }
1943
1944         *idx = ++i;
1945
1946         return parse_filter;
1947 }
1948
1949 /* Parse attributes */
1950 static int
1951 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1952                      struct rte_flow_error *error)
1953 {
1954         /* Must be input direction */
1955         if (!attr->ingress) {
1956                 rte_flow_error_set(error, EINVAL,
1957                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1958                                    attr, "Only support ingress.");
1959                 return -rte_errno;
1960         }
1961
1962         /* Not supported */
1963         if (attr->egress) {
1964                 rte_flow_error_set(error, EINVAL,
1965                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1966                                    attr, "Not support egress.");
1967                 return -rte_errno;
1968         }
1969
1970         /* Not supported */
1971         if (attr->priority) {
1972                 rte_flow_error_set(error, EINVAL,
1973                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1974                                    attr, "Not support priority.");
1975                 return -rte_errno;
1976         }
1977
1978         /* Not supported */
1979         if (attr->group) {
1980                 rte_flow_error_set(error, EINVAL,
1981                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1982                                    attr, "Not support group.");
1983                 return -rte_errno;
1984         }
1985
1986         return 0;
1987 }
1988
1989 static uint16_t
1990 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1991 {
1992         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         int qinq = dev->data->dev_conf.rxmode.offloads &
1994                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1995         uint64_t reg_r = 0;
1996         uint16_t reg_id;
1997         uint16_t tpid;
1998
1999         if (qinq)
2000                 reg_id = 2;
2001         else
2002                 reg_id = 3;
2003
2004         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2005                                     &reg_r, NULL);
2006
2007         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
2008
2009         return tpid;
2010 }
2011
2012 /* 1. Last in item should be NULL as range is not supported.
2013  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
2014  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
2015  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
2016  *    FF:FF:FF:FF:FF:FF
2017  * 5. Ether_type mask should be 0xFFFF.
2018  */
2019 static int
2020 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
2021                                   const struct rte_flow_item *pattern,
2022                                   struct rte_flow_error *error,
2023                                   struct rte_eth_ethertype_filter *filter)
2024 {
2025         const struct rte_flow_item *item = pattern;
2026         const struct rte_flow_item_eth *eth_spec;
2027         const struct rte_flow_item_eth *eth_mask;
2028         enum rte_flow_item_type item_type;
2029         uint16_t outer_tpid;
2030
2031         outer_tpid = i40e_get_outer_vlan(dev);
2032
2033         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2034                 if (item->last) {
2035                         rte_flow_error_set(error, EINVAL,
2036                                            RTE_FLOW_ERROR_TYPE_ITEM,
2037                                            item,
2038                                            "Not support range");
2039                         return -rte_errno;
2040                 }
2041                 item_type = item->type;
2042                 switch (item_type) {
2043                 case RTE_FLOW_ITEM_TYPE_ETH:
2044                         eth_spec = item->spec;
2045                         eth_mask = item->mask;
2046                         /* Get the MAC info. */
2047                         if (!eth_spec || !eth_mask) {
2048                                 rte_flow_error_set(error, EINVAL,
2049                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2050                                                    item,
2051                                                    "NULL ETH spec/mask");
2052                                 return -rte_errno;
2053                         }
2054
2055                         /* Mask bits of source MAC address must be full of 0.
2056                          * Mask bits of destination MAC address must be full
2057                          * of 1 or full of 0.
2058                          */
2059                         if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2060                             (!rte_is_zero_ether_addr(&eth_mask->dst) &&
2061                              !rte_is_broadcast_ether_addr(&eth_mask->dst))) {
2062                                 rte_flow_error_set(error, EINVAL,
2063                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2064                                                    item,
2065                                                    "Invalid MAC_addr mask");
2066                                 return -rte_errno;
2067                         }
2068
2069                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2070                                 rte_flow_error_set(error, EINVAL,
2071                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2072                                                    item,
2073                                                    "Invalid ethertype mask");
2074                                 return -rte_errno;
2075                         }
2076
2077                         /* If mask bits of destination MAC address
2078                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2079                          */
2080                         if (rte_is_broadcast_ether_addr(&eth_mask->dst)) {
2081                                 filter->mac_addr = eth_spec->dst;
2082                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2083                         } else {
2084                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2085                         }
2086                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2087
2088                         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2089                             filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2090                             filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2091                             filter->ether_type == outer_tpid) {
2092                                 rte_flow_error_set(error, EINVAL,
2093                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2094                                                    item,
2095                                                    "Unsupported ether_type in"
2096                                                    " control packet filter.");
2097                                 return -rte_errno;
2098                         }
2099                         break;
2100                 default:
2101                         break;
2102                 }
2103         }
2104
2105         return 0;
2106 }
2107
2108 /* Ethertype action only supports QUEUE or DROP. */
2109 static int
2110 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2111                                  const struct rte_flow_action *actions,
2112                                  struct rte_flow_error *error,
2113                                  struct rte_eth_ethertype_filter *filter)
2114 {
2115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116         const struct rte_flow_action *act;
2117         const struct rte_flow_action_queue *act_q;
2118         uint32_t index = 0;
2119
2120         /* Check if the first non-void action is QUEUE or DROP. */
2121         NEXT_ITEM_OF_ACTION(act, actions, index);
2122         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2123             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2124                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2125                                    act, "Not supported action.");
2126                 return -rte_errno;
2127         }
2128
2129         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2130                 act_q = act->conf;
2131                 filter->queue = act_q->index;
2132                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2133                         rte_flow_error_set(error, EINVAL,
2134                                            RTE_FLOW_ERROR_TYPE_ACTION,
2135                                            act, "Invalid queue ID for"
2136                                            " ethertype_filter.");
2137                         return -rte_errno;
2138                 }
2139         } else {
2140                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2141         }
2142
2143         /* Check if the next non-void item is END */
2144         index++;
2145         NEXT_ITEM_OF_ACTION(act, actions, index);
2146         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2147                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2148                                    act, "Not supported action.");
2149                 return -rte_errno;
2150         }
2151
2152         return 0;
2153 }
2154
2155 static int
2156 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2157                                  const struct rte_flow_attr *attr,
2158                                  const struct rte_flow_item pattern[],
2159                                  const struct rte_flow_action actions[],
2160                                  struct rte_flow_error *error,
2161                                  union i40e_filter_t *filter)
2162 {
2163         struct rte_eth_ethertype_filter *ethertype_filter =
2164                 &filter->ethertype_filter;
2165         int ret;
2166
2167         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2168                                                 ethertype_filter);
2169         if (ret)
2170                 return ret;
2171
2172         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2173                                                ethertype_filter);
2174         if (ret)
2175                 return ret;
2176
2177         ret = i40e_flow_parse_attr(attr, error);
2178         if (ret)
2179                 return ret;
2180
2181         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2182
2183         return ret;
2184 }
2185
2186 static int
2187 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2188                          const struct rte_flow_item_raw *raw_spec,
2189                          struct rte_flow_error *error)
2190 {
2191         if (!raw_spec->relative) {
2192                 rte_flow_error_set(error, EINVAL,
2193                                    RTE_FLOW_ERROR_TYPE_ITEM,
2194                                    item,
2195                                    "Relative should be 1.");
2196                 return -rte_errno;
2197         }
2198
2199         if (raw_spec->offset % sizeof(uint16_t)) {
2200                 rte_flow_error_set(error, EINVAL,
2201                                    RTE_FLOW_ERROR_TYPE_ITEM,
2202                                    item,
2203                                    "Offset should be even.");
2204                 return -rte_errno;
2205         }
2206
2207         if (raw_spec->search || raw_spec->limit) {
2208                 rte_flow_error_set(error, EINVAL,
2209                                    RTE_FLOW_ERROR_TYPE_ITEM,
2210                                    item,
2211                                    "search or limit is not supported.");
2212                 return -rte_errno;
2213         }
2214
2215         if (raw_spec->offset < 0) {
2216                 rte_flow_error_set(error, EINVAL,
2217                                    RTE_FLOW_ERROR_TYPE_ITEM,
2218                                    item,
2219                                    "Offset should be non-negative.");
2220                 return -rte_errno;
2221         }
2222         return 0;
2223 }
2224
2225 static int
2226 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2227                          struct i40e_fdir_flex_pit *flex_pit,
2228                          enum i40e_flxpld_layer_idx layer_idx,
2229                          uint8_t raw_id)
2230 {
2231         uint8_t field_idx;
2232
2233         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2234         /* Check if the configuration is conflicted */
2235         if (pf->fdir.flex_pit_flag[layer_idx] &&
2236             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2237              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2238              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2239                 return -1;
2240
2241         /* Check if the configuration exists. */
2242         if (pf->fdir.flex_pit_flag[layer_idx] &&
2243             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2244              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2245              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2246                 return 1;
2247
2248         pf->fdir.flex_set[field_idx].src_offset =
2249                 flex_pit->src_offset;
2250         pf->fdir.flex_set[field_idx].size =
2251                 flex_pit->size;
2252         pf->fdir.flex_set[field_idx].dst_offset =
2253                 flex_pit->dst_offset;
2254
2255         return 0;
2256 }
2257
2258 static int
2259 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2260                           enum i40e_filter_pctype pctype,
2261                           uint8_t *mask)
2262 {
2263         struct i40e_fdir_flex_mask flex_mask;
2264         uint16_t mask_tmp;
2265         uint8_t i, nb_bitmask = 0;
2266
2267         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2268         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2269                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2270                 if (mask_tmp) {
2271                         flex_mask.word_mask |=
2272                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2273                         if (mask_tmp != UINT16_MAX) {
2274                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2275                                 flex_mask.bitmask[nb_bitmask].offset =
2276                                         i / sizeof(uint16_t);
2277                                 nb_bitmask++;
2278                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2279                                         return -1;
2280                         }
2281                 }
2282         }
2283         flex_mask.nb_bitmask = nb_bitmask;
2284
2285         if (pf->fdir.flex_mask_flag[pctype] &&
2286             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2287                     sizeof(struct i40e_fdir_flex_mask))))
2288                 return -2;
2289         else if (pf->fdir.flex_mask_flag[pctype] &&
2290                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2291                           sizeof(struct i40e_fdir_flex_mask))))
2292                 return 1;
2293
2294         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2295                sizeof(struct i40e_fdir_flex_mask));
2296         return 0;
2297 }
2298
2299 static void
2300 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2301                             enum i40e_flxpld_layer_idx layer_idx,
2302                             uint8_t raw_id)
2303 {
2304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2305         uint32_t flx_pit, flx_ort;
2306         uint8_t field_idx;
2307         uint16_t min_next_off = 0;  /* in words */
2308         uint8_t i;
2309
2310         if (raw_id) {
2311                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2312                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2313                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2314                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2315         }
2316
2317         /* Set flex pit */
2318         for (i = 0; i < raw_id; i++) {
2319                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2320                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2321                                      pf->fdir.flex_set[field_idx].size,
2322                                      pf->fdir.flex_set[field_idx].dst_offset);
2323
2324                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2325                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2326                         pf->fdir.flex_set[field_idx].size;
2327         }
2328
2329         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2330                 /* set the non-used register obeying register's constrain */
2331                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2332                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2333                                      NONUSE_FLX_PIT_DEST_OFF);
2334                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2335                 min_next_off++;
2336         }
2337
2338         pf->fdir.flex_pit_flag[layer_idx] = 1;
2339 }
2340
2341 static void
2342 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2343                             enum i40e_filter_pctype pctype)
2344 {
2345         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2346         struct i40e_fdir_flex_mask *flex_mask;
2347         uint32_t flxinset, fd_mask;
2348         uint8_t i;
2349
2350         /* Set flex mask */
2351         flex_mask = &pf->fdir.flex_mask[pctype];
2352         flxinset = (flex_mask->word_mask <<
2353                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2354                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2355         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2356
2357         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2358                 fd_mask = (flex_mask->bitmask[i].mask <<
2359                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2360                         I40E_PRTQF_FD_MSK_MASK_MASK;
2361                 fd_mask |= ((flex_mask->bitmask[i].offset +
2362                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2363                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2364                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2365                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2366         }
2367
2368         pf->fdir.flex_mask_flag[pctype] = 1;
2369 }
2370
2371 static int
2372 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2373                          enum i40e_filter_pctype pctype,
2374                          uint64_t input_set)
2375 {
2376         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2377         uint64_t inset_reg = 0;
2378         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2379         int i, num;
2380
2381         /* Check if the input set is valid */
2382         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2383                                     input_set) != 0) {
2384                 PMD_DRV_LOG(ERR, "Invalid input set");
2385                 return -EINVAL;
2386         }
2387
2388         /* Check if the configuration is conflicted */
2389         if (pf->fdir.inset_flag[pctype] &&
2390             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2391                 return -1;
2392
2393         if (pf->fdir.inset_flag[pctype] &&
2394             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2395                 return 0;
2396
2397         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2398                                            I40E_INSET_MASK_NUM_REG);
2399         if (num < 0)
2400                 return -EINVAL;
2401
2402         if (pf->support_multi_driver) {
2403                 for (i = 0; i < num; i++)
2404                         if (i40e_read_rx_ctl(hw,
2405                                         I40E_GLQF_FD_MSK(i, pctype)) !=
2406                                         mask_reg[i]) {
2407                                 PMD_DRV_LOG(ERR, "Input set setting is not"
2408                                                 " supported with"
2409                                                 " `support-multi-driver`"
2410                                                 " enabled!");
2411                                 return -EPERM;
2412                         }
2413                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2414                         if (i40e_read_rx_ctl(hw,
2415                                         I40E_GLQF_FD_MSK(i, pctype)) != 0) {
2416                                 PMD_DRV_LOG(ERR, "Input set setting is not"
2417                                                 " supported with"
2418                                                 " `support-multi-driver`"
2419                                                 " enabled!");
2420                                 return -EPERM;
2421                         }
2422
2423         } else {
2424                 for (i = 0; i < num; i++)
2425                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2426                                 mask_reg[i]);
2427                 /*clear unused mask registers of the pctype */
2428                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2429                         i40e_check_write_reg(hw,
2430                                         I40E_GLQF_FD_MSK(i, pctype), 0);
2431         }
2432
2433         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2434
2435         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2436                              (uint32_t)(inset_reg & UINT32_MAX));
2437         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2438                              (uint32_t)((inset_reg >>
2439                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2440
2441         I40E_WRITE_FLUSH(hw);
2442
2443         pf->fdir.input_set[pctype] = input_set;
2444         pf->fdir.inset_flag[pctype] = 1;
2445         return 0;
2446 }
2447
2448 static uint8_t
2449 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2450                                 enum rte_flow_item_type item_type,
2451                                 struct i40e_fdir_filter_conf *filter)
2452 {
2453         struct i40e_customized_pctype *cus_pctype = NULL;
2454
2455         switch (item_type) {
2456         case RTE_FLOW_ITEM_TYPE_GTPC:
2457                 cus_pctype = i40e_find_customized_pctype(pf,
2458                                                          I40E_CUSTOMIZED_GTPC);
2459                 break;
2460         case RTE_FLOW_ITEM_TYPE_GTPU:
2461                 if (!filter->input.flow_ext.inner_ip)
2462                         cus_pctype = i40e_find_customized_pctype(pf,
2463                                                          I40E_CUSTOMIZED_GTPU);
2464                 else if (filter->input.flow_ext.iip_type ==
2465                          I40E_FDIR_IPTYPE_IPV4)
2466                         cus_pctype = i40e_find_customized_pctype(pf,
2467                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2468                 else if (filter->input.flow_ext.iip_type ==
2469                          I40E_FDIR_IPTYPE_IPV6)
2470                         cus_pctype = i40e_find_customized_pctype(pf,
2471                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2472                 break;
2473         case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
2474                 if (filter->input.flow_ext.oip_type == I40E_FDIR_IPTYPE_IPV4)
2475                         cus_pctype = i40e_find_customized_pctype(pf,
2476                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
2477                 else if (filter->input.flow_ext.oip_type ==
2478                          I40E_FDIR_IPTYPE_IPV6)
2479                         cus_pctype = i40e_find_customized_pctype(pf,
2480                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
2481                 break;
2482         case RTE_FLOW_ITEM_TYPE_ESP:
2483                 if (!filter->input.flow_ext.is_udp) {
2484                         if (filter->input.flow_ext.oip_type ==
2485                                 I40E_FDIR_IPTYPE_IPV4)
2486                                 cus_pctype = i40e_find_customized_pctype(pf,
2487                                                 I40E_CUSTOMIZED_ESP_IPV4);
2488                         else if (filter->input.flow_ext.oip_type ==
2489                                 I40E_FDIR_IPTYPE_IPV6)
2490                                 cus_pctype = i40e_find_customized_pctype(pf,
2491                                                 I40E_CUSTOMIZED_ESP_IPV6);
2492                 } else {
2493                         if (filter->input.flow_ext.oip_type ==
2494                                 I40E_FDIR_IPTYPE_IPV4)
2495                                 cus_pctype = i40e_find_customized_pctype(pf,
2496                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
2497                         else if (filter->input.flow_ext.oip_type ==
2498                                         I40E_FDIR_IPTYPE_IPV6)
2499                                 cus_pctype = i40e_find_customized_pctype(pf,
2500                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
2501                         filter->input.flow_ext.is_udp = false;
2502                 }
2503                 break;
2504         default:
2505                 PMD_DRV_LOG(ERR, "Unsupported item type");
2506                 break;
2507         }
2508
2509         if (cus_pctype && cus_pctype->valid)
2510                 return cus_pctype->pctype;
2511
2512         return I40E_FILTER_PCTYPE_INVALID;
2513 }
2514
2515 static void
2516 i40e_flow_set_filter_spi(struct i40e_fdir_filter_conf *filter,
2517         const struct rte_flow_item_esp *esp_spec)
2518 {
2519         if (filter->input.flow_ext.oip_type ==
2520                 I40E_FDIR_IPTYPE_IPV4) {
2521                 if (filter->input.flow_ext.is_udp)
2522                         filter->input.flow.esp_ipv4_udp_flow.spi =
2523                                 esp_spec->hdr.spi;
2524                 else
2525                         filter->input.flow.esp_ipv4_flow.spi =
2526                                 esp_spec->hdr.spi;
2527         }
2528         if (filter->input.flow_ext.oip_type ==
2529                 I40E_FDIR_IPTYPE_IPV6) {
2530                 if (filter->input.flow_ext.is_udp)
2531                         filter->input.flow.esp_ipv6_udp_flow.spi =
2532                                 esp_spec->hdr.spi;
2533                 else
2534                         filter->input.flow.esp_ipv6_flow.spi =
2535                                 esp_spec->hdr.spi;
2536         }
2537 }
2538
2539 /* 1. Last in item should be NULL as range is not supported.
2540  * 2. Supported patterns: refer to array i40e_supported_patterns.
2541  * 3. Default supported flow type and input set: refer to array
2542  *    valid_fdir_inset_table in i40e_ethdev.c.
2543  * 4. Mask of fields which need to be matched should be
2544  *    filled with 1.
2545  * 5. Mask of fields which needn't to be matched should be
2546  *    filled with 0.
2547  * 6. GTP profile supports GTPv1 only.
2548  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2549  */
2550 static int
2551 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2552                              const struct rte_flow_attr *attr,
2553                              const struct rte_flow_item *pattern,
2554                              struct rte_flow_error *error,
2555                              struct i40e_fdir_filter_conf *filter)
2556 {
2557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2558         const struct rte_flow_item *item = pattern;
2559         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2560         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2561         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2562         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2563         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2564         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2565         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2566         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2567         const struct rte_flow_item_esp *esp_spec, *esp_mask;
2568         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2569         const struct rte_flow_item_vf *vf_spec;
2570         const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
2571
2572         uint8_t pctype = 0;
2573         uint64_t input_set = I40E_INSET_NONE;
2574         uint16_t frag_off;
2575         enum rte_flow_item_type item_type;
2576         enum rte_flow_item_type next_type;
2577         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2578         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2579         uint32_t i, j;
2580         uint8_t  ipv6_addr_mask[16] = {
2581                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2582                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2583         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2584         uint8_t raw_id = 0;
2585         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2586         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2587         struct i40e_fdir_flex_pit flex_pit;
2588         uint8_t next_dst_off = 0;
2589         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2590         uint16_t flex_size;
2591         bool cfg_flex_pit = true;
2592         bool cfg_flex_msk = true;
2593         uint16_t outer_tpid;
2594         uint16_t ether_type;
2595         uint32_t vtc_flow_cpu;
2596         bool outer_ip = true;
2597         int ret;
2598
2599         memset(off_arr, 0, sizeof(off_arr));
2600         memset(len_arr, 0, sizeof(len_arr));
2601         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2602         outer_tpid = i40e_get_outer_vlan(dev);
2603         filter->input.flow_ext.customized_pctype = false;
2604         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2605                 if (item->last) {
2606                         rte_flow_error_set(error, EINVAL,
2607                                            RTE_FLOW_ERROR_TYPE_ITEM,
2608                                            item,
2609                                            "Not support range");
2610                         return -rte_errno;
2611                 }
2612                 item_type = item->type;
2613                 switch (item_type) {
2614                 case RTE_FLOW_ITEM_TYPE_ETH:
2615                         eth_spec = item->spec;
2616                         eth_mask = item->mask;
2617                         next_type = (item + 1)->type;
2618
2619                         if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2620                                                 (!eth_spec || !eth_mask)) {
2621                                 rte_flow_error_set(error, EINVAL,
2622                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2623                                                    item,
2624                                                    "NULL eth spec/mask.");
2625                                 return -rte_errno;
2626                         }
2627
2628                         if (eth_spec && eth_mask) {
2629                                 if (rte_is_broadcast_ether_addr(&eth_mask->dst) &&
2630                                         rte_is_zero_ether_addr(&eth_mask->src)) {
2631                                         filter->input.flow.l2_flow.dst =
2632                                                 eth_spec->dst;
2633                                         input_set |= I40E_INSET_DMAC;
2634                                 } else if (rte_is_zero_ether_addr(&eth_mask->dst) &&
2635                                         rte_is_broadcast_ether_addr(&eth_mask->src)) {
2636                                         filter->input.flow.l2_flow.src =
2637                                                 eth_spec->src;
2638                                         input_set |= I40E_INSET_SMAC;
2639                                 } else if (rte_is_broadcast_ether_addr(&eth_mask->dst) &&
2640                                         rte_is_broadcast_ether_addr(&eth_mask->src)) {
2641                                         filter->input.flow.l2_flow.dst =
2642                                                 eth_spec->dst;
2643                                         filter->input.flow.l2_flow.src =
2644                                                 eth_spec->src;
2645                                         input_set |= (I40E_INSET_DMAC | I40E_INSET_SMAC);
2646                                 } else {
2647                                         rte_flow_error_set(error, EINVAL,
2648                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2649                                                       item,
2650                                                       "Invalid MAC_addr mask.");
2651                                         return -rte_errno;
2652                                 }
2653                         }
2654                         if (eth_spec && eth_mask &&
2655                         next_type == RTE_FLOW_ITEM_TYPE_END) {
2656                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2657                                         rte_flow_error_set(error, EINVAL,
2658                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2659                                                       item,
2660                                                       "Invalid type mask.");
2661                                         return -rte_errno;
2662                                 }
2663
2664                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2665
2666                                 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2667                                     ether_type == RTE_ETHER_TYPE_IPV4 ||
2668                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2669                                     ether_type == outer_tpid) {
2670                                         rte_flow_error_set(error, EINVAL,
2671                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2672                                                      item,
2673                                                      "Unsupported ether_type.");
2674                                         return -rte_errno;
2675                                 }
2676                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2677                                 filter->input.flow.l2_flow.ether_type =
2678                                         eth_spec->type;
2679                         }
2680
2681                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2682                         layer_idx = I40E_FLXPLD_L2_IDX;
2683
2684                         break;
2685                 case RTE_FLOW_ITEM_TYPE_VLAN:
2686                         vlan_spec = item->spec;
2687                         vlan_mask = item->mask;
2688
2689                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2690                         if (vlan_spec && vlan_mask) {
2691                                 if (vlan_mask->tci ==
2692                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2693                                         input_set |= I40E_INSET_VLAN_INNER;
2694                                         filter->input.flow_ext.vlan_tci =
2695                                                 vlan_spec->tci;
2696                                 }
2697                         }
2698                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2699                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2700                                         rte_flow_error_set(error, EINVAL,
2701                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2702                                                       item,
2703                                                       "Invalid inner_type"
2704                                                       " mask.");
2705                                         return -rte_errno;
2706                                 }
2707
2708                                 ether_type =
2709                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2710
2711                                 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2712                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2713                                     ether_type == outer_tpid) {
2714                                         rte_flow_error_set(error, EINVAL,
2715                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2716                                                      item,
2717                                                      "Unsupported inner_type.");
2718                                         return -rte_errno;
2719                                 }
2720                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2721                                 filter->input.flow.l2_flow.ether_type =
2722                                         vlan_spec->inner_type;
2723                         }
2724
2725                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2726                         layer_idx = I40E_FLXPLD_L2_IDX;
2727
2728                         break;
2729                 case RTE_FLOW_ITEM_TYPE_IPV4:
2730                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2731                         ipv4_spec = item->spec;
2732                         ipv4_mask = item->mask;
2733                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2734                         layer_idx = I40E_FLXPLD_L3_IDX;
2735
2736                         if (ipv4_spec && ipv4_mask && outer_ip) {
2737                                 /* Check IPv4 mask and update input set */
2738                                 if (ipv4_mask->hdr.version_ihl ||
2739                                     ipv4_mask->hdr.total_length ||
2740                                     ipv4_mask->hdr.packet_id ||
2741                                     ipv4_mask->hdr.fragment_offset ||
2742                                     ipv4_mask->hdr.hdr_checksum) {
2743                                         rte_flow_error_set(error, EINVAL,
2744                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2745                                                    item,
2746                                                    "Invalid IPv4 mask.");
2747                                         return -rte_errno;
2748                                 }
2749
2750                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2751                                         input_set |= I40E_INSET_IPV4_SRC;
2752                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2753                                         input_set |= I40E_INSET_IPV4_DST;
2754                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2755                                         input_set |= I40E_INSET_IPV4_TOS;
2756                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2757                                         input_set |= I40E_INSET_IPV4_TTL;
2758                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2759                                         input_set |= I40E_INSET_IPV4_PROTO;
2760
2761                                 /* Check if it is fragment. */
2762                                 frag_off = ipv4_spec->hdr.fragment_offset;
2763                                 frag_off = rte_be_to_cpu_16(frag_off);
2764                                 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2765                                     frag_off & RTE_IPV4_HDR_MF_FLAG)
2766                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2767
2768                                 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2769                                         if (input_set & (I40E_INSET_IPV4_SRC |
2770                                                 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
2771                                                 I40E_INSET_IPV4_TTL | I40E_INSET_IPV4_PROTO)) {
2772                                                 rte_flow_error_set(error, EINVAL,
2773                                                         RTE_FLOW_ERROR_TYPE_ITEM,
2774                                                         item,
2775                                                         "L2 and L3 input set are exclusive.");
2776                                                 return -rte_errno;
2777                                         }
2778                                 } else {
2779                                         /* Get the filter info */
2780                                         filter->input.flow.ip4_flow.proto =
2781                                                 ipv4_spec->hdr.next_proto_id;
2782                                         filter->input.flow.ip4_flow.tos =
2783                                                 ipv4_spec->hdr.type_of_service;
2784                                         filter->input.flow.ip4_flow.ttl =
2785                                                 ipv4_spec->hdr.time_to_live;
2786                                         filter->input.flow.ip4_flow.src_ip =
2787                                                 ipv4_spec->hdr.src_addr;
2788                                         filter->input.flow.ip4_flow.dst_ip =
2789                                                 ipv4_spec->hdr.dst_addr;
2790
2791                                         filter->input.flow_ext.inner_ip = false;
2792                                         filter->input.flow_ext.oip_type =
2793                                                 I40E_FDIR_IPTYPE_IPV4;
2794                                 }
2795                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2796                                 filter->input.flow_ext.inner_ip = true;
2797                                 filter->input.flow_ext.iip_type =
2798                                         I40E_FDIR_IPTYPE_IPV4;
2799                         } else if (!ipv4_spec && !ipv4_mask && outer_ip) {
2800                                 filter->input.flow_ext.inner_ip = false;
2801                                 filter->input.flow_ext.oip_type =
2802                                         I40E_FDIR_IPTYPE_IPV4;
2803                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2804                                 rte_flow_error_set(error, EINVAL,
2805                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2806                                                    item,
2807                                                    "Invalid inner IPv4 mask.");
2808                                 return -rte_errno;
2809                         }
2810
2811                         if (outer_ip)
2812                                 outer_ip = false;
2813
2814                         break;
2815                 case RTE_FLOW_ITEM_TYPE_IPV6:
2816                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2817                         ipv6_spec = item->spec;
2818                         ipv6_mask = item->mask;
2819                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2820                         layer_idx = I40E_FLXPLD_L3_IDX;
2821
2822                         if (ipv6_spec && ipv6_mask && outer_ip) {
2823                                 /* Check IPv6 mask and update input set */
2824                                 if (ipv6_mask->hdr.payload_len) {
2825                                         rte_flow_error_set(error, EINVAL,
2826                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2827                                                    item,
2828                                                    "Invalid IPv6 mask");
2829                                         return -rte_errno;
2830                                 }
2831
2832                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2833                                             ipv6_addr_mask,
2834                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2835                                         input_set |= I40E_INSET_IPV6_SRC;
2836                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2837                                             ipv6_addr_mask,
2838                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2839                                         input_set |= I40E_INSET_IPV6_DST;
2840
2841                                 if ((ipv6_mask->hdr.vtc_flow &
2842                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2843                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2844                                         input_set |= I40E_INSET_IPV6_TC;
2845                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2846                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2847                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2848                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2849
2850                                 /* Get filter info */
2851                                 vtc_flow_cpu =
2852                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2853                                 filter->input.flow.ipv6_flow.tc =
2854                                         (uint8_t)(vtc_flow_cpu >>
2855                                                   I40E_FDIR_IPv6_TC_OFFSET);
2856                                 filter->input.flow.ipv6_flow.proto =
2857                                         ipv6_spec->hdr.proto;
2858                                 filter->input.flow.ipv6_flow.hop_limits =
2859                                         ipv6_spec->hdr.hop_limits;
2860
2861                                 filter->input.flow_ext.inner_ip = false;
2862                                 filter->input.flow_ext.oip_type =
2863                                         I40E_FDIR_IPTYPE_IPV6;
2864
2865                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2866                                            ipv6_spec->hdr.src_addr, 16);
2867                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2868                                            ipv6_spec->hdr.dst_addr, 16);
2869
2870                                 /* Check if it is fragment. */
2871                                 if (ipv6_spec->hdr.proto ==
2872                                     I40E_IPV6_FRAG_HEADER)
2873                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2874                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2875                                 filter->input.flow_ext.inner_ip = true;
2876                                 filter->input.flow_ext.iip_type =
2877                                         I40E_FDIR_IPTYPE_IPV6;
2878                         } else if (!ipv6_spec && !ipv6_mask && outer_ip) {
2879                                 filter->input.flow_ext.inner_ip = false;
2880                                 filter->input.flow_ext.oip_type =
2881                                         I40E_FDIR_IPTYPE_IPV6;
2882                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2883                                 rte_flow_error_set(error, EINVAL,
2884                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2885                                                    item,
2886                                                    "Invalid inner IPv6 mask");
2887                                 return -rte_errno;
2888                         }
2889
2890                         if (outer_ip)
2891                                 outer_ip = false;
2892                         break;
2893                 case RTE_FLOW_ITEM_TYPE_TCP:
2894                         tcp_spec = item->spec;
2895                         tcp_mask = item->mask;
2896
2897                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2898                                 pctype =
2899                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2900                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2901                                 pctype =
2902                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2903                         if (tcp_spec && tcp_mask) {
2904                                 /* Check TCP mask and update input set */
2905                                 if (tcp_mask->hdr.sent_seq ||
2906                                     tcp_mask->hdr.recv_ack ||
2907                                     tcp_mask->hdr.data_off ||
2908                                     tcp_mask->hdr.tcp_flags ||
2909                                     tcp_mask->hdr.rx_win ||
2910                                     tcp_mask->hdr.cksum ||
2911                                     tcp_mask->hdr.tcp_urp) {
2912                                         rte_flow_error_set(error, EINVAL,
2913                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2914                                                    item,
2915                                                    "Invalid TCP mask");
2916                                         return -rte_errno;
2917                                 }
2918
2919                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2920                                         input_set |= I40E_INSET_SRC_PORT;
2921                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2922                                         input_set |= I40E_INSET_DST_PORT;
2923
2924                                 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2925                                         if (input_set &
2926                                                 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2927                                                 rte_flow_error_set(error, EINVAL,
2928                                                         RTE_FLOW_ERROR_TYPE_ITEM,
2929                                                         item,
2930                                                         "L2 and L4 input set are exclusive.");
2931                                                 return -rte_errno;
2932                                         }
2933                                 } else {
2934                                         /* Get filter info */
2935                                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2936                                                 filter->input.flow.tcp4_flow.src_port =
2937                                                         tcp_spec->hdr.src_port;
2938                                                 filter->input.flow.tcp4_flow.dst_port =
2939                                                         tcp_spec->hdr.dst_port;
2940                                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2941                                                 filter->input.flow.tcp6_flow.src_port =
2942                                                         tcp_spec->hdr.src_port;
2943                                                 filter->input.flow.tcp6_flow.dst_port =
2944                                                         tcp_spec->hdr.dst_port;
2945                                         }
2946                                 }
2947                         }
2948
2949                         layer_idx = I40E_FLXPLD_L4_IDX;
2950
2951                         break;
2952                 case RTE_FLOW_ITEM_TYPE_UDP:
2953                         udp_spec = item->spec;
2954                         udp_mask = item->mask;
2955
2956                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2957                                 pctype =
2958                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2959                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2960                                 pctype =
2961                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2962
2963                         if (udp_spec && udp_mask) {
2964                                 /* Check UDP mask and update input set*/
2965                                 if (udp_mask->hdr.dgram_len ||
2966                                     udp_mask->hdr.dgram_cksum) {
2967                                         rte_flow_error_set(error, EINVAL,
2968                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2969                                                    item,
2970                                                    "Invalid UDP mask");
2971                                         return -rte_errno;
2972                                 }
2973
2974                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2975                                         input_set |= I40E_INSET_SRC_PORT;
2976                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2977                                         input_set |= I40E_INSET_DST_PORT;
2978
2979                                 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2980                                         if (input_set &
2981                                                 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2982                                                 rte_flow_error_set(error, EINVAL,
2983                                                         RTE_FLOW_ERROR_TYPE_ITEM,
2984                                                         item,
2985                                                         "L2 and L4 input set are exclusive.");
2986                                                 return -rte_errno;
2987                                         }
2988                                 } else {
2989                                         /* Get filter info */
2990                                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2991                                                 filter->input.flow.udp4_flow.src_port =
2992                                                         udp_spec->hdr.src_port;
2993                                                 filter->input.flow.udp4_flow.dst_port =
2994                                                         udp_spec->hdr.dst_port;
2995                                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2996                                                 filter->input.flow.udp6_flow.src_port =
2997                                                         udp_spec->hdr.src_port;
2998                                                 filter->input.flow.udp6_flow.dst_port =
2999                                                         udp_spec->hdr.dst_port;
3000                                         }
3001                                 }
3002                         }
3003                         filter->input.flow_ext.is_udp = true;
3004                         layer_idx = I40E_FLXPLD_L4_IDX;
3005
3006                         break;
3007                 case RTE_FLOW_ITEM_TYPE_GTPC:
3008                 case RTE_FLOW_ITEM_TYPE_GTPU:
3009                         if (!pf->gtp_support) {
3010                                 rte_flow_error_set(error, EINVAL,
3011                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3012                                                    item,
3013                                                    "Unsupported protocol");
3014                                 return -rte_errno;
3015                         }
3016
3017                         gtp_spec = item->spec;
3018                         gtp_mask = item->mask;
3019
3020                         if (gtp_spec && gtp_mask) {
3021                                 if (gtp_mask->v_pt_rsv_flags ||
3022                                     gtp_mask->msg_type ||
3023                                     gtp_mask->msg_len ||
3024                                     gtp_mask->teid != UINT32_MAX) {
3025                                         rte_flow_error_set(error, EINVAL,
3026                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3027                                                    item,
3028                                                    "Invalid GTP mask");
3029                                         return -rte_errno;
3030                                 }
3031
3032                                 filter->input.flow.gtp_flow.teid =
3033                                         gtp_spec->teid;
3034                                 filter->input.flow_ext.customized_pctype = true;
3035                                 cus_proto = item_type;
3036                         }
3037                         break;
3038                 case RTE_FLOW_ITEM_TYPE_ESP:
3039                         if (!pf->esp_support) {
3040                                 rte_flow_error_set(error, EINVAL,
3041                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3042                                                    item,
3043                                                    "Unsupported ESP protocol");
3044                                 return -rte_errno;
3045                         }
3046
3047                         esp_spec = item->spec;
3048                         esp_mask = item->mask;
3049
3050                         if (!esp_spec || !esp_mask) {
3051                                 rte_flow_error_set(error, EINVAL,
3052                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3053                                                    item,
3054                                                    "Invalid ESP item");
3055                                 return -rte_errno;
3056                         }
3057
3058                         if (esp_spec && esp_mask) {
3059                                 if (esp_mask->hdr.spi != UINT32_MAX) {
3060                                         rte_flow_error_set(error, EINVAL,
3061                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3062                                                    item,
3063                                                    "Invalid ESP mask");
3064                                         return -rte_errno;
3065                                 }
3066                                 i40e_flow_set_filter_spi(filter, esp_spec);
3067                                 filter->input.flow_ext.customized_pctype = true;
3068                                 cus_proto = item_type;
3069                         }
3070                         break;
3071                 case RTE_FLOW_ITEM_TYPE_SCTP:
3072                         sctp_spec = item->spec;
3073                         sctp_mask = item->mask;
3074
3075                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
3076                                 pctype =
3077                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3078                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
3079                                 pctype =
3080                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3081
3082                         if (sctp_spec && sctp_mask) {
3083                                 /* Check SCTP mask and update input set */
3084                                 if (sctp_mask->hdr.cksum) {
3085                                         rte_flow_error_set(error, EINVAL,
3086                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3087                                                    item,
3088                                                    "Invalid UDP mask");
3089                                         return -rte_errno;
3090                                 }
3091
3092                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
3093                                         input_set |= I40E_INSET_SRC_PORT;
3094                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
3095                                         input_set |= I40E_INSET_DST_PORT;
3096                                 if (sctp_mask->hdr.tag == UINT32_MAX)
3097                                         input_set |= I40E_INSET_SCTP_VT;
3098
3099                                 /* Get filter info */
3100                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3101                                         filter->input.flow.sctp4_flow.src_port =
3102                                                 sctp_spec->hdr.src_port;
3103                                         filter->input.flow.sctp4_flow.dst_port =
3104                                                 sctp_spec->hdr.dst_port;
3105                                         filter->input.flow.sctp4_flow.verify_tag
3106                                                 = sctp_spec->hdr.tag;
3107                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3108                                         filter->input.flow.sctp6_flow.src_port =
3109                                                 sctp_spec->hdr.src_port;
3110                                         filter->input.flow.sctp6_flow.dst_port =
3111                                                 sctp_spec->hdr.dst_port;
3112                                         filter->input.flow.sctp6_flow.verify_tag
3113                                                 = sctp_spec->hdr.tag;
3114                                 }
3115                         }
3116
3117                         layer_idx = I40E_FLXPLD_L4_IDX;
3118
3119                         break;
3120                 case RTE_FLOW_ITEM_TYPE_RAW:
3121                         raw_spec = item->spec;
3122                         raw_mask = item->mask;
3123
3124                         if (!raw_spec || !raw_mask) {
3125                                 rte_flow_error_set(error, EINVAL,
3126                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3127                                                    item,
3128                                                    "NULL RAW spec/mask");
3129                                 return -rte_errno;
3130                         }
3131
3132                         if (pf->support_multi_driver) {
3133                                 rte_flow_error_set(error, ENOTSUP,
3134                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3135                                                    item,
3136                                                    "Unsupported flexible payload.");
3137                                 return -rte_errno;
3138                         }
3139
3140                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
3141                         if (ret < 0)
3142                                 return ret;
3143
3144                         off_arr[raw_id] = raw_spec->offset;
3145                         len_arr[raw_id] = raw_spec->length;
3146
3147                         flex_size = 0;
3148                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
3149                         flex_pit.size =
3150                                 raw_spec->length / sizeof(uint16_t);
3151                         flex_pit.dst_offset =
3152                                 next_dst_off / sizeof(uint16_t);
3153
3154                         for (i = 0; i <= raw_id; i++) {
3155                                 if (i == raw_id)
3156                                         flex_pit.src_offset +=
3157                                                 raw_spec->offset /
3158                                                 sizeof(uint16_t);
3159                                 else
3160                                         flex_pit.src_offset +=
3161                                                 (off_arr[i] + len_arr[i]) /
3162                                                 sizeof(uint16_t);
3163                                 flex_size += len_arr[i];
3164                         }
3165                         if (((flex_pit.src_offset + flex_pit.size) >=
3166                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
3167                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
3168                                 rte_flow_error_set(error, EINVAL,
3169                                            RTE_FLOW_ERROR_TYPE_ITEM,
3170                                            item,
3171                                            "Exceeds maxmial payload limit.");
3172                                 return -rte_errno;
3173                         }
3174
3175                         /* Store flex pit to SW */
3176                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
3177                                                        layer_idx, raw_id);
3178                         if (ret < 0) {
3179                                 rte_flow_error_set(error, EINVAL,
3180                                    RTE_FLOW_ERROR_TYPE_ITEM,
3181                                    item,
3182                                    "Conflict with the first flexible rule.");
3183                                 return -rte_errno;
3184                         } else if (ret > 0)
3185                                 cfg_flex_pit = false;
3186
3187                         for (i = 0; i < raw_spec->length; i++) {
3188                                 j = i + next_dst_off;
3189                                 filter->input.flow_ext.flexbytes[j] =
3190                                         raw_spec->pattern[i];
3191                                 flex_mask[j] = raw_mask->pattern[i];
3192                         }
3193
3194                         next_dst_off += raw_spec->length;
3195                         raw_id++;
3196                         break;
3197                 case RTE_FLOW_ITEM_TYPE_VF:
3198                         vf_spec = item->spec;
3199                         if (!attr->transfer) {
3200                                 rte_flow_error_set(error, ENOTSUP,
3201                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3202                                                    item,
3203                                                    "Matching VF traffic"
3204                                                    " without affecting it"
3205                                                    " (transfer attribute)"
3206                                                    " is unsupported");
3207                                 return -rte_errno;
3208                         }
3209                         filter->input.flow_ext.is_vf = 1;
3210                         filter->input.flow_ext.dst_id = vf_spec->id;
3211                         if (filter->input.flow_ext.is_vf &&
3212                             filter->input.flow_ext.dst_id >= pf->vf_num) {
3213                                 rte_flow_error_set(error, EINVAL,
3214                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3215                                                    item,
3216                                                    "Invalid VF ID for FDIR.");
3217                                 return -rte_errno;
3218                         }
3219                         break;
3220                 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
3221                         l2tpv3oip_spec = item->spec;
3222                         l2tpv3oip_mask = item->mask;
3223
3224                         if (!l2tpv3oip_spec || !l2tpv3oip_mask)
3225                                 break;
3226
3227                         if (l2tpv3oip_mask->session_id != UINT32_MAX) {
3228                                 rte_flow_error_set(error, EINVAL,
3229                                         RTE_FLOW_ERROR_TYPE_ITEM,
3230                                         item,
3231                                         "Invalid L2TPv3 mask");
3232                                 return -rte_errno;
3233                         }
3234
3235                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3236                                 filter->input.flow.ip4_l2tpv3oip_flow.session_id =
3237                                         l2tpv3oip_spec->session_id;
3238                                 filter->input.flow_ext.oip_type =
3239                                         I40E_FDIR_IPTYPE_IPV4;
3240                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3241                                 filter->input.flow.ip6_l2tpv3oip_flow.session_id =
3242                                         l2tpv3oip_spec->session_id;
3243                                 filter->input.flow_ext.oip_type =
3244                                         I40E_FDIR_IPTYPE_IPV6;
3245                         }
3246
3247                         filter->input.flow_ext.customized_pctype = true;
3248                         cus_proto = item_type;
3249                         break;
3250                 default:
3251                         break;
3252                 }
3253         }
3254
3255         /* Get customized pctype value */
3256         if (filter->input.flow_ext.customized_pctype) {
3257                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
3258                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3259                         rte_flow_error_set(error, EINVAL,
3260                                            RTE_FLOW_ERROR_TYPE_ITEM,
3261                                            item,
3262                                            "Unsupported pctype");
3263                         return -rte_errno;
3264                 }
3265         }
3266
3267         /* If customized pctype is not used, set fdir configuration.*/
3268         if (!filter->input.flow_ext.customized_pctype) {
3269                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3270                 if (ret == -1) {
3271                         rte_flow_error_set(error, EINVAL,
3272                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3273                                            "Conflict with the first rule's input set.");
3274                         return -rte_errno;
3275                 } else if (ret == -EINVAL) {
3276                         rte_flow_error_set(error, EINVAL,
3277                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3278                                            "Invalid pattern mask.");
3279                         return -rte_errno;
3280                 }
3281
3282                 /* Store flex mask to SW */
3283                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3284                 if (ret == -1) {
3285                         rte_flow_error_set(error, EINVAL,
3286                                            RTE_FLOW_ERROR_TYPE_ITEM,
3287                                            item,
3288                                            "Exceed maximal number of bitmasks");
3289                         return -rte_errno;
3290                 } else if (ret == -2) {
3291                         rte_flow_error_set(error, EINVAL,
3292                                            RTE_FLOW_ERROR_TYPE_ITEM,
3293                                            item,
3294                                            "Conflict with the first flexible rule");
3295                         return -rte_errno;
3296                 } else if (ret > 0)
3297                         cfg_flex_msk = false;
3298
3299                 if (cfg_flex_pit)
3300                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3301
3302                 if (cfg_flex_msk)
3303                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3304         }
3305
3306         filter->input.pctype = pctype;
3307
3308         return 0;
3309 }
3310
3311 /* Parse to get the action info of a FDIR filter.
3312  * FDIR action supports QUEUE or (QUEUE + MARK).
3313  */
3314 static int
3315 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3316                             const struct rte_flow_action *actions,
3317                             struct rte_flow_error *error,
3318                             struct i40e_fdir_filter_conf *filter)
3319 {
3320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3321         const struct rte_flow_action *act;
3322         const struct rte_flow_action_queue *act_q;
3323         const struct rte_flow_action_mark *mark_spec = NULL;
3324         uint32_t index = 0;
3325
3326         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3327         NEXT_ITEM_OF_ACTION(act, actions, index);
3328         switch (act->type) {
3329         case RTE_FLOW_ACTION_TYPE_QUEUE:
3330                 act_q = act->conf;
3331                 filter->action.rx_queue = act_q->index;
3332                 if ((!filter->input.flow_ext.is_vf &&
3333                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3334                     (filter->input.flow_ext.is_vf &&
3335                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3336                         rte_flow_error_set(error, EINVAL,
3337                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3338                                            "Invalid queue ID for FDIR.");
3339                         return -rte_errno;
3340                 }
3341                 filter->action.behavior = I40E_FDIR_ACCEPT;
3342                 break;
3343         case RTE_FLOW_ACTION_TYPE_DROP:
3344                 filter->action.behavior = I40E_FDIR_REJECT;
3345                 break;
3346         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3347                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3348                 break;
3349         case RTE_FLOW_ACTION_TYPE_MARK:
3350                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3351                 mark_spec = act->conf;
3352                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3353                 filter->soft_id = mark_spec->id;
3354         break;
3355         default:
3356                 rte_flow_error_set(error, EINVAL,
3357                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3358                                    "Invalid action.");
3359                 return -rte_errno;
3360         }
3361
3362         /* Check if the next non-void item is MARK or FLAG or END. */
3363         index++;
3364         NEXT_ITEM_OF_ACTION(act, actions, index);
3365         switch (act->type) {
3366         case RTE_FLOW_ACTION_TYPE_MARK:
3367                 if (mark_spec) {
3368                         /* Double MARK actions requested */
3369                         rte_flow_error_set(error, EINVAL,
3370                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3371                            "Invalid action.");
3372                         return -rte_errno;
3373                 }
3374                 mark_spec = act->conf;
3375                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3376                 filter->soft_id = mark_spec->id;
3377                 break;
3378         case RTE_FLOW_ACTION_TYPE_FLAG:
3379                 if (mark_spec) {
3380                         /* MARK + FLAG not supported */
3381                         rte_flow_error_set(error, EINVAL,
3382                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3383                                            "Invalid action.");
3384                         return -rte_errno;
3385                 }
3386                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3387                 break;
3388         case RTE_FLOW_ACTION_TYPE_RSS:
3389                 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3390                         /* RSS filter won't be next if FDIR did not pass thru */
3391                         rte_flow_error_set(error, EINVAL,
3392                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3393                                            "Invalid action.");
3394                         return -rte_errno;
3395                 }
3396                 break;
3397         case RTE_FLOW_ACTION_TYPE_END:
3398                 return 0;
3399         default:
3400                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3401                                    act, "Invalid action.");
3402                 return -rte_errno;
3403         }
3404
3405         /* Check if the next non-void item is END */
3406         index++;
3407         NEXT_ITEM_OF_ACTION(act, actions, index);
3408         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3409                 rte_flow_error_set(error, EINVAL,
3410                                    RTE_FLOW_ERROR_TYPE_ACTION,
3411                                    act, "Invalid action.");
3412                 return -rte_errno;
3413         }
3414
3415         return 0;
3416 }
3417
3418 static int
3419 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3420                             const struct rte_flow_attr *attr,
3421                             const struct rte_flow_item pattern[],
3422                             const struct rte_flow_action actions[],
3423                             struct rte_flow_error *error,
3424                             union i40e_filter_t *filter)
3425 {
3426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3427         struct i40e_fdir_filter_conf *fdir_filter =
3428                 &filter->fdir_filter;
3429         int ret;
3430
3431         ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3432                                            fdir_filter);
3433         if (ret)
3434                 return ret;
3435
3436         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3437         if (ret)
3438                 return ret;
3439
3440         ret = i40e_flow_parse_attr(attr, error);
3441         if (ret)
3442                 return ret;
3443
3444         cons_filter_type = RTE_ETH_FILTER_FDIR;
3445
3446         if (pf->fdir.fdir_vsi == NULL) {
3447                 /* Enable fdir when fdir flow is added at first time. */
3448                 ret = i40e_fdir_setup(pf);
3449                 if (ret != I40E_SUCCESS) {
3450                         rte_flow_error_set(error, ENOTSUP,
3451                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3452                                            NULL, "Failed to setup fdir.");
3453                         return -rte_errno;
3454                 }
3455                 ret = i40e_fdir_configure(dev);
3456                 if (ret < 0) {
3457                         rte_flow_error_set(error, ENOTSUP,
3458                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3459                                            NULL, "Failed to configure fdir.");
3460                         goto err;
3461                 }
3462         }
3463
3464         return 0;
3465 err:
3466         i40e_fdir_teardown(pf);
3467         return -rte_errno;
3468 }
3469
3470 /* Parse to get the action info of a tunnel filter
3471  * Tunnel action only supports PF, VF and QUEUE.
3472  */
3473 static int
3474 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3475                               const struct rte_flow_action *actions,
3476                               struct rte_flow_error *error,
3477                               struct i40e_tunnel_filter_conf *filter)
3478 {
3479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3480         const struct rte_flow_action *act;
3481         const struct rte_flow_action_queue *act_q;
3482         const struct rte_flow_action_vf *act_vf;
3483         uint32_t index = 0;
3484
3485         /* Check if the first non-void action is PF or VF. */
3486         NEXT_ITEM_OF_ACTION(act, actions, index);
3487         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3488             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3489                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3490                                    act, "Not supported action.");
3491                 return -rte_errno;
3492         }
3493
3494         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3495                 act_vf = act->conf;
3496                 filter->vf_id = act_vf->id;
3497                 filter->is_to_vf = 1;
3498                 if (filter->vf_id >= pf->vf_num) {
3499                         rte_flow_error_set(error, EINVAL,
3500                                    RTE_FLOW_ERROR_TYPE_ACTION,
3501                                    act, "Invalid VF ID for tunnel filter");
3502                         return -rte_errno;
3503                 }
3504         }
3505
3506         /* Check if the next non-void item is QUEUE */
3507         index++;
3508         NEXT_ITEM_OF_ACTION(act, actions, index);
3509         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3510                 act_q = act->conf;
3511                 filter->queue_id = act_q->index;
3512                 if ((!filter->is_to_vf) &&
3513                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3514                         rte_flow_error_set(error, EINVAL,
3515                                    RTE_FLOW_ERROR_TYPE_ACTION,
3516                                    act, "Invalid queue ID for tunnel filter");
3517                         return -rte_errno;
3518                 } else if (filter->is_to_vf &&
3519                            (filter->queue_id >= pf->vf_nb_qps)) {
3520                         rte_flow_error_set(error, EINVAL,
3521                                    RTE_FLOW_ERROR_TYPE_ACTION,
3522                                    act, "Invalid queue ID for tunnel filter");
3523                         return -rte_errno;
3524                 }
3525         }
3526
3527         /* Check if the next non-void item is END */
3528         index++;
3529         NEXT_ITEM_OF_ACTION(act, actions, index);
3530         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3531                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3532                                    act, "Not supported action.");
3533                 return -rte_errno;
3534         }
3535
3536         return 0;
3537 }
3538
3539 static uint16_t i40e_supported_tunnel_filter_types[] = {
3540         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3541         ETH_TUNNEL_FILTER_IVLAN,
3542         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3543         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3544         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3545         ETH_TUNNEL_FILTER_IMAC,
3546         ETH_TUNNEL_FILTER_IMAC,
3547 };
3548
3549 static int
3550 i40e_check_tunnel_filter_type(uint8_t filter_type)
3551 {
3552         uint8_t i;
3553
3554         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3555                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3556                         return 0;
3557         }
3558
3559         return -1;
3560 }
3561
3562 /* 1. Last in item should be NULL as range is not supported.
3563  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3564  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3565  * 3. Mask of fields which need to be matched should be
3566  *    filled with 1.
3567  * 4. Mask of fields which needn't to be matched should be
3568  *    filled with 0.
3569  */
3570 static int
3571 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3572                               const struct rte_flow_item *pattern,
3573                               struct rte_flow_error *error,
3574                               struct i40e_tunnel_filter_conf *filter)
3575 {
3576         const struct rte_flow_item *item = pattern;
3577         const struct rte_flow_item_eth *eth_spec;
3578         const struct rte_flow_item_eth *eth_mask;
3579         const struct rte_flow_item_vxlan *vxlan_spec;
3580         const struct rte_flow_item_vxlan *vxlan_mask;
3581         const struct rte_flow_item_vlan *vlan_spec;
3582         const struct rte_flow_item_vlan *vlan_mask;
3583         uint8_t filter_type = 0;
3584         bool is_vni_masked = 0;
3585         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3586         enum rte_flow_item_type item_type;
3587         bool vxlan_flag = 0;
3588         uint32_t tenant_id_be = 0;
3589         int ret;
3590
3591         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3592                 if (item->last) {
3593                         rte_flow_error_set(error, EINVAL,
3594                                            RTE_FLOW_ERROR_TYPE_ITEM,
3595                                            item,
3596                                            "Not support range");
3597                         return -rte_errno;
3598                 }
3599                 item_type = item->type;
3600                 switch (item_type) {
3601                 case RTE_FLOW_ITEM_TYPE_ETH:
3602                         eth_spec = item->spec;
3603                         eth_mask = item->mask;
3604
3605                         /* Check if ETH item is used for place holder.
3606                          * If yes, both spec and mask should be NULL.
3607                          * If no, both spec and mask shouldn't be NULL.
3608                          */
3609                         if ((!eth_spec && eth_mask) ||
3610                             (eth_spec && !eth_mask)) {
3611                                 rte_flow_error_set(error, EINVAL,
3612                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3613                                                    item,
3614                                                    "Invalid ether spec/mask");
3615                                 return -rte_errno;
3616                         }
3617
3618                         if (eth_spec && eth_mask) {
3619                                 /* DST address of inner MAC shouldn't be masked.
3620                                  * SRC address of Inner MAC should be masked.
3621                                  */
3622                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3623                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3624                                     eth_mask->type) {
3625                                         rte_flow_error_set(error, EINVAL,
3626                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3627                                                    item,
3628                                                    "Invalid ether spec/mask");
3629                                         return -rte_errno;
3630                                 }
3631
3632                                 if (!vxlan_flag) {
3633                                         rte_memcpy(&filter->outer_mac,
3634                                                    &eth_spec->dst,
3635                                                    RTE_ETHER_ADDR_LEN);
3636                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3637                                 } else {
3638                                         rte_memcpy(&filter->inner_mac,
3639                                                    &eth_spec->dst,
3640                                                    RTE_ETHER_ADDR_LEN);
3641                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3642                                 }
3643                         }
3644                         break;
3645                 case RTE_FLOW_ITEM_TYPE_VLAN:
3646                         vlan_spec = item->spec;
3647                         vlan_mask = item->mask;
3648                         if (!(vlan_spec && vlan_mask) ||
3649                             vlan_mask->inner_type) {
3650                                 rte_flow_error_set(error, EINVAL,
3651                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3652                                                    item,
3653                                                    "Invalid vlan item");
3654                                 return -rte_errno;
3655                         }
3656
3657                         if (vlan_spec && vlan_mask) {
3658                                 if (vlan_mask->tci ==
3659                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3660                                         filter->inner_vlan =
3661                                               rte_be_to_cpu_16(vlan_spec->tci) &
3662                                               I40E_TCI_MASK;
3663                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3664                         }
3665                         break;
3666                 case RTE_FLOW_ITEM_TYPE_IPV4:
3667                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3668                         /* IPv4 is used to describe protocol,
3669                          * spec and mask should be NULL.
3670                          */
3671                         if (item->spec || item->mask) {
3672                                 rte_flow_error_set(error, EINVAL,
3673                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3674                                                    item,
3675                                                    "Invalid IPv4 item");
3676                                 return -rte_errno;
3677                         }
3678                         break;
3679                 case RTE_FLOW_ITEM_TYPE_IPV6:
3680                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3681                         /* IPv6 is used to describe protocol,
3682                          * spec and mask should be NULL.
3683                          */
3684                         if (item->spec || item->mask) {
3685                                 rte_flow_error_set(error, EINVAL,
3686                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3687                                                    item,
3688                                                    "Invalid IPv6 item");
3689                                 return -rte_errno;
3690                         }
3691                         break;
3692                 case RTE_FLOW_ITEM_TYPE_UDP:
3693                         /* UDP is used to describe protocol,
3694                          * spec and mask should be NULL.
3695                          */
3696                         if (item->spec || item->mask) {
3697                                 rte_flow_error_set(error, EINVAL,
3698                                            RTE_FLOW_ERROR_TYPE_ITEM,
3699                                            item,
3700                                            "Invalid UDP item");
3701                                 return -rte_errno;
3702                         }
3703                         break;
3704                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3705                         vxlan_spec = item->spec;
3706                         vxlan_mask = item->mask;
3707                         /* Check if VXLAN item is used to describe protocol.
3708                          * If yes, both spec and mask should be NULL.
3709                          * If no, both spec and mask shouldn't be NULL.
3710                          */
3711                         if ((!vxlan_spec && vxlan_mask) ||
3712                             (vxlan_spec && !vxlan_mask)) {
3713                                 rte_flow_error_set(error, EINVAL,
3714                                            RTE_FLOW_ERROR_TYPE_ITEM,
3715                                            item,
3716                                            "Invalid VXLAN item");
3717                                 return -rte_errno;
3718                         }
3719
3720                         /* Check if VNI is masked. */
3721                         if (vxlan_spec && vxlan_mask) {
3722                                 is_vni_masked =
3723                                         !!memcmp(vxlan_mask->vni, vni_mask,
3724                                                  RTE_DIM(vni_mask));
3725                                 if (is_vni_masked) {
3726                                         rte_flow_error_set(error, EINVAL,
3727                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3728                                                    item,
3729                                                    "Invalid VNI mask");
3730                                         return -rte_errno;
3731                                 }
3732
3733                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3734                                            vxlan_spec->vni, 3);
3735                                 filter->tenant_id =
3736                                         rte_be_to_cpu_32(tenant_id_be);
3737                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3738                         }
3739
3740                         vxlan_flag = 1;
3741                         break;
3742                 default:
3743                         break;
3744                 }
3745         }
3746
3747         ret = i40e_check_tunnel_filter_type(filter_type);
3748         if (ret < 0) {
3749                 rte_flow_error_set(error, EINVAL,
3750                                    RTE_FLOW_ERROR_TYPE_ITEM,
3751                                    NULL,
3752                                    "Invalid filter type");
3753                 return -rte_errno;
3754         }
3755         filter->filter_type = filter_type;
3756
3757         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3758
3759         return 0;
3760 }
3761
3762 static int
3763 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3764                              const struct rte_flow_attr *attr,
3765                              const struct rte_flow_item pattern[],
3766                              const struct rte_flow_action actions[],
3767                              struct rte_flow_error *error,
3768                              union i40e_filter_t *filter)
3769 {
3770         struct i40e_tunnel_filter_conf *tunnel_filter =
3771                 &filter->consistent_tunnel_filter;
3772         int ret;
3773
3774         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3775                                             error, tunnel_filter);
3776         if (ret)
3777                 return ret;
3778
3779         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3780         if (ret)
3781                 return ret;
3782
3783         ret = i40e_flow_parse_attr(attr, error);
3784         if (ret)
3785                 return ret;
3786
3787         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3788
3789         return ret;
3790 }
3791
3792 /* 1. Last in item should be NULL as range is not supported.
3793  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3794  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3795  * 3. Mask of fields which need to be matched should be
3796  *    filled with 1.
3797  * 4. Mask of fields which needn't to be matched should be
3798  *    filled with 0.
3799  */
3800 static int
3801 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3802                               const struct rte_flow_item *pattern,
3803                               struct rte_flow_error *error,
3804                               struct i40e_tunnel_filter_conf *filter)
3805 {
3806         const struct rte_flow_item *item = pattern;
3807         const struct rte_flow_item_eth *eth_spec;
3808         const struct rte_flow_item_eth *eth_mask;
3809         const struct rte_flow_item_nvgre *nvgre_spec;
3810         const struct rte_flow_item_nvgre *nvgre_mask;
3811         const struct rte_flow_item_vlan *vlan_spec;
3812         const struct rte_flow_item_vlan *vlan_mask;
3813         enum rte_flow_item_type item_type;
3814         uint8_t filter_type = 0;
3815         bool is_tni_masked = 0;
3816         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3817         bool nvgre_flag = 0;
3818         uint32_t tenant_id_be = 0;
3819         int ret;
3820
3821         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3822                 if (item->last) {
3823                         rte_flow_error_set(error, EINVAL,
3824                                            RTE_FLOW_ERROR_TYPE_ITEM,
3825                                            item,
3826                                            "Not support range");
3827                         return -rte_errno;
3828                 }
3829                 item_type = item->type;
3830                 switch (item_type) {
3831                 case RTE_FLOW_ITEM_TYPE_ETH:
3832                         eth_spec = item->spec;
3833                         eth_mask = item->mask;
3834
3835                         /* Check if ETH item is used for place holder.
3836                          * If yes, both spec and mask should be NULL.
3837                          * If no, both spec and mask shouldn't be NULL.
3838                          */
3839                         if ((!eth_spec && eth_mask) ||
3840                             (eth_spec && !eth_mask)) {
3841                                 rte_flow_error_set(error, EINVAL,
3842                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3843                                                    item,
3844                                                    "Invalid ether spec/mask");
3845                                 return -rte_errno;
3846                         }
3847
3848                         if (eth_spec && eth_mask) {
3849                                 /* DST address of inner MAC shouldn't be masked.
3850                                  * SRC address of Inner MAC should be masked.
3851                                  */
3852                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3853                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3854                                     eth_mask->type) {
3855                                         rte_flow_error_set(error, EINVAL,
3856                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3857                                                    item,
3858                                                    "Invalid ether spec/mask");
3859                                         return -rte_errno;
3860                                 }
3861
3862                                 if (!nvgre_flag) {
3863                                         rte_memcpy(&filter->outer_mac,
3864                                                    &eth_spec->dst,
3865                                                    RTE_ETHER_ADDR_LEN);
3866                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3867                                 } else {
3868                                         rte_memcpy(&filter->inner_mac,
3869                                                    &eth_spec->dst,
3870                                                    RTE_ETHER_ADDR_LEN);
3871                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3872                                 }
3873                         }
3874
3875                         break;
3876                 case RTE_FLOW_ITEM_TYPE_VLAN:
3877                         vlan_spec = item->spec;
3878                         vlan_mask = item->mask;
3879                         if (!(vlan_spec && vlan_mask) ||
3880                             vlan_mask->inner_type) {
3881                                 rte_flow_error_set(error, EINVAL,
3882                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3883                                                    item,
3884                                                    "Invalid vlan item");
3885                                 return -rte_errno;
3886                         }
3887
3888                         if (vlan_spec && vlan_mask) {
3889                                 if (vlan_mask->tci ==
3890                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3891                                         filter->inner_vlan =
3892                                               rte_be_to_cpu_16(vlan_spec->tci) &
3893                                               I40E_TCI_MASK;
3894                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3895                         }
3896                         break;
3897                 case RTE_FLOW_ITEM_TYPE_IPV4:
3898                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3899                         /* IPv4 is used to describe protocol,
3900                          * spec and mask should be NULL.
3901                          */
3902                         if (item->spec || item->mask) {
3903                                 rte_flow_error_set(error, EINVAL,
3904                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3905                                                    item,
3906                                                    "Invalid IPv4 item");
3907                                 return -rte_errno;
3908                         }
3909                         break;
3910                 case RTE_FLOW_ITEM_TYPE_IPV6:
3911                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3912                         /* IPv6 is used to describe protocol,
3913                          * spec and mask should be NULL.
3914                          */
3915                         if (item->spec || item->mask) {
3916                                 rte_flow_error_set(error, EINVAL,
3917                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3918                                                    item,
3919                                                    "Invalid IPv6 item");
3920                                 return -rte_errno;
3921                         }
3922                         break;
3923                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3924                         nvgre_spec = item->spec;
3925                         nvgre_mask = item->mask;
3926                         /* Check if NVGRE item is used to describe protocol.
3927                          * If yes, both spec and mask should be NULL.
3928                          * If no, both spec and mask shouldn't be NULL.
3929                          */
3930                         if ((!nvgre_spec && nvgre_mask) ||
3931                             (nvgre_spec && !nvgre_mask)) {
3932                                 rte_flow_error_set(error, EINVAL,
3933                                            RTE_FLOW_ERROR_TYPE_ITEM,
3934                                            item,
3935                                            "Invalid NVGRE item");
3936                                 return -rte_errno;
3937                         }
3938
3939                         if (nvgre_spec && nvgre_mask) {
3940                                 is_tni_masked =
3941                                         !!memcmp(nvgre_mask->tni, tni_mask,
3942                                                  RTE_DIM(tni_mask));
3943                                 if (is_tni_masked) {
3944                                         rte_flow_error_set(error, EINVAL,
3945                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3946                                                        item,
3947                                                        "Invalid TNI mask");
3948                                         return -rte_errno;
3949                                 }
3950                                 if (nvgre_mask->protocol &&
3951                                         nvgre_mask->protocol != 0xFFFF) {
3952                                         rte_flow_error_set(error, EINVAL,
3953                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3954                                                 item,
3955                                                 "Invalid NVGRE item");
3956                                         return -rte_errno;
3957                                 }
3958                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3959                                         nvgre_mask->c_k_s_rsvd0_ver !=
3960                                         rte_cpu_to_be_16(0xFFFF)) {
3961                                         rte_flow_error_set(error, EINVAL,
3962                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3963                                                    item,
3964                                                    "Invalid NVGRE item");
3965                                         return -rte_errno;
3966                                 }
3967                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3968                                         rte_cpu_to_be_16(0x2000) &&
3969                                         nvgre_mask->c_k_s_rsvd0_ver) {
3970                                         rte_flow_error_set(error, EINVAL,
3971                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3972                                                    item,
3973                                                    "Invalid NVGRE item");
3974                                         return -rte_errno;
3975                                 }
3976                                 if (nvgre_mask->protocol &&
3977                                         nvgre_spec->protocol !=
3978                                         rte_cpu_to_be_16(0x6558)) {
3979                                         rte_flow_error_set(error, EINVAL,
3980                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3981                                                    item,
3982                                                    "Invalid NVGRE item");
3983                                         return -rte_errno;
3984                                 }
3985                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3986                                            nvgre_spec->tni, 3);
3987                                 filter->tenant_id =
3988                                         rte_be_to_cpu_32(tenant_id_be);
3989                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3990                         }
3991
3992                         nvgre_flag = 1;
3993                         break;
3994                 default:
3995                         break;
3996                 }
3997         }
3998
3999         ret = i40e_check_tunnel_filter_type(filter_type);
4000         if (ret < 0) {
4001                 rte_flow_error_set(error, EINVAL,
4002                                    RTE_FLOW_ERROR_TYPE_ITEM,
4003                                    NULL,
4004                                    "Invalid filter type");
4005                 return -rte_errno;
4006         }
4007         filter->filter_type = filter_type;
4008
4009         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
4010
4011         return 0;
4012 }
4013
4014 static int
4015 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
4016                              const struct rte_flow_attr *attr,
4017                              const struct rte_flow_item pattern[],
4018                              const struct rte_flow_action actions[],
4019                              struct rte_flow_error *error,
4020                              union i40e_filter_t *filter)
4021 {
4022         struct i40e_tunnel_filter_conf *tunnel_filter =
4023                 &filter->consistent_tunnel_filter;
4024         int ret;
4025
4026         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
4027                                             error, tunnel_filter);
4028         if (ret)
4029                 return ret;
4030
4031         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4032         if (ret)
4033                 return ret;
4034
4035         ret = i40e_flow_parse_attr(attr, error);
4036         if (ret)
4037                 return ret;
4038
4039         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4040
4041         return ret;
4042 }
4043
4044 /* 1. Last in item should be NULL as range is not supported.
4045  * 2. Supported filter types: MPLS label.
4046  * 3. Mask of fields which need to be matched should be
4047  *    filled with 1.
4048  * 4. Mask of fields which needn't to be matched should be
4049  *    filled with 0.
4050  */
4051 static int
4052 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
4053                              const struct rte_flow_item *pattern,
4054                              struct rte_flow_error *error,
4055                              struct i40e_tunnel_filter_conf *filter)
4056 {
4057         const struct rte_flow_item *item = pattern;
4058         const struct rte_flow_item_mpls *mpls_spec;
4059         const struct rte_flow_item_mpls *mpls_mask;
4060         enum rte_flow_item_type item_type;
4061         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
4062         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
4063         uint32_t label_be = 0;
4064
4065         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4066                 if (item->last) {
4067                         rte_flow_error_set(error, EINVAL,
4068                                            RTE_FLOW_ERROR_TYPE_ITEM,
4069                                            item,
4070                                            "Not support range");
4071                         return -rte_errno;
4072                 }
4073                 item_type = item->type;
4074                 switch (item_type) {
4075                 case RTE_FLOW_ITEM_TYPE_ETH:
4076                         if (item->spec || item->mask) {
4077                                 rte_flow_error_set(error, EINVAL,
4078                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4079                                                    item,
4080                                                    "Invalid ETH item");
4081                                 return -rte_errno;
4082                         }
4083                         break;
4084                 case RTE_FLOW_ITEM_TYPE_IPV4:
4085                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4086                         /* IPv4 is used to describe protocol,
4087                          * spec and mask should be NULL.
4088                          */
4089                         if (item->spec || item->mask) {
4090                                 rte_flow_error_set(error, EINVAL,
4091                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4092                                                    item,
4093                                                    "Invalid IPv4 item");
4094                                 return -rte_errno;
4095                         }
4096                         break;
4097                 case RTE_FLOW_ITEM_TYPE_IPV6:
4098                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
4099                         /* IPv6 is used to describe protocol,
4100                          * spec and mask should be NULL.
4101                          */
4102                         if (item->spec || item->mask) {
4103                                 rte_flow_error_set(error, EINVAL,
4104                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4105                                                    item,
4106                                                    "Invalid IPv6 item");
4107                                 return -rte_errno;
4108                         }
4109                         break;
4110                 case RTE_FLOW_ITEM_TYPE_UDP:
4111                         /* UDP is used to describe protocol,
4112                          * spec and mask should be NULL.
4113                          */
4114                         if (item->spec || item->mask) {
4115                                 rte_flow_error_set(error, EINVAL,
4116                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4117                                                    item,
4118                                                    "Invalid UDP item");
4119                                 return -rte_errno;
4120                         }
4121                         is_mplsoudp = 1;
4122                         break;
4123                 case RTE_FLOW_ITEM_TYPE_GRE:
4124                         /* GRE is used to describe protocol,
4125                          * spec and mask should be NULL.
4126                          */
4127                         if (item->spec || item->mask) {
4128                                 rte_flow_error_set(error, EINVAL,
4129                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4130                                                    item,
4131                                                    "Invalid GRE item");
4132                                 return -rte_errno;
4133                         }
4134                         break;
4135                 case RTE_FLOW_ITEM_TYPE_MPLS:
4136                         mpls_spec = item->spec;
4137                         mpls_mask = item->mask;
4138
4139                         if (!mpls_spec || !mpls_mask) {
4140                                 rte_flow_error_set(error, EINVAL,
4141                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4142                                                    item,
4143                                                    "Invalid MPLS item");
4144                                 return -rte_errno;
4145                         }
4146
4147                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
4148                                 rte_flow_error_set(error, EINVAL,
4149                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4150                                                    item,
4151                                                    "Invalid MPLS label mask");
4152                                 return -rte_errno;
4153                         }
4154                         rte_memcpy(((uint8_t *)&label_be + 1),
4155                                    mpls_spec->label_tc_s, 3);
4156                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
4157                         break;
4158                 default:
4159                         break;
4160                 }
4161         }
4162
4163         if (is_mplsoudp)
4164                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
4165         else
4166                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
4167
4168         return 0;
4169 }
4170
4171 static int
4172 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
4173                             const struct rte_flow_attr *attr,
4174                             const struct rte_flow_item pattern[],
4175                             const struct rte_flow_action actions[],
4176                             struct rte_flow_error *error,
4177                             union i40e_filter_t *filter)
4178 {
4179         struct i40e_tunnel_filter_conf *tunnel_filter =
4180                 &filter->consistent_tunnel_filter;
4181         int ret;
4182
4183         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
4184                                            error, tunnel_filter);
4185         if (ret)
4186                 return ret;
4187
4188         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4189         if (ret)
4190                 return ret;
4191
4192         ret = i40e_flow_parse_attr(attr, error);
4193         if (ret)
4194                 return ret;
4195
4196         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4197
4198         return ret;
4199 }
4200
4201 /* 1. Last in item should be NULL as range is not supported.
4202  * 2. Supported filter types: GTP TEID.
4203  * 3. Mask of fields which need to be matched should be
4204  *    filled with 1.
4205  * 4. Mask of fields which needn't to be matched should be
4206  *    filled with 0.
4207  * 5. GTP profile supports GTPv1 only.
4208  * 6. GTP-C response message ('source_port' = 2123) is not supported.
4209  */
4210 static int
4211 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
4212                             const struct rte_flow_item *pattern,
4213                             struct rte_flow_error *error,
4214                             struct i40e_tunnel_filter_conf *filter)
4215 {
4216         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4217         const struct rte_flow_item *item = pattern;
4218         const struct rte_flow_item_gtp *gtp_spec;
4219         const struct rte_flow_item_gtp *gtp_mask;
4220         enum rte_flow_item_type item_type;
4221
4222         if (!pf->gtp_support) {
4223                 rte_flow_error_set(error, EINVAL,
4224                                    RTE_FLOW_ERROR_TYPE_ITEM,
4225                                    item,
4226                                    "GTP is not supported by default.");
4227                 return -rte_errno;
4228         }
4229
4230         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4231                 if (item->last) {
4232                         rte_flow_error_set(error, EINVAL,
4233                                            RTE_FLOW_ERROR_TYPE_ITEM,
4234                                            item,
4235                                            "Not support range");
4236                         return -rte_errno;
4237                 }
4238                 item_type = item->type;
4239                 switch (item_type) {
4240                 case RTE_FLOW_ITEM_TYPE_ETH:
4241                         if (item->spec || item->mask) {
4242                                 rte_flow_error_set(error, EINVAL,
4243                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4244                                                    item,
4245                                                    "Invalid ETH item");
4246                                 return -rte_errno;
4247                         }
4248                         break;
4249                 case RTE_FLOW_ITEM_TYPE_IPV4:
4250                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4251                         /* IPv4 is used to describe protocol,
4252                          * spec and mask should be NULL.
4253                          */
4254                         if (item->spec || item->mask) {
4255                                 rte_flow_error_set(error, EINVAL,
4256                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4257                                                    item,
4258                                                    "Invalid IPv4 item");
4259                                 return -rte_errno;
4260                         }
4261                         break;
4262                 case RTE_FLOW_ITEM_TYPE_UDP:
4263                         if (item->spec || item->mask) {
4264                                 rte_flow_error_set(error, EINVAL,
4265                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4266                                                    item,
4267                                                    "Invalid UDP item");
4268                                 return -rte_errno;
4269                         }
4270                         break;
4271                 case RTE_FLOW_ITEM_TYPE_GTPC:
4272                 case RTE_FLOW_ITEM_TYPE_GTPU:
4273                         gtp_spec = item->spec;
4274                         gtp_mask = item->mask;
4275
4276                         if (!gtp_spec || !gtp_mask) {
4277                                 rte_flow_error_set(error, EINVAL,
4278                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4279                                                    item,
4280                                                    "Invalid GTP item");
4281                                 return -rte_errno;
4282                         }
4283
4284                         if (gtp_mask->v_pt_rsv_flags ||
4285                             gtp_mask->msg_type ||
4286                             gtp_mask->msg_len ||
4287                             gtp_mask->teid != UINT32_MAX) {
4288                                 rte_flow_error_set(error, EINVAL,
4289                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4290                                                    item,
4291                                                    "Invalid GTP mask");
4292                                 return -rte_errno;
4293                         }
4294
4295                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4296                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4297                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4298                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4299
4300                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4301
4302                         break;
4303                 default:
4304                         break;
4305                 }
4306         }
4307
4308         return 0;
4309 }
4310
4311 static int
4312 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4313                            const struct rte_flow_attr *attr,
4314                            const struct rte_flow_item pattern[],
4315                            const struct rte_flow_action actions[],
4316                            struct rte_flow_error *error,
4317                            union i40e_filter_t *filter)
4318 {
4319         struct i40e_tunnel_filter_conf *tunnel_filter =
4320                 &filter->consistent_tunnel_filter;
4321         int ret;
4322
4323         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4324                                           error, tunnel_filter);
4325         if (ret)
4326                 return ret;
4327
4328         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4329         if (ret)
4330                 return ret;
4331
4332         ret = i40e_flow_parse_attr(attr, error);
4333         if (ret)
4334                 return ret;
4335
4336         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4337
4338         return ret;
4339 }
4340
4341 /* 1. Last in item should be NULL as range is not supported.
4342  * 2. Supported filter types: QINQ.
4343  * 3. Mask of fields which need to be matched should be
4344  *    filled with 1.
4345  * 4. Mask of fields which needn't to be matched should be
4346  *    filled with 0.
4347  */
4348 static int
4349 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4350                               const struct rte_flow_item *pattern,
4351                               struct rte_flow_error *error,
4352                               struct i40e_tunnel_filter_conf *filter)
4353 {
4354         const struct rte_flow_item *item = pattern;
4355         const struct rte_flow_item_vlan *vlan_spec = NULL;
4356         const struct rte_flow_item_vlan *vlan_mask = NULL;
4357         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4358         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4359         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4360         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4361
4362         enum rte_flow_item_type item_type;
4363         bool vlan_flag = 0;
4364
4365         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4366                 if (item->last) {
4367                         rte_flow_error_set(error, EINVAL,
4368                                            RTE_FLOW_ERROR_TYPE_ITEM,
4369                                            item,
4370                                            "Not support range");
4371                         return -rte_errno;
4372                 }
4373                 item_type = item->type;
4374                 switch (item_type) {
4375                 case RTE_FLOW_ITEM_TYPE_ETH:
4376                         if (item->spec || item->mask) {
4377                                 rte_flow_error_set(error, EINVAL,
4378                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4379                                                    item,
4380                                                    "Invalid ETH item");
4381                                 return -rte_errno;
4382                         }
4383                         break;
4384                 case RTE_FLOW_ITEM_TYPE_VLAN:
4385                         vlan_spec = item->spec;
4386                         vlan_mask = item->mask;
4387
4388                         if (!(vlan_spec && vlan_mask) ||
4389                             vlan_mask->inner_type) {
4390                                 rte_flow_error_set(error, EINVAL,
4391                                            RTE_FLOW_ERROR_TYPE_ITEM,
4392                                            item,
4393                                            "Invalid vlan item");
4394                                 return -rte_errno;
4395                         }
4396
4397                         if (!vlan_flag) {
4398                                 o_vlan_spec = vlan_spec;
4399                                 o_vlan_mask = vlan_mask;
4400                                 vlan_flag = 1;
4401                         } else {
4402                                 i_vlan_spec = vlan_spec;
4403                                 i_vlan_mask = vlan_mask;
4404                                 vlan_flag = 0;
4405                         }
4406                         break;
4407
4408                 default:
4409                         break;
4410                 }
4411         }
4412
4413         /* Get filter specification */
4414         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4415                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4416                         (i_vlan_mask != NULL) &&
4417                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4418                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4419                         & I40E_TCI_MASK;
4420                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4421                         & I40E_TCI_MASK;
4422         } else {
4423                         rte_flow_error_set(error, EINVAL,
4424                                            RTE_FLOW_ERROR_TYPE_ITEM,
4425                                            NULL,
4426                                            "Invalid filter type");
4427                         return -rte_errno;
4428         }
4429
4430         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4431         return 0;
4432 }
4433
4434 static int
4435 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4436                               const struct rte_flow_attr *attr,
4437                               const struct rte_flow_item pattern[],
4438                               const struct rte_flow_action actions[],
4439                               struct rte_flow_error *error,
4440                               union i40e_filter_t *filter)
4441 {
4442         struct i40e_tunnel_filter_conf *tunnel_filter =
4443                 &filter->consistent_tunnel_filter;
4444         int ret;
4445
4446         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4447                                              error, tunnel_filter);
4448         if (ret)
4449                 return ret;
4450
4451         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4452         if (ret)
4453                 return ret;
4454
4455         ret = i40e_flow_parse_attr(attr, error);
4456         if (ret)
4457                 return ret;
4458
4459         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4460
4461         return ret;
4462 }
4463
4464 /**
4465  * This function is used to do configuration i40e existing RSS with rte_flow.
4466  * It also enable queue region configuration using flow API for i40e.
4467  * pattern can be used indicate what parameters will be include in flow,
4468  * like user_priority or flowtype for queue region or HASH function for RSS.
4469  * Action is used to transmit parameter like queue index and HASH
4470  * function for RSS, or flowtype for queue region configuration.
4471  * For example:
4472  * pattern:
4473  * Case 1: try to transform patterns to pctype. valid pctype will be
4474  *         used in parse action.
4475  * Case 2: only ETH, indicate flowtype for queue region will be parsed.
4476  * Case 3: only VLAN, indicate user_priority for queue region will be parsed.
4477  * So, pattern choice is depened on the purpose of configuration of
4478  * that flow.
4479  * action:
4480  * action RSS will be used to transmit valid parameter with
4481  * struct rte_flow_action_rss for all the 3 case.
4482  */
4483 static int
4484 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4485                              const struct rte_flow_item *pattern,
4486                              struct rte_flow_error *error,
4487                              struct i40e_rss_pattern_info *p_info,
4488                              struct i40e_queue_regions *info)
4489 {
4490         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4491         const struct rte_flow_item *item = pattern;
4492         enum rte_flow_item_type item_type;
4493         struct rte_flow_item *items;
4494         uint32_t item_num = 0; /* non-void item number of pattern*/
4495         uint32_t i = 0;
4496         static const struct {
4497                 enum rte_flow_item_type *item_array;
4498                 uint64_t type;
4499         } i40e_rss_pctype_patterns[] = {
4500                 { pattern_fdir_ipv4,
4501                         ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER },
4502                 { pattern_fdir_ipv4_tcp, ETH_RSS_NONFRAG_IPV4_TCP },
4503                 { pattern_fdir_ipv4_udp, ETH_RSS_NONFRAG_IPV4_UDP },
4504                 { pattern_fdir_ipv4_sctp, ETH_RSS_NONFRAG_IPV4_SCTP },
4505                 { pattern_fdir_ipv4_esp, ETH_RSS_ESP },
4506                 { pattern_fdir_ipv4_udp_esp, ETH_RSS_ESP },
4507                 { pattern_fdir_ipv6,
4508                         ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER },
4509                 { pattern_fdir_ipv6_tcp, ETH_RSS_NONFRAG_IPV6_TCP },
4510                 { pattern_fdir_ipv6_udp, ETH_RSS_NONFRAG_IPV6_UDP },
4511                 { pattern_fdir_ipv6_sctp, ETH_RSS_NONFRAG_IPV6_SCTP },
4512                 { pattern_fdir_ipv6_esp, ETH_RSS_ESP },
4513                 { pattern_fdir_ipv6_udp_esp, ETH_RSS_ESP },
4514         };
4515
4516         p_info->types = I40E_RSS_TYPE_INVALID;
4517
4518         if (item->type == RTE_FLOW_ITEM_TYPE_END) {
4519                 p_info->types = I40E_RSS_TYPE_NONE;
4520                 return 0;
4521         }
4522
4523         /* Convert pattern to RSS offload types */
4524         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4525                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4526                         item_num++;
4527                 i++;
4528         }
4529         item_num++;
4530
4531         items = rte_zmalloc("i40e_pattern",
4532                             item_num * sizeof(struct rte_flow_item), 0);
4533         if (!items) {
4534                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4535                                    NULL, "No memory for PMD internal items.");
4536                 return -ENOMEM;
4537         }
4538
4539         i40e_pattern_skip_void_item(items, pattern);
4540
4541         for (i = 0; i < RTE_DIM(i40e_rss_pctype_patterns); i++) {
4542                 if (i40e_match_pattern(i40e_rss_pctype_patterns[i].item_array,
4543                                         items)) {
4544                         p_info->types = i40e_rss_pctype_patterns[i].type;
4545                         rte_free(items);
4546                         return 0;
4547                 }
4548         }
4549
4550         rte_free(items);
4551
4552         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4553                 if (item->last) {
4554                         rte_flow_error_set(error, EINVAL,
4555                                            RTE_FLOW_ERROR_TYPE_ITEM,
4556                                            item,
4557                                            "Not support range");
4558                         return -rte_errno;
4559                 }
4560                 item_type = item->type;
4561                 switch (item_type) {
4562                 case RTE_FLOW_ITEM_TYPE_ETH:
4563                         p_info->action_flag = 1;
4564                         break;
4565                 case RTE_FLOW_ITEM_TYPE_VLAN:
4566                         vlan_spec = item->spec;
4567                         vlan_mask = item->mask;
4568                         if (vlan_spec && vlan_mask) {
4569                                 if (vlan_mask->tci ==
4570                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4571                                         info->region[0].user_priority[0] =
4572                                                 (rte_be_to_cpu_16(
4573                                                 vlan_spec->tci) >> 13) & 0x7;
4574                                         info->region[0].user_priority_num = 1;
4575                                         info->queue_region_number = 1;
4576                                         p_info->action_flag = 0;
4577                                 }
4578                         }
4579                         break;
4580                 default:
4581                         rte_flow_error_set(error, EINVAL,
4582                                         RTE_FLOW_ERROR_TYPE_ITEM,
4583                                         item,
4584                                         "Not support range");
4585                         return -rte_errno;
4586                 }
4587         }
4588
4589         return 0;
4590 }
4591
4592 /**
4593  * This function is used to parse RSS queue index, total queue number and
4594  * hash functions, If the purpose of this configuration is for queue region
4595  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4596  * In queue region configuration, it also need to parse hardware flowtype
4597  * and user_priority from configuration, it will also cheeck the validity
4598  * of these parameters. For example, The queue region sizes should
4599  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4600  * hw_flowtype or PCTYPE max index should be 63, the user priority
4601  * max index should be 7, and so on. And also, queue index should be
4602  * continuous sequence and queue region index should be part of RSS
4603  * queue index for this port.
4604  * For hash params, the pctype in action and pattern must be same.
4605  * Set queue index must be with non-types.
4606  */
4607 static int
4608 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4609                             const struct rte_flow_action *actions,
4610                             struct rte_flow_error *error,
4611                                 struct i40e_rss_pattern_info p_info,
4612                             struct i40e_queue_regions *conf_info,
4613                             union i40e_filter_t *filter)
4614 {
4615         const struct rte_flow_action *act;
4616         const struct rte_flow_action_rss *rss;
4617         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4618         struct i40e_queue_regions *info = &pf->queue_region;
4619         struct i40e_rte_flow_rss_conf *rss_config =
4620                         &filter->rss_conf;
4621         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4622         uint16_t i, j, n, tmp, nb_types;
4623         uint32_t index = 0;
4624         uint64_t hf_bit = 1;
4625
4626         NEXT_ITEM_OF_ACTION(act, actions, index);
4627         rss = act->conf;
4628
4629         /**
4630          * RSS only supports forwarding,
4631          * check if the first not void action is RSS.
4632          */
4633         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4634                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4635                 rte_flow_error_set(error, EINVAL,
4636                         RTE_FLOW_ERROR_TYPE_ACTION,
4637                         act, "Not supported action.");
4638                 return -rte_errno;
4639         }
4640
4641         if (p_info.action_flag) {
4642                 for (n = 0; n < 64; n++) {
4643                         if (rss->types & (hf_bit << n)) {
4644                                 conf_info->region[0].hw_flowtype[0] = n;
4645                                 conf_info->region[0].flowtype_num = 1;
4646                                 conf_info->queue_region_number = 1;
4647                                 break;
4648                         }
4649                 }
4650         }
4651
4652         /**
4653          * Do some queue region related parameters check
4654          * in order to keep queue index for queue region to be
4655          * continuous sequence and also to be part of RSS
4656          * queue index for this port.
4657          */
4658         if (conf_info->queue_region_number) {
4659                 for (i = 0; i < rss->queue_num; i++) {
4660                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4661                                 if (rss->queue[i] == rss_info->conf.queue[j])
4662                                         break;
4663                         }
4664                         if (j == rss_info->conf.queue_num) {
4665                                 rte_flow_error_set(error, EINVAL,
4666                                         RTE_FLOW_ERROR_TYPE_ACTION,
4667                                         act,
4668                                         "no valid queues");
4669                                 return -rte_errno;
4670                         }
4671                 }
4672
4673                 for (i = 0; i < rss->queue_num - 1; i++) {
4674                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4675                                 rte_flow_error_set(error, EINVAL,
4676                                         RTE_FLOW_ERROR_TYPE_ACTION,
4677                                         act,
4678                                         "no valid queues");
4679                                 return -rte_errno;
4680                         }
4681                 }
4682         }
4683
4684         /* Parse queue region related parameters from configuration */
4685         for (n = 0; n < conf_info->queue_region_number; n++) {
4686                 if (conf_info->region[n].user_priority_num ||
4687                                 conf_info->region[n].flowtype_num) {
4688                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4689                                         rss->queue_num <= 64)) {
4690                                 rte_flow_error_set(error, EINVAL,
4691                                         RTE_FLOW_ERROR_TYPE_ACTION,
4692                                         act,
4693                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4694                                         "total number of queues do not exceed the VSI allocation");
4695                                 return -rte_errno;
4696                         }
4697
4698                         if (conf_info->region[n].user_priority[n] >=
4699                                         I40E_MAX_USER_PRIORITY) {
4700                                 rte_flow_error_set(error, EINVAL,
4701                                         RTE_FLOW_ERROR_TYPE_ACTION,
4702                                         act,
4703                                         "the user priority max index is 7");
4704                                 return -rte_errno;
4705                         }
4706
4707                         if (conf_info->region[n].hw_flowtype[n] >=
4708                                         I40E_FILTER_PCTYPE_MAX) {
4709                                 rte_flow_error_set(error, EINVAL,
4710                                         RTE_FLOW_ERROR_TYPE_ACTION,
4711                                         act,
4712                                         "the hw_flowtype or PCTYPE max index is 63");
4713                                 return -rte_errno;
4714                         }
4715
4716                         for (i = 0; i < info->queue_region_number; i++) {
4717                                 if (info->region[i].queue_num ==
4718                                     rss->queue_num &&
4719                                         info->region[i].queue_start_index ==
4720                                                 rss->queue[0])
4721                                         break;
4722                         }
4723
4724                         if (i == info->queue_region_number) {
4725                                 if (i > I40E_REGION_MAX_INDEX) {
4726                                         rte_flow_error_set(error, EINVAL,
4727                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4728                                                 act,
4729                                                 "the queue region max index is 7");
4730                                         return -rte_errno;
4731                                 }
4732
4733                                 info->region[i].queue_num =
4734                                         rss->queue_num;
4735                                 info->region[i].queue_start_index =
4736                                         rss->queue[0];
4737                                 info->region[i].region_id =
4738                                         info->queue_region_number;
4739
4740                                 j = info->region[i].user_priority_num;
4741                                 tmp = conf_info->region[n].user_priority[0];
4742                                 if (conf_info->region[n].user_priority_num) {
4743                                         info->region[i].user_priority[j] = tmp;
4744                                         info->region[i].user_priority_num++;
4745                                 }
4746
4747                                 j = info->region[i].flowtype_num;
4748                                 tmp = conf_info->region[n].hw_flowtype[0];
4749                                 if (conf_info->region[n].flowtype_num) {
4750                                         info->region[i].hw_flowtype[j] = tmp;
4751                                         info->region[i].flowtype_num++;
4752                                 }
4753                                 info->queue_region_number++;
4754                         } else {
4755                                 j = info->region[i].user_priority_num;
4756                                 tmp = conf_info->region[n].user_priority[0];
4757                                 if (conf_info->region[n].user_priority_num) {
4758                                         info->region[i].user_priority[j] = tmp;
4759                                         info->region[i].user_priority_num++;
4760                                 }
4761
4762                                 j = info->region[i].flowtype_num;
4763                                 tmp = conf_info->region[n].hw_flowtype[0];
4764                                 if (conf_info->region[n].flowtype_num) {
4765                                         info->region[i].hw_flowtype[j] = tmp;
4766                                         info->region[i].flowtype_num++;
4767                                 }
4768                         }
4769                 }
4770
4771                 rss_config->queue_region_conf = TRUE;
4772         }
4773
4774         /**
4775          * Return function if this flow is used for queue region configuration
4776          */
4777         if (rss_config->queue_region_conf)
4778                 return 0;
4779
4780         if (!rss) {
4781                 rte_flow_error_set(error, EINVAL,
4782                                 RTE_FLOW_ERROR_TYPE_ACTION,
4783                                 act,
4784                                 "invalid rule");
4785                 return -rte_errno;
4786         }
4787
4788         for (n = 0; n < rss->queue_num; n++) {
4789                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4790                         rte_flow_error_set(error, EINVAL,
4791                                    RTE_FLOW_ERROR_TYPE_ACTION,
4792                                    act,
4793                                    "queue id > max number of queues");
4794                         return -rte_errno;
4795                 }
4796         }
4797
4798         if (rss->queue_num && (p_info.types || rss->types))
4799                 return rte_flow_error_set
4800                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4801                          "RSS types must be empty while configuring queue region");
4802
4803         /* validate pattern and pctype */
4804         if (!(rss->types & p_info.types) &&
4805             (rss->types || p_info.types) && !rss->queue_num)
4806                 return rte_flow_error_set
4807                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
4808                          act, "invalid pctype");
4809
4810         nb_types = 0;
4811         for (n = 0; n < RTE_ETH_FLOW_MAX; n++) {
4812                 if (rss->types & (hf_bit << n))
4813                         nb_types++;
4814                 if (nb_types > 1)
4815                         return rte_flow_error_set
4816                                 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
4817                                  act, "multi pctype is not supported");
4818         }
4819
4820         if (rss->func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
4821             (p_info.types || rss->types || rss->queue_num))
4822                 return rte_flow_error_set
4823                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4824                          "pattern, type and queues must be empty while"
4825                          " setting hash function as simple_xor");
4826
4827         if (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ &&
4828             !(p_info.types && rss->types))
4829                 return rte_flow_error_set
4830                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4831                          "pctype and queues can not be empty while"
4832                          " setting hash function as symmetric toeplitz");
4833
4834         /* Parse RSS related parameters from configuration */
4835         if (rss->func >= RTE_ETH_HASH_FUNCTION_MAX ||
4836             rss->func == RTE_ETH_HASH_FUNCTION_TOEPLITZ)
4837                 return rte_flow_error_set
4838                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4839                          "RSS hash functions are not supported");
4840         if (rss->level)
4841                 return rte_flow_error_set
4842                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4843                          "a nonzero RSS encapsulation level is not supported");
4844         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4845                 return rte_flow_error_set
4846                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4847                          "RSS hash key too large");
4848         if (rss->queue_num > RTE_DIM(rss_config->queue))
4849                 return rte_flow_error_set
4850                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4851                          "too many queues for RSS context");
4852         if (i40e_rss_conf_init(rss_config, rss))
4853                 return rte_flow_error_set
4854                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4855                          "RSS context initialization failure");
4856
4857         index++;
4858
4859         /* check if the next not void action is END */
4860         NEXT_ITEM_OF_ACTION(act, actions, index);
4861         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4862                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4863                 rte_flow_error_set(error, EINVAL,
4864                         RTE_FLOW_ERROR_TYPE_ACTION,
4865                         act, "Not supported action.");
4866                 return -rte_errno;
4867         }
4868         rss_config->queue_region_conf = FALSE;
4869
4870         return 0;
4871 }
4872
4873 static int
4874 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4875                         const struct rte_flow_attr *attr,
4876                         const struct rte_flow_item pattern[],
4877                         const struct rte_flow_action actions[],
4878                         union i40e_filter_t *filter,
4879                         struct rte_flow_error *error)
4880 {
4881         struct i40e_rss_pattern_info p_info;
4882         struct i40e_queue_regions info;
4883         int ret;
4884
4885         memset(&info, 0, sizeof(struct i40e_queue_regions));
4886         memset(&p_info, 0, sizeof(struct i40e_rss_pattern_info));
4887
4888         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4889                                         error, &p_info, &info);
4890         if (ret)
4891                 return ret;
4892
4893         ret = i40e_flow_parse_rss_action(dev, actions, error,
4894                                         p_info, &info, filter);
4895         if (ret)
4896                 return ret;
4897
4898         ret = i40e_flow_parse_attr(attr, error);
4899         if (ret)
4900                 return ret;
4901
4902         cons_filter_type = RTE_ETH_FILTER_HASH;
4903
4904         return 0;
4905 }
4906
4907 static int
4908 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4909                 struct i40e_rte_flow_rss_conf *conf)
4910 {
4911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         struct i40e_rss_filter *rss_filter;
4914         int ret;
4915
4916         if (conf->queue_region_conf) {
4917                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4918         } else {
4919                 ret = i40e_config_rss_filter(pf, conf, 1);
4920         }
4921
4922         if (ret)
4923                 return ret;
4924
4925         rss_filter = rte_zmalloc("i40e_rss_filter",
4926                                 sizeof(*rss_filter), 0);
4927         if (rss_filter == NULL) {
4928                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4929                 return -ENOMEM;
4930         }
4931         rss_filter->rss_filter_info = *conf;
4932         /* the rule new created is always valid
4933          * the existing rule covered by new rule will be set invalid
4934          */
4935         rss_filter->rss_filter_info.valid = true;
4936
4937         TAILQ_INSERT_TAIL(&pf->rss_config_list, rss_filter, next);
4938
4939         return 0;
4940 }
4941
4942 static int
4943 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4944                 struct i40e_rte_flow_rss_conf *conf)
4945 {
4946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4948         struct i40e_rss_filter *rss_filter;
4949         void *temp;
4950
4951         if (conf->queue_region_conf)
4952                 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4953         else
4954                 i40e_config_rss_filter(pf, conf, 0);
4955
4956         TAILQ_FOREACH_SAFE(rss_filter, &pf->rss_config_list, next, temp) {
4957                 if (!memcmp(&rss_filter->rss_filter_info, conf,
4958                         sizeof(struct rte_flow_action_rss))) {
4959                         TAILQ_REMOVE(&pf->rss_config_list, rss_filter, next);
4960                         rte_free(rss_filter);
4961                 }
4962         }
4963         return 0;
4964 }
4965
4966 static int
4967 i40e_flow_validate(struct rte_eth_dev *dev,
4968                    const struct rte_flow_attr *attr,
4969                    const struct rte_flow_item pattern[],
4970                    const struct rte_flow_action actions[],
4971                    struct rte_flow_error *error)
4972 {
4973         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4974         parse_filter_t parse_filter;
4975         uint32_t item_num = 0; /* non-void item number of pattern*/
4976         uint32_t i = 0;
4977         bool flag = false;
4978         int ret = I40E_NOT_SUPPORTED;
4979
4980         if (!pattern) {
4981                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4982                                    NULL, "NULL pattern.");
4983                 return -rte_errno;
4984         }
4985
4986         if (!actions) {
4987                 rte_flow_error_set(error, EINVAL,
4988                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4989                                    NULL, "NULL action.");
4990                 return -rte_errno;
4991         }
4992
4993         if (!attr) {
4994                 rte_flow_error_set(error, EINVAL,
4995                                    RTE_FLOW_ERROR_TYPE_ATTR,
4996                                    NULL, "NULL attribute.");
4997                 return -rte_errno;
4998         }
4999
5000         memset(&cons_filter, 0, sizeof(cons_filter));
5001
5002         /* Get the non-void item of action */
5003         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
5004                 i++;
5005
5006         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
5007                 ret = i40e_parse_rss_filter(dev, attr, pattern,
5008                                         actions, &cons_filter, error);
5009                 return ret;
5010         }
5011
5012         i = 0;
5013         /* Get the non-void item number of pattern */
5014         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
5015                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
5016                         item_num++;
5017                 i++;
5018         }
5019         item_num++;
5020
5021         items = rte_zmalloc("i40e_pattern",
5022                             item_num * sizeof(struct rte_flow_item), 0);
5023         if (!items) {
5024                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
5025                                    NULL, "No memory for PMD internal items.");
5026                 return -ENOMEM;
5027         }
5028
5029         i40e_pattern_skip_void_item(items, pattern);
5030
5031         i = 0;
5032         do {
5033                 parse_filter = i40e_find_parse_filter_func(items, &i);
5034                 if (!parse_filter && !flag) {
5035                         rte_flow_error_set(error, EINVAL,
5036                                            RTE_FLOW_ERROR_TYPE_ITEM,
5037                                            pattern, "Unsupported pattern");
5038                         rte_free(items);
5039                         return -rte_errno;
5040                 }
5041                 if (parse_filter)
5042                         ret = parse_filter(dev, attr, items, actions,
5043                                            error, &cons_filter);
5044                 flag = true;
5045         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
5046
5047         rte_free(items);
5048
5049         return ret;
5050 }
5051
5052 static struct rte_flow *
5053 i40e_flow_create(struct rte_eth_dev *dev,
5054                  const struct rte_flow_attr *attr,
5055                  const struct rte_flow_item pattern[],
5056                  const struct rte_flow_action actions[],
5057                  struct rte_flow_error *error)
5058 {
5059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5060         struct rte_flow *flow;
5061         int ret;
5062
5063         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
5064         if (!flow) {
5065                 rte_flow_error_set(error, ENOMEM,
5066                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5067                                    "Failed to allocate memory");
5068                 return flow;
5069         }
5070
5071         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
5072         if (ret < 0)
5073                 return NULL;
5074
5075         switch (cons_filter_type) {
5076         case RTE_ETH_FILTER_ETHERTYPE:
5077                 ret = i40e_ethertype_filter_set(pf,
5078                                         &cons_filter.ethertype_filter, 1);
5079                 if (ret)
5080                         goto free_flow;
5081                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
5082                                         i40e_ethertype_filter_list);
5083                 break;
5084         case RTE_ETH_FILTER_FDIR:
5085                 ret = i40e_flow_add_del_fdir_filter(dev,
5086                                        &cons_filter.fdir_filter, 1);
5087                 if (ret)
5088                         goto free_flow;
5089                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
5090                                         i40e_fdir_filter_list);
5091                 break;
5092         case RTE_ETH_FILTER_TUNNEL:
5093                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
5094                             &cons_filter.consistent_tunnel_filter, 1);
5095                 if (ret)
5096                         goto free_flow;
5097                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
5098                                         i40e_tunnel_filter_list);
5099                 break;
5100         case RTE_ETH_FILTER_HASH:
5101                 ret = i40e_config_rss_filter_set(dev,
5102                             &cons_filter.rss_conf);
5103                 if (ret)
5104                         goto free_flow;
5105                 flow->rule = TAILQ_LAST(&pf->rss_config_list,
5106                                 i40e_rss_conf_list);
5107                 break;
5108         default:
5109                 goto free_flow;
5110         }
5111
5112         flow->filter_type = cons_filter_type;
5113         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
5114         return flow;
5115
5116 free_flow:
5117         rte_flow_error_set(error, -ret,
5118                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5119                            "Failed to create flow.");
5120         rte_free(flow);
5121         return NULL;
5122 }
5123
5124 static int
5125 i40e_flow_destroy(struct rte_eth_dev *dev,
5126                   struct rte_flow *flow,
5127                   struct rte_flow_error *error)
5128 {
5129         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5130         enum rte_filter_type filter_type = flow->filter_type;
5131         int ret = 0;
5132
5133         switch (filter_type) {
5134         case RTE_ETH_FILTER_ETHERTYPE:
5135                 ret = i40e_flow_destroy_ethertype_filter(pf,
5136                          (struct i40e_ethertype_filter *)flow->rule);
5137                 break;
5138         case RTE_ETH_FILTER_TUNNEL:
5139                 ret = i40e_flow_destroy_tunnel_filter(pf,
5140                               (struct i40e_tunnel_filter *)flow->rule);
5141                 break;
5142         case RTE_ETH_FILTER_FDIR:
5143                 ret = i40e_flow_add_del_fdir_filter(dev,
5144                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
5145
5146                 /* If the last flow is destroyed, disable fdir. */
5147                 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) {
5148                         i40e_fdir_rx_proc_enable(dev, 0);
5149                 }
5150                 break;
5151         case RTE_ETH_FILTER_HASH:
5152                 ret = i40e_config_rss_filter_del(dev,
5153                         &((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
5154                 break;
5155         default:
5156                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5157                             filter_type);
5158                 ret = -EINVAL;
5159                 break;
5160         }
5161
5162         if (!ret) {
5163                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5164                 rte_free(flow);
5165         } else
5166                 rte_flow_error_set(error, -ret,
5167                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5168                                    "Failed to destroy flow.");
5169
5170         return ret;
5171 }
5172
5173 static int
5174 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
5175                                    struct i40e_ethertype_filter *filter)
5176 {
5177         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5178         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
5179         struct i40e_ethertype_filter *node;
5180         struct i40e_control_filter_stats stats;
5181         uint16_t flags = 0;
5182         int ret = 0;
5183
5184         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5185                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5186         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5187                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5188         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5189
5190         memset(&stats, 0, sizeof(stats));
5191         ret = i40e_aq_add_rem_control_packet_filter(hw,
5192                                     filter->input.mac_addr.addr_bytes,
5193                                     filter->input.ether_type,
5194                                     flags, pf->main_vsi->seid,
5195                                     filter->queue, 0, &stats, NULL);
5196         if (ret < 0)
5197                 return ret;
5198
5199         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
5200         if (!node)
5201                 return -EINVAL;
5202
5203         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
5204
5205         return ret;
5206 }
5207
5208 static int
5209 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
5210                                 struct i40e_tunnel_filter *filter)
5211 {
5212         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5213         struct i40e_vsi *vsi;
5214         struct i40e_pf_vf *vf;
5215         struct i40e_aqc_cloud_filters_element_bb cld_filter;
5216         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
5217         struct i40e_tunnel_filter *node;
5218         bool big_buffer = 0;
5219         int ret = 0;
5220
5221         memset(&cld_filter, 0, sizeof(cld_filter));
5222         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
5223                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
5224         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
5225                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
5226         cld_filter.element.inner_vlan = filter->input.inner_vlan;
5227         cld_filter.element.flags = filter->input.flags;
5228         cld_filter.element.tenant_id = filter->input.tenant_id;
5229         cld_filter.element.queue_number = filter->queue;
5230         rte_memcpy(cld_filter.general_fields,
5231                    filter->input.general_fields,
5232                    sizeof(cld_filter.general_fields));
5233
5234         if (!filter->is_to_vf)
5235                 vsi = pf->main_vsi;
5236         else {
5237                 vf = &pf->vfs[filter->vf_id];
5238                 vsi = vf->vsi;
5239         }
5240
5241         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
5242             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
5243             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
5244             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
5245             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
5246             I40E_AQC_ADD_CLOUD_FILTER_0X10))
5247                 big_buffer = 1;
5248
5249         if (big_buffer)
5250                 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
5251                                                 &cld_filter, 1);
5252         else
5253                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
5254                                                 &cld_filter.element, 1);
5255         if (ret < 0)
5256                 return -ENOTSUP;
5257
5258         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
5259         if (!node)
5260                 return -EINVAL;
5261
5262         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
5263
5264         return ret;
5265 }
5266
5267 static int
5268 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
5269 {
5270         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5271         int ret;
5272
5273         ret = i40e_flow_flush_fdir_filter(pf);
5274         if (ret) {
5275                 rte_flow_error_set(error, -ret,
5276                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5277                                    "Failed to flush FDIR flows.");
5278                 return -rte_errno;
5279         }
5280
5281         ret = i40e_flow_flush_ethertype_filter(pf);
5282         if (ret) {
5283                 rte_flow_error_set(error, -ret,
5284                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5285                                    "Failed to ethertype flush flows.");
5286                 return -rte_errno;
5287         }
5288
5289         ret = i40e_flow_flush_tunnel_filter(pf);
5290         if (ret) {
5291                 rte_flow_error_set(error, -ret,
5292                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5293                                    "Failed to flush tunnel flows.");
5294                 return -rte_errno;
5295         }
5296
5297         ret = i40e_flow_flush_rss_filter(dev);
5298         if (ret) {
5299                 rte_flow_error_set(error, -ret,
5300                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5301                                    "Failed to flush RSS flows.");
5302                 return -rte_errno;
5303         }
5304
5305         /* Disable FDIR processing as all FDIR rules are now flushed */
5306         i40e_fdir_rx_proc_enable(dev, 0);
5307
5308         return ret;
5309 }
5310
5311 static int
5312 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
5313 {
5314         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5315         struct i40e_fdir_info *fdir_info = &pf->fdir;
5316         struct i40e_fdir_filter *fdir_filter;
5317         enum i40e_filter_pctype pctype;
5318         struct rte_flow *flow;
5319         void *temp;
5320         int ret;
5321
5322         ret = i40e_fdir_flush(dev);
5323         if (!ret) {
5324                 /* Delete FDIR filters in FDIR list. */
5325                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
5326                         ret = i40e_sw_fdir_filter_del(pf,
5327                                                       &fdir_filter->fdir.input);
5328                         if (ret < 0)
5329                                 return ret;
5330                 }
5331
5332                 /* Delete FDIR flows in flow list. */
5333                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5334                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
5335                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5336                                 rte_free(flow);
5337                         }
5338                 }
5339
5340                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5341                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
5342                         pf->fdir.inset_flag[pctype] = 0;
5343         }
5344
5345         return ret;
5346 }
5347
5348 /* Flush all ethertype filters */
5349 static int
5350 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
5351 {
5352         struct i40e_ethertype_filter_list
5353                 *ethertype_list = &pf->ethertype.ethertype_list;
5354         struct i40e_ethertype_filter *filter;
5355         struct rte_flow *flow;
5356         void *temp;
5357         int ret = 0;
5358
5359         while ((filter = TAILQ_FIRST(ethertype_list))) {
5360                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
5361                 if (ret)
5362                         return ret;
5363         }
5364
5365         /* Delete ethertype flows in flow list. */
5366         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5367                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
5368                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5369                         rte_free(flow);
5370                 }
5371         }
5372
5373         return ret;
5374 }
5375
5376 /* Flush all tunnel filters */
5377 static int
5378 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5379 {
5380         struct i40e_tunnel_filter_list
5381                 *tunnel_list = &pf->tunnel.tunnel_list;
5382         struct i40e_tunnel_filter *filter;
5383         struct rte_flow *flow;
5384         void *temp;
5385         int ret = 0;
5386
5387         while ((filter = TAILQ_FIRST(tunnel_list))) {
5388                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5389                 if (ret)
5390                         return ret;
5391         }
5392
5393         /* Delete tunnel flows in flow list. */
5394         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5395                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5396                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5397                         rte_free(flow);
5398                 }
5399         }
5400
5401         return ret;
5402 }
5403
5404 /* remove the RSS filter */
5405 static int
5406 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5407 {
5408         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5409         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5410         struct rte_flow *flow;
5411         void *temp;
5412         int32_t ret = -EINVAL;
5413
5414         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5415
5416         /* Delete RSS flows in flow list. */
5417         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5418                 if (flow->filter_type != RTE_ETH_FILTER_HASH)
5419                         continue;
5420
5421                 if (flow->rule) {
5422                         ret = i40e_config_rss_filter_del(dev,
5423                                 &((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
5424                         if (ret)
5425                                 return ret;
5426                 }
5427                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5428                 rte_free(flow);
5429         }
5430
5431         return ret;
5432 }