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33 #include <sys/queue.h>
41 #include <rte_ether.h>
42 #include <rte_ethdev.h>
44 #include <rte_malloc.h>
45 #include <rte_eth_ctrl.h>
46 #include <rte_tailq.h>
47 #include <rte_flow_driver.h>
49 #include "i40e_logs.h"
50 #include "base/i40e_type.h"
51 #include "base/i40e_prototype.h"
52 #include "i40e_ethdev.h"
54 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
55 #define I40E_IPV6_FRAG_HEADER 44
56 #define I40E_TENANT_ARRAY_NUM 3
57 #define I40E_TCI_MASK 0xFFFF
59 static int i40e_flow_validate(struct rte_eth_dev *dev,
60 const struct rte_flow_attr *attr,
61 const struct rte_flow_item pattern[],
62 const struct rte_flow_action actions[],
63 struct rte_flow_error *error);
64 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
65 const struct rte_flow_attr *attr,
66 const struct rte_flow_item pattern[],
67 const struct rte_flow_action actions[],
68 struct rte_flow_error *error);
69 static int i40e_flow_destroy(struct rte_eth_dev *dev,
70 struct rte_flow *flow,
71 struct rte_flow_error *error);
72 static int i40e_flow_flush(struct rte_eth_dev *dev,
73 struct rte_flow_error *error);
75 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
76 const struct rte_flow_item *pattern,
77 struct rte_flow_error *error,
78 struct rte_eth_ethertype_filter *filter);
79 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
80 const struct rte_flow_action *actions,
81 struct rte_flow_error *error,
82 struct rte_eth_ethertype_filter *filter);
83 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
84 const struct rte_flow_item *pattern,
85 struct rte_flow_error *error,
86 struct i40e_fdir_filter_conf *filter);
87 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
88 const struct rte_flow_action *actions,
89 struct rte_flow_error *error,
90 struct i40e_fdir_filter_conf *filter);
91 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
92 const struct rte_flow_action *actions,
93 struct rte_flow_error *error,
94 struct i40e_tunnel_filter_conf *filter);
95 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
96 struct rte_flow_error *error);
97 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
98 const struct rte_flow_attr *attr,
99 const struct rte_flow_item pattern[],
100 const struct rte_flow_action actions[],
101 struct rte_flow_error *error,
102 union i40e_filter_t *filter);
103 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
104 const struct rte_flow_attr *attr,
105 const struct rte_flow_item pattern[],
106 const struct rte_flow_action actions[],
107 struct rte_flow_error *error,
108 union i40e_filter_t *filter);
109 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
110 const struct rte_flow_attr *attr,
111 const struct rte_flow_item pattern[],
112 const struct rte_flow_action actions[],
113 struct rte_flow_error *error,
114 union i40e_filter_t *filter);
115 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
116 const struct rte_flow_attr *attr,
117 const struct rte_flow_item pattern[],
118 const struct rte_flow_action actions[],
119 struct rte_flow_error *error,
120 union i40e_filter_t *filter);
121 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
122 const struct rte_flow_attr *attr,
123 const struct rte_flow_item pattern[],
124 const struct rte_flow_action actions[],
125 struct rte_flow_error *error,
126 union i40e_filter_t *filter);
127 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
128 const struct rte_flow_attr *attr,
129 const struct rte_flow_item pattern[],
130 const struct rte_flow_action actions[],
131 struct rte_flow_error *error,
132 union i40e_filter_t *filter);
133 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
134 struct i40e_ethertype_filter *filter);
135 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
136 struct i40e_tunnel_filter *filter);
137 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
138 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
139 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
141 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
142 const struct rte_flow_attr *attr,
143 const struct rte_flow_item pattern[],
144 const struct rte_flow_action actions[],
145 struct rte_flow_error *error,
146 union i40e_filter_t *filter);
148 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
149 const struct rte_flow_item *pattern,
150 struct rte_flow_error *error,
151 struct i40e_tunnel_filter_conf *filter);
153 const struct rte_flow_ops i40e_flow_ops = {
154 .validate = i40e_flow_validate,
155 .create = i40e_flow_create,
156 .destroy = i40e_flow_destroy,
157 .flush = i40e_flow_flush,
160 union i40e_filter_t cons_filter;
161 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
163 /* Pattern matched ethertype filter */
164 static enum rte_flow_item_type pattern_ethertype[] = {
165 RTE_FLOW_ITEM_TYPE_ETH,
166 RTE_FLOW_ITEM_TYPE_END,
169 /* Pattern matched flow director filter */
170 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
171 RTE_FLOW_ITEM_TYPE_ETH,
172 RTE_FLOW_ITEM_TYPE_IPV4,
173 RTE_FLOW_ITEM_TYPE_END,
176 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
177 RTE_FLOW_ITEM_TYPE_ETH,
178 RTE_FLOW_ITEM_TYPE_IPV4,
179 RTE_FLOW_ITEM_TYPE_UDP,
180 RTE_FLOW_ITEM_TYPE_END,
183 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
184 RTE_FLOW_ITEM_TYPE_ETH,
185 RTE_FLOW_ITEM_TYPE_IPV4,
186 RTE_FLOW_ITEM_TYPE_TCP,
187 RTE_FLOW_ITEM_TYPE_END,
190 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
191 RTE_FLOW_ITEM_TYPE_ETH,
192 RTE_FLOW_ITEM_TYPE_IPV4,
193 RTE_FLOW_ITEM_TYPE_SCTP,
194 RTE_FLOW_ITEM_TYPE_END,
197 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
198 RTE_FLOW_ITEM_TYPE_ETH,
199 RTE_FLOW_ITEM_TYPE_IPV4,
200 RTE_FLOW_ITEM_TYPE_UDP,
201 RTE_FLOW_ITEM_TYPE_GTPC,
202 RTE_FLOW_ITEM_TYPE_END,
205 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
206 RTE_FLOW_ITEM_TYPE_ETH,
207 RTE_FLOW_ITEM_TYPE_IPV4,
208 RTE_FLOW_ITEM_TYPE_UDP,
209 RTE_FLOW_ITEM_TYPE_GTPU,
210 RTE_FLOW_ITEM_TYPE_END,
213 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
214 RTE_FLOW_ITEM_TYPE_ETH,
215 RTE_FLOW_ITEM_TYPE_IPV4,
216 RTE_FLOW_ITEM_TYPE_UDP,
217 RTE_FLOW_ITEM_TYPE_GTPU,
218 RTE_FLOW_ITEM_TYPE_IPV4,
219 RTE_FLOW_ITEM_TYPE_END,
222 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
223 RTE_FLOW_ITEM_TYPE_ETH,
224 RTE_FLOW_ITEM_TYPE_IPV4,
225 RTE_FLOW_ITEM_TYPE_UDP,
226 RTE_FLOW_ITEM_TYPE_GTPU,
227 RTE_FLOW_ITEM_TYPE_IPV6,
228 RTE_FLOW_ITEM_TYPE_END,
231 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
232 RTE_FLOW_ITEM_TYPE_ETH,
233 RTE_FLOW_ITEM_TYPE_IPV6,
234 RTE_FLOW_ITEM_TYPE_END,
237 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
238 RTE_FLOW_ITEM_TYPE_ETH,
239 RTE_FLOW_ITEM_TYPE_IPV6,
240 RTE_FLOW_ITEM_TYPE_UDP,
241 RTE_FLOW_ITEM_TYPE_END,
244 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
245 RTE_FLOW_ITEM_TYPE_ETH,
246 RTE_FLOW_ITEM_TYPE_IPV6,
247 RTE_FLOW_ITEM_TYPE_TCP,
248 RTE_FLOW_ITEM_TYPE_END,
251 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
252 RTE_FLOW_ITEM_TYPE_ETH,
253 RTE_FLOW_ITEM_TYPE_IPV6,
254 RTE_FLOW_ITEM_TYPE_SCTP,
255 RTE_FLOW_ITEM_TYPE_END,
258 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
259 RTE_FLOW_ITEM_TYPE_ETH,
260 RTE_FLOW_ITEM_TYPE_IPV6,
261 RTE_FLOW_ITEM_TYPE_UDP,
262 RTE_FLOW_ITEM_TYPE_GTPC,
263 RTE_FLOW_ITEM_TYPE_END,
266 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
267 RTE_FLOW_ITEM_TYPE_ETH,
268 RTE_FLOW_ITEM_TYPE_IPV6,
269 RTE_FLOW_ITEM_TYPE_UDP,
270 RTE_FLOW_ITEM_TYPE_GTPU,
271 RTE_FLOW_ITEM_TYPE_END,
274 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
275 RTE_FLOW_ITEM_TYPE_ETH,
276 RTE_FLOW_ITEM_TYPE_IPV6,
277 RTE_FLOW_ITEM_TYPE_UDP,
278 RTE_FLOW_ITEM_TYPE_GTPU,
279 RTE_FLOW_ITEM_TYPE_IPV4,
280 RTE_FLOW_ITEM_TYPE_END,
283 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
284 RTE_FLOW_ITEM_TYPE_ETH,
285 RTE_FLOW_ITEM_TYPE_IPV6,
286 RTE_FLOW_ITEM_TYPE_UDP,
287 RTE_FLOW_ITEM_TYPE_GTPU,
288 RTE_FLOW_ITEM_TYPE_IPV6,
289 RTE_FLOW_ITEM_TYPE_END,
292 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
293 RTE_FLOW_ITEM_TYPE_ETH,
294 RTE_FLOW_ITEM_TYPE_RAW,
295 RTE_FLOW_ITEM_TYPE_END,
298 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
299 RTE_FLOW_ITEM_TYPE_ETH,
300 RTE_FLOW_ITEM_TYPE_RAW,
301 RTE_FLOW_ITEM_TYPE_RAW,
302 RTE_FLOW_ITEM_TYPE_END,
305 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
306 RTE_FLOW_ITEM_TYPE_ETH,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_RAW,
309 RTE_FLOW_ITEM_TYPE_RAW,
310 RTE_FLOW_ITEM_TYPE_END,
313 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
314 RTE_FLOW_ITEM_TYPE_ETH,
315 RTE_FLOW_ITEM_TYPE_IPV4,
316 RTE_FLOW_ITEM_TYPE_RAW,
317 RTE_FLOW_ITEM_TYPE_END,
320 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
321 RTE_FLOW_ITEM_TYPE_ETH,
322 RTE_FLOW_ITEM_TYPE_IPV4,
323 RTE_FLOW_ITEM_TYPE_RAW,
324 RTE_FLOW_ITEM_TYPE_RAW,
325 RTE_FLOW_ITEM_TYPE_END,
328 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
329 RTE_FLOW_ITEM_TYPE_ETH,
330 RTE_FLOW_ITEM_TYPE_IPV4,
331 RTE_FLOW_ITEM_TYPE_RAW,
332 RTE_FLOW_ITEM_TYPE_RAW,
333 RTE_FLOW_ITEM_TYPE_RAW,
334 RTE_FLOW_ITEM_TYPE_END,
337 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
338 RTE_FLOW_ITEM_TYPE_ETH,
339 RTE_FLOW_ITEM_TYPE_IPV4,
340 RTE_FLOW_ITEM_TYPE_UDP,
341 RTE_FLOW_ITEM_TYPE_RAW,
342 RTE_FLOW_ITEM_TYPE_END,
345 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
346 RTE_FLOW_ITEM_TYPE_ETH,
347 RTE_FLOW_ITEM_TYPE_IPV4,
348 RTE_FLOW_ITEM_TYPE_UDP,
349 RTE_FLOW_ITEM_TYPE_RAW,
350 RTE_FLOW_ITEM_TYPE_RAW,
351 RTE_FLOW_ITEM_TYPE_END,
354 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
355 RTE_FLOW_ITEM_TYPE_ETH,
356 RTE_FLOW_ITEM_TYPE_IPV4,
357 RTE_FLOW_ITEM_TYPE_UDP,
358 RTE_FLOW_ITEM_TYPE_RAW,
359 RTE_FLOW_ITEM_TYPE_RAW,
360 RTE_FLOW_ITEM_TYPE_RAW,
361 RTE_FLOW_ITEM_TYPE_END,
364 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
365 RTE_FLOW_ITEM_TYPE_ETH,
366 RTE_FLOW_ITEM_TYPE_IPV4,
367 RTE_FLOW_ITEM_TYPE_TCP,
368 RTE_FLOW_ITEM_TYPE_RAW,
369 RTE_FLOW_ITEM_TYPE_END,
372 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
373 RTE_FLOW_ITEM_TYPE_ETH,
374 RTE_FLOW_ITEM_TYPE_IPV4,
375 RTE_FLOW_ITEM_TYPE_TCP,
376 RTE_FLOW_ITEM_TYPE_RAW,
377 RTE_FLOW_ITEM_TYPE_RAW,
378 RTE_FLOW_ITEM_TYPE_END,
381 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
382 RTE_FLOW_ITEM_TYPE_ETH,
383 RTE_FLOW_ITEM_TYPE_IPV4,
384 RTE_FLOW_ITEM_TYPE_TCP,
385 RTE_FLOW_ITEM_TYPE_RAW,
386 RTE_FLOW_ITEM_TYPE_RAW,
387 RTE_FLOW_ITEM_TYPE_RAW,
388 RTE_FLOW_ITEM_TYPE_END,
391 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
392 RTE_FLOW_ITEM_TYPE_ETH,
393 RTE_FLOW_ITEM_TYPE_IPV4,
394 RTE_FLOW_ITEM_TYPE_SCTP,
395 RTE_FLOW_ITEM_TYPE_RAW,
396 RTE_FLOW_ITEM_TYPE_END,
399 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
400 RTE_FLOW_ITEM_TYPE_ETH,
401 RTE_FLOW_ITEM_TYPE_IPV4,
402 RTE_FLOW_ITEM_TYPE_SCTP,
403 RTE_FLOW_ITEM_TYPE_RAW,
404 RTE_FLOW_ITEM_TYPE_RAW,
405 RTE_FLOW_ITEM_TYPE_END,
408 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
409 RTE_FLOW_ITEM_TYPE_ETH,
410 RTE_FLOW_ITEM_TYPE_IPV4,
411 RTE_FLOW_ITEM_TYPE_SCTP,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_RAW,
414 RTE_FLOW_ITEM_TYPE_RAW,
415 RTE_FLOW_ITEM_TYPE_END,
418 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
419 RTE_FLOW_ITEM_TYPE_ETH,
420 RTE_FLOW_ITEM_TYPE_IPV6,
421 RTE_FLOW_ITEM_TYPE_RAW,
422 RTE_FLOW_ITEM_TYPE_END,
425 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
426 RTE_FLOW_ITEM_TYPE_ETH,
427 RTE_FLOW_ITEM_TYPE_IPV6,
428 RTE_FLOW_ITEM_TYPE_RAW,
429 RTE_FLOW_ITEM_TYPE_RAW,
430 RTE_FLOW_ITEM_TYPE_END,
433 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
434 RTE_FLOW_ITEM_TYPE_ETH,
435 RTE_FLOW_ITEM_TYPE_IPV6,
436 RTE_FLOW_ITEM_TYPE_RAW,
437 RTE_FLOW_ITEM_TYPE_RAW,
438 RTE_FLOW_ITEM_TYPE_RAW,
439 RTE_FLOW_ITEM_TYPE_END,
442 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
443 RTE_FLOW_ITEM_TYPE_ETH,
444 RTE_FLOW_ITEM_TYPE_IPV6,
445 RTE_FLOW_ITEM_TYPE_UDP,
446 RTE_FLOW_ITEM_TYPE_RAW,
447 RTE_FLOW_ITEM_TYPE_END,
450 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
451 RTE_FLOW_ITEM_TYPE_ETH,
452 RTE_FLOW_ITEM_TYPE_IPV6,
453 RTE_FLOW_ITEM_TYPE_UDP,
454 RTE_FLOW_ITEM_TYPE_RAW,
455 RTE_FLOW_ITEM_TYPE_RAW,
456 RTE_FLOW_ITEM_TYPE_END,
459 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
460 RTE_FLOW_ITEM_TYPE_ETH,
461 RTE_FLOW_ITEM_TYPE_IPV6,
462 RTE_FLOW_ITEM_TYPE_UDP,
463 RTE_FLOW_ITEM_TYPE_RAW,
464 RTE_FLOW_ITEM_TYPE_RAW,
465 RTE_FLOW_ITEM_TYPE_RAW,
466 RTE_FLOW_ITEM_TYPE_END,
469 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
470 RTE_FLOW_ITEM_TYPE_ETH,
471 RTE_FLOW_ITEM_TYPE_IPV6,
472 RTE_FLOW_ITEM_TYPE_TCP,
473 RTE_FLOW_ITEM_TYPE_RAW,
474 RTE_FLOW_ITEM_TYPE_END,
477 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
478 RTE_FLOW_ITEM_TYPE_ETH,
479 RTE_FLOW_ITEM_TYPE_IPV6,
480 RTE_FLOW_ITEM_TYPE_TCP,
481 RTE_FLOW_ITEM_TYPE_RAW,
482 RTE_FLOW_ITEM_TYPE_RAW,
483 RTE_FLOW_ITEM_TYPE_END,
486 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
487 RTE_FLOW_ITEM_TYPE_ETH,
488 RTE_FLOW_ITEM_TYPE_IPV6,
489 RTE_FLOW_ITEM_TYPE_TCP,
490 RTE_FLOW_ITEM_TYPE_RAW,
491 RTE_FLOW_ITEM_TYPE_RAW,
492 RTE_FLOW_ITEM_TYPE_RAW,
493 RTE_FLOW_ITEM_TYPE_END,
496 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
497 RTE_FLOW_ITEM_TYPE_ETH,
498 RTE_FLOW_ITEM_TYPE_IPV6,
499 RTE_FLOW_ITEM_TYPE_SCTP,
500 RTE_FLOW_ITEM_TYPE_RAW,
501 RTE_FLOW_ITEM_TYPE_END,
504 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
505 RTE_FLOW_ITEM_TYPE_ETH,
506 RTE_FLOW_ITEM_TYPE_IPV6,
507 RTE_FLOW_ITEM_TYPE_SCTP,
508 RTE_FLOW_ITEM_TYPE_RAW,
509 RTE_FLOW_ITEM_TYPE_RAW,
510 RTE_FLOW_ITEM_TYPE_END,
513 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
514 RTE_FLOW_ITEM_TYPE_ETH,
515 RTE_FLOW_ITEM_TYPE_IPV6,
516 RTE_FLOW_ITEM_TYPE_SCTP,
517 RTE_FLOW_ITEM_TYPE_RAW,
518 RTE_FLOW_ITEM_TYPE_RAW,
519 RTE_FLOW_ITEM_TYPE_RAW,
520 RTE_FLOW_ITEM_TYPE_END,
523 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
524 RTE_FLOW_ITEM_TYPE_ETH,
525 RTE_FLOW_ITEM_TYPE_VLAN,
526 RTE_FLOW_ITEM_TYPE_END,
529 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
530 RTE_FLOW_ITEM_TYPE_ETH,
531 RTE_FLOW_ITEM_TYPE_VLAN,
532 RTE_FLOW_ITEM_TYPE_IPV4,
533 RTE_FLOW_ITEM_TYPE_END,
536 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
537 RTE_FLOW_ITEM_TYPE_ETH,
538 RTE_FLOW_ITEM_TYPE_VLAN,
539 RTE_FLOW_ITEM_TYPE_IPV4,
540 RTE_FLOW_ITEM_TYPE_UDP,
541 RTE_FLOW_ITEM_TYPE_END,
544 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
545 RTE_FLOW_ITEM_TYPE_ETH,
546 RTE_FLOW_ITEM_TYPE_VLAN,
547 RTE_FLOW_ITEM_TYPE_IPV4,
548 RTE_FLOW_ITEM_TYPE_TCP,
549 RTE_FLOW_ITEM_TYPE_END,
552 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
553 RTE_FLOW_ITEM_TYPE_ETH,
554 RTE_FLOW_ITEM_TYPE_VLAN,
555 RTE_FLOW_ITEM_TYPE_IPV4,
556 RTE_FLOW_ITEM_TYPE_SCTP,
557 RTE_FLOW_ITEM_TYPE_END,
560 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
561 RTE_FLOW_ITEM_TYPE_ETH,
562 RTE_FLOW_ITEM_TYPE_VLAN,
563 RTE_FLOW_ITEM_TYPE_IPV6,
564 RTE_FLOW_ITEM_TYPE_END,
567 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
568 RTE_FLOW_ITEM_TYPE_ETH,
569 RTE_FLOW_ITEM_TYPE_VLAN,
570 RTE_FLOW_ITEM_TYPE_IPV6,
571 RTE_FLOW_ITEM_TYPE_UDP,
572 RTE_FLOW_ITEM_TYPE_END,
575 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
576 RTE_FLOW_ITEM_TYPE_ETH,
577 RTE_FLOW_ITEM_TYPE_VLAN,
578 RTE_FLOW_ITEM_TYPE_IPV6,
579 RTE_FLOW_ITEM_TYPE_TCP,
580 RTE_FLOW_ITEM_TYPE_END,
583 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
584 RTE_FLOW_ITEM_TYPE_ETH,
585 RTE_FLOW_ITEM_TYPE_VLAN,
586 RTE_FLOW_ITEM_TYPE_IPV6,
587 RTE_FLOW_ITEM_TYPE_SCTP,
588 RTE_FLOW_ITEM_TYPE_END,
591 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
592 RTE_FLOW_ITEM_TYPE_ETH,
593 RTE_FLOW_ITEM_TYPE_VLAN,
594 RTE_FLOW_ITEM_TYPE_RAW,
595 RTE_FLOW_ITEM_TYPE_END,
598 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
599 RTE_FLOW_ITEM_TYPE_ETH,
600 RTE_FLOW_ITEM_TYPE_VLAN,
601 RTE_FLOW_ITEM_TYPE_RAW,
602 RTE_FLOW_ITEM_TYPE_RAW,
603 RTE_FLOW_ITEM_TYPE_END,
606 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
607 RTE_FLOW_ITEM_TYPE_ETH,
608 RTE_FLOW_ITEM_TYPE_VLAN,
609 RTE_FLOW_ITEM_TYPE_RAW,
610 RTE_FLOW_ITEM_TYPE_RAW,
611 RTE_FLOW_ITEM_TYPE_RAW,
612 RTE_FLOW_ITEM_TYPE_END,
615 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
616 RTE_FLOW_ITEM_TYPE_ETH,
617 RTE_FLOW_ITEM_TYPE_VLAN,
618 RTE_FLOW_ITEM_TYPE_IPV4,
619 RTE_FLOW_ITEM_TYPE_RAW,
620 RTE_FLOW_ITEM_TYPE_END,
623 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
624 RTE_FLOW_ITEM_TYPE_ETH,
625 RTE_FLOW_ITEM_TYPE_VLAN,
626 RTE_FLOW_ITEM_TYPE_IPV4,
627 RTE_FLOW_ITEM_TYPE_RAW,
628 RTE_FLOW_ITEM_TYPE_RAW,
629 RTE_FLOW_ITEM_TYPE_END,
632 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
633 RTE_FLOW_ITEM_TYPE_ETH,
634 RTE_FLOW_ITEM_TYPE_VLAN,
635 RTE_FLOW_ITEM_TYPE_IPV4,
636 RTE_FLOW_ITEM_TYPE_RAW,
637 RTE_FLOW_ITEM_TYPE_RAW,
638 RTE_FLOW_ITEM_TYPE_RAW,
639 RTE_FLOW_ITEM_TYPE_END,
642 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
643 RTE_FLOW_ITEM_TYPE_ETH,
644 RTE_FLOW_ITEM_TYPE_VLAN,
645 RTE_FLOW_ITEM_TYPE_IPV4,
646 RTE_FLOW_ITEM_TYPE_UDP,
647 RTE_FLOW_ITEM_TYPE_RAW,
648 RTE_FLOW_ITEM_TYPE_END,
651 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
652 RTE_FLOW_ITEM_TYPE_ETH,
653 RTE_FLOW_ITEM_TYPE_VLAN,
654 RTE_FLOW_ITEM_TYPE_IPV4,
655 RTE_FLOW_ITEM_TYPE_UDP,
656 RTE_FLOW_ITEM_TYPE_RAW,
657 RTE_FLOW_ITEM_TYPE_RAW,
658 RTE_FLOW_ITEM_TYPE_END,
661 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
662 RTE_FLOW_ITEM_TYPE_ETH,
663 RTE_FLOW_ITEM_TYPE_VLAN,
664 RTE_FLOW_ITEM_TYPE_IPV4,
665 RTE_FLOW_ITEM_TYPE_UDP,
666 RTE_FLOW_ITEM_TYPE_RAW,
667 RTE_FLOW_ITEM_TYPE_RAW,
668 RTE_FLOW_ITEM_TYPE_RAW,
669 RTE_FLOW_ITEM_TYPE_END,
672 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
673 RTE_FLOW_ITEM_TYPE_ETH,
674 RTE_FLOW_ITEM_TYPE_VLAN,
675 RTE_FLOW_ITEM_TYPE_IPV4,
676 RTE_FLOW_ITEM_TYPE_TCP,
677 RTE_FLOW_ITEM_TYPE_RAW,
678 RTE_FLOW_ITEM_TYPE_END,
681 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
682 RTE_FLOW_ITEM_TYPE_ETH,
683 RTE_FLOW_ITEM_TYPE_VLAN,
684 RTE_FLOW_ITEM_TYPE_IPV4,
685 RTE_FLOW_ITEM_TYPE_TCP,
686 RTE_FLOW_ITEM_TYPE_RAW,
687 RTE_FLOW_ITEM_TYPE_RAW,
688 RTE_FLOW_ITEM_TYPE_END,
691 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
692 RTE_FLOW_ITEM_TYPE_ETH,
693 RTE_FLOW_ITEM_TYPE_VLAN,
694 RTE_FLOW_ITEM_TYPE_IPV4,
695 RTE_FLOW_ITEM_TYPE_TCP,
696 RTE_FLOW_ITEM_TYPE_RAW,
697 RTE_FLOW_ITEM_TYPE_RAW,
698 RTE_FLOW_ITEM_TYPE_RAW,
699 RTE_FLOW_ITEM_TYPE_END,
702 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
703 RTE_FLOW_ITEM_TYPE_ETH,
704 RTE_FLOW_ITEM_TYPE_VLAN,
705 RTE_FLOW_ITEM_TYPE_IPV4,
706 RTE_FLOW_ITEM_TYPE_SCTP,
707 RTE_FLOW_ITEM_TYPE_RAW,
708 RTE_FLOW_ITEM_TYPE_END,
711 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
712 RTE_FLOW_ITEM_TYPE_ETH,
713 RTE_FLOW_ITEM_TYPE_VLAN,
714 RTE_FLOW_ITEM_TYPE_IPV4,
715 RTE_FLOW_ITEM_TYPE_SCTP,
716 RTE_FLOW_ITEM_TYPE_RAW,
717 RTE_FLOW_ITEM_TYPE_RAW,
718 RTE_FLOW_ITEM_TYPE_END,
721 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
722 RTE_FLOW_ITEM_TYPE_ETH,
723 RTE_FLOW_ITEM_TYPE_VLAN,
724 RTE_FLOW_ITEM_TYPE_IPV4,
725 RTE_FLOW_ITEM_TYPE_SCTP,
726 RTE_FLOW_ITEM_TYPE_RAW,
727 RTE_FLOW_ITEM_TYPE_RAW,
728 RTE_FLOW_ITEM_TYPE_RAW,
729 RTE_FLOW_ITEM_TYPE_END,
732 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
733 RTE_FLOW_ITEM_TYPE_ETH,
734 RTE_FLOW_ITEM_TYPE_VLAN,
735 RTE_FLOW_ITEM_TYPE_IPV6,
736 RTE_FLOW_ITEM_TYPE_RAW,
737 RTE_FLOW_ITEM_TYPE_END,
740 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
741 RTE_FLOW_ITEM_TYPE_ETH,
742 RTE_FLOW_ITEM_TYPE_VLAN,
743 RTE_FLOW_ITEM_TYPE_IPV6,
744 RTE_FLOW_ITEM_TYPE_RAW,
745 RTE_FLOW_ITEM_TYPE_RAW,
746 RTE_FLOW_ITEM_TYPE_END,
749 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
750 RTE_FLOW_ITEM_TYPE_ETH,
751 RTE_FLOW_ITEM_TYPE_VLAN,
752 RTE_FLOW_ITEM_TYPE_IPV6,
753 RTE_FLOW_ITEM_TYPE_RAW,
754 RTE_FLOW_ITEM_TYPE_RAW,
755 RTE_FLOW_ITEM_TYPE_RAW,
756 RTE_FLOW_ITEM_TYPE_END,
759 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
760 RTE_FLOW_ITEM_TYPE_ETH,
761 RTE_FLOW_ITEM_TYPE_VLAN,
762 RTE_FLOW_ITEM_TYPE_IPV6,
763 RTE_FLOW_ITEM_TYPE_UDP,
764 RTE_FLOW_ITEM_TYPE_RAW,
765 RTE_FLOW_ITEM_TYPE_END,
768 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
769 RTE_FLOW_ITEM_TYPE_ETH,
770 RTE_FLOW_ITEM_TYPE_VLAN,
771 RTE_FLOW_ITEM_TYPE_IPV6,
772 RTE_FLOW_ITEM_TYPE_UDP,
773 RTE_FLOW_ITEM_TYPE_RAW,
774 RTE_FLOW_ITEM_TYPE_RAW,
775 RTE_FLOW_ITEM_TYPE_END,
778 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
779 RTE_FLOW_ITEM_TYPE_ETH,
780 RTE_FLOW_ITEM_TYPE_VLAN,
781 RTE_FLOW_ITEM_TYPE_IPV6,
782 RTE_FLOW_ITEM_TYPE_UDP,
783 RTE_FLOW_ITEM_TYPE_RAW,
784 RTE_FLOW_ITEM_TYPE_RAW,
785 RTE_FLOW_ITEM_TYPE_RAW,
786 RTE_FLOW_ITEM_TYPE_END,
789 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
790 RTE_FLOW_ITEM_TYPE_ETH,
791 RTE_FLOW_ITEM_TYPE_VLAN,
792 RTE_FLOW_ITEM_TYPE_IPV6,
793 RTE_FLOW_ITEM_TYPE_TCP,
794 RTE_FLOW_ITEM_TYPE_RAW,
795 RTE_FLOW_ITEM_TYPE_END,
798 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
799 RTE_FLOW_ITEM_TYPE_ETH,
800 RTE_FLOW_ITEM_TYPE_VLAN,
801 RTE_FLOW_ITEM_TYPE_IPV6,
802 RTE_FLOW_ITEM_TYPE_TCP,
803 RTE_FLOW_ITEM_TYPE_RAW,
804 RTE_FLOW_ITEM_TYPE_RAW,
805 RTE_FLOW_ITEM_TYPE_END,
808 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
809 RTE_FLOW_ITEM_TYPE_ETH,
810 RTE_FLOW_ITEM_TYPE_VLAN,
811 RTE_FLOW_ITEM_TYPE_IPV6,
812 RTE_FLOW_ITEM_TYPE_TCP,
813 RTE_FLOW_ITEM_TYPE_RAW,
814 RTE_FLOW_ITEM_TYPE_RAW,
815 RTE_FLOW_ITEM_TYPE_RAW,
816 RTE_FLOW_ITEM_TYPE_END,
819 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
820 RTE_FLOW_ITEM_TYPE_ETH,
821 RTE_FLOW_ITEM_TYPE_VLAN,
822 RTE_FLOW_ITEM_TYPE_IPV6,
823 RTE_FLOW_ITEM_TYPE_SCTP,
824 RTE_FLOW_ITEM_TYPE_RAW,
825 RTE_FLOW_ITEM_TYPE_END,
828 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
829 RTE_FLOW_ITEM_TYPE_ETH,
830 RTE_FLOW_ITEM_TYPE_VLAN,
831 RTE_FLOW_ITEM_TYPE_IPV6,
832 RTE_FLOW_ITEM_TYPE_SCTP,
833 RTE_FLOW_ITEM_TYPE_RAW,
834 RTE_FLOW_ITEM_TYPE_RAW,
835 RTE_FLOW_ITEM_TYPE_END,
838 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
839 RTE_FLOW_ITEM_TYPE_ETH,
840 RTE_FLOW_ITEM_TYPE_VLAN,
841 RTE_FLOW_ITEM_TYPE_IPV6,
842 RTE_FLOW_ITEM_TYPE_SCTP,
843 RTE_FLOW_ITEM_TYPE_RAW,
844 RTE_FLOW_ITEM_TYPE_RAW,
845 RTE_FLOW_ITEM_TYPE_RAW,
846 RTE_FLOW_ITEM_TYPE_END,
849 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
850 RTE_FLOW_ITEM_TYPE_ETH,
851 RTE_FLOW_ITEM_TYPE_IPV4,
852 RTE_FLOW_ITEM_TYPE_VF,
853 RTE_FLOW_ITEM_TYPE_END,
856 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
857 RTE_FLOW_ITEM_TYPE_ETH,
858 RTE_FLOW_ITEM_TYPE_IPV4,
859 RTE_FLOW_ITEM_TYPE_UDP,
860 RTE_FLOW_ITEM_TYPE_VF,
861 RTE_FLOW_ITEM_TYPE_END,
864 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
865 RTE_FLOW_ITEM_TYPE_ETH,
866 RTE_FLOW_ITEM_TYPE_IPV4,
867 RTE_FLOW_ITEM_TYPE_TCP,
868 RTE_FLOW_ITEM_TYPE_VF,
869 RTE_FLOW_ITEM_TYPE_END,
872 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
873 RTE_FLOW_ITEM_TYPE_ETH,
874 RTE_FLOW_ITEM_TYPE_IPV4,
875 RTE_FLOW_ITEM_TYPE_SCTP,
876 RTE_FLOW_ITEM_TYPE_VF,
877 RTE_FLOW_ITEM_TYPE_END,
880 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
881 RTE_FLOW_ITEM_TYPE_ETH,
882 RTE_FLOW_ITEM_TYPE_IPV6,
883 RTE_FLOW_ITEM_TYPE_VF,
884 RTE_FLOW_ITEM_TYPE_END,
887 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
888 RTE_FLOW_ITEM_TYPE_ETH,
889 RTE_FLOW_ITEM_TYPE_IPV6,
890 RTE_FLOW_ITEM_TYPE_UDP,
891 RTE_FLOW_ITEM_TYPE_VF,
892 RTE_FLOW_ITEM_TYPE_END,
895 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
896 RTE_FLOW_ITEM_TYPE_ETH,
897 RTE_FLOW_ITEM_TYPE_IPV6,
898 RTE_FLOW_ITEM_TYPE_TCP,
899 RTE_FLOW_ITEM_TYPE_VF,
900 RTE_FLOW_ITEM_TYPE_END,
903 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
904 RTE_FLOW_ITEM_TYPE_ETH,
905 RTE_FLOW_ITEM_TYPE_IPV6,
906 RTE_FLOW_ITEM_TYPE_SCTP,
907 RTE_FLOW_ITEM_TYPE_VF,
908 RTE_FLOW_ITEM_TYPE_END,
911 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
912 RTE_FLOW_ITEM_TYPE_ETH,
913 RTE_FLOW_ITEM_TYPE_RAW,
914 RTE_FLOW_ITEM_TYPE_VF,
915 RTE_FLOW_ITEM_TYPE_END,
918 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
919 RTE_FLOW_ITEM_TYPE_ETH,
920 RTE_FLOW_ITEM_TYPE_RAW,
921 RTE_FLOW_ITEM_TYPE_RAW,
922 RTE_FLOW_ITEM_TYPE_VF,
923 RTE_FLOW_ITEM_TYPE_END,
926 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
927 RTE_FLOW_ITEM_TYPE_ETH,
928 RTE_FLOW_ITEM_TYPE_RAW,
929 RTE_FLOW_ITEM_TYPE_RAW,
930 RTE_FLOW_ITEM_TYPE_RAW,
931 RTE_FLOW_ITEM_TYPE_VF,
932 RTE_FLOW_ITEM_TYPE_END,
935 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
936 RTE_FLOW_ITEM_TYPE_ETH,
937 RTE_FLOW_ITEM_TYPE_IPV4,
938 RTE_FLOW_ITEM_TYPE_RAW,
939 RTE_FLOW_ITEM_TYPE_VF,
940 RTE_FLOW_ITEM_TYPE_END,
943 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
944 RTE_FLOW_ITEM_TYPE_ETH,
945 RTE_FLOW_ITEM_TYPE_IPV4,
946 RTE_FLOW_ITEM_TYPE_RAW,
947 RTE_FLOW_ITEM_TYPE_RAW,
948 RTE_FLOW_ITEM_TYPE_VF,
949 RTE_FLOW_ITEM_TYPE_END,
952 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
953 RTE_FLOW_ITEM_TYPE_ETH,
954 RTE_FLOW_ITEM_TYPE_IPV4,
955 RTE_FLOW_ITEM_TYPE_RAW,
956 RTE_FLOW_ITEM_TYPE_RAW,
957 RTE_FLOW_ITEM_TYPE_RAW,
958 RTE_FLOW_ITEM_TYPE_VF,
959 RTE_FLOW_ITEM_TYPE_END,
962 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
963 RTE_FLOW_ITEM_TYPE_ETH,
964 RTE_FLOW_ITEM_TYPE_IPV4,
965 RTE_FLOW_ITEM_TYPE_UDP,
966 RTE_FLOW_ITEM_TYPE_RAW,
967 RTE_FLOW_ITEM_TYPE_VF,
968 RTE_FLOW_ITEM_TYPE_END,
971 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
972 RTE_FLOW_ITEM_TYPE_ETH,
973 RTE_FLOW_ITEM_TYPE_IPV4,
974 RTE_FLOW_ITEM_TYPE_UDP,
975 RTE_FLOW_ITEM_TYPE_RAW,
976 RTE_FLOW_ITEM_TYPE_RAW,
977 RTE_FLOW_ITEM_TYPE_VF,
978 RTE_FLOW_ITEM_TYPE_END,
981 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
982 RTE_FLOW_ITEM_TYPE_ETH,
983 RTE_FLOW_ITEM_TYPE_IPV4,
984 RTE_FLOW_ITEM_TYPE_UDP,
985 RTE_FLOW_ITEM_TYPE_RAW,
986 RTE_FLOW_ITEM_TYPE_RAW,
987 RTE_FLOW_ITEM_TYPE_RAW,
988 RTE_FLOW_ITEM_TYPE_VF,
989 RTE_FLOW_ITEM_TYPE_END,
992 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
993 RTE_FLOW_ITEM_TYPE_ETH,
994 RTE_FLOW_ITEM_TYPE_IPV4,
995 RTE_FLOW_ITEM_TYPE_TCP,
996 RTE_FLOW_ITEM_TYPE_RAW,
997 RTE_FLOW_ITEM_TYPE_VF,
998 RTE_FLOW_ITEM_TYPE_END,
1001 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
1002 RTE_FLOW_ITEM_TYPE_ETH,
1003 RTE_FLOW_ITEM_TYPE_IPV4,
1004 RTE_FLOW_ITEM_TYPE_TCP,
1005 RTE_FLOW_ITEM_TYPE_RAW,
1006 RTE_FLOW_ITEM_TYPE_RAW,
1007 RTE_FLOW_ITEM_TYPE_VF,
1008 RTE_FLOW_ITEM_TYPE_END,
1011 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
1012 RTE_FLOW_ITEM_TYPE_ETH,
1013 RTE_FLOW_ITEM_TYPE_IPV4,
1014 RTE_FLOW_ITEM_TYPE_TCP,
1015 RTE_FLOW_ITEM_TYPE_RAW,
1016 RTE_FLOW_ITEM_TYPE_RAW,
1017 RTE_FLOW_ITEM_TYPE_RAW,
1018 RTE_FLOW_ITEM_TYPE_VF,
1019 RTE_FLOW_ITEM_TYPE_END,
1022 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
1023 RTE_FLOW_ITEM_TYPE_ETH,
1024 RTE_FLOW_ITEM_TYPE_IPV4,
1025 RTE_FLOW_ITEM_TYPE_SCTP,
1026 RTE_FLOW_ITEM_TYPE_RAW,
1027 RTE_FLOW_ITEM_TYPE_VF,
1028 RTE_FLOW_ITEM_TYPE_END,
1031 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1032 RTE_FLOW_ITEM_TYPE_ETH,
1033 RTE_FLOW_ITEM_TYPE_IPV4,
1034 RTE_FLOW_ITEM_TYPE_SCTP,
1035 RTE_FLOW_ITEM_TYPE_RAW,
1036 RTE_FLOW_ITEM_TYPE_RAW,
1037 RTE_FLOW_ITEM_TYPE_VF,
1038 RTE_FLOW_ITEM_TYPE_END,
1041 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1042 RTE_FLOW_ITEM_TYPE_ETH,
1043 RTE_FLOW_ITEM_TYPE_IPV4,
1044 RTE_FLOW_ITEM_TYPE_SCTP,
1045 RTE_FLOW_ITEM_TYPE_RAW,
1046 RTE_FLOW_ITEM_TYPE_RAW,
1047 RTE_FLOW_ITEM_TYPE_RAW,
1048 RTE_FLOW_ITEM_TYPE_VF,
1049 RTE_FLOW_ITEM_TYPE_END,
1052 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1053 RTE_FLOW_ITEM_TYPE_ETH,
1054 RTE_FLOW_ITEM_TYPE_IPV6,
1055 RTE_FLOW_ITEM_TYPE_RAW,
1056 RTE_FLOW_ITEM_TYPE_VF,
1057 RTE_FLOW_ITEM_TYPE_END,
1060 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1061 RTE_FLOW_ITEM_TYPE_ETH,
1062 RTE_FLOW_ITEM_TYPE_IPV6,
1063 RTE_FLOW_ITEM_TYPE_RAW,
1064 RTE_FLOW_ITEM_TYPE_RAW,
1065 RTE_FLOW_ITEM_TYPE_VF,
1066 RTE_FLOW_ITEM_TYPE_END,
1069 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1070 RTE_FLOW_ITEM_TYPE_ETH,
1071 RTE_FLOW_ITEM_TYPE_IPV6,
1072 RTE_FLOW_ITEM_TYPE_RAW,
1073 RTE_FLOW_ITEM_TYPE_RAW,
1074 RTE_FLOW_ITEM_TYPE_RAW,
1075 RTE_FLOW_ITEM_TYPE_VF,
1076 RTE_FLOW_ITEM_TYPE_END,
1079 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1080 RTE_FLOW_ITEM_TYPE_ETH,
1081 RTE_FLOW_ITEM_TYPE_IPV6,
1082 RTE_FLOW_ITEM_TYPE_UDP,
1083 RTE_FLOW_ITEM_TYPE_RAW,
1084 RTE_FLOW_ITEM_TYPE_VF,
1085 RTE_FLOW_ITEM_TYPE_END,
1088 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1089 RTE_FLOW_ITEM_TYPE_ETH,
1090 RTE_FLOW_ITEM_TYPE_IPV6,
1091 RTE_FLOW_ITEM_TYPE_UDP,
1092 RTE_FLOW_ITEM_TYPE_RAW,
1093 RTE_FLOW_ITEM_TYPE_RAW,
1094 RTE_FLOW_ITEM_TYPE_VF,
1095 RTE_FLOW_ITEM_TYPE_END,
1098 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1099 RTE_FLOW_ITEM_TYPE_ETH,
1100 RTE_FLOW_ITEM_TYPE_IPV6,
1101 RTE_FLOW_ITEM_TYPE_UDP,
1102 RTE_FLOW_ITEM_TYPE_RAW,
1103 RTE_FLOW_ITEM_TYPE_RAW,
1104 RTE_FLOW_ITEM_TYPE_RAW,
1105 RTE_FLOW_ITEM_TYPE_VF,
1106 RTE_FLOW_ITEM_TYPE_END,
1109 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1110 RTE_FLOW_ITEM_TYPE_ETH,
1111 RTE_FLOW_ITEM_TYPE_IPV6,
1112 RTE_FLOW_ITEM_TYPE_TCP,
1113 RTE_FLOW_ITEM_TYPE_RAW,
1114 RTE_FLOW_ITEM_TYPE_VF,
1115 RTE_FLOW_ITEM_TYPE_END,
1118 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1119 RTE_FLOW_ITEM_TYPE_ETH,
1120 RTE_FLOW_ITEM_TYPE_IPV6,
1121 RTE_FLOW_ITEM_TYPE_TCP,
1122 RTE_FLOW_ITEM_TYPE_RAW,
1123 RTE_FLOW_ITEM_TYPE_RAW,
1124 RTE_FLOW_ITEM_TYPE_VF,
1125 RTE_FLOW_ITEM_TYPE_END,
1128 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1129 RTE_FLOW_ITEM_TYPE_ETH,
1130 RTE_FLOW_ITEM_TYPE_IPV6,
1131 RTE_FLOW_ITEM_TYPE_TCP,
1132 RTE_FLOW_ITEM_TYPE_RAW,
1133 RTE_FLOW_ITEM_TYPE_RAW,
1134 RTE_FLOW_ITEM_TYPE_RAW,
1135 RTE_FLOW_ITEM_TYPE_VF,
1136 RTE_FLOW_ITEM_TYPE_END,
1139 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1140 RTE_FLOW_ITEM_TYPE_ETH,
1141 RTE_FLOW_ITEM_TYPE_IPV6,
1142 RTE_FLOW_ITEM_TYPE_SCTP,
1143 RTE_FLOW_ITEM_TYPE_RAW,
1144 RTE_FLOW_ITEM_TYPE_VF,
1145 RTE_FLOW_ITEM_TYPE_END,
1148 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1149 RTE_FLOW_ITEM_TYPE_ETH,
1150 RTE_FLOW_ITEM_TYPE_IPV6,
1151 RTE_FLOW_ITEM_TYPE_SCTP,
1152 RTE_FLOW_ITEM_TYPE_RAW,
1153 RTE_FLOW_ITEM_TYPE_RAW,
1154 RTE_FLOW_ITEM_TYPE_VF,
1155 RTE_FLOW_ITEM_TYPE_END,
1158 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1159 RTE_FLOW_ITEM_TYPE_ETH,
1160 RTE_FLOW_ITEM_TYPE_IPV6,
1161 RTE_FLOW_ITEM_TYPE_SCTP,
1162 RTE_FLOW_ITEM_TYPE_RAW,
1163 RTE_FLOW_ITEM_TYPE_RAW,
1164 RTE_FLOW_ITEM_TYPE_RAW,
1165 RTE_FLOW_ITEM_TYPE_VF,
1166 RTE_FLOW_ITEM_TYPE_END,
1169 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1170 RTE_FLOW_ITEM_TYPE_ETH,
1171 RTE_FLOW_ITEM_TYPE_VLAN,
1172 RTE_FLOW_ITEM_TYPE_VF,
1173 RTE_FLOW_ITEM_TYPE_END,
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1177 RTE_FLOW_ITEM_TYPE_ETH,
1178 RTE_FLOW_ITEM_TYPE_VLAN,
1179 RTE_FLOW_ITEM_TYPE_IPV4,
1180 RTE_FLOW_ITEM_TYPE_VF,
1181 RTE_FLOW_ITEM_TYPE_END,
1184 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1185 RTE_FLOW_ITEM_TYPE_ETH,
1186 RTE_FLOW_ITEM_TYPE_VLAN,
1187 RTE_FLOW_ITEM_TYPE_IPV4,
1188 RTE_FLOW_ITEM_TYPE_UDP,
1189 RTE_FLOW_ITEM_TYPE_VF,
1190 RTE_FLOW_ITEM_TYPE_END,
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1194 RTE_FLOW_ITEM_TYPE_ETH,
1195 RTE_FLOW_ITEM_TYPE_VLAN,
1196 RTE_FLOW_ITEM_TYPE_IPV4,
1197 RTE_FLOW_ITEM_TYPE_TCP,
1198 RTE_FLOW_ITEM_TYPE_VF,
1199 RTE_FLOW_ITEM_TYPE_END,
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1203 RTE_FLOW_ITEM_TYPE_ETH,
1204 RTE_FLOW_ITEM_TYPE_VLAN,
1205 RTE_FLOW_ITEM_TYPE_IPV4,
1206 RTE_FLOW_ITEM_TYPE_SCTP,
1207 RTE_FLOW_ITEM_TYPE_VF,
1208 RTE_FLOW_ITEM_TYPE_END,
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1212 RTE_FLOW_ITEM_TYPE_ETH,
1213 RTE_FLOW_ITEM_TYPE_VLAN,
1214 RTE_FLOW_ITEM_TYPE_IPV6,
1215 RTE_FLOW_ITEM_TYPE_VF,
1216 RTE_FLOW_ITEM_TYPE_END,
1219 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1220 RTE_FLOW_ITEM_TYPE_ETH,
1221 RTE_FLOW_ITEM_TYPE_VLAN,
1222 RTE_FLOW_ITEM_TYPE_IPV6,
1223 RTE_FLOW_ITEM_TYPE_UDP,
1224 RTE_FLOW_ITEM_TYPE_VF,
1225 RTE_FLOW_ITEM_TYPE_END,
1228 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1229 RTE_FLOW_ITEM_TYPE_ETH,
1230 RTE_FLOW_ITEM_TYPE_VLAN,
1231 RTE_FLOW_ITEM_TYPE_IPV6,
1232 RTE_FLOW_ITEM_TYPE_TCP,
1233 RTE_FLOW_ITEM_TYPE_VF,
1234 RTE_FLOW_ITEM_TYPE_END,
1237 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1238 RTE_FLOW_ITEM_TYPE_ETH,
1239 RTE_FLOW_ITEM_TYPE_VLAN,
1240 RTE_FLOW_ITEM_TYPE_IPV6,
1241 RTE_FLOW_ITEM_TYPE_SCTP,
1242 RTE_FLOW_ITEM_TYPE_VF,
1243 RTE_FLOW_ITEM_TYPE_END,
1246 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1247 RTE_FLOW_ITEM_TYPE_ETH,
1248 RTE_FLOW_ITEM_TYPE_VLAN,
1249 RTE_FLOW_ITEM_TYPE_RAW,
1250 RTE_FLOW_ITEM_TYPE_VF,
1251 RTE_FLOW_ITEM_TYPE_END,
1254 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1255 RTE_FLOW_ITEM_TYPE_ETH,
1256 RTE_FLOW_ITEM_TYPE_VLAN,
1257 RTE_FLOW_ITEM_TYPE_RAW,
1258 RTE_FLOW_ITEM_TYPE_RAW,
1259 RTE_FLOW_ITEM_TYPE_VF,
1260 RTE_FLOW_ITEM_TYPE_END,
1263 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1264 RTE_FLOW_ITEM_TYPE_ETH,
1265 RTE_FLOW_ITEM_TYPE_VLAN,
1266 RTE_FLOW_ITEM_TYPE_RAW,
1267 RTE_FLOW_ITEM_TYPE_RAW,
1268 RTE_FLOW_ITEM_TYPE_RAW,
1269 RTE_FLOW_ITEM_TYPE_VF,
1270 RTE_FLOW_ITEM_TYPE_END,
1273 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1274 RTE_FLOW_ITEM_TYPE_ETH,
1275 RTE_FLOW_ITEM_TYPE_VLAN,
1276 RTE_FLOW_ITEM_TYPE_IPV4,
1277 RTE_FLOW_ITEM_TYPE_RAW,
1278 RTE_FLOW_ITEM_TYPE_VF,
1279 RTE_FLOW_ITEM_TYPE_END,
1282 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1283 RTE_FLOW_ITEM_TYPE_ETH,
1284 RTE_FLOW_ITEM_TYPE_VLAN,
1285 RTE_FLOW_ITEM_TYPE_IPV4,
1286 RTE_FLOW_ITEM_TYPE_RAW,
1287 RTE_FLOW_ITEM_TYPE_RAW,
1288 RTE_FLOW_ITEM_TYPE_VF,
1289 RTE_FLOW_ITEM_TYPE_END,
1292 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1293 RTE_FLOW_ITEM_TYPE_ETH,
1294 RTE_FLOW_ITEM_TYPE_VLAN,
1295 RTE_FLOW_ITEM_TYPE_IPV4,
1296 RTE_FLOW_ITEM_TYPE_RAW,
1297 RTE_FLOW_ITEM_TYPE_RAW,
1298 RTE_FLOW_ITEM_TYPE_RAW,
1299 RTE_FLOW_ITEM_TYPE_VF,
1300 RTE_FLOW_ITEM_TYPE_END,
1303 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1304 RTE_FLOW_ITEM_TYPE_ETH,
1305 RTE_FLOW_ITEM_TYPE_VLAN,
1306 RTE_FLOW_ITEM_TYPE_IPV4,
1307 RTE_FLOW_ITEM_TYPE_UDP,
1308 RTE_FLOW_ITEM_TYPE_RAW,
1309 RTE_FLOW_ITEM_TYPE_VF,
1310 RTE_FLOW_ITEM_TYPE_END,
1313 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1314 RTE_FLOW_ITEM_TYPE_ETH,
1315 RTE_FLOW_ITEM_TYPE_VLAN,
1316 RTE_FLOW_ITEM_TYPE_IPV4,
1317 RTE_FLOW_ITEM_TYPE_UDP,
1318 RTE_FLOW_ITEM_TYPE_RAW,
1319 RTE_FLOW_ITEM_TYPE_RAW,
1320 RTE_FLOW_ITEM_TYPE_VF,
1321 RTE_FLOW_ITEM_TYPE_END,
1324 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1325 RTE_FLOW_ITEM_TYPE_ETH,
1326 RTE_FLOW_ITEM_TYPE_VLAN,
1327 RTE_FLOW_ITEM_TYPE_IPV4,
1328 RTE_FLOW_ITEM_TYPE_UDP,
1329 RTE_FLOW_ITEM_TYPE_RAW,
1330 RTE_FLOW_ITEM_TYPE_RAW,
1331 RTE_FLOW_ITEM_TYPE_RAW,
1332 RTE_FLOW_ITEM_TYPE_VF,
1333 RTE_FLOW_ITEM_TYPE_END,
1336 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1337 RTE_FLOW_ITEM_TYPE_ETH,
1338 RTE_FLOW_ITEM_TYPE_VLAN,
1339 RTE_FLOW_ITEM_TYPE_IPV4,
1340 RTE_FLOW_ITEM_TYPE_TCP,
1341 RTE_FLOW_ITEM_TYPE_RAW,
1342 RTE_FLOW_ITEM_TYPE_VF,
1343 RTE_FLOW_ITEM_TYPE_END,
1346 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1347 RTE_FLOW_ITEM_TYPE_ETH,
1348 RTE_FLOW_ITEM_TYPE_VLAN,
1349 RTE_FLOW_ITEM_TYPE_IPV4,
1350 RTE_FLOW_ITEM_TYPE_TCP,
1351 RTE_FLOW_ITEM_TYPE_RAW,
1352 RTE_FLOW_ITEM_TYPE_RAW,
1353 RTE_FLOW_ITEM_TYPE_VF,
1354 RTE_FLOW_ITEM_TYPE_END,
1357 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1358 RTE_FLOW_ITEM_TYPE_ETH,
1359 RTE_FLOW_ITEM_TYPE_VLAN,
1360 RTE_FLOW_ITEM_TYPE_IPV4,
1361 RTE_FLOW_ITEM_TYPE_TCP,
1362 RTE_FLOW_ITEM_TYPE_RAW,
1363 RTE_FLOW_ITEM_TYPE_RAW,
1364 RTE_FLOW_ITEM_TYPE_RAW,
1365 RTE_FLOW_ITEM_TYPE_VF,
1366 RTE_FLOW_ITEM_TYPE_END,
1369 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1370 RTE_FLOW_ITEM_TYPE_ETH,
1371 RTE_FLOW_ITEM_TYPE_VLAN,
1372 RTE_FLOW_ITEM_TYPE_IPV4,
1373 RTE_FLOW_ITEM_TYPE_SCTP,
1374 RTE_FLOW_ITEM_TYPE_RAW,
1375 RTE_FLOW_ITEM_TYPE_VF,
1376 RTE_FLOW_ITEM_TYPE_END,
1379 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1380 RTE_FLOW_ITEM_TYPE_ETH,
1381 RTE_FLOW_ITEM_TYPE_VLAN,
1382 RTE_FLOW_ITEM_TYPE_IPV4,
1383 RTE_FLOW_ITEM_TYPE_SCTP,
1384 RTE_FLOW_ITEM_TYPE_RAW,
1385 RTE_FLOW_ITEM_TYPE_RAW,
1386 RTE_FLOW_ITEM_TYPE_VF,
1387 RTE_FLOW_ITEM_TYPE_END,
1390 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1391 RTE_FLOW_ITEM_TYPE_ETH,
1392 RTE_FLOW_ITEM_TYPE_VLAN,
1393 RTE_FLOW_ITEM_TYPE_IPV4,
1394 RTE_FLOW_ITEM_TYPE_SCTP,
1395 RTE_FLOW_ITEM_TYPE_RAW,
1396 RTE_FLOW_ITEM_TYPE_RAW,
1397 RTE_FLOW_ITEM_TYPE_RAW,
1398 RTE_FLOW_ITEM_TYPE_VF,
1399 RTE_FLOW_ITEM_TYPE_END,
1402 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1403 RTE_FLOW_ITEM_TYPE_ETH,
1404 RTE_FLOW_ITEM_TYPE_VLAN,
1405 RTE_FLOW_ITEM_TYPE_IPV6,
1406 RTE_FLOW_ITEM_TYPE_RAW,
1407 RTE_FLOW_ITEM_TYPE_VF,
1408 RTE_FLOW_ITEM_TYPE_END,
1411 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1412 RTE_FLOW_ITEM_TYPE_ETH,
1413 RTE_FLOW_ITEM_TYPE_VLAN,
1414 RTE_FLOW_ITEM_TYPE_IPV6,
1415 RTE_FLOW_ITEM_TYPE_RAW,
1416 RTE_FLOW_ITEM_TYPE_RAW,
1417 RTE_FLOW_ITEM_TYPE_VF,
1418 RTE_FLOW_ITEM_TYPE_END,
1421 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1422 RTE_FLOW_ITEM_TYPE_ETH,
1423 RTE_FLOW_ITEM_TYPE_VLAN,
1424 RTE_FLOW_ITEM_TYPE_IPV6,
1425 RTE_FLOW_ITEM_TYPE_RAW,
1426 RTE_FLOW_ITEM_TYPE_RAW,
1427 RTE_FLOW_ITEM_TYPE_RAW,
1428 RTE_FLOW_ITEM_TYPE_VF,
1429 RTE_FLOW_ITEM_TYPE_END,
1432 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1433 RTE_FLOW_ITEM_TYPE_ETH,
1434 RTE_FLOW_ITEM_TYPE_VLAN,
1435 RTE_FLOW_ITEM_TYPE_IPV6,
1436 RTE_FLOW_ITEM_TYPE_UDP,
1437 RTE_FLOW_ITEM_TYPE_RAW,
1438 RTE_FLOW_ITEM_TYPE_VF,
1439 RTE_FLOW_ITEM_TYPE_END,
1442 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1443 RTE_FLOW_ITEM_TYPE_ETH,
1444 RTE_FLOW_ITEM_TYPE_VLAN,
1445 RTE_FLOW_ITEM_TYPE_IPV6,
1446 RTE_FLOW_ITEM_TYPE_UDP,
1447 RTE_FLOW_ITEM_TYPE_RAW,
1448 RTE_FLOW_ITEM_TYPE_RAW,
1449 RTE_FLOW_ITEM_TYPE_VF,
1450 RTE_FLOW_ITEM_TYPE_END,
1453 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1454 RTE_FLOW_ITEM_TYPE_ETH,
1455 RTE_FLOW_ITEM_TYPE_VLAN,
1456 RTE_FLOW_ITEM_TYPE_IPV6,
1457 RTE_FLOW_ITEM_TYPE_UDP,
1458 RTE_FLOW_ITEM_TYPE_RAW,
1459 RTE_FLOW_ITEM_TYPE_RAW,
1460 RTE_FLOW_ITEM_TYPE_RAW,
1461 RTE_FLOW_ITEM_TYPE_VF,
1462 RTE_FLOW_ITEM_TYPE_END,
1465 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1466 RTE_FLOW_ITEM_TYPE_ETH,
1467 RTE_FLOW_ITEM_TYPE_VLAN,
1468 RTE_FLOW_ITEM_TYPE_IPV6,
1469 RTE_FLOW_ITEM_TYPE_TCP,
1470 RTE_FLOW_ITEM_TYPE_RAW,
1471 RTE_FLOW_ITEM_TYPE_VF,
1472 RTE_FLOW_ITEM_TYPE_END,
1475 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1476 RTE_FLOW_ITEM_TYPE_ETH,
1477 RTE_FLOW_ITEM_TYPE_VLAN,
1478 RTE_FLOW_ITEM_TYPE_IPV6,
1479 RTE_FLOW_ITEM_TYPE_TCP,
1480 RTE_FLOW_ITEM_TYPE_RAW,
1481 RTE_FLOW_ITEM_TYPE_RAW,
1482 RTE_FLOW_ITEM_TYPE_VF,
1483 RTE_FLOW_ITEM_TYPE_END,
1486 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1487 RTE_FLOW_ITEM_TYPE_ETH,
1488 RTE_FLOW_ITEM_TYPE_VLAN,
1489 RTE_FLOW_ITEM_TYPE_IPV6,
1490 RTE_FLOW_ITEM_TYPE_TCP,
1491 RTE_FLOW_ITEM_TYPE_RAW,
1492 RTE_FLOW_ITEM_TYPE_RAW,
1493 RTE_FLOW_ITEM_TYPE_RAW,
1494 RTE_FLOW_ITEM_TYPE_VF,
1495 RTE_FLOW_ITEM_TYPE_END,
1498 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1499 RTE_FLOW_ITEM_TYPE_ETH,
1500 RTE_FLOW_ITEM_TYPE_VLAN,
1501 RTE_FLOW_ITEM_TYPE_IPV6,
1502 RTE_FLOW_ITEM_TYPE_SCTP,
1503 RTE_FLOW_ITEM_TYPE_RAW,
1504 RTE_FLOW_ITEM_TYPE_VF,
1505 RTE_FLOW_ITEM_TYPE_END,
1508 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1509 RTE_FLOW_ITEM_TYPE_ETH,
1510 RTE_FLOW_ITEM_TYPE_VLAN,
1511 RTE_FLOW_ITEM_TYPE_IPV6,
1512 RTE_FLOW_ITEM_TYPE_SCTP,
1513 RTE_FLOW_ITEM_TYPE_RAW,
1514 RTE_FLOW_ITEM_TYPE_RAW,
1515 RTE_FLOW_ITEM_TYPE_VF,
1516 RTE_FLOW_ITEM_TYPE_END,
1519 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1520 RTE_FLOW_ITEM_TYPE_ETH,
1521 RTE_FLOW_ITEM_TYPE_VLAN,
1522 RTE_FLOW_ITEM_TYPE_IPV6,
1523 RTE_FLOW_ITEM_TYPE_SCTP,
1524 RTE_FLOW_ITEM_TYPE_RAW,
1525 RTE_FLOW_ITEM_TYPE_RAW,
1526 RTE_FLOW_ITEM_TYPE_RAW,
1527 RTE_FLOW_ITEM_TYPE_VF,
1528 RTE_FLOW_ITEM_TYPE_END,
1531 /* Pattern matched tunnel filter */
1532 static enum rte_flow_item_type pattern_vxlan_1[] = {
1533 RTE_FLOW_ITEM_TYPE_ETH,
1534 RTE_FLOW_ITEM_TYPE_IPV4,
1535 RTE_FLOW_ITEM_TYPE_UDP,
1536 RTE_FLOW_ITEM_TYPE_VXLAN,
1537 RTE_FLOW_ITEM_TYPE_ETH,
1538 RTE_FLOW_ITEM_TYPE_END,
1541 static enum rte_flow_item_type pattern_vxlan_2[] = {
1542 RTE_FLOW_ITEM_TYPE_ETH,
1543 RTE_FLOW_ITEM_TYPE_IPV6,
1544 RTE_FLOW_ITEM_TYPE_UDP,
1545 RTE_FLOW_ITEM_TYPE_VXLAN,
1546 RTE_FLOW_ITEM_TYPE_ETH,
1547 RTE_FLOW_ITEM_TYPE_END,
1550 static enum rte_flow_item_type pattern_vxlan_3[] = {
1551 RTE_FLOW_ITEM_TYPE_ETH,
1552 RTE_FLOW_ITEM_TYPE_IPV4,
1553 RTE_FLOW_ITEM_TYPE_UDP,
1554 RTE_FLOW_ITEM_TYPE_VXLAN,
1555 RTE_FLOW_ITEM_TYPE_ETH,
1556 RTE_FLOW_ITEM_TYPE_VLAN,
1557 RTE_FLOW_ITEM_TYPE_END,
1560 static enum rte_flow_item_type pattern_vxlan_4[] = {
1561 RTE_FLOW_ITEM_TYPE_ETH,
1562 RTE_FLOW_ITEM_TYPE_IPV6,
1563 RTE_FLOW_ITEM_TYPE_UDP,
1564 RTE_FLOW_ITEM_TYPE_VXLAN,
1565 RTE_FLOW_ITEM_TYPE_ETH,
1566 RTE_FLOW_ITEM_TYPE_VLAN,
1567 RTE_FLOW_ITEM_TYPE_END,
1570 static enum rte_flow_item_type pattern_nvgre_1[] = {
1571 RTE_FLOW_ITEM_TYPE_ETH,
1572 RTE_FLOW_ITEM_TYPE_IPV4,
1573 RTE_FLOW_ITEM_TYPE_NVGRE,
1574 RTE_FLOW_ITEM_TYPE_ETH,
1575 RTE_FLOW_ITEM_TYPE_END,
1578 static enum rte_flow_item_type pattern_nvgre_2[] = {
1579 RTE_FLOW_ITEM_TYPE_ETH,
1580 RTE_FLOW_ITEM_TYPE_IPV6,
1581 RTE_FLOW_ITEM_TYPE_NVGRE,
1582 RTE_FLOW_ITEM_TYPE_ETH,
1583 RTE_FLOW_ITEM_TYPE_END,
1586 static enum rte_flow_item_type pattern_nvgre_3[] = {
1587 RTE_FLOW_ITEM_TYPE_ETH,
1588 RTE_FLOW_ITEM_TYPE_IPV4,
1589 RTE_FLOW_ITEM_TYPE_NVGRE,
1590 RTE_FLOW_ITEM_TYPE_ETH,
1591 RTE_FLOW_ITEM_TYPE_VLAN,
1592 RTE_FLOW_ITEM_TYPE_END,
1595 static enum rte_flow_item_type pattern_nvgre_4[] = {
1596 RTE_FLOW_ITEM_TYPE_ETH,
1597 RTE_FLOW_ITEM_TYPE_IPV6,
1598 RTE_FLOW_ITEM_TYPE_NVGRE,
1599 RTE_FLOW_ITEM_TYPE_ETH,
1600 RTE_FLOW_ITEM_TYPE_VLAN,
1601 RTE_FLOW_ITEM_TYPE_END,
1604 static enum rte_flow_item_type pattern_mpls_1[] = {
1605 RTE_FLOW_ITEM_TYPE_ETH,
1606 RTE_FLOW_ITEM_TYPE_IPV4,
1607 RTE_FLOW_ITEM_TYPE_UDP,
1608 RTE_FLOW_ITEM_TYPE_MPLS,
1609 RTE_FLOW_ITEM_TYPE_END,
1612 static enum rte_flow_item_type pattern_mpls_2[] = {
1613 RTE_FLOW_ITEM_TYPE_ETH,
1614 RTE_FLOW_ITEM_TYPE_IPV6,
1615 RTE_FLOW_ITEM_TYPE_UDP,
1616 RTE_FLOW_ITEM_TYPE_MPLS,
1617 RTE_FLOW_ITEM_TYPE_END,
1620 static enum rte_flow_item_type pattern_mpls_3[] = {
1621 RTE_FLOW_ITEM_TYPE_ETH,
1622 RTE_FLOW_ITEM_TYPE_IPV4,
1623 RTE_FLOW_ITEM_TYPE_GRE,
1624 RTE_FLOW_ITEM_TYPE_MPLS,
1625 RTE_FLOW_ITEM_TYPE_END,
1628 static enum rte_flow_item_type pattern_mpls_4[] = {
1629 RTE_FLOW_ITEM_TYPE_ETH,
1630 RTE_FLOW_ITEM_TYPE_IPV6,
1631 RTE_FLOW_ITEM_TYPE_GRE,
1632 RTE_FLOW_ITEM_TYPE_MPLS,
1633 RTE_FLOW_ITEM_TYPE_END,
1636 static enum rte_flow_item_type pattern_qinq_1[] = {
1637 RTE_FLOW_ITEM_TYPE_ETH,
1638 RTE_FLOW_ITEM_TYPE_VLAN,
1639 RTE_FLOW_ITEM_TYPE_VLAN,
1640 RTE_FLOW_ITEM_TYPE_END,
1643 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1645 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1646 /* FDIR - support default flow type without flexible payload*/
1647 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1648 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1649 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1650 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1651 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1652 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1653 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1654 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1655 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1656 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1657 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1658 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1659 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1660 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1661 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1662 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1663 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1664 /* FDIR - support default flow type with flexible payload */
1665 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1666 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1667 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1668 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1669 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1692 /* FDIR - support single vlan input set */
1693 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1703 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1704 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1705 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1729 /* FDIR - support VF item */
1730 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1731 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1732 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1751 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1752 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1768 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1769 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1775 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1776 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1777 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1778 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1779 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1780 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1781 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1782 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1783 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1784 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1785 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1786 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1787 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1788 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1789 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1790 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1791 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1792 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1793 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1794 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1795 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1796 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1797 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1798 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1799 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1800 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1802 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1803 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1804 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1805 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1807 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1808 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1809 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1810 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1811 /* MPLSoUDP & MPLSoGRE */
1812 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1813 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1814 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1815 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1817 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1818 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1819 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1820 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1822 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1825 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1827 act = actions + index; \
1828 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1830 act = actions + index; \
1834 /* Find the first VOID or non-VOID item pointer */
1835 static const struct rte_flow_item *
1836 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1840 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1842 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1844 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1852 /* Skip all VOID items of the pattern */
1854 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1855 const struct rte_flow_item *pattern)
1857 uint32_t cpy_count = 0;
1858 const struct rte_flow_item *pb = pattern, *pe = pattern;
1861 /* Find a non-void item first */
1862 pb = i40e_find_first_item(pb, false);
1863 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1868 /* Find a void item */
1869 pe = i40e_find_first_item(pb + 1, true);
1871 cpy_count = pe - pb;
1872 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1876 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1883 /* Copy the END item. */
1884 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1887 /* Check if the pattern matches a supported item type array */
1889 i40e_match_pattern(enum rte_flow_item_type *item_array,
1890 struct rte_flow_item *pattern)
1892 struct rte_flow_item *item = pattern;
1894 while ((*item_array == item->type) &&
1895 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1900 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1901 item->type == RTE_FLOW_ITEM_TYPE_END);
1904 /* Find if there's parse filter function matched */
1905 static parse_filter_t
1906 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1908 parse_filter_t parse_filter = NULL;
1911 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1912 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1914 parse_filter = i40e_supported_patterns[i].parse_filter;
1921 return parse_filter;
1924 /* Parse attributes */
1926 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1927 struct rte_flow_error *error)
1929 /* Must be input direction */
1930 if (!attr->ingress) {
1931 rte_flow_error_set(error, EINVAL,
1932 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1933 attr, "Only support ingress.");
1939 rte_flow_error_set(error, EINVAL,
1940 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1941 attr, "Not support egress.");
1946 if (attr->priority) {
1947 rte_flow_error_set(error, EINVAL,
1948 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1949 attr, "Not support priority.");
1955 rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1957 attr, "Not support group.");
1965 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1967 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1978 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1981 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1986 /* 1. Last in item should be NULL as range is not supported.
1987 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1988 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1989 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1991 * 5. Ether_type mask should be 0xFFFF.
1994 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1995 const struct rte_flow_item *pattern,
1996 struct rte_flow_error *error,
1997 struct rte_eth_ethertype_filter *filter)
1999 const struct rte_flow_item *item = pattern;
2000 const struct rte_flow_item_eth *eth_spec;
2001 const struct rte_flow_item_eth *eth_mask;
2002 enum rte_flow_item_type item_type;
2003 uint16_t outer_tpid;
2005 outer_tpid = i40e_get_outer_vlan(dev);
2007 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2009 rte_flow_error_set(error, EINVAL,
2010 RTE_FLOW_ERROR_TYPE_ITEM,
2012 "Not support range");
2015 item_type = item->type;
2016 switch (item_type) {
2017 case RTE_FLOW_ITEM_TYPE_ETH:
2018 eth_spec = (const struct rte_flow_item_eth *)item->spec;
2019 eth_mask = (const struct rte_flow_item_eth *)item->mask;
2020 /* Get the MAC info. */
2021 if (!eth_spec || !eth_mask) {
2022 rte_flow_error_set(error, EINVAL,
2023 RTE_FLOW_ERROR_TYPE_ITEM,
2025 "NULL ETH spec/mask");
2029 /* Mask bits of source MAC address must be full of 0.
2030 * Mask bits of destination MAC address must be full
2031 * of 1 or full of 0.
2033 if (!is_zero_ether_addr(ð_mask->src) ||
2034 (!is_zero_ether_addr(ð_mask->dst) &&
2035 !is_broadcast_ether_addr(ð_mask->dst))) {
2036 rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ITEM,
2039 "Invalid MAC_addr mask");
2043 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2044 rte_flow_error_set(error, EINVAL,
2045 RTE_FLOW_ERROR_TYPE_ITEM,
2047 "Invalid ethertype mask");
2051 /* If mask bits of destination MAC address
2052 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2054 if (is_broadcast_ether_addr(ð_mask->dst)) {
2055 filter->mac_addr = eth_spec->dst;
2056 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2058 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2060 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2062 if (filter->ether_type == ETHER_TYPE_IPv4 ||
2063 filter->ether_type == ETHER_TYPE_IPv6 ||
2064 filter->ether_type == ETHER_TYPE_LLDP ||
2065 filter->ether_type == outer_tpid) {
2066 rte_flow_error_set(error, EINVAL,
2067 RTE_FLOW_ERROR_TYPE_ITEM,
2069 "Unsupported ether_type in"
2070 " control packet filter.");
2082 /* Ethertype action only supports QUEUE or DROP. */
2084 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2085 const struct rte_flow_action *actions,
2086 struct rte_flow_error *error,
2087 struct rte_eth_ethertype_filter *filter)
2089 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2090 const struct rte_flow_action *act;
2091 const struct rte_flow_action_queue *act_q;
2094 /* Check if the first non-void action is QUEUE or DROP. */
2095 NEXT_ITEM_OF_ACTION(act, actions, index);
2096 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2097 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2098 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2099 act, "Not supported action.");
2103 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2104 act_q = (const struct rte_flow_action_queue *)act->conf;
2105 filter->queue = act_q->index;
2106 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2107 rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ACTION,
2109 act, "Invalid queue ID for"
2110 " ethertype_filter.");
2114 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2117 /* Check if the next non-void item is END */
2119 NEXT_ITEM_OF_ACTION(act, actions, index);
2120 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2121 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2122 act, "Not supported action.");
2130 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2131 const struct rte_flow_attr *attr,
2132 const struct rte_flow_item pattern[],
2133 const struct rte_flow_action actions[],
2134 struct rte_flow_error *error,
2135 union i40e_filter_t *filter)
2137 struct rte_eth_ethertype_filter *ethertype_filter =
2138 &filter->ethertype_filter;
2141 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2146 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2151 ret = i40e_flow_parse_attr(attr, error);
2155 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2161 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2162 const struct rte_flow_item_raw *raw_spec,
2163 struct rte_flow_error *error)
2165 if (!raw_spec->relative) {
2166 rte_flow_error_set(error, EINVAL,
2167 RTE_FLOW_ERROR_TYPE_ITEM,
2169 "Relative should be 1.");
2173 if (raw_spec->offset % sizeof(uint16_t)) {
2174 rte_flow_error_set(error, EINVAL,
2175 RTE_FLOW_ERROR_TYPE_ITEM,
2177 "Offset should be even.");
2181 if (raw_spec->search || raw_spec->limit) {
2182 rte_flow_error_set(error, EINVAL,
2183 RTE_FLOW_ERROR_TYPE_ITEM,
2185 "search or limit is not supported.");
2189 if (raw_spec->offset < 0) {
2190 rte_flow_error_set(error, EINVAL,
2191 RTE_FLOW_ERROR_TYPE_ITEM,
2193 "Offset should be non-negative.");
2200 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2201 struct i40e_fdir_flex_pit *flex_pit,
2202 enum i40e_flxpld_layer_idx layer_idx,
2207 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2208 /* Check if the configuration is conflicted */
2209 if (pf->fdir.flex_pit_flag[layer_idx] &&
2210 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2211 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2212 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2215 /* Check if the configuration exists. */
2216 if (pf->fdir.flex_pit_flag[layer_idx] &&
2217 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2218 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2219 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2222 pf->fdir.flex_set[field_idx].src_offset =
2223 flex_pit->src_offset;
2224 pf->fdir.flex_set[field_idx].size =
2226 pf->fdir.flex_set[field_idx].dst_offset =
2227 flex_pit->dst_offset;
2233 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2234 enum i40e_filter_pctype pctype,
2237 struct i40e_fdir_flex_mask flex_mask;
2239 uint8_t i, nb_bitmask = 0;
2241 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2242 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2243 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2245 flex_mask.word_mask |=
2246 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2247 if (mask_tmp != UINT16_MAX) {
2248 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2249 flex_mask.bitmask[nb_bitmask].offset =
2250 i / sizeof(uint16_t);
2252 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2257 flex_mask.nb_bitmask = nb_bitmask;
2259 if (pf->fdir.flex_mask_flag[pctype] &&
2260 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2261 sizeof(struct i40e_fdir_flex_mask))))
2263 else if (pf->fdir.flex_mask_flag[pctype] &&
2264 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2265 sizeof(struct i40e_fdir_flex_mask))))
2268 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2269 sizeof(struct i40e_fdir_flex_mask));
2274 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2275 enum i40e_flxpld_layer_idx layer_idx,
2278 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2281 uint16_t min_next_off = 0; /* in words */
2285 for (i = 0; i < raw_id; i++) {
2286 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2287 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2288 pf->fdir.flex_set[field_idx].size,
2289 pf->fdir.flex_set[field_idx].dst_offset);
2291 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2292 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2293 pf->fdir.flex_set[field_idx].size;
2296 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2297 /* set the non-used register obeying register's constrain */
2298 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2299 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2300 NONUSE_FLX_PIT_DEST_OFF);
2301 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2305 pf->fdir.flex_pit_flag[layer_idx] = 1;
2309 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2310 enum i40e_filter_pctype pctype)
2312 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2313 struct i40e_fdir_flex_mask *flex_mask;
2314 uint32_t flxinset, fd_mask;
2318 flex_mask = &pf->fdir.flex_mask[pctype];
2319 flxinset = (flex_mask->word_mask <<
2320 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2321 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2322 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2324 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2325 fd_mask = (flex_mask->bitmask[i].mask <<
2326 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2327 I40E_PRTQF_FD_MSK_MASK_MASK;
2328 fd_mask |= ((flex_mask->bitmask[i].offset +
2329 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2330 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2331 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2332 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2335 pf->fdir.flex_mask_flag[pctype] = 1;
2339 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2340 enum i40e_filter_pctype pctype,
2343 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2344 uint64_t inset_reg = 0;
2345 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2348 /* Check if the input set is valid */
2349 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2351 PMD_DRV_LOG(ERR, "Invalid input set");
2355 /* Check if the configuration is conflicted */
2356 if (pf->fdir.inset_flag[pctype] &&
2357 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2360 if (pf->fdir.inset_flag[pctype] &&
2361 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2364 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2365 I40E_INSET_MASK_NUM_REG);
2369 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2371 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2372 (uint32_t)(inset_reg & UINT32_MAX));
2373 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2374 (uint32_t)((inset_reg >>
2375 I40E_32_BIT_WIDTH) & UINT32_MAX));
2377 for (i = 0; i < num; i++)
2378 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2381 /*clear unused mask registers of the pctype */
2382 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2383 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2384 I40E_WRITE_FLUSH(hw);
2386 pf->fdir.input_set[pctype] = input_set;
2387 pf->fdir.inset_flag[pctype] = 1;
2392 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2393 enum rte_flow_item_type item_type,
2394 struct i40e_fdir_filter_conf *filter)
2396 struct i40e_customized_pctype *cus_pctype = NULL;
2398 switch (item_type) {
2399 case RTE_FLOW_ITEM_TYPE_GTPC:
2400 cus_pctype = i40e_find_customized_pctype(pf,
2401 I40E_CUSTOMIZED_GTPC);
2403 case RTE_FLOW_ITEM_TYPE_GTPU:
2404 if (!filter->input.flow_ext.inner_ip)
2405 cus_pctype = i40e_find_customized_pctype(pf,
2406 I40E_CUSTOMIZED_GTPU);
2407 else if (filter->input.flow_ext.iip_type ==
2408 I40E_FDIR_IPTYPE_IPV4)
2409 cus_pctype = i40e_find_customized_pctype(pf,
2410 I40E_CUSTOMIZED_GTPU_IPV4);
2411 else if (filter->input.flow_ext.iip_type ==
2412 I40E_FDIR_IPTYPE_IPV6)
2413 cus_pctype = i40e_find_customized_pctype(pf,
2414 I40E_CUSTOMIZED_GTPU_IPV6);
2417 PMD_DRV_LOG(ERR, "Unsupported item type");
2422 return cus_pctype->pctype;
2424 return I40E_FILTER_PCTYPE_INVALID;
2427 /* 1. Last in item should be NULL as range is not supported.
2428 * 2. Supported patterns: refer to array i40e_supported_patterns.
2429 * 3. Default supported flow type and input set: refer to array
2430 * valid_fdir_inset_table in i40e_ethdev.c.
2431 * 4. Mask of fields which need to be matched should be
2433 * 5. Mask of fields which needn't to be matched should be
2435 * 6. GTP profile supports GTPv1 only.
2436 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2439 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2440 const struct rte_flow_item *pattern,
2441 struct rte_flow_error *error,
2442 struct i40e_fdir_filter_conf *filter)
2444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2445 const struct rte_flow_item *item = pattern;
2446 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2447 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2448 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2449 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2450 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2451 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2452 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2453 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2454 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2455 const struct rte_flow_item_vf *vf_spec;
2458 uint64_t input_set = I40E_INSET_NONE;
2460 enum rte_flow_item_type item_type;
2461 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2462 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2464 uint8_t ipv6_addr_mask[16] = {
2465 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2466 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2467 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2469 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2470 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2471 struct i40e_fdir_flex_pit flex_pit;
2472 uint8_t next_dst_off = 0;
2473 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2475 bool cfg_flex_pit = true;
2476 bool cfg_flex_msk = true;
2477 uint16_t outer_tpid;
2478 uint16_t ether_type;
2479 uint32_t vtc_flow_cpu;
2480 bool outer_ip = true;
2483 memset(off_arr, 0, sizeof(off_arr));
2484 memset(len_arr, 0, sizeof(len_arr));
2485 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2486 outer_tpid = i40e_get_outer_vlan(dev);
2487 filter->input.flow_ext.customized_pctype = false;
2488 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2490 rte_flow_error_set(error, EINVAL,
2491 RTE_FLOW_ERROR_TYPE_ITEM,
2493 "Not support range");
2496 item_type = item->type;
2497 switch (item_type) {
2498 case RTE_FLOW_ITEM_TYPE_ETH:
2499 eth_spec = (const struct rte_flow_item_eth *)item->spec;
2500 eth_mask = (const struct rte_flow_item_eth *)item->mask;
2502 if (eth_spec && eth_mask) {
2503 if (!is_zero_ether_addr(ð_mask->src) ||
2504 !is_zero_ether_addr(ð_mask->dst)) {
2505 rte_flow_error_set(error, EINVAL,
2506 RTE_FLOW_ERROR_TYPE_ITEM,
2508 "Invalid MAC_addr mask.");
2512 if ((eth_mask->type & UINT16_MAX) ==
2514 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2515 filter->input.flow.l2_flow.ether_type =
2519 ether_type = rte_be_to_cpu_16(eth_spec->type);
2520 if (ether_type == ETHER_TYPE_IPv4 ||
2521 ether_type == ETHER_TYPE_IPv6 ||
2522 ether_type == ETHER_TYPE_ARP ||
2523 ether_type == outer_tpid) {
2524 rte_flow_error_set(error, EINVAL,
2525 RTE_FLOW_ERROR_TYPE_ITEM,
2527 "Unsupported ether_type.");
2532 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2533 layer_idx = I40E_FLXPLD_L2_IDX;
2536 case RTE_FLOW_ITEM_TYPE_VLAN:
2538 (const struct rte_flow_item_vlan *)item->spec;
2540 (const struct rte_flow_item_vlan *)item->mask;
2541 if (vlan_spec && vlan_mask) {
2542 if (vlan_mask->tci ==
2543 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2544 input_set |= I40E_INSET_VLAN_INNER;
2545 filter->input.flow_ext.vlan_tci =
2550 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2551 layer_idx = I40E_FLXPLD_L2_IDX;
2554 case RTE_FLOW_ITEM_TYPE_IPV4:
2555 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2557 (const struct rte_flow_item_ipv4 *)item->spec;
2559 (const struct rte_flow_item_ipv4 *)item->mask;
2560 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2561 layer_idx = I40E_FLXPLD_L3_IDX;
2563 if (ipv4_spec && ipv4_mask && outer_ip) {
2564 /* Check IPv4 mask and update input set */
2565 if (ipv4_mask->hdr.version_ihl ||
2566 ipv4_mask->hdr.total_length ||
2567 ipv4_mask->hdr.packet_id ||
2568 ipv4_mask->hdr.fragment_offset ||
2569 ipv4_mask->hdr.hdr_checksum) {
2570 rte_flow_error_set(error, EINVAL,
2571 RTE_FLOW_ERROR_TYPE_ITEM,
2573 "Invalid IPv4 mask.");
2577 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2578 input_set |= I40E_INSET_IPV4_SRC;
2579 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2580 input_set |= I40E_INSET_IPV4_DST;
2581 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2582 input_set |= I40E_INSET_IPV4_TOS;
2583 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2584 input_set |= I40E_INSET_IPV4_TTL;
2585 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2586 input_set |= I40E_INSET_IPV4_PROTO;
2588 /* Check if it is fragment. */
2589 frag_off = ipv4_spec->hdr.fragment_offset;
2590 frag_off = rte_be_to_cpu_16(frag_off);
2591 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2592 frag_off & IPV4_HDR_MF_FLAG)
2593 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2595 /* Get the filter info */
2596 filter->input.flow.ip4_flow.proto =
2597 ipv4_spec->hdr.next_proto_id;
2598 filter->input.flow.ip4_flow.tos =
2599 ipv4_spec->hdr.type_of_service;
2600 filter->input.flow.ip4_flow.ttl =
2601 ipv4_spec->hdr.time_to_live;
2602 filter->input.flow.ip4_flow.src_ip =
2603 ipv4_spec->hdr.src_addr;
2604 filter->input.flow.ip4_flow.dst_ip =
2605 ipv4_spec->hdr.dst_addr;
2606 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2607 filter->input.flow_ext.inner_ip = true;
2608 filter->input.flow_ext.iip_type =
2609 I40E_FDIR_IPTYPE_IPV4;
2610 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2611 rte_flow_error_set(error, EINVAL,
2612 RTE_FLOW_ERROR_TYPE_ITEM,
2614 "Invalid inner IPv4 mask.");
2622 case RTE_FLOW_ITEM_TYPE_IPV6:
2623 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2625 (const struct rte_flow_item_ipv6 *)item->spec;
2627 (const struct rte_flow_item_ipv6 *)item->mask;
2628 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2629 layer_idx = I40E_FLXPLD_L3_IDX;
2631 if (ipv6_spec && ipv6_mask && outer_ip) {
2632 /* Check IPv6 mask and update input set */
2633 if (ipv6_mask->hdr.payload_len) {
2634 rte_flow_error_set(error, EINVAL,
2635 RTE_FLOW_ERROR_TYPE_ITEM,
2637 "Invalid IPv6 mask");
2641 if (!memcmp(ipv6_mask->hdr.src_addr,
2643 RTE_DIM(ipv6_mask->hdr.src_addr)))
2644 input_set |= I40E_INSET_IPV6_SRC;
2645 if (!memcmp(ipv6_mask->hdr.dst_addr,
2647 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2648 input_set |= I40E_INSET_IPV6_DST;
2650 if ((ipv6_mask->hdr.vtc_flow &
2651 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2652 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2653 input_set |= I40E_INSET_IPV6_TC;
2654 if (ipv6_mask->hdr.proto == UINT8_MAX)
2655 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2656 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2657 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2659 /* Get filter info */
2661 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2662 filter->input.flow.ipv6_flow.tc =
2663 (uint8_t)(vtc_flow_cpu >>
2664 I40E_FDIR_IPv6_TC_OFFSET);
2665 filter->input.flow.ipv6_flow.proto =
2666 ipv6_spec->hdr.proto;
2667 filter->input.flow.ipv6_flow.hop_limits =
2668 ipv6_spec->hdr.hop_limits;
2670 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2671 ipv6_spec->hdr.src_addr, 16);
2672 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2673 ipv6_spec->hdr.dst_addr, 16);
2675 /* Check if it is fragment. */
2676 if (ipv6_spec->hdr.proto ==
2677 I40E_IPV6_FRAG_HEADER)
2678 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2679 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2680 filter->input.flow_ext.inner_ip = true;
2681 filter->input.flow_ext.iip_type =
2682 I40E_FDIR_IPTYPE_IPV6;
2683 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2684 rte_flow_error_set(error, EINVAL,
2685 RTE_FLOW_ERROR_TYPE_ITEM,
2687 "Invalid inner IPv6 mask");
2694 case RTE_FLOW_ITEM_TYPE_TCP:
2695 tcp_spec = (const struct rte_flow_item_tcp *)item->spec;
2696 tcp_mask = (const struct rte_flow_item_tcp *)item->mask;
2698 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2700 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2701 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2703 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2704 if (tcp_spec && tcp_mask) {
2705 /* Check TCP mask and update input set */
2706 if (tcp_mask->hdr.sent_seq ||
2707 tcp_mask->hdr.recv_ack ||
2708 tcp_mask->hdr.data_off ||
2709 tcp_mask->hdr.tcp_flags ||
2710 tcp_mask->hdr.rx_win ||
2711 tcp_mask->hdr.cksum ||
2712 tcp_mask->hdr.tcp_urp) {
2713 rte_flow_error_set(error, EINVAL,
2714 RTE_FLOW_ERROR_TYPE_ITEM,
2716 "Invalid TCP mask");
2720 if (tcp_mask->hdr.src_port == UINT16_MAX)
2721 input_set |= I40E_INSET_SRC_PORT;
2722 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2723 input_set |= I40E_INSET_DST_PORT;
2725 /* Get filter info */
2726 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2727 filter->input.flow.tcp4_flow.src_port =
2728 tcp_spec->hdr.src_port;
2729 filter->input.flow.tcp4_flow.dst_port =
2730 tcp_spec->hdr.dst_port;
2731 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2732 filter->input.flow.tcp6_flow.src_port =
2733 tcp_spec->hdr.src_port;
2734 filter->input.flow.tcp6_flow.dst_port =
2735 tcp_spec->hdr.dst_port;
2739 layer_idx = I40E_FLXPLD_L4_IDX;
2742 case RTE_FLOW_ITEM_TYPE_UDP:
2743 udp_spec = (const struct rte_flow_item_udp *)item->spec;
2744 udp_mask = (const struct rte_flow_item_udp *)item->mask;
2746 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2748 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2749 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2751 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2753 if (udp_spec && udp_mask) {
2754 /* Check UDP mask and update input set*/
2755 if (udp_mask->hdr.dgram_len ||
2756 udp_mask->hdr.dgram_cksum) {
2757 rte_flow_error_set(error, EINVAL,
2758 RTE_FLOW_ERROR_TYPE_ITEM,
2760 "Invalid UDP mask");
2764 if (udp_mask->hdr.src_port == UINT16_MAX)
2765 input_set |= I40E_INSET_SRC_PORT;
2766 if (udp_mask->hdr.dst_port == UINT16_MAX)
2767 input_set |= I40E_INSET_DST_PORT;
2769 /* Get filter info */
2770 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2771 filter->input.flow.udp4_flow.src_port =
2772 udp_spec->hdr.src_port;
2773 filter->input.flow.udp4_flow.dst_port =
2774 udp_spec->hdr.dst_port;
2775 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2776 filter->input.flow.udp6_flow.src_port =
2777 udp_spec->hdr.src_port;
2778 filter->input.flow.udp6_flow.dst_port =
2779 udp_spec->hdr.dst_port;
2783 layer_idx = I40E_FLXPLD_L4_IDX;
2786 case RTE_FLOW_ITEM_TYPE_GTPC:
2787 case RTE_FLOW_ITEM_TYPE_GTPU:
2788 if (!pf->gtp_support) {
2789 rte_flow_error_set(error, EINVAL,
2790 RTE_FLOW_ERROR_TYPE_ITEM,
2792 "Unsupported protocol");
2796 gtp_spec = (const struct rte_flow_item_gtp *)item->spec;
2797 gtp_mask = (const struct rte_flow_item_gtp *)item->mask;
2799 if (gtp_spec && gtp_mask) {
2800 if (gtp_mask->v_pt_rsv_flags ||
2801 gtp_mask->msg_type ||
2802 gtp_mask->msg_len ||
2803 gtp_mask->teid != UINT32_MAX) {
2804 rte_flow_error_set(error, EINVAL,
2805 RTE_FLOW_ERROR_TYPE_ITEM,
2807 "Invalid GTP mask");
2811 filter->input.flow.gtp_flow.teid =
2813 filter->input.flow_ext.customized_pctype = true;
2814 cus_proto = item_type;
2817 case RTE_FLOW_ITEM_TYPE_SCTP:
2819 (const struct rte_flow_item_sctp *)item->spec;
2821 (const struct rte_flow_item_sctp *)item->mask;
2823 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2825 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2826 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2828 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2830 if (sctp_spec && sctp_mask) {
2831 /* Check SCTP mask and update input set */
2832 if (sctp_mask->hdr.cksum) {
2833 rte_flow_error_set(error, EINVAL,
2834 RTE_FLOW_ERROR_TYPE_ITEM,
2836 "Invalid UDP mask");
2840 if (sctp_mask->hdr.src_port == UINT16_MAX)
2841 input_set |= I40E_INSET_SRC_PORT;
2842 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2843 input_set |= I40E_INSET_DST_PORT;
2844 if (sctp_mask->hdr.tag == UINT32_MAX)
2845 input_set |= I40E_INSET_SCTP_VT;
2847 /* Get filter info */
2848 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2849 filter->input.flow.sctp4_flow.src_port =
2850 sctp_spec->hdr.src_port;
2851 filter->input.flow.sctp4_flow.dst_port =
2852 sctp_spec->hdr.dst_port;
2853 filter->input.flow.sctp4_flow.verify_tag
2854 = sctp_spec->hdr.tag;
2855 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2856 filter->input.flow.sctp6_flow.src_port =
2857 sctp_spec->hdr.src_port;
2858 filter->input.flow.sctp6_flow.dst_port =
2859 sctp_spec->hdr.dst_port;
2860 filter->input.flow.sctp6_flow.verify_tag
2861 = sctp_spec->hdr.tag;
2865 layer_idx = I40E_FLXPLD_L4_IDX;
2868 case RTE_FLOW_ITEM_TYPE_RAW:
2869 raw_spec = (const struct rte_flow_item_raw *)item->spec;
2870 raw_mask = (const struct rte_flow_item_raw *)item->mask;
2872 if (!raw_spec || !raw_mask) {
2873 rte_flow_error_set(error, EINVAL,
2874 RTE_FLOW_ERROR_TYPE_ITEM,
2876 "NULL RAW spec/mask");
2880 ret = i40e_flow_check_raw_item(item, raw_spec, error);
2884 off_arr[raw_id] = raw_spec->offset;
2885 len_arr[raw_id] = raw_spec->length;
2888 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2890 raw_spec->length / sizeof(uint16_t);
2891 flex_pit.dst_offset =
2892 next_dst_off / sizeof(uint16_t);
2894 for (i = 0; i <= raw_id; i++) {
2896 flex_pit.src_offset +=
2900 flex_pit.src_offset +=
2901 (off_arr[i] + len_arr[i]) /
2903 flex_size += len_arr[i];
2905 if (((flex_pit.src_offset + flex_pit.size) >=
2906 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2907 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2908 rte_flow_error_set(error, EINVAL,
2909 RTE_FLOW_ERROR_TYPE_ITEM,
2911 "Exceeds maxmial payload limit.");
2915 /* Store flex pit to SW */
2916 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2919 rte_flow_error_set(error, EINVAL,
2920 RTE_FLOW_ERROR_TYPE_ITEM,
2922 "Conflict with the first flexible rule.");
2925 cfg_flex_pit = false;
2927 for (i = 0; i < raw_spec->length; i++) {
2928 j = i + next_dst_off;
2929 filter->input.flow_ext.flexbytes[j] =
2930 raw_spec->pattern[i];
2931 flex_mask[j] = raw_mask->pattern[i];
2934 next_dst_off += raw_spec->length;
2937 case RTE_FLOW_ITEM_TYPE_VF:
2938 vf_spec = (const struct rte_flow_item_vf *)item->spec;
2939 filter->input.flow_ext.is_vf = 1;
2940 filter->input.flow_ext.dst_id = vf_spec->id;
2941 if (filter->input.flow_ext.is_vf &&
2942 filter->input.flow_ext.dst_id >= pf->vf_num) {
2943 rte_flow_error_set(error, EINVAL,
2944 RTE_FLOW_ERROR_TYPE_ITEM,
2946 "Invalid VF ID for FDIR.");
2955 /* Get customized pctype value */
2956 if (filter->input.flow_ext.customized_pctype) {
2957 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2958 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2959 rte_flow_error_set(error, EINVAL,
2960 RTE_FLOW_ERROR_TYPE_ITEM,
2962 "Unsupported pctype");
2967 /* If customized pctype is not used, set fdir configuration.*/
2968 if (!filter->input.flow_ext.customized_pctype) {
2969 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2971 rte_flow_error_set(error, EINVAL,
2972 RTE_FLOW_ERROR_TYPE_ITEM, item,
2973 "Conflict with the first rule's input set.");
2975 } else if (ret == -EINVAL) {
2976 rte_flow_error_set(error, EINVAL,
2977 RTE_FLOW_ERROR_TYPE_ITEM, item,
2978 "Invalid pattern mask.");
2982 /* Store flex mask to SW */
2983 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2985 rte_flow_error_set(error, EINVAL,
2986 RTE_FLOW_ERROR_TYPE_ITEM,
2988 "Exceed maximal number of bitmasks");
2990 } else if (ret == -2) {
2991 rte_flow_error_set(error, EINVAL,
2992 RTE_FLOW_ERROR_TYPE_ITEM,
2994 "Conflict with the first flexible rule");
2997 cfg_flex_msk = false;
3000 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3003 i40e_flow_set_fdir_flex_msk(pf, pctype);
3006 filter->input.pctype = pctype;
3011 /* Parse to get the action info of a FDIR filter.
3012 * FDIR action supports QUEUE or (QUEUE + MARK).
3015 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3016 const struct rte_flow_action *actions,
3017 struct rte_flow_error *error,
3018 struct i40e_fdir_filter_conf *filter)
3020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3021 const struct rte_flow_action *act;
3022 const struct rte_flow_action_queue *act_q;
3023 const struct rte_flow_action_mark *mark_spec;
3026 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3027 NEXT_ITEM_OF_ACTION(act, actions, index);
3028 switch (act->type) {
3029 case RTE_FLOW_ACTION_TYPE_QUEUE:
3030 act_q = (const struct rte_flow_action_queue *)act->conf;
3031 filter->action.rx_queue = act_q->index;
3032 if ((!filter->input.flow_ext.is_vf &&
3033 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3034 (filter->input.flow_ext.is_vf &&
3035 filter->action.rx_queue >= pf->vf_nb_qps)) {
3036 rte_flow_error_set(error, EINVAL,
3037 RTE_FLOW_ERROR_TYPE_ACTION, act,
3038 "Invalid queue ID for FDIR.");
3041 filter->action.behavior = I40E_FDIR_ACCEPT;
3043 case RTE_FLOW_ACTION_TYPE_DROP:
3044 filter->action.behavior = I40E_FDIR_REJECT;
3046 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3047 filter->action.behavior = I40E_FDIR_PASSTHRU;
3050 rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION, act,
3056 /* Check if the next non-void item is MARK or FLAG or END. */
3058 NEXT_ITEM_OF_ACTION(act, actions, index);
3059 switch (act->type) {
3060 case RTE_FLOW_ACTION_TYPE_MARK:
3061 mark_spec = (const struct rte_flow_action_mark *)act->conf;
3062 filter->action.report_status = I40E_FDIR_REPORT_ID;
3063 filter->soft_id = mark_spec->id;
3065 case RTE_FLOW_ACTION_TYPE_FLAG:
3066 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3068 case RTE_FLOW_ACTION_TYPE_END:
3071 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3072 act, "Invalid action.");
3076 /* Check if the next non-void item is END */
3078 NEXT_ITEM_OF_ACTION(act, actions, index);
3079 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3080 rte_flow_error_set(error, EINVAL,
3081 RTE_FLOW_ERROR_TYPE_ACTION,
3082 act, "Invalid action.");
3090 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3091 const struct rte_flow_attr *attr,
3092 const struct rte_flow_item pattern[],
3093 const struct rte_flow_action actions[],
3094 struct rte_flow_error *error,
3095 union i40e_filter_t *filter)
3097 struct i40e_fdir_filter_conf *fdir_filter =
3098 &filter->fdir_filter;
3101 ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3105 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3109 ret = i40e_flow_parse_attr(attr, error);
3113 cons_filter_type = RTE_ETH_FILTER_FDIR;
3115 if (dev->data->dev_conf.fdir_conf.mode !=
3116 RTE_FDIR_MODE_PERFECT) {
3117 rte_flow_error_set(error, ENOTSUP,
3118 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3120 "Check the mode in fdir_conf.");
3127 /* Parse to get the action info of a tunnel filter
3128 * Tunnel action only supports PF, VF and QUEUE.
3131 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3132 const struct rte_flow_action *actions,
3133 struct rte_flow_error *error,
3134 struct i40e_tunnel_filter_conf *filter)
3136 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3137 const struct rte_flow_action *act;
3138 const struct rte_flow_action_queue *act_q;
3139 const struct rte_flow_action_vf *act_vf;
3142 /* Check if the first non-void action is PF or VF. */
3143 NEXT_ITEM_OF_ACTION(act, actions, index);
3144 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3145 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3146 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3147 act, "Not supported action.");
3151 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3152 act_vf = (const struct rte_flow_action_vf *)act->conf;
3153 filter->vf_id = act_vf->id;
3154 filter->is_to_vf = 1;
3155 if (filter->vf_id >= pf->vf_num) {
3156 rte_flow_error_set(error, EINVAL,
3157 RTE_FLOW_ERROR_TYPE_ACTION,
3158 act, "Invalid VF ID for tunnel filter");
3163 /* Check if the next non-void item is QUEUE */
3165 NEXT_ITEM_OF_ACTION(act, actions, index);
3166 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3167 act_q = (const struct rte_flow_action_queue *)act->conf;
3168 filter->queue_id = act_q->index;
3169 if ((!filter->is_to_vf) &&
3170 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3171 rte_flow_error_set(error, EINVAL,
3172 RTE_FLOW_ERROR_TYPE_ACTION,
3173 act, "Invalid queue ID for tunnel filter");
3175 } else if (filter->is_to_vf &&
3176 (filter->queue_id >= pf->vf_nb_qps)) {
3177 rte_flow_error_set(error, EINVAL,
3178 RTE_FLOW_ERROR_TYPE_ACTION,
3179 act, "Invalid queue ID for tunnel filter");
3184 /* Check if the next non-void item is END */
3186 NEXT_ITEM_OF_ACTION(act, actions, index);
3187 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3188 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3189 act, "Not supported action.");
3196 static uint16_t i40e_supported_tunnel_filter_types[] = {
3197 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3198 ETH_TUNNEL_FILTER_IVLAN,
3199 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3200 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3201 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3202 ETH_TUNNEL_FILTER_IMAC,
3203 ETH_TUNNEL_FILTER_IMAC,
3207 i40e_check_tunnel_filter_type(uint8_t filter_type)
3211 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3212 if (filter_type == i40e_supported_tunnel_filter_types[i])
3219 /* 1. Last in item should be NULL as range is not supported.
3220 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3221 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3222 * 3. Mask of fields which need to be matched should be
3224 * 4. Mask of fields which needn't to be matched should be
3228 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3229 const struct rte_flow_item *pattern,
3230 struct rte_flow_error *error,
3231 struct i40e_tunnel_filter_conf *filter)
3233 const struct rte_flow_item *item = pattern;
3234 const struct rte_flow_item_eth *eth_spec;
3235 const struct rte_flow_item_eth *eth_mask;
3236 const struct rte_flow_item_vxlan *vxlan_spec;
3237 const struct rte_flow_item_vxlan *vxlan_mask;
3238 const struct rte_flow_item_vlan *vlan_spec;
3239 const struct rte_flow_item_vlan *vlan_mask;
3240 uint8_t filter_type = 0;
3241 bool is_vni_masked = 0;
3242 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3243 enum rte_flow_item_type item_type;
3244 bool vxlan_flag = 0;
3245 uint32_t tenant_id_be = 0;
3248 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3250 rte_flow_error_set(error, EINVAL,
3251 RTE_FLOW_ERROR_TYPE_ITEM,
3253 "Not support range");
3256 item_type = item->type;
3257 switch (item_type) {
3258 case RTE_FLOW_ITEM_TYPE_ETH:
3259 eth_spec = (const struct rte_flow_item_eth *)item->spec;
3260 eth_mask = (const struct rte_flow_item_eth *)item->mask;
3262 /* Check if ETH item is used for place holder.
3263 * If yes, both spec and mask should be NULL.
3264 * If no, both spec and mask shouldn't be NULL.
3266 if ((!eth_spec && eth_mask) ||
3267 (eth_spec && !eth_mask)) {
3268 rte_flow_error_set(error, EINVAL,
3269 RTE_FLOW_ERROR_TYPE_ITEM,
3271 "Invalid ether spec/mask");
3275 if (eth_spec && eth_mask) {
3276 /* DST address of inner MAC shouldn't be masked.
3277 * SRC address of Inner MAC should be masked.
3279 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3280 !is_zero_ether_addr(ð_mask->src) ||
3282 rte_flow_error_set(error, EINVAL,
3283 RTE_FLOW_ERROR_TYPE_ITEM,
3285 "Invalid ether spec/mask");
3290 rte_memcpy(&filter->outer_mac,
3293 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3295 rte_memcpy(&filter->inner_mac,
3298 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3302 case RTE_FLOW_ITEM_TYPE_VLAN:
3304 (const struct rte_flow_item_vlan *)item->spec;
3306 (const struct rte_flow_item_vlan *)item->mask;
3307 if (!(vlan_spec && vlan_mask)) {
3308 rte_flow_error_set(error, EINVAL,
3309 RTE_FLOW_ERROR_TYPE_ITEM,
3311 "Invalid vlan item");
3315 if (vlan_spec && vlan_mask) {
3316 if (vlan_mask->tci ==
3317 rte_cpu_to_be_16(I40E_TCI_MASK))
3318 filter->inner_vlan =
3319 rte_be_to_cpu_16(vlan_spec->tci) &
3321 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3324 case RTE_FLOW_ITEM_TYPE_IPV4:
3325 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3326 /* IPv4 is used to describe protocol,
3327 * spec and mask should be NULL.
3329 if (item->spec || item->mask) {
3330 rte_flow_error_set(error, EINVAL,
3331 RTE_FLOW_ERROR_TYPE_ITEM,
3333 "Invalid IPv4 item");
3337 case RTE_FLOW_ITEM_TYPE_IPV6:
3338 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3339 /* IPv6 is used to describe protocol,
3340 * spec and mask should be NULL.
3342 if (item->spec || item->mask) {
3343 rte_flow_error_set(error, EINVAL,
3344 RTE_FLOW_ERROR_TYPE_ITEM,
3346 "Invalid IPv6 item");
3350 case RTE_FLOW_ITEM_TYPE_UDP:
3351 /* UDP is used to describe protocol,
3352 * spec and mask should be NULL.
3354 if (item->spec || item->mask) {
3355 rte_flow_error_set(error, EINVAL,
3356 RTE_FLOW_ERROR_TYPE_ITEM,
3358 "Invalid UDP item");
3362 case RTE_FLOW_ITEM_TYPE_VXLAN:
3364 (const struct rte_flow_item_vxlan *)item->spec;
3366 (const struct rte_flow_item_vxlan *)item->mask;
3367 /* Check if VXLAN item is used to describe protocol.
3368 * If yes, both spec and mask should be NULL.
3369 * If no, both spec and mask shouldn't be NULL.
3371 if ((!vxlan_spec && vxlan_mask) ||
3372 (vxlan_spec && !vxlan_mask)) {
3373 rte_flow_error_set(error, EINVAL,
3374 RTE_FLOW_ERROR_TYPE_ITEM,
3376 "Invalid VXLAN item");
3380 /* Check if VNI is masked. */
3381 if (vxlan_spec && vxlan_mask) {
3383 !!memcmp(vxlan_mask->vni, vni_mask,
3385 if (is_vni_masked) {
3386 rte_flow_error_set(error, EINVAL,
3387 RTE_FLOW_ERROR_TYPE_ITEM,
3389 "Invalid VNI mask");
3393 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3394 vxlan_spec->vni, 3);
3396 rte_be_to_cpu_32(tenant_id_be);
3397 filter_type |= ETH_TUNNEL_FILTER_TENID;
3407 ret = i40e_check_tunnel_filter_type(filter_type);
3409 rte_flow_error_set(error, EINVAL,
3410 RTE_FLOW_ERROR_TYPE_ITEM,
3412 "Invalid filter type");
3415 filter->filter_type = filter_type;
3417 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3423 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3424 const struct rte_flow_attr *attr,
3425 const struct rte_flow_item pattern[],
3426 const struct rte_flow_action actions[],
3427 struct rte_flow_error *error,
3428 union i40e_filter_t *filter)
3430 struct i40e_tunnel_filter_conf *tunnel_filter =
3431 &filter->consistent_tunnel_filter;
3434 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3435 error, tunnel_filter);
3439 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3443 ret = i40e_flow_parse_attr(attr, error);
3447 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3452 /* 1. Last in item should be NULL as range is not supported.
3453 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3454 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3455 * 3. Mask of fields which need to be matched should be
3457 * 4. Mask of fields which needn't to be matched should be
3461 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3462 const struct rte_flow_item *pattern,
3463 struct rte_flow_error *error,
3464 struct i40e_tunnel_filter_conf *filter)
3466 const struct rte_flow_item *item = pattern;
3467 const struct rte_flow_item_eth *eth_spec;
3468 const struct rte_flow_item_eth *eth_mask;
3469 const struct rte_flow_item_nvgre *nvgre_spec;
3470 const struct rte_flow_item_nvgre *nvgre_mask;
3471 const struct rte_flow_item_vlan *vlan_spec;
3472 const struct rte_flow_item_vlan *vlan_mask;
3473 enum rte_flow_item_type item_type;
3474 uint8_t filter_type = 0;
3475 bool is_tni_masked = 0;
3476 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3477 bool nvgre_flag = 0;
3478 uint32_t tenant_id_be = 0;
3481 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3483 rte_flow_error_set(error, EINVAL,
3484 RTE_FLOW_ERROR_TYPE_ITEM,
3486 "Not support range");
3489 item_type = item->type;
3490 switch (item_type) {
3491 case RTE_FLOW_ITEM_TYPE_ETH:
3492 eth_spec = (const struct rte_flow_item_eth *)item->spec;
3493 eth_mask = (const struct rte_flow_item_eth *)item->mask;
3495 /* Check if ETH item is used for place holder.
3496 * If yes, both spec and mask should be NULL.
3497 * If no, both spec and mask shouldn't be NULL.
3499 if ((!eth_spec && eth_mask) ||
3500 (eth_spec && !eth_mask)) {
3501 rte_flow_error_set(error, EINVAL,
3502 RTE_FLOW_ERROR_TYPE_ITEM,
3504 "Invalid ether spec/mask");
3508 if (eth_spec && eth_mask) {
3509 /* DST address of inner MAC shouldn't be masked.
3510 * SRC address of Inner MAC should be masked.
3512 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3513 !is_zero_ether_addr(ð_mask->src) ||
3515 rte_flow_error_set(error, EINVAL,
3516 RTE_FLOW_ERROR_TYPE_ITEM,
3518 "Invalid ether spec/mask");
3523 rte_memcpy(&filter->outer_mac,
3526 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3528 rte_memcpy(&filter->inner_mac,
3531 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3536 case RTE_FLOW_ITEM_TYPE_VLAN:
3538 (const struct rte_flow_item_vlan *)item->spec;
3540 (const struct rte_flow_item_vlan *)item->mask;
3541 if (!(vlan_spec && vlan_mask)) {
3542 rte_flow_error_set(error, EINVAL,
3543 RTE_FLOW_ERROR_TYPE_ITEM,
3545 "Invalid vlan item");
3549 if (vlan_spec && vlan_mask) {
3550 if (vlan_mask->tci ==
3551 rte_cpu_to_be_16(I40E_TCI_MASK))
3552 filter->inner_vlan =
3553 rte_be_to_cpu_16(vlan_spec->tci) &
3555 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3558 case RTE_FLOW_ITEM_TYPE_IPV4:
3559 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3560 /* IPv4 is used to describe protocol,
3561 * spec and mask should be NULL.
3563 if (item->spec || item->mask) {
3564 rte_flow_error_set(error, EINVAL,
3565 RTE_FLOW_ERROR_TYPE_ITEM,
3567 "Invalid IPv4 item");
3571 case RTE_FLOW_ITEM_TYPE_IPV6:
3572 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3573 /* IPv6 is used to describe protocol,
3574 * spec and mask should be NULL.
3576 if (item->spec || item->mask) {
3577 rte_flow_error_set(error, EINVAL,
3578 RTE_FLOW_ERROR_TYPE_ITEM,
3580 "Invalid IPv6 item");
3584 case RTE_FLOW_ITEM_TYPE_NVGRE:
3586 (const struct rte_flow_item_nvgre *)item->spec;
3588 (const struct rte_flow_item_nvgre *)item->mask;
3589 /* Check if NVGRE item is used to describe protocol.
3590 * If yes, both spec and mask should be NULL.
3591 * If no, both spec and mask shouldn't be NULL.
3593 if ((!nvgre_spec && nvgre_mask) ||
3594 (nvgre_spec && !nvgre_mask)) {
3595 rte_flow_error_set(error, EINVAL,
3596 RTE_FLOW_ERROR_TYPE_ITEM,
3598 "Invalid NVGRE item");
3602 if (nvgre_spec && nvgre_mask) {
3604 !!memcmp(nvgre_mask->tni, tni_mask,
3606 if (is_tni_masked) {
3607 rte_flow_error_set(error, EINVAL,
3608 RTE_FLOW_ERROR_TYPE_ITEM,
3610 "Invalid TNI mask");
3613 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3614 nvgre_spec->tni, 3);
3616 rte_be_to_cpu_32(tenant_id_be);
3617 filter_type |= ETH_TUNNEL_FILTER_TENID;
3627 ret = i40e_check_tunnel_filter_type(filter_type);
3629 rte_flow_error_set(error, EINVAL,
3630 RTE_FLOW_ERROR_TYPE_ITEM,
3632 "Invalid filter type");
3635 filter->filter_type = filter_type;
3637 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3643 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3644 const struct rte_flow_attr *attr,
3645 const struct rte_flow_item pattern[],
3646 const struct rte_flow_action actions[],
3647 struct rte_flow_error *error,
3648 union i40e_filter_t *filter)
3650 struct i40e_tunnel_filter_conf *tunnel_filter =
3651 &filter->consistent_tunnel_filter;
3654 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3655 error, tunnel_filter);
3659 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3663 ret = i40e_flow_parse_attr(attr, error);
3667 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3672 /* 1. Last in item should be NULL as range is not supported.
3673 * 2. Supported filter types: MPLS label.
3674 * 3. Mask of fields which need to be matched should be
3676 * 4. Mask of fields which needn't to be matched should be
3680 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3681 const struct rte_flow_item *pattern,
3682 struct rte_flow_error *error,
3683 struct i40e_tunnel_filter_conf *filter)
3685 const struct rte_flow_item *item = pattern;
3686 const struct rte_flow_item_mpls *mpls_spec;
3687 const struct rte_flow_item_mpls *mpls_mask;
3688 enum rte_flow_item_type item_type;
3689 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3690 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3691 uint32_t label_be = 0;
3693 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3695 rte_flow_error_set(error, EINVAL,
3696 RTE_FLOW_ERROR_TYPE_ITEM,
3698 "Not support range");
3701 item_type = item->type;
3702 switch (item_type) {
3703 case RTE_FLOW_ITEM_TYPE_ETH:
3704 if (item->spec || item->mask) {
3705 rte_flow_error_set(error, EINVAL,
3706 RTE_FLOW_ERROR_TYPE_ITEM,
3708 "Invalid ETH item");
3712 case RTE_FLOW_ITEM_TYPE_IPV4:
3713 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3714 /* IPv4 is used to describe protocol,
3715 * spec and mask should be NULL.
3717 if (item->spec || item->mask) {
3718 rte_flow_error_set(error, EINVAL,
3719 RTE_FLOW_ERROR_TYPE_ITEM,
3721 "Invalid IPv4 item");
3725 case RTE_FLOW_ITEM_TYPE_IPV6:
3726 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3727 /* IPv6 is used to describe protocol,
3728 * spec and mask should be NULL.
3730 if (item->spec || item->mask) {
3731 rte_flow_error_set(error, EINVAL,
3732 RTE_FLOW_ERROR_TYPE_ITEM,
3734 "Invalid IPv6 item");
3738 case RTE_FLOW_ITEM_TYPE_UDP:
3739 /* UDP is used to describe protocol,
3740 * spec and mask should be NULL.
3742 if (item->spec || item->mask) {
3743 rte_flow_error_set(error, EINVAL,
3744 RTE_FLOW_ERROR_TYPE_ITEM,
3746 "Invalid UDP item");
3751 case RTE_FLOW_ITEM_TYPE_GRE:
3752 /* GRE is used to describe protocol,
3753 * spec and mask should be NULL.
3755 if (item->spec || item->mask) {
3756 rte_flow_error_set(error, EINVAL,
3757 RTE_FLOW_ERROR_TYPE_ITEM,
3759 "Invalid GRE item");
3763 case RTE_FLOW_ITEM_TYPE_MPLS:
3765 (const struct rte_flow_item_mpls *)item->spec;
3767 (const struct rte_flow_item_mpls *)item->mask;
3769 if (!mpls_spec || !mpls_mask) {
3770 rte_flow_error_set(error, EINVAL,
3771 RTE_FLOW_ERROR_TYPE_ITEM,
3773 "Invalid MPLS item");
3777 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3778 rte_flow_error_set(error, EINVAL,
3779 RTE_FLOW_ERROR_TYPE_ITEM,
3781 "Invalid MPLS label mask");
3784 rte_memcpy(((uint8_t *)&label_be + 1),
3785 mpls_spec->label_tc_s, 3);
3786 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3794 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3796 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3802 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3803 const struct rte_flow_attr *attr,
3804 const struct rte_flow_item pattern[],
3805 const struct rte_flow_action actions[],
3806 struct rte_flow_error *error,
3807 union i40e_filter_t *filter)
3809 struct i40e_tunnel_filter_conf *tunnel_filter =
3810 &filter->consistent_tunnel_filter;
3813 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3814 error, tunnel_filter);
3818 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3822 ret = i40e_flow_parse_attr(attr, error);
3826 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3831 /* 1. Last in item should be NULL as range is not supported.
3832 * 2. Supported filter types: GTP TEID.
3833 * 3. Mask of fields which need to be matched should be
3835 * 4. Mask of fields which needn't to be matched should be
3837 * 5. GTP profile supports GTPv1 only.
3838 * 6. GTP-C response message ('source_port' = 2123) is not supported.
3841 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3842 const struct rte_flow_item *pattern,
3843 struct rte_flow_error *error,
3844 struct i40e_tunnel_filter_conf *filter)
3846 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3847 const struct rte_flow_item *item = pattern;
3848 const struct rte_flow_item_gtp *gtp_spec;
3849 const struct rte_flow_item_gtp *gtp_mask;
3850 enum rte_flow_item_type item_type;
3852 if (!pf->gtp_support) {
3853 rte_flow_error_set(error, EINVAL,
3854 RTE_FLOW_ERROR_TYPE_ITEM,
3856 "GTP is not supported by default.");
3860 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3862 rte_flow_error_set(error, EINVAL,
3863 RTE_FLOW_ERROR_TYPE_ITEM,
3865 "Not support range");
3868 item_type = item->type;
3869 switch (item_type) {
3870 case RTE_FLOW_ITEM_TYPE_ETH:
3871 if (item->spec || item->mask) {
3872 rte_flow_error_set(error, EINVAL,
3873 RTE_FLOW_ERROR_TYPE_ITEM,
3875 "Invalid ETH item");
3879 case RTE_FLOW_ITEM_TYPE_IPV4:
3880 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3881 /* IPv4 is used to describe protocol,
3882 * spec and mask should be NULL.
3884 if (item->spec || item->mask) {
3885 rte_flow_error_set(error, EINVAL,
3886 RTE_FLOW_ERROR_TYPE_ITEM,
3888 "Invalid IPv4 item");
3892 case RTE_FLOW_ITEM_TYPE_UDP:
3893 if (item->spec || item->mask) {
3894 rte_flow_error_set(error, EINVAL,
3895 RTE_FLOW_ERROR_TYPE_ITEM,
3897 "Invalid UDP item");
3901 case RTE_FLOW_ITEM_TYPE_GTPC:
3902 case RTE_FLOW_ITEM_TYPE_GTPU:
3904 (const struct rte_flow_item_gtp *)item->spec;
3906 (const struct rte_flow_item_gtp *)item->mask;
3908 if (!gtp_spec || !gtp_mask) {
3909 rte_flow_error_set(error, EINVAL,
3910 RTE_FLOW_ERROR_TYPE_ITEM,
3912 "Invalid GTP item");
3916 if (gtp_mask->v_pt_rsv_flags ||
3917 gtp_mask->msg_type ||
3918 gtp_mask->msg_len ||
3919 gtp_mask->teid != UINT32_MAX) {
3920 rte_flow_error_set(error, EINVAL,
3921 RTE_FLOW_ERROR_TYPE_ITEM,
3923 "Invalid GTP mask");
3927 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3928 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3929 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3930 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3932 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3944 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3945 const struct rte_flow_attr *attr,
3946 const struct rte_flow_item pattern[],
3947 const struct rte_flow_action actions[],
3948 struct rte_flow_error *error,
3949 union i40e_filter_t *filter)
3951 struct i40e_tunnel_filter_conf *tunnel_filter =
3952 &filter->consistent_tunnel_filter;
3955 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3956 error, tunnel_filter);
3960 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3964 ret = i40e_flow_parse_attr(attr, error);
3968 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3973 /* 1. Last in item should be NULL as range is not supported.
3974 * 2. Supported filter types: QINQ.
3975 * 3. Mask of fields which need to be matched should be
3977 * 4. Mask of fields which needn't to be matched should be
3981 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3982 const struct rte_flow_item *pattern,
3983 struct rte_flow_error *error,
3984 struct i40e_tunnel_filter_conf *filter)
3986 const struct rte_flow_item *item = pattern;
3987 const struct rte_flow_item_vlan *vlan_spec = NULL;
3988 const struct rte_flow_item_vlan *vlan_mask = NULL;
3989 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3990 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3991 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3992 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3994 enum rte_flow_item_type item_type;
3997 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3999 rte_flow_error_set(error, EINVAL,
4000 RTE_FLOW_ERROR_TYPE_ITEM,
4002 "Not support range");
4005 item_type = item->type;
4006 switch (item_type) {
4007 case RTE_FLOW_ITEM_TYPE_ETH:
4008 if (item->spec || item->mask) {
4009 rte_flow_error_set(error, EINVAL,
4010 RTE_FLOW_ERROR_TYPE_ITEM,
4012 "Invalid ETH item");
4016 case RTE_FLOW_ITEM_TYPE_VLAN:
4018 (const struct rte_flow_item_vlan *)item->spec;
4020 (const struct rte_flow_item_vlan *)item->mask;
4022 if (!(vlan_spec && vlan_mask)) {
4023 rte_flow_error_set(error, EINVAL,
4024 RTE_FLOW_ERROR_TYPE_ITEM,
4026 "Invalid vlan item");
4031 o_vlan_spec = vlan_spec;
4032 o_vlan_mask = vlan_mask;
4035 i_vlan_spec = vlan_spec;
4036 i_vlan_mask = vlan_mask;
4046 /* Get filter specification */
4047 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4048 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4049 (i_vlan_mask != NULL) &&
4050 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4051 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4053 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4056 rte_flow_error_set(error, EINVAL,
4057 RTE_FLOW_ERROR_TYPE_ITEM,
4059 "Invalid filter type");
4063 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4068 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4069 const struct rte_flow_attr *attr,
4070 const struct rte_flow_item pattern[],
4071 const struct rte_flow_action actions[],
4072 struct rte_flow_error *error,
4073 union i40e_filter_t *filter)
4075 struct i40e_tunnel_filter_conf *tunnel_filter =
4076 &filter->consistent_tunnel_filter;
4079 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4080 error, tunnel_filter);
4084 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4088 ret = i40e_flow_parse_attr(attr, error);
4092 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4098 i40e_flow_validate(struct rte_eth_dev *dev,
4099 const struct rte_flow_attr *attr,
4100 const struct rte_flow_item pattern[],
4101 const struct rte_flow_action actions[],
4102 struct rte_flow_error *error)
4104 struct rte_flow_item *items; /* internal pattern w/o VOID items */
4105 parse_filter_t parse_filter;
4106 uint32_t item_num = 0; /* non-void item number of pattern*/
4109 int ret = I40E_NOT_SUPPORTED;
4112 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4113 NULL, "NULL pattern.");
4118 rte_flow_error_set(error, EINVAL,
4119 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4120 NULL, "NULL action.");
4125 rte_flow_error_set(error, EINVAL,
4126 RTE_FLOW_ERROR_TYPE_ATTR,
4127 NULL, "NULL attribute.");
4131 memset(&cons_filter, 0, sizeof(cons_filter));
4133 /* Get the non-void item number of pattern */
4134 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4135 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4141 items = rte_zmalloc("i40e_pattern",
4142 item_num * sizeof(struct rte_flow_item), 0);
4144 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4145 NULL, "No memory for PMD internal items.");
4149 i40e_pattern_skip_void_item(items, pattern);
4153 parse_filter = i40e_find_parse_filter_func(items, &i);
4154 if (!parse_filter && !flag) {
4155 rte_flow_error_set(error, EINVAL,
4156 RTE_FLOW_ERROR_TYPE_ITEM,
4157 pattern, "Unsupported pattern");
4162 ret = parse_filter(dev, attr, items, actions,
4163 error, &cons_filter);
4165 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4172 static struct rte_flow *
4173 i40e_flow_create(struct rte_eth_dev *dev,
4174 const struct rte_flow_attr *attr,
4175 const struct rte_flow_item pattern[],
4176 const struct rte_flow_action actions[],
4177 struct rte_flow_error *error)
4179 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4180 struct rte_flow *flow;
4183 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4185 rte_flow_error_set(error, ENOMEM,
4186 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4187 "Failed to allocate memory");
4191 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4195 switch (cons_filter_type) {
4196 case RTE_ETH_FILTER_ETHERTYPE:
4197 ret = i40e_ethertype_filter_set(pf,
4198 &cons_filter.ethertype_filter, 1);
4201 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4202 i40e_ethertype_filter_list);
4204 case RTE_ETH_FILTER_FDIR:
4205 ret = i40e_flow_add_del_fdir_filter(dev,
4206 &cons_filter.fdir_filter, 1);
4209 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4210 i40e_fdir_filter_list);
4212 case RTE_ETH_FILTER_TUNNEL:
4213 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4214 &cons_filter.consistent_tunnel_filter, 1);
4217 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4218 i40e_tunnel_filter_list);
4224 flow->filter_type = cons_filter_type;
4225 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4229 rte_flow_error_set(error, -ret,
4230 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4231 "Failed to create flow.");
4237 i40e_flow_destroy(struct rte_eth_dev *dev,
4238 struct rte_flow *flow,
4239 struct rte_flow_error *error)
4241 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4242 enum rte_filter_type filter_type = flow->filter_type;
4245 switch (filter_type) {
4246 case RTE_ETH_FILTER_ETHERTYPE:
4247 ret = i40e_flow_destroy_ethertype_filter(pf,
4248 (struct i40e_ethertype_filter *)flow->rule);
4250 case RTE_ETH_FILTER_TUNNEL:
4251 ret = i40e_flow_destroy_tunnel_filter(pf,
4252 (struct i40e_tunnel_filter *)flow->rule);
4254 case RTE_ETH_FILTER_FDIR:
4255 ret = i40e_flow_add_del_fdir_filter(dev,
4256 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4259 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4266 TAILQ_REMOVE(&pf->flow_list, flow, node);
4269 rte_flow_error_set(error, -ret,
4270 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4271 "Failed to destroy flow.");
4277 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4278 struct i40e_ethertype_filter *filter)
4280 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4281 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4282 struct i40e_ethertype_filter *node;
4283 struct i40e_control_filter_stats stats;
4287 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4288 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4289 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4290 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4291 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4293 memset(&stats, 0, sizeof(stats));
4294 ret = i40e_aq_add_rem_control_packet_filter(hw,
4295 filter->input.mac_addr.addr_bytes,
4296 filter->input.ether_type,
4297 flags, pf->main_vsi->seid,
4298 filter->queue, 0, &stats, NULL);
4302 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4306 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4312 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4313 struct i40e_tunnel_filter *filter)
4315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4316 struct i40e_vsi *vsi;
4317 struct i40e_pf_vf *vf;
4318 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4319 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4320 struct i40e_tunnel_filter *node;
4321 bool big_buffer = 0;
4324 memset(&cld_filter, 0, sizeof(cld_filter));
4325 ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4326 (struct ether_addr *)&cld_filter.element.outer_mac);
4327 ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4328 (struct ether_addr *)&cld_filter.element.inner_mac);
4329 cld_filter.element.inner_vlan = filter->input.inner_vlan;
4330 cld_filter.element.flags = filter->input.flags;
4331 cld_filter.element.tenant_id = filter->input.tenant_id;
4332 cld_filter.element.queue_number = filter->queue;
4333 rte_memcpy(cld_filter.general_fields,
4334 filter->input.general_fields,
4335 sizeof(cld_filter.general_fields));
4337 if (!filter->is_to_vf)
4340 vf = &pf->vfs[filter->vf_id];
4344 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4345 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4346 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4347 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4348 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4349 I40E_AQC_ADD_CLOUD_FILTER_0X10))
4353 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4356 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4357 &cld_filter.element, 1);
4361 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4365 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4371 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4376 ret = i40e_flow_flush_fdir_filter(pf);
4378 rte_flow_error_set(error, -ret,
4379 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4380 "Failed to flush FDIR flows.");
4384 ret = i40e_flow_flush_ethertype_filter(pf);
4386 rte_flow_error_set(error, -ret,
4387 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4388 "Failed to ethertype flush flows.");
4392 ret = i40e_flow_flush_tunnel_filter(pf);
4394 rte_flow_error_set(error, -ret,
4395 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4396 "Failed to flush tunnel flows.");
4404 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4406 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4407 struct i40e_fdir_info *fdir_info = &pf->fdir;
4408 struct i40e_fdir_filter *fdir_filter;
4409 struct rte_flow *flow;
4413 ret = i40e_fdir_flush(dev);
4415 /* Delete FDIR filters in FDIR list. */
4416 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4417 ret = i40e_sw_fdir_filter_del(pf,
4418 &fdir_filter->fdir.input);
4423 /* Delete FDIR flows in flow list. */
4424 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4425 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4426 TAILQ_REMOVE(&pf->flow_list, flow, node);
4435 /* Flush all ethertype filters */
4437 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4439 struct i40e_ethertype_filter_list
4440 *ethertype_list = &pf->ethertype.ethertype_list;
4441 struct i40e_ethertype_filter *filter;
4442 struct rte_flow *flow;
4446 while ((filter = TAILQ_FIRST(ethertype_list))) {
4447 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4452 /* Delete ethertype flows in flow list. */
4453 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4454 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4455 TAILQ_REMOVE(&pf->flow_list, flow, node);
4463 /* Flush all tunnel filters */
4465 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4467 struct i40e_tunnel_filter_list
4468 *tunnel_list = &pf->tunnel.tunnel_list;
4469 struct i40e_tunnel_filter *filter;
4470 struct rte_flow *flow;
4474 while ((filter = TAILQ_FIRST(tunnel_list))) {
4475 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4480 /* Delete tunnel flows in flow list. */
4481 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4482 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4483 TAILQ_REMOVE(&pf->flow_list, flow, node);