1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_eth_ctrl.h>
18 #include <rte_tailq.h>
19 #include <rte_flow_driver.h>
21 #include "i40e_logs.h"
22 #include "base/i40e_type.h"
23 #include "base/i40e_prototype.h"
24 #include "i40e_ethdev.h"
26 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
27 #define I40E_IPV6_FRAG_HEADER 44
28 #define I40E_TENANT_ARRAY_NUM 3
29 #define I40E_TCI_MASK 0xFFFF
31 static int i40e_flow_validate(struct rte_eth_dev *dev,
32 const struct rte_flow_attr *attr,
33 const struct rte_flow_item pattern[],
34 const struct rte_flow_action actions[],
35 struct rte_flow_error *error);
36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
37 const struct rte_flow_attr *attr,
38 const struct rte_flow_item pattern[],
39 const struct rte_flow_action actions[],
40 struct rte_flow_error *error);
41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
42 struct rte_flow *flow,
43 struct rte_flow_error *error);
44 static int i40e_flow_flush(struct rte_eth_dev *dev,
45 struct rte_flow_error *error);
47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
48 const struct rte_flow_item *pattern,
49 struct rte_flow_error *error,
50 struct rte_eth_ethertype_filter *filter);
51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
52 const struct rte_flow_action *actions,
53 struct rte_flow_error *error,
54 struct rte_eth_ethertype_filter *filter);
55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
56 const struct rte_flow_item *pattern,
57 struct rte_flow_error *error,
58 struct i40e_fdir_filter_conf *filter);
59 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
60 const struct rte_flow_action *actions,
61 struct rte_flow_error *error,
62 struct i40e_fdir_filter_conf *filter);
63 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
64 const struct rte_flow_action *actions,
65 struct rte_flow_error *error,
66 struct i40e_tunnel_filter_conf *filter);
67 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
68 struct rte_flow_error *error);
69 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
70 const struct rte_flow_attr *attr,
71 const struct rte_flow_item pattern[],
72 const struct rte_flow_action actions[],
73 struct rte_flow_error *error,
74 union i40e_filter_t *filter);
75 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
76 const struct rte_flow_attr *attr,
77 const struct rte_flow_item pattern[],
78 const struct rte_flow_action actions[],
79 struct rte_flow_error *error,
80 union i40e_filter_t *filter);
81 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
82 const struct rte_flow_attr *attr,
83 const struct rte_flow_item pattern[],
84 const struct rte_flow_action actions[],
85 struct rte_flow_error *error,
86 union i40e_filter_t *filter);
87 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
88 const struct rte_flow_attr *attr,
89 const struct rte_flow_item pattern[],
90 const struct rte_flow_action actions[],
91 struct rte_flow_error *error,
92 union i40e_filter_t *filter);
93 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
94 const struct rte_flow_attr *attr,
95 const struct rte_flow_item pattern[],
96 const struct rte_flow_action actions[],
97 struct rte_flow_error *error,
98 union i40e_filter_t *filter);
99 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
100 const struct rte_flow_attr *attr,
101 const struct rte_flow_item pattern[],
102 const struct rte_flow_action actions[],
103 struct rte_flow_error *error,
104 union i40e_filter_t *filter);
105 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
106 struct i40e_ethertype_filter *filter);
107 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
108 struct i40e_tunnel_filter *filter);
109 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
110 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
111 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
113 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
116 const struct rte_flow_attr *attr,
117 const struct rte_flow_item pattern[],
118 const struct rte_flow_action actions[],
119 struct rte_flow_error *error,
120 union i40e_filter_t *filter);
122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
123 const struct rte_flow_item *pattern,
124 struct rte_flow_error *error,
125 struct i40e_tunnel_filter_conf *filter);
127 const struct rte_flow_ops i40e_flow_ops = {
128 .validate = i40e_flow_validate,
129 .create = i40e_flow_create,
130 .destroy = i40e_flow_destroy,
131 .flush = i40e_flow_flush,
134 union i40e_filter_t cons_filter;
135 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
137 /* Pattern matched ethertype filter */
138 static enum rte_flow_item_type pattern_ethertype[] = {
139 RTE_FLOW_ITEM_TYPE_ETH,
140 RTE_FLOW_ITEM_TYPE_END,
143 /* Pattern matched flow director filter */
144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
145 RTE_FLOW_ITEM_TYPE_ETH,
146 RTE_FLOW_ITEM_TYPE_IPV4,
147 RTE_FLOW_ITEM_TYPE_END,
150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
151 RTE_FLOW_ITEM_TYPE_ETH,
152 RTE_FLOW_ITEM_TYPE_IPV4,
153 RTE_FLOW_ITEM_TYPE_UDP,
154 RTE_FLOW_ITEM_TYPE_END,
157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
158 RTE_FLOW_ITEM_TYPE_ETH,
159 RTE_FLOW_ITEM_TYPE_IPV4,
160 RTE_FLOW_ITEM_TYPE_TCP,
161 RTE_FLOW_ITEM_TYPE_END,
164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
165 RTE_FLOW_ITEM_TYPE_ETH,
166 RTE_FLOW_ITEM_TYPE_IPV4,
167 RTE_FLOW_ITEM_TYPE_SCTP,
168 RTE_FLOW_ITEM_TYPE_END,
171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
172 RTE_FLOW_ITEM_TYPE_ETH,
173 RTE_FLOW_ITEM_TYPE_IPV4,
174 RTE_FLOW_ITEM_TYPE_UDP,
175 RTE_FLOW_ITEM_TYPE_GTPC,
176 RTE_FLOW_ITEM_TYPE_END,
179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
180 RTE_FLOW_ITEM_TYPE_ETH,
181 RTE_FLOW_ITEM_TYPE_IPV4,
182 RTE_FLOW_ITEM_TYPE_UDP,
183 RTE_FLOW_ITEM_TYPE_GTPU,
184 RTE_FLOW_ITEM_TYPE_END,
187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
188 RTE_FLOW_ITEM_TYPE_ETH,
189 RTE_FLOW_ITEM_TYPE_IPV4,
190 RTE_FLOW_ITEM_TYPE_UDP,
191 RTE_FLOW_ITEM_TYPE_GTPU,
192 RTE_FLOW_ITEM_TYPE_IPV4,
193 RTE_FLOW_ITEM_TYPE_END,
196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
197 RTE_FLOW_ITEM_TYPE_ETH,
198 RTE_FLOW_ITEM_TYPE_IPV4,
199 RTE_FLOW_ITEM_TYPE_UDP,
200 RTE_FLOW_ITEM_TYPE_GTPU,
201 RTE_FLOW_ITEM_TYPE_IPV6,
202 RTE_FLOW_ITEM_TYPE_END,
205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
206 RTE_FLOW_ITEM_TYPE_ETH,
207 RTE_FLOW_ITEM_TYPE_IPV6,
208 RTE_FLOW_ITEM_TYPE_END,
211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
212 RTE_FLOW_ITEM_TYPE_ETH,
213 RTE_FLOW_ITEM_TYPE_IPV6,
214 RTE_FLOW_ITEM_TYPE_UDP,
215 RTE_FLOW_ITEM_TYPE_END,
218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
219 RTE_FLOW_ITEM_TYPE_ETH,
220 RTE_FLOW_ITEM_TYPE_IPV6,
221 RTE_FLOW_ITEM_TYPE_TCP,
222 RTE_FLOW_ITEM_TYPE_END,
225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
226 RTE_FLOW_ITEM_TYPE_ETH,
227 RTE_FLOW_ITEM_TYPE_IPV6,
228 RTE_FLOW_ITEM_TYPE_SCTP,
229 RTE_FLOW_ITEM_TYPE_END,
232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
233 RTE_FLOW_ITEM_TYPE_ETH,
234 RTE_FLOW_ITEM_TYPE_IPV6,
235 RTE_FLOW_ITEM_TYPE_UDP,
236 RTE_FLOW_ITEM_TYPE_GTPC,
237 RTE_FLOW_ITEM_TYPE_END,
240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
241 RTE_FLOW_ITEM_TYPE_ETH,
242 RTE_FLOW_ITEM_TYPE_IPV6,
243 RTE_FLOW_ITEM_TYPE_UDP,
244 RTE_FLOW_ITEM_TYPE_GTPU,
245 RTE_FLOW_ITEM_TYPE_END,
248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
249 RTE_FLOW_ITEM_TYPE_ETH,
250 RTE_FLOW_ITEM_TYPE_IPV6,
251 RTE_FLOW_ITEM_TYPE_UDP,
252 RTE_FLOW_ITEM_TYPE_GTPU,
253 RTE_FLOW_ITEM_TYPE_IPV4,
254 RTE_FLOW_ITEM_TYPE_END,
257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
258 RTE_FLOW_ITEM_TYPE_ETH,
259 RTE_FLOW_ITEM_TYPE_IPV6,
260 RTE_FLOW_ITEM_TYPE_UDP,
261 RTE_FLOW_ITEM_TYPE_GTPU,
262 RTE_FLOW_ITEM_TYPE_IPV6,
263 RTE_FLOW_ITEM_TYPE_END,
266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
267 RTE_FLOW_ITEM_TYPE_ETH,
268 RTE_FLOW_ITEM_TYPE_RAW,
269 RTE_FLOW_ITEM_TYPE_END,
272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
273 RTE_FLOW_ITEM_TYPE_ETH,
274 RTE_FLOW_ITEM_TYPE_RAW,
275 RTE_FLOW_ITEM_TYPE_RAW,
276 RTE_FLOW_ITEM_TYPE_END,
279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
280 RTE_FLOW_ITEM_TYPE_ETH,
281 RTE_FLOW_ITEM_TYPE_RAW,
282 RTE_FLOW_ITEM_TYPE_RAW,
283 RTE_FLOW_ITEM_TYPE_RAW,
284 RTE_FLOW_ITEM_TYPE_END,
287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
288 RTE_FLOW_ITEM_TYPE_ETH,
289 RTE_FLOW_ITEM_TYPE_IPV4,
290 RTE_FLOW_ITEM_TYPE_RAW,
291 RTE_FLOW_ITEM_TYPE_END,
294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
295 RTE_FLOW_ITEM_TYPE_ETH,
296 RTE_FLOW_ITEM_TYPE_IPV4,
297 RTE_FLOW_ITEM_TYPE_RAW,
298 RTE_FLOW_ITEM_TYPE_RAW,
299 RTE_FLOW_ITEM_TYPE_END,
302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
303 RTE_FLOW_ITEM_TYPE_ETH,
304 RTE_FLOW_ITEM_TYPE_IPV4,
305 RTE_FLOW_ITEM_TYPE_RAW,
306 RTE_FLOW_ITEM_TYPE_RAW,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_END,
311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
312 RTE_FLOW_ITEM_TYPE_ETH,
313 RTE_FLOW_ITEM_TYPE_IPV4,
314 RTE_FLOW_ITEM_TYPE_UDP,
315 RTE_FLOW_ITEM_TYPE_RAW,
316 RTE_FLOW_ITEM_TYPE_END,
319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
320 RTE_FLOW_ITEM_TYPE_ETH,
321 RTE_FLOW_ITEM_TYPE_IPV4,
322 RTE_FLOW_ITEM_TYPE_UDP,
323 RTE_FLOW_ITEM_TYPE_RAW,
324 RTE_FLOW_ITEM_TYPE_RAW,
325 RTE_FLOW_ITEM_TYPE_END,
328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
329 RTE_FLOW_ITEM_TYPE_ETH,
330 RTE_FLOW_ITEM_TYPE_IPV4,
331 RTE_FLOW_ITEM_TYPE_UDP,
332 RTE_FLOW_ITEM_TYPE_RAW,
333 RTE_FLOW_ITEM_TYPE_RAW,
334 RTE_FLOW_ITEM_TYPE_RAW,
335 RTE_FLOW_ITEM_TYPE_END,
338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
339 RTE_FLOW_ITEM_TYPE_ETH,
340 RTE_FLOW_ITEM_TYPE_IPV4,
341 RTE_FLOW_ITEM_TYPE_TCP,
342 RTE_FLOW_ITEM_TYPE_RAW,
343 RTE_FLOW_ITEM_TYPE_END,
346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
347 RTE_FLOW_ITEM_TYPE_ETH,
348 RTE_FLOW_ITEM_TYPE_IPV4,
349 RTE_FLOW_ITEM_TYPE_TCP,
350 RTE_FLOW_ITEM_TYPE_RAW,
351 RTE_FLOW_ITEM_TYPE_RAW,
352 RTE_FLOW_ITEM_TYPE_END,
355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
356 RTE_FLOW_ITEM_TYPE_ETH,
357 RTE_FLOW_ITEM_TYPE_IPV4,
358 RTE_FLOW_ITEM_TYPE_TCP,
359 RTE_FLOW_ITEM_TYPE_RAW,
360 RTE_FLOW_ITEM_TYPE_RAW,
361 RTE_FLOW_ITEM_TYPE_RAW,
362 RTE_FLOW_ITEM_TYPE_END,
365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
366 RTE_FLOW_ITEM_TYPE_ETH,
367 RTE_FLOW_ITEM_TYPE_IPV4,
368 RTE_FLOW_ITEM_TYPE_SCTP,
369 RTE_FLOW_ITEM_TYPE_RAW,
370 RTE_FLOW_ITEM_TYPE_END,
373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
374 RTE_FLOW_ITEM_TYPE_ETH,
375 RTE_FLOW_ITEM_TYPE_IPV4,
376 RTE_FLOW_ITEM_TYPE_SCTP,
377 RTE_FLOW_ITEM_TYPE_RAW,
378 RTE_FLOW_ITEM_TYPE_RAW,
379 RTE_FLOW_ITEM_TYPE_END,
382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
383 RTE_FLOW_ITEM_TYPE_ETH,
384 RTE_FLOW_ITEM_TYPE_IPV4,
385 RTE_FLOW_ITEM_TYPE_SCTP,
386 RTE_FLOW_ITEM_TYPE_RAW,
387 RTE_FLOW_ITEM_TYPE_RAW,
388 RTE_FLOW_ITEM_TYPE_RAW,
389 RTE_FLOW_ITEM_TYPE_END,
392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
393 RTE_FLOW_ITEM_TYPE_ETH,
394 RTE_FLOW_ITEM_TYPE_IPV6,
395 RTE_FLOW_ITEM_TYPE_RAW,
396 RTE_FLOW_ITEM_TYPE_END,
399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
400 RTE_FLOW_ITEM_TYPE_ETH,
401 RTE_FLOW_ITEM_TYPE_IPV6,
402 RTE_FLOW_ITEM_TYPE_RAW,
403 RTE_FLOW_ITEM_TYPE_RAW,
404 RTE_FLOW_ITEM_TYPE_END,
407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
408 RTE_FLOW_ITEM_TYPE_ETH,
409 RTE_FLOW_ITEM_TYPE_IPV6,
410 RTE_FLOW_ITEM_TYPE_RAW,
411 RTE_FLOW_ITEM_TYPE_RAW,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_END,
416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
417 RTE_FLOW_ITEM_TYPE_ETH,
418 RTE_FLOW_ITEM_TYPE_IPV6,
419 RTE_FLOW_ITEM_TYPE_UDP,
420 RTE_FLOW_ITEM_TYPE_RAW,
421 RTE_FLOW_ITEM_TYPE_END,
424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
425 RTE_FLOW_ITEM_TYPE_ETH,
426 RTE_FLOW_ITEM_TYPE_IPV6,
427 RTE_FLOW_ITEM_TYPE_UDP,
428 RTE_FLOW_ITEM_TYPE_RAW,
429 RTE_FLOW_ITEM_TYPE_RAW,
430 RTE_FLOW_ITEM_TYPE_END,
433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
434 RTE_FLOW_ITEM_TYPE_ETH,
435 RTE_FLOW_ITEM_TYPE_IPV6,
436 RTE_FLOW_ITEM_TYPE_UDP,
437 RTE_FLOW_ITEM_TYPE_RAW,
438 RTE_FLOW_ITEM_TYPE_RAW,
439 RTE_FLOW_ITEM_TYPE_RAW,
440 RTE_FLOW_ITEM_TYPE_END,
443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
444 RTE_FLOW_ITEM_TYPE_ETH,
445 RTE_FLOW_ITEM_TYPE_IPV6,
446 RTE_FLOW_ITEM_TYPE_TCP,
447 RTE_FLOW_ITEM_TYPE_RAW,
448 RTE_FLOW_ITEM_TYPE_END,
451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
452 RTE_FLOW_ITEM_TYPE_ETH,
453 RTE_FLOW_ITEM_TYPE_IPV6,
454 RTE_FLOW_ITEM_TYPE_TCP,
455 RTE_FLOW_ITEM_TYPE_RAW,
456 RTE_FLOW_ITEM_TYPE_RAW,
457 RTE_FLOW_ITEM_TYPE_END,
460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
461 RTE_FLOW_ITEM_TYPE_ETH,
462 RTE_FLOW_ITEM_TYPE_IPV6,
463 RTE_FLOW_ITEM_TYPE_TCP,
464 RTE_FLOW_ITEM_TYPE_RAW,
465 RTE_FLOW_ITEM_TYPE_RAW,
466 RTE_FLOW_ITEM_TYPE_RAW,
467 RTE_FLOW_ITEM_TYPE_END,
470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
471 RTE_FLOW_ITEM_TYPE_ETH,
472 RTE_FLOW_ITEM_TYPE_IPV6,
473 RTE_FLOW_ITEM_TYPE_SCTP,
474 RTE_FLOW_ITEM_TYPE_RAW,
475 RTE_FLOW_ITEM_TYPE_END,
478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
479 RTE_FLOW_ITEM_TYPE_ETH,
480 RTE_FLOW_ITEM_TYPE_IPV6,
481 RTE_FLOW_ITEM_TYPE_SCTP,
482 RTE_FLOW_ITEM_TYPE_RAW,
483 RTE_FLOW_ITEM_TYPE_RAW,
484 RTE_FLOW_ITEM_TYPE_END,
487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
488 RTE_FLOW_ITEM_TYPE_ETH,
489 RTE_FLOW_ITEM_TYPE_IPV6,
490 RTE_FLOW_ITEM_TYPE_SCTP,
491 RTE_FLOW_ITEM_TYPE_RAW,
492 RTE_FLOW_ITEM_TYPE_RAW,
493 RTE_FLOW_ITEM_TYPE_RAW,
494 RTE_FLOW_ITEM_TYPE_END,
497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
498 RTE_FLOW_ITEM_TYPE_ETH,
499 RTE_FLOW_ITEM_TYPE_VLAN,
500 RTE_FLOW_ITEM_TYPE_END,
503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
504 RTE_FLOW_ITEM_TYPE_ETH,
505 RTE_FLOW_ITEM_TYPE_VLAN,
506 RTE_FLOW_ITEM_TYPE_IPV4,
507 RTE_FLOW_ITEM_TYPE_END,
510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
511 RTE_FLOW_ITEM_TYPE_ETH,
512 RTE_FLOW_ITEM_TYPE_VLAN,
513 RTE_FLOW_ITEM_TYPE_IPV4,
514 RTE_FLOW_ITEM_TYPE_UDP,
515 RTE_FLOW_ITEM_TYPE_END,
518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
519 RTE_FLOW_ITEM_TYPE_ETH,
520 RTE_FLOW_ITEM_TYPE_VLAN,
521 RTE_FLOW_ITEM_TYPE_IPV4,
522 RTE_FLOW_ITEM_TYPE_TCP,
523 RTE_FLOW_ITEM_TYPE_END,
526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
527 RTE_FLOW_ITEM_TYPE_ETH,
528 RTE_FLOW_ITEM_TYPE_VLAN,
529 RTE_FLOW_ITEM_TYPE_IPV4,
530 RTE_FLOW_ITEM_TYPE_SCTP,
531 RTE_FLOW_ITEM_TYPE_END,
534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
535 RTE_FLOW_ITEM_TYPE_ETH,
536 RTE_FLOW_ITEM_TYPE_VLAN,
537 RTE_FLOW_ITEM_TYPE_IPV6,
538 RTE_FLOW_ITEM_TYPE_END,
541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
542 RTE_FLOW_ITEM_TYPE_ETH,
543 RTE_FLOW_ITEM_TYPE_VLAN,
544 RTE_FLOW_ITEM_TYPE_IPV6,
545 RTE_FLOW_ITEM_TYPE_UDP,
546 RTE_FLOW_ITEM_TYPE_END,
549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
550 RTE_FLOW_ITEM_TYPE_ETH,
551 RTE_FLOW_ITEM_TYPE_VLAN,
552 RTE_FLOW_ITEM_TYPE_IPV6,
553 RTE_FLOW_ITEM_TYPE_TCP,
554 RTE_FLOW_ITEM_TYPE_END,
557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
558 RTE_FLOW_ITEM_TYPE_ETH,
559 RTE_FLOW_ITEM_TYPE_VLAN,
560 RTE_FLOW_ITEM_TYPE_IPV6,
561 RTE_FLOW_ITEM_TYPE_SCTP,
562 RTE_FLOW_ITEM_TYPE_END,
565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
566 RTE_FLOW_ITEM_TYPE_ETH,
567 RTE_FLOW_ITEM_TYPE_VLAN,
568 RTE_FLOW_ITEM_TYPE_RAW,
569 RTE_FLOW_ITEM_TYPE_END,
572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
573 RTE_FLOW_ITEM_TYPE_ETH,
574 RTE_FLOW_ITEM_TYPE_VLAN,
575 RTE_FLOW_ITEM_TYPE_RAW,
576 RTE_FLOW_ITEM_TYPE_RAW,
577 RTE_FLOW_ITEM_TYPE_END,
580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
581 RTE_FLOW_ITEM_TYPE_ETH,
582 RTE_FLOW_ITEM_TYPE_VLAN,
583 RTE_FLOW_ITEM_TYPE_RAW,
584 RTE_FLOW_ITEM_TYPE_RAW,
585 RTE_FLOW_ITEM_TYPE_RAW,
586 RTE_FLOW_ITEM_TYPE_END,
589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
590 RTE_FLOW_ITEM_TYPE_ETH,
591 RTE_FLOW_ITEM_TYPE_VLAN,
592 RTE_FLOW_ITEM_TYPE_IPV4,
593 RTE_FLOW_ITEM_TYPE_RAW,
594 RTE_FLOW_ITEM_TYPE_END,
597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
598 RTE_FLOW_ITEM_TYPE_ETH,
599 RTE_FLOW_ITEM_TYPE_VLAN,
600 RTE_FLOW_ITEM_TYPE_IPV4,
601 RTE_FLOW_ITEM_TYPE_RAW,
602 RTE_FLOW_ITEM_TYPE_RAW,
603 RTE_FLOW_ITEM_TYPE_END,
606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
607 RTE_FLOW_ITEM_TYPE_ETH,
608 RTE_FLOW_ITEM_TYPE_VLAN,
609 RTE_FLOW_ITEM_TYPE_IPV4,
610 RTE_FLOW_ITEM_TYPE_RAW,
611 RTE_FLOW_ITEM_TYPE_RAW,
612 RTE_FLOW_ITEM_TYPE_RAW,
613 RTE_FLOW_ITEM_TYPE_END,
616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
617 RTE_FLOW_ITEM_TYPE_ETH,
618 RTE_FLOW_ITEM_TYPE_VLAN,
619 RTE_FLOW_ITEM_TYPE_IPV4,
620 RTE_FLOW_ITEM_TYPE_UDP,
621 RTE_FLOW_ITEM_TYPE_RAW,
622 RTE_FLOW_ITEM_TYPE_END,
625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
626 RTE_FLOW_ITEM_TYPE_ETH,
627 RTE_FLOW_ITEM_TYPE_VLAN,
628 RTE_FLOW_ITEM_TYPE_IPV4,
629 RTE_FLOW_ITEM_TYPE_UDP,
630 RTE_FLOW_ITEM_TYPE_RAW,
631 RTE_FLOW_ITEM_TYPE_RAW,
632 RTE_FLOW_ITEM_TYPE_END,
635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
636 RTE_FLOW_ITEM_TYPE_ETH,
637 RTE_FLOW_ITEM_TYPE_VLAN,
638 RTE_FLOW_ITEM_TYPE_IPV4,
639 RTE_FLOW_ITEM_TYPE_UDP,
640 RTE_FLOW_ITEM_TYPE_RAW,
641 RTE_FLOW_ITEM_TYPE_RAW,
642 RTE_FLOW_ITEM_TYPE_RAW,
643 RTE_FLOW_ITEM_TYPE_END,
646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
647 RTE_FLOW_ITEM_TYPE_ETH,
648 RTE_FLOW_ITEM_TYPE_VLAN,
649 RTE_FLOW_ITEM_TYPE_IPV4,
650 RTE_FLOW_ITEM_TYPE_TCP,
651 RTE_FLOW_ITEM_TYPE_RAW,
652 RTE_FLOW_ITEM_TYPE_END,
655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
656 RTE_FLOW_ITEM_TYPE_ETH,
657 RTE_FLOW_ITEM_TYPE_VLAN,
658 RTE_FLOW_ITEM_TYPE_IPV4,
659 RTE_FLOW_ITEM_TYPE_TCP,
660 RTE_FLOW_ITEM_TYPE_RAW,
661 RTE_FLOW_ITEM_TYPE_RAW,
662 RTE_FLOW_ITEM_TYPE_END,
665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
666 RTE_FLOW_ITEM_TYPE_ETH,
667 RTE_FLOW_ITEM_TYPE_VLAN,
668 RTE_FLOW_ITEM_TYPE_IPV4,
669 RTE_FLOW_ITEM_TYPE_TCP,
670 RTE_FLOW_ITEM_TYPE_RAW,
671 RTE_FLOW_ITEM_TYPE_RAW,
672 RTE_FLOW_ITEM_TYPE_RAW,
673 RTE_FLOW_ITEM_TYPE_END,
676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
677 RTE_FLOW_ITEM_TYPE_ETH,
678 RTE_FLOW_ITEM_TYPE_VLAN,
679 RTE_FLOW_ITEM_TYPE_IPV4,
680 RTE_FLOW_ITEM_TYPE_SCTP,
681 RTE_FLOW_ITEM_TYPE_RAW,
682 RTE_FLOW_ITEM_TYPE_END,
685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
686 RTE_FLOW_ITEM_TYPE_ETH,
687 RTE_FLOW_ITEM_TYPE_VLAN,
688 RTE_FLOW_ITEM_TYPE_IPV4,
689 RTE_FLOW_ITEM_TYPE_SCTP,
690 RTE_FLOW_ITEM_TYPE_RAW,
691 RTE_FLOW_ITEM_TYPE_RAW,
692 RTE_FLOW_ITEM_TYPE_END,
695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
696 RTE_FLOW_ITEM_TYPE_ETH,
697 RTE_FLOW_ITEM_TYPE_VLAN,
698 RTE_FLOW_ITEM_TYPE_IPV4,
699 RTE_FLOW_ITEM_TYPE_SCTP,
700 RTE_FLOW_ITEM_TYPE_RAW,
701 RTE_FLOW_ITEM_TYPE_RAW,
702 RTE_FLOW_ITEM_TYPE_RAW,
703 RTE_FLOW_ITEM_TYPE_END,
706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
707 RTE_FLOW_ITEM_TYPE_ETH,
708 RTE_FLOW_ITEM_TYPE_VLAN,
709 RTE_FLOW_ITEM_TYPE_IPV6,
710 RTE_FLOW_ITEM_TYPE_RAW,
711 RTE_FLOW_ITEM_TYPE_END,
714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
715 RTE_FLOW_ITEM_TYPE_ETH,
716 RTE_FLOW_ITEM_TYPE_VLAN,
717 RTE_FLOW_ITEM_TYPE_IPV6,
718 RTE_FLOW_ITEM_TYPE_RAW,
719 RTE_FLOW_ITEM_TYPE_RAW,
720 RTE_FLOW_ITEM_TYPE_END,
723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
724 RTE_FLOW_ITEM_TYPE_ETH,
725 RTE_FLOW_ITEM_TYPE_VLAN,
726 RTE_FLOW_ITEM_TYPE_IPV6,
727 RTE_FLOW_ITEM_TYPE_RAW,
728 RTE_FLOW_ITEM_TYPE_RAW,
729 RTE_FLOW_ITEM_TYPE_RAW,
730 RTE_FLOW_ITEM_TYPE_END,
733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
734 RTE_FLOW_ITEM_TYPE_ETH,
735 RTE_FLOW_ITEM_TYPE_VLAN,
736 RTE_FLOW_ITEM_TYPE_IPV6,
737 RTE_FLOW_ITEM_TYPE_UDP,
738 RTE_FLOW_ITEM_TYPE_RAW,
739 RTE_FLOW_ITEM_TYPE_END,
742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
743 RTE_FLOW_ITEM_TYPE_ETH,
744 RTE_FLOW_ITEM_TYPE_VLAN,
745 RTE_FLOW_ITEM_TYPE_IPV6,
746 RTE_FLOW_ITEM_TYPE_UDP,
747 RTE_FLOW_ITEM_TYPE_RAW,
748 RTE_FLOW_ITEM_TYPE_RAW,
749 RTE_FLOW_ITEM_TYPE_END,
752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
753 RTE_FLOW_ITEM_TYPE_ETH,
754 RTE_FLOW_ITEM_TYPE_VLAN,
755 RTE_FLOW_ITEM_TYPE_IPV6,
756 RTE_FLOW_ITEM_TYPE_UDP,
757 RTE_FLOW_ITEM_TYPE_RAW,
758 RTE_FLOW_ITEM_TYPE_RAW,
759 RTE_FLOW_ITEM_TYPE_RAW,
760 RTE_FLOW_ITEM_TYPE_END,
763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
764 RTE_FLOW_ITEM_TYPE_ETH,
765 RTE_FLOW_ITEM_TYPE_VLAN,
766 RTE_FLOW_ITEM_TYPE_IPV6,
767 RTE_FLOW_ITEM_TYPE_TCP,
768 RTE_FLOW_ITEM_TYPE_RAW,
769 RTE_FLOW_ITEM_TYPE_END,
772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
773 RTE_FLOW_ITEM_TYPE_ETH,
774 RTE_FLOW_ITEM_TYPE_VLAN,
775 RTE_FLOW_ITEM_TYPE_IPV6,
776 RTE_FLOW_ITEM_TYPE_TCP,
777 RTE_FLOW_ITEM_TYPE_RAW,
778 RTE_FLOW_ITEM_TYPE_RAW,
779 RTE_FLOW_ITEM_TYPE_END,
782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
783 RTE_FLOW_ITEM_TYPE_ETH,
784 RTE_FLOW_ITEM_TYPE_VLAN,
785 RTE_FLOW_ITEM_TYPE_IPV6,
786 RTE_FLOW_ITEM_TYPE_TCP,
787 RTE_FLOW_ITEM_TYPE_RAW,
788 RTE_FLOW_ITEM_TYPE_RAW,
789 RTE_FLOW_ITEM_TYPE_RAW,
790 RTE_FLOW_ITEM_TYPE_END,
793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
794 RTE_FLOW_ITEM_TYPE_ETH,
795 RTE_FLOW_ITEM_TYPE_VLAN,
796 RTE_FLOW_ITEM_TYPE_IPV6,
797 RTE_FLOW_ITEM_TYPE_SCTP,
798 RTE_FLOW_ITEM_TYPE_RAW,
799 RTE_FLOW_ITEM_TYPE_END,
802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
803 RTE_FLOW_ITEM_TYPE_ETH,
804 RTE_FLOW_ITEM_TYPE_VLAN,
805 RTE_FLOW_ITEM_TYPE_IPV6,
806 RTE_FLOW_ITEM_TYPE_SCTP,
807 RTE_FLOW_ITEM_TYPE_RAW,
808 RTE_FLOW_ITEM_TYPE_RAW,
809 RTE_FLOW_ITEM_TYPE_END,
812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
813 RTE_FLOW_ITEM_TYPE_ETH,
814 RTE_FLOW_ITEM_TYPE_VLAN,
815 RTE_FLOW_ITEM_TYPE_IPV6,
816 RTE_FLOW_ITEM_TYPE_SCTP,
817 RTE_FLOW_ITEM_TYPE_RAW,
818 RTE_FLOW_ITEM_TYPE_RAW,
819 RTE_FLOW_ITEM_TYPE_RAW,
820 RTE_FLOW_ITEM_TYPE_END,
823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
824 RTE_FLOW_ITEM_TYPE_ETH,
825 RTE_FLOW_ITEM_TYPE_IPV4,
826 RTE_FLOW_ITEM_TYPE_VF,
827 RTE_FLOW_ITEM_TYPE_END,
830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
831 RTE_FLOW_ITEM_TYPE_ETH,
832 RTE_FLOW_ITEM_TYPE_IPV4,
833 RTE_FLOW_ITEM_TYPE_UDP,
834 RTE_FLOW_ITEM_TYPE_VF,
835 RTE_FLOW_ITEM_TYPE_END,
838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
839 RTE_FLOW_ITEM_TYPE_ETH,
840 RTE_FLOW_ITEM_TYPE_IPV4,
841 RTE_FLOW_ITEM_TYPE_TCP,
842 RTE_FLOW_ITEM_TYPE_VF,
843 RTE_FLOW_ITEM_TYPE_END,
846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
847 RTE_FLOW_ITEM_TYPE_ETH,
848 RTE_FLOW_ITEM_TYPE_IPV4,
849 RTE_FLOW_ITEM_TYPE_SCTP,
850 RTE_FLOW_ITEM_TYPE_VF,
851 RTE_FLOW_ITEM_TYPE_END,
854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
855 RTE_FLOW_ITEM_TYPE_ETH,
856 RTE_FLOW_ITEM_TYPE_IPV6,
857 RTE_FLOW_ITEM_TYPE_VF,
858 RTE_FLOW_ITEM_TYPE_END,
861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
862 RTE_FLOW_ITEM_TYPE_ETH,
863 RTE_FLOW_ITEM_TYPE_IPV6,
864 RTE_FLOW_ITEM_TYPE_UDP,
865 RTE_FLOW_ITEM_TYPE_VF,
866 RTE_FLOW_ITEM_TYPE_END,
869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
870 RTE_FLOW_ITEM_TYPE_ETH,
871 RTE_FLOW_ITEM_TYPE_IPV6,
872 RTE_FLOW_ITEM_TYPE_TCP,
873 RTE_FLOW_ITEM_TYPE_VF,
874 RTE_FLOW_ITEM_TYPE_END,
877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
878 RTE_FLOW_ITEM_TYPE_ETH,
879 RTE_FLOW_ITEM_TYPE_IPV6,
880 RTE_FLOW_ITEM_TYPE_SCTP,
881 RTE_FLOW_ITEM_TYPE_VF,
882 RTE_FLOW_ITEM_TYPE_END,
885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
886 RTE_FLOW_ITEM_TYPE_ETH,
887 RTE_FLOW_ITEM_TYPE_RAW,
888 RTE_FLOW_ITEM_TYPE_VF,
889 RTE_FLOW_ITEM_TYPE_END,
892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
893 RTE_FLOW_ITEM_TYPE_ETH,
894 RTE_FLOW_ITEM_TYPE_RAW,
895 RTE_FLOW_ITEM_TYPE_RAW,
896 RTE_FLOW_ITEM_TYPE_VF,
897 RTE_FLOW_ITEM_TYPE_END,
900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
901 RTE_FLOW_ITEM_TYPE_ETH,
902 RTE_FLOW_ITEM_TYPE_RAW,
903 RTE_FLOW_ITEM_TYPE_RAW,
904 RTE_FLOW_ITEM_TYPE_RAW,
905 RTE_FLOW_ITEM_TYPE_VF,
906 RTE_FLOW_ITEM_TYPE_END,
909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
910 RTE_FLOW_ITEM_TYPE_ETH,
911 RTE_FLOW_ITEM_TYPE_IPV4,
912 RTE_FLOW_ITEM_TYPE_RAW,
913 RTE_FLOW_ITEM_TYPE_VF,
914 RTE_FLOW_ITEM_TYPE_END,
917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
918 RTE_FLOW_ITEM_TYPE_ETH,
919 RTE_FLOW_ITEM_TYPE_IPV4,
920 RTE_FLOW_ITEM_TYPE_RAW,
921 RTE_FLOW_ITEM_TYPE_RAW,
922 RTE_FLOW_ITEM_TYPE_VF,
923 RTE_FLOW_ITEM_TYPE_END,
926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
927 RTE_FLOW_ITEM_TYPE_ETH,
928 RTE_FLOW_ITEM_TYPE_IPV4,
929 RTE_FLOW_ITEM_TYPE_RAW,
930 RTE_FLOW_ITEM_TYPE_RAW,
931 RTE_FLOW_ITEM_TYPE_RAW,
932 RTE_FLOW_ITEM_TYPE_VF,
933 RTE_FLOW_ITEM_TYPE_END,
936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
937 RTE_FLOW_ITEM_TYPE_ETH,
938 RTE_FLOW_ITEM_TYPE_IPV4,
939 RTE_FLOW_ITEM_TYPE_UDP,
940 RTE_FLOW_ITEM_TYPE_RAW,
941 RTE_FLOW_ITEM_TYPE_VF,
942 RTE_FLOW_ITEM_TYPE_END,
945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
946 RTE_FLOW_ITEM_TYPE_ETH,
947 RTE_FLOW_ITEM_TYPE_IPV4,
948 RTE_FLOW_ITEM_TYPE_UDP,
949 RTE_FLOW_ITEM_TYPE_RAW,
950 RTE_FLOW_ITEM_TYPE_RAW,
951 RTE_FLOW_ITEM_TYPE_VF,
952 RTE_FLOW_ITEM_TYPE_END,
955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
956 RTE_FLOW_ITEM_TYPE_ETH,
957 RTE_FLOW_ITEM_TYPE_IPV4,
958 RTE_FLOW_ITEM_TYPE_UDP,
959 RTE_FLOW_ITEM_TYPE_RAW,
960 RTE_FLOW_ITEM_TYPE_RAW,
961 RTE_FLOW_ITEM_TYPE_RAW,
962 RTE_FLOW_ITEM_TYPE_VF,
963 RTE_FLOW_ITEM_TYPE_END,
966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
967 RTE_FLOW_ITEM_TYPE_ETH,
968 RTE_FLOW_ITEM_TYPE_IPV4,
969 RTE_FLOW_ITEM_TYPE_TCP,
970 RTE_FLOW_ITEM_TYPE_RAW,
971 RTE_FLOW_ITEM_TYPE_VF,
972 RTE_FLOW_ITEM_TYPE_END,
975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
976 RTE_FLOW_ITEM_TYPE_ETH,
977 RTE_FLOW_ITEM_TYPE_IPV4,
978 RTE_FLOW_ITEM_TYPE_TCP,
979 RTE_FLOW_ITEM_TYPE_RAW,
980 RTE_FLOW_ITEM_TYPE_RAW,
981 RTE_FLOW_ITEM_TYPE_VF,
982 RTE_FLOW_ITEM_TYPE_END,
985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
986 RTE_FLOW_ITEM_TYPE_ETH,
987 RTE_FLOW_ITEM_TYPE_IPV4,
988 RTE_FLOW_ITEM_TYPE_TCP,
989 RTE_FLOW_ITEM_TYPE_RAW,
990 RTE_FLOW_ITEM_TYPE_RAW,
991 RTE_FLOW_ITEM_TYPE_RAW,
992 RTE_FLOW_ITEM_TYPE_VF,
993 RTE_FLOW_ITEM_TYPE_END,
996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
997 RTE_FLOW_ITEM_TYPE_ETH,
998 RTE_FLOW_ITEM_TYPE_IPV4,
999 RTE_FLOW_ITEM_TYPE_SCTP,
1000 RTE_FLOW_ITEM_TYPE_RAW,
1001 RTE_FLOW_ITEM_TYPE_VF,
1002 RTE_FLOW_ITEM_TYPE_END,
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006 RTE_FLOW_ITEM_TYPE_ETH,
1007 RTE_FLOW_ITEM_TYPE_IPV4,
1008 RTE_FLOW_ITEM_TYPE_SCTP,
1009 RTE_FLOW_ITEM_TYPE_RAW,
1010 RTE_FLOW_ITEM_TYPE_RAW,
1011 RTE_FLOW_ITEM_TYPE_VF,
1012 RTE_FLOW_ITEM_TYPE_END,
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016 RTE_FLOW_ITEM_TYPE_ETH,
1017 RTE_FLOW_ITEM_TYPE_IPV4,
1018 RTE_FLOW_ITEM_TYPE_SCTP,
1019 RTE_FLOW_ITEM_TYPE_RAW,
1020 RTE_FLOW_ITEM_TYPE_RAW,
1021 RTE_FLOW_ITEM_TYPE_RAW,
1022 RTE_FLOW_ITEM_TYPE_VF,
1023 RTE_FLOW_ITEM_TYPE_END,
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027 RTE_FLOW_ITEM_TYPE_ETH,
1028 RTE_FLOW_ITEM_TYPE_IPV6,
1029 RTE_FLOW_ITEM_TYPE_RAW,
1030 RTE_FLOW_ITEM_TYPE_VF,
1031 RTE_FLOW_ITEM_TYPE_END,
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035 RTE_FLOW_ITEM_TYPE_ETH,
1036 RTE_FLOW_ITEM_TYPE_IPV6,
1037 RTE_FLOW_ITEM_TYPE_RAW,
1038 RTE_FLOW_ITEM_TYPE_RAW,
1039 RTE_FLOW_ITEM_TYPE_VF,
1040 RTE_FLOW_ITEM_TYPE_END,
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044 RTE_FLOW_ITEM_TYPE_ETH,
1045 RTE_FLOW_ITEM_TYPE_IPV6,
1046 RTE_FLOW_ITEM_TYPE_RAW,
1047 RTE_FLOW_ITEM_TYPE_RAW,
1048 RTE_FLOW_ITEM_TYPE_RAW,
1049 RTE_FLOW_ITEM_TYPE_VF,
1050 RTE_FLOW_ITEM_TYPE_END,
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054 RTE_FLOW_ITEM_TYPE_ETH,
1055 RTE_FLOW_ITEM_TYPE_IPV6,
1056 RTE_FLOW_ITEM_TYPE_UDP,
1057 RTE_FLOW_ITEM_TYPE_RAW,
1058 RTE_FLOW_ITEM_TYPE_VF,
1059 RTE_FLOW_ITEM_TYPE_END,
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063 RTE_FLOW_ITEM_TYPE_ETH,
1064 RTE_FLOW_ITEM_TYPE_IPV6,
1065 RTE_FLOW_ITEM_TYPE_UDP,
1066 RTE_FLOW_ITEM_TYPE_RAW,
1067 RTE_FLOW_ITEM_TYPE_RAW,
1068 RTE_FLOW_ITEM_TYPE_VF,
1069 RTE_FLOW_ITEM_TYPE_END,
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073 RTE_FLOW_ITEM_TYPE_ETH,
1074 RTE_FLOW_ITEM_TYPE_IPV6,
1075 RTE_FLOW_ITEM_TYPE_UDP,
1076 RTE_FLOW_ITEM_TYPE_RAW,
1077 RTE_FLOW_ITEM_TYPE_RAW,
1078 RTE_FLOW_ITEM_TYPE_RAW,
1079 RTE_FLOW_ITEM_TYPE_VF,
1080 RTE_FLOW_ITEM_TYPE_END,
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084 RTE_FLOW_ITEM_TYPE_ETH,
1085 RTE_FLOW_ITEM_TYPE_IPV6,
1086 RTE_FLOW_ITEM_TYPE_TCP,
1087 RTE_FLOW_ITEM_TYPE_RAW,
1088 RTE_FLOW_ITEM_TYPE_VF,
1089 RTE_FLOW_ITEM_TYPE_END,
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093 RTE_FLOW_ITEM_TYPE_ETH,
1094 RTE_FLOW_ITEM_TYPE_IPV6,
1095 RTE_FLOW_ITEM_TYPE_TCP,
1096 RTE_FLOW_ITEM_TYPE_RAW,
1097 RTE_FLOW_ITEM_TYPE_RAW,
1098 RTE_FLOW_ITEM_TYPE_VF,
1099 RTE_FLOW_ITEM_TYPE_END,
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103 RTE_FLOW_ITEM_TYPE_ETH,
1104 RTE_FLOW_ITEM_TYPE_IPV6,
1105 RTE_FLOW_ITEM_TYPE_TCP,
1106 RTE_FLOW_ITEM_TYPE_RAW,
1107 RTE_FLOW_ITEM_TYPE_RAW,
1108 RTE_FLOW_ITEM_TYPE_RAW,
1109 RTE_FLOW_ITEM_TYPE_VF,
1110 RTE_FLOW_ITEM_TYPE_END,
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114 RTE_FLOW_ITEM_TYPE_ETH,
1115 RTE_FLOW_ITEM_TYPE_IPV6,
1116 RTE_FLOW_ITEM_TYPE_SCTP,
1117 RTE_FLOW_ITEM_TYPE_RAW,
1118 RTE_FLOW_ITEM_TYPE_VF,
1119 RTE_FLOW_ITEM_TYPE_END,
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123 RTE_FLOW_ITEM_TYPE_ETH,
1124 RTE_FLOW_ITEM_TYPE_IPV6,
1125 RTE_FLOW_ITEM_TYPE_SCTP,
1126 RTE_FLOW_ITEM_TYPE_RAW,
1127 RTE_FLOW_ITEM_TYPE_RAW,
1128 RTE_FLOW_ITEM_TYPE_VF,
1129 RTE_FLOW_ITEM_TYPE_END,
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133 RTE_FLOW_ITEM_TYPE_ETH,
1134 RTE_FLOW_ITEM_TYPE_IPV6,
1135 RTE_FLOW_ITEM_TYPE_SCTP,
1136 RTE_FLOW_ITEM_TYPE_RAW,
1137 RTE_FLOW_ITEM_TYPE_RAW,
1138 RTE_FLOW_ITEM_TYPE_RAW,
1139 RTE_FLOW_ITEM_TYPE_VF,
1140 RTE_FLOW_ITEM_TYPE_END,
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144 RTE_FLOW_ITEM_TYPE_ETH,
1145 RTE_FLOW_ITEM_TYPE_VLAN,
1146 RTE_FLOW_ITEM_TYPE_VF,
1147 RTE_FLOW_ITEM_TYPE_END,
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151 RTE_FLOW_ITEM_TYPE_ETH,
1152 RTE_FLOW_ITEM_TYPE_VLAN,
1153 RTE_FLOW_ITEM_TYPE_IPV4,
1154 RTE_FLOW_ITEM_TYPE_VF,
1155 RTE_FLOW_ITEM_TYPE_END,
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159 RTE_FLOW_ITEM_TYPE_ETH,
1160 RTE_FLOW_ITEM_TYPE_VLAN,
1161 RTE_FLOW_ITEM_TYPE_IPV4,
1162 RTE_FLOW_ITEM_TYPE_UDP,
1163 RTE_FLOW_ITEM_TYPE_VF,
1164 RTE_FLOW_ITEM_TYPE_END,
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168 RTE_FLOW_ITEM_TYPE_ETH,
1169 RTE_FLOW_ITEM_TYPE_VLAN,
1170 RTE_FLOW_ITEM_TYPE_IPV4,
1171 RTE_FLOW_ITEM_TYPE_TCP,
1172 RTE_FLOW_ITEM_TYPE_VF,
1173 RTE_FLOW_ITEM_TYPE_END,
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177 RTE_FLOW_ITEM_TYPE_ETH,
1178 RTE_FLOW_ITEM_TYPE_VLAN,
1179 RTE_FLOW_ITEM_TYPE_IPV4,
1180 RTE_FLOW_ITEM_TYPE_SCTP,
1181 RTE_FLOW_ITEM_TYPE_VF,
1182 RTE_FLOW_ITEM_TYPE_END,
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186 RTE_FLOW_ITEM_TYPE_ETH,
1187 RTE_FLOW_ITEM_TYPE_VLAN,
1188 RTE_FLOW_ITEM_TYPE_IPV6,
1189 RTE_FLOW_ITEM_TYPE_VF,
1190 RTE_FLOW_ITEM_TYPE_END,
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194 RTE_FLOW_ITEM_TYPE_ETH,
1195 RTE_FLOW_ITEM_TYPE_VLAN,
1196 RTE_FLOW_ITEM_TYPE_IPV6,
1197 RTE_FLOW_ITEM_TYPE_UDP,
1198 RTE_FLOW_ITEM_TYPE_VF,
1199 RTE_FLOW_ITEM_TYPE_END,
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203 RTE_FLOW_ITEM_TYPE_ETH,
1204 RTE_FLOW_ITEM_TYPE_VLAN,
1205 RTE_FLOW_ITEM_TYPE_IPV6,
1206 RTE_FLOW_ITEM_TYPE_TCP,
1207 RTE_FLOW_ITEM_TYPE_VF,
1208 RTE_FLOW_ITEM_TYPE_END,
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212 RTE_FLOW_ITEM_TYPE_ETH,
1213 RTE_FLOW_ITEM_TYPE_VLAN,
1214 RTE_FLOW_ITEM_TYPE_IPV6,
1215 RTE_FLOW_ITEM_TYPE_SCTP,
1216 RTE_FLOW_ITEM_TYPE_VF,
1217 RTE_FLOW_ITEM_TYPE_END,
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221 RTE_FLOW_ITEM_TYPE_ETH,
1222 RTE_FLOW_ITEM_TYPE_VLAN,
1223 RTE_FLOW_ITEM_TYPE_RAW,
1224 RTE_FLOW_ITEM_TYPE_VF,
1225 RTE_FLOW_ITEM_TYPE_END,
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229 RTE_FLOW_ITEM_TYPE_ETH,
1230 RTE_FLOW_ITEM_TYPE_VLAN,
1231 RTE_FLOW_ITEM_TYPE_RAW,
1232 RTE_FLOW_ITEM_TYPE_RAW,
1233 RTE_FLOW_ITEM_TYPE_VF,
1234 RTE_FLOW_ITEM_TYPE_END,
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238 RTE_FLOW_ITEM_TYPE_ETH,
1239 RTE_FLOW_ITEM_TYPE_VLAN,
1240 RTE_FLOW_ITEM_TYPE_RAW,
1241 RTE_FLOW_ITEM_TYPE_RAW,
1242 RTE_FLOW_ITEM_TYPE_RAW,
1243 RTE_FLOW_ITEM_TYPE_VF,
1244 RTE_FLOW_ITEM_TYPE_END,
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248 RTE_FLOW_ITEM_TYPE_ETH,
1249 RTE_FLOW_ITEM_TYPE_VLAN,
1250 RTE_FLOW_ITEM_TYPE_IPV4,
1251 RTE_FLOW_ITEM_TYPE_RAW,
1252 RTE_FLOW_ITEM_TYPE_VF,
1253 RTE_FLOW_ITEM_TYPE_END,
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257 RTE_FLOW_ITEM_TYPE_ETH,
1258 RTE_FLOW_ITEM_TYPE_VLAN,
1259 RTE_FLOW_ITEM_TYPE_IPV4,
1260 RTE_FLOW_ITEM_TYPE_RAW,
1261 RTE_FLOW_ITEM_TYPE_RAW,
1262 RTE_FLOW_ITEM_TYPE_VF,
1263 RTE_FLOW_ITEM_TYPE_END,
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267 RTE_FLOW_ITEM_TYPE_ETH,
1268 RTE_FLOW_ITEM_TYPE_VLAN,
1269 RTE_FLOW_ITEM_TYPE_IPV4,
1270 RTE_FLOW_ITEM_TYPE_RAW,
1271 RTE_FLOW_ITEM_TYPE_RAW,
1272 RTE_FLOW_ITEM_TYPE_RAW,
1273 RTE_FLOW_ITEM_TYPE_VF,
1274 RTE_FLOW_ITEM_TYPE_END,
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278 RTE_FLOW_ITEM_TYPE_ETH,
1279 RTE_FLOW_ITEM_TYPE_VLAN,
1280 RTE_FLOW_ITEM_TYPE_IPV4,
1281 RTE_FLOW_ITEM_TYPE_UDP,
1282 RTE_FLOW_ITEM_TYPE_RAW,
1283 RTE_FLOW_ITEM_TYPE_VF,
1284 RTE_FLOW_ITEM_TYPE_END,
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288 RTE_FLOW_ITEM_TYPE_ETH,
1289 RTE_FLOW_ITEM_TYPE_VLAN,
1290 RTE_FLOW_ITEM_TYPE_IPV4,
1291 RTE_FLOW_ITEM_TYPE_UDP,
1292 RTE_FLOW_ITEM_TYPE_RAW,
1293 RTE_FLOW_ITEM_TYPE_RAW,
1294 RTE_FLOW_ITEM_TYPE_VF,
1295 RTE_FLOW_ITEM_TYPE_END,
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299 RTE_FLOW_ITEM_TYPE_ETH,
1300 RTE_FLOW_ITEM_TYPE_VLAN,
1301 RTE_FLOW_ITEM_TYPE_IPV4,
1302 RTE_FLOW_ITEM_TYPE_UDP,
1303 RTE_FLOW_ITEM_TYPE_RAW,
1304 RTE_FLOW_ITEM_TYPE_RAW,
1305 RTE_FLOW_ITEM_TYPE_RAW,
1306 RTE_FLOW_ITEM_TYPE_VF,
1307 RTE_FLOW_ITEM_TYPE_END,
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311 RTE_FLOW_ITEM_TYPE_ETH,
1312 RTE_FLOW_ITEM_TYPE_VLAN,
1313 RTE_FLOW_ITEM_TYPE_IPV4,
1314 RTE_FLOW_ITEM_TYPE_TCP,
1315 RTE_FLOW_ITEM_TYPE_RAW,
1316 RTE_FLOW_ITEM_TYPE_VF,
1317 RTE_FLOW_ITEM_TYPE_END,
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321 RTE_FLOW_ITEM_TYPE_ETH,
1322 RTE_FLOW_ITEM_TYPE_VLAN,
1323 RTE_FLOW_ITEM_TYPE_IPV4,
1324 RTE_FLOW_ITEM_TYPE_TCP,
1325 RTE_FLOW_ITEM_TYPE_RAW,
1326 RTE_FLOW_ITEM_TYPE_RAW,
1327 RTE_FLOW_ITEM_TYPE_VF,
1328 RTE_FLOW_ITEM_TYPE_END,
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332 RTE_FLOW_ITEM_TYPE_ETH,
1333 RTE_FLOW_ITEM_TYPE_VLAN,
1334 RTE_FLOW_ITEM_TYPE_IPV4,
1335 RTE_FLOW_ITEM_TYPE_TCP,
1336 RTE_FLOW_ITEM_TYPE_RAW,
1337 RTE_FLOW_ITEM_TYPE_RAW,
1338 RTE_FLOW_ITEM_TYPE_RAW,
1339 RTE_FLOW_ITEM_TYPE_VF,
1340 RTE_FLOW_ITEM_TYPE_END,
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344 RTE_FLOW_ITEM_TYPE_ETH,
1345 RTE_FLOW_ITEM_TYPE_VLAN,
1346 RTE_FLOW_ITEM_TYPE_IPV4,
1347 RTE_FLOW_ITEM_TYPE_SCTP,
1348 RTE_FLOW_ITEM_TYPE_RAW,
1349 RTE_FLOW_ITEM_TYPE_VF,
1350 RTE_FLOW_ITEM_TYPE_END,
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354 RTE_FLOW_ITEM_TYPE_ETH,
1355 RTE_FLOW_ITEM_TYPE_VLAN,
1356 RTE_FLOW_ITEM_TYPE_IPV4,
1357 RTE_FLOW_ITEM_TYPE_SCTP,
1358 RTE_FLOW_ITEM_TYPE_RAW,
1359 RTE_FLOW_ITEM_TYPE_RAW,
1360 RTE_FLOW_ITEM_TYPE_VF,
1361 RTE_FLOW_ITEM_TYPE_END,
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365 RTE_FLOW_ITEM_TYPE_ETH,
1366 RTE_FLOW_ITEM_TYPE_VLAN,
1367 RTE_FLOW_ITEM_TYPE_IPV4,
1368 RTE_FLOW_ITEM_TYPE_SCTP,
1369 RTE_FLOW_ITEM_TYPE_RAW,
1370 RTE_FLOW_ITEM_TYPE_RAW,
1371 RTE_FLOW_ITEM_TYPE_RAW,
1372 RTE_FLOW_ITEM_TYPE_VF,
1373 RTE_FLOW_ITEM_TYPE_END,
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377 RTE_FLOW_ITEM_TYPE_ETH,
1378 RTE_FLOW_ITEM_TYPE_VLAN,
1379 RTE_FLOW_ITEM_TYPE_IPV6,
1380 RTE_FLOW_ITEM_TYPE_RAW,
1381 RTE_FLOW_ITEM_TYPE_VF,
1382 RTE_FLOW_ITEM_TYPE_END,
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386 RTE_FLOW_ITEM_TYPE_ETH,
1387 RTE_FLOW_ITEM_TYPE_VLAN,
1388 RTE_FLOW_ITEM_TYPE_IPV6,
1389 RTE_FLOW_ITEM_TYPE_RAW,
1390 RTE_FLOW_ITEM_TYPE_RAW,
1391 RTE_FLOW_ITEM_TYPE_VF,
1392 RTE_FLOW_ITEM_TYPE_END,
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396 RTE_FLOW_ITEM_TYPE_ETH,
1397 RTE_FLOW_ITEM_TYPE_VLAN,
1398 RTE_FLOW_ITEM_TYPE_IPV6,
1399 RTE_FLOW_ITEM_TYPE_RAW,
1400 RTE_FLOW_ITEM_TYPE_RAW,
1401 RTE_FLOW_ITEM_TYPE_RAW,
1402 RTE_FLOW_ITEM_TYPE_VF,
1403 RTE_FLOW_ITEM_TYPE_END,
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407 RTE_FLOW_ITEM_TYPE_ETH,
1408 RTE_FLOW_ITEM_TYPE_VLAN,
1409 RTE_FLOW_ITEM_TYPE_IPV6,
1410 RTE_FLOW_ITEM_TYPE_UDP,
1411 RTE_FLOW_ITEM_TYPE_RAW,
1412 RTE_FLOW_ITEM_TYPE_VF,
1413 RTE_FLOW_ITEM_TYPE_END,
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417 RTE_FLOW_ITEM_TYPE_ETH,
1418 RTE_FLOW_ITEM_TYPE_VLAN,
1419 RTE_FLOW_ITEM_TYPE_IPV6,
1420 RTE_FLOW_ITEM_TYPE_UDP,
1421 RTE_FLOW_ITEM_TYPE_RAW,
1422 RTE_FLOW_ITEM_TYPE_RAW,
1423 RTE_FLOW_ITEM_TYPE_VF,
1424 RTE_FLOW_ITEM_TYPE_END,
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428 RTE_FLOW_ITEM_TYPE_ETH,
1429 RTE_FLOW_ITEM_TYPE_VLAN,
1430 RTE_FLOW_ITEM_TYPE_IPV6,
1431 RTE_FLOW_ITEM_TYPE_UDP,
1432 RTE_FLOW_ITEM_TYPE_RAW,
1433 RTE_FLOW_ITEM_TYPE_RAW,
1434 RTE_FLOW_ITEM_TYPE_RAW,
1435 RTE_FLOW_ITEM_TYPE_VF,
1436 RTE_FLOW_ITEM_TYPE_END,
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440 RTE_FLOW_ITEM_TYPE_ETH,
1441 RTE_FLOW_ITEM_TYPE_VLAN,
1442 RTE_FLOW_ITEM_TYPE_IPV6,
1443 RTE_FLOW_ITEM_TYPE_TCP,
1444 RTE_FLOW_ITEM_TYPE_RAW,
1445 RTE_FLOW_ITEM_TYPE_VF,
1446 RTE_FLOW_ITEM_TYPE_END,
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450 RTE_FLOW_ITEM_TYPE_ETH,
1451 RTE_FLOW_ITEM_TYPE_VLAN,
1452 RTE_FLOW_ITEM_TYPE_IPV6,
1453 RTE_FLOW_ITEM_TYPE_TCP,
1454 RTE_FLOW_ITEM_TYPE_RAW,
1455 RTE_FLOW_ITEM_TYPE_RAW,
1456 RTE_FLOW_ITEM_TYPE_VF,
1457 RTE_FLOW_ITEM_TYPE_END,
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461 RTE_FLOW_ITEM_TYPE_ETH,
1462 RTE_FLOW_ITEM_TYPE_VLAN,
1463 RTE_FLOW_ITEM_TYPE_IPV6,
1464 RTE_FLOW_ITEM_TYPE_TCP,
1465 RTE_FLOW_ITEM_TYPE_RAW,
1466 RTE_FLOW_ITEM_TYPE_RAW,
1467 RTE_FLOW_ITEM_TYPE_RAW,
1468 RTE_FLOW_ITEM_TYPE_VF,
1469 RTE_FLOW_ITEM_TYPE_END,
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473 RTE_FLOW_ITEM_TYPE_ETH,
1474 RTE_FLOW_ITEM_TYPE_VLAN,
1475 RTE_FLOW_ITEM_TYPE_IPV6,
1476 RTE_FLOW_ITEM_TYPE_SCTP,
1477 RTE_FLOW_ITEM_TYPE_RAW,
1478 RTE_FLOW_ITEM_TYPE_VF,
1479 RTE_FLOW_ITEM_TYPE_END,
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483 RTE_FLOW_ITEM_TYPE_ETH,
1484 RTE_FLOW_ITEM_TYPE_VLAN,
1485 RTE_FLOW_ITEM_TYPE_IPV6,
1486 RTE_FLOW_ITEM_TYPE_SCTP,
1487 RTE_FLOW_ITEM_TYPE_RAW,
1488 RTE_FLOW_ITEM_TYPE_RAW,
1489 RTE_FLOW_ITEM_TYPE_VF,
1490 RTE_FLOW_ITEM_TYPE_END,
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494 RTE_FLOW_ITEM_TYPE_ETH,
1495 RTE_FLOW_ITEM_TYPE_VLAN,
1496 RTE_FLOW_ITEM_TYPE_IPV6,
1497 RTE_FLOW_ITEM_TYPE_SCTP,
1498 RTE_FLOW_ITEM_TYPE_RAW,
1499 RTE_FLOW_ITEM_TYPE_RAW,
1500 RTE_FLOW_ITEM_TYPE_RAW,
1501 RTE_FLOW_ITEM_TYPE_VF,
1502 RTE_FLOW_ITEM_TYPE_END,
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507 RTE_FLOW_ITEM_TYPE_ETH,
1508 RTE_FLOW_ITEM_TYPE_IPV4,
1509 RTE_FLOW_ITEM_TYPE_UDP,
1510 RTE_FLOW_ITEM_TYPE_VXLAN,
1511 RTE_FLOW_ITEM_TYPE_ETH,
1512 RTE_FLOW_ITEM_TYPE_END,
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516 RTE_FLOW_ITEM_TYPE_ETH,
1517 RTE_FLOW_ITEM_TYPE_IPV6,
1518 RTE_FLOW_ITEM_TYPE_UDP,
1519 RTE_FLOW_ITEM_TYPE_VXLAN,
1520 RTE_FLOW_ITEM_TYPE_ETH,
1521 RTE_FLOW_ITEM_TYPE_END,
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525 RTE_FLOW_ITEM_TYPE_ETH,
1526 RTE_FLOW_ITEM_TYPE_IPV4,
1527 RTE_FLOW_ITEM_TYPE_UDP,
1528 RTE_FLOW_ITEM_TYPE_VXLAN,
1529 RTE_FLOW_ITEM_TYPE_ETH,
1530 RTE_FLOW_ITEM_TYPE_VLAN,
1531 RTE_FLOW_ITEM_TYPE_END,
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535 RTE_FLOW_ITEM_TYPE_ETH,
1536 RTE_FLOW_ITEM_TYPE_IPV6,
1537 RTE_FLOW_ITEM_TYPE_UDP,
1538 RTE_FLOW_ITEM_TYPE_VXLAN,
1539 RTE_FLOW_ITEM_TYPE_ETH,
1540 RTE_FLOW_ITEM_TYPE_VLAN,
1541 RTE_FLOW_ITEM_TYPE_END,
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545 RTE_FLOW_ITEM_TYPE_ETH,
1546 RTE_FLOW_ITEM_TYPE_IPV4,
1547 RTE_FLOW_ITEM_TYPE_NVGRE,
1548 RTE_FLOW_ITEM_TYPE_ETH,
1549 RTE_FLOW_ITEM_TYPE_END,
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553 RTE_FLOW_ITEM_TYPE_ETH,
1554 RTE_FLOW_ITEM_TYPE_IPV6,
1555 RTE_FLOW_ITEM_TYPE_NVGRE,
1556 RTE_FLOW_ITEM_TYPE_ETH,
1557 RTE_FLOW_ITEM_TYPE_END,
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561 RTE_FLOW_ITEM_TYPE_ETH,
1562 RTE_FLOW_ITEM_TYPE_IPV4,
1563 RTE_FLOW_ITEM_TYPE_NVGRE,
1564 RTE_FLOW_ITEM_TYPE_ETH,
1565 RTE_FLOW_ITEM_TYPE_VLAN,
1566 RTE_FLOW_ITEM_TYPE_END,
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570 RTE_FLOW_ITEM_TYPE_ETH,
1571 RTE_FLOW_ITEM_TYPE_IPV6,
1572 RTE_FLOW_ITEM_TYPE_NVGRE,
1573 RTE_FLOW_ITEM_TYPE_ETH,
1574 RTE_FLOW_ITEM_TYPE_VLAN,
1575 RTE_FLOW_ITEM_TYPE_END,
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579 RTE_FLOW_ITEM_TYPE_ETH,
1580 RTE_FLOW_ITEM_TYPE_IPV4,
1581 RTE_FLOW_ITEM_TYPE_UDP,
1582 RTE_FLOW_ITEM_TYPE_MPLS,
1583 RTE_FLOW_ITEM_TYPE_END,
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587 RTE_FLOW_ITEM_TYPE_ETH,
1588 RTE_FLOW_ITEM_TYPE_IPV6,
1589 RTE_FLOW_ITEM_TYPE_UDP,
1590 RTE_FLOW_ITEM_TYPE_MPLS,
1591 RTE_FLOW_ITEM_TYPE_END,
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595 RTE_FLOW_ITEM_TYPE_ETH,
1596 RTE_FLOW_ITEM_TYPE_IPV4,
1597 RTE_FLOW_ITEM_TYPE_GRE,
1598 RTE_FLOW_ITEM_TYPE_MPLS,
1599 RTE_FLOW_ITEM_TYPE_END,
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603 RTE_FLOW_ITEM_TYPE_ETH,
1604 RTE_FLOW_ITEM_TYPE_IPV6,
1605 RTE_FLOW_ITEM_TYPE_GRE,
1606 RTE_FLOW_ITEM_TYPE_MPLS,
1607 RTE_FLOW_ITEM_TYPE_END,
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611 RTE_FLOW_ITEM_TYPE_ETH,
1612 RTE_FLOW_ITEM_TYPE_VLAN,
1613 RTE_FLOW_ITEM_TYPE_VLAN,
1614 RTE_FLOW_ITEM_TYPE_END,
1617 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1619 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1620 /* FDIR - support default flow type without flexible payload*/
1621 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1622 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1623 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1624 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1625 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1626 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1627 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1628 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1629 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1630 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1631 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1632 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1633 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1634 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1635 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1636 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1637 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1638 /* FDIR - support default flow type with flexible payload */
1639 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1640 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1641 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1642 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1643 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1644 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1645 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1646 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1647 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1648 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1649 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1650 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1651 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1652 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1653 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1654 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1655 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1656 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1657 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1658 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1659 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1660 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1661 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1662 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1663 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1664 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1665 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1666 /* FDIR - support single vlan input set */
1667 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1668 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1669 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1703 /* FDIR - support VF item */
1704 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1705 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1729 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1730 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1731 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1732 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1751 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1752 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1776 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1777 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1778 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1779 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1781 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1782 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1783 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1784 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1785 /* MPLSoUDP & MPLSoGRE */
1786 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1787 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1788 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1789 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1791 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1792 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1793 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1794 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1796 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1799 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1801 act = actions + index; \
1802 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1804 act = actions + index; \
1808 /* Find the first VOID or non-VOID item pointer */
1809 static const struct rte_flow_item *
1810 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1814 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1816 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1818 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1826 /* Skip all VOID items of the pattern */
1828 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1829 const struct rte_flow_item *pattern)
1831 uint32_t cpy_count = 0;
1832 const struct rte_flow_item *pb = pattern, *pe = pattern;
1835 /* Find a non-void item first */
1836 pb = i40e_find_first_item(pb, false);
1837 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1842 /* Find a void item */
1843 pe = i40e_find_first_item(pb + 1, true);
1845 cpy_count = pe - pb;
1846 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1850 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1857 /* Copy the END item. */
1858 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1861 /* Check if the pattern matches a supported item type array */
1863 i40e_match_pattern(enum rte_flow_item_type *item_array,
1864 struct rte_flow_item *pattern)
1866 struct rte_flow_item *item = pattern;
1868 while ((*item_array == item->type) &&
1869 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1874 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1875 item->type == RTE_FLOW_ITEM_TYPE_END);
1878 /* Find if there's parse filter function matched */
1879 static parse_filter_t
1880 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1882 parse_filter_t parse_filter = NULL;
1885 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1886 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1888 parse_filter = i40e_supported_patterns[i].parse_filter;
1895 return parse_filter;
1898 /* Parse attributes */
1900 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1901 struct rte_flow_error *error)
1903 /* Must be input direction */
1904 if (!attr->ingress) {
1905 rte_flow_error_set(error, EINVAL,
1906 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1907 attr, "Only support ingress.");
1913 rte_flow_error_set(error, EINVAL,
1914 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1915 attr, "Not support egress.");
1920 if (attr->priority) {
1921 rte_flow_error_set(error, EINVAL,
1922 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1923 attr, "Not support priority.");
1929 rte_flow_error_set(error, EINVAL,
1930 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1931 attr, "Not support group.");
1939 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1952 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1955 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1960 /* 1. Last in item should be NULL as range is not supported.
1961 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1962 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1963 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1965 * 5. Ether_type mask should be 0xFFFF.
1968 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1969 const struct rte_flow_item *pattern,
1970 struct rte_flow_error *error,
1971 struct rte_eth_ethertype_filter *filter)
1973 const struct rte_flow_item *item = pattern;
1974 const struct rte_flow_item_eth *eth_spec;
1975 const struct rte_flow_item_eth *eth_mask;
1976 enum rte_flow_item_type item_type;
1977 uint16_t outer_tpid;
1979 outer_tpid = i40e_get_outer_vlan(dev);
1981 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1983 rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ITEM,
1986 "Not support range");
1989 item_type = item->type;
1990 switch (item_type) {
1991 case RTE_FLOW_ITEM_TYPE_ETH:
1992 eth_spec = (const struct rte_flow_item_eth *)item->spec;
1993 eth_mask = (const struct rte_flow_item_eth *)item->mask;
1994 /* Get the MAC info. */
1995 if (!eth_spec || !eth_mask) {
1996 rte_flow_error_set(error, EINVAL,
1997 RTE_FLOW_ERROR_TYPE_ITEM,
1999 "NULL ETH spec/mask");
2003 /* Mask bits of source MAC address must be full of 0.
2004 * Mask bits of destination MAC address must be full
2005 * of 1 or full of 0.
2007 if (!is_zero_ether_addr(ð_mask->src) ||
2008 (!is_zero_ether_addr(ð_mask->dst) &&
2009 !is_broadcast_ether_addr(ð_mask->dst))) {
2010 rte_flow_error_set(error, EINVAL,
2011 RTE_FLOW_ERROR_TYPE_ITEM,
2013 "Invalid MAC_addr mask");
2017 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2018 rte_flow_error_set(error, EINVAL,
2019 RTE_FLOW_ERROR_TYPE_ITEM,
2021 "Invalid ethertype mask");
2025 /* If mask bits of destination MAC address
2026 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2028 if (is_broadcast_ether_addr(ð_mask->dst)) {
2029 filter->mac_addr = eth_spec->dst;
2030 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2032 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2034 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2036 if (filter->ether_type == ETHER_TYPE_IPv4 ||
2037 filter->ether_type == ETHER_TYPE_IPv6 ||
2038 filter->ether_type == ETHER_TYPE_LLDP ||
2039 filter->ether_type == outer_tpid) {
2040 rte_flow_error_set(error, EINVAL,
2041 RTE_FLOW_ERROR_TYPE_ITEM,
2043 "Unsupported ether_type in"
2044 " control packet filter.");
2056 /* Ethertype action only supports QUEUE or DROP. */
2058 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2059 const struct rte_flow_action *actions,
2060 struct rte_flow_error *error,
2061 struct rte_eth_ethertype_filter *filter)
2063 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064 const struct rte_flow_action *act;
2065 const struct rte_flow_action_queue *act_q;
2068 /* Check if the first non-void action is QUEUE or DROP. */
2069 NEXT_ITEM_OF_ACTION(act, actions, index);
2070 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2071 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2072 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2073 act, "Not supported action.");
2077 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2078 act_q = (const struct rte_flow_action_queue *)act->conf;
2079 filter->queue = act_q->index;
2080 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2081 rte_flow_error_set(error, EINVAL,
2082 RTE_FLOW_ERROR_TYPE_ACTION,
2083 act, "Invalid queue ID for"
2084 " ethertype_filter.");
2088 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2091 /* Check if the next non-void item is END */
2093 NEXT_ITEM_OF_ACTION(act, actions, index);
2094 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2095 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2096 act, "Not supported action.");
2104 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2105 const struct rte_flow_attr *attr,
2106 const struct rte_flow_item pattern[],
2107 const struct rte_flow_action actions[],
2108 struct rte_flow_error *error,
2109 union i40e_filter_t *filter)
2111 struct rte_eth_ethertype_filter *ethertype_filter =
2112 &filter->ethertype_filter;
2115 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2120 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2125 ret = i40e_flow_parse_attr(attr, error);
2129 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2135 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2136 const struct rte_flow_item_raw *raw_spec,
2137 struct rte_flow_error *error)
2139 if (!raw_spec->relative) {
2140 rte_flow_error_set(error, EINVAL,
2141 RTE_FLOW_ERROR_TYPE_ITEM,
2143 "Relative should be 1.");
2147 if (raw_spec->offset % sizeof(uint16_t)) {
2148 rte_flow_error_set(error, EINVAL,
2149 RTE_FLOW_ERROR_TYPE_ITEM,
2151 "Offset should be even.");
2155 if (raw_spec->search || raw_spec->limit) {
2156 rte_flow_error_set(error, EINVAL,
2157 RTE_FLOW_ERROR_TYPE_ITEM,
2159 "search or limit is not supported.");
2163 if (raw_spec->offset < 0) {
2164 rte_flow_error_set(error, EINVAL,
2165 RTE_FLOW_ERROR_TYPE_ITEM,
2167 "Offset should be non-negative.");
2174 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2175 struct i40e_fdir_flex_pit *flex_pit,
2176 enum i40e_flxpld_layer_idx layer_idx,
2181 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2182 /* Check if the configuration is conflicted */
2183 if (pf->fdir.flex_pit_flag[layer_idx] &&
2184 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2185 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2186 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2189 /* Check if the configuration exists. */
2190 if (pf->fdir.flex_pit_flag[layer_idx] &&
2191 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2192 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2193 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2196 pf->fdir.flex_set[field_idx].src_offset =
2197 flex_pit->src_offset;
2198 pf->fdir.flex_set[field_idx].size =
2200 pf->fdir.flex_set[field_idx].dst_offset =
2201 flex_pit->dst_offset;
2207 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2208 enum i40e_filter_pctype pctype,
2211 struct i40e_fdir_flex_mask flex_mask;
2213 uint8_t i, nb_bitmask = 0;
2215 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2216 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2217 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2219 flex_mask.word_mask |=
2220 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2221 if (mask_tmp != UINT16_MAX) {
2222 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2223 flex_mask.bitmask[nb_bitmask].offset =
2224 i / sizeof(uint16_t);
2226 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2231 flex_mask.nb_bitmask = nb_bitmask;
2233 if (pf->fdir.flex_mask_flag[pctype] &&
2234 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2235 sizeof(struct i40e_fdir_flex_mask))))
2237 else if (pf->fdir.flex_mask_flag[pctype] &&
2238 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2239 sizeof(struct i40e_fdir_flex_mask))))
2242 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2243 sizeof(struct i40e_fdir_flex_mask));
2248 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2249 enum i40e_flxpld_layer_idx layer_idx,
2252 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2253 uint32_t flx_pit, flx_ort;
2255 uint16_t min_next_off = 0; /* in words */
2259 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2260 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2261 (layer_idx * I40E_MAX_FLXPLD_FIED);
2262 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2266 for (i = 0; i < raw_id; i++) {
2267 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2268 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2269 pf->fdir.flex_set[field_idx].size,
2270 pf->fdir.flex_set[field_idx].dst_offset);
2272 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2273 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2274 pf->fdir.flex_set[field_idx].size;
2277 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2278 /* set the non-used register obeying register's constrain */
2279 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2280 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2281 NONUSE_FLX_PIT_DEST_OFF);
2282 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2286 pf->fdir.flex_pit_flag[layer_idx] = 1;
2290 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2291 enum i40e_filter_pctype pctype)
2293 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2294 struct i40e_fdir_flex_mask *flex_mask;
2295 uint32_t flxinset, fd_mask;
2299 flex_mask = &pf->fdir.flex_mask[pctype];
2300 flxinset = (flex_mask->word_mask <<
2301 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2302 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2303 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2305 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2306 fd_mask = (flex_mask->bitmask[i].mask <<
2307 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2308 I40E_PRTQF_FD_MSK_MASK_MASK;
2309 fd_mask |= ((flex_mask->bitmask[i].offset +
2310 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2311 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2312 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2313 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2316 pf->fdir.flex_mask_flag[pctype] = 1;
2320 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2321 enum i40e_filter_pctype pctype,
2324 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2325 uint64_t inset_reg = 0;
2326 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2329 /* Check if the input set is valid */
2330 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2332 PMD_DRV_LOG(ERR, "Invalid input set");
2336 /* Check if the configuration is conflicted */
2337 if (pf->fdir.inset_flag[pctype] &&
2338 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2341 if (pf->fdir.inset_flag[pctype] &&
2342 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2345 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2346 I40E_INSET_MASK_NUM_REG);
2350 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2352 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2353 (uint32_t)(inset_reg & UINT32_MAX));
2354 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2355 (uint32_t)((inset_reg >>
2356 I40E_32_BIT_WIDTH) & UINT32_MAX));
2358 for (i = 0; i < num; i++)
2359 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2362 /*clear unused mask registers of the pctype */
2363 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2364 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2365 I40E_WRITE_FLUSH(hw);
2367 pf->fdir.input_set[pctype] = input_set;
2368 pf->fdir.inset_flag[pctype] = 1;
2373 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2374 enum rte_flow_item_type item_type,
2375 struct i40e_fdir_filter_conf *filter)
2377 struct i40e_customized_pctype *cus_pctype = NULL;
2379 switch (item_type) {
2380 case RTE_FLOW_ITEM_TYPE_GTPC:
2381 cus_pctype = i40e_find_customized_pctype(pf,
2382 I40E_CUSTOMIZED_GTPC);
2384 case RTE_FLOW_ITEM_TYPE_GTPU:
2385 if (!filter->input.flow_ext.inner_ip)
2386 cus_pctype = i40e_find_customized_pctype(pf,
2387 I40E_CUSTOMIZED_GTPU);
2388 else if (filter->input.flow_ext.iip_type ==
2389 I40E_FDIR_IPTYPE_IPV4)
2390 cus_pctype = i40e_find_customized_pctype(pf,
2391 I40E_CUSTOMIZED_GTPU_IPV4);
2392 else if (filter->input.flow_ext.iip_type ==
2393 I40E_FDIR_IPTYPE_IPV6)
2394 cus_pctype = i40e_find_customized_pctype(pf,
2395 I40E_CUSTOMIZED_GTPU_IPV6);
2398 PMD_DRV_LOG(ERR, "Unsupported item type");
2403 return cus_pctype->pctype;
2405 return I40E_FILTER_PCTYPE_INVALID;
2408 /* 1. Last in item should be NULL as range is not supported.
2409 * 2. Supported patterns: refer to array i40e_supported_patterns.
2410 * 3. Default supported flow type and input set: refer to array
2411 * valid_fdir_inset_table in i40e_ethdev.c.
2412 * 4. Mask of fields which need to be matched should be
2414 * 5. Mask of fields which needn't to be matched should be
2416 * 6. GTP profile supports GTPv1 only.
2417 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2420 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2421 const struct rte_flow_item *pattern,
2422 struct rte_flow_error *error,
2423 struct i40e_fdir_filter_conf *filter)
2425 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2426 const struct rte_flow_item *item = pattern;
2427 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2428 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2429 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2430 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2431 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2432 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2433 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2434 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2435 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2436 const struct rte_flow_item_vf *vf_spec;
2439 uint64_t input_set = I40E_INSET_NONE;
2441 enum rte_flow_item_type item_type;
2442 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2443 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2445 uint8_t ipv6_addr_mask[16] = {
2446 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2447 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2448 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2450 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2451 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2452 struct i40e_fdir_flex_pit flex_pit;
2453 uint8_t next_dst_off = 0;
2454 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2456 bool cfg_flex_pit = true;
2457 bool cfg_flex_msk = true;
2458 uint16_t outer_tpid;
2459 uint16_t ether_type;
2460 uint32_t vtc_flow_cpu;
2461 bool outer_ip = true;
2464 memset(off_arr, 0, sizeof(off_arr));
2465 memset(len_arr, 0, sizeof(len_arr));
2466 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2467 outer_tpid = i40e_get_outer_vlan(dev);
2468 filter->input.flow_ext.customized_pctype = false;
2469 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2471 rte_flow_error_set(error, EINVAL,
2472 RTE_FLOW_ERROR_TYPE_ITEM,
2474 "Not support range");
2477 item_type = item->type;
2478 switch (item_type) {
2479 case RTE_FLOW_ITEM_TYPE_ETH:
2480 eth_spec = (const struct rte_flow_item_eth *)item->spec;
2481 eth_mask = (const struct rte_flow_item_eth *)item->mask;
2483 if (eth_spec && eth_mask) {
2484 if (!is_zero_ether_addr(ð_mask->src) ||
2485 !is_zero_ether_addr(ð_mask->dst)) {
2486 rte_flow_error_set(error, EINVAL,
2487 RTE_FLOW_ERROR_TYPE_ITEM,
2489 "Invalid MAC_addr mask.");
2493 if ((eth_mask->type & UINT16_MAX) ==
2495 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2496 filter->input.flow.l2_flow.ether_type =
2500 ether_type = rte_be_to_cpu_16(eth_spec->type);
2501 if (ether_type == ETHER_TYPE_IPv4 ||
2502 ether_type == ETHER_TYPE_IPv6 ||
2503 ether_type == ETHER_TYPE_ARP ||
2504 ether_type == outer_tpid) {
2505 rte_flow_error_set(error, EINVAL,
2506 RTE_FLOW_ERROR_TYPE_ITEM,
2508 "Unsupported ether_type.");
2513 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2514 layer_idx = I40E_FLXPLD_L2_IDX;
2517 case RTE_FLOW_ITEM_TYPE_VLAN:
2519 (const struct rte_flow_item_vlan *)item->spec;
2521 (const struct rte_flow_item_vlan *)item->mask;
2522 if (vlan_spec && vlan_mask) {
2523 if (vlan_mask->tci ==
2524 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2525 input_set |= I40E_INSET_VLAN_INNER;
2526 filter->input.flow_ext.vlan_tci =
2531 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2532 layer_idx = I40E_FLXPLD_L2_IDX;
2535 case RTE_FLOW_ITEM_TYPE_IPV4:
2536 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2538 (const struct rte_flow_item_ipv4 *)item->spec;
2540 (const struct rte_flow_item_ipv4 *)item->mask;
2541 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2542 layer_idx = I40E_FLXPLD_L3_IDX;
2544 if (ipv4_spec && ipv4_mask && outer_ip) {
2545 /* Check IPv4 mask and update input set */
2546 if (ipv4_mask->hdr.version_ihl ||
2547 ipv4_mask->hdr.total_length ||
2548 ipv4_mask->hdr.packet_id ||
2549 ipv4_mask->hdr.fragment_offset ||
2550 ipv4_mask->hdr.hdr_checksum) {
2551 rte_flow_error_set(error, EINVAL,
2552 RTE_FLOW_ERROR_TYPE_ITEM,
2554 "Invalid IPv4 mask.");
2558 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2559 input_set |= I40E_INSET_IPV4_SRC;
2560 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2561 input_set |= I40E_INSET_IPV4_DST;
2562 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2563 input_set |= I40E_INSET_IPV4_TOS;
2564 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2565 input_set |= I40E_INSET_IPV4_TTL;
2566 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2567 input_set |= I40E_INSET_IPV4_PROTO;
2569 /* Check if it is fragment. */
2570 frag_off = ipv4_spec->hdr.fragment_offset;
2571 frag_off = rte_be_to_cpu_16(frag_off);
2572 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2573 frag_off & IPV4_HDR_MF_FLAG)
2574 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2576 /* Get the filter info */
2577 filter->input.flow.ip4_flow.proto =
2578 ipv4_spec->hdr.next_proto_id;
2579 filter->input.flow.ip4_flow.tos =
2580 ipv4_spec->hdr.type_of_service;
2581 filter->input.flow.ip4_flow.ttl =
2582 ipv4_spec->hdr.time_to_live;
2583 filter->input.flow.ip4_flow.src_ip =
2584 ipv4_spec->hdr.src_addr;
2585 filter->input.flow.ip4_flow.dst_ip =
2586 ipv4_spec->hdr.dst_addr;
2587 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2588 filter->input.flow_ext.inner_ip = true;
2589 filter->input.flow_ext.iip_type =
2590 I40E_FDIR_IPTYPE_IPV4;
2591 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2592 rte_flow_error_set(error, EINVAL,
2593 RTE_FLOW_ERROR_TYPE_ITEM,
2595 "Invalid inner IPv4 mask.");
2603 case RTE_FLOW_ITEM_TYPE_IPV6:
2604 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2606 (const struct rte_flow_item_ipv6 *)item->spec;
2608 (const struct rte_flow_item_ipv6 *)item->mask;
2609 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2610 layer_idx = I40E_FLXPLD_L3_IDX;
2612 if (ipv6_spec && ipv6_mask && outer_ip) {
2613 /* Check IPv6 mask and update input set */
2614 if (ipv6_mask->hdr.payload_len) {
2615 rte_flow_error_set(error, EINVAL,
2616 RTE_FLOW_ERROR_TYPE_ITEM,
2618 "Invalid IPv6 mask");
2622 if (!memcmp(ipv6_mask->hdr.src_addr,
2624 RTE_DIM(ipv6_mask->hdr.src_addr)))
2625 input_set |= I40E_INSET_IPV6_SRC;
2626 if (!memcmp(ipv6_mask->hdr.dst_addr,
2628 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2629 input_set |= I40E_INSET_IPV6_DST;
2631 if ((ipv6_mask->hdr.vtc_flow &
2632 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2633 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2634 input_set |= I40E_INSET_IPV6_TC;
2635 if (ipv6_mask->hdr.proto == UINT8_MAX)
2636 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2637 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2638 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2640 /* Get filter info */
2642 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2643 filter->input.flow.ipv6_flow.tc =
2644 (uint8_t)(vtc_flow_cpu >>
2645 I40E_FDIR_IPv6_TC_OFFSET);
2646 filter->input.flow.ipv6_flow.proto =
2647 ipv6_spec->hdr.proto;
2648 filter->input.flow.ipv6_flow.hop_limits =
2649 ipv6_spec->hdr.hop_limits;
2651 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2652 ipv6_spec->hdr.src_addr, 16);
2653 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2654 ipv6_spec->hdr.dst_addr, 16);
2656 /* Check if it is fragment. */
2657 if (ipv6_spec->hdr.proto ==
2658 I40E_IPV6_FRAG_HEADER)
2659 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2660 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2661 filter->input.flow_ext.inner_ip = true;
2662 filter->input.flow_ext.iip_type =
2663 I40E_FDIR_IPTYPE_IPV6;
2664 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2665 rte_flow_error_set(error, EINVAL,
2666 RTE_FLOW_ERROR_TYPE_ITEM,
2668 "Invalid inner IPv6 mask");
2675 case RTE_FLOW_ITEM_TYPE_TCP:
2676 tcp_spec = (const struct rte_flow_item_tcp *)item->spec;
2677 tcp_mask = (const struct rte_flow_item_tcp *)item->mask;
2679 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2681 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2682 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2684 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2685 if (tcp_spec && tcp_mask) {
2686 /* Check TCP mask and update input set */
2687 if (tcp_mask->hdr.sent_seq ||
2688 tcp_mask->hdr.recv_ack ||
2689 tcp_mask->hdr.data_off ||
2690 tcp_mask->hdr.tcp_flags ||
2691 tcp_mask->hdr.rx_win ||
2692 tcp_mask->hdr.cksum ||
2693 tcp_mask->hdr.tcp_urp) {
2694 rte_flow_error_set(error, EINVAL,
2695 RTE_FLOW_ERROR_TYPE_ITEM,
2697 "Invalid TCP mask");
2701 if (tcp_mask->hdr.src_port == UINT16_MAX)
2702 input_set |= I40E_INSET_SRC_PORT;
2703 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2704 input_set |= I40E_INSET_DST_PORT;
2706 /* Get filter info */
2707 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2708 filter->input.flow.tcp4_flow.src_port =
2709 tcp_spec->hdr.src_port;
2710 filter->input.flow.tcp4_flow.dst_port =
2711 tcp_spec->hdr.dst_port;
2712 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2713 filter->input.flow.tcp6_flow.src_port =
2714 tcp_spec->hdr.src_port;
2715 filter->input.flow.tcp6_flow.dst_port =
2716 tcp_spec->hdr.dst_port;
2720 layer_idx = I40E_FLXPLD_L4_IDX;
2723 case RTE_FLOW_ITEM_TYPE_UDP:
2724 udp_spec = (const struct rte_flow_item_udp *)item->spec;
2725 udp_mask = (const struct rte_flow_item_udp *)item->mask;
2727 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2729 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2730 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2732 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2734 if (udp_spec && udp_mask) {
2735 /* Check UDP mask and update input set*/
2736 if (udp_mask->hdr.dgram_len ||
2737 udp_mask->hdr.dgram_cksum) {
2738 rte_flow_error_set(error, EINVAL,
2739 RTE_FLOW_ERROR_TYPE_ITEM,
2741 "Invalid UDP mask");
2745 if (udp_mask->hdr.src_port == UINT16_MAX)
2746 input_set |= I40E_INSET_SRC_PORT;
2747 if (udp_mask->hdr.dst_port == UINT16_MAX)
2748 input_set |= I40E_INSET_DST_PORT;
2750 /* Get filter info */
2751 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2752 filter->input.flow.udp4_flow.src_port =
2753 udp_spec->hdr.src_port;
2754 filter->input.flow.udp4_flow.dst_port =
2755 udp_spec->hdr.dst_port;
2756 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2757 filter->input.flow.udp6_flow.src_port =
2758 udp_spec->hdr.src_port;
2759 filter->input.flow.udp6_flow.dst_port =
2760 udp_spec->hdr.dst_port;
2764 layer_idx = I40E_FLXPLD_L4_IDX;
2767 case RTE_FLOW_ITEM_TYPE_GTPC:
2768 case RTE_FLOW_ITEM_TYPE_GTPU:
2769 if (!pf->gtp_support) {
2770 rte_flow_error_set(error, EINVAL,
2771 RTE_FLOW_ERROR_TYPE_ITEM,
2773 "Unsupported protocol");
2777 gtp_spec = (const struct rte_flow_item_gtp *)item->spec;
2778 gtp_mask = (const struct rte_flow_item_gtp *)item->mask;
2780 if (gtp_spec && gtp_mask) {
2781 if (gtp_mask->v_pt_rsv_flags ||
2782 gtp_mask->msg_type ||
2783 gtp_mask->msg_len ||
2784 gtp_mask->teid != UINT32_MAX) {
2785 rte_flow_error_set(error, EINVAL,
2786 RTE_FLOW_ERROR_TYPE_ITEM,
2788 "Invalid GTP mask");
2792 filter->input.flow.gtp_flow.teid =
2794 filter->input.flow_ext.customized_pctype = true;
2795 cus_proto = item_type;
2798 case RTE_FLOW_ITEM_TYPE_SCTP:
2800 (const struct rte_flow_item_sctp *)item->spec;
2802 (const struct rte_flow_item_sctp *)item->mask;
2804 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2806 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2807 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2809 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2811 if (sctp_spec && sctp_mask) {
2812 /* Check SCTP mask and update input set */
2813 if (sctp_mask->hdr.cksum) {
2814 rte_flow_error_set(error, EINVAL,
2815 RTE_FLOW_ERROR_TYPE_ITEM,
2817 "Invalid UDP mask");
2821 if (sctp_mask->hdr.src_port == UINT16_MAX)
2822 input_set |= I40E_INSET_SRC_PORT;
2823 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2824 input_set |= I40E_INSET_DST_PORT;
2825 if (sctp_mask->hdr.tag == UINT32_MAX)
2826 input_set |= I40E_INSET_SCTP_VT;
2828 /* Get filter info */
2829 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2830 filter->input.flow.sctp4_flow.src_port =
2831 sctp_spec->hdr.src_port;
2832 filter->input.flow.sctp4_flow.dst_port =
2833 sctp_spec->hdr.dst_port;
2834 filter->input.flow.sctp4_flow.verify_tag
2835 = sctp_spec->hdr.tag;
2836 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2837 filter->input.flow.sctp6_flow.src_port =
2838 sctp_spec->hdr.src_port;
2839 filter->input.flow.sctp6_flow.dst_port =
2840 sctp_spec->hdr.dst_port;
2841 filter->input.flow.sctp6_flow.verify_tag
2842 = sctp_spec->hdr.tag;
2846 layer_idx = I40E_FLXPLD_L4_IDX;
2849 case RTE_FLOW_ITEM_TYPE_RAW:
2850 raw_spec = (const struct rte_flow_item_raw *)item->spec;
2851 raw_mask = (const struct rte_flow_item_raw *)item->mask;
2853 if (!raw_spec || !raw_mask) {
2854 rte_flow_error_set(error, EINVAL,
2855 RTE_FLOW_ERROR_TYPE_ITEM,
2857 "NULL RAW spec/mask");
2861 ret = i40e_flow_check_raw_item(item, raw_spec, error);
2865 off_arr[raw_id] = raw_spec->offset;
2866 len_arr[raw_id] = raw_spec->length;
2869 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2871 raw_spec->length / sizeof(uint16_t);
2872 flex_pit.dst_offset =
2873 next_dst_off / sizeof(uint16_t);
2875 for (i = 0; i <= raw_id; i++) {
2877 flex_pit.src_offset +=
2881 flex_pit.src_offset +=
2882 (off_arr[i] + len_arr[i]) /
2884 flex_size += len_arr[i];
2886 if (((flex_pit.src_offset + flex_pit.size) >=
2887 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2888 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2889 rte_flow_error_set(error, EINVAL,
2890 RTE_FLOW_ERROR_TYPE_ITEM,
2892 "Exceeds maxmial payload limit.");
2896 /* Store flex pit to SW */
2897 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2900 rte_flow_error_set(error, EINVAL,
2901 RTE_FLOW_ERROR_TYPE_ITEM,
2903 "Conflict with the first flexible rule.");
2906 cfg_flex_pit = false;
2908 for (i = 0; i < raw_spec->length; i++) {
2909 j = i + next_dst_off;
2910 filter->input.flow_ext.flexbytes[j] =
2911 raw_spec->pattern[i];
2912 flex_mask[j] = raw_mask->pattern[i];
2915 next_dst_off += raw_spec->length;
2918 case RTE_FLOW_ITEM_TYPE_VF:
2919 vf_spec = (const struct rte_flow_item_vf *)item->spec;
2920 filter->input.flow_ext.is_vf = 1;
2921 filter->input.flow_ext.dst_id = vf_spec->id;
2922 if (filter->input.flow_ext.is_vf &&
2923 filter->input.flow_ext.dst_id >= pf->vf_num) {
2924 rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ITEM,
2927 "Invalid VF ID for FDIR.");
2936 /* Get customized pctype value */
2937 if (filter->input.flow_ext.customized_pctype) {
2938 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2939 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2940 rte_flow_error_set(error, EINVAL,
2941 RTE_FLOW_ERROR_TYPE_ITEM,
2943 "Unsupported pctype");
2948 /* If customized pctype is not used, set fdir configuration.*/
2949 if (!filter->input.flow_ext.customized_pctype) {
2950 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2952 rte_flow_error_set(error, EINVAL,
2953 RTE_FLOW_ERROR_TYPE_ITEM, item,
2954 "Conflict with the first rule's input set.");
2956 } else if (ret == -EINVAL) {
2957 rte_flow_error_set(error, EINVAL,
2958 RTE_FLOW_ERROR_TYPE_ITEM, item,
2959 "Invalid pattern mask.");
2963 /* Store flex mask to SW */
2964 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2966 rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ITEM,
2969 "Exceed maximal number of bitmasks");
2971 } else if (ret == -2) {
2972 rte_flow_error_set(error, EINVAL,
2973 RTE_FLOW_ERROR_TYPE_ITEM,
2975 "Conflict with the first flexible rule");
2978 cfg_flex_msk = false;
2981 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2984 i40e_flow_set_fdir_flex_msk(pf, pctype);
2987 filter->input.pctype = pctype;
2992 /* Parse to get the action info of a FDIR filter.
2993 * FDIR action supports QUEUE or (QUEUE + MARK).
2996 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2997 const struct rte_flow_action *actions,
2998 struct rte_flow_error *error,
2999 struct i40e_fdir_filter_conf *filter)
3001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3002 const struct rte_flow_action *act;
3003 const struct rte_flow_action_queue *act_q;
3004 const struct rte_flow_action_mark *mark_spec;
3007 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3008 NEXT_ITEM_OF_ACTION(act, actions, index);
3009 switch (act->type) {
3010 case RTE_FLOW_ACTION_TYPE_QUEUE:
3011 act_q = (const struct rte_flow_action_queue *)act->conf;
3012 filter->action.rx_queue = act_q->index;
3013 if ((!filter->input.flow_ext.is_vf &&
3014 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3015 (filter->input.flow_ext.is_vf &&
3016 filter->action.rx_queue >= pf->vf_nb_qps)) {
3017 rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION, act,
3019 "Invalid queue ID for FDIR.");
3022 filter->action.behavior = I40E_FDIR_ACCEPT;
3024 case RTE_FLOW_ACTION_TYPE_DROP:
3025 filter->action.behavior = I40E_FDIR_REJECT;
3027 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3028 filter->action.behavior = I40E_FDIR_PASSTHRU;
3031 rte_flow_error_set(error, EINVAL,
3032 RTE_FLOW_ERROR_TYPE_ACTION, act,
3037 /* Check if the next non-void item is MARK or FLAG or END. */
3039 NEXT_ITEM_OF_ACTION(act, actions, index);
3040 switch (act->type) {
3041 case RTE_FLOW_ACTION_TYPE_MARK:
3042 mark_spec = (const struct rte_flow_action_mark *)act->conf;
3043 filter->action.report_status = I40E_FDIR_REPORT_ID;
3044 filter->soft_id = mark_spec->id;
3046 case RTE_FLOW_ACTION_TYPE_FLAG:
3047 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3049 case RTE_FLOW_ACTION_TYPE_END:
3052 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3053 act, "Invalid action.");
3057 /* Check if the next non-void item is END */
3059 NEXT_ITEM_OF_ACTION(act, actions, index);
3060 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3061 rte_flow_error_set(error, EINVAL,
3062 RTE_FLOW_ERROR_TYPE_ACTION,
3063 act, "Invalid action.");
3071 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3072 const struct rte_flow_attr *attr,
3073 const struct rte_flow_item pattern[],
3074 const struct rte_flow_action actions[],
3075 struct rte_flow_error *error,
3076 union i40e_filter_t *filter)
3078 struct i40e_fdir_filter_conf *fdir_filter =
3079 &filter->fdir_filter;
3082 ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3086 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3090 ret = i40e_flow_parse_attr(attr, error);
3094 cons_filter_type = RTE_ETH_FILTER_FDIR;
3096 if (dev->data->dev_conf.fdir_conf.mode !=
3097 RTE_FDIR_MODE_PERFECT) {
3098 rte_flow_error_set(error, ENOTSUP,
3099 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3101 "Check the mode in fdir_conf.");
3108 /* Parse to get the action info of a tunnel filter
3109 * Tunnel action only supports PF, VF and QUEUE.
3112 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3113 const struct rte_flow_action *actions,
3114 struct rte_flow_error *error,
3115 struct i40e_tunnel_filter_conf *filter)
3117 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3118 const struct rte_flow_action *act;
3119 const struct rte_flow_action_queue *act_q;
3120 const struct rte_flow_action_vf *act_vf;
3123 /* Check if the first non-void action is PF or VF. */
3124 NEXT_ITEM_OF_ACTION(act, actions, index);
3125 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3126 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3127 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3128 act, "Not supported action.");
3132 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3133 act_vf = (const struct rte_flow_action_vf *)act->conf;
3134 filter->vf_id = act_vf->id;
3135 filter->is_to_vf = 1;
3136 if (filter->vf_id >= pf->vf_num) {
3137 rte_flow_error_set(error, EINVAL,
3138 RTE_FLOW_ERROR_TYPE_ACTION,
3139 act, "Invalid VF ID for tunnel filter");
3144 /* Check if the next non-void item is QUEUE */
3146 NEXT_ITEM_OF_ACTION(act, actions, index);
3147 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3148 act_q = (const struct rte_flow_action_queue *)act->conf;
3149 filter->queue_id = act_q->index;
3150 if ((!filter->is_to_vf) &&
3151 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3152 rte_flow_error_set(error, EINVAL,
3153 RTE_FLOW_ERROR_TYPE_ACTION,
3154 act, "Invalid queue ID for tunnel filter");
3156 } else if (filter->is_to_vf &&
3157 (filter->queue_id >= pf->vf_nb_qps)) {
3158 rte_flow_error_set(error, EINVAL,
3159 RTE_FLOW_ERROR_TYPE_ACTION,
3160 act, "Invalid queue ID for tunnel filter");
3165 /* Check if the next non-void item is END */
3167 NEXT_ITEM_OF_ACTION(act, actions, index);
3168 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3169 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3170 act, "Not supported action.");
3177 static uint16_t i40e_supported_tunnel_filter_types[] = {
3178 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3179 ETH_TUNNEL_FILTER_IVLAN,
3180 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3181 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3182 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3183 ETH_TUNNEL_FILTER_IMAC,
3184 ETH_TUNNEL_FILTER_IMAC,
3188 i40e_check_tunnel_filter_type(uint8_t filter_type)
3192 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3193 if (filter_type == i40e_supported_tunnel_filter_types[i])
3200 /* 1. Last in item should be NULL as range is not supported.
3201 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3202 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3203 * 3. Mask of fields which need to be matched should be
3205 * 4. Mask of fields which needn't to be matched should be
3209 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3210 const struct rte_flow_item *pattern,
3211 struct rte_flow_error *error,
3212 struct i40e_tunnel_filter_conf *filter)
3214 const struct rte_flow_item *item = pattern;
3215 const struct rte_flow_item_eth *eth_spec;
3216 const struct rte_flow_item_eth *eth_mask;
3217 const struct rte_flow_item_vxlan *vxlan_spec;
3218 const struct rte_flow_item_vxlan *vxlan_mask;
3219 const struct rte_flow_item_vlan *vlan_spec;
3220 const struct rte_flow_item_vlan *vlan_mask;
3221 uint8_t filter_type = 0;
3222 bool is_vni_masked = 0;
3223 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3224 enum rte_flow_item_type item_type;
3225 bool vxlan_flag = 0;
3226 uint32_t tenant_id_be = 0;
3229 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3231 rte_flow_error_set(error, EINVAL,
3232 RTE_FLOW_ERROR_TYPE_ITEM,
3234 "Not support range");
3237 item_type = item->type;
3238 switch (item_type) {
3239 case RTE_FLOW_ITEM_TYPE_ETH:
3240 eth_spec = (const struct rte_flow_item_eth *)item->spec;
3241 eth_mask = (const struct rte_flow_item_eth *)item->mask;
3243 /* Check if ETH item is used for place holder.
3244 * If yes, both spec and mask should be NULL.
3245 * If no, both spec and mask shouldn't be NULL.
3247 if ((!eth_spec && eth_mask) ||
3248 (eth_spec && !eth_mask)) {
3249 rte_flow_error_set(error, EINVAL,
3250 RTE_FLOW_ERROR_TYPE_ITEM,
3252 "Invalid ether spec/mask");
3256 if (eth_spec && eth_mask) {
3257 /* DST address of inner MAC shouldn't be masked.
3258 * SRC address of Inner MAC should be masked.
3260 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3261 !is_zero_ether_addr(ð_mask->src) ||
3263 rte_flow_error_set(error, EINVAL,
3264 RTE_FLOW_ERROR_TYPE_ITEM,
3266 "Invalid ether spec/mask");
3271 rte_memcpy(&filter->outer_mac,
3274 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3276 rte_memcpy(&filter->inner_mac,
3279 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3283 case RTE_FLOW_ITEM_TYPE_VLAN:
3285 (const struct rte_flow_item_vlan *)item->spec;
3287 (const struct rte_flow_item_vlan *)item->mask;
3288 if (!(vlan_spec && vlan_mask)) {
3289 rte_flow_error_set(error, EINVAL,
3290 RTE_FLOW_ERROR_TYPE_ITEM,
3292 "Invalid vlan item");
3296 if (vlan_spec && vlan_mask) {
3297 if (vlan_mask->tci ==
3298 rte_cpu_to_be_16(I40E_TCI_MASK))
3299 filter->inner_vlan =
3300 rte_be_to_cpu_16(vlan_spec->tci) &
3302 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3305 case RTE_FLOW_ITEM_TYPE_IPV4:
3306 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3307 /* IPv4 is used to describe protocol,
3308 * spec and mask should be NULL.
3310 if (item->spec || item->mask) {
3311 rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ITEM,
3314 "Invalid IPv4 item");
3318 case RTE_FLOW_ITEM_TYPE_IPV6:
3319 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3320 /* IPv6 is used to describe protocol,
3321 * spec and mask should be NULL.
3323 if (item->spec || item->mask) {
3324 rte_flow_error_set(error, EINVAL,
3325 RTE_FLOW_ERROR_TYPE_ITEM,
3327 "Invalid IPv6 item");
3331 case RTE_FLOW_ITEM_TYPE_UDP:
3332 /* UDP is used to describe protocol,
3333 * spec and mask should be NULL.
3335 if (item->spec || item->mask) {
3336 rte_flow_error_set(error, EINVAL,
3337 RTE_FLOW_ERROR_TYPE_ITEM,
3339 "Invalid UDP item");
3343 case RTE_FLOW_ITEM_TYPE_VXLAN:
3345 (const struct rte_flow_item_vxlan *)item->spec;
3347 (const struct rte_flow_item_vxlan *)item->mask;
3348 /* Check if VXLAN item is used to describe protocol.
3349 * If yes, both spec and mask should be NULL.
3350 * If no, both spec and mask shouldn't be NULL.
3352 if ((!vxlan_spec && vxlan_mask) ||
3353 (vxlan_spec && !vxlan_mask)) {
3354 rte_flow_error_set(error, EINVAL,
3355 RTE_FLOW_ERROR_TYPE_ITEM,
3357 "Invalid VXLAN item");
3361 /* Check if VNI is masked. */
3362 if (vxlan_spec && vxlan_mask) {
3364 !!memcmp(vxlan_mask->vni, vni_mask,
3366 if (is_vni_masked) {
3367 rte_flow_error_set(error, EINVAL,
3368 RTE_FLOW_ERROR_TYPE_ITEM,
3370 "Invalid VNI mask");
3374 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3375 vxlan_spec->vni, 3);
3377 rte_be_to_cpu_32(tenant_id_be);
3378 filter_type |= ETH_TUNNEL_FILTER_TENID;
3388 ret = i40e_check_tunnel_filter_type(filter_type);
3390 rte_flow_error_set(error, EINVAL,
3391 RTE_FLOW_ERROR_TYPE_ITEM,
3393 "Invalid filter type");
3396 filter->filter_type = filter_type;
3398 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3404 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3405 const struct rte_flow_attr *attr,
3406 const struct rte_flow_item pattern[],
3407 const struct rte_flow_action actions[],
3408 struct rte_flow_error *error,
3409 union i40e_filter_t *filter)
3411 struct i40e_tunnel_filter_conf *tunnel_filter =
3412 &filter->consistent_tunnel_filter;
3415 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3416 error, tunnel_filter);
3420 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3424 ret = i40e_flow_parse_attr(attr, error);
3428 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3433 /* 1. Last in item should be NULL as range is not supported.
3434 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3435 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3436 * 3. Mask of fields which need to be matched should be
3438 * 4. Mask of fields which needn't to be matched should be
3442 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3443 const struct rte_flow_item *pattern,
3444 struct rte_flow_error *error,
3445 struct i40e_tunnel_filter_conf *filter)
3447 const struct rte_flow_item *item = pattern;
3448 const struct rte_flow_item_eth *eth_spec;
3449 const struct rte_flow_item_eth *eth_mask;
3450 const struct rte_flow_item_nvgre *nvgre_spec;
3451 const struct rte_flow_item_nvgre *nvgre_mask;
3452 const struct rte_flow_item_vlan *vlan_spec;
3453 const struct rte_flow_item_vlan *vlan_mask;
3454 enum rte_flow_item_type item_type;
3455 uint8_t filter_type = 0;
3456 bool is_tni_masked = 0;
3457 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3458 bool nvgre_flag = 0;
3459 uint32_t tenant_id_be = 0;
3462 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3464 rte_flow_error_set(error, EINVAL,
3465 RTE_FLOW_ERROR_TYPE_ITEM,
3467 "Not support range");
3470 item_type = item->type;
3471 switch (item_type) {
3472 case RTE_FLOW_ITEM_TYPE_ETH:
3473 eth_spec = (const struct rte_flow_item_eth *)item->spec;
3474 eth_mask = (const struct rte_flow_item_eth *)item->mask;
3476 /* Check if ETH item is used for place holder.
3477 * If yes, both spec and mask should be NULL.
3478 * If no, both spec and mask shouldn't be NULL.
3480 if ((!eth_spec && eth_mask) ||
3481 (eth_spec && !eth_mask)) {
3482 rte_flow_error_set(error, EINVAL,
3483 RTE_FLOW_ERROR_TYPE_ITEM,
3485 "Invalid ether spec/mask");
3489 if (eth_spec && eth_mask) {
3490 /* DST address of inner MAC shouldn't be masked.
3491 * SRC address of Inner MAC should be masked.
3493 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3494 !is_zero_ether_addr(ð_mask->src) ||
3496 rte_flow_error_set(error, EINVAL,
3497 RTE_FLOW_ERROR_TYPE_ITEM,
3499 "Invalid ether spec/mask");
3504 rte_memcpy(&filter->outer_mac,
3507 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3509 rte_memcpy(&filter->inner_mac,
3512 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3517 case RTE_FLOW_ITEM_TYPE_VLAN:
3519 (const struct rte_flow_item_vlan *)item->spec;
3521 (const struct rte_flow_item_vlan *)item->mask;
3522 if (!(vlan_spec && vlan_mask)) {
3523 rte_flow_error_set(error, EINVAL,
3524 RTE_FLOW_ERROR_TYPE_ITEM,
3526 "Invalid vlan item");
3530 if (vlan_spec && vlan_mask) {
3531 if (vlan_mask->tci ==
3532 rte_cpu_to_be_16(I40E_TCI_MASK))
3533 filter->inner_vlan =
3534 rte_be_to_cpu_16(vlan_spec->tci) &
3536 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3539 case RTE_FLOW_ITEM_TYPE_IPV4:
3540 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3541 /* IPv4 is used to describe protocol,
3542 * spec and mask should be NULL.
3544 if (item->spec || item->mask) {
3545 rte_flow_error_set(error, EINVAL,
3546 RTE_FLOW_ERROR_TYPE_ITEM,
3548 "Invalid IPv4 item");
3552 case RTE_FLOW_ITEM_TYPE_IPV6:
3553 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3554 /* IPv6 is used to describe protocol,
3555 * spec and mask should be NULL.
3557 if (item->spec || item->mask) {
3558 rte_flow_error_set(error, EINVAL,
3559 RTE_FLOW_ERROR_TYPE_ITEM,
3561 "Invalid IPv6 item");
3565 case RTE_FLOW_ITEM_TYPE_NVGRE:
3567 (const struct rte_flow_item_nvgre *)item->spec;
3569 (const struct rte_flow_item_nvgre *)item->mask;
3570 /* Check if NVGRE item is used to describe protocol.
3571 * If yes, both spec and mask should be NULL.
3572 * If no, both spec and mask shouldn't be NULL.
3574 if ((!nvgre_spec && nvgre_mask) ||
3575 (nvgre_spec && !nvgre_mask)) {
3576 rte_flow_error_set(error, EINVAL,
3577 RTE_FLOW_ERROR_TYPE_ITEM,
3579 "Invalid NVGRE item");
3583 if (nvgre_spec && nvgre_mask) {
3585 !!memcmp(nvgre_mask->tni, tni_mask,
3587 if (is_tni_masked) {
3588 rte_flow_error_set(error, EINVAL,
3589 RTE_FLOW_ERROR_TYPE_ITEM,
3591 "Invalid TNI mask");
3594 if (nvgre_mask->protocol &&
3595 nvgre_mask->protocol != 0xFFFF) {
3596 rte_flow_error_set(error, EINVAL,
3597 RTE_FLOW_ERROR_TYPE_ITEM,
3599 "Invalid NVGRE item");
3602 if (nvgre_mask->c_k_s_rsvd0_ver &&
3603 nvgre_mask->c_k_s_rsvd0_ver !=
3604 rte_cpu_to_be_16(0xFFFF)) {
3605 rte_flow_error_set(error, EINVAL,
3606 RTE_FLOW_ERROR_TYPE_ITEM,
3608 "Invalid NVGRE item");
3611 if (nvgre_spec->c_k_s_rsvd0_ver !=
3612 rte_cpu_to_be_16(0x2000) &&
3613 nvgre_mask->c_k_s_rsvd0_ver) {
3614 rte_flow_error_set(error, EINVAL,
3615 RTE_FLOW_ERROR_TYPE_ITEM,
3617 "Invalid NVGRE item");
3620 if (nvgre_mask->protocol &&
3621 nvgre_spec->protocol !=
3622 rte_cpu_to_be_16(0x6558)) {
3623 rte_flow_error_set(error, EINVAL,
3624 RTE_FLOW_ERROR_TYPE_ITEM,
3626 "Invalid NVGRE item");
3629 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3630 nvgre_spec->tni, 3);
3632 rte_be_to_cpu_32(tenant_id_be);
3633 filter_type |= ETH_TUNNEL_FILTER_TENID;
3643 ret = i40e_check_tunnel_filter_type(filter_type);
3645 rte_flow_error_set(error, EINVAL,
3646 RTE_FLOW_ERROR_TYPE_ITEM,
3648 "Invalid filter type");
3651 filter->filter_type = filter_type;
3653 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3659 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3660 const struct rte_flow_attr *attr,
3661 const struct rte_flow_item pattern[],
3662 const struct rte_flow_action actions[],
3663 struct rte_flow_error *error,
3664 union i40e_filter_t *filter)
3666 struct i40e_tunnel_filter_conf *tunnel_filter =
3667 &filter->consistent_tunnel_filter;
3670 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3671 error, tunnel_filter);
3675 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3679 ret = i40e_flow_parse_attr(attr, error);
3683 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3688 /* 1. Last in item should be NULL as range is not supported.
3689 * 2. Supported filter types: MPLS label.
3690 * 3. Mask of fields which need to be matched should be
3692 * 4. Mask of fields which needn't to be matched should be
3696 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3697 const struct rte_flow_item *pattern,
3698 struct rte_flow_error *error,
3699 struct i40e_tunnel_filter_conf *filter)
3701 const struct rte_flow_item *item = pattern;
3702 const struct rte_flow_item_mpls *mpls_spec;
3703 const struct rte_flow_item_mpls *mpls_mask;
3704 enum rte_flow_item_type item_type;
3705 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3706 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3707 uint32_t label_be = 0;
3709 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3711 rte_flow_error_set(error, EINVAL,
3712 RTE_FLOW_ERROR_TYPE_ITEM,
3714 "Not support range");
3717 item_type = item->type;
3718 switch (item_type) {
3719 case RTE_FLOW_ITEM_TYPE_ETH:
3720 if (item->spec || item->mask) {
3721 rte_flow_error_set(error, EINVAL,
3722 RTE_FLOW_ERROR_TYPE_ITEM,
3724 "Invalid ETH item");
3728 case RTE_FLOW_ITEM_TYPE_IPV4:
3729 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3730 /* IPv4 is used to describe protocol,
3731 * spec and mask should be NULL.
3733 if (item->spec || item->mask) {
3734 rte_flow_error_set(error, EINVAL,
3735 RTE_FLOW_ERROR_TYPE_ITEM,
3737 "Invalid IPv4 item");
3741 case RTE_FLOW_ITEM_TYPE_IPV6:
3742 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3743 /* IPv6 is used to describe protocol,
3744 * spec and mask should be NULL.
3746 if (item->spec || item->mask) {
3747 rte_flow_error_set(error, EINVAL,
3748 RTE_FLOW_ERROR_TYPE_ITEM,
3750 "Invalid IPv6 item");
3754 case RTE_FLOW_ITEM_TYPE_UDP:
3755 /* UDP is used to describe protocol,
3756 * spec and mask should be NULL.
3758 if (item->spec || item->mask) {
3759 rte_flow_error_set(error, EINVAL,
3760 RTE_FLOW_ERROR_TYPE_ITEM,
3762 "Invalid UDP item");
3767 case RTE_FLOW_ITEM_TYPE_GRE:
3768 /* GRE is used to describe protocol,
3769 * spec and mask should be NULL.
3771 if (item->spec || item->mask) {
3772 rte_flow_error_set(error, EINVAL,
3773 RTE_FLOW_ERROR_TYPE_ITEM,
3775 "Invalid GRE item");
3779 case RTE_FLOW_ITEM_TYPE_MPLS:
3781 (const struct rte_flow_item_mpls *)item->spec;
3783 (const struct rte_flow_item_mpls *)item->mask;
3785 if (!mpls_spec || !mpls_mask) {
3786 rte_flow_error_set(error, EINVAL,
3787 RTE_FLOW_ERROR_TYPE_ITEM,
3789 "Invalid MPLS item");
3793 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3794 rte_flow_error_set(error, EINVAL,
3795 RTE_FLOW_ERROR_TYPE_ITEM,
3797 "Invalid MPLS label mask");
3800 rte_memcpy(((uint8_t *)&label_be + 1),
3801 mpls_spec->label_tc_s, 3);
3802 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3810 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3812 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3818 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3819 const struct rte_flow_attr *attr,
3820 const struct rte_flow_item pattern[],
3821 const struct rte_flow_action actions[],
3822 struct rte_flow_error *error,
3823 union i40e_filter_t *filter)
3825 struct i40e_tunnel_filter_conf *tunnel_filter =
3826 &filter->consistent_tunnel_filter;
3829 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3830 error, tunnel_filter);
3834 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3838 ret = i40e_flow_parse_attr(attr, error);
3842 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3847 /* 1. Last in item should be NULL as range is not supported.
3848 * 2. Supported filter types: GTP TEID.
3849 * 3. Mask of fields which need to be matched should be
3851 * 4. Mask of fields which needn't to be matched should be
3853 * 5. GTP profile supports GTPv1 only.
3854 * 6. GTP-C response message ('source_port' = 2123) is not supported.
3857 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3858 const struct rte_flow_item *pattern,
3859 struct rte_flow_error *error,
3860 struct i40e_tunnel_filter_conf *filter)
3862 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3863 const struct rte_flow_item *item = pattern;
3864 const struct rte_flow_item_gtp *gtp_spec;
3865 const struct rte_flow_item_gtp *gtp_mask;
3866 enum rte_flow_item_type item_type;
3868 if (!pf->gtp_support) {
3869 rte_flow_error_set(error, EINVAL,
3870 RTE_FLOW_ERROR_TYPE_ITEM,
3872 "GTP is not supported by default.");
3876 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3878 rte_flow_error_set(error, EINVAL,
3879 RTE_FLOW_ERROR_TYPE_ITEM,
3881 "Not support range");
3884 item_type = item->type;
3885 switch (item_type) {
3886 case RTE_FLOW_ITEM_TYPE_ETH:
3887 if (item->spec || item->mask) {
3888 rte_flow_error_set(error, EINVAL,
3889 RTE_FLOW_ERROR_TYPE_ITEM,
3891 "Invalid ETH item");
3895 case RTE_FLOW_ITEM_TYPE_IPV4:
3896 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3897 /* IPv4 is used to describe protocol,
3898 * spec and mask should be NULL.
3900 if (item->spec || item->mask) {
3901 rte_flow_error_set(error, EINVAL,
3902 RTE_FLOW_ERROR_TYPE_ITEM,
3904 "Invalid IPv4 item");
3908 case RTE_FLOW_ITEM_TYPE_UDP:
3909 if (item->spec || item->mask) {
3910 rte_flow_error_set(error, EINVAL,
3911 RTE_FLOW_ERROR_TYPE_ITEM,
3913 "Invalid UDP item");
3917 case RTE_FLOW_ITEM_TYPE_GTPC:
3918 case RTE_FLOW_ITEM_TYPE_GTPU:
3920 (const struct rte_flow_item_gtp *)item->spec;
3922 (const struct rte_flow_item_gtp *)item->mask;
3924 if (!gtp_spec || !gtp_mask) {
3925 rte_flow_error_set(error, EINVAL,
3926 RTE_FLOW_ERROR_TYPE_ITEM,
3928 "Invalid GTP item");
3932 if (gtp_mask->v_pt_rsv_flags ||
3933 gtp_mask->msg_type ||
3934 gtp_mask->msg_len ||
3935 gtp_mask->teid != UINT32_MAX) {
3936 rte_flow_error_set(error, EINVAL,
3937 RTE_FLOW_ERROR_TYPE_ITEM,
3939 "Invalid GTP mask");
3943 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3944 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3945 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3946 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3948 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3960 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3961 const struct rte_flow_attr *attr,
3962 const struct rte_flow_item pattern[],
3963 const struct rte_flow_action actions[],
3964 struct rte_flow_error *error,
3965 union i40e_filter_t *filter)
3967 struct i40e_tunnel_filter_conf *tunnel_filter =
3968 &filter->consistent_tunnel_filter;
3971 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3972 error, tunnel_filter);
3976 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3980 ret = i40e_flow_parse_attr(attr, error);
3984 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3989 /* 1. Last in item should be NULL as range is not supported.
3990 * 2. Supported filter types: QINQ.
3991 * 3. Mask of fields which need to be matched should be
3993 * 4. Mask of fields which needn't to be matched should be
3997 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3998 const struct rte_flow_item *pattern,
3999 struct rte_flow_error *error,
4000 struct i40e_tunnel_filter_conf *filter)
4002 const struct rte_flow_item *item = pattern;
4003 const struct rte_flow_item_vlan *vlan_spec = NULL;
4004 const struct rte_flow_item_vlan *vlan_mask = NULL;
4005 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4006 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4007 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4008 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4010 enum rte_flow_item_type item_type;
4013 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4015 rte_flow_error_set(error, EINVAL,
4016 RTE_FLOW_ERROR_TYPE_ITEM,
4018 "Not support range");
4021 item_type = item->type;
4022 switch (item_type) {
4023 case RTE_FLOW_ITEM_TYPE_ETH:
4024 if (item->spec || item->mask) {
4025 rte_flow_error_set(error, EINVAL,
4026 RTE_FLOW_ERROR_TYPE_ITEM,
4028 "Invalid ETH item");
4032 case RTE_FLOW_ITEM_TYPE_VLAN:
4034 (const struct rte_flow_item_vlan *)item->spec;
4036 (const struct rte_flow_item_vlan *)item->mask;
4038 if (!(vlan_spec && vlan_mask)) {
4039 rte_flow_error_set(error, EINVAL,
4040 RTE_FLOW_ERROR_TYPE_ITEM,
4042 "Invalid vlan item");
4047 o_vlan_spec = vlan_spec;
4048 o_vlan_mask = vlan_mask;
4051 i_vlan_spec = vlan_spec;
4052 i_vlan_mask = vlan_mask;
4062 /* Get filter specification */
4063 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4064 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4065 (i_vlan_mask != NULL) &&
4066 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4067 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4069 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4072 rte_flow_error_set(error, EINVAL,
4073 RTE_FLOW_ERROR_TYPE_ITEM,
4075 "Invalid filter type");
4079 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4084 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4085 const struct rte_flow_attr *attr,
4086 const struct rte_flow_item pattern[],
4087 const struct rte_flow_action actions[],
4088 struct rte_flow_error *error,
4089 union i40e_filter_t *filter)
4091 struct i40e_tunnel_filter_conf *tunnel_filter =
4092 &filter->consistent_tunnel_filter;
4095 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4096 error, tunnel_filter);
4100 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4104 ret = i40e_flow_parse_attr(attr, error);
4108 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4114 * This function is used to do configuration i40e existing RSS with rte_flow.
4115 * It also enable queue region configuration using flow API for i40e.
4116 * pattern can be used indicate what parameters will be include in flow,
4117 * like user_priority or flowtype for queue region or HASH function for RSS.
4118 * Action is used to transmit parameter like queue index and HASH
4119 * function for RSS, or flowtype for queue region configuration.
4122 * Case 1: only ETH, indicate flowtype for queue region will be parsed.
4123 * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4124 * Case 3: none, indicate RSS related will be parsed in action.
4125 * Any pattern other the ETH or VLAN will be treated as invalid except END.
4126 * So, pattern choice is depened on the purpose of configuration of
4129 * action RSS will be uaed to transmit valid parameter with
4130 * struct rte_flow_action_rss for all the 3 case.
4133 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4134 const struct rte_flow_item *pattern,
4135 struct rte_flow_error *error,
4136 uint8_t *action_flag,
4137 struct i40e_queue_regions *info)
4139 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4140 const struct rte_flow_item *item = pattern;
4141 enum rte_flow_item_type item_type;
4143 if (item->type == RTE_FLOW_ITEM_TYPE_END)
4146 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4148 rte_flow_error_set(error, EINVAL,
4149 RTE_FLOW_ERROR_TYPE_ITEM,
4151 "Not support range");
4154 item_type = item->type;
4155 switch (item_type) {
4156 case RTE_FLOW_ITEM_TYPE_ETH:
4159 case RTE_FLOW_ITEM_TYPE_VLAN:
4161 (const struct rte_flow_item_vlan *)item->spec;
4163 (const struct rte_flow_item_vlan *)item->mask;
4164 if (vlan_spec && vlan_mask) {
4165 if (vlan_mask->tci ==
4166 rte_cpu_to_be_16(I40E_TCI_MASK)) {
4167 info->region[0].user_priority[0] =
4168 (vlan_spec->tci >> 13) & 0x7;
4169 info->region[0].user_priority_num = 1;
4170 info->queue_region_number = 1;
4176 rte_flow_error_set(error, EINVAL,
4177 RTE_FLOW_ERROR_TYPE_ITEM,
4179 "Not support range");
4188 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4189 const struct rte_flow_action *actions,
4190 struct rte_flow_error *error,
4191 uint8_t *action_flag,
4192 struct i40e_queue_regions *conf_info,
4193 union i40e_filter_t *filter)
4195 const struct rte_flow_action *act;
4196 const struct rte_flow_action_rss *rss;
4197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4198 struct i40e_queue_regions *info = &pf->queue_region;
4199 struct i40e_rte_flow_rss_conf *rss_config =
4201 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4202 uint16_t i, j, n, tmp;
4205 NEXT_ITEM_OF_ACTION(act, actions, index);
4206 rss = (const struct rte_flow_action_rss *)act->conf;
4209 * rss only supports forwarding,
4210 * check if the first not void action is RSS.
4212 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4213 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4214 rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ACTION,
4216 act, "Not supported action.");
4221 for (n = 0; n < 64; n++) {
4222 if (rss->rss_conf->rss_hf & (1 << n)) {
4223 conf_info->region[0].hw_flowtype[0] = n;
4224 conf_info->region[0].flowtype_num = 1;
4225 conf_info->queue_region_number = 1;
4231 for (n = 0; n < conf_info->queue_region_number; n++) {
4232 if (conf_info->region[n].user_priority_num ||
4233 conf_info->region[n].flowtype_num) {
4234 if (!((rte_is_power_of_2(rss->num)) &&
4236 PMD_DRV_LOG(ERR, "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4237 "total number of queues do not exceed the VSI allocation");
4241 if (conf_info->region[n].user_priority[n] >=
4242 I40E_MAX_USER_PRIORITY) {
4243 PMD_DRV_LOG(ERR, "the user priority max index is 7");
4247 if (conf_info->region[n].hw_flowtype[n] >=
4248 I40E_FILTER_PCTYPE_MAX) {
4249 PMD_DRV_LOG(ERR, "the hw_flowtype or PCTYPE max index is 63");
4253 if (rss_info->num < rss->num ||
4254 rss_info->queue[0] < rss->queue[0] ||
4255 (rss->queue[0] + rss->num >
4256 rss_info->num + rss_info->queue[0])) {
4257 rte_flow_error_set(error, EINVAL,
4258 RTE_FLOW_ERROR_TYPE_ACTION,
4264 for (i = 0; i < info->queue_region_number; i++) {
4265 if (info->region[i].queue_num == rss->num &&
4266 info->region[i].queue_start_index ==
4271 if (i == info->queue_region_number) {
4272 if (i > I40E_REGION_MAX_INDEX) {
4273 PMD_DRV_LOG(ERR, "the queue region max index is 7");
4277 info->region[i].queue_num =
4279 info->region[i].queue_start_index =
4281 info->region[i].region_id =
4282 info->queue_region_number;
4284 j = info->region[i].user_priority_num;
4285 tmp = conf_info->region[n].user_priority[0];
4286 if (conf_info->region[n].user_priority_num) {
4287 info->region[i].user_priority[j] = tmp;
4288 info->region[i].user_priority_num++;
4291 j = info->region[i].flowtype_num;
4292 tmp = conf_info->region[n].hw_flowtype[0];
4293 if (conf_info->region[n].flowtype_num) {
4294 info->region[i].hw_flowtype[j] = tmp;
4295 info->region[i].flowtype_num++;
4297 info->queue_region_number++;
4299 j = info->region[i].user_priority_num;
4300 tmp = conf_info->region[n].user_priority[0];
4301 if (conf_info->region[n].user_priority_num) {
4302 info->region[i].user_priority[j] = tmp;
4303 info->region[i].user_priority_num++;
4306 j = info->region[i].flowtype_num;
4307 tmp = conf_info->region[n].hw_flowtype[0];
4308 if (conf_info->region[n].flowtype_num) {
4309 info->region[i].hw_flowtype[j] = tmp;
4310 info->region[i].flowtype_num++;
4315 rss_config->queue_region_conf = TRUE;
4319 if (!rss || !rss->num) {
4320 rte_flow_error_set(error, EINVAL,
4321 RTE_FLOW_ERROR_TYPE_ACTION,
4327 for (n = 0; n < rss->num; n++) {
4328 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4329 rte_flow_error_set(error, EINVAL,
4330 RTE_FLOW_ERROR_TYPE_ACTION,
4332 "queue id > max number of queues");
4337 rss_config->rss_conf = *rss->rss_conf;
4339 rss_config->rss_conf.rss_hf =
4340 pf->adapter->flow_types_mask;
4342 for (n = 0; n < rss->num; ++n)
4343 rss_config->queue[n] = rss->queue[n];
4344 rss_config->num = rss->num;
4347 /* check if the next not void action is END */
4348 NEXT_ITEM_OF_ACTION(act, actions, index);
4349 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4350 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4351 rte_flow_error_set(error, EINVAL,
4352 RTE_FLOW_ERROR_TYPE_ACTION,
4353 act, "Not supported action.");
4356 rss_config->queue_region_conf = FALSE;
4362 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4363 const struct rte_flow_attr *attr,
4364 const struct rte_flow_item pattern[],
4365 const struct rte_flow_action actions[],
4366 union i40e_filter_t *filter,
4367 struct rte_flow_error *error)
4370 struct i40e_queue_regions info;
4371 uint8_t action_flag = 0;
4373 memset(&info, 0, sizeof(struct i40e_queue_regions));
4375 ret = i40e_flow_parse_rss_pattern(dev, pattern,
4376 error, &action_flag, &info);
4380 ret = i40e_flow_parse_rss_action(dev, actions, error,
4381 &action_flag, &info, filter);
4385 ret = i40e_flow_parse_attr(attr, error);
4389 cons_filter_type = RTE_ETH_FILTER_HASH;
4395 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4396 struct i40e_rte_flow_rss_conf *conf)
4398 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4399 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401 if (conf->queue_region_conf) {
4402 i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4403 conf->queue_region_conf = 0;
4405 i40e_config_rss_filter(pf, conf, 1);
4411 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4412 struct i40e_rte_flow_rss_conf *conf)
4414 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4419 i40e_config_rss_filter(pf, conf, 0);
4424 i40e_flow_validate(struct rte_eth_dev *dev,
4425 const struct rte_flow_attr *attr,
4426 const struct rte_flow_item pattern[],
4427 const struct rte_flow_action actions[],
4428 struct rte_flow_error *error)
4430 struct rte_flow_item *items; /* internal pattern w/o VOID items */
4431 parse_filter_t parse_filter;
4432 uint32_t item_num = 0; /* non-void item number of pattern*/
4435 int ret = I40E_NOT_SUPPORTED;
4438 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4439 NULL, "NULL pattern.");
4444 rte_flow_error_set(error, EINVAL,
4445 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4446 NULL, "NULL action.");
4451 rte_flow_error_set(error, EINVAL,
4452 RTE_FLOW_ERROR_TYPE_ATTR,
4453 NULL, "NULL attribute.");
4457 memset(&cons_filter, 0, sizeof(cons_filter));
4459 /* Get the non-void item of action */
4460 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4463 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4464 ret = i40e_parse_rss_filter(dev, attr, pattern,
4465 actions, &cons_filter, error);
4470 /* Get the non-void item number of pattern */
4471 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4472 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4478 items = rte_zmalloc("i40e_pattern",
4479 item_num * sizeof(struct rte_flow_item), 0);
4481 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4482 NULL, "No memory for PMD internal items.");
4486 i40e_pattern_skip_void_item(items, pattern);
4490 parse_filter = i40e_find_parse_filter_func(items, &i);
4491 if (!parse_filter && !flag) {
4492 rte_flow_error_set(error, EINVAL,
4493 RTE_FLOW_ERROR_TYPE_ITEM,
4494 pattern, "Unsupported pattern");
4499 ret = parse_filter(dev, attr, items, actions,
4500 error, &cons_filter);
4502 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4509 static struct rte_flow *
4510 i40e_flow_create(struct rte_eth_dev *dev,
4511 const struct rte_flow_attr *attr,
4512 const struct rte_flow_item pattern[],
4513 const struct rte_flow_action actions[],
4514 struct rte_flow_error *error)
4516 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517 struct rte_flow *flow;
4520 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4522 rte_flow_error_set(error, ENOMEM,
4523 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4524 "Failed to allocate memory");
4528 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4532 switch (cons_filter_type) {
4533 case RTE_ETH_FILTER_ETHERTYPE:
4534 ret = i40e_ethertype_filter_set(pf,
4535 &cons_filter.ethertype_filter, 1);
4538 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4539 i40e_ethertype_filter_list);
4541 case RTE_ETH_FILTER_FDIR:
4542 ret = i40e_flow_add_del_fdir_filter(dev,
4543 &cons_filter.fdir_filter, 1);
4546 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4547 i40e_fdir_filter_list);
4549 case RTE_ETH_FILTER_TUNNEL:
4550 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4551 &cons_filter.consistent_tunnel_filter, 1);
4554 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4555 i40e_tunnel_filter_list);
4557 case RTE_ETH_FILTER_HASH:
4558 ret = i40e_config_rss_filter_set(dev,
4559 &cons_filter.rss_conf);
4560 flow->rule = &pf->rss_info;
4566 flow->filter_type = cons_filter_type;
4567 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4571 rte_flow_error_set(error, -ret,
4572 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4573 "Failed to create flow.");
4579 i40e_flow_destroy(struct rte_eth_dev *dev,
4580 struct rte_flow *flow,
4581 struct rte_flow_error *error)
4583 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4584 enum rte_filter_type filter_type = flow->filter_type;
4587 switch (filter_type) {
4588 case RTE_ETH_FILTER_ETHERTYPE:
4589 ret = i40e_flow_destroy_ethertype_filter(pf,
4590 (struct i40e_ethertype_filter *)flow->rule);
4592 case RTE_ETH_FILTER_TUNNEL:
4593 ret = i40e_flow_destroy_tunnel_filter(pf,
4594 (struct i40e_tunnel_filter *)flow->rule);
4596 case RTE_ETH_FILTER_FDIR:
4597 ret = i40e_flow_add_del_fdir_filter(dev,
4598 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4600 case RTE_ETH_FILTER_HASH:
4601 ret = i40e_config_rss_filter_del(dev,
4602 (struct i40e_rte_flow_rss_conf *)flow->rule);
4605 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4612 TAILQ_REMOVE(&pf->flow_list, flow, node);
4615 rte_flow_error_set(error, -ret,
4616 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4617 "Failed to destroy flow.");
4623 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4624 struct i40e_ethertype_filter *filter)
4626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4627 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4628 struct i40e_ethertype_filter *node;
4629 struct i40e_control_filter_stats stats;
4633 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4634 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4635 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4636 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4637 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4639 memset(&stats, 0, sizeof(stats));
4640 ret = i40e_aq_add_rem_control_packet_filter(hw,
4641 filter->input.mac_addr.addr_bytes,
4642 filter->input.ether_type,
4643 flags, pf->main_vsi->seid,
4644 filter->queue, 0, &stats, NULL);
4648 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4652 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4658 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4659 struct i40e_tunnel_filter *filter)
4661 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4662 struct i40e_vsi *vsi;
4663 struct i40e_pf_vf *vf;
4664 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4665 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4666 struct i40e_tunnel_filter *node;
4667 bool big_buffer = 0;
4670 memset(&cld_filter, 0, sizeof(cld_filter));
4671 ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4672 (struct ether_addr *)&cld_filter.element.outer_mac);
4673 ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4674 (struct ether_addr *)&cld_filter.element.inner_mac);
4675 cld_filter.element.inner_vlan = filter->input.inner_vlan;
4676 cld_filter.element.flags = filter->input.flags;
4677 cld_filter.element.tenant_id = filter->input.tenant_id;
4678 cld_filter.element.queue_number = filter->queue;
4679 rte_memcpy(cld_filter.general_fields,
4680 filter->input.general_fields,
4681 sizeof(cld_filter.general_fields));
4683 if (!filter->is_to_vf)
4686 vf = &pf->vfs[filter->vf_id];
4690 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4691 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4692 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4693 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4694 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4695 I40E_AQC_ADD_CLOUD_FILTER_0X10))
4699 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4702 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4703 &cld_filter.element, 1);
4707 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4711 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4717 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4722 ret = i40e_flow_flush_fdir_filter(pf);
4724 rte_flow_error_set(error, -ret,
4725 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4726 "Failed to flush FDIR flows.");
4730 ret = i40e_flow_flush_ethertype_filter(pf);
4732 rte_flow_error_set(error, -ret,
4733 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4734 "Failed to ethertype flush flows.");
4738 ret = i40e_flow_flush_tunnel_filter(pf);
4740 rte_flow_error_set(error, -ret,
4741 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4742 "Failed to flush tunnel flows.");
4746 ret = i40e_flow_flush_rss_filter(dev);
4748 rte_flow_error_set(error, -ret,
4749 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4750 "Failed to flush rss flows.");
4758 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4760 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4761 struct i40e_fdir_info *fdir_info = &pf->fdir;
4762 struct i40e_fdir_filter *fdir_filter;
4763 enum i40e_filter_pctype pctype;
4764 struct rte_flow *flow;
4768 ret = i40e_fdir_flush(dev);
4770 /* Delete FDIR filters in FDIR list. */
4771 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4772 ret = i40e_sw_fdir_filter_del(pf,
4773 &fdir_filter->fdir.input);
4778 /* Delete FDIR flows in flow list. */
4779 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4780 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4781 TAILQ_REMOVE(&pf->flow_list, flow, node);
4786 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4787 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4788 pf->fdir.inset_flag[pctype] = 0;
4794 /* Flush all ethertype filters */
4796 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4798 struct i40e_ethertype_filter_list
4799 *ethertype_list = &pf->ethertype.ethertype_list;
4800 struct i40e_ethertype_filter *filter;
4801 struct rte_flow *flow;
4805 while ((filter = TAILQ_FIRST(ethertype_list))) {
4806 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4811 /* Delete ethertype flows in flow list. */
4812 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4813 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4814 TAILQ_REMOVE(&pf->flow_list, flow, node);
4822 /* Flush all tunnel filters */
4824 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4826 struct i40e_tunnel_filter_list
4827 *tunnel_list = &pf->tunnel.tunnel_list;
4828 struct i40e_tunnel_filter *filter;
4829 struct rte_flow *flow;
4833 while ((filter = TAILQ_FIRST(tunnel_list))) {
4834 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4839 /* Delete tunnel flows in flow list. */
4840 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4841 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4842 TAILQ_REMOVE(&pf->flow_list, flow, node);
4850 /* remove the rss filter */
4852 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4854 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4855 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4856 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857 int32_t ret = -EINVAL;
4859 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4862 ret = i40e_config_rss_filter(pf, rss_info, FALSE);