1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
13 #include <rte_debug.h>
14 #include <rte_ether.h>
15 #include <rte_ethdev_driver.h>
17 #include <rte_malloc.h>
18 #include <rte_tailq.h>
19 #include <rte_flow_driver.h>
20 #include <rte_bitmap.h>
22 #include "i40e_logs.h"
23 #include "base/i40e_type.h"
24 #include "base/i40e_prototype.h"
25 #include "i40e_ethdev.h"
27 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
28 #define I40E_IPV6_FRAG_HEADER 44
29 #define I40E_TENANT_ARRAY_NUM 3
30 #define I40E_VLAN_TCI_MASK 0xFFFF
31 #define I40E_VLAN_PRI_MASK 0xE000
32 #define I40E_VLAN_CFI_MASK 0x1000
33 #define I40E_VLAN_VID_MASK 0x0FFF
35 static int i40e_flow_validate(struct rte_eth_dev *dev,
36 const struct rte_flow_attr *attr,
37 const struct rte_flow_item pattern[],
38 const struct rte_flow_action actions[],
39 struct rte_flow_error *error);
40 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
41 const struct rte_flow_attr *attr,
42 const struct rte_flow_item pattern[],
43 const struct rte_flow_action actions[],
44 struct rte_flow_error *error);
45 static int i40e_flow_destroy(struct rte_eth_dev *dev,
46 struct rte_flow *flow,
47 struct rte_flow_error *error);
48 static int i40e_flow_flush(struct rte_eth_dev *dev,
49 struct rte_flow_error *error);
50 static int i40e_flow_query(struct rte_eth_dev *dev,
51 struct rte_flow *flow,
52 const struct rte_flow_action *actions,
53 void *data, struct rte_flow_error *error);
55 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
56 const struct rte_flow_item *pattern,
57 struct rte_flow_error *error,
58 struct rte_eth_ethertype_filter *filter);
59 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
60 const struct rte_flow_action *actions,
61 struct rte_flow_error *error,
62 struct rte_eth_ethertype_filter *filter);
63 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
64 const struct rte_flow_attr *attr,
65 const struct rte_flow_item *pattern,
66 struct rte_flow_error *error,
67 struct i40e_fdir_filter_conf *filter);
68 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
69 const struct rte_flow_action *actions,
70 struct rte_flow_error *error,
71 struct i40e_fdir_filter_conf *filter);
72 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
73 const struct rte_flow_action *actions,
74 struct rte_flow_error *error,
75 struct i40e_tunnel_filter_conf *filter);
76 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
77 struct rte_flow_error *error);
78 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
79 const struct rte_flow_attr *attr,
80 const struct rte_flow_item pattern[],
81 const struct rte_flow_action actions[],
82 struct rte_flow_error *error,
83 union i40e_filter_t *filter);
84 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
85 const struct rte_flow_attr *attr,
86 const struct rte_flow_item pattern[],
87 const struct rte_flow_action actions[],
88 struct rte_flow_error *error,
89 union i40e_filter_t *filter);
90 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
91 const struct rte_flow_attr *attr,
92 const struct rte_flow_item pattern[],
93 const struct rte_flow_action actions[],
94 struct rte_flow_error *error,
95 union i40e_filter_t *filter);
96 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
97 const struct rte_flow_attr *attr,
98 const struct rte_flow_item pattern[],
99 const struct rte_flow_action actions[],
100 struct rte_flow_error *error,
101 union i40e_filter_t *filter);
102 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
103 const struct rte_flow_attr *attr,
104 const struct rte_flow_item pattern[],
105 const struct rte_flow_action actions[],
106 struct rte_flow_error *error,
107 union i40e_filter_t *filter);
108 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
109 const struct rte_flow_attr *attr,
110 const struct rte_flow_item pattern[],
111 const struct rte_flow_action actions[],
112 struct rte_flow_error *error,
113 union i40e_filter_t *filter);
114 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
115 struct i40e_ethertype_filter *filter);
116 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
117 struct i40e_tunnel_filter *filter);
118 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
119 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
120 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
121 static int i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
123 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
124 const struct rte_flow_attr *attr,
125 const struct rte_flow_item pattern[],
126 const struct rte_flow_action actions[],
127 struct rte_flow_error *error,
128 union i40e_filter_t *filter);
130 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
131 const struct rte_flow_item *pattern,
132 struct rte_flow_error *error,
133 struct i40e_tunnel_filter_conf *filter);
135 static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
136 const struct rte_flow_attr *attr,
137 const struct rte_flow_item pattern[],
138 const struct rte_flow_action actions[],
139 struct rte_flow_error *error,
140 union i40e_filter_t *filter);
141 const struct rte_flow_ops i40e_flow_ops = {
142 .validate = i40e_flow_validate,
143 .create = i40e_flow_create,
144 .destroy = i40e_flow_destroy,
145 .flush = i40e_flow_flush,
146 .query = i40e_flow_query,
149 static union i40e_filter_t cons_filter;
150 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
151 /* internal pattern w/o VOID items */
152 struct rte_flow_item g_items[32];
154 /* Pattern matched ethertype filter */
155 static enum rte_flow_item_type pattern_ethertype[] = {
156 RTE_FLOW_ITEM_TYPE_ETH,
157 RTE_FLOW_ITEM_TYPE_END,
160 /* Pattern matched flow director filter */
161 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
162 RTE_FLOW_ITEM_TYPE_ETH,
163 RTE_FLOW_ITEM_TYPE_IPV4,
164 RTE_FLOW_ITEM_TYPE_END,
167 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
168 RTE_FLOW_ITEM_TYPE_ETH,
169 RTE_FLOW_ITEM_TYPE_IPV4,
170 RTE_FLOW_ITEM_TYPE_UDP,
171 RTE_FLOW_ITEM_TYPE_END,
174 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
175 RTE_FLOW_ITEM_TYPE_ETH,
176 RTE_FLOW_ITEM_TYPE_IPV4,
177 RTE_FLOW_ITEM_TYPE_TCP,
178 RTE_FLOW_ITEM_TYPE_END,
181 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
182 RTE_FLOW_ITEM_TYPE_ETH,
183 RTE_FLOW_ITEM_TYPE_IPV4,
184 RTE_FLOW_ITEM_TYPE_SCTP,
185 RTE_FLOW_ITEM_TYPE_END,
188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
189 RTE_FLOW_ITEM_TYPE_ETH,
190 RTE_FLOW_ITEM_TYPE_IPV4,
191 RTE_FLOW_ITEM_TYPE_UDP,
192 RTE_FLOW_ITEM_TYPE_GTPC,
193 RTE_FLOW_ITEM_TYPE_END,
196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
197 RTE_FLOW_ITEM_TYPE_ETH,
198 RTE_FLOW_ITEM_TYPE_IPV4,
199 RTE_FLOW_ITEM_TYPE_UDP,
200 RTE_FLOW_ITEM_TYPE_GTPU,
201 RTE_FLOW_ITEM_TYPE_END,
204 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
205 RTE_FLOW_ITEM_TYPE_ETH,
206 RTE_FLOW_ITEM_TYPE_IPV4,
207 RTE_FLOW_ITEM_TYPE_UDP,
208 RTE_FLOW_ITEM_TYPE_GTPU,
209 RTE_FLOW_ITEM_TYPE_IPV4,
210 RTE_FLOW_ITEM_TYPE_END,
213 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
214 RTE_FLOW_ITEM_TYPE_ETH,
215 RTE_FLOW_ITEM_TYPE_IPV4,
216 RTE_FLOW_ITEM_TYPE_UDP,
217 RTE_FLOW_ITEM_TYPE_GTPU,
218 RTE_FLOW_ITEM_TYPE_IPV6,
219 RTE_FLOW_ITEM_TYPE_END,
222 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
223 RTE_FLOW_ITEM_TYPE_ETH,
224 RTE_FLOW_ITEM_TYPE_IPV6,
225 RTE_FLOW_ITEM_TYPE_END,
228 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
229 RTE_FLOW_ITEM_TYPE_ETH,
230 RTE_FLOW_ITEM_TYPE_IPV6,
231 RTE_FLOW_ITEM_TYPE_UDP,
232 RTE_FLOW_ITEM_TYPE_END,
235 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
236 RTE_FLOW_ITEM_TYPE_ETH,
237 RTE_FLOW_ITEM_TYPE_IPV6,
238 RTE_FLOW_ITEM_TYPE_TCP,
239 RTE_FLOW_ITEM_TYPE_END,
242 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
243 RTE_FLOW_ITEM_TYPE_ETH,
244 RTE_FLOW_ITEM_TYPE_IPV6,
245 RTE_FLOW_ITEM_TYPE_SCTP,
246 RTE_FLOW_ITEM_TYPE_END,
249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
250 RTE_FLOW_ITEM_TYPE_ETH,
251 RTE_FLOW_ITEM_TYPE_IPV6,
252 RTE_FLOW_ITEM_TYPE_UDP,
253 RTE_FLOW_ITEM_TYPE_GTPC,
254 RTE_FLOW_ITEM_TYPE_END,
257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
258 RTE_FLOW_ITEM_TYPE_ETH,
259 RTE_FLOW_ITEM_TYPE_IPV6,
260 RTE_FLOW_ITEM_TYPE_UDP,
261 RTE_FLOW_ITEM_TYPE_GTPU,
262 RTE_FLOW_ITEM_TYPE_END,
265 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
266 RTE_FLOW_ITEM_TYPE_ETH,
267 RTE_FLOW_ITEM_TYPE_IPV6,
268 RTE_FLOW_ITEM_TYPE_UDP,
269 RTE_FLOW_ITEM_TYPE_GTPU,
270 RTE_FLOW_ITEM_TYPE_IPV4,
271 RTE_FLOW_ITEM_TYPE_END,
274 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
275 RTE_FLOW_ITEM_TYPE_ETH,
276 RTE_FLOW_ITEM_TYPE_IPV6,
277 RTE_FLOW_ITEM_TYPE_UDP,
278 RTE_FLOW_ITEM_TYPE_GTPU,
279 RTE_FLOW_ITEM_TYPE_IPV6,
280 RTE_FLOW_ITEM_TYPE_END,
283 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
284 RTE_FLOW_ITEM_TYPE_ETH,
285 RTE_FLOW_ITEM_TYPE_RAW,
286 RTE_FLOW_ITEM_TYPE_END,
289 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
290 RTE_FLOW_ITEM_TYPE_ETH,
291 RTE_FLOW_ITEM_TYPE_RAW,
292 RTE_FLOW_ITEM_TYPE_RAW,
293 RTE_FLOW_ITEM_TYPE_END,
296 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
297 RTE_FLOW_ITEM_TYPE_ETH,
298 RTE_FLOW_ITEM_TYPE_RAW,
299 RTE_FLOW_ITEM_TYPE_RAW,
300 RTE_FLOW_ITEM_TYPE_RAW,
301 RTE_FLOW_ITEM_TYPE_END,
304 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
305 RTE_FLOW_ITEM_TYPE_ETH,
306 RTE_FLOW_ITEM_TYPE_IPV4,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_END,
311 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
312 RTE_FLOW_ITEM_TYPE_ETH,
313 RTE_FLOW_ITEM_TYPE_IPV4,
314 RTE_FLOW_ITEM_TYPE_RAW,
315 RTE_FLOW_ITEM_TYPE_RAW,
316 RTE_FLOW_ITEM_TYPE_END,
319 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
320 RTE_FLOW_ITEM_TYPE_ETH,
321 RTE_FLOW_ITEM_TYPE_IPV4,
322 RTE_FLOW_ITEM_TYPE_RAW,
323 RTE_FLOW_ITEM_TYPE_RAW,
324 RTE_FLOW_ITEM_TYPE_RAW,
325 RTE_FLOW_ITEM_TYPE_END,
328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
329 RTE_FLOW_ITEM_TYPE_ETH,
330 RTE_FLOW_ITEM_TYPE_IPV4,
331 RTE_FLOW_ITEM_TYPE_UDP,
332 RTE_FLOW_ITEM_TYPE_RAW,
333 RTE_FLOW_ITEM_TYPE_END,
336 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
337 RTE_FLOW_ITEM_TYPE_ETH,
338 RTE_FLOW_ITEM_TYPE_IPV4,
339 RTE_FLOW_ITEM_TYPE_UDP,
340 RTE_FLOW_ITEM_TYPE_RAW,
341 RTE_FLOW_ITEM_TYPE_RAW,
342 RTE_FLOW_ITEM_TYPE_END,
345 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
346 RTE_FLOW_ITEM_TYPE_ETH,
347 RTE_FLOW_ITEM_TYPE_IPV4,
348 RTE_FLOW_ITEM_TYPE_UDP,
349 RTE_FLOW_ITEM_TYPE_RAW,
350 RTE_FLOW_ITEM_TYPE_RAW,
351 RTE_FLOW_ITEM_TYPE_RAW,
352 RTE_FLOW_ITEM_TYPE_END,
355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
356 RTE_FLOW_ITEM_TYPE_ETH,
357 RTE_FLOW_ITEM_TYPE_IPV4,
358 RTE_FLOW_ITEM_TYPE_TCP,
359 RTE_FLOW_ITEM_TYPE_RAW,
360 RTE_FLOW_ITEM_TYPE_END,
363 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
364 RTE_FLOW_ITEM_TYPE_ETH,
365 RTE_FLOW_ITEM_TYPE_IPV4,
366 RTE_FLOW_ITEM_TYPE_TCP,
367 RTE_FLOW_ITEM_TYPE_RAW,
368 RTE_FLOW_ITEM_TYPE_RAW,
369 RTE_FLOW_ITEM_TYPE_END,
372 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
373 RTE_FLOW_ITEM_TYPE_ETH,
374 RTE_FLOW_ITEM_TYPE_IPV4,
375 RTE_FLOW_ITEM_TYPE_TCP,
376 RTE_FLOW_ITEM_TYPE_RAW,
377 RTE_FLOW_ITEM_TYPE_RAW,
378 RTE_FLOW_ITEM_TYPE_RAW,
379 RTE_FLOW_ITEM_TYPE_END,
382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
383 RTE_FLOW_ITEM_TYPE_ETH,
384 RTE_FLOW_ITEM_TYPE_IPV4,
385 RTE_FLOW_ITEM_TYPE_SCTP,
386 RTE_FLOW_ITEM_TYPE_RAW,
387 RTE_FLOW_ITEM_TYPE_END,
390 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
391 RTE_FLOW_ITEM_TYPE_ETH,
392 RTE_FLOW_ITEM_TYPE_IPV4,
393 RTE_FLOW_ITEM_TYPE_SCTP,
394 RTE_FLOW_ITEM_TYPE_RAW,
395 RTE_FLOW_ITEM_TYPE_RAW,
396 RTE_FLOW_ITEM_TYPE_END,
399 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
400 RTE_FLOW_ITEM_TYPE_ETH,
401 RTE_FLOW_ITEM_TYPE_IPV4,
402 RTE_FLOW_ITEM_TYPE_SCTP,
403 RTE_FLOW_ITEM_TYPE_RAW,
404 RTE_FLOW_ITEM_TYPE_RAW,
405 RTE_FLOW_ITEM_TYPE_RAW,
406 RTE_FLOW_ITEM_TYPE_END,
409 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
410 RTE_FLOW_ITEM_TYPE_ETH,
411 RTE_FLOW_ITEM_TYPE_IPV6,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_END,
416 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
417 RTE_FLOW_ITEM_TYPE_ETH,
418 RTE_FLOW_ITEM_TYPE_IPV6,
419 RTE_FLOW_ITEM_TYPE_RAW,
420 RTE_FLOW_ITEM_TYPE_RAW,
421 RTE_FLOW_ITEM_TYPE_END,
424 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
425 RTE_FLOW_ITEM_TYPE_ETH,
426 RTE_FLOW_ITEM_TYPE_IPV6,
427 RTE_FLOW_ITEM_TYPE_RAW,
428 RTE_FLOW_ITEM_TYPE_RAW,
429 RTE_FLOW_ITEM_TYPE_RAW,
430 RTE_FLOW_ITEM_TYPE_END,
433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
434 RTE_FLOW_ITEM_TYPE_ETH,
435 RTE_FLOW_ITEM_TYPE_IPV6,
436 RTE_FLOW_ITEM_TYPE_UDP,
437 RTE_FLOW_ITEM_TYPE_RAW,
438 RTE_FLOW_ITEM_TYPE_END,
441 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
442 RTE_FLOW_ITEM_TYPE_ETH,
443 RTE_FLOW_ITEM_TYPE_IPV6,
444 RTE_FLOW_ITEM_TYPE_UDP,
445 RTE_FLOW_ITEM_TYPE_RAW,
446 RTE_FLOW_ITEM_TYPE_RAW,
447 RTE_FLOW_ITEM_TYPE_END,
450 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
451 RTE_FLOW_ITEM_TYPE_ETH,
452 RTE_FLOW_ITEM_TYPE_IPV6,
453 RTE_FLOW_ITEM_TYPE_UDP,
454 RTE_FLOW_ITEM_TYPE_RAW,
455 RTE_FLOW_ITEM_TYPE_RAW,
456 RTE_FLOW_ITEM_TYPE_RAW,
457 RTE_FLOW_ITEM_TYPE_END,
460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
461 RTE_FLOW_ITEM_TYPE_ETH,
462 RTE_FLOW_ITEM_TYPE_IPV6,
463 RTE_FLOW_ITEM_TYPE_TCP,
464 RTE_FLOW_ITEM_TYPE_RAW,
465 RTE_FLOW_ITEM_TYPE_END,
468 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
469 RTE_FLOW_ITEM_TYPE_ETH,
470 RTE_FLOW_ITEM_TYPE_IPV6,
471 RTE_FLOW_ITEM_TYPE_TCP,
472 RTE_FLOW_ITEM_TYPE_RAW,
473 RTE_FLOW_ITEM_TYPE_RAW,
474 RTE_FLOW_ITEM_TYPE_END,
477 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
478 RTE_FLOW_ITEM_TYPE_ETH,
479 RTE_FLOW_ITEM_TYPE_IPV6,
480 RTE_FLOW_ITEM_TYPE_TCP,
481 RTE_FLOW_ITEM_TYPE_RAW,
482 RTE_FLOW_ITEM_TYPE_RAW,
483 RTE_FLOW_ITEM_TYPE_RAW,
484 RTE_FLOW_ITEM_TYPE_END,
487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
488 RTE_FLOW_ITEM_TYPE_ETH,
489 RTE_FLOW_ITEM_TYPE_IPV6,
490 RTE_FLOW_ITEM_TYPE_SCTP,
491 RTE_FLOW_ITEM_TYPE_RAW,
492 RTE_FLOW_ITEM_TYPE_END,
495 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
496 RTE_FLOW_ITEM_TYPE_ETH,
497 RTE_FLOW_ITEM_TYPE_IPV6,
498 RTE_FLOW_ITEM_TYPE_SCTP,
499 RTE_FLOW_ITEM_TYPE_RAW,
500 RTE_FLOW_ITEM_TYPE_RAW,
501 RTE_FLOW_ITEM_TYPE_END,
504 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
505 RTE_FLOW_ITEM_TYPE_ETH,
506 RTE_FLOW_ITEM_TYPE_IPV6,
507 RTE_FLOW_ITEM_TYPE_SCTP,
508 RTE_FLOW_ITEM_TYPE_RAW,
509 RTE_FLOW_ITEM_TYPE_RAW,
510 RTE_FLOW_ITEM_TYPE_RAW,
511 RTE_FLOW_ITEM_TYPE_END,
514 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
515 RTE_FLOW_ITEM_TYPE_ETH,
516 RTE_FLOW_ITEM_TYPE_VLAN,
517 RTE_FLOW_ITEM_TYPE_END,
520 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
521 RTE_FLOW_ITEM_TYPE_ETH,
522 RTE_FLOW_ITEM_TYPE_VLAN,
523 RTE_FLOW_ITEM_TYPE_IPV4,
524 RTE_FLOW_ITEM_TYPE_END,
527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
528 RTE_FLOW_ITEM_TYPE_ETH,
529 RTE_FLOW_ITEM_TYPE_VLAN,
530 RTE_FLOW_ITEM_TYPE_IPV4,
531 RTE_FLOW_ITEM_TYPE_UDP,
532 RTE_FLOW_ITEM_TYPE_END,
535 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
536 RTE_FLOW_ITEM_TYPE_ETH,
537 RTE_FLOW_ITEM_TYPE_VLAN,
538 RTE_FLOW_ITEM_TYPE_IPV4,
539 RTE_FLOW_ITEM_TYPE_TCP,
540 RTE_FLOW_ITEM_TYPE_END,
543 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
544 RTE_FLOW_ITEM_TYPE_ETH,
545 RTE_FLOW_ITEM_TYPE_VLAN,
546 RTE_FLOW_ITEM_TYPE_IPV4,
547 RTE_FLOW_ITEM_TYPE_SCTP,
548 RTE_FLOW_ITEM_TYPE_END,
551 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
552 RTE_FLOW_ITEM_TYPE_ETH,
553 RTE_FLOW_ITEM_TYPE_VLAN,
554 RTE_FLOW_ITEM_TYPE_IPV6,
555 RTE_FLOW_ITEM_TYPE_END,
558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
559 RTE_FLOW_ITEM_TYPE_ETH,
560 RTE_FLOW_ITEM_TYPE_VLAN,
561 RTE_FLOW_ITEM_TYPE_IPV6,
562 RTE_FLOW_ITEM_TYPE_UDP,
563 RTE_FLOW_ITEM_TYPE_END,
566 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
567 RTE_FLOW_ITEM_TYPE_ETH,
568 RTE_FLOW_ITEM_TYPE_VLAN,
569 RTE_FLOW_ITEM_TYPE_IPV6,
570 RTE_FLOW_ITEM_TYPE_TCP,
571 RTE_FLOW_ITEM_TYPE_END,
574 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
575 RTE_FLOW_ITEM_TYPE_ETH,
576 RTE_FLOW_ITEM_TYPE_VLAN,
577 RTE_FLOW_ITEM_TYPE_IPV6,
578 RTE_FLOW_ITEM_TYPE_SCTP,
579 RTE_FLOW_ITEM_TYPE_END,
582 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
583 RTE_FLOW_ITEM_TYPE_ETH,
584 RTE_FLOW_ITEM_TYPE_VLAN,
585 RTE_FLOW_ITEM_TYPE_RAW,
586 RTE_FLOW_ITEM_TYPE_END,
589 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
590 RTE_FLOW_ITEM_TYPE_ETH,
591 RTE_FLOW_ITEM_TYPE_VLAN,
592 RTE_FLOW_ITEM_TYPE_RAW,
593 RTE_FLOW_ITEM_TYPE_RAW,
594 RTE_FLOW_ITEM_TYPE_END,
597 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
598 RTE_FLOW_ITEM_TYPE_ETH,
599 RTE_FLOW_ITEM_TYPE_VLAN,
600 RTE_FLOW_ITEM_TYPE_RAW,
601 RTE_FLOW_ITEM_TYPE_RAW,
602 RTE_FLOW_ITEM_TYPE_RAW,
603 RTE_FLOW_ITEM_TYPE_END,
606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
607 RTE_FLOW_ITEM_TYPE_ETH,
608 RTE_FLOW_ITEM_TYPE_VLAN,
609 RTE_FLOW_ITEM_TYPE_IPV4,
610 RTE_FLOW_ITEM_TYPE_RAW,
611 RTE_FLOW_ITEM_TYPE_END,
614 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
615 RTE_FLOW_ITEM_TYPE_ETH,
616 RTE_FLOW_ITEM_TYPE_VLAN,
617 RTE_FLOW_ITEM_TYPE_IPV4,
618 RTE_FLOW_ITEM_TYPE_RAW,
619 RTE_FLOW_ITEM_TYPE_RAW,
620 RTE_FLOW_ITEM_TYPE_END,
623 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
624 RTE_FLOW_ITEM_TYPE_ETH,
625 RTE_FLOW_ITEM_TYPE_VLAN,
626 RTE_FLOW_ITEM_TYPE_IPV4,
627 RTE_FLOW_ITEM_TYPE_RAW,
628 RTE_FLOW_ITEM_TYPE_RAW,
629 RTE_FLOW_ITEM_TYPE_RAW,
630 RTE_FLOW_ITEM_TYPE_END,
633 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
634 RTE_FLOW_ITEM_TYPE_ETH,
635 RTE_FLOW_ITEM_TYPE_VLAN,
636 RTE_FLOW_ITEM_TYPE_IPV4,
637 RTE_FLOW_ITEM_TYPE_UDP,
638 RTE_FLOW_ITEM_TYPE_RAW,
639 RTE_FLOW_ITEM_TYPE_END,
642 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
643 RTE_FLOW_ITEM_TYPE_ETH,
644 RTE_FLOW_ITEM_TYPE_VLAN,
645 RTE_FLOW_ITEM_TYPE_IPV4,
646 RTE_FLOW_ITEM_TYPE_UDP,
647 RTE_FLOW_ITEM_TYPE_RAW,
648 RTE_FLOW_ITEM_TYPE_RAW,
649 RTE_FLOW_ITEM_TYPE_END,
652 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
653 RTE_FLOW_ITEM_TYPE_ETH,
654 RTE_FLOW_ITEM_TYPE_VLAN,
655 RTE_FLOW_ITEM_TYPE_IPV4,
656 RTE_FLOW_ITEM_TYPE_UDP,
657 RTE_FLOW_ITEM_TYPE_RAW,
658 RTE_FLOW_ITEM_TYPE_RAW,
659 RTE_FLOW_ITEM_TYPE_RAW,
660 RTE_FLOW_ITEM_TYPE_END,
663 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
664 RTE_FLOW_ITEM_TYPE_ETH,
665 RTE_FLOW_ITEM_TYPE_VLAN,
666 RTE_FLOW_ITEM_TYPE_IPV4,
667 RTE_FLOW_ITEM_TYPE_TCP,
668 RTE_FLOW_ITEM_TYPE_RAW,
669 RTE_FLOW_ITEM_TYPE_END,
672 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
673 RTE_FLOW_ITEM_TYPE_ETH,
674 RTE_FLOW_ITEM_TYPE_VLAN,
675 RTE_FLOW_ITEM_TYPE_IPV4,
676 RTE_FLOW_ITEM_TYPE_TCP,
677 RTE_FLOW_ITEM_TYPE_RAW,
678 RTE_FLOW_ITEM_TYPE_RAW,
679 RTE_FLOW_ITEM_TYPE_END,
682 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
683 RTE_FLOW_ITEM_TYPE_ETH,
684 RTE_FLOW_ITEM_TYPE_VLAN,
685 RTE_FLOW_ITEM_TYPE_IPV4,
686 RTE_FLOW_ITEM_TYPE_TCP,
687 RTE_FLOW_ITEM_TYPE_RAW,
688 RTE_FLOW_ITEM_TYPE_RAW,
689 RTE_FLOW_ITEM_TYPE_RAW,
690 RTE_FLOW_ITEM_TYPE_END,
693 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
694 RTE_FLOW_ITEM_TYPE_ETH,
695 RTE_FLOW_ITEM_TYPE_VLAN,
696 RTE_FLOW_ITEM_TYPE_IPV4,
697 RTE_FLOW_ITEM_TYPE_SCTP,
698 RTE_FLOW_ITEM_TYPE_RAW,
699 RTE_FLOW_ITEM_TYPE_END,
702 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
703 RTE_FLOW_ITEM_TYPE_ETH,
704 RTE_FLOW_ITEM_TYPE_VLAN,
705 RTE_FLOW_ITEM_TYPE_IPV4,
706 RTE_FLOW_ITEM_TYPE_SCTP,
707 RTE_FLOW_ITEM_TYPE_RAW,
708 RTE_FLOW_ITEM_TYPE_RAW,
709 RTE_FLOW_ITEM_TYPE_END,
712 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
713 RTE_FLOW_ITEM_TYPE_ETH,
714 RTE_FLOW_ITEM_TYPE_VLAN,
715 RTE_FLOW_ITEM_TYPE_IPV4,
716 RTE_FLOW_ITEM_TYPE_SCTP,
717 RTE_FLOW_ITEM_TYPE_RAW,
718 RTE_FLOW_ITEM_TYPE_RAW,
719 RTE_FLOW_ITEM_TYPE_RAW,
720 RTE_FLOW_ITEM_TYPE_END,
723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
724 RTE_FLOW_ITEM_TYPE_ETH,
725 RTE_FLOW_ITEM_TYPE_VLAN,
726 RTE_FLOW_ITEM_TYPE_IPV6,
727 RTE_FLOW_ITEM_TYPE_RAW,
728 RTE_FLOW_ITEM_TYPE_END,
731 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
732 RTE_FLOW_ITEM_TYPE_ETH,
733 RTE_FLOW_ITEM_TYPE_VLAN,
734 RTE_FLOW_ITEM_TYPE_IPV6,
735 RTE_FLOW_ITEM_TYPE_RAW,
736 RTE_FLOW_ITEM_TYPE_RAW,
737 RTE_FLOW_ITEM_TYPE_END,
740 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
741 RTE_FLOW_ITEM_TYPE_ETH,
742 RTE_FLOW_ITEM_TYPE_VLAN,
743 RTE_FLOW_ITEM_TYPE_IPV6,
744 RTE_FLOW_ITEM_TYPE_RAW,
745 RTE_FLOW_ITEM_TYPE_RAW,
746 RTE_FLOW_ITEM_TYPE_RAW,
747 RTE_FLOW_ITEM_TYPE_END,
750 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
751 RTE_FLOW_ITEM_TYPE_ETH,
752 RTE_FLOW_ITEM_TYPE_VLAN,
753 RTE_FLOW_ITEM_TYPE_IPV6,
754 RTE_FLOW_ITEM_TYPE_UDP,
755 RTE_FLOW_ITEM_TYPE_RAW,
756 RTE_FLOW_ITEM_TYPE_END,
759 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
760 RTE_FLOW_ITEM_TYPE_ETH,
761 RTE_FLOW_ITEM_TYPE_VLAN,
762 RTE_FLOW_ITEM_TYPE_IPV6,
763 RTE_FLOW_ITEM_TYPE_UDP,
764 RTE_FLOW_ITEM_TYPE_RAW,
765 RTE_FLOW_ITEM_TYPE_RAW,
766 RTE_FLOW_ITEM_TYPE_END,
769 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
770 RTE_FLOW_ITEM_TYPE_ETH,
771 RTE_FLOW_ITEM_TYPE_VLAN,
772 RTE_FLOW_ITEM_TYPE_IPV6,
773 RTE_FLOW_ITEM_TYPE_UDP,
774 RTE_FLOW_ITEM_TYPE_RAW,
775 RTE_FLOW_ITEM_TYPE_RAW,
776 RTE_FLOW_ITEM_TYPE_RAW,
777 RTE_FLOW_ITEM_TYPE_END,
780 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
781 RTE_FLOW_ITEM_TYPE_ETH,
782 RTE_FLOW_ITEM_TYPE_VLAN,
783 RTE_FLOW_ITEM_TYPE_IPV6,
784 RTE_FLOW_ITEM_TYPE_TCP,
785 RTE_FLOW_ITEM_TYPE_RAW,
786 RTE_FLOW_ITEM_TYPE_END,
789 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
790 RTE_FLOW_ITEM_TYPE_ETH,
791 RTE_FLOW_ITEM_TYPE_VLAN,
792 RTE_FLOW_ITEM_TYPE_IPV6,
793 RTE_FLOW_ITEM_TYPE_TCP,
794 RTE_FLOW_ITEM_TYPE_RAW,
795 RTE_FLOW_ITEM_TYPE_RAW,
796 RTE_FLOW_ITEM_TYPE_END,
799 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
800 RTE_FLOW_ITEM_TYPE_ETH,
801 RTE_FLOW_ITEM_TYPE_VLAN,
802 RTE_FLOW_ITEM_TYPE_IPV6,
803 RTE_FLOW_ITEM_TYPE_TCP,
804 RTE_FLOW_ITEM_TYPE_RAW,
805 RTE_FLOW_ITEM_TYPE_RAW,
806 RTE_FLOW_ITEM_TYPE_RAW,
807 RTE_FLOW_ITEM_TYPE_END,
810 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
811 RTE_FLOW_ITEM_TYPE_ETH,
812 RTE_FLOW_ITEM_TYPE_VLAN,
813 RTE_FLOW_ITEM_TYPE_IPV6,
814 RTE_FLOW_ITEM_TYPE_SCTP,
815 RTE_FLOW_ITEM_TYPE_RAW,
816 RTE_FLOW_ITEM_TYPE_END,
819 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
820 RTE_FLOW_ITEM_TYPE_ETH,
821 RTE_FLOW_ITEM_TYPE_VLAN,
822 RTE_FLOW_ITEM_TYPE_IPV6,
823 RTE_FLOW_ITEM_TYPE_SCTP,
824 RTE_FLOW_ITEM_TYPE_RAW,
825 RTE_FLOW_ITEM_TYPE_RAW,
826 RTE_FLOW_ITEM_TYPE_END,
829 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
830 RTE_FLOW_ITEM_TYPE_ETH,
831 RTE_FLOW_ITEM_TYPE_VLAN,
832 RTE_FLOW_ITEM_TYPE_IPV6,
833 RTE_FLOW_ITEM_TYPE_SCTP,
834 RTE_FLOW_ITEM_TYPE_RAW,
835 RTE_FLOW_ITEM_TYPE_RAW,
836 RTE_FLOW_ITEM_TYPE_RAW,
837 RTE_FLOW_ITEM_TYPE_END,
840 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
841 RTE_FLOW_ITEM_TYPE_ETH,
842 RTE_FLOW_ITEM_TYPE_IPV4,
843 RTE_FLOW_ITEM_TYPE_VF,
844 RTE_FLOW_ITEM_TYPE_END,
847 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
848 RTE_FLOW_ITEM_TYPE_ETH,
849 RTE_FLOW_ITEM_TYPE_IPV4,
850 RTE_FLOW_ITEM_TYPE_UDP,
851 RTE_FLOW_ITEM_TYPE_VF,
852 RTE_FLOW_ITEM_TYPE_END,
855 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
856 RTE_FLOW_ITEM_TYPE_ETH,
857 RTE_FLOW_ITEM_TYPE_IPV4,
858 RTE_FLOW_ITEM_TYPE_TCP,
859 RTE_FLOW_ITEM_TYPE_VF,
860 RTE_FLOW_ITEM_TYPE_END,
863 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
864 RTE_FLOW_ITEM_TYPE_ETH,
865 RTE_FLOW_ITEM_TYPE_IPV4,
866 RTE_FLOW_ITEM_TYPE_SCTP,
867 RTE_FLOW_ITEM_TYPE_VF,
868 RTE_FLOW_ITEM_TYPE_END,
871 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
872 RTE_FLOW_ITEM_TYPE_ETH,
873 RTE_FLOW_ITEM_TYPE_IPV6,
874 RTE_FLOW_ITEM_TYPE_VF,
875 RTE_FLOW_ITEM_TYPE_END,
878 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
879 RTE_FLOW_ITEM_TYPE_ETH,
880 RTE_FLOW_ITEM_TYPE_IPV6,
881 RTE_FLOW_ITEM_TYPE_UDP,
882 RTE_FLOW_ITEM_TYPE_VF,
883 RTE_FLOW_ITEM_TYPE_END,
886 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
887 RTE_FLOW_ITEM_TYPE_ETH,
888 RTE_FLOW_ITEM_TYPE_IPV6,
889 RTE_FLOW_ITEM_TYPE_TCP,
890 RTE_FLOW_ITEM_TYPE_VF,
891 RTE_FLOW_ITEM_TYPE_END,
894 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
895 RTE_FLOW_ITEM_TYPE_ETH,
896 RTE_FLOW_ITEM_TYPE_IPV6,
897 RTE_FLOW_ITEM_TYPE_SCTP,
898 RTE_FLOW_ITEM_TYPE_VF,
899 RTE_FLOW_ITEM_TYPE_END,
902 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
903 RTE_FLOW_ITEM_TYPE_ETH,
904 RTE_FLOW_ITEM_TYPE_RAW,
905 RTE_FLOW_ITEM_TYPE_VF,
906 RTE_FLOW_ITEM_TYPE_END,
909 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
910 RTE_FLOW_ITEM_TYPE_ETH,
911 RTE_FLOW_ITEM_TYPE_RAW,
912 RTE_FLOW_ITEM_TYPE_RAW,
913 RTE_FLOW_ITEM_TYPE_VF,
914 RTE_FLOW_ITEM_TYPE_END,
917 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
918 RTE_FLOW_ITEM_TYPE_ETH,
919 RTE_FLOW_ITEM_TYPE_RAW,
920 RTE_FLOW_ITEM_TYPE_RAW,
921 RTE_FLOW_ITEM_TYPE_RAW,
922 RTE_FLOW_ITEM_TYPE_VF,
923 RTE_FLOW_ITEM_TYPE_END,
926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
927 RTE_FLOW_ITEM_TYPE_ETH,
928 RTE_FLOW_ITEM_TYPE_IPV4,
929 RTE_FLOW_ITEM_TYPE_RAW,
930 RTE_FLOW_ITEM_TYPE_VF,
931 RTE_FLOW_ITEM_TYPE_END,
934 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
935 RTE_FLOW_ITEM_TYPE_ETH,
936 RTE_FLOW_ITEM_TYPE_IPV4,
937 RTE_FLOW_ITEM_TYPE_RAW,
938 RTE_FLOW_ITEM_TYPE_RAW,
939 RTE_FLOW_ITEM_TYPE_VF,
940 RTE_FLOW_ITEM_TYPE_END,
943 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
944 RTE_FLOW_ITEM_TYPE_ETH,
945 RTE_FLOW_ITEM_TYPE_IPV4,
946 RTE_FLOW_ITEM_TYPE_RAW,
947 RTE_FLOW_ITEM_TYPE_RAW,
948 RTE_FLOW_ITEM_TYPE_RAW,
949 RTE_FLOW_ITEM_TYPE_VF,
950 RTE_FLOW_ITEM_TYPE_END,
953 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
954 RTE_FLOW_ITEM_TYPE_ETH,
955 RTE_FLOW_ITEM_TYPE_IPV4,
956 RTE_FLOW_ITEM_TYPE_UDP,
957 RTE_FLOW_ITEM_TYPE_RAW,
958 RTE_FLOW_ITEM_TYPE_VF,
959 RTE_FLOW_ITEM_TYPE_END,
962 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
963 RTE_FLOW_ITEM_TYPE_ETH,
964 RTE_FLOW_ITEM_TYPE_IPV4,
965 RTE_FLOW_ITEM_TYPE_UDP,
966 RTE_FLOW_ITEM_TYPE_RAW,
967 RTE_FLOW_ITEM_TYPE_RAW,
968 RTE_FLOW_ITEM_TYPE_VF,
969 RTE_FLOW_ITEM_TYPE_END,
972 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
973 RTE_FLOW_ITEM_TYPE_ETH,
974 RTE_FLOW_ITEM_TYPE_IPV4,
975 RTE_FLOW_ITEM_TYPE_UDP,
976 RTE_FLOW_ITEM_TYPE_RAW,
977 RTE_FLOW_ITEM_TYPE_RAW,
978 RTE_FLOW_ITEM_TYPE_RAW,
979 RTE_FLOW_ITEM_TYPE_VF,
980 RTE_FLOW_ITEM_TYPE_END,
983 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
984 RTE_FLOW_ITEM_TYPE_ETH,
985 RTE_FLOW_ITEM_TYPE_IPV4,
986 RTE_FLOW_ITEM_TYPE_TCP,
987 RTE_FLOW_ITEM_TYPE_RAW,
988 RTE_FLOW_ITEM_TYPE_VF,
989 RTE_FLOW_ITEM_TYPE_END,
992 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
993 RTE_FLOW_ITEM_TYPE_ETH,
994 RTE_FLOW_ITEM_TYPE_IPV4,
995 RTE_FLOW_ITEM_TYPE_TCP,
996 RTE_FLOW_ITEM_TYPE_RAW,
997 RTE_FLOW_ITEM_TYPE_RAW,
998 RTE_FLOW_ITEM_TYPE_VF,
999 RTE_FLOW_ITEM_TYPE_END,
1002 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
1003 RTE_FLOW_ITEM_TYPE_ETH,
1004 RTE_FLOW_ITEM_TYPE_IPV4,
1005 RTE_FLOW_ITEM_TYPE_TCP,
1006 RTE_FLOW_ITEM_TYPE_RAW,
1007 RTE_FLOW_ITEM_TYPE_RAW,
1008 RTE_FLOW_ITEM_TYPE_RAW,
1009 RTE_FLOW_ITEM_TYPE_VF,
1010 RTE_FLOW_ITEM_TYPE_END,
1013 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
1014 RTE_FLOW_ITEM_TYPE_ETH,
1015 RTE_FLOW_ITEM_TYPE_IPV4,
1016 RTE_FLOW_ITEM_TYPE_SCTP,
1017 RTE_FLOW_ITEM_TYPE_RAW,
1018 RTE_FLOW_ITEM_TYPE_VF,
1019 RTE_FLOW_ITEM_TYPE_END,
1022 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1023 RTE_FLOW_ITEM_TYPE_ETH,
1024 RTE_FLOW_ITEM_TYPE_IPV4,
1025 RTE_FLOW_ITEM_TYPE_SCTP,
1026 RTE_FLOW_ITEM_TYPE_RAW,
1027 RTE_FLOW_ITEM_TYPE_RAW,
1028 RTE_FLOW_ITEM_TYPE_VF,
1029 RTE_FLOW_ITEM_TYPE_END,
1032 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1033 RTE_FLOW_ITEM_TYPE_ETH,
1034 RTE_FLOW_ITEM_TYPE_IPV4,
1035 RTE_FLOW_ITEM_TYPE_SCTP,
1036 RTE_FLOW_ITEM_TYPE_RAW,
1037 RTE_FLOW_ITEM_TYPE_RAW,
1038 RTE_FLOW_ITEM_TYPE_RAW,
1039 RTE_FLOW_ITEM_TYPE_VF,
1040 RTE_FLOW_ITEM_TYPE_END,
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1044 RTE_FLOW_ITEM_TYPE_ETH,
1045 RTE_FLOW_ITEM_TYPE_IPV6,
1046 RTE_FLOW_ITEM_TYPE_RAW,
1047 RTE_FLOW_ITEM_TYPE_VF,
1048 RTE_FLOW_ITEM_TYPE_END,
1051 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1052 RTE_FLOW_ITEM_TYPE_ETH,
1053 RTE_FLOW_ITEM_TYPE_IPV6,
1054 RTE_FLOW_ITEM_TYPE_RAW,
1055 RTE_FLOW_ITEM_TYPE_RAW,
1056 RTE_FLOW_ITEM_TYPE_VF,
1057 RTE_FLOW_ITEM_TYPE_END,
1060 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1061 RTE_FLOW_ITEM_TYPE_ETH,
1062 RTE_FLOW_ITEM_TYPE_IPV6,
1063 RTE_FLOW_ITEM_TYPE_RAW,
1064 RTE_FLOW_ITEM_TYPE_RAW,
1065 RTE_FLOW_ITEM_TYPE_RAW,
1066 RTE_FLOW_ITEM_TYPE_VF,
1067 RTE_FLOW_ITEM_TYPE_END,
1070 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1071 RTE_FLOW_ITEM_TYPE_ETH,
1072 RTE_FLOW_ITEM_TYPE_IPV6,
1073 RTE_FLOW_ITEM_TYPE_UDP,
1074 RTE_FLOW_ITEM_TYPE_RAW,
1075 RTE_FLOW_ITEM_TYPE_VF,
1076 RTE_FLOW_ITEM_TYPE_END,
1079 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1080 RTE_FLOW_ITEM_TYPE_ETH,
1081 RTE_FLOW_ITEM_TYPE_IPV6,
1082 RTE_FLOW_ITEM_TYPE_UDP,
1083 RTE_FLOW_ITEM_TYPE_RAW,
1084 RTE_FLOW_ITEM_TYPE_RAW,
1085 RTE_FLOW_ITEM_TYPE_VF,
1086 RTE_FLOW_ITEM_TYPE_END,
1089 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1090 RTE_FLOW_ITEM_TYPE_ETH,
1091 RTE_FLOW_ITEM_TYPE_IPV6,
1092 RTE_FLOW_ITEM_TYPE_UDP,
1093 RTE_FLOW_ITEM_TYPE_RAW,
1094 RTE_FLOW_ITEM_TYPE_RAW,
1095 RTE_FLOW_ITEM_TYPE_RAW,
1096 RTE_FLOW_ITEM_TYPE_VF,
1097 RTE_FLOW_ITEM_TYPE_END,
1100 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1101 RTE_FLOW_ITEM_TYPE_ETH,
1102 RTE_FLOW_ITEM_TYPE_IPV6,
1103 RTE_FLOW_ITEM_TYPE_TCP,
1104 RTE_FLOW_ITEM_TYPE_RAW,
1105 RTE_FLOW_ITEM_TYPE_VF,
1106 RTE_FLOW_ITEM_TYPE_END,
1109 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1110 RTE_FLOW_ITEM_TYPE_ETH,
1111 RTE_FLOW_ITEM_TYPE_IPV6,
1112 RTE_FLOW_ITEM_TYPE_TCP,
1113 RTE_FLOW_ITEM_TYPE_RAW,
1114 RTE_FLOW_ITEM_TYPE_RAW,
1115 RTE_FLOW_ITEM_TYPE_VF,
1116 RTE_FLOW_ITEM_TYPE_END,
1119 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1120 RTE_FLOW_ITEM_TYPE_ETH,
1121 RTE_FLOW_ITEM_TYPE_IPV6,
1122 RTE_FLOW_ITEM_TYPE_TCP,
1123 RTE_FLOW_ITEM_TYPE_RAW,
1124 RTE_FLOW_ITEM_TYPE_RAW,
1125 RTE_FLOW_ITEM_TYPE_RAW,
1126 RTE_FLOW_ITEM_TYPE_VF,
1127 RTE_FLOW_ITEM_TYPE_END,
1130 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1131 RTE_FLOW_ITEM_TYPE_ETH,
1132 RTE_FLOW_ITEM_TYPE_IPV6,
1133 RTE_FLOW_ITEM_TYPE_SCTP,
1134 RTE_FLOW_ITEM_TYPE_RAW,
1135 RTE_FLOW_ITEM_TYPE_VF,
1136 RTE_FLOW_ITEM_TYPE_END,
1139 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1140 RTE_FLOW_ITEM_TYPE_ETH,
1141 RTE_FLOW_ITEM_TYPE_IPV6,
1142 RTE_FLOW_ITEM_TYPE_SCTP,
1143 RTE_FLOW_ITEM_TYPE_RAW,
1144 RTE_FLOW_ITEM_TYPE_RAW,
1145 RTE_FLOW_ITEM_TYPE_VF,
1146 RTE_FLOW_ITEM_TYPE_END,
1149 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1150 RTE_FLOW_ITEM_TYPE_ETH,
1151 RTE_FLOW_ITEM_TYPE_IPV6,
1152 RTE_FLOW_ITEM_TYPE_SCTP,
1153 RTE_FLOW_ITEM_TYPE_RAW,
1154 RTE_FLOW_ITEM_TYPE_RAW,
1155 RTE_FLOW_ITEM_TYPE_RAW,
1156 RTE_FLOW_ITEM_TYPE_VF,
1157 RTE_FLOW_ITEM_TYPE_END,
1160 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1161 RTE_FLOW_ITEM_TYPE_ETH,
1162 RTE_FLOW_ITEM_TYPE_VLAN,
1163 RTE_FLOW_ITEM_TYPE_VF,
1164 RTE_FLOW_ITEM_TYPE_END,
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1168 RTE_FLOW_ITEM_TYPE_ETH,
1169 RTE_FLOW_ITEM_TYPE_VLAN,
1170 RTE_FLOW_ITEM_TYPE_IPV4,
1171 RTE_FLOW_ITEM_TYPE_VF,
1172 RTE_FLOW_ITEM_TYPE_END,
1175 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1176 RTE_FLOW_ITEM_TYPE_ETH,
1177 RTE_FLOW_ITEM_TYPE_VLAN,
1178 RTE_FLOW_ITEM_TYPE_IPV4,
1179 RTE_FLOW_ITEM_TYPE_UDP,
1180 RTE_FLOW_ITEM_TYPE_VF,
1181 RTE_FLOW_ITEM_TYPE_END,
1184 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1185 RTE_FLOW_ITEM_TYPE_ETH,
1186 RTE_FLOW_ITEM_TYPE_VLAN,
1187 RTE_FLOW_ITEM_TYPE_IPV4,
1188 RTE_FLOW_ITEM_TYPE_TCP,
1189 RTE_FLOW_ITEM_TYPE_VF,
1190 RTE_FLOW_ITEM_TYPE_END,
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1194 RTE_FLOW_ITEM_TYPE_ETH,
1195 RTE_FLOW_ITEM_TYPE_VLAN,
1196 RTE_FLOW_ITEM_TYPE_IPV4,
1197 RTE_FLOW_ITEM_TYPE_SCTP,
1198 RTE_FLOW_ITEM_TYPE_VF,
1199 RTE_FLOW_ITEM_TYPE_END,
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1203 RTE_FLOW_ITEM_TYPE_ETH,
1204 RTE_FLOW_ITEM_TYPE_VLAN,
1205 RTE_FLOW_ITEM_TYPE_IPV6,
1206 RTE_FLOW_ITEM_TYPE_VF,
1207 RTE_FLOW_ITEM_TYPE_END,
1210 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1211 RTE_FLOW_ITEM_TYPE_ETH,
1212 RTE_FLOW_ITEM_TYPE_VLAN,
1213 RTE_FLOW_ITEM_TYPE_IPV6,
1214 RTE_FLOW_ITEM_TYPE_UDP,
1215 RTE_FLOW_ITEM_TYPE_VF,
1216 RTE_FLOW_ITEM_TYPE_END,
1219 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1220 RTE_FLOW_ITEM_TYPE_ETH,
1221 RTE_FLOW_ITEM_TYPE_VLAN,
1222 RTE_FLOW_ITEM_TYPE_IPV6,
1223 RTE_FLOW_ITEM_TYPE_TCP,
1224 RTE_FLOW_ITEM_TYPE_VF,
1225 RTE_FLOW_ITEM_TYPE_END,
1228 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1229 RTE_FLOW_ITEM_TYPE_ETH,
1230 RTE_FLOW_ITEM_TYPE_VLAN,
1231 RTE_FLOW_ITEM_TYPE_IPV6,
1232 RTE_FLOW_ITEM_TYPE_SCTP,
1233 RTE_FLOW_ITEM_TYPE_VF,
1234 RTE_FLOW_ITEM_TYPE_END,
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1238 RTE_FLOW_ITEM_TYPE_ETH,
1239 RTE_FLOW_ITEM_TYPE_VLAN,
1240 RTE_FLOW_ITEM_TYPE_RAW,
1241 RTE_FLOW_ITEM_TYPE_VF,
1242 RTE_FLOW_ITEM_TYPE_END,
1245 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1246 RTE_FLOW_ITEM_TYPE_ETH,
1247 RTE_FLOW_ITEM_TYPE_VLAN,
1248 RTE_FLOW_ITEM_TYPE_RAW,
1249 RTE_FLOW_ITEM_TYPE_RAW,
1250 RTE_FLOW_ITEM_TYPE_VF,
1251 RTE_FLOW_ITEM_TYPE_END,
1254 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1255 RTE_FLOW_ITEM_TYPE_ETH,
1256 RTE_FLOW_ITEM_TYPE_VLAN,
1257 RTE_FLOW_ITEM_TYPE_RAW,
1258 RTE_FLOW_ITEM_TYPE_RAW,
1259 RTE_FLOW_ITEM_TYPE_RAW,
1260 RTE_FLOW_ITEM_TYPE_VF,
1261 RTE_FLOW_ITEM_TYPE_END,
1264 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1265 RTE_FLOW_ITEM_TYPE_ETH,
1266 RTE_FLOW_ITEM_TYPE_VLAN,
1267 RTE_FLOW_ITEM_TYPE_IPV4,
1268 RTE_FLOW_ITEM_TYPE_RAW,
1269 RTE_FLOW_ITEM_TYPE_VF,
1270 RTE_FLOW_ITEM_TYPE_END,
1273 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1274 RTE_FLOW_ITEM_TYPE_ETH,
1275 RTE_FLOW_ITEM_TYPE_VLAN,
1276 RTE_FLOW_ITEM_TYPE_IPV4,
1277 RTE_FLOW_ITEM_TYPE_RAW,
1278 RTE_FLOW_ITEM_TYPE_RAW,
1279 RTE_FLOW_ITEM_TYPE_VF,
1280 RTE_FLOW_ITEM_TYPE_END,
1283 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1284 RTE_FLOW_ITEM_TYPE_ETH,
1285 RTE_FLOW_ITEM_TYPE_VLAN,
1286 RTE_FLOW_ITEM_TYPE_IPV4,
1287 RTE_FLOW_ITEM_TYPE_RAW,
1288 RTE_FLOW_ITEM_TYPE_RAW,
1289 RTE_FLOW_ITEM_TYPE_RAW,
1290 RTE_FLOW_ITEM_TYPE_VF,
1291 RTE_FLOW_ITEM_TYPE_END,
1294 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1295 RTE_FLOW_ITEM_TYPE_ETH,
1296 RTE_FLOW_ITEM_TYPE_VLAN,
1297 RTE_FLOW_ITEM_TYPE_IPV4,
1298 RTE_FLOW_ITEM_TYPE_UDP,
1299 RTE_FLOW_ITEM_TYPE_RAW,
1300 RTE_FLOW_ITEM_TYPE_VF,
1301 RTE_FLOW_ITEM_TYPE_END,
1304 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1305 RTE_FLOW_ITEM_TYPE_ETH,
1306 RTE_FLOW_ITEM_TYPE_VLAN,
1307 RTE_FLOW_ITEM_TYPE_IPV4,
1308 RTE_FLOW_ITEM_TYPE_UDP,
1309 RTE_FLOW_ITEM_TYPE_RAW,
1310 RTE_FLOW_ITEM_TYPE_RAW,
1311 RTE_FLOW_ITEM_TYPE_VF,
1312 RTE_FLOW_ITEM_TYPE_END,
1315 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1316 RTE_FLOW_ITEM_TYPE_ETH,
1317 RTE_FLOW_ITEM_TYPE_VLAN,
1318 RTE_FLOW_ITEM_TYPE_IPV4,
1319 RTE_FLOW_ITEM_TYPE_UDP,
1320 RTE_FLOW_ITEM_TYPE_RAW,
1321 RTE_FLOW_ITEM_TYPE_RAW,
1322 RTE_FLOW_ITEM_TYPE_RAW,
1323 RTE_FLOW_ITEM_TYPE_VF,
1324 RTE_FLOW_ITEM_TYPE_END,
1327 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1328 RTE_FLOW_ITEM_TYPE_ETH,
1329 RTE_FLOW_ITEM_TYPE_VLAN,
1330 RTE_FLOW_ITEM_TYPE_IPV4,
1331 RTE_FLOW_ITEM_TYPE_TCP,
1332 RTE_FLOW_ITEM_TYPE_RAW,
1333 RTE_FLOW_ITEM_TYPE_VF,
1334 RTE_FLOW_ITEM_TYPE_END,
1337 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1338 RTE_FLOW_ITEM_TYPE_ETH,
1339 RTE_FLOW_ITEM_TYPE_VLAN,
1340 RTE_FLOW_ITEM_TYPE_IPV4,
1341 RTE_FLOW_ITEM_TYPE_TCP,
1342 RTE_FLOW_ITEM_TYPE_RAW,
1343 RTE_FLOW_ITEM_TYPE_RAW,
1344 RTE_FLOW_ITEM_TYPE_VF,
1345 RTE_FLOW_ITEM_TYPE_END,
1348 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1349 RTE_FLOW_ITEM_TYPE_ETH,
1350 RTE_FLOW_ITEM_TYPE_VLAN,
1351 RTE_FLOW_ITEM_TYPE_IPV4,
1352 RTE_FLOW_ITEM_TYPE_TCP,
1353 RTE_FLOW_ITEM_TYPE_RAW,
1354 RTE_FLOW_ITEM_TYPE_RAW,
1355 RTE_FLOW_ITEM_TYPE_RAW,
1356 RTE_FLOW_ITEM_TYPE_VF,
1357 RTE_FLOW_ITEM_TYPE_END,
1360 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1361 RTE_FLOW_ITEM_TYPE_ETH,
1362 RTE_FLOW_ITEM_TYPE_VLAN,
1363 RTE_FLOW_ITEM_TYPE_IPV4,
1364 RTE_FLOW_ITEM_TYPE_SCTP,
1365 RTE_FLOW_ITEM_TYPE_RAW,
1366 RTE_FLOW_ITEM_TYPE_VF,
1367 RTE_FLOW_ITEM_TYPE_END,
1370 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1371 RTE_FLOW_ITEM_TYPE_ETH,
1372 RTE_FLOW_ITEM_TYPE_VLAN,
1373 RTE_FLOW_ITEM_TYPE_IPV4,
1374 RTE_FLOW_ITEM_TYPE_SCTP,
1375 RTE_FLOW_ITEM_TYPE_RAW,
1376 RTE_FLOW_ITEM_TYPE_RAW,
1377 RTE_FLOW_ITEM_TYPE_VF,
1378 RTE_FLOW_ITEM_TYPE_END,
1381 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1382 RTE_FLOW_ITEM_TYPE_ETH,
1383 RTE_FLOW_ITEM_TYPE_VLAN,
1384 RTE_FLOW_ITEM_TYPE_IPV4,
1385 RTE_FLOW_ITEM_TYPE_SCTP,
1386 RTE_FLOW_ITEM_TYPE_RAW,
1387 RTE_FLOW_ITEM_TYPE_RAW,
1388 RTE_FLOW_ITEM_TYPE_RAW,
1389 RTE_FLOW_ITEM_TYPE_VF,
1390 RTE_FLOW_ITEM_TYPE_END,
1393 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1394 RTE_FLOW_ITEM_TYPE_ETH,
1395 RTE_FLOW_ITEM_TYPE_VLAN,
1396 RTE_FLOW_ITEM_TYPE_IPV6,
1397 RTE_FLOW_ITEM_TYPE_RAW,
1398 RTE_FLOW_ITEM_TYPE_VF,
1399 RTE_FLOW_ITEM_TYPE_END,
1402 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1403 RTE_FLOW_ITEM_TYPE_ETH,
1404 RTE_FLOW_ITEM_TYPE_VLAN,
1405 RTE_FLOW_ITEM_TYPE_IPV6,
1406 RTE_FLOW_ITEM_TYPE_RAW,
1407 RTE_FLOW_ITEM_TYPE_RAW,
1408 RTE_FLOW_ITEM_TYPE_VF,
1409 RTE_FLOW_ITEM_TYPE_END,
1412 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1413 RTE_FLOW_ITEM_TYPE_ETH,
1414 RTE_FLOW_ITEM_TYPE_VLAN,
1415 RTE_FLOW_ITEM_TYPE_IPV6,
1416 RTE_FLOW_ITEM_TYPE_RAW,
1417 RTE_FLOW_ITEM_TYPE_RAW,
1418 RTE_FLOW_ITEM_TYPE_RAW,
1419 RTE_FLOW_ITEM_TYPE_VF,
1420 RTE_FLOW_ITEM_TYPE_END,
1423 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1424 RTE_FLOW_ITEM_TYPE_ETH,
1425 RTE_FLOW_ITEM_TYPE_VLAN,
1426 RTE_FLOW_ITEM_TYPE_IPV6,
1427 RTE_FLOW_ITEM_TYPE_UDP,
1428 RTE_FLOW_ITEM_TYPE_RAW,
1429 RTE_FLOW_ITEM_TYPE_VF,
1430 RTE_FLOW_ITEM_TYPE_END,
1433 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1434 RTE_FLOW_ITEM_TYPE_ETH,
1435 RTE_FLOW_ITEM_TYPE_VLAN,
1436 RTE_FLOW_ITEM_TYPE_IPV6,
1437 RTE_FLOW_ITEM_TYPE_UDP,
1438 RTE_FLOW_ITEM_TYPE_RAW,
1439 RTE_FLOW_ITEM_TYPE_RAW,
1440 RTE_FLOW_ITEM_TYPE_VF,
1441 RTE_FLOW_ITEM_TYPE_END,
1444 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1445 RTE_FLOW_ITEM_TYPE_ETH,
1446 RTE_FLOW_ITEM_TYPE_VLAN,
1447 RTE_FLOW_ITEM_TYPE_IPV6,
1448 RTE_FLOW_ITEM_TYPE_UDP,
1449 RTE_FLOW_ITEM_TYPE_RAW,
1450 RTE_FLOW_ITEM_TYPE_RAW,
1451 RTE_FLOW_ITEM_TYPE_RAW,
1452 RTE_FLOW_ITEM_TYPE_VF,
1453 RTE_FLOW_ITEM_TYPE_END,
1456 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1457 RTE_FLOW_ITEM_TYPE_ETH,
1458 RTE_FLOW_ITEM_TYPE_VLAN,
1459 RTE_FLOW_ITEM_TYPE_IPV6,
1460 RTE_FLOW_ITEM_TYPE_TCP,
1461 RTE_FLOW_ITEM_TYPE_RAW,
1462 RTE_FLOW_ITEM_TYPE_VF,
1463 RTE_FLOW_ITEM_TYPE_END,
1466 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1467 RTE_FLOW_ITEM_TYPE_ETH,
1468 RTE_FLOW_ITEM_TYPE_VLAN,
1469 RTE_FLOW_ITEM_TYPE_IPV6,
1470 RTE_FLOW_ITEM_TYPE_TCP,
1471 RTE_FLOW_ITEM_TYPE_RAW,
1472 RTE_FLOW_ITEM_TYPE_RAW,
1473 RTE_FLOW_ITEM_TYPE_VF,
1474 RTE_FLOW_ITEM_TYPE_END,
1477 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1478 RTE_FLOW_ITEM_TYPE_ETH,
1479 RTE_FLOW_ITEM_TYPE_VLAN,
1480 RTE_FLOW_ITEM_TYPE_IPV6,
1481 RTE_FLOW_ITEM_TYPE_TCP,
1482 RTE_FLOW_ITEM_TYPE_RAW,
1483 RTE_FLOW_ITEM_TYPE_RAW,
1484 RTE_FLOW_ITEM_TYPE_RAW,
1485 RTE_FLOW_ITEM_TYPE_VF,
1486 RTE_FLOW_ITEM_TYPE_END,
1489 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1490 RTE_FLOW_ITEM_TYPE_ETH,
1491 RTE_FLOW_ITEM_TYPE_VLAN,
1492 RTE_FLOW_ITEM_TYPE_IPV6,
1493 RTE_FLOW_ITEM_TYPE_SCTP,
1494 RTE_FLOW_ITEM_TYPE_RAW,
1495 RTE_FLOW_ITEM_TYPE_VF,
1496 RTE_FLOW_ITEM_TYPE_END,
1499 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1500 RTE_FLOW_ITEM_TYPE_ETH,
1501 RTE_FLOW_ITEM_TYPE_VLAN,
1502 RTE_FLOW_ITEM_TYPE_IPV6,
1503 RTE_FLOW_ITEM_TYPE_SCTP,
1504 RTE_FLOW_ITEM_TYPE_RAW,
1505 RTE_FLOW_ITEM_TYPE_RAW,
1506 RTE_FLOW_ITEM_TYPE_VF,
1507 RTE_FLOW_ITEM_TYPE_END,
1510 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1511 RTE_FLOW_ITEM_TYPE_ETH,
1512 RTE_FLOW_ITEM_TYPE_VLAN,
1513 RTE_FLOW_ITEM_TYPE_IPV6,
1514 RTE_FLOW_ITEM_TYPE_SCTP,
1515 RTE_FLOW_ITEM_TYPE_RAW,
1516 RTE_FLOW_ITEM_TYPE_RAW,
1517 RTE_FLOW_ITEM_TYPE_RAW,
1518 RTE_FLOW_ITEM_TYPE_VF,
1519 RTE_FLOW_ITEM_TYPE_END,
1522 /* Pattern matched tunnel filter */
1523 static enum rte_flow_item_type pattern_vxlan_1[] = {
1524 RTE_FLOW_ITEM_TYPE_ETH,
1525 RTE_FLOW_ITEM_TYPE_IPV4,
1526 RTE_FLOW_ITEM_TYPE_UDP,
1527 RTE_FLOW_ITEM_TYPE_VXLAN,
1528 RTE_FLOW_ITEM_TYPE_ETH,
1529 RTE_FLOW_ITEM_TYPE_END,
1532 static enum rte_flow_item_type pattern_vxlan_2[] = {
1533 RTE_FLOW_ITEM_TYPE_ETH,
1534 RTE_FLOW_ITEM_TYPE_IPV6,
1535 RTE_FLOW_ITEM_TYPE_UDP,
1536 RTE_FLOW_ITEM_TYPE_VXLAN,
1537 RTE_FLOW_ITEM_TYPE_ETH,
1538 RTE_FLOW_ITEM_TYPE_END,
1541 static enum rte_flow_item_type pattern_vxlan_3[] = {
1542 RTE_FLOW_ITEM_TYPE_ETH,
1543 RTE_FLOW_ITEM_TYPE_IPV4,
1544 RTE_FLOW_ITEM_TYPE_UDP,
1545 RTE_FLOW_ITEM_TYPE_VXLAN,
1546 RTE_FLOW_ITEM_TYPE_ETH,
1547 RTE_FLOW_ITEM_TYPE_VLAN,
1548 RTE_FLOW_ITEM_TYPE_END,
1551 static enum rte_flow_item_type pattern_vxlan_4[] = {
1552 RTE_FLOW_ITEM_TYPE_ETH,
1553 RTE_FLOW_ITEM_TYPE_IPV6,
1554 RTE_FLOW_ITEM_TYPE_UDP,
1555 RTE_FLOW_ITEM_TYPE_VXLAN,
1556 RTE_FLOW_ITEM_TYPE_ETH,
1557 RTE_FLOW_ITEM_TYPE_VLAN,
1558 RTE_FLOW_ITEM_TYPE_END,
1561 static enum rte_flow_item_type pattern_nvgre_1[] = {
1562 RTE_FLOW_ITEM_TYPE_ETH,
1563 RTE_FLOW_ITEM_TYPE_IPV4,
1564 RTE_FLOW_ITEM_TYPE_NVGRE,
1565 RTE_FLOW_ITEM_TYPE_ETH,
1566 RTE_FLOW_ITEM_TYPE_END,
1569 static enum rte_flow_item_type pattern_nvgre_2[] = {
1570 RTE_FLOW_ITEM_TYPE_ETH,
1571 RTE_FLOW_ITEM_TYPE_IPV6,
1572 RTE_FLOW_ITEM_TYPE_NVGRE,
1573 RTE_FLOW_ITEM_TYPE_ETH,
1574 RTE_FLOW_ITEM_TYPE_END,
1577 static enum rte_flow_item_type pattern_nvgre_3[] = {
1578 RTE_FLOW_ITEM_TYPE_ETH,
1579 RTE_FLOW_ITEM_TYPE_IPV4,
1580 RTE_FLOW_ITEM_TYPE_NVGRE,
1581 RTE_FLOW_ITEM_TYPE_ETH,
1582 RTE_FLOW_ITEM_TYPE_VLAN,
1583 RTE_FLOW_ITEM_TYPE_END,
1586 static enum rte_flow_item_type pattern_nvgre_4[] = {
1587 RTE_FLOW_ITEM_TYPE_ETH,
1588 RTE_FLOW_ITEM_TYPE_IPV6,
1589 RTE_FLOW_ITEM_TYPE_NVGRE,
1590 RTE_FLOW_ITEM_TYPE_ETH,
1591 RTE_FLOW_ITEM_TYPE_VLAN,
1592 RTE_FLOW_ITEM_TYPE_END,
1595 static enum rte_flow_item_type pattern_mpls_1[] = {
1596 RTE_FLOW_ITEM_TYPE_ETH,
1597 RTE_FLOW_ITEM_TYPE_IPV4,
1598 RTE_FLOW_ITEM_TYPE_UDP,
1599 RTE_FLOW_ITEM_TYPE_MPLS,
1600 RTE_FLOW_ITEM_TYPE_END,
1603 static enum rte_flow_item_type pattern_mpls_2[] = {
1604 RTE_FLOW_ITEM_TYPE_ETH,
1605 RTE_FLOW_ITEM_TYPE_IPV6,
1606 RTE_FLOW_ITEM_TYPE_UDP,
1607 RTE_FLOW_ITEM_TYPE_MPLS,
1608 RTE_FLOW_ITEM_TYPE_END,
1611 static enum rte_flow_item_type pattern_mpls_3[] = {
1612 RTE_FLOW_ITEM_TYPE_ETH,
1613 RTE_FLOW_ITEM_TYPE_IPV4,
1614 RTE_FLOW_ITEM_TYPE_GRE,
1615 RTE_FLOW_ITEM_TYPE_MPLS,
1616 RTE_FLOW_ITEM_TYPE_END,
1619 static enum rte_flow_item_type pattern_mpls_4[] = {
1620 RTE_FLOW_ITEM_TYPE_ETH,
1621 RTE_FLOW_ITEM_TYPE_IPV6,
1622 RTE_FLOW_ITEM_TYPE_GRE,
1623 RTE_FLOW_ITEM_TYPE_MPLS,
1624 RTE_FLOW_ITEM_TYPE_END,
1627 static enum rte_flow_item_type pattern_qinq_1[] = {
1628 RTE_FLOW_ITEM_TYPE_ETH,
1629 RTE_FLOW_ITEM_TYPE_VLAN,
1630 RTE_FLOW_ITEM_TYPE_VLAN,
1631 RTE_FLOW_ITEM_TYPE_END,
1634 static enum rte_flow_item_type pattern_fdir_ipv4_l2tpv3oip[] = {
1635 RTE_FLOW_ITEM_TYPE_ETH,
1636 RTE_FLOW_ITEM_TYPE_IPV4,
1637 RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1638 RTE_FLOW_ITEM_TYPE_END,
1641 static enum rte_flow_item_type pattern_fdir_ipv6_l2tpv3oip[] = {
1642 RTE_FLOW_ITEM_TYPE_ETH,
1643 RTE_FLOW_ITEM_TYPE_IPV6,
1644 RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1645 RTE_FLOW_ITEM_TYPE_END,
1648 static enum rte_flow_item_type pattern_fdir_ipv4_esp[] = {
1649 RTE_FLOW_ITEM_TYPE_ETH,
1650 RTE_FLOW_ITEM_TYPE_IPV4,
1651 RTE_FLOW_ITEM_TYPE_ESP,
1652 RTE_FLOW_ITEM_TYPE_END,
1655 static enum rte_flow_item_type pattern_fdir_ipv6_esp[] = {
1656 RTE_FLOW_ITEM_TYPE_ETH,
1657 RTE_FLOW_ITEM_TYPE_IPV6,
1658 RTE_FLOW_ITEM_TYPE_ESP,
1659 RTE_FLOW_ITEM_TYPE_END,
1662 static enum rte_flow_item_type pattern_fdir_ipv4_udp_esp[] = {
1663 RTE_FLOW_ITEM_TYPE_ETH,
1664 RTE_FLOW_ITEM_TYPE_IPV4,
1665 RTE_FLOW_ITEM_TYPE_UDP,
1666 RTE_FLOW_ITEM_TYPE_ESP,
1667 RTE_FLOW_ITEM_TYPE_END,
1670 static enum rte_flow_item_type pattern_fdir_ipv6_udp_esp[] = {
1671 RTE_FLOW_ITEM_TYPE_ETH,
1672 RTE_FLOW_ITEM_TYPE_IPV6,
1673 RTE_FLOW_ITEM_TYPE_UDP,
1674 RTE_FLOW_ITEM_TYPE_ESP,
1675 RTE_FLOW_ITEM_TYPE_END,
1678 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1680 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1681 /* FDIR - support default flow type without flexible payload*/
1682 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_ipv4_esp, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_ipv4_udp_esp, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_ipv6_esp, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_ipv6_udp_esp, i40e_flow_parse_fdir_filter },
1703 /* FDIR - support default flow type with flexible payload */
1704 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1705 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1729 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1730 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1731 /* FDIR - support single vlan input set */
1732 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1751 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1752 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1768 /* FDIR - support VF item */
1769 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1775 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1776 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1777 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1778 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1779 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1780 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1781 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1782 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1783 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1784 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1785 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1786 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1787 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1788 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1789 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1790 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1791 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1792 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1793 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1794 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1795 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1796 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1797 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1798 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1799 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1800 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1801 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1802 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1803 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1804 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1805 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1806 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1807 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1808 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1809 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1810 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1811 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1812 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1813 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1814 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1815 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1816 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1817 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1818 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1819 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1820 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1821 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1822 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1823 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1824 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1825 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1826 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1827 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1828 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1829 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1830 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1831 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1832 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1833 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1834 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1835 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1836 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1837 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1838 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1839 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1841 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1842 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1843 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1844 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1846 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1847 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1848 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1849 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1850 /* MPLSoUDP & MPLSoGRE */
1851 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1852 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1853 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1854 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1856 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1857 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1858 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1859 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1861 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1862 /* L2TPv3 over IP */
1863 { pattern_fdir_ipv4_l2tpv3oip, i40e_flow_parse_fdir_filter },
1864 { pattern_fdir_ipv6_l2tpv3oip, i40e_flow_parse_fdir_filter },
1866 { pattern_fdir_ipv4_udp, i40e_flow_parse_l4_cloud_filter },
1867 { pattern_fdir_ipv4_tcp, i40e_flow_parse_l4_cloud_filter },
1868 { pattern_fdir_ipv4_sctp, i40e_flow_parse_l4_cloud_filter },
1869 { pattern_fdir_ipv6_udp, i40e_flow_parse_l4_cloud_filter },
1870 { pattern_fdir_ipv6_tcp, i40e_flow_parse_l4_cloud_filter },
1871 { pattern_fdir_ipv6_sctp, i40e_flow_parse_l4_cloud_filter },
1874 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1876 act = actions + index; \
1877 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1879 act = actions + index; \
1883 /* Find the first VOID or non-VOID item pointer */
1884 static const struct rte_flow_item *
1885 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1889 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1891 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1893 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1901 /* Skip all VOID items of the pattern */
1903 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1904 const struct rte_flow_item *pattern)
1906 uint32_t cpy_count = 0;
1907 const struct rte_flow_item *pb = pattern, *pe = pattern;
1910 /* Find a non-void item first */
1911 pb = i40e_find_first_item(pb, false);
1912 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1917 /* Find a void item */
1918 pe = i40e_find_first_item(pb + 1, true);
1920 cpy_count = pe - pb;
1921 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1925 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1932 /* Copy the END item. */
1933 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1936 /* Check if the pattern matches a supported item type array */
1938 i40e_match_pattern(enum rte_flow_item_type *item_array,
1939 struct rte_flow_item *pattern)
1941 struct rte_flow_item *item = pattern;
1943 while ((*item_array == item->type) &&
1944 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1949 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1950 item->type == RTE_FLOW_ITEM_TYPE_END);
1953 /* Find if there's parse filter function matched */
1954 static parse_filter_t
1955 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1957 parse_filter_t parse_filter = NULL;
1960 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1961 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1963 parse_filter = i40e_supported_patterns[i].parse_filter;
1970 return parse_filter;
1973 /* Parse attributes */
1975 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1976 struct rte_flow_error *error)
1978 /* Must be input direction */
1979 if (!attr->ingress) {
1980 rte_flow_error_set(error, EINVAL,
1981 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1982 attr, "Only support ingress.");
1988 rte_flow_error_set(error, EINVAL,
1989 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1990 attr, "Not support egress.");
1995 if (attr->priority) {
1996 rte_flow_error_set(error, EINVAL,
1997 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1998 attr, "Not support priority.");
2004 rte_flow_error_set(error, EINVAL,
2005 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
2006 attr, "Not support group.");
2014 i40e_get_outer_vlan(struct rte_eth_dev *dev)
2016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017 int qinq = dev->data->dev_conf.rxmode.offloads &
2018 DEV_RX_OFFLOAD_VLAN_EXTEND;
2028 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2031 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
2036 /* 1. Last in item should be NULL as range is not supported.
2037 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
2038 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
2039 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
2041 * 5. Ether_type mask should be 0xFFFF.
2044 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
2045 const struct rte_flow_item *pattern,
2046 struct rte_flow_error *error,
2047 struct rte_eth_ethertype_filter *filter)
2049 const struct rte_flow_item *item = pattern;
2050 const struct rte_flow_item_eth *eth_spec;
2051 const struct rte_flow_item_eth *eth_mask;
2052 enum rte_flow_item_type item_type;
2054 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2056 rte_flow_error_set(error, EINVAL,
2057 RTE_FLOW_ERROR_TYPE_ITEM,
2059 "Not support range");
2062 item_type = item->type;
2063 switch (item_type) {
2064 case RTE_FLOW_ITEM_TYPE_ETH:
2065 eth_spec = item->spec;
2066 eth_mask = item->mask;
2067 /* Get the MAC info. */
2068 if (!eth_spec || !eth_mask) {
2069 rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ITEM,
2072 "NULL ETH spec/mask");
2076 /* Mask bits of source MAC address must be full of 0.
2077 * Mask bits of destination MAC address must be full
2078 * of 1 or full of 0.
2080 if (!rte_is_zero_ether_addr(ð_mask->src) ||
2081 (!rte_is_zero_ether_addr(ð_mask->dst) &&
2082 !rte_is_broadcast_ether_addr(ð_mask->dst))) {
2083 rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ITEM,
2086 "Invalid MAC_addr mask");
2090 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2091 rte_flow_error_set(error, EINVAL,
2092 RTE_FLOW_ERROR_TYPE_ITEM,
2094 "Invalid ethertype mask");
2098 /* If mask bits of destination MAC address
2099 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2101 if (rte_is_broadcast_ether_addr(ð_mask->dst)) {
2102 filter->mac_addr = eth_spec->dst;
2103 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2105 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2107 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2109 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2110 filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2111 filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2112 filter->ether_type == i40e_get_outer_vlan(dev)) {
2113 rte_flow_error_set(error, EINVAL,
2114 RTE_FLOW_ERROR_TYPE_ITEM,
2116 "Unsupported ether_type in"
2117 " control packet filter.");
2129 /* Ethertype action only supports QUEUE or DROP. */
2131 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2132 const struct rte_flow_action *actions,
2133 struct rte_flow_error *error,
2134 struct rte_eth_ethertype_filter *filter)
2136 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2137 const struct rte_flow_action *act;
2138 const struct rte_flow_action_queue *act_q;
2141 /* Check if the first non-void action is QUEUE or DROP. */
2142 NEXT_ITEM_OF_ACTION(act, actions, index);
2143 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2144 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2145 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2146 act, "Not supported action.");
2150 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2152 filter->queue = act_q->index;
2153 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2154 rte_flow_error_set(error, EINVAL,
2155 RTE_FLOW_ERROR_TYPE_ACTION,
2156 act, "Invalid queue ID for"
2157 " ethertype_filter.");
2161 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2164 /* Check if the next non-void item is END */
2166 NEXT_ITEM_OF_ACTION(act, actions, index);
2167 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2168 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2169 act, "Not supported action.");
2177 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2178 const struct rte_flow_attr *attr,
2179 const struct rte_flow_item pattern[],
2180 const struct rte_flow_action actions[],
2181 struct rte_flow_error *error,
2182 union i40e_filter_t *filter)
2184 struct rte_eth_ethertype_filter *ethertype_filter =
2185 &filter->ethertype_filter;
2188 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2193 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2198 ret = i40e_flow_parse_attr(attr, error);
2202 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2208 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2209 const struct rte_flow_item_raw *raw_spec,
2210 struct rte_flow_error *error)
2212 if (!raw_spec->relative) {
2213 rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ITEM,
2216 "Relative should be 1.");
2220 if (raw_spec->offset % sizeof(uint16_t)) {
2221 rte_flow_error_set(error, EINVAL,
2222 RTE_FLOW_ERROR_TYPE_ITEM,
2224 "Offset should be even.");
2228 if (raw_spec->search || raw_spec->limit) {
2229 rte_flow_error_set(error, EINVAL,
2230 RTE_FLOW_ERROR_TYPE_ITEM,
2232 "search or limit is not supported.");
2236 if (raw_spec->offset < 0) {
2237 rte_flow_error_set(error, EINVAL,
2238 RTE_FLOW_ERROR_TYPE_ITEM,
2240 "Offset should be non-negative.");
2247 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2248 enum i40e_filter_pctype pctype,
2251 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2252 uint64_t inset_reg = 0;
2253 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2256 /* Check if the input set is valid */
2257 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2259 PMD_DRV_LOG(ERR, "Invalid input set");
2263 /* Check if the configuration is conflicted */
2264 if (pf->fdir.inset_flag[pctype] &&
2265 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2268 if (pf->fdir.inset_flag[pctype] &&
2269 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2272 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2273 I40E_INSET_MASK_NUM_REG);
2277 if (pf->support_multi_driver) {
2278 for (i = 0; i < num; i++)
2279 if (i40e_read_rx_ctl(hw,
2280 I40E_GLQF_FD_MSK(i, pctype)) !=
2282 PMD_DRV_LOG(ERR, "Input set setting is not"
2284 " `support-multi-driver`"
2288 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2289 if (i40e_read_rx_ctl(hw,
2290 I40E_GLQF_FD_MSK(i, pctype)) != 0) {
2291 PMD_DRV_LOG(ERR, "Input set setting is not"
2293 " `support-multi-driver`"
2299 for (i = 0; i < num; i++)
2300 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2302 /*clear unused mask registers of the pctype */
2303 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2304 i40e_check_write_reg(hw,
2305 I40E_GLQF_FD_MSK(i, pctype), 0);
2308 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2310 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2311 (uint32_t)(inset_reg & UINT32_MAX));
2312 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2313 (uint32_t)((inset_reg >>
2314 I40E_32_BIT_WIDTH) & UINT32_MAX));
2316 I40E_WRITE_FLUSH(hw);
2318 pf->fdir.input_set[pctype] = input_set;
2319 pf->fdir.inset_flag[pctype] = 1;
2324 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2325 enum rte_flow_item_type item_type,
2326 struct i40e_fdir_filter_conf *filter)
2328 struct i40e_customized_pctype *cus_pctype = NULL;
2330 switch (item_type) {
2331 case RTE_FLOW_ITEM_TYPE_GTPC:
2332 cus_pctype = i40e_find_customized_pctype(pf,
2333 I40E_CUSTOMIZED_GTPC);
2335 case RTE_FLOW_ITEM_TYPE_GTPU:
2336 if (!filter->input.flow_ext.inner_ip)
2337 cus_pctype = i40e_find_customized_pctype(pf,
2338 I40E_CUSTOMIZED_GTPU);
2339 else if (filter->input.flow_ext.iip_type ==
2340 I40E_FDIR_IPTYPE_IPV4)
2341 cus_pctype = i40e_find_customized_pctype(pf,
2342 I40E_CUSTOMIZED_GTPU_IPV4);
2343 else if (filter->input.flow_ext.iip_type ==
2344 I40E_FDIR_IPTYPE_IPV6)
2345 cus_pctype = i40e_find_customized_pctype(pf,
2346 I40E_CUSTOMIZED_GTPU_IPV6);
2348 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
2349 if (filter->input.flow_ext.oip_type == I40E_FDIR_IPTYPE_IPV4)
2350 cus_pctype = i40e_find_customized_pctype(pf,
2351 I40E_CUSTOMIZED_IPV4_L2TPV3);
2352 else if (filter->input.flow_ext.oip_type ==
2353 I40E_FDIR_IPTYPE_IPV6)
2354 cus_pctype = i40e_find_customized_pctype(pf,
2355 I40E_CUSTOMIZED_IPV6_L2TPV3);
2357 case RTE_FLOW_ITEM_TYPE_ESP:
2358 if (!filter->input.flow_ext.is_udp) {
2359 if (filter->input.flow_ext.oip_type ==
2360 I40E_FDIR_IPTYPE_IPV4)
2361 cus_pctype = i40e_find_customized_pctype(pf,
2362 I40E_CUSTOMIZED_ESP_IPV4);
2363 else if (filter->input.flow_ext.oip_type ==
2364 I40E_FDIR_IPTYPE_IPV6)
2365 cus_pctype = i40e_find_customized_pctype(pf,
2366 I40E_CUSTOMIZED_ESP_IPV6);
2368 if (filter->input.flow_ext.oip_type ==
2369 I40E_FDIR_IPTYPE_IPV4)
2370 cus_pctype = i40e_find_customized_pctype(pf,
2371 I40E_CUSTOMIZED_ESP_IPV4_UDP);
2372 else if (filter->input.flow_ext.oip_type ==
2373 I40E_FDIR_IPTYPE_IPV6)
2374 cus_pctype = i40e_find_customized_pctype(pf,
2375 I40E_CUSTOMIZED_ESP_IPV6_UDP);
2376 filter->input.flow_ext.is_udp = false;
2380 PMD_DRV_LOG(ERR, "Unsupported item type");
2384 if (cus_pctype && cus_pctype->valid)
2385 return cus_pctype->pctype;
2387 return I40E_FILTER_PCTYPE_INVALID;
2391 i40e_flow_set_filter_spi(struct i40e_fdir_filter_conf *filter,
2392 const struct rte_flow_item_esp *esp_spec)
2394 if (filter->input.flow_ext.oip_type ==
2395 I40E_FDIR_IPTYPE_IPV4) {
2396 if (filter->input.flow_ext.is_udp)
2397 filter->input.flow.esp_ipv4_udp_flow.spi =
2400 filter->input.flow.esp_ipv4_flow.spi =
2403 if (filter->input.flow_ext.oip_type ==
2404 I40E_FDIR_IPTYPE_IPV6) {
2405 if (filter->input.flow_ext.is_udp)
2406 filter->input.flow.esp_ipv6_udp_flow.spi =
2409 filter->input.flow.esp_ipv6_flow.spi =
2414 /* 1. Last in item should be NULL as range is not supported.
2415 * 2. Supported patterns: refer to array i40e_supported_patterns.
2416 * 3. Default supported flow type and input set: refer to array
2417 * valid_fdir_inset_table in i40e_ethdev.c.
2418 * 4. Mask of fields which need to be matched should be
2420 * 5. Mask of fields which needn't to be matched should be
2422 * 6. GTP profile supports GTPv1 only.
2423 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2426 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2427 const struct rte_flow_attr *attr,
2428 const struct rte_flow_item *pattern,
2429 struct rte_flow_error *error,
2430 struct i40e_fdir_filter_conf *filter)
2432 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2433 const struct rte_flow_item *item = pattern;
2434 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2435 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2436 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2437 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2438 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2439 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2440 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2441 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2442 const struct rte_flow_item_esp *esp_spec, *esp_mask;
2443 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2444 const struct rte_flow_item_vf *vf_spec;
2445 const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
2448 uint64_t input_set = I40E_INSET_NONE;
2450 enum rte_flow_item_type item_type;
2451 enum rte_flow_item_type next_type;
2452 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2453 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2455 uint8_t ipv6_addr_mask[16] = {
2456 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2457 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2458 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2460 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2461 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2462 struct i40e_fdir_flex_pit flex_pit;
2463 uint8_t next_dst_off = 0;
2465 uint16_t ether_type;
2466 uint32_t vtc_flow_cpu;
2467 bool outer_ip = true;
2471 memset(off_arr, 0, sizeof(off_arr));
2472 memset(len_arr, 0, sizeof(len_arr));
2473 filter->input.flow_ext.customized_pctype = false;
2474 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2476 rte_flow_error_set(error, EINVAL,
2477 RTE_FLOW_ERROR_TYPE_ITEM,
2479 "Not support range");
2482 item_type = item->type;
2483 switch (item_type) {
2484 case RTE_FLOW_ITEM_TYPE_ETH:
2485 eth_spec = item->spec;
2486 eth_mask = item->mask;
2487 next_type = (item + 1)->type;
2489 if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2490 (!eth_spec || !eth_mask)) {
2491 rte_flow_error_set(error, EINVAL,
2492 RTE_FLOW_ERROR_TYPE_ITEM,
2494 "NULL eth spec/mask.");
2498 if (eth_spec && eth_mask) {
2499 if (rte_is_broadcast_ether_addr(ð_mask->dst) &&
2500 rte_is_zero_ether_addr(ð_mask->src)) {
2501 filter->input.flow.l2_flow.dst =
2503 input_set |= I40E_INSET_DMAC;
2504 } else if (rte_is_zero_ether_addr(ð_mask->dst) &&
2505 rte_is_broadcast_ether_addr(ð_mask->src)) {
2506 filter->input.flow.l2_flow.src =
2508 input_set |= I40E_INSET_SMAC;
2509 } else if (rte_is_broadcast_ether_addr(ð_mask->dst) &&
2510 rte_is_broadcast_ether_addr(ð_mask->src)) {
2511 filter->input.flow.l2_flow.dst =
2513 filter->input.flow.l2_flow.src =
2515 input_set |= (I40E_INSET_DMAC | I40E_INSET_SMAC);
2516 } else if (!rte_is_zero_ether_addr(ð_mask->src) ||
2517 !rte_is_zero_ether_addr(ð_mask->dst)) {
2518 rte_flow_error_set(error, EINVAL,
2519 RTE_FLOW_ERROR_TYPE_ITEM,
2521 "Invalid MAC_addr mask.");
2525 if (eth_spec && eth_mask &&
2526 next_type == RTE_FLOW_ITEM_TYPE_END) {
2527 if (eth_mask->type != RTE_BE16(0xffff)) {
2528 rte_flow_error_set(error, EINVAL,
2529 RTE_FLOW_ERROR_TYPE_ITEM,
2531 "Invalid type mask.");
2535 ether_type = rte_be_to_cpu_16(eth_spec->type);
2537 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2538 ether_type == RTE_ETHER_TYPE_IPV4 ||
2539 ether_type == RTE_ETHER_TYPE_IPV6 ||
2540 ether_type == i40e_get_outer_vlan(dev)) {
2541 rte_flow_error_set(error, EINVAL,
2542 RTE_FLOW_ERROR_TYPE_ITEM,
2544 "Unsupported ether_type.");
2547 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2548 filter->input.flow.l2_flow.ether_type =
2552 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2553 layer_idx = I40E_FLXPLD_L2_IDX;
2556 case RTE_FLOW_ITEM_TYPE_VLAN:
2557 vlan_spec = item->spec;
2558 vlan_mask = item->mask;
2560 RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2561 if (vlan_spec && vlan_mask) {
2562 if (vlan_mask->tci !=
2563 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK) &&
2565 rte_cpu_to_be_16(I40E_VLAN_PRI_MASK) &&
2567 rte_cpu_to_be_16(I40E_VLAN_CFI_MASK) &&
2569 rte_cpu_to_be_16(I40E_VLAN_VID_MASK)) {
2570 rte_flow_error_set(error, EINVAL,
2571 RTE_FLOW_ERROR_TYPE_ITEM,
2573 "Unsupported TCI mask.");
2575 input_set |= I40E_INSET_VLAN_INNER;
2576 filter->input.flow_ext.vlan_tci =
2579 if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2580 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2581 rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ITEM,
2584 "Invalid inner_type"
2590 rte_be_to_cpu_16(vlan_spec->inner_type);
2592 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2593 ether_type == RTE_ETHER_TYPE_IPV6 ||
2594 ether_type == i40e_get_outer_vlan(dev)) {
2595 rte_flow_error_set(error, EINVAL,
2596 RTE_FLOW_ERROR_TYPE_ITEM,
2598 "Unsupported inner_type.");
2601 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2602 filter->input.flow.l2_flow.ether_type =
2603 vlan_spec->inner_type;
2606 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2607 layer_idx = I40E_FLXPLD_L2_IDX;
2610 case RTE_FLOW_ITEM_TYPE_IPV4:
2611 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2612 ipv4_spec = item->spec;
2613 ipv4_mask = item->mask;
2614 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2615 layer_idx = I40E_FLXPLD_L3_IDX;
2617 if (ipv4_spec && ipv4_mask && outer_ip) {
2618 /* Check IPv4 mask and update input set */
2619 if (ipv4_mask->hdr.version_ihl ||
2620 ipv4_mask->hdr.total_length ||
2621 ipv4_mask->hdr.packet_id ||
2622 ipv4_mask->hdr.fragment_offset ||
2623 ipv4_mask->hdr.hdr_checksum) {
2624 rte_flow_error_set(error, EINVAL,
2625 RTE_FLOW_ERROR_TYPE_ITEM,
2627 "Invalid IPv4 mask.");
2631 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2632 input_set |= I40E_INSET_IPV4_SRC;
2633 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2634 input_set |= I40E_INSET_IPV4_DST;
2635 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2636 input_set |= I40E_INSET_IPV4_TOS;
2637 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2638 input_set |= I40E_INSET_IPV4_TTL;
2639 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2640 input_set |= I40E_INSET_IPV4_PROTO;
2642 /* Check if it is fragment. */
2643 frag_off = ipv4_spec->hdr.fragment_offset;
2644 frag_off = rte_be_to_cpu_16(frag_off);
2645 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2646 frag_off & RTE_IPV4_HDR_MF_FLAG)
2647 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2649 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2650 if (input_set & (I40E_INSET_IPV4_SRC |
2651 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
2652 I40E_INSET_IPV4_TTL | I40E_INSET_IPV4_PROTO)) {
2653 rte_flow_error_set(error, EINVAL,
2654 RTE_FLOW_ERROR_TYPE_ITEM,
2656 "L2 and L3 input set are exclusive.");
2660 /* Get the filter info */
2661 filter->input.flow.ip4_flow.proto =
2662 ipv4_spec->hdr.next_proto_id;
2663 filter->input.flow.ip4_flow.tos =
2664 ipv4_spec->hdr.type_of_service;
2665 filter->input.flow.ip4_flow.ttl =
2666 ipv4_spec->hdr.time_to_live;
2667 filter->input.flow.ip4_flow.src_ip =
2668 ipv4_spec->hdr.src_addr;
2669 filter->input.flow.ip4_flow.dst_ip =
2670 ipv4_spec->hdr.dst_addr;
2672 filter->input.flow_ext.inner_ip = false;
2673 filter->input.flow_ext.oip_type =
2674 I40E_FDIR_IPTYPE_IPV4;
2676 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2677 filter->input.flow_ext.inner_ip = true;
2678 filter->input.flow_ext.iip_type =
2679 I40E_FDIR_IPTYPE_IPV4;
2680 } else if (!ipv4_spec && !ipv4_mask && outer_ip) {
2681 filter->input.flow_ext.inner_ip = false;
2682 filter->input.flow_ext.oip_type =
2683 I40E_FDIR_IPTYPE_IPV4;
2684 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2685 rte_flow_error_set(error, EINVAL,
2686 RTE_FLOW_ERROR_TYPE_ITEM,
2688 "Invalid inner IPv4 mask.");
2696 case RTE_FLOW_ITEM_TYPE_IPV6:
2697 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2698 ipv6_spec = item->spec;
2699 ipv6_mask = item->mask;
2700 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2701 layer_idx = I40E_FLXPLD_L3_IDX;
2703 if (ipv6_spec && ipv6_mask && outer_ip) {
2704 /* Check IPv6 mask and update input set */
2705 if (ipv6_mask->hdr.payload_len) {
2706 rte_flow_error_set(error, EINVAL,
2707 RTE_FLOW_ERROR_TYPE_ITEM,
2709 "Invalid IPv6 mask");
2713 if (!memcmp(ipv6_mask->hdr.src_addr,
2715 RTE_DIM(ipv6_mask->hdr.src_addr)))
2716 input_set |= I40E_INSET_IPV6_SRC;
2717 if (!memcmp(ipv6_mask->hdr.dst_addr,
2719 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2720 input_set |= I40E_INSET_IPV6_DST;
2722 if ((ipv6_mask->hdr.vtc_flow &
2723 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2724 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2725 input_set |= I40E_INSET_IPV6_TC;
2726 if (ipv6_mask->hdr.proto == UINT8_MAX)
2727 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2728 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2729 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2731 /* Get filter info */
2733 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2734 filter->input.flow.ipv6_flow.tc =
2735 (uint8_t)(vtc_flow_cpu >>
2736 I40E_FDIR_IPv6_TC_OFFSET);
2737 filter->input.flow.ipv6_flow.proto =
2738 ipv6_spec->hdr.proto;
2739 filter->input.flow.ipv6_flow.hop_limits =
2740 ipv6_spec->hdr.hop_limits;
2742 filter->input.flow_ext.inner_ip = false;
2743 filter->input.flow_ext.oip_type =
2744 I40E_FDIR_IPTYPE_IPV6;
2746 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2747 ipv6_spec->hdr.src_addr, 16);
2748 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2749 ipv6_spec->hdr.dst_addr, 16);
2751 /* Check if it is fragment. */
2752 if (ipv6_spec->hdr.proto ==
2753 I40E_IPV6_FRAG_HEADER)
2754 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2755 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2756 filter->input.flow_ext.inner_ip = true;
2757 filter->input.flow_ext.iip_type =
2758 I40E_FDIR_IPTYPE_IPV6;
2759 } else if (!ipv6_spec && !ipv6_mask && outer_ip) {
2760 filter->input.flow_ext.inner_ip = false;
2761 filter->input.flow_ext.oip_type =
2762 I40E_FDIR_IPTYPE_IPV6;
2763 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2764 rte_flow_error_set(error, EINVAL,
2765 RTE_FLOW_ERROR_TYPE_ITEM,
2767 "Invalid inner IPv6 mask");
2774 case RTE_FLOW_ITEM_TYPE_TCP:
2775 tcp_spec = item->spec;
2776 tcp_mask = item->mask;
2778 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2780 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2781 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2783 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2784 if (tcp_spec && tcp_mask) {
2785 /* Check TCP mask and update input set */
2786 if (tcp_mask->hdr.sent_seq ||
2787 tcp_mask->hdr.recv_ack ||
2788 tcp_mask->hdr.data_off ||
2789 tcp_mask->hdr.tcp_flags ||
2790 tcp_mask->hdr.rx_win ||
2791 tcp_mask->hdr.cksum ||
2792 tcp_mask->hdr.tcp_urp) {
2793 rte_flow_error_set(error, EINVAL,
2794 RTE_FLOW_ERROR_TYPE_ITEM,
2796 "Invalid TCP mask");
2800 if (tcp_mask->hdr.src_port == UINT16_MAX)
2801 input_set |= I40E_INSET_SRC_PORT;
2802 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2803 input_set |= I40E_INSET_DST_PORT;
2805 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2807 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2808 rte_flow_error_set(error, EINVAL,
2809 RTE_FLOW_ERROR_TYPE_ITEM,
2811 "L2 and L4 input set are exclusive.");
2815 /* Get filter info */
2816 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2817 filter->input.flow.tcp4_flow.src_port =
2818 tcp_spec->hdr.src_port;
2819 filter->input.flow.tcp4_flow.dst_port =
2820 tcp_spec->hdr.dst_port;
2821 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2822 filter->input.flow.tcp6_flow.src_port =
2823 tcp_spec->hdr.src_port;
2824 filter->input.flow.tcp6_flow.dst_port =
2825 tcp_spec->hdr.dst_port;
2830 layer_idx = I40E_FLXPLD_L4_IDX;
2833 case RTE_FLOW_ITEM_TYPE_UDP:
2834 udp_spec = item->spec;
2835 udp_mask = item->mask;
2837 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2839 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2840 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2842 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2844 if (udp_spec && udp_mask) {
2845 /* Check UDP mask and update input set*/
2846 if (udp_mask->hdr.dgram_len ||
2847 udp_mask->hdr.dgram_cksum) {
2848 rte_flow_error_set(error, EINVAL,
2849 RTE_FLOW_ERROR_TYPE_ITEM,
2851 "Invalid UDP mask");
2855 if (udp_mask->hdr.src_port == UINT16_MAX)
2856 input_set |= I40E_INSET_SRC_PORT;
2857 if (udp_mask->hdr.dst_port == UINT16_MAX)
2858 input_set |= I40E_INSET_DST_PORT;
2860 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2862 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2863 rte_flow_error_set(error, EINVAL,
2864 RTE_FLOW_ERROR_TYPE_ITEM,
2866 "L2 and L4 input set are exclusive.");
2870 /* Get filter info */
2871 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2872 filter->input.flow.udp4_flow.src_port =
2873 udp_spec->hdr.src_port;
2874 filter->input.flow.udp4_flow.dst_port =
2875 udp_spec->hdr.dst_port;
2876 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2877 filter->input.flow.udp6_flow.src_port =
2878 udp_spec->hdr.src_port;
2879 filter->input.flow.udp6_flow.dst_port =
2880 udp_spec->hdr.dst_port;
2884 filter->input.flow_ext.is_udp = true;
2885 layer_idx = I40E_FLXPLD_L4_IDX;
2888 case RTE_FLOW_ITEM_TYPE_GTPC:
2889 case RTE_FLOW_ITEM_TYPE_GTPU:
2890 if (!pf->gtp_support) {
2891 rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ITEM,
2894 "Unsupported protocol");
2898 gtp_spec = item->spec;
2899 gtp_mask = item->mask;
2901 if (gtp_spec && gtp_mask) {
2902 if (gtp_mask->v_pt_rsv_flags ||
2903 gtp_mask->msg_type ||
2904 gtp_mask->msg_len ||
2905 gtp_mask->teid != UINT32_MAX) {
2906 rte_flow_error_set(error, EINVAL,
2907 RTE_FLOW_ERROR_TYPE_ITEM,
2909 "Invalid GTP mask");
2913 filter->input.flow.gtp_flow.teid =
2915 filter->input.flow_ext.customized_pctype = true;
2916 cus_proto = item_type;
2919 case RTE_FLOW_ITEM_TYPE_ESP:
2920 if (!pf->esp_support) {
2921 rte_flow_error_set(error, EINVAL,
2922 RTE_FLOW_ERROR_TYPE_ITEM,
2924 "Unsupported ESP protocol");
2928 esp_spec = item->spec;
2929 esp_mask = item->mask;
2931 if (!esp_spec || !esp_mask) {
2932 rte_flow_error_set(error, EINVAL,
2933 RTE_FLOW_ERROR_TYPE_ITEM,
2935 "Invalid ESP item");
2939 if (esp_spec && esp_mask) {
2940 if (esp_mask->hdr.spi != UINT32_MAX) {
2941 rte_flow_error_set(error, EINVAL,
2942 RTE_FLOW_ERROR_TYPE_ITEM,
2944 "Invalid ESP mask");
2947 i40e_flow_set_filter_spi(filter, esp_spec);
2948 filter->input.flow_ext.customized_pctype = true;
2949 cus_proto = item_type;
2952 case RTE_FLOW_ITEM_TYPE_SCTP:
2953 sctp_spec = item->spec;
2954 sctp_mask = item->mask;
2956 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2958 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2959 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2961 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2963 if (sctp_spec && sctp_mask) {
2964 /* Check SCTP mask and update input set */
2965 if (sctp_mask->hdr.cksum) {
2966 rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ITEM,
2969 "Invalid UDP mask");
2973 if (sctp_mask->hdr.src_port == UINT16_MAX)
2974 input_set |= I40E_INSET_SRC_PORT;
2975 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2976 input_set |= I40E_INSET_DST_PORT;
2977 if (sctp_mask->hdr.tag == UINT32_MAX)
2978 input_set |= I40E_INSET_SCTP_VT;
2980 /* Get filter info */
2981 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2982 filter->input.flow.sctp4_flow.src_port =
2983 sctp_spec->hdr.src_port;
2984 filter->input.flow.sctp4_flow.dst_port =
2985 sctp_spec->hdr.dst_port;
2986 filter->input.flow.sctp4_flow.verify_tag
2987 = sctp_spec->hdr.tag;
2988 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2989 filter->input.flow.sctp6_flow.src_port =
2990 sctp_spec->hdr.src_port;
2991 filter->input.flow.sctp6_flow.dst_port =
2992 sctp_spec->hdr.dst_port;
2993 filter->input.flow.sctp6_flow.verify_tag
2994 = sctp_spec->hdr.tag;
2998 layer_idx = I40E_FLXPLD_L4_IDX;
3001 case RTE_FLOW_ITEM_TYPE_RAW:
3002 raw_spec = item->spec;
3003 raw_mask = item->mask;
3005 if (!raw_spec || !raw_mask) {
3006 rte_flow_error_set(error, EINVAL,
3007 RTE_FLOW_ERROR_TYPE_ITEM,
3009 "NULL RAW spec/mask");
3013 if (pf->support_multi_driver) {
3014 rte_flow_error_set(error, ENOTSUP,
3015 RTE_FLOW_ERROR_TYPE_ITEM,
3017 "Unsupported flexible payload.");
3021 ret = i40e_flow_check_raw_item(item, raw_spec, error);
3025 off_arr[raw_id] = raw_spec->offset;
3026 len_arr[raw_id] = raw_spec->length;
3029 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
3030 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
3032 raw_spec->length / sizeof(uint16_t);
3033 flex_pit.dst_offset =
3034 next_dst_off / sizeof(uint16_t);
3036 for (i = 0; i <= raw_id; i++) {
3038 flex_pit.src_offset +=
3042 flex_pit.src_offset +=
3043 (off_arr[i] + len_arr[i]) /
3045 flex_size += len_arr[i];
3047 if (((flex_pit.src_offset + flex_pit.size) >=
3048 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
3049 flex_size > I40E_FDIR_MAX_FLEXLEN) {
3050 rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ITEM,
3053 "Exceeds maxmial payload limit.");
3057 for (i = 0; i < raw_spec->length; i++) {
3058 j = i + next_dst_off;
3059 filter->input.flow_ext.flexbytes[j] =
3060 raw_spec->pattern[i];
3061 filter->input.flow_ext.flex_mask[j] =
3062 raw_mask->pattern[i];
3065 next_dst_off += raw_spec->length;
3068 memcpy(&filter->input.flow_ext.flex_pit[field_idx],
3069 &flex_pit, sizeof(struct i40e_fdir_flex_pit));
3070 filter->input.flow_ext.layer_idx = layer_idx;
3071 filter->input.flow_ext.raw_id = raw_id;
3073 case RTE_FLOW_ITEM_TYPE_VF:
3074 vf_spec = item->spec;
3075 if (!attr->transfer) {
3076 rte_flow_error_set(error, ENOTSUP,
3077 RTE_FLOW_ERROR_TYPE_ITEM,
3079 "Matching VF traffic"
3080 " without affecting it"
3081 " (transfer attribute)"
3085 filter->input.flow_ext.is_vf = 1;
3086 filter->input.flow_ext.dst_id = vf_spec->id;
3087 if (filter->input.flow_ext.is_vf &&
3088 filter->input.flow_ext.dst_id >= pf->vf_num) {
3089 rte_flow_error_set(error, EINVAL,
3090 RTE_FLOW_ERROR_TYPE_ITEM,
3092 "Invalid VF ID for FDIR.");
3096 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
3097 l2tpv3oip_spec = item->spec;
3098 l2tpv3oip_mask = item->mask;
3100 if (!l2tpv3oip_spec || !l2tpv3oip_mask)
3103 if (l2tpv3oip_mask->session_id != UINT32_MAX) {
3104 rte_flow_error_set(error, EINVAL,
3105 RTE_FLOW_ERROR_TYPE_ITEM,
3107 "Invalid L2TPv3 mask");
3111 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3112 filter->input.flow.ip4_l2tpv3oip_flow.session_id =
3113 l2tpv3oip_spec->session_id;
3114 filter->input.flow_ext.oip_type =
3115 I40E_FDIR_IPTYPE_IPV4;
3116 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3117 filter->input.flow.ip6_l2tpv3oip_flow.session_id =
3118 l2tpv3oip_spec->session_id;
3119 filter->input.flow_ext.oip_type =
3120 I40E_FDIR_IPTYPE_IPV6;
3123 filter->input.flow_ext.customized_pctype = true;
3124 cus_proto = item_type;
3131 /* Get customized pctype value */
3132 if (filter->input.flow_ext.customized_pctype) {
3133 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
3134 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3135 rte_flow_error_set(error, EINVAL,
3136 RTE_FLOW_ERROR_TYPE_ITEM,
3138 "Unsupported pctype");
3143 /* If customized pctype is not used, set fdir configuration.*/
3144 if (!filter->input.flow_ext.customized_pctype) {
3145 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3147 rte_flow_error_set(error, EINVAL,
3148 RTE_FLOW_ERROR_TYPE_ITEM, item,
3149 "Conflict with the first rule's input set.");
3151 } else if (ret == -EINVAL) {
3152 rte_flow_error_set(error, EINVAL,
3153 RTE_FLOW_ERROR_TYPE_ITEM, item,
3154 "Invalid pattern mask.");
3159 filter->input.pctype = pctype;
3164 /* Parse to get the action info of a FDIR filter.
3165 * FDIR action supports QUEUE or (QUEUE + MARK).
3168 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3169 const struct rte_flow_action *actions,
3170 struct rte_flow_error *error,
3171 struct i40e_fdir_filter_conf *filter)
3173 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3174 const struct rte_flow_action *act;
3175 const struct rte_flow_action_queue *act_q;
3176 const struct rte_flow_action_mark *mark_spec = NULL;
3179 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3180 NEXT_ITEM_OF_ACTION(act, actions, index);
3181 switch (act->type) {
3182 case RTE_FLOW_ACTION_TYPE_QUEUE:
3184 filter->action.rx_queue = act_q->index;
3185 if ((!filter->input.flow_ext.is_vf &&
3186 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3187 (filter->input.flow_ext.is_vf &&
3188 filter->action.rx_queue >= pf->vf_nb_qps)) {
3189 rte_flow_error_set(error, EINVAL,
3190 RTE_FLOW_ERROR_TYPE_ACTION, act,
3191 "Invalid queue ID for FDIR.");
3194 filter->action.behavior = I40E_FDIR_ACCEPT;
3196 case RTE_FLOW_ACTION_TYPE_DROP:
3197 filter->action.behavior = I40E_FDIR_REJECT;
3199 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3200 filter->action.behavior = I40E_FDIR_PASSTHRU;
3202 case RTE_FLOW_ACTION_TYPE_MARK:
3203 filter->action.behavior = I40E_FDIR_PASSTHRU;
3204 mark_spec = act->conf;
3205 filter->action.report_status = I40E_FDIR_REPORT_ID;
3206 filter->soft_id = mark_spec->id;
3209 rte_flow_error_set(error, EINVAL,
3210 RTE_FLOW_ERROR_TYPE_ACTION, act,
3215 /* Check if the next non-void item is MARK or FLAG or END. */
3217 NEXT_ITEM_OF_ACTION(act, actions, index);
3218 switch (act->type) {
3219 case RTE_FLOW_ACTION_TYPE_MARK:
3221 /* Double MARK actions requested */
3222 rte_flow_error_set(error, EINVAL,
3223 RTE_FLOW_ERROR_TYPE_ACTION, act,
3227 mark_spec = act->conf;
3228 filter->action.report_status = I40E_FDIR_REPORT_ID;
3229 filter->soft_id = mark_spec->id;
3231 case RTE_FLOW_ACTION_TYPE_FLAG:
3233 /* MARK + FLAG not supported */
3234 rte_flow_error_set(error, EINVAL,
3235 RTE_FLOW_ERROR_TYPE_ACTION, act,
3239 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3241 case RTE_FLOW_ACTION_TYPE_RSS:
3242 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3243 /* RSS filter won't be next if FDIR did not pass thru */
3244 rte_flow_error_set(error, EINVAL,
3245 RTE_FLOW_ERROR_TYPE_ACTION, act,
3250 case RTE_FLOW_ACTION_TYPE_END:
3253 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3254 act, "Invalid action.");
3258 /* Check if the next non-void item is END */
3260 NEXT_ITEM_OF_ACTION(act, actions, index);
3261 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3262 rte_flow_error_set(error, EINVAL,
3263 RTE_FLOW_ERROR_TYPE_ACTION,
3264 act, "Invalid action.");
3272 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3273 const struct rte_flow_attr *attr,
3274 const struct rte_flow_item pattern[],
3275 const struct rte_flow_action actions[],
3276 struct rte_flow_error *error,
3277 union i40e_filter_t *filter)
3279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280 struct i40e_fdir_filter_conf *fdir_filter =
3281 &filter->fdir_filter;
3284 ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3289 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3293 ret = i40e_flow_parse_attr(attr, error);
3297 cons_filter_type = RTE_ETH_FILTER_FDIR;
3299 if (pf->fdir.fdir_vsi == NULL) {
3300 /* Enable fdir when fdir flow is added at first time. */
3301 ret = i40e_fdir_setup(pf);
3302 if (ret != I40E_SUCCESS) {
3303 rte_flow_error_set(error, ENOTSUP,
3304 RTE_FLOW_ERROR_TYPE_HANDLE,
3305 NULL, "Failed to setup fdir.");
3308 ret = i40e_fdir_configure(dev);
3310 rte_flow_error_set(error, ENOTSUP,
3311 RTE_FLOW_ERROR_TYPE_HANDLE,
3312 NULL, "Failed to configure fdir.");
3317 /* If create the first fdir rule, enable fdir check for rx queues */
3318 if (TAILQ_EMPTY(&pf->fdir.fdir_list))
3319 i40e_fdir_rx_proc_enable(dev, 1);
3323 i40e_fdir_teardown(pf);
3327 /* Parse to get the action info of a tunnel filter
3328 * Tunnel action only supports PF, VF and QUEUE.
3331 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3332 const struct rte_flow_action *actions,
3333 struct rte_flow_error *error,
3334 struct i40e_tunnel_filter_conf *filter)
3336 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3337 const struct rte_flow_action *act;
3338 const struct rte_flow_action_queue *act_q;
3339 const struct rte_flow_action_vf *act_vf;
3342 /* Check if the first non-void action is PF or VF. */
3343 NEXT_ITEM_OF_ACTION(act, actions, index);
3344 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3345 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3346 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3347 act, "Not supported action.");
3351 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3353 filter->vf_id = act_vf->id;
3354 filter->is_to_vf = 1;
3355 if (filter->vf_id >= pf->vf_num) {
3356 rte_flow_error_set(error, EINVAL,
3357 RTE_FLOW_ERROR_TYPE_ACTION,
3358 act, "Invalid VF ID for tunnel filter");
3363 /* Check if the next non-void item is QUEUE */
3365 NEXT_ITEM_OF_ACTION(act, actions, index);
3366 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3368 filter->queue_id = act_q->index;
3369 if ((!filter->is_to_vf) &&
3370 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3371 rte_flow_error_set(error, EINVAL,
3372 RTE_FLOW_ERROR_TYPE_ACTION,
3373 act, "Invalid queue ID for tunnel filter");
3375 } else if (filter->is_to_vf &&
3376 (filter->queue_id >= pf->vf_nb_qps)) {
3377 rte_flow_error_set(error, EINVAL,
3378 RTE_FLOW_ERROR_TYPE_ACTION,
3379 act, "Invalid queue ID for tunnel filter");
3384 /* Check if the next non-void item is END */
3386 NEXT_ITEM_OF_ACTION(act, actions, index);
3387 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3388 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3389 act, "Not supported action.");
3396 /* 1. Last in item should be NULL as range is not supported.
3397 * 2. Supported filter types: Source port only and Destination port only.
3398 * 3. Mask of fields which need to be matched should be
3400 * 4. Mask of fields which needn't to be matched should be
3404 i40e_flow_parse_l4_pattern(const struct rte_flow_item *pattern,
3405 struct rte_flow_error *error,
3406 struct i40e_tunnel_filter_conf *filter)
3408 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
3409 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
3410 const struct rte_flow_item_udp *udp_spec, *udp_mask;
3411 const struct rte_flow_item *item = pattern;
3412 enum rte_flow_item_type item_type;
3414 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3416 rte_flow_error_set(error, EINVAL,
3417 RTE_FLOW_ERROR_TYPE_ITEM,
3419 "Not support range");
3422 item_type = item->type;
3423 switch (item_type) {
3424 case RTE_FLOW_ITEM_TYPE_ETH:
3425 if (item->spec || item->mask) {
3426 rte_flow_error_set(error, EINVAL,
3427 RTE_FLOW_ERROR_TYPE_ITEM,
3429 "Invalid ETH item");
3434 case RTE_FLOW_ITEM_TYPE_IPV4:
3435 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3436 /* IPv4 is used to describe protocol,
3437 * spec and mask should be NULL.
3439 if (item->spec || item->mask) {
3440 rte_flow_error_set(error, EINVAL,
3441 RTE_FLOW_ERROR_TYPE_ITEM,
3443 "Invalid IPv4 item");
3448 case RTE_FLOW_ITEM_TYPE_IPV6:
3449 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3450 /* IPv6 is used to describe protocol,
3451 * spec and mask should be NULL.
3453 if (item->spec || item->mask) {
3454 rte_flow_error_set(error, EINVAL,
3455 RTE_FLOW_ERROR_TYPE_ITEM,
3457 "Invalid IPv6 item");
3462 case RTE_FLOW_ITEM_TYPE_UDP:
3463 udp_spec = item->spec;
3464 udp_mask = item->mask;
3466 if (!udp_spec || !udp_mask) {
3467 rte_flow_error_set(error, EINVAL,
3468 RTE_FLOW_ERROR_TYPE_ITEM,
3470 "Invalid udp item");
3474 if (udp_spec->hdr.src_port != 0 &&
3475 udp_spec->hdr.dst_port != 0) {
3476 rte_flow_error_set(error, EINVAL,
3477 RTE_FLOW_ERROR_TYPE_ITEM,
3479 "Invalid udp spec");
3483 if (udp_spec->hdr.src_port != 0) {
3484 filter->l4_port_type =
3485 I40E_L4_PORT_TYPE_SRC;
3487 rte_be_to_cpu_32(udp_spec->hdr.src_port);
3490 if (udp_spec->hdr.dst_port != 0) {
3491 filter->l4_port_type =
3492 I40E_L4_PORT_TYPE_DST;
3494 rte_be_to_cpu_32(udp_spec->hdr.dst_port);
3497 filter->tunnel_type = I40E_CLOUD_TYPE_UDP;
3500 case RTE_FLOW_ITEM_TYPE_TCP:
3501 tcp_spec = item->spec;
3502 tcp_mask = item->mask;
3504 if (!tcp_spec || !tcp_mask) {
3505 rte_flow_error_set(error, EINVAL,
3506 RTE_FLOW_ERROR_TYPE_ITEM,
3508 "Invalid tcp item");
3512 if (tcp_spec->hdr.src_port != 0 &&
3513 tcp_spec->hdr.dst_port != 0) {
3514 rte_flow_error_set(error, EINVAL,
3515 RTE_FLOW_ERROR_TYPE_ITEM,
3517 "Invalid tcp spec");
3521 if (tcp_spec->hdr.src_port != 0) {
3522 filter->l4_port_type =
3523 I40E_L4_PORT_TYPE_SRC;
3525 rte_be_to_cpu_32(tcp_spec->hdr.src_port);
3528 if (tcp_spec->hdr.dst_port != 0) {
3529 filter->l4_port_type =
3530 I40E_L4_PORT_TYPE_DST;
3532 rte_be_to_cpu_32(tcp_spec->hdr.dst_port);
3535 filter->tunnel_type = I40E_CLOUD_TYPE_TCP;
3538 case RTE_FLOW_ITEM_TYPE_SCTP:
3539 sctp_spec = item->spec;
3540 sctp_mask = item->mask;
3542 if (!sctp_spec || !sctp_mask) {
3543 rte_flow_error_set(error, EINVAL,
3544 RTE_FLOW_ERROR_TYPE_ITEM,
3546 "Invalid sctp item");
3550 if (sctp_spec->hdr.src_port != 0 &&
3551 sctp_spec->hdr.dst_port != 0) {
3552 rte_flow_error_set(error, EINVAL,
3553 RTE_FLOW_ERROR_TYPE_ITEM,
3555 "Invalid sctp spec");
3559 if (sctp_spec->hdr.src_port != 0) {
3560 filter->l4_port_type =
3561 I40E_L4_PORT_TYPE_SRC;
3563 rte_be_to_cpu_32(sctp_spec->hdr.src_port);
3566 if (sctp_spec->hdr.dst_port != 0) {
3567 filter->l4_port_type =
3568 I40E_L4_PORT_TYPE_DST;
3570 rte_be_to_cpu_32(sctp_spec->hdr.dst_port);
3573 filter->tunnel_type = I40E_CLOUD_TYPE_SCTP;
3585 i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
3586 const struct rte_flow_attr *attr,
3587 const struct rte_flow_item pattern[],
3588 const struct rte_flow_action actions[],
3589 struct rte_flow_error *error,
3590 union i40e_filter_t *filter)
3592 struct i40e_tunnel_filter_conf *tunnel_filter =
3593 &filter->consistent_tunnel_filter;
3596 ret = i40e_flow_parse_l4_pattern(pattern, error, tunnel_filter);
3600 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3604 ret = i40e_flow_parse_attr(attr, error);
3608 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3613 static uint16_t i40e_supported_tunnel_filter_types[] = {
3614 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3615 ETH_TUNNEL_FILTER_IVLAN,
3616 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3617 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3618 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3619 ETH_TUNNEL_FILTER_IMAC,
3620 ETH_TUNNEL_FILTER_IMAC,
3624 i40e_check_tunnel_filter_type(uint8_t filter_type)
3628 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3629 if (filter_type == i40e_supported_tunnel_filter_types[i])
3636 /* 1. Last in item should be NULL as range is not supported.
3637 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3638 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3639 * 3. Mask of fields which need to be matched should be
3641 * 4. Mask of fields which needn't to be matched should be
3645 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3646 const struct rte_flow_item *pattern,
3647 struct rte_flow_error *error,
3648 struct i40e_tunnel_filter_conf *filter)
3650 const struct rte_flow_item *item = pattern;
3651 const struct rte_flow_item_eth *eth_spec;
3652 const struct rte_flow_item_eth *eth_mask;
3653 const struct rte_flow_item_vxlan *vxlan_spec;
3654 const struct rte_flow_item_vxlan *vxlan_mask;
3655 const struct rte_flow_item_vlan *vlan_spec;
3656 const struct rte_flow_item_vlan *vlan_mask;
3657 uint8_t filter_type = 0;
3658 bool is_vni_masked = 0;
3659 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3660 enum rte_flow_item_type item_type;
3661 bool vxlan_flag = 0;
3662 uint32_t tenant_id_be = 0;
3665 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3667 rte_flow_error_set(error, EINVAL,
3668 RTE_FLOW_ERROR_TYPE_ITEM,
3670 "Not support range");
3673 item_type = item->type;
3674 switch (item_type) {
3675 case RTE_FLOW_ITEM_TYPE_ETH:
3676 eth_spec = item->spec;
3677 eth_mask = item->mask;
3679 /* Check if ETH item is used for place holder.
3680 * If yes, both spec and mask should be NULL.
3681 * If no, both spec and mask shouldn't be NULL.
3683 if ((!eth_spec && eth_mask) ||
3684 (eth_spec && !eth_mask)) {
3685 rte_flow_error_set(error, EINVAL,
3686 RTE_FLOW_ERROR_TYPE_ITEM,
3688 "Invalid ether spec/mask");
3692 if (eth_spec && eth_mask) {
3693 /* DST address of inner MAC shouldn't be masked.
3694 * SRC address of Inner MAC should be masked.
3696 if (!rte_is_broadcast_ether_addr(ð_mask->dst) ||
3697 !rte_is_zero_ether_addr(ð_mask->src) ||
3699 rte_flow_error_set(error, EINVAL,
3700 RTE_FLOW_ERROR_TYPE_ITEM,
3702 "Invalid ether spec/mask");
3707 rte_memcpy(&filter->outer_mac,
3709 RTE_ETHER_ADDR_LEN);
3710 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3712 rte_memcpy(&filter->inner_mac,
3714 RTE_ETHER_ADDR_LEN);
3715 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3719 case RTE_FLOW_ITEM_TYPE_VLAN:
3720 vlan_spec = item->spec;
3721 vlan_mask = item->mask;
3722 if (!(vlan_spec && vlan_mask) ||
3723 vlan_mask->inner_type) {
3724 rte_flow_error_set(error, EINVAL,
3725 RTE_FLOW_ERROR_TYPE_ITEM,
3727 "Invalid vlan item");
3731 if (vlan_spec && vlan_mask) {
3732 if (vlan_mask->tci ==
3733 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK))
3734 filter->inner_vlan =
3735 rte_be_to_cpu_16(vlan_spec->tci) &
3737 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3740 case RTE_FLOW_ITEM_TYPE_IPV4:
3741 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3742 /* IPv4 is used to describe protocol,
3743 * spec and mask should be NULL.
3745 if (item->spec || item->mask) {
3746 rte_flow_error_set(error, EINVAL,
3747 RTE_FLOW_ERROR_TYPE_ITEM,
3749 "Invalid IPv4 item");
3753 case RTE_FLOW_ITEM_TYPE_IPV6:
3754 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3755 /* IPv6 is used to describe protocol,
3756 * spec and mask should be NULL.
3758 if (item->spec || item->mask) {
3759 rte_flow_error_set(error, EINVAL,
3760 RTE_FLOW_ERROR_TYPE_ITEM,
3762 "Invalid IPv6 item");
3766 case RTE_FLOW_ITEM_TYPE_UDP:
3767 /* UDP is used to describe protocol,
3768 * spec and mask should be NULL.
3770 if (item->spec || item->mask) {
3771 rte_flow_error_set(error, EINVAL,
3772 RTE_FLOW_ERROR_TYPE_ITEM,
3774 "Invalid UDP item");
3778 case RTE_FLOW_ITEM_TYPE_VXLAN:
3779 vxlan_spec = item->spec;
3780 vxlan_mask = item->mask;
3781 /* Check if VXLAN item is used to describe protocol.
3782 * If yes, both spec and mask should be NULL.
3783 * If no, both spec and mask shouldn't be NULL.
3785 if ((!vxlan_spec && vxlan_mask) ||
3786 (vxlan_spec && !vxlan_mask)) {
3787 rte_flow_error_set(error, EINVAL,
3788 RTE_FLOW_ERROR_TYPE_ITEM,
3790 "Invalid VXLAN item");
3794 /* Check if VNI is masked. */
3795 if (vxlan_spec && vxlan_mask) {
3797 !!memcmp(vxlan_mask->vni, vni_mask,
3799 if (is_vni_masked) {
3800 rte_flow_error_set(error, EINVAL,
3801 RTE_FLOW_ERROR_TYPE_ITEM,
3803 "Invalid VNI mask");
3807 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3808 vxlan_spec->vni, 3);
3810 rte_be_to_cpu_32(tenant_id_be);
3811 filter_type |= ETH_TUNNEL_FILTER_TENID;
3821 ret = i40e_check_tunnel_filter_type(filter_type);
3823 rte_flow_error_set(error, EINVAL,
3824 RTE_FLOW_ERROR_TYPE_ITEM,
3826 "Invalid filter type");
3829 filter->filter_type = filter_type;
3831 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3837 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3838 const struct rte_flow_attr *attr,
3839 const struct rte_flow_item pattern[],
3840 const struct rte_flow_action actions[],
3841 struct rte_flow_error *error,
3842 union i40e_filter_t *filter)
3844 struct i40e_tunnel_filter_conf *tunnel_filter =
3845 &filter->consistent_tunnel_filter;
3848 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3849 error, tunnel_filter);
3853 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3857 ret = i40e_flow_parse_attr(attr, error);
3861 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3866 /* 1. Last in item should be NULL as range is not supported.
3867 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3868 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3869 * 3. Mask of fields which need to be matched should be
3871 * 4. Mask of fields which needn't to be matched should be
3875 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3876 const struct rte_flow_item *pattern,
3877 struct rte_flow_error *error,
3878 struct i40e_tunnel_filter_conf *filter)
3880 const struct rte_flow_item *item = pattern;
3881 const struct rte_flow_item_eth *eth_spec;
3882 const struct rte_flow_item_eth *eth_mask;
3883 const struct rte_flow_item_nvgre *nvgre_spec;
3884 const struct rte_flow_item_nvgre *nvgre_mask;
3885 const struct rte_flow_item_vlan *vlan_spec;
3886 const struct rte_flow_item_vlan *vlan_mask;
3887 enum rte_flow_item_type item_type;
3888 uint8_t filter_type = 0;
3889 bool is_tni_masked = 0;
3890 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3891 bool nvgre_flag = 0;
3892 uint32_t tenant_id_be = 0;
3895 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3897 rte_flow_error_set(error, EINVAL,
3898 RTE_FLOW_ERROR_TYPE_ITEM,
3900 "Not support range");
3903 item_type = item->type;
3904 switch (item_type) {
3905 case RTE_FLOW_ITEM_TYPE_ETH:
3906 eth_spec = item->spec;
3907 eth_mask = item->mask;
3909 /* Check if ETH item is used for place holder.
3910 * If yes, both spec and mask should be NULL.
3911 * If no, both spec and mask shouldn't be NULL.
3913 if ((!eth_spec && eth_mask) ||
3914 (eth_spec && !eth_mask)) {
3915 rte_flow_error_set(error, EINVAL,
3916 RTE_FLOW_ERROR_TYPE_ITEM,
3918 "Invalid ether spec/mask");
3922 if (eth_spec && eth_mask) {
3923 /* DST address of inner MAC shouldn't be masked.
3924 * SRC address of Inner MAC should be masked.
3926 if (!rte_is_broadcast_ether_addr(ð_mask->dst) ||
3927 !rte_is_zero_ether_addr(ð_mask->src) ||
3929 rte_flow_error_set(error, EINVAL,
3930 RTE_FLOW_ERROR_TYPE_ITEM,
3932 "Invalid ether spec/mask");
3937 rte_memcpy(&filter->outer_mac,
3939 RTE_ETHER_ADDR_LEN);
3940 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3942 rte_memcpy(&filter->inner_mac,
3944 RTE_ETHER_ADDR_LEN);
3945 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3950 case RTE_FLOW_ITEM_TYPE_VLAN:
3951 vlan_spec = item->spec;
3952 vlan_mask = item->mask;
3953 if (!(vlan_spec && vlan_mask) ||
3954 vlan_mask->inner_type) {
3955 rte_flow_error_set(error, EINVAL,
3956 RTE_FLOW_ERROR_TYPE_ITEM,
3958 "Invalid vlan item");
3962 if (vlan_spec && vlan_mask) {
3963 if (vlan_mask->tci ==
3964 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK))
3965 filter->inner_vlan =
3966 rte_be_to_cpu_16(vlan_spec->tci) &
3968 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3971 case RTE_FLOW_ITEM_TYPE_IPV4:
3972 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3973 /* IPv4 is used to describe protocol,
3974 * spec and mask should be NULL.
3976 if (item->spec || item->mask) {
3977 rte_flow_error_set(error, EINVAL,
3978 RTE_FLOW_ERROR_TYPE_ITEM,
3980 "Invalid IPv4 item");
3984 case RTE_FLOW_ITEM_TYPE_IPV6:
3985 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3986 /* IPv6 is used to describe protocol,
3987 * spec and mask should be NULL.
3989 if (item->spec || item->mask) {
3990 rte_flow_error_set(error, EINVAL,
3991 RTE_FLOW_ERROR_TYPE_ITEM,
3993 "Invalid IPv6 item");
3997 case RTE_FLOW_ITEM_TYPE_NVGRE:
3998 nvgre_spec = item->spec;
3999 nvgre_mask = item->mask;
4000 /* Check if NVGRE item is used to describe protocol.
4001 * If yes, both spec and mask should be NULL.
4002 * If no, both spec and mask shouldn't be NULL.
4004 if ((!nvgre_spec && nvgre_mask) ||
4005 (nvgre_spec && !nvgre_mask)) {
4006 rte_flow_error_set(error, EINVAL,
4007 RTE_FLOW_ERROR_TYPE_ITEM,
4009 "Invalid NVGRE item");
4013 if (nvgre_spec && nvgre_mask) {
4015 !!memcmp(nvgre_mask->tni, tni_mask,
4017 if (is_tni_masked) {
4018 rte_flow_error_set(error, EINVAL,
4019 RTE_FLOW_ERROR_TYPE_ITEM,
4021 "Invalid TNI mask");
4024 if (nvgre_mask->protocol &&
4025 nvgre_mask->protocol != 0xFFFF) {
4026 rte_flow_error_set(error, EINVAL,
4027 RTE_FLOW_ERROR_TYPE_ITEM,
4029 "Invalid NVGRE item");
4032 if (nvgre_mask->c_k_s_rsvd0_ver &&
4033 nvgre_mask->c_k_s_rsvd0_ver !=
4034 rte_cpu_to_be_16(0xFFFF)) {
4035 rte_flow_error_set(error, EINVAL,
4036 RTE_FLOW_ERROR_TYPE_ITEM,
4038 "Invalid NVGRE item");
4041 if (nvgre_spec->c_k_s_rsvd0_ver !=
4042 rte_cpu_to_be_16(0x2000) &&
4043 nvgre_mask->c_k_s_rsvd0_ver) {
4044 rte_flow_error_set(error, EINVAL,
4045 RTE_FLOW_ERROR_TYPE_ITEM,
4047 "Invalid NVGRE item");
4050 if (nvgre_mask->protocol &&
4051 nvgre_spec->protocol !=
4052 rte_cpu_to_be_16(0x6558)) {
4053 rte_flow_error_set(error, EINVAL,
4054 RTE_FLOW_ERROR_TYPE_ITEM,
4056 "Invalid NVGRE item");
4059 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
4060 nvgre_spec->tni, 3);
4062 rte_be_to_cpu_32(tenant_id_be);
4063 filter_type |= ETH_TUNNEL_FILTER_TENID;
4073 ret = i40e_check_tunnel_filter_type(filter_type);
4075 rte_flow_error_set(error, EINVAL,
4076 RTE_FLOW_ERROR_TYPE_ITEM,
4078 "Invalid filter type");
4081 filter->filter_type = filter_type;
4083 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
4089 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
4090 const struct rte_flow_attr *attr,
4091 const struct rte_flow_item pattern[],
4092 const struct rte_flow_action actions[],
4093 struct rte_flow_error *error,
4094 union i40e_filter_t *filter)
4096 struct i40e_tunnel_filter_conf *tunnel_filter =
4097 &filter->consistent_tunnel_filter;
4100 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
4101 error, tunnel_filter);
4105 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4109 ret = i40e_flow_parse_attr(attr, error);
4113 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4118 /* 1. Last in item should be NULL as range is not supported.
4119 * 2. Supported filter types: MPLS label.
4120 * 3. Mask of fields which need to be matched should be
4122 * 4. Mask of fields which needn't to be matched should be
4126 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
4127 const struct rte_flow_item *pattern,
4128 struct rte_flow_error *error,
4129 struct i40e_tunnel_filter_conf *filter)
4131 const struct rte_flow_item *item = pattern;
4132 const struct rte_flow_item_mpls *mpls_spec;
4133 const struct rte_flow_item_mpls *mpls_mask;
4134 enum rte_flow_item_type item_type;
4135 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
4136 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
4137 uint32_t label_be = 0;
4139 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4141 rte_flow_error_set(error, EINVAL,
4142 RTE_FLOW_ERROR_TYPE_ITEM,
4144 "Not support range");
4147 item_type = item->type;
4148 switch (item_type) {
4149 case RTE_FLOW_ITEM_TYPE_ETH:
4150 if (item->spec || item->mask) {
4151 rte_flow_error_set(error, EINVAL,
4152 RTE_FLOW_ERROR_TYPE_ITEM,
4154 "Invalid ETH item");
4158 case RTE_FLOW_ITEM_TYPE_IPV4:
4159 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4160 /* IPv4 is used to describe protocol,
4161 * spec and mask should be NULL.
4163 if (item->spec || item->mask) {
4164 rte_flow_error_set(error, EINVAL,
4165 RTE_FLOW_ERROR_TYPE_ITEM,
4167 "Invalid IPv4 item");
4171 case RTE_FLOW_ITEM_TYPE_IPV6:
4172 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
4173 /* IPv6 is used to describe protocol,
4174 * spec and mask should be NULL.
4176 if (item->spec || item->mask) {
4177 rte_flow_error_set(error, EINVAL,
4178 RTE_FLOW_ERROR_TYPE_ITEM,
4180 "Invalid IPv6 item");
4184 case RTE_FLOW_ITEM_TYPE_UDP:
4185 /* UDP is used to describe protocol,
4186 * spec and mask should be NULL.
4188 if (item->spec || item->mask) {
4189 rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ITEM,
4192 "Invalid UDP item");
4197 case RTE_FLOW_ITEM_TYPE_GRE:
4198 /* GRE is used to describe protocol,
4199 * spec and mask should be NULL.
4201 if (item->spec || item->mask) {
4202 rte_flow_error_set(error, EINVAL,
4203 RTE_FLOW_ERROR_TYPE_ITEM,
4205 "Invalid GRE item");
4209 case RTE_FLOW_ITEM_TYPE_MPLS:
4210 mpls_spec = item->spec;
4211 mpls_mask = item->mask;
4213 if (!mpls_spec || !mpls_mask) {
4214 rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ITEM,
4217 "Invalid MPLS item");
4221 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
4222 rte_flow_error_set(error, EINVAL,
4223 RTE_FLOW_ERROR_TYPE_ITEM,
4225 "Invalid MPLS label mask");
4228 rte_memcpy(((uint8_t *)&label_be + 1),
4229 mpls_spec->label_tc_s, 3);
4230 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
4238 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
4240 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
4246 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
4247 const struct rte_flow_attr *attr,
4248 const struct rte_flow_item pattern[],
4249 const struct rte_flow_action actions[],
4250 struct rte_flow_error *error,
4251 union i40e_filter_t *filter)
4253 struct i40e_tunnel_filter_conf *tunnel_filter =
4254 &filter->consistent_tunnel_filter;
4257 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
4258 error, tunnel_filter);
4262 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4266 ret = i40e_flow_parse_attr(attr, error);
4270 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4275 /* 1. Last in item should be NULL as range is not supported.
4276 * 2. Supported filter types: GTP TEID.
4277 * 3. Mask of fields which need to be matched should be
4279 * 4. Mask of fields which needn't to be matched should be
4281 * 5. GTP profile supports GTPv1 only.
4282 * 6. GTP-C response message ('source_port' = 2123) is not supported.
4285 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
4286 const struct rte_flow_item *pattern,
4287 struct rte_flow_error *error,
4288 struct i40e_tunnel_filter_conf *filter)
4290 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4291 const struct rte_flow_item *item = pattern;
4292 const struct rte_flow_item_gtp *gtp_spec;
4293 const struct rte_flow_item_gtp *gtp_mask;
4294 enum rte_flow_item_type item_type;
4296 if (!pf->gtp_support) {
4297 rte_flow_error_set(error, EINVAL,
4298 RTE_FLOW_ERROR_TYPE_ITEM,
4300 "GTP is not supported by default.");
4304 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4306 rte_flow_error_set(error, EINVAL,
4307 RTE_FLOW_ERROR_TYPE_ITEM,
4309 "Not support range");
4312 item_type = item->type;
4313 switch (item_type) {
4314 case RTE_FLOW_ITEM_TYPE_ETH:
4315 if (item->spec || item->mask) {
4316 rte_flow_error_set(error, EINVAL,
4317 RTE_FLOW_ERROR_TYPE_ITEM,
4319 "Invalid ETH item");
4323 case RTE_FLOW_ITEM_TYPE_IPV4:
4324 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4325 /* IPv4 is used to describe protocol,
4326 * spec and mask should be NULL.
4328 if (item->spec || item->mask) {
4329 rte_flow_error_set(error, EINVAL,
4330 RTE_FLOW_ERROR_TYPE_ITEM,
4332 "Invalid IPv4 item");
4336 case RTE_FLOW_ITEM_TYPE_UDP:
4337 if (item->spec || item->mask) {
4338 rte_flow_error_set(error, EINVAL,
4339 RTE_FLOW_ERROR_TYPE_ITEM,
4341 "Invalid UDP item");
4345 case RTE_FLOW_ITEM_TYPE_GTPC:
4346 case RTE_FLOW_ITEM_TYPE_GTPU:
4347 gtp_spec = item->spec;
4348 gtp_mask = item->mask;
4350 if (!gtp_spec || !gtp_mask) {
4351 rte_flow_error_set(error, EINVAL,
4352 RTE_FLOW_ERROR_TYPE_ITEM,
4354 "Invalid GTP item");
4358 if (gtp_mask->v_pt_rsv_flags ||
4359 gtp_mask->msg_type ||
4360 gtp_mask->msg_len ||
4361 gtp_mask->teid != UINT32_MAX) {
4362 rte_flow_error_set(error, EINVAL,
4363 RTE_FLOW_ERROR_TYPE_ITEM,
4365 "Invalid GTP mask");
4369 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4370 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4371 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4372 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4374 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4386 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4387 const struct rte_flow_attr *attr,
4388 const struct rte_flow_item pattern[],
4389 const struct rte_flow_action actions[],
4390 struct rte_flow_error *error,
4391 union i40e_filter_t *filter)
4393 struct i40e_tunnel_filter_conf *tunnel_filter =
4394 &filter->consistent_tunnel_filter;
4397 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4398 error, tunnel_filter);
4402 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4406 ret = i40e_flow_parse_attr(attr, error);
4410 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4415 /* 1. Last in item should be NULL as range is not supported.
4416 * 2. Supported filter types: QINQ.
4417 * 3. Mask of fields which need to be matched should be
4419 * 4. Mask of fields which needn't to be matched should be
4423 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4424 const struct rte_flow_item *pattern,
4425 struct rte_flow_error *error,
4426 struct i40e_tunnel_filter_conf *filter)
4428 const struct rte_flow_item *item = pattern;
4429 const struct rte_flow_item_vlan *vlan_spec = NULL;
4430 const struct rte_flow_item_vlan *vlan_mask = NULL;
4431 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4432 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4433 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4434 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4436 enum rte_flow_item_type item_type;
4439 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4441 rte_flow_error_set(error, EINVAL,
4442 RTE_FLOW_ERROR_TYPE_ITEM,
4444 "Not support range");
4447 item_type = item->type;
4448 switch (item_type) {
4449 case RTE_FLOW_ITEM_TYPE_ETH:
4450 if (item->spec || item->mask) {
4451 rte_flow_error_set(error, EINVAL,
4452 RTE_FLOW_ERROR_TYPE_ITEM,
4454 "Invalid ETH item");
4458 case RTE_FLOW_ITEM_TYPE_VLAN:
4459 vlan_spec = item->spec;
4460 vlan_mask = item->mask;
4462 if (!(vlan_spec && vlan_mask) ||
4463 vlan_mask->inner_type) {
4464 rte_flow_error_set(error, EINVAL,
4465 RTE_FLOW_ERROR_TYPE_ITEM,
4467 "Invalid vlan item");
4472 o_vlan_spec = vlan_spec;
4473 o_vlan_mask = vlan_mask;
4476 i_vlan_spec = vlan_spec;
4477 i_vlan_mask = vlan_mask;
4487 /* Get filter specification */
4488 if (o_vlan_mask != NULL && i_vlan_mask != NULL) {
4489 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci);
4490 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci);
4492 rte_flow_error_set(error, EINVAL,
4493 RTE_FLOW_ERROR_TYPE_ITEM,
4495 "Invalid filter type");
4499 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4504 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4505 const struct rte_flow_attr *attr,
4506 const struct rte_flow_item pattern[],
4507 const struct rte_flow_action actions[],
4508 struct rte_flow_error *error,
4509 union i40e_filter_t *filter)
4511 struct i40e_tunnel_filter_conf *tunnel_filter =
4512 &filter->consistent_tunnel_filter;
4515 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4516 error, tunnel_filter);
4520 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4524 ret = i40e_flow_parse_attr(attr, error);
4528 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4534 * This function is used to do configuration i40e existing RSS with rte_flow.
4535 * It also enable queue region configuration using flow API for i40e.
4536 * pattern can be used indicate what parameters will be include in flow,
4537 * like user_priority or flowtype for queue region or HASH function for RSS.
4538 * Action is used to transmit parameter like queue index and HASH
4539 * function for RSS, or flowtype for queue region configuration.
4542 * Case 1: try to transform patterns to pctype. valid pctype will be
4543 * used in parse action.
4544 * Case 2: only ETH, indicate flowtype for queue region will be parsed.
4545 * Case 3: only VLAN, indicate user_priority for queue region will be parsed.
4546 * So, pattern choice is depened on the purpose of configuration of
4549 * action RSS will be used to transmit valid parameter with
4550 * struct rte_flow_action_rss for all the 3 case.
4553 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4554 const struct rte_flow_item *pattern,
4555 struct rte_flow_error *error,
4556 struct i40e_rss_pattern_info *p_info,
4557 struct i40e_queue_regions *info)
4559 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4560 const struct rte_flow_item *item = pattern;
4561 enum rte_flow_item_type item_type;
4562 struct rte_flow_item *items;
4563 uint32_t item_num = 0; /* non-void item number of pattern*/
4565 static const struct {
4566 enum rte_flow_item_type *item_array;
4568 } i40e_rss_pctype_patterns[] = {
4569 { pattern_fdir_ipv4,
4570 ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER },
4571 { pattern_fdir_ipv4_tcp, ETH_RSS_NONFRAG_IPV4_TCP },
4572 { pattern_fdir_ipv4_udp, ETH_RSS_NONFRAG_IPV4_UDP },
4573 { pattern_fdir_ipv4_sctp, ETH_RSS_NONFRAG_IPV4_SCTP },
4574 { pattern_fdir_ipv4_esp, ETH_RSS_ESP },
4575 { pattern_fdir_ipv4_udp_esp, ETH_RSS_ESP },
4576 { pattern_fdir_ipv6,
4577 ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER },
4578 { pattern_fdir_ipv6_tcp, ETH_RSS_NONFRAG_IPV6_TCP },
4579 { pattern_fdir_ipv6_udp, ETH_RSS_NONFRAG_IPV6_UDP },
4580 { pattern_fdir_ipv6_sctp, ETH_RSS_NONFRAG_IPV6_SCTP },
4581 { pattern_ethertype, ETH_RSS_L2_PAYLOAD },
4582 { pattern_fdir_ipv6_esp, ETH_RSS_ESP },
4583 { pattern_fdir_ipv6_udp_esp, ETH_RSS_ESP },
4586 p_info->types = I40E_RSS_TYPE_INVALID;
4588 if (item->type == RTE_FLOW_ITEM_TYPE_END) {
4589 p_info->types = I40E_RSS_TYPE_NONE;
4593 /* Convert pattern to RSS offload types */
4594 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4595 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4601 items = rte_zmalloc("i40e_pattern",
4602 item_num * sizeof(struct rte_flow_item), 0);
4604 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4605 NULL, "No memory for PMD internal items.");
4609 i40e_pattern_skip_void_item(items, pattern);
4611 for (i = 0; i < RTE_DIM(i40e_rss_pctype_patterns); i++) {
4612 if (i40e_match_pattern(i40e_rss_pctype_patterns[i].item_array,
4614 p_info->types = i40e_rss_pctype_patterns[i].type;
4621 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4623 rte_flow_error_set(error, EINVAL,
4624 RTE_FLOW_ERROR_TYPE_ITEM,
4626 "Not support range");
4629 item_type = item->type;
4630 switch (item_type) {
4631 case RTE_FLOW_ITEM_TYPE_ETH:
4632 p_info->action_flag = 1;
4634 case RTE_FLOW_ITEM_TYPE_VLAN:
4635 vlan_spec = item->spec;
4636 vlan_mask = item->mask;
4637 if (vlan_spec && vlan_mask) {
4638 if (vlan_mask->tci ==
4639 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) {
4640 info->region[0].user_priority[0] =
4642 vlan_spec->tci) >> 13) & 0x7;
4643 info->region[0].user_priority_num = 1;
4644 info->queue_region_number = 1;
4645 p_info->action_flag = 0;
4650 p_info->action_flag = 0;
4651 memset(info, 0, sizeof(struct i40e_queue_regions));
4660 * This function is used to parse RSS queue index, total queue number and
4661 * hash functions, If the purpose of this configuration is for queue region
4662 * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4663 * In queue region configuration, it also need to parse hardware flowtype
4664 * and user_priority from configuration, it will also cheeck the validity
4665 * of these parameters. For example, The queue region sizes should
4666 * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4667 * hw_flowtype or PCTYPE max index should be 63, the user priority
4668 * max index should be 7, and so on. And also, queue index should be
4669 * continuous sequence and queue region index should be part of RSS
4670 * queue index for this port.
4671 * For hash params, the pctype in action and pattern must be same.
4672 * Set queue index must be with non-types.
4675 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4676 const struct rte_flow_action *actions,
4677 struct rte_flow_error *error,
4678 struct i40e_rss_pattern_info p_info,
4679 struct i40e_queue_regions *conf_info,
4680 union i40e_filter_t *filter)
4682 const struct rte_flow_action *act;
4683 const struct rte_flow_action_rss *rss;
4684 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686 struct i40e_queue_regions *info = &pf->queue_region;
4687 struct i40e_rte_flow_rss_conf *rss_config =
4689 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4690 uint16_t i, j, n, m, tmp, nb_types;
4692 uint64_t hf_bit = 1;
4694 static const struct {
4696 enum i40e_filter_pctype pctype;
4697 } pctype_match_table[] = {
4699 I40E_FILTER_PCTYPE_FRAG_IPV4},
4700 {ETH_RSS_NONFRAG_IPV4_TCP,
4701 I40E_FILTER_PCTYPE_NONF_IPV4_TCP},
4702 {ETH_RSS_NONFRAG_IPV4_UDP,
4703 I40E_FILTER_PCTYPE_NONF_IPV4_UDP},
4704 {ETH_RSS_NONFRAG_IPV4_SCTP,
4705 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP},
4706 {ETH_RSS_NONFRAG_IPV4_OTHER,
4707 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER},
4709 I40E_FILTER_PCTYPE_FRAG_IPV6},
4710 {ETH_RSS_NONFRAG_IPV6_TCP,
4711 I40E_FILTER_PCTYPE_NONF_IPV6_TCP},
4712 {ETH_RSS_NONFRAG_IPV6_UDP,
4713 I40E_FILTER_PCTYPE_NONF_IPV6_UDP},
4714 {ETH_RSS_NONFRAG_IPV6_SCTP,
4715 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP},
4716 {ETH_RSS_NONFRAG_IPV6_OTHER,
4717 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER},
4718 {ETH_RSS_L2_PAYLOAD,
4719 I40E_FILTER_PCTYPE_L2_PAYLOAD},
4722 static const struct {
4724 enum i40e_filter_pctype pctype;
4725 } pctype_match_table_x722[] = {
4726 {ETH_RSS_NONFRAG_IPV4_TCP,
4727 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK},
4728 {ETH_RSS_NONFRAG_IPV4_UDP,
4729 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP},
4730 {ETH_RSS_NONFRAG_IPV4_UDP,
4731 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP},
4732 {ETH_RSS_NONFRAG_IPV6_TCP,
4733 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK},
4734 {ETH_RSS_NONFRAG_IPV6_UDP,
4735 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP},
4736 {ETH_RSS_NONFRAG_IPV6_UDP,
4737 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP},
4740 NEXT_ITEM_OF_ACTION(act, actions, index);
4744 * RSS only supports forwarding,
4745 * check if the first not void action is RSS.
4747 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4748 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4749 rte_flow_error_set(error, EINVAL,
4750 RTE_FLOW_ERROR_TYPE_ACTION,
4751 act, "Not supported action.");
4755 if (p_info.action_flag && rss->queue_num) {
4756 for (j = 0; j < RTE_DIM(pctype_match_table); j++) {
4757 if (rss->types & pctype_match_table[j].rss_type) {
4758 conf_info->region[0].hw_flowtype[0] =
4759 (uint8_t)pctype_match_table[j].pctype;
4760 conf_info->region[0].flowtype_num = 1;
4761 conf_info->queue_region_number = 1;
4766 if (hw->mac.type == I40E_MAC_X722)
4767 for (j = 0; j < RTE_DIM(pctype_match_table_x722); j++) {
4769 pctype_match_table_x722[j].rss_type) {
4770 m = conf_info->region[0].flowtype_num;
4771 conf_info->region[0].hw_flowtype[m] =
4772 pctype_match_table_x722[j].pctype;
4773 conf_info->region[0].flowtype_num++;
4774 conf_info->queue_region_number = 1;
4780 * Do some queue region related parameters check
4781 * in order to keep queue index for queue region to be
4782 * continuous sequence and also to be part of RSS
4783 * queue index for this port.
4785 if (conf_info->queue_region_number) {
4786 for (i = 0; i < rss->queue_num; i++) {
4787 for (j = 0; j < rss_info->conf.queue_num; j++) {
4788 if (rss->queue[i] == rss_info->conf.queue[j])
4791 if (j == rss_info->conf.queue_num) {
4792 rte_flow_error_set(error, EINVAL,
4793 RTE_FLOW_ERROR_TYPE_ACTION,
4800 for (i = 0; i < rss->queue_num - 1; i++) {
4801 if (rss->queue[i + 1] != rss->queue[i] + 1) {
4802 rte_flow_error_set(error, EINVAL,
4803 RTE_FLOW_ERROR_TYPE_ACTION,
4811 /* Parse queue region related parameters from configuration */
4812 for (n = 0; n < conf_info->queue_region_number; n++) {
4813 if (conf_info->region[n].user_priority_num ||
4814 conf_info->region[n].flowtype_num) {
4815 if (!((rte_is_power_of_2(rss->queue_num)) &&
4816 rss->queue_num <= 64)) {
4817 rte_flow_error_set(error, EINVAL,
4818 RTE_FLOW_ERROR_TYPE_ACTION,
4820 "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4821 "total number of queues do not exceed the VSI allocation");
4825 if (conf_info->region[n].user_priority[n] >=
4826 I40E_MAX_USER_PRIORITY) {
4827 rte_flow_error_set(error, EINVAL,
4828 RTE_FLOW_ERROR_TYPE_ACTION,
4830 "the user priority max index is 7");
4834 if (conf_info->region[n].hw_flowtype[n] >=
4835 I40E_FILTER_PCTYPE_MAX) {
4836 rte_flow_error_set(error, EINVAL,
4837 RTE_FLOW_ERROR_TYPE_ACTION,
4839 "the hw_flowtype or PCTYPE max index is 63");
4843 for (i = 0; i < info->queue_region_number; i++) {
4844 if (info->region[i].queue_num ==
4846 info->region[i].queue_start_index ==
4851 if (i == info->queue_region_number) {
4852 if (i > I40E_REGION_MAX_INDEX) {
4853 rte_flow_error_set(error, EINVAL,
4854 RTE_FLOW_ERROR_TYPE_ACTION,
4856 "the queue region max index is 7");
4860 info->region[i].queue_num =
4862 info->region[i].queue_start_index =
4864 info->region[i].region_id =
4865 info->queue_region_number;
4867 j = info->region[i].user_priority_num;
4868 tmp = conf_info->region[n].user_priority[0];
4869 if (conf_info->region[n].user_priority_num) {
4870 info->region[i].user_priority[j] = tmp;
4871 info->region[i].user_priority_num++;
4874 for (m = 0; m < conf_info->region[n].flowtype_num; m++) {
4875 j = info->region[i].flowtype_num;
4876 tmp = conf_info->region[n].hw_flowtype[m];
4877 info->region[i].hw_flowtype[j] = tmp;
4878 info->region[i].flowtype_num++;
4880 info->queue_region_number++;
4882 j = info->region[i].user_priority_num;
4883 tmp = conf_info->region[n].user_priority[0];
4884 if (conf_info->region[n].user_priority_num) {
4885 info->region[i].user_priority[j] = tmp;
4886 info->region[i].user_priority_num++;
4889 for (m = 0; m < conf_info->region[n].flowtype_num; m++) {
4890 j = info->region[i].flowtype_num;
4891 tmp = conf_info->region[n].hw_flowtype[m];
4892 info->region[i].hw_flowtype[j] = tmp;
4893 info->region[i].flowtype_num++;
4898 rss_config->queue_region_conf = TRUE;
4902 * Return function if this flow is used for queue region configuration
4904 if (rss_config->queue_region_conf)
4908 rte_flow_error_set(error, EINVAL,
4909 RTE_FLOW_ERROR_TYPE_ACTION,
4915 for (n = 0; n < rss->queue_num; n++) {
4916 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4917 rte_flow_error_set(error, EINVAL,
4918 RTE_FLOW_ERROR_TYPE_ACTION,
4920 "queue id > max number of queues");
4925 if (rss->queue_num && (p_info.types || rss->types))
4926 return rte_flow_error_set
4927 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4928 "RSS types must be empty while configuring queue region");
4930 /* validate pattern and pctype */
4931 if (!(rss->types & p_info.types) &&
4932 (rss->types || p_info.types) && !rss->queue_num)
4933 return rte_flow_error_set
4934 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
4935 act, "invalid pctype");
4938 for (n = 0; n < RTE_ETH_FLOW_MAX; n++) {
4939 if (rss->types & (hf_bit << n))
4942 return rte_flow_error_set
4943 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
4944 act, "multi pctype is not supported");
4947 if (rss->func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
4948 (p_info.types || rss->types || rss->queue_num))
4949 return rte_flow_error_set
4950 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4951 "pattern, type and queues must be empty while"
4952 " setting hash function as simple_xor");
4954 if (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ &&
4955 !(p_info.types && rss->types))
4956 return rte_flow_error_set
4957 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4958 "pctype and queues can not be empty while"
4959 " setting hash function as symmetric toeplitz");
4961 /* Parse RSS related parameters from configuration */
4962 if (rss->func >= RTE_ETH_HASH_FUNCTION_MAX ||
4963 rss->func == RTE_ETH_HASH_FUNCTION_TOEPLITZ)
4964 return rte_flow_error_set
4965 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4966 "RSS hash functions are not supported");
4968 return rte_flow_error_set
4969 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4970 "a nonzero RSS encapsulation level is not supported");
4971 if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4972 return rte_flow_error_set
4973 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4974 "RSS hash key too large");
4975 if (rss->queue_num > RTE_DIM(rss_config->queue))
4976 return rte_flow_error_set
4977 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4978 "too many queues for RSS context");
4979 if (i40e_rss_conf_init(rss_config, rss))
4980 return rte_flow_error_set
4981 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4982 "RSS context initialization failure");
4986 /* check if the next not void action is END */
4987 NEXT_ITEM_OF_ACTION(act, actions, index);
4988 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4989 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4990 rte_flow_error_set(error, EINVAL,
4991 RTE_FLOW_ERROR_TYPE_ACTION,
4992 act, "Not supported action.");
4995 rss_config->queue_region_conf = FALSE;
5001 i40e_parse_rss_filter(struct rte_eth_dev *dev,
5002 const struct rte_flow_attr *attr,
5003 const struct rte_flow_item pattern[],
5004 const struct rte_flow_action actions[],
5005 union i40e_filter_t *filter,
5006 struct rte_flow_error *error)
5008 struct i40e_rss_pattern_info p_info;
5009 struct i40e_queue_regions info;
5012 memset(&info, 0, sizeof(struct i40e_queue_regions));
5013 memset(&p_info, 0, sizeof(struct i40e_rss_pattern_info));
5015 ret = i40e_flow_parse_rss_pattern(dev, pattern,
5016 error, &p_info, &info);
5020 ret = i40e_flow_parse_rss_action(dev, actions, error,
5021 p_info, &info, filter);
5025 ret = i40e_flow_parse_attr(attr, error);
5029 cons_filter_type = RTE_ETH_FILTER_HASH;
5035 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
5036 struct i40e_rte_flow_rss_conf *conf)
5038 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5039 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5040 struct i40e_rss_filter *rss_filter;
5043 if (conf->queue_region_conf) {
5044 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
5046 ret = i40e_config_rss_filter(pf, conf, 1);
5052 rss_filter = rte_zmalloc("i40e_rss_filter",
5053 sizeof(*rss_filter), 0);
5054 if (rss_filter == NULL) {
5055 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5058 rss_filter->rss_filter_info = *conf;
5059 /* the rule new created is always valid
5060 * the existing rule covered by new rule will be set invalid
5062 rss_filter->rss_filter_info.valid = true;
5064 TAILQ_INSERT_TAIL(&pf->rss_config_list, rss_filter, next);
5070 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
5071 struct i40e_rte_flow_rss_conf *conf)
5073 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5074 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075 struct i40e_rss_filter *rss_filter;
5078 if (conf->queue_region_conf)
5079 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5081 i40e_config_rss_filter(pf, conf, 0);
5083 TAILQ_FOREACH_SAFE(rss_filter, &pf->rss_config_list, next, temp) {
5084 if (!memcmp(&rss_filter->rss_filter_info, conf,
5085 sizeof(struct rte_flow_action_rss))) {
5086 TAILQ_REMOVE(&pf->rss_config_list, rss_filter, next);
5087 rte_free(rss_filter);
5094 i40e_flow_validate(struct rte_eth_dev *dev,
5095 const struct rte_flow_attr *attr,
5096 const struct rte_flow_item pattern[],
5097 const struct rte_flow_action actions[],
5098 struct rte_flow_error *error)
5100 struct rte_flow_item *items; /* internal pattern w/o VOID items */
5101 parse_filter_t parse_filter;
5102 uint32_t item_num = 0; /* non-void item number of pattern*/
5105 int ret = I40E_NOT_SUPPORTED;
5108 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
5109 NULL, "NULL pattern.");
5114 rte_flow_error_set(error, EINVAL,
5115 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
5116 NULL, "NULL action.");
5121 rte_flow_error_set(error, EINVAL,
5122 RTE_FLOW_ERROR_TYPE_ATTR,
5123 NULL, "NULL attribute.");
5126 memset(&cons_filter, 0, sizeof(cons_filter));
5128 /* Get the non-void item of action */
5129 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
5132 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
5133 ret = i40e_parse_rss_filter(dev, attr, pattern,
5134 actions, &cons_filter, error);
5139 /* Get the non-void item number of pattern */
5140 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
5141 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
5147 if (item_num <= ARRAY_SIZE(g_items)) {
5150 items = rte_zmalloc("i40e_pattern",
5151 item_num * sizeof(struct rte_flow_item), 0);
5153 rte_flow_error_set(error, ENOMEM,
5154 RTE_FLOW_ERROR_TYPE_ITEM_NUM,
5156 "No memory for PMD internal items.");
5161 i40e_pattern_skip_void_item(items, pattern);
5165 parse_filter = i40e_find_parse_filter_func(items, &i);
5166 if (!parse_filter && !flag) {
5167 rte_flow_error_set(error, EINVAL,
5168 RTE_FLOW_ERROR_TYPE_ITEM,
5169 pattern, "Unsupported pattern");
5171 if (items != g_items)
5177 ret = parse_filter(dev, attr, items, actions,
5178 error, &cons_filter);
5181 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
5183 if (items != g_items)
5189 static struct rte_flow *
5190 i40e_flow_create(struct rte_eth_dev *dev,
5191 const struct rte_flow_attr *attr,
5192 const struct rte_flow_item pattern[],
5193 const struct rte_flow_action actions[],
5194 struct rte_flow_error *error)
5196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5197 struct rte_flow *flow = NULL;
5198 struct i40e_fdir_info *fdir_info = &pf->fdir;
5201 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
5205 if (cons_filter_type == RTE_ETH_FILTER_FDIR) {
5206 flow = i40e_fdir_entry_pool_get(fdir_info);
5208 rte_flow_error_set(error, ENOBUFS,
5209 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5215 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
5217 rte_flow_error_set(error, ENOMEM,
5218 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5219 "Failed to allocate memory");
5224 switch (cons_filter_type) {
5225 case RTE_ETH_FILTER_ETHERTYPE:
5226 ret = i40e_ethertype_filter_set(pf,
5227 &cons_filter.ethertype_filter, 1);
5230 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
5231 i40e_ethertype_filter_list);
5233 case RTE_ETH_FILTER_FDIR:
5234 ret = i40e_flow_add_del_fdir_filter(dev,
5235 &cons_filter.fdir_filter, 1);
5238 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
5239 i40e_fdir_filter_list);
5241 case RTE_ETH_FILTER_TUNNEL:
5242 ret = i40e_dev_consistent_tunnel_filter_set(pf,
5243 &cons_filter.consistent_tunnel_filter, 1);
5246 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
5247 i40e_tunnel_filter_list);
5249 case RTE_ETH_FILTER_HASH:
5250 ret = i40e_config_rss_filter_set(dev,
5251 &cons_filter.rss_conf);
5254 flow->rule = TAILQ_LAST(&pf->rss_config_list,
5255 i40e_rss_conf_list);
5261 flow->filter_type = cons_filter_type;
5262 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
5266 rte_flow_error_set(error, -ret,
5267 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5268 "Failed to create flow.");
5270 if (cons_filter_type != RTE_ETH_FILTER_FDIR)
5273 i40e_fdir_entry_pool_put(fdir_info, flow);
5279 i40e_flow_destroy(struct rte_eth_dev *dev,
5280 struct rte_flow *flow,
5281 struct rte_flow_error *error)
5283 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5284 enum rte_filter_type filter_type = flow->filter_type;
5285 struct i40e_fdir_info *fdir_info = &pf->fdir;
5288 switch (filter_type) {
5289 case RTE_ETH_FILTER_ETHERTYPE:
5290 ret = i40e_flow_destroy_ethertype_filter(pf,
5291 (struct i40e_ethertype_filter *)flow->rule);
5293 case RTE_ETH_FILTER_TUNNEL:
5294 ret = i40e_flow_destroy_tunnel_filter(pf,
5295 (struct i40e_tunnel_filter *)flow->rule);
5297 case RTE_ETH_FILTER_FDIR:
5298 ret = i40e_flow_add_del_fdir_filter(dev,
5299 &((struct i40e_fdir_filter *)flow->rule)->fdir,
5302 /* If the last flow is destroyed, disable fdir. */
5303 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) {
5304 i40e_fdir_rx_proc_enable(dev, 0);
5307 case RTE_ETH_FILTER_HASH:
5308 ret = i40e_config_rss_filter_del(dev,
5309 &((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
5312 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5319 TAILQ_REMOVE(&pf->flow_list, flow, node);
5320 if (filter_type == RTE_ETH_FILTER_FDIR)
5321 i40e_fdir_entry_pool_put(fdir_info, flow);
5326 rte_flow_error_set(error, -ret,
5327 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5328 "Failed to destroy flow.");
5334 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
5335 struct i40e_ethertype_filter *filter)
5337 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5338 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
5339 struct i40e_ethertype_filter *node;
5340 struct i40e_control_filter_stats stats;
5344 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5345 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5346 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5347 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5348 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5350 memset(&stats, 0, sizeof(stats));
5351 ret = i40e_aq_add_rem_control_packet_filter(hw,
5352 filter->input.mac_addr.addr_bytes,
5353 filter->input.ether_type,
5354 flags, pf->main_vsi->seid,
5355 filter->queue, 0, &stats, NULL);
5359 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
5363 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
5369 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
5370 struct i40e_tunnel_filter *filter)
5372 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5373 struct i40e_vsi *vsi;
5374 struct i40e_pf_vf *vf;
5375 struct i40e_aqc_cloud_filters_element_bb cld_filter;
5376 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
5377 struct i40e_tunnel_filter *node;
5378 bool big_buffer = 0;
5381 memset(&cld_filter, 0, sizeof(cld_filter));
5382 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
5383 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
5384 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
5385 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
5386 cld_filter.element.inner_vlan = filter->input.inner_vlan;
5387 cld_filter.element.flags = filter->input.flags;
5388 cld_filter.element.tenant_id = filter->input.tenant_id;
5389 cld_filter.element.queue_number = filter->queue;
5390 rte_memcpy(cld_filter.general_fields,
5391 filter->input.general_fields,
5392 sizeof(cld_filter.general_fields));
5394 if (!filter->is_to_vf)
5397 vf = &pf->vfs[filter->vf_id];
5401 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
5402 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
5403 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
5404 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
5405 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
5406 I40E_AQC_ADD_CLOUD_FILTER_0X10))
5410 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
5413 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
5414 &cld_filter.element, 1);
5418 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
5422 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
5428 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
5430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5433 ret = i40e_flow_flush_fdir_filter(pf);
5435 rte_flow_error_set(error, -ret,
5436 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5437 "Failed to flush FDIR flows.");
5441 ret = i40e_flow_flush_ethertype_filter(pf);
5443 rte_flow_error_set(error, -ret,
5444 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5445 "Failed to ethertype flush flows.");
5449 ret = i40e_flow_flush_tunnel_filter(pf);
5451 rte_flow_error_set(error, -ret,
5452 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5453 "Failed to flush tunnel flows.");
5457 ret = i40e_flow_flush_rss_filter(dev);
5459 rte_flow_error_set(error, -ret,
5460 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5461 "Failed to flush RSS flows.");
5469 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
5471 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5472 struct i40e_fdir_info *fdir_info = &pf->fdir;
5473 struct i40e_fdir_filter *fdir_filter;
5474 enum i40e_filter_pctype pctype;
5475 struct rte_flow *flow;
5480 ret = i40e_fdir_flush(dev);
5482 /* Delete FDIR filters in FDIR list. */
5483 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
5484 ret = i40e_sw_fdir_filter_del(pf,
5485 &fdir_filter->fdir.input);
5490 /* Delete FDIR flows in flow list. */
5491 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5492 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
5493 TAILQ_REMOVE(&pf->flow_list, flow, node);
5498 rte_bitmap_reset(fdir_info->fdir_flow_pool.bitmap);
5499 for (i = 0; i < fdir_info->fdir_space_size; i++) {
5500 fdir_info->fdir_flow_pool.pool[i].idx = i;
5501 rte_bitmap_set(fdir_info->fdir_flow_pool.bitmap, i);
5504 fdir_info->fdir_actual_cnt = 0;
5505 fdir_info->fdir_guarantee_free_space =
5506 fdir_info->fdir_guarantee_total_space;
5507 memset(fdir_info->fdir_filter_array,
5509 sizeof(struct i40e_fdir_filter) *
5510 I40E_MAX_FDIR_FILTER_NUM);
5512 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5513 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
5514 pf->fdir.inset_flag[pctype] = 0;
5515 pf->fdir.flex_mask_flag[pctype] = 0;
5518 /* Disable FDIR processing as all FDIR rules are now flushed */
5519 i40e_fdir_rx_proc_enable(dev, 0);
5525 /* Flush all ethertype filters */
5527 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
5529 struct i40e_ethertype_filter_list
5530 *ethertype_list = &pf->ethertype.ethertype_list;
5531 struct i40e_ethertype_filter *filter;
5532 struct rte_flow *flow;
5536 while ((filter = TAILQ_FIRST(ethertype_list))) {
5537 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
5542 /* Delete ethertype flows in flow list. */
5543 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5544 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
5545 TAILQ_REMOVE(&pf->flow_list, flow, node);
5553 /* Flush all tunnel filters */
5555 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5557 struct i40e_tunnel_filter_list
5558 *tunnel_list = &pf->tunnel.tunnel_list;
5559 struct i40e_tunnel_filter *filter;
5560 struct rte_flow *flow;
5564 while ((filter = TAILQ_FIRST(tunnel_list))) {
5565 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5570 /* Delete tunnel flows in flow list. */
5571 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5572 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5573 TAILQ_REMOVE(&pf->flow_list, flow, node);
5581 /* remove the RSS filter */
5583 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5585 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5587 struct rte_flow *flow;
5589 int32_t ret = -EINVAL;
5591 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5593 /* Delete RSS flows in flow list. */
5594 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5595 if (flow->filter_type != RTE_ETH_FILTER_HASH)
5599 ret = i40e_config_rss_filter_del(dev,
5600 &((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
5604 TAILQ_REMOVE(&pf->flow_list, flow, node);
5612 i40e_flow_query(struct rte_eth_dev *dev __rte_unused,
5613 struct rte_flow *flow,
5614 const struct rte_flow_action *actions,
5615 void *data, struct rte_flow_error *error)
5617 struct i40e_rss_filter *rss_rule = (struct i40e_rss_filter *)flow->rule;
5618 enum rte_filter_type filter_type = flow->filter_type;
5619 struct rte_flow_action_rss *rss_conf = data;
5622 rte_flow_error_set(error, EINVAL,
5623 RTE_FLOW_ERROR_TYPE_HANDLE,
5624 NULL, "Invalid rule");
5628 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5629 switch (actions->type) {
5630 case RTE_FLOW_ACTION_TYPE_VOID:
5632 case RTE_FLOW_ACTION_TYPE_RSS:
5633 if (filter_type != RTE_ETH_FILTER_HASH) {
5634 rte_flow_error_set(error, ENOTSUP,
5635 RTE_FLOW_ERROR_TYPE_ACTION,
5637 "action not supported");
5640 rte_memcpy(rss_conf,
5641 &rss_rule->rss_filter_info.conf,
5642 sizeof(struct rte_flow_action_rss));
5645 return rte_flow_error_set(error, ENOTSUP,
5646 RTE_FLOW_ERROR_TYPE_ACTION,
5648 "action not supported");