1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
13 #include <rte_debug.h>
14 #include <rte_ether.h>
15 #include <rte_ethdev_driver.h>
17 #include <rte_malloc.h>
18 #include <rte_tailq.h>
19 #include <rte_flow_driver.h>
21 #include "i40e_logs.h"
22 #include "base/i40e_type.h"
23 #include "base/i40e_prototype.h"
24 #include "i40e_ethdev.h"
26 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
27 #define I40E_IPV6_FRAG_HEADER 44
28 #define I40E_TENANT_ARRAY_NUM 3
29 #define I40E_TCI_MASK 0xFFFF
31 static int i40e_flow_validate(struct rte_eth_dev *dev,
32 const struct rte_flow_attr *attr,
33 const struct rte_flow_item pattern[],
34 const struct rte_flow_action actions[],
35 struct rte_flow_error *error);
36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
37 const struct rte_flow_attr *attr,
38 const struct rte_flow_item pattern[],
39 const struct rte_flow_action actions[],
40 struct rte_flow_error *error);
41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
42 struct rte_flow *flow,
43 struct rte_flow_error *error);
44 static int i40e_flow_flush(struct rte_eth_dev *dev,
45 struct rte_flow_error *error);
47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
48 const struct rte_flow_item *pattern,
49 struct rte_flow_error *error,
50 struct rte_eth_ethertype_filter *filter);
51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
52 const struct rte_flow_action *actions,
53 struct rte_flow_error *error,
54 struct rte_eth_ethertype_filter *filter);
55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
56 const struct rte_flow_attr *attr,
57 const struct rte_flow_item *pattern,
58 struct rte_flow_error *error,
59 struct i40e_fdir_filter_conf *filter);
60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
61 const struct rte_flow_action *actions,
62 struct rte_flow_error *error,
63 struct i40e_fdir_filter_conf *filter);
64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
65 const struct rte_flow_action *actions,
66 struct rte_flow_error *error,
67 struct i40e_tunnel_filter_conf *filter);
68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
69 struct rte_flow_error *error);
70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
71 const struct rte_flow_attr *attr,
72 const struct rte_flow_item pattern[],
73 const struct rte_flow_action actions[],
74 struct rte_flow_error *error,
75 union i40e_filter_t *filter);
76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
77 const struct rte_flow_attr *attr,
78 const struct rte_flow_item pattern[],
79 const struct rte_flow_action actions[],
80 struct rte_flow_error *error,
81 union i40e_filter_t *filter);
82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
83 const struct rte_flow_attr *attr,
84 const struct rte_flow_item pattern[],
85 const struct rte_flow_action actions[],
86 struct rte_flow_error *error,
87 union i40e_filter_t *filter);
88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
89 const struct rte_flow_attr *attr,
90 const struct rte_flow_item pattern[],
91 const struct rte_flow_action actions[],
92 struct rte_flow_error *error,
93 union i40e_filter_t *filter);
94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
95 const struct rte_flow_attr *attr,
96 const struct rte_flow_item pattern[],
97 const struct rte_flow_action actions[],
98 struct rte_flow_error *error,
99 union i40e_filter_t *filter);
100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
101 const struct rte_flow_attr *attr,
102 const struct rte_flow_item pattern[],
103 const struct rte_flow_action actions[],
104 struct rte_flow_error *error,
105 union i40e_filter_t *filter);
106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
107 struct i40e_ethertype_filter *filter);
108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
109 struct i40e_tunnel_filter *filter);
110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
113 static int i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
116 const struct rte_flow_attr *attr,
117 const struct rte_flow_item pattern[],
118 const struct rte_flow_action actions[],
119 struct rte_flow_error *error,
120 union i40e_filter_t *filter);
122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
123 const struct rte_flow_item *pattern,
124 struct rte_flow_error *error,
125 struct i40e_tunnel_filter_conf *filter);
127 const struct rte_flow_ops i40e_flow_ops = {
128 .validate = i40e_flow_validate,
129 .create = i40e_flow_create,
130 .destroy = i40e_flow_destroy,
131 .flush = i40e_flow_flush,
134 static union i40e_filter_t cons_filter;
135 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
137 /* Pattern matched ethertype filter */
138 static enum rte_flow_item_type pattern_ethertype[] = {
139 RTE_FLOW_ITEM_TYPE_ETH,
140 RTE_FLOW_ITEM_TYPE_END,
143 /* Pattern matched flow director filter */
144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
145 RTE_FLOW_ITEM_TYPE_ETH,
146 RTE_FLOW_ITEM_TYPE_IPV4,
147 RTE_FLOW_ITEM_TYPE_END,
150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
151 RTE_FLOW_ITEM_TYPE_ETH,
152 RTE_FLOW_ITEM_TYPE_IPV4,
153 RTE_FLOW_ITEM_TYPE_UDP,
154 RTE_FLOW_ITEM_TYPE_END,
157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
158 RTE_FLOW_ITEM_TYPE_ETH,
159 RTE_FLOW_ITEM_TYPE_IPV4,
160 RTE_FLOW_ITEM_TYPE_TCP,
161 RTE_FLOW_ITEM_TYPE_END,
164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
165 RTE_FLOW_ITEM_TYPE_ETH,
166 RTE_FLOW_ITEM_TYPE_IPV4,
167 RTE_FLOW_ITEM_TYPE_SCTP,
168 RTE_FLOW_ITEM_TYPE_END,
171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
172 RTE_FLOW_ITEM_TYPE_ETH,
173 RTE_FLOW_ITEM_TYPE_IPV4,
174 RTE_FLOW_ITEM_TYPE_UDP,
175 RTE_FLOW_ITEM_TYPE_GTPC,
176 RTE_FLOW_ITEM_TYPE_END,
179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
180 RTE_FLOW_ITEM_TYPE_ETH,
181 RTE_FLOW_ITEM_TYPE_IPV4,
182 RTE_FLOW_ITEM_TYPE_UDP,
183 RTE_FLOW_ITEM_TYPE_GTPU,
184 RTE_FLOW_ITEM_TYPE_END,
187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
188 RTE_FLOW_ITEM_TYPE_ETH,
189 RTE_FLOW_ITEM_TYPE_IPV4,
190 RTE_FLOW_ITEM_TYPE_UDP,
191 RTE_FLOW_ITEM_TYPE_GTPU,
192 RTE_FLOW_ITEM_TYPE_IPV4,
193 RTE_FLOW_ITEM_TYPE_END,
196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
197 RTE_FLOW_ITEM_TYPE_ETH,
198 RTE_FLOW_ITEM_TYPE_IPV4,
199 RTE_FLOW_ITEM_TYPE_UDP,
200 RTE_FLOW_ITEM_TYPE_GTPU,
201 RTE_FLOW_ITEM_TYPE_IPV6,
202 RTE_FLOW_ITEM_TYPE_END,
205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
206 RTE_FLOW_ITEM_TYPE_ETH,
207 RTE_FLOW_ITEM_TYPE_IPV6,
208 RTE_FLOW_ITEM_TYPE_END,
211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
212 RTE_FLOW_ITEM_TYPE_ETH,
213 RTE_FLOW_ITEM_TYPE_IPV6,
214 RTE_FLOW_ITEM_TYPE_UDP,
215 RTE_FLOW_ITEM_TYPE_END,
218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
219 RTE_FLOW_ITEM_TYPE_ETH,
220 RTE_FLOW_ITEM_TYPE_IPV6,
221 RTE_FLOW_ITEM_TYPE_TCP,
222 RTE_FLOW_ITEM_TYPE_END,
225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
226 RTE_FLOW_ITEM_TYPE_ETH,
227 RTE_FLOW_ITEM_TYPE_IPV6,
228 RTE_FLOW_ITEM_TYPE_SCTP,
229 RTE_FLOW_ITEM_TYPE_END,
232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
233 RTE_FLOW_ITEM_TYPE_ETH,
234 RTE_FLOW_ITEM_TYPE_IPV6,
235 RTE_FLOW_ITEM_TYPE_UDP,
236 RTE_FLOW_ITEM_TYPE_GTPC,
237 RTE_FLOW_ITEM_TYPE_END,
240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
241 RTE_FLOW_ITEM_TYPE_ETH,
242 RTE_FLOW_ITEM_TYPE_IPV6,
243 RTE_FLOW_ITEM_TYPE_UDP,
244 RTE_FLOW_ITEM_TYPE_GTPU,
245 RTE_FLOW_ITEM_TYPE_END,
248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
249 RTE_FLOW_ITEM_TYPE_ETH,
250 RTE_FLOW_ITEM_TYPE_IPV6,
251 RTE_FLOW_ITEM_TYPE_UDP,
252 RTE_FLOW_ITEM_TYPE_GTPU,
253 RTE_FLOW_ITEM_TYPE_IPV4,
254 RTE_FLOW_ITEM_TYPE_END,
257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
258 RTE_FLOW_ITEM_TYPE_ETH,
259 RTE_FLOW_ITEM_TYPE_IPV6,
260 RTE_FLOW_ITEM_TYPE_UDP,
261 RTE_FLOW_ITEM_TYPE_GTPU,
262 RTE_FLOW_ITEM_TYPE_IPV6,
263 RTE_FLOW_ITEM_TYPE_END,
266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
267 RTE_FLOW_ITEM_TYPE_ETH,
268 RTE_FLOW_ITEM_TYPE_RAW,
269 RTE_FLOW_ITEM_TYPE_END,
272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
273 RTE_FLOW_ITEM_TYPE_ETH,
274 RTE_FLOW_ITEM_TYPE_RAW,
275 RTE_FLOW_ITEM_TYPE_RAW,
276 RTE_FLOW_ITEM_TYPE_END,
279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
280 RTE_FLOW_ITEM_TYPE_ETH,
281 RTE_FLOW_ITEM_TYPE_RAW,
282 RTE_FLOW_ITEM_TYPE_RAW,
283 RTE_FLOW_ITEM_TYPE_RAW,
284 RTE_FLOW_ITEM_TYPE_END,
287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
288 RTE_FLOW_ITEM_TYPE_ETH,
289 RTE_FLOW_ITEM_TYPE_IPV4,
290 RTE_FLOW_ITEM_TYPE_RAW,
291 RTE_FLOW_ITEM_TYPE_END,
294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
295 RTE_FLOW_ITEM_TYPE_ETH,
296 RTE_FLOW_ITEM_TYPE_IPV4,
297 RTE_FLOW_ITEM_TYPE_RAW,
298 RTE_FLOW_ITEM_TYPE_RAW,
299 RTE_FLOW_ITEM_TYPE_END,
302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
303 RTE_FLOW_ITEM_TYPE_ETH,
304 RTE_FLOW_ITEM_TYPE_IPV4,
305 RTE_FLOW_ITEM_TYPE_RAW,
306 RTE_FLOW_ITEM_TYPE_RAW,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_END,
311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
312 RTE_FLOW_ITEM_TYPE_ETH,
313 RTE_FLOW_ITEM_TYPE_IPV4,
314 RTE_FLOW_ITEM_TYPE_UDP,
315 RTE_FLOW_ITEM_TYPE_RAW,
316 RTE_FLOW_ITEM_TYPE_END,
319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
320 RTE_FLOW_ITEM_TYPE_ETH,
321 RTE_FLOW_ITEM_TYPE_IPV4,
322 RTE_FLOW_ITEM_TYPE_UDP,
323 RTE_FLOW_ITEM_TYPE_RAW,
324 RTE_FLOW_ITEM_TYPE_RAW,
325 RTE_FLOW_ITEM_TYPE_END,
328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
329 RTE_FLOW_ITEM_TYPE_ETH,
330 RTE_FLOW_ITEM_TYPE_IPV4,
331 RTE_FLOW_ITEM_TYPE_UDP,
332 RTE_FLOW_ITEM_TYPE_RAW,
333 RTE_FLOW_ITEM_TYPE_RAW,
334 RTE_FLOW_ITEM_TYPE_RAW,
335 RTE_FLOW_ITEM_TYPE_END,
338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
339 RTE_FLOW_ITEM_TYPE_ETH,
340 RTE_FLOW_ITEM_TYPE_IPV4,
341 RTE_FLOW_ITEM_TYPE_TCP,
342 RTE_FLOW_ITEM_TYPE_RAW,
343 RTE_FLOW_ITEM_TYPE_END,
346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
347 RTE_FLOW_ITEM_TYPE_ETH,
348 RTE_FLOW_ITEM_TYPE_IPV4,
349 RTE_FLOW_ITEM_TYPE_TCP,
350 RTE_FLOW_ITEM_TYPE_RAW,
351 RTE_FLOW_ITEM_TYPE_RAW,
352 RTE_FLOW_ITEM_TYPE_END,
355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
356 RTE_FLOW_ITEM_TYPE_ETH,
357 RTE_FLOW_ITEM_TYPE_IPV4,
358 RTE_FLOW_ITEM_TYPE_TCP,
359 RTE_FLOW_ITEM_TYPE_RAW,
360 RTE_FLOW_ITEM_TYPE_RAW,
361 RTE_FLOW_ITEM_TYPE_RAW,
362 RTE_FLOW_ITEM_TYPE_END,
365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
366 RTE_FLOW_ITEM_TYPE_ETH,
367 RTE_FLOW_ITEM_TYPE_IPV4,
368 RTE_FLOW_ITEM_TYPE_SCTP,
369 RTE_FLOW_ITEM_TYPE_RAW,
370 RTE_FLOW_ITEM_TYPE_END,
373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
374 RTE_FLOW_ITEM_TYPE_ETH,
375 RTE_FLOW_ITEM_TYPE_IPV4,
376 RTE_FLOW_ITEM_TYPE_SCTP,
377 RTE_FLOW_ITEM_TYPE_RAW,
378 RTE_FLOW_ITEM_TYPE_RAW,
379 RTE_FLOW_ITEM_TYPE_END,
382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
383 RTE_FLOW_ITEM_TYPE_ETH,
384 RTE_FLOW_ITEM_TYPE_IPV4,
385 RTE_FLOW_ITEM_TYPE_SCTP,
386 RTE_FLOW_ITEM_TYPE_RAW,
387 RTE_FLOW_ITEM_TYPE_RAW,
388 RTE_FLOW_ITEM_TYPE_RAW,
389 RTE_FLOW_ITEM_TYPE_END,
392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
393 RTE_FLOW_ITEM_TYPE_ETH,
394 RTE_FLOW_ITEM_TYPE_IPV6,
395 RTE_FLOW_ITEM_TYPE_RAW,
396 RTE_FLOW_ITEM_TYPE_END,
399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
400 RTE_FLOW_ITEM_TYPE_ETH,
401 RTE_FLOW_ITEM_TYPE_IPV6,
402 RTE_FLOW_ITEM_TYPE_RAW,
403 RTE_FLOW_ITEM_TYPE_RAW,
404 RTE_FLOW_ITEM_TYPE_END,
407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
408 RTE_FLOW_ITEM_TYPE_ETH,
409 RTE_FLOW_ITEM_TYPE_IPV6,
410 RTE_FLOW_ITEM_TYPE_RAW,
411 RTE_FLOW_ITEM_TYPE_RAW,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_END,
416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
417 RTE_FLOW_ITEM_TYPE_ETH,
418 RTE_FLOW_ITEM_TYPE_IPV6,
419 RTE_FLOW_ITEM_TYPE_UDP,
420 RTE_FLOW_ITEM_TYPE_RAW,
421 RTE_FLOW_ITEM_TYPE_END,
424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
425 RTE_FLOW_ITEM_TYPE_ETH,
426 RTE_FLOW_ITEM_TYPE_IPV6,
427 RTE_FLOW_ITEM_TYPE_UDP,
428 RTE_FLOW_ITEM_TYPE_RAW,
429 RTE_FLOW_ITEM_TYPE_RAW,
430 RTE_FLOW_ITEM_TYPE_END,
433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
434 RTE_FLOW_ITEM_TYPE_ETH,
435 RTE_FLOW_ITEM_TYPE_IPV6,
436 RTE_FLOW_ITEM_TYPE_UDP,
437 RTE_FLOW_ITEM_TYPE_RAW,
438 RTE_FLOW_ITEM_TYPE_RAW,
439 RTE_FLOW_ITEM_TYPE_RAW,
440 RTE_FLOW_ITEM_TYPE_END,
443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
444 RTE_FLOW_ITEM_TYPE_ETH,
445 RTE_FLOW_ITEM_TYPE_IPV6,
446 RTE_FLOW_ITEM_TYPE_TCP,
447 RTE_FLOW_ITEM_TYPE_RAW,
448 RTE_FLOW_ITEM_TYPE_END,
451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
452 RTE_FLOW_ITEM_TYPE_ETH,
453 RTE_FLOW_ITEM_TYPE_IPV6,
454 RTE_FLOW_ITEM_TYPE_TCP,
455 RTE_FLOW_ITEM_TYPE_RAW,
456 RTE_FLOW_ITEM_TYPE_RAW,
457 RTE_FLOW_ITEM_TYPE_END,
460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
461 RTE_FLOW_ITEM_TYPE_ETH,
462 RTE_FLOW_ITEM_TYPE_IPV6,
463 RTE_FLOW_ITEM_TYPE_TCP,
464 RTE_FLOW_ITEM_TYPE_RAW,
465 RTE_FLOW_ITEM_TYPE_RAW,
466 RTE_FLOW_ITEM_TYPE_RAW,
467 RTE_FLOW_ITEM_TYPE_END,
470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
471 RTE_FLOW_ITEM_TYPE_ETH,
472 RTE_FLOW_ITEM_TYPE_IPV6,
473 RTE_FLOW_ITEM_TYPE_SCTP,
474 RTE_FLOW_ITEM_TYPE_RAW,
475 RTE_FLOW_ITEM_TYPE_END,
478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
479 RTE_FLOW_ITEM_TYPE_ETH,
480 RTE_FLOW_ITEM_TYPE_IPV6,
481 RTE_FLOW_ITEM_TYPE_SCTP,
482 RTE_FLOW_ITEM_TYPE_RAW,
483 RTE_FLOW_ITEM_TYPE_RAW,
484 RTE_FLOW_ITEM_TYPE_END,
487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
488 RTE_FLOW_ITEM_TYPE_ETH,
489 RTE_FLOW_ITEM_TYPE_IPV6,
490 RTE_FLOW_ITEM_TYPE_SCTP,
491 RTE_FLOW_ITEM_TYPE_RAW,
492 RTE_FLOW_ITEM_TYPE_RAW,
493 RTE_FLOW_ITEM_TYPE_RAW,
494 RTE_FLOW_ITEM_TYPE_END,
497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
498 RTE_FLOW_ITEM_TYPE_ETH,
499 RTE_FLOW_ITEM_TYPE_VLAN,
500 RTE_FLOW_ITEM_TYPE_END,
503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
504 RTE_FLOW_ITEM_TYPE_ETH,
505 RTE_FLOW_ITEM_TYPE_VLAN,
506 RTE_FLOW_ITEM_TYPE_IPV4,
507 RTE_FLOW_ITEM_TYPE_END,
510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
511 RTE_FLOW_ITEM_TYPE_ETH,
512 RTE_FLOW_ITEM_TYPE_VLAN,
513 RTE_FLOW_ITEM_TYPE_IPV4,
514 RTE_FLOW_ITEM_TYPE_UDP,
515 RTE_FLOW_ITEM_TYPE_END,
518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
519 RTE_FLOW_ITEM_TYPE_ETH,
520 RTE_FLOW_ITEM_TYPE_VLAN,
521 RTE_FLOW_ITEM_TYPE_IPV4,
522 RTE_FLOW_ITEM_TYPE_TCP,
523 RTE_FLOW_ITEM_TYPE_END,
526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
527 RTE_FLOW_ITEM_TYPE_ETH,
528 RTE_FLOW_ITEM_TYPE_VLAN,
529 RTE_FLOW_ITEM_TYPE_IPV4,
530 RTE_FLOW_ITEM_TYPE_SCTP,
531 RTE_FLOW_ITEM_TYPE_END,
534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
535 RTE_FLOW_ITEM_TYPE_ETH,
536 RTE_FLOW_ITEM_TYPE_VLAN,
537 RTE_FLOW_ITEM_TYPE_IPV6,
538 RTE_FLOW_ITEM_TYPE_END,
541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
542 RTE_FLOW_ITEM_TYPE_ETH,
543 RTE_FLOW_ITEM_TYPE_VLAN,
544 RTE_FLOW_ITEM_TYPE_IPV6,
545 RTE_FLOW_ITEM_TYPE_UDP,
546 RTE_FLOW_ITEM_TYPE_END,
549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
550 RTE_FLOW_ITEM_TYPE_ETH,
551 RTE_FLOW_ITEM_TYPE_VLAN,
552 RTE_FLOW_ITEM_TYPE_IPV6,
553 RTE_FLOW_ITEM_TYPE_TCP,
554 RTE_FLOW_ITEM_TYPE_END,
557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
558 RTE_FLOW_ITEM_TYPE_ETH,
559 RTE_FLOW_ITEM_TYPE_VLAN,
560 RTE_FLOW_ITEM_TYPE_IPV6,
561 RTE_FLOW_ITEM_TYPE_SCTP,
562 RTE_FLOW_ITEM_TYPE_END,
565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
566 RTE_FLOW_ITEM_TYPE_ETH,
567 RTE_FLOW_ITEM_TYPE_VLAN,
568 RTE_FLOW_ITEM_TYPE_RAW,
569 RTE_FLOW_ITEM_TYPE_END,
572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
573 RTE_FLOW_ITEM_TYPE_ETH,
574 RTE_FLOW_ITEM_TYPE_VLAN,
575 RTE_FLOW_ITEM_TYPE_RAW,
576 RTE_FLOW_ITEM_TYPE_RAW,
577 RTE_FLOW_ITEM_TYPE_END,
580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
581 RTE_FLOW_ITEM_TYPE_ETH,
582 RTE_FLOW_ITEM_TYPE_VLAN,
583 RTE_FLOW_ITEM_TYPE_RAW,
584 RTE_FLOW_ITEM_TYPE_RAW,
585 RTE_FLOW_ITEM_TYPE_RAW,
586 RTE_FLOW_ITEM_TYPE_END,
589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
590 RTE_FLOW_ITEM_TYPE_ETH,
591 RTE_FLOW_ITEM_TYPE_VLAN,
592 RTE_FLOW_ITEM_TYPE_IPV4,
593 RTE_FLOW_ITEM_TYPE_RAW,
594 RTE_FLOW_ITEM_TYPE_END,
597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
598 RTE_FLOW_ITEM_TYPE_ETH,
599 RTE_FLOW_ITEM_TYPE_VLAN,
600 RTE_FLOW_ITEM_TYPE_IPV4,
601 RTE_FLOW_ITEM_TYPE_RAW,
602 RTE_FLOW_ITEM_TYPE_RAW,
603 RTE_FLOW_ITEM_TYPE_END,
606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
607 RTE_FLOW_ITEM_TYPE_ETH,
608 RTE_FLOW_ITEM_TYPE_VLAN,
609 RTE_FLOW_ITEM_TYPE_IPV4,
610 RTE_FLOW_ITEM_TYPE_RAW,
611 RTE_FLOW_ITEM_TYPE_RAW,
612 RTE_FLOW_ITEM_TYPE_RAW,
613 RTE_FLOW_ITEM_TYPE_END,
616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
617 RTE_FLOW_ITEM_TYPE_ETH,
618 RTE_FLOW_ITEM_TYPE_VLAN,
619 RTE_FLOW_ITEM_TYPE_IPV4,
620 RTE_FLOW_ITEM_TYPE_UDP,
621 RTE_FLOW_ITEM_TYPE_RAW,
622 RTE_FLOW_ITEM_TYPE_END,
625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
626 RTE_FLOW_ITEM_TYPE_ETH,
627 RTE_FLOW_ITEM_TYPE_VLAN,
628 RTE_FLOW_ITEM_TYPE_IPV4,
629 RTE_FLOW_ITEM_TYPE_UDP,
630 RTE_FLOW_ITEM_TYPE_RAW,
631 RTE_FLOW_ITEM_TYPE_RAW,
632 RTE_FLOW_ITEM_TYPE_END,
635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
636 RTE_FLOW_ITEM_TYPE_ETH,
637 RTE_FLOW_ITEM_TYPE_VLAN,
638 RTE_FLOW_ITEM_TYPE_IPV4,
639 RTE_FLOW_ITEM_TYPE_UDP,
640 RTE_FLOW_ITEM_TYPE_RAW,
641 RTE_FLOW_ITEM_TYPE_RAW,
642 RTE_FLOW_ITEM_TYPE_RAW,
643 RTE_FLOW_ITEM_TYPE_END,
646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
647 RTE_FLOW_ITEM_TYPE_ETH,
648 RTE_FLOW_ITEM_TYPE_VLAN,
649 RTE_FLOW_ITEM_TYPE_IPV4,
650 RTE_FLOW_ITEM_TYPE_TCP,
651 RTE_FLOW_ITEM_TYPE_RAW,
652 RTE_FLOW_ITEM_TYPE_END,
655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
656 RTE_FLOW_ITEM_TYPE_ETH,
657 RTE_FLOW_ITEM_TYPE_VLAN,
658 RTE_FLOW_ITEM_TYPE_IPV4,
659 RTE_FLOW_ITEM_TYPE_TCP,
660 RTE_FLOW_ITEM_TYPE_RAW,
661 RTE_FLOW_ITEM_TYPE_RAW,
662 RTE_FLOW_ITEM_TYPE_END,
665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
666 RTE_FLOW_ITEM_TYPE_ETH,
667 RTE_FLOW_ITEM_TYPE_VLAN,
668 RTE_FLOW_ITEM_TYPE_IPV4,
669 RTE_FLOW_ITEM_TYPE_TCP,
670 RTE_FLOW_ITEM_TYPE_RAW,
671 RTE_FLOW_ITEM_TYPE_RAW,
672 RTE_FLOW_ITEM_TYPE_RAW,
673 RTE_FLOW_ITEM_TYPE_END,
676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
677 RTE_FLOW_ITEM_TYPE_ETH,
678 RTE_FLOW_ITEM_TYPE_VLAN,
679 RTE_FLOW_ITEM_TYPE_IPV4,
680 RTE_FLOW_ITEM_TYPE_SCTP,
681 RTE_FLOW_ITEM_TYPE_RAW,
682 RTE_FLOW_ITEM_TYPE_END,
685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
686 RTE_FLOW_ITEM_TYPE_ETH,
687 RTE_FLOW_ITEM_TYPE_VLAN,
688 RTE_FLOW_ITEM_TYPE_IPV4,
689 RTE_FLOW_ITEM_TYPE_SCTP,
690 RTE_FLOW_ITEM_TYPE_RAW,
691 RTE_FLOW_ITEM_TYPE_RAW,
692 RTE_FLOW_ITEM_TYPE_END,
695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
696 RTE_FLOW_ITEM_TYPE_ETH,
697 RTE_FLOW_ITEM_TYPE_VLAN,
698 RTE_FLOW_ITEM_TYPE_IPV4,
699 RTE_FLOW_ITEM_TYPE_SCTP,
700 RTE_FLOW_ITEM_TYPE_RAW,
701 RTE_FLOW_ITEM_TYPE_RAW,
702 RTE_FLOW_ITEM_TYPE_RAW,
703 RTE_FLOW_ITEM_TYPE_END,
706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
707 RTE_FLOW_ITEM_TYPE_ETH,
708 RTE_FLOW_ITEM_TYPE_VLAN,
709 RTE_FLOW_ITEM_TYPE_IPV6,
710 RTE_FLOW_ITEM_TYPE_RAW,
711 RTE_FLOW_ITEM_TYPE_END,
714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
715 RTE_FLOW_ITEM_TYPE_ETH,
716 RTE_FLOW_ITEM_TYPE_VLAN,
717 RTE_FLOW_ITEM_TYPE_IPV6,
718 RTE_FLOW_ITEM_TYPE_RAW,
719 RTE_FLOW_ITEM_TYPE_RAW,
720 RTE_FLOW_ITEM_TYPE_END,
723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
724 RTE_FLOW_ITEM_TYPE_ETH,
725 RTE_FLOW_ITEM_TYPE_VLAN,
726 RTE_FLOW_ITEM_TYPE_IPV6,
727 RTE_FLOW_ITEM_TYPE_RAW,
728 RTE_FLOW_ITEM_TYPE_RAW,
729 RTE_FLOW_ITEM_TYPE_RAW,
730 RTE_FLOW_ITEM_TYPE_END,
733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
734 RTE_FLOW_ITEM_TYPE_ETH,
735 RTE_FLOW_ITEM_TYPE_VLAN,
736 RTE_FLOW_ITEM_TYPE_IPV6,
737 RTE_FLOW_ITEM_TYPE_UDP,
738 RTE_FLOW_ITEM_TYPE_RAW,
739 RTE_FLOW_ITEM_TYPE_END,
742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
743 RTE_FLOW_ITEM_TYPE_ETH,
744 RTE_FLOW_ITEM_TYPE_VLAN,
745 RTE_FLOW_ITEM_TYPE_IPV6,
746 RTE_FLOW_ITEM_TYPE_UDP,
747 RTE_FLOW_ITEM_TYPE_RAW,
748 RTE_FLOW_ITEM_TYPE_RAW,
749 RTE_FLOW_ITEM_TYPE_END,
752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
753 RTE_FLOW_ITEM_TYPE_ETH,
754 RTE_FLOW_ITEM_TYPE_VLAN,
755 RTE_FLOW_ITEM_TYPE_IPV6,
756 RTE_FLOW_ITEM_TYPE_UDP,
757 RTE_FLOW_ITEM_TYPE_RAW,
758 RTE_FLOW_ITEM_TYPE_RAW,
759 RTE_FLOW_ITEM_TYPE_RAW,
760 RTE_FLOW_ITEM_TYPE_END,
763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
764 RTE_FLOW_ITEM_TYPE_ETH,
765 RTE_FLOW_ITEM_TYPE_VLAN,
766 RTE_FLOW_ITEM_TYPE_IPV6,
767 RTE_FLOW_ITEM_TYPE_TCP,
768 RTE_FLOW_ITEM_TYPE_RAW,
769 RTE_FLOW_ITEM_TYPE_END,
772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
773 RTE_FLOW_ITEM_TYPE_ETH,
774 RTE_FLOW_ITEM_TYPE_VLAN,
775 RTE_FLOW_ITEM_TYPE_IPV6,
776 RTE_FLOW_ITEM_TYPE_TCP,
777 RTE_FLOW_ITEM_TYPE_RAW,
778 RTE_FLOW_ITEM_TYPE_RAW,
779 RTE_FLOW_ITEM_TYPE_END,
782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
783 RTE_FLOW_ITEM_TYPE_ETH,
784 RTE_FLOW_ITEM_TYPE_VLAN,
785 RTE_FLOW_ITEM_TYPE_IPV6,
786 RTE_FLOW_ITEM_TYPE_TCP,
787 RTE_FLOW_ITEM_TYPE_RAW,
788 RTE_FLOW_ITEM_TYPE_RAW,
789 RTE_FLOW_ITEM_TYPE_RAW,
790 RTE_FLOW_ITEM_TYPE_END,
793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
794 RTE_FLOW_ITEM_TYPE_ETH,
795 RTE_FLOW_ITEM_TYPE_VLAN,
796 RTE_FLOW_ITEM_TYPE_IPV6,
797 RTE_FLOW_ITEM_TYPE_SCTP,
798 RTE_FLOW_ITEM_TYPE_RAW,
799 RTE_FLOW_ITEM_TYPE_END,
802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
803 RTE_FLOW_ITEM_TYPE_ETH,
804 RTE_FLOW_ITEM_TYPE_VLAN,
805 RTE_FLOW_ITEM_TYPE_IPV6,
806 RTE_FLOW_ITEM_TYPE_SCTP,
807 RTE_FLOW_ITEM_TYPE_RAW,
808 RTE_FLOW_ITEM_TYPE_RAW,
809 RTE_FLOW_ITEM_TYPE_END,
812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
813 RTE_FLOW_ITEM_TYPE_ETH,
814 RTE_FLOW_ITEM_TYPE_VLAN,
815 RTE_FLOW_ITEM_TYPE_IPV6,
816 RTE_FLOW_ITEM_TYPE_SCTP,
817 RTE_FLOW_ITEM_TYPE_RAW,
818 RTE_FLOW_ITEM_TYPE_RAW,
819 RTE_FLOW_ITEM_TYPE_RAW,
820 RTE_FLOW_ITEM_TYPE_END,
823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
824 RTE_FLOW_ITEM_TYPE_ETH,
825 RTE_FLOW_ITEM_TYPE_IPV4,
826 RTE_FLOW_ITEM_TYPE_VF,
827 RTE_FLOW_ITEM_TYPE_END,
830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
831 RTE_FLOW_ITEM_TYPE_ETH,
832 RTE_FLOW_ITEM_TYPE_IPV4,
833 RTE_FLOW_ITEM_TYPE_UDP,
834 RTE_FLOW_ITEM_TYPE_VF,
835 RTE_FLOW_ITEM_TYPE_END,
838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
839 RTE_FLOW_ITEM_TYPE_ETH,
840 RTE_FLOW_ITEM_TYPE_IPV4,
841 RTE_FLOW_ITEM_TYPE_TCP,
842 RTE_FLOW_ITEM_TYPE_VF,
843 RTE_FLOW_ITEM_TYPE_END,
846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
847 RTE_FLOW_ITEM_TYPE_ETH,
848 RTE_FLOW_ITEM_TYPE_IPV4,
849 RTE_FLOW_ITEM_TYPE_SCTP,
850 RTE_FLOW_ITEM_TYPE_VF,
851 RTE_FLOW_ITEM_TYPE_END,
854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
855 RTE_FLOW_ITEM_TYPE_ETH,
856 RTE_FLOW_ITEM_TYPE_IPV6,
857 RTE_FLOW_ITEM_TYPE_VF,
858 RTE_FLOW_ITEM_TYPE_END,
861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
862 RTE_FLOW_ITEM_TYPE_ETH,
863 RTE_FLOW_ITEM_TYPE_IPV6,
864 RTE_FLOW_ITEM_TYPE_UDP,
865 RTE_FLOW_ITEM_TYPE_VF,
866 RTE_FLOW_ITEM_TYPE_END,
869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
870 RTE_FLOW_ITEM_TYPE_ETH,
871 RTE_FLOW_ITEM_TYPE_IPV6,
872 RTE_FLOW_ITEM_TYPE_TCP,
873 RTE_FLOW_ITEM_TYPE_VF,
874 RTE_FLOW_ITEM_TYPE_END,
877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
878 RTE_FLOW_ITEM_TYPE_ETH,
879 RTE_FLOW_ITEM_TYPE_IPV6,
880 RTE_FLOW_ITEM_TYPE_SCTP,
881 RTE_FLOW_ITEM_TYPE_VF,
882 RTE_FLOW_ITEM_TYPE_END,
885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
886 RTE_FLOW_ITEM_TYPE_ETH,
887 RTE_FLOW_ITEM_TYPE_RAW,
888 RTE_FLOW_ITEM_TYPE_VF,
889 RTE_FLOW_ITEM_TYPE_END,
892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
893 RTE_FLOW_ITEM_TYPE_ETH,
894 RTE_FLOW_ITEM_TYPE_RAW,
895 RTE_FLOW_ITEM_TYPE_RAW,
896 RTE_FLOW_ITEM_TYPE_VF,
897 RTE_FLOW_ITEM_TYPE_END,
900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
901 RTE_FLOW_ITEM_TYPE_ETH,
902 RTE_FLOW_ITEM_TYPE_RAW,
903 RTE_FLOW_ITEM_TYPE_RAW,
904 RTE_FLOW_ITEM_TYPE_RAW,
905 RTE_FLOW_ITEM_TYPE_VF,
906 RTE_FLOW_ITEM_TYPE_END,
909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
910 RTE_FLOW_ITEM_TYPE_ETH,
911 RTE_FLOW_ITEM_TYPE_IPV4,
912 RTE_FLOW_ITEM_TYPE_RAW,
913 RTE_FLOW_ITEM_TYPE_VF,
914 RTE_FLOW_ITEM_TYPE_END,
917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
918 RTE_FLOW_ITEM_TYPE_ETH,
919 RTE_FLOW_ITEM_TYPE_IPV4,
920 RTE_FLOW_ITEM_TYPE_RAW,
921 RTE_FLOW_ITEM_TYPE_RAW,
922 RTE_FLOW_ITEM_TYPE_VF,
923 RTE_FLOW_ITEM_TYPE_END,
926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
927 RTE_FLOW_ITEM_TYPE_ETH,
928 RTE_FLOW_ITEM_TYPE_IPV4,
929 RTE_FLOW_ITEM_TYPE_RAW,
930 RTE_FLOW_ITEM_TYPE_RAW,
931 RTE_FLOW_ITEM_TYPE_RAW,
932 RTE_FLOW_ITEM_TYPE_VF,
933 RTE_FLOW_ITEM_TYPE_END,
936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
937 RTE_FLOW_ITEM_TYPE_ETH,
938 RTE_FLOW_ITEM_TYPE_IPV4,
939 RTE_FLOW_ITEM_TYPE_UDP,
940 RTE_FLOW_ITEM_TYPE_RAW,
941 RTE_FLOW_ITEM_TYPE_VF,
942 RTE_FLOW_ITEM_TYPE_END,
945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
946 RTE_FLOW_ITEM_TYPE_ETH,
947 RTE_FLOW_ITEM_TYPE_IPV4,
948 RTE_FLOW_ITEM_TYPE_UDP,
949 RTE_FLOW_ITEM_TYPE_RAW,
950 RTE_FLOW_ITEM_TYPE_RAW,
951 RTE_FLOW_ITEM_TYPE_VF,
952 RTE_FLOW_ITEM_TYPE_END,
955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
956 RTE_FLOW_ITEM_TYPE_ETH,
957 RTE_FLOW_ITEM_TYPE_IPV4,
958 RTE_FLOW_ITEM_TYPE_UDP,
959 RTE_FLOW_ITEM_TYPE_RAW,
960 RTE_FLOW_ITEM_TYPE_RAW,
961 RTE_FLOW_ITEM_TYPE_RAW,
962 RTE_FLOW_ITEM_TYPE_VF,
963 RTE_FLOW_ITEM_TYPE_END,
966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
967 RTE_FLOW_ITEM_TYPE_ETH,
968 RTE_FLOW_ITEM_TYPE_IPV4,
969 RTE_FLOW_ITEM_TYPE_TCP,
970 RTE_FLOW_ITEM_TYPE_RAW,
971 RTE_FLOW_ITEM_TYPE_VF,
972 RTE_FLOW_ITEM_TYPE_END,
975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
976 RTE_FLOW_ITEM_TYPE_ETH,
977 RTE_FLOW_ITEM_TYPE_IPV4,
978 RTE_FLOW_ITEM_TYPE_TCP,
979 RTE_FLOW_ITEM_TYPE_RAW,
980 RTE_FLOW_ITEM_TYPE_RAW,
981 RTE_FLOW_ITEM_TYPE_VF,
982 RTE_FLOW_ITEM_TYPE_END,
985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
986 RTE_FLOW_ITEM_TYPE_ETH,
987 RTE_FLOW_ITEM_TYPE_IPV4,
988 RTE_FLOW_ITEM_TYPE_TCP,
989 RTE_FLOW_ITEM_TYPE_RAW,
990 RTE_FLOW_ITEM_TYPE_RAW,
991 RTE_FLOW_ITEM_TYPE_RAW,
992 RTE_FLOW_ITEM_TYPE_VF,
993 RTE_FLOW_ITEM_TYPE_END,
996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
997 RTE_FLOW_ITEM_TYPE_ETH,
998 RTE_FLOW_ITEM_TYPE_IPV4,
999 RTE_FLOW_ITEM_TYPE_SCTP,
1000 RTE_FLOW_ITEM_TYPE_RAW,
1001 RTE_FLOW_ITEM_TYPE_VF,
1002 RTE_FLOW_ITEM_TYPE_END,
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006 RTE_FLOW_ITEM_TYPE_ETH,
1007 RTE_FLOW_ITEM_TYPE_IPV4,
1008 RTE_FLOW_ITEM_TYPE_SCTP,
1009 RTE_FLOW_ITEM_TYPE_RAW,
1010 RTE_FLOW_ITEM_TYPE_RAW,
1011 RTE_FLOW_ITEM_TYPE_VF,
1012 RTE_FLOW_ITEM_TYPE_END,
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016 RTE_FLOW_ITEM_TYPE_ETH,
1017 RTE_FLOW_ITEM_TYPE_IPV4,
1018 RTE_FLOW_ITEM_TYPE_SCTP,
1019 RTE_FLOW_ITEM_TYPE_RAW,
1020 RTE_FLOW_ITEM_TYPE_RAW,
1021 RTE_FLOW_ITEM_TYPE_RAW,
1022 RTE_FLOW_ITEM_TYPE_VF,
1023 RTE_FLOW_ITEM_TYPE_END,
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027 RTE_FLOW_ITEM_TYPE_ETH,
1028 RTE_FLOW_ITEM_TYPE_IPV6,
1029 RTE_FLOW_ITEM_TYPE_RAW,
1030 RTE_FLOW_ITEM_TYPE_VF,
1031 RTE_FLOW_ITEM_TYPE_END,
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035 RTE_FLOW_ITEM_TYPE_ETH,
1036 RTE_FLOW_ITEM_TYPE_IPV6,
1037 RTE_FLOW_ITEM_TYPE_RAW,
1038 RTE_FLOW_ITEM_TYPE_RAW,
1039 RTE_FLOW_ITEM_TYPE_VF,
1040 RTE_FLOW_ITEM_TYPE_END,
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044 RTE_FLOW_ITEM_TYPE_ETH,
1045 RTE_FLOW_ITEM_TYPE_IPV6,
1046 RTE_FLOW_ITEM_TYPE_RAW,
1047 RTE_FLOW_ITEM_TYPE_RAW,
1048 RTE_FLOW_ITEM_TYPE_RAW,
1049 RTE_FLOW_ITEM_TYPE_VF,
1050 RTE_FLOW_ITEM_TYPE_END,
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054 RTE_FLOW_ITEM_TYPE_ETH,
1055 RTE_FLOW_ITEM_TYPE_IPV6,
1056 RTE_FLOW_ITEM_TYPE_UDP,
1057 RTE_FLOW_ITEM_TYPE_RAW,
1058 RTE_FLOW_ITEM_TYPE_VF,
1059 RTE_FLOW_ITEM_TYPE_END,
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063 RTE_FLOW_ITEM_TYPE_ETH,
1064 RTE_FLOW_ITEM_TYPE_IPV6,
1065 RTE_FLOW_ITEM_TYPE_UDP,
1066 RTE_FLOW_ITEM_TYPE_RAW,
1067 RTE_FLOW_ITEM_TYPE_RAW,
1068 RTE_FLOW_ITEM_TYPE_VF,
1069 RTE_FLOW_ITEM_TYPE_END,
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073 RTE_FLOW_ITEM_TYPE_ETH,
1074 RTE_FLOW_ITEM_TYPE_IPV6,
1075 RTE_FLOW_ITEM_TYPE_UDP,
1076 RTE_FLOW_ITEM_TYPE_RAW,
1077 RTE_FLOW_ITEM_TYPE_RAW,
1078 RTE_FLOW_ITEM_TYPE_RAW,
1079 RTE_FLOW_ITEM_TYPE_VF,
1080 RTE_FLOW_ITEM_TYPE_END,
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084 RTE_FLOW_ITEM_TYPE_ETH,
1085 RTE_FLOW_ITEM_TYPE_IPV6,
1086 RTE_FLOW_ITEM_TYPE_TCP,
1087 RTE_FLOW_ITEM_TYPE_RAW,
1088 RTE_FLOW_ITEM_TYPE_VF,
1089 RTE_FLOW_ITEM_TYPE_END,
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093 RTE_FLOW_ITEM_TYPE_ETH,
1094 RTE_FLOW_ITEM_TYPE_IPV6,
1095 RTE_FLOW_ITEM_TYPE_TCP,
1096 RTE_FLOW_ITEM_TYPE_RAW,
1097 RTE_FLOW_ITEM_TYPE_RAW,
1098 RTE_FLOW_ITEM_TYPE_VF,
1099 RTE_FLOW_ITEM_TYPE_END,
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103 RTE_FLOW_ITEM_TYPE_ETH,
1104 RTE_FLOW_ITEM_TYPE_IPV6,
1105 RTE_FLOW_ITEM_TYPE_TCP,
1106 RTE_FLOW_ITEM_TYPE_RAW,
1107 RTE_FLOW_ITEM_TYPE_RAW,
1108 RTE_FLOW_ITEM_TYPE_RAW,
1109 RTE_FLOW_ITEM_TYPE_VF,
1110 RTE_FLOW_ITEM_TYPE_END,
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114 RTE_FLOW_ITEM_TYPE_ETH,
1115 RTE_FLOW_ITEM_TYPE_IPV6,
1116 RTE_FLOW_ITEM_TYPE_SCTP,
1117 RTE_FLOW_ITEM_TYPE_RAW,
1118 RTE_FLOW_ITEM_TYPE_VF,
1119 RTE_FLOW_ITEM_TYPE_END,
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123 RTE_FLOW_ITEM_TYPE_ETH,
1124 RTE_FLOW_ITEM_TYPE_IPV6,
1125 RTE_FLOW_ITEM_TYPE_SCTP,
1126 RTE_FLOW_ITEM_TYPE_RAW,
1127 RTE_FLOW_ITEM_TYPE_RAW,
1128 RTE_FLOW_ITEM_TYPE_VF,
1129 RTE_FLOW_ITEM_TYPE_END,
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133 RTE_FLOW_ITEM_TYPE_ETH,
1134 RTE_FLOW_ITEM_TYPE_IPV6,
1135 RTE_FLOW_ITEM_TYPE_SCTP,
1136 RTE_FLOW_ITEM_TYPE_RAW,
1137 RTE_FLOW_ITEM_TYPE_RAW,
1138 RTE_FLOW_ITEM_TYPE_RAW,
1139 RTE_FLOW_ITEM_TYPE_VF,
1140 RTE_FLOW_ITEM_TYPE_END,
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144 RTE_FLOW_ITEM_TYPE_ETH,
1145 RTE_FLOW_ITEM_TYPE_VLAN,
1146 RTE_FLOW_ITEM_TYPE_VF,
1147 RTE_FLOW_ITEM_TYPE_END,
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151 RTE_FLOW_ITEM_TYPE_ETH,
1152 RTE_FLOW_ITEM_TYPE_VLAN,
1153 RTE_FLOW_ITEM_TYPE_IPV4,
1154 RTE_FLOW_ITEM_TYPE_VF,
1155 RTE_FLOW_ITEM_TYPE_END,
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159 RTE_FLOW_ITEM_TYPE_ETH,
1160 RTE_FLOW_ITEM_TYPE_VLAN,
1161 RTE_FLOW_ITEM_TYPE_IPV4,
1162 RTE_FLOW_ITEM_TYPE_UDP,
1163 RTE_FLOW_ITEM_TYPE_VF,
1164 RTE_FLOW_ITEM_TYPE_END,
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168 RTE_FLOW_ITEM_TYPE_ETH,
1169 RTE_FLOW_ITEM_TYPE_VLAN,
1170 RTE_FLOW_ITEM_TYPE_IPV4,
1171 RTE_FLOW_ITEM_TYPE_TCP,
1172 RTE_FLOW_ITEM_TYPE_VF,
1173 RTE_FLOW_ITEM_TYPE_END,
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177 RTE_FLOW_ITEM_TYPE_ETH,
1178 RTE_FLOW_ITEM_TYPE_VLAN,
1179 RTE_FLOW_ITEM_TYPE_IPV4,
1180 RTE_FLOW_ITEM_TYPE_SCTP,
1181 RTE_FLOW_ITEM_TYPE_VF,
1182 RTE_FLOW_ITEM_TYPE_END,
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186 RTE_FLOW_ITEM_TYPE_ETH,
1187 RTE_FLOW_ITEM_TYPE_VLAN,
1188 RTE_FLOW_ITEM_TYPE_IPV6,
1189 RTE_FLOW_ITEM_TYPE_VF,
1190 RTE_FLOW_ITEM_TYPE_END,
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194 RTE_FLOW_ITEM_TYPE_ETH,
1195 RTE_FLOW_ITEM_TYPE_VLAN,
1196 RTE_FLOW_ITEM_TYPE_IPV6,
1197 RTE_FLOW_ITEM_TYPE_UDP,
1198 RTE_FLOW_ITEM_TYPE_VF,
1199 RTE_FLOW_ITEM_TYPE_END,
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203 RTE_FLOW_ITEM_TYPE_ETH,
1204 RTE_FLOW_ITEM_TYPE_VLAN,
1205 RTE_FLOW_ITEM_TYPE_IPV6,
1206 RTE_FLOW_ITEM_TYPE_TCP,
1207 RTE_FLOW_ITEM_TYPE_VF,
1208 RTE_FLOW_ITEM_TYPE_END,
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212 RTE_FLOW_ITEM_TYPE_ETH,
1213 RTE_FLOW_ITEM_TYPE_VLAN,
1214 RTE_FLOW_ITEM_TYPE_IPV6,
1215 RTE_FLOW_ITEM_TYPE_SCTP,
1216 RTE_FLOW_ITEM_TYPE_VF,
1217 RTE_FLOW_ITEM_TYPE_END,
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221 RTE_FLOW_ITEM_TYPE_ETH,
1222 RTE_FLOW_ITEM_TYPE_VLAN,
1223 RTE_FLOW_ITEM_TYPE_RAW,
1224 RTE_FLOW_ITEM_TYPE_VF,
1225 RTE_FLOW_ITEM_TYPE_END,
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229 RTE_FLOW_ITEM_TYPE_ETH,
1230 RTE_FLOW_ITEM_TYPE_VLAN,
1231 RTE_FLOW_ITEM_TYPE_RAW,
1232 RTE_FLOW_ITEM_TYPE_RAW,
1233 RTE_FLOW_ITEM_TYPE_VF,
1234 RTE_FLOW_ITEM_TYPE_END,
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238 RTE_FLOW_ITEM_TYPE_ETH,
1239 RTE_FLOW_ITEM_TYPE_VLAN,
1240 RTE_FLOW_ITEM_TYPE_RAW,
1241 RTE_FLOW_ITEM_TYPE_RAW,
1242 RTE_FLOW_ITEM_TYPE_RAW,
1243 RTE_FLOW_ITEM_TYPE_VF,
1244 RTE_FLOW_ITEM_TYPE_END,
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248 RTE_FLOW_ITEM_TYPE_ETH,
1249 RTE_FLOW_ITEM_TYPE_VLAN,
1250 RTE_FLOW_ITEM_TYPE_IPV4,
1251 RTE_FLOW_ITEM_TYPE_RAW,
1252 RTE_FLOW_ITEM_TYPE_VF,
1253 RTE_FLOW_ITEM_TYPE_END,
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257 RTE_FLOW_ITEM_TYPE_ETH,
1258 RTE_FLOW_ITEM_TYPE_VLAN,
1259 RTE_FLOW_ITEM_TYPE_IPV4,
1260 RTE_FLOW_ITEM_TYPE_RAW,
1261 RTE_FLOW_ITEM_TYPE_RAW,
1262 RTE_FLOW_ITEM_TYPE_VF,
1263 RTE_FLOW_ITEM_TYPE_END,
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267 RTE_FLOW_ITEM_TYPE_ETH,
1268 RTE_FLOW_ITEM_TYPE_VLAN,
1269 RTE_FLOW_ITEM_TYPE_IPV4,
1270 RTE_FLOW_ITEM_TYPE_RAW,
1271 RTE_FLOW_ITEM_TYPE_RAW,
1272 RTE_FLOW_ITEM_TYPE_RAW,
1273 RTE_FLOW_ITEM_TYPE_VF,
1274 RTE_FLOW_ITEM_TYPE_END,
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278 RTE_FLOW_ITEM_TYPE_ETH,
1279 RTE_FLOW_ITEM_TYPE_VLAN,
1280 RTE_FLOW_ITEM_TYPE_IPV4,
1281 RTE_FLOW_ITEM_TYPE_UDP,
1282 RTE_FLOW_ITEM_TYPE_RAW,
1283 RTE_FLOW_ITEM_TYPE_VF,
1284 RTE_FLOW_ITEM_TYPE_END,
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288 RTE_FLOW_ITEM_TYPE_ETH,
1289 RTE_FLOW_ITEM_TYPE_VLAN,
1290 RTE_FLOW_ITEM_TYPE_IPV4,
1291 RTE_FLOW_ITEM_TYPE_UDP,
1292 RTE_FLOW_ITEM_TYPE_RAW,
1293 RTE_FLOW_ITEM_TYPE_RAW,
1294 RTE_FLOW_ITEM_TYPE_VF,
1295 RTE_FLOW_ITEM_TYPE_END,
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299 RTE_FLOW_ITEM_TYPE_ETH,
1300 RTE_FLOW_ITEM_TYPE_VLAN,
1301 RTE_FLOW_ITEM_TYPE_IPV4,
1302 RTE_FLOW_ITEM_TYPE_UDP,
1303 RTE_FLOW_ITEM_TYPE_RAW,
1304 RTE_FLOW_ITEM_TYPE_RAW,
1305 RTE_FLOW_ITEM_TYPE_RAW,
1306 RTE_FLOW_ITEM_TYPE_VF,
1307 RTE_FLOW_ITEM_TYPE_END,
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311 RTE_FLOW_ITEM_TYPE_ETH,
1312 RTE_FLOW_ITEM_TYPE_VLAN,
1313 RTE_FLOW_ITEM_TYPE_IPV4,
1314 RTE_FLOW_ITEM_TYPE_TCP,
1315 RTE_FLOW_ITEM_TYPE_RAW,
1316 RTE_FLOW_ITEM_TYPE_VF,
1317 RTE_FLOW_ITEM_TYPE_END,
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321 RTE_FLOW_ITEM_TYPE_ETH,
1322 RTE_FLOW_ITEM_TYPE_VLAN,
1323 RTE_FLOW_ITEM_TYPE_IPV4,
1324 RTE_FLOW_ITEM_TYPE_TCP,
1325 RTE_FLOW_ITEM_TYPE_RAW,
1326 RTE_FLOW_ITEM_TYPE_RAW,
1327 RTE_FLOW_ITEM_TYPE_VF,
1328 RTE_FLOW_ITEM_TYPE_END,
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332 RTE_FLOW_ITEM_TYPE_ETH,
1333 RTE_FLOW_ITEM_TYPE_VLAN,
1334 RTE_FLOW_ITEM_TYPE_IPV4,
1335 RTE_FLOW_ITEM_TYPE_TCP,
1336 RTE_FLOW_ITEM_TYPE_RAW,
1337 RTE_FLOW_ITEM_TYPE_RAW,
1338 RTE_FLOW_ITEM_TYPE_RAW,
1339 RTE_FLOW_ITEM_TYPE_VF,
1340 RTE_FLOW_ITEM_TYPE_END,
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344 RTE_FLOW_ITEM_TYPE_ETH,
1345 RTE_FLOW_ITEM_TYPE_VLAN,
1346 RTE_FLOW_ITEM_TYPE_IPV4,
1347 RTE_FLOW_ITEM_TYPE_SCTP,
1348 RTE_FLOW_ITEM_TYPE_RAW,
1349 RTE_FLOW_ITEM_TYPE_VF,
1350 RTE_FLOW_ITEM_TYPE_END,
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354 RTE_FLOW_ITEM_TYPE_ETH,
1355 RTE_FLOW_ITEM_TYPE_VLAN,
1356 RTE_FLOW_ITEM_TYPE_IPV4,
1357 RTE_FLOW_ITEM_TYPE_SCTP,
1358 RTE_FLOW_ITEM_TYPE_RAW,
1359 RTE_FLOW_ITEM_TYPE_RAW,
1360 RTE_FLOW_ITEM_TYPE_VF,
1361 RTE_FLOW_ITEM_TYPE_END,
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365 RTE_FLOW_ITEM_TYPE_ETH,
1366 RTE_FLOW_ITEM_TYPE_VLAN,
1367 RTE_FLOW_ITEM_TYPE_IPV4,
1368 RTE_FLOW_ITEM_TYPE_SCTP,
1369 RTE_FLOW_ITEM_TYPE_RAW,
1370 RTE_FLOW_ITEM_TYPE_RAW,
1371 RTE_FLOW_ITEM_TYPE_RAW,
1372 RTE_FLOW_ITEM_TYPE_VF,
1373 RTE_FLOW_ITEM_TYPE_END,
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377 RTE_FLOW_ITEM_TYPE_ETH,
1378 RTE_FLOW_ITEM_TYPE_VLAN,
1379 RTE_FLOW_ITEM_TYPE_IPV6,
1380 RTE_FLOW_ITEM_TYPE_RAW,
1381 RTE_FLOW_ITEM_TYPE_VF,
1382 RTE_FLOW_ITEM_TYPE_END,
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386 RTE_FLOW_ITEM_TYPE_ETH,
1387 RTE_FLOW_ITEM_TYPE_VLAN,
1388 RTE_FLOW_ITEM_TYPE_IPV6,
1389 RTE_FLOW_ITEM_TYPE_RAW,
1390 RTE_FLOW_ITEM_TYPE_RAW,
1391 RTE_FLOW_ITEM_TYPE_VF,
1392 RTE_FLOW_ITEM_TYPE_END,
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396 RTE_FLOW_ITEM_TYPE_ETH,
1397 RTE_FLOW_ITEM_TYPE_VLAN,
1398 RTE_FLOW_ITEM_TYPE_IPV6,
1399 RTE_FLOW_ITEM_TYPE_RAW,
1400 RTE_FLOW_ITEM_TYPE_RAW,
1401 RTE_FLOW_ITEM_TYPE_RAW,
1402 RTE_FLOW_ITEM_TYPE_VF,
1403 RTE_FLOW_ITEM_TYPE_END,
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407 RTE_FLOW_ITEM_TYPE_ETH,
1408 RTE_FLOW_ITEM_TYPE_VLAN,
1409 RTE_FLOW_ITEM_TYPE_IPV6,
1410 RTE_FLOW_ITEM_TYPE_UDP,
1411 RTE_FLOW_ITEM_TYPE_RAW,
1412 RTE_FLOW_ITEM_TYPE_VF,
1413 RTE_FLOW_ITEM_TYPE_END,
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417 RTE_FLOW_ITEM_TYPE_ETH,
1418 RTE_FLOW_ITEM_TYPE_VLAN,
1419 RTE_FLOW_ITEM_TYPE_IPV6,
1420 RTE_FLOW_ITEM_TYPE_UDP,
1421 RTE_FLOW_ITEM_TYPE_RAW,
1422 RTE_FLOW_ITEM_TYPE_RAW,
1423 RTE_FLOW_ITEM_TYPE_VF,
1424 RTE_FLOW_ITEM_TYPE_END,
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428 RTE_FLOW_ITEM_TYPE_ETH,
1429 RTE_FLOW_ITEM_TYPE_VLAN,
1430 RTE_FLOW_ITEM_TYPE_IPV6,
1431 RTE_FLOW_ITEM_TYPE_UDP,
1432 RTE_FLOW_ITEM_TYPE_RAW,
1433 RTE_FLOW_ITEM_TYPE_RAW,
1434 RTE_FLOW_ITEM_TYPE_RAW,
1435 RTE_FLOW_ITEM_TYPE_VF,
1436 RTE_FLOW_ITEM_TYPE_END,
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440 RTE_FLOW_ITEM_TYPE_ETH,
1441 RTE_FLOW_ITEM_TYPE_VLAN,
1442 RTE_FLOW_ITEM_TYPE_IPV6,
1443 RTE_FLOW_ITEM_TYPE_TCP,
1444 RTE_FLOW_ITEM_TYPE_RAW,
1445 RTE_FLOW_ITEM_TYPE_VF,
1446 RTE_FLOW_ITEM_TYPE_END,
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450 RTE_FLOW_ITEM_TYPE_ETH,
1451 RTE_FLOW_ITEM_TYPE_VLAN,
1452 RTE_FLOW_ITEM_TYPE_IPV6,
1453 RTE_FLOW_ITEM_TYPE_TCP,
1454 RTE_FLOW_ITEM_TYPE_RAW,
1455 RTE_FLOW_ITEM_TYPE_RAW,
1456 RTE_FLOW_ITEM_TYPE_VF,
1457 RTE_FLOW_ITEM_TYPE_END,
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461 RTE_FLOW_ITEM_TYPE_ETH,
1462 RTE_FLOW_ITEM_TYPE_VLAN,
1463 RTE_FLOW_ITEM_TYPE_IPV6,
1464 RTE_FLOW_ITEM_TYPE_TCP,
1465 RTE_FLOW_ITEM_TYPE_RAW,
1466 RTE_FLOW_ITEM_TYPE_RAW,
1467 RTE_FLOW_ITEM_TYPE_RAW,
1468 RTE_FLOW_ITEM_TYPE_VF,
1469 RTE_FLOW_ITEM_TYPE_END,
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473 RTE_FLOW_ITEM_TYPE_ETH,
1474 RTE_FLOW_ITEM_TYPE_VLAN,
1475 RTE_FLOW_ITEM_TYPE_IPV6,
1476 RTE_FLOW_ITEM_TYPE_SCTP,
1477 RTE_FLOW_ITEM_TYPE_RAW,
1478 RTE_FLOW_ITEM_TYPE_VF,
1479 RTE_FLOW_ITEM_TYPE_END,
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483 RTE_FLOW_ITEM_TYPE_ETH,
1484 RTE_FLOW_ITEM_TYPE_VLAN,
1485 RTE_FLOW_ITEM_TYPE_IPV6,
1486 RTE_FLOW_ITEM_TYPE_SCTP,
1487 RTE_FLOW_ITEM_TYPE_RAW,
1488 RTE_FLOW_ITEM_TYPE_RAW,
1489 RTE_FLOW_ITEM_TYPE_VF,
1490 RTE_FLOW_ITEM_TYPE_END,
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494 RTE_FLOW_ITEM_TYPE_ETH,
1495 RTE_FLOW_ITEM_TYPE_VLAN,
1496 RTE_FLOW_ITEM_TYPE_IPV6,
1497 RTE_FLOW_ITEM_TYPE_SCTP,
1498 RTE_FLOW_ITEM_TYPE_RAW,
1499 RTE_FLOW_ITEM_TYPE_RAW,
1500 RTE_FLOW_ITEM_TYPE_RAW,
1501 RTE_FLOW_ITEM_TYPE_VF,
1502 RTE_FLOW_ITEM_TYPE_END,
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507 RTE_FLOW_ITEM_TYPE_ETH,
1508 RTE_FLOW_ITEM_TYPE_IPV4,
1509 RTE_FLOW_ITEM_TYPE_UDP,
1510 RTE_FLOW_ITEM_TYPE_VXLAN,
1511 RTE_FLOW_ITEM_TYPE_ETH,
1512 RTE_FLOW_ITEM_TYPE_END,
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516 RTE_FLOW_ITEM_TYPE_ETH,
1517 RTE_FLOW_ITEM_TYPE_IPV6,
1518 RTE_FLOW_ITEM_TYPE_UDP,
1519 RTE_FLOW_ITEM_TYPE_VXLAN,
1520 RTE_FLOW_ITEM_TYPE_ETH,
1521 RTE_FLOW_ITEM_TYPE_END,
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525 RTE_FLOW_ITEM_TYPE_ETH,
1526 RTE_FLOW_ITEM_TYPE_IPV4,
1527 RTE_FLOW_ITEM_TYPE_UDP,
1528 RTE_FLOW_ITEM_TYPE_VXLAN,
1529 RTE_FLOW_ITEM_TYPE_ETH,
1530 RTE_FLOW_ITEM_TYPE_VLAN,
1531 RTE_FLOW_ITEM_TYPE_END,
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535 RTE_FLOW_ITEM_TYPE_ETH,
1536 RTE_FLOW_ITEM_TYPE_IPV6,
1537 RTE_FLOW_ITEM_TYPE_UDP,
1538 RTE_FLOW_ITEM_TYPE_VXLAN,
1539 RTE_FLOW_ITEM_TYPE_ETH,
1540 RTE_FLOW_ITEM_TYPE_VLAN,
1541 RTE_FLOW_ITEM_TYPE_END,
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545 RTE_FLOW_ITEM_TYPE_ETH,
1546 RTE_FLOW_ITEM_TYPE_IPV4,
1547 RTE_FLOW_ITEM_TYPE_NVGRE,
1548 RTE_FLOW_ITEM_TYPE_ETH,
1549 RTE_FLOW_ITEM_TYPE_END,
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553 RTE_FLOW_ITEM_TYPE_ETH,
1554 RTE_FLOW_ITEM_TYPE_IPV6,
1555 RTE_FLOW_ITEM_TYPE_NVGRE,
1556 RTE_FLOW_ITEM_TYPE_ETH,
1557 RTE_FLOW_ITEM_TYPE_END,
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561 RTE_FLOW_ITEM_TYPE_ETH,
1562 RTE_FLOW_ITEM_TYPE_IPV4,
1563 RTE_FLOW_ITEM_TYPE_NVGRE,
1564 RTE_FLOW_ITEM_TYPE_ETH,
1565 RTE_FLOW_ITEM_TYPE_VLAN,
1566 RTE_FLOW_ITEM_TYPE_END,
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570 RTE_FLOW_ITEM_TYPE_ETH,
1571 RTE_FLOW_ITEM_TYPE_IPV6,
1572 RTE_FLOW_ITEM_TYPE_NVGRE,
1573 RTE_FLOW_ITEM_TYPE_ETH,
1574 RTE_FLOW_ITEM_TYPE_VLAN,
1575 RTE_FLOW_ITEM_TYPE_END,
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579 RTE_FLOW_ITEM_TYPE_ETH,
1580 RTE_FLOW_ITEM_TYPE_IPV4,
1581 RTE_FLOW_ITEM_TYPE_UDP,
1582 RTE_FLOW_ITEM_TYPE_MPLS,
1583 RTE_FLOW_ITEM_TYPE_END,
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587 RTE_FLOW_ITEM_TYPE_ETH,
1588 RTE_FLOW_ITEM_TYPE_IPV6,
1589 RTE_FLOW_ITEM_TYPE_UDP,
1590 RTE_FLOW_ITEM_TYPE_MPLS,
1591 RTE_FLOW_ITEM_TYPE_END,
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595 RTE_FLOW_ITEM_TYPE_ETH,
1596 RTE_FLOW_ITEM_TYPE_IPV4,
1597 RTE_FLOW_ITEM_TYPE_GRE,
1598 RTE_FLOW_ITEM_TYPE_MPLS,
1599 RTE_FLOW_ITEM_TYPE_END,
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603 RTE_FLOW_ITEM_TYPE_ETH,
1604 RTE_FLOW_ITEM_TYPE_IPV6,
1605 RTE_FLOW_ITEM_TYPE_GRE,
1606 RTE_FLOW_ITEM_TYPE_MPLS,
1607 RTE_FLOW_ITEM_TYPE_END,
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611 RTE_FLOW_ITEM_TYPE_ETH,
1612 RTE_FLOW_ITEM_TYPE_VLAN,
1613 RTE_FLOW_ITEM_TYPE_VLAN,
1614 RTE_FLOW_ITEM_TYPE_END,
1617 static enum rte_flow_item_type pattern_fdir_ipv4_l2tpv3oip[] = {
1618 RTE_FLOW_ITEM_TYPE_ETH,
1619 RTE_FLOW_ITEM_TYPE_IPV4,
1620 RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1621 RTE_FLOW_ITEM_TYPE_END,
1624 static enum rte_flow_item_type pattern_fdir_ipv6_l2tpv3oip[] = {
1625 RTE_FLOW_ITEM_TYPE_ETH,
1626 RTE_FLOW_ITEM_TYPE_IPV6,
1627 RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1628 RTE_FLOW_ITEM_TYPE_END,
1631 static enum rte_flow_item_type pattern_fdir_ipv4_esp[] = {
1632 RTE_FLOW_ITEM_TYPE_ETH,
1633 RTE_FLOW_ITEM_TYPE_IPV4,
1634 RTE_FLOW_ITEM_TYPE_ESP,
1635 RTE_FLOW_ITEM_TYPE_END,
1638 static enum rte_flow_item_type pattern_fdir_ipv6_esp[] = {
1639 RTE_FLOW_ITEM_TYPE_ETH,
1640 RTE_FLOW_ITEM_TYPE_IPV6,
1641 RTE_FLOW_ITEM_TYPE_ESP,
1642 RTE_FLOW_ITEM_TYPE_END,
1645 static enum rte_flow_item_type pattern_fdir_ipv4_udp_esp[] = {
1646 RTE_FLOW_ITEM_TYPE_ETH,
1647 RTE_FLOW_ITEM_TYPE_IPV4,
1648 RTE_FLOW_ITEM_TYPE_UDP,
1649 RTE_FLOW_ITEM_TYPE_ESP,
1650 RTE_FLOW_ITEM_TYPE_END,
1653 static enum rte_flow_item_type pattern_fdir_ipv6_udp_esp[] = {
1654 RTE_FLOW_ITEM_TYPE_ETH,
1655 RTE_FLOW_ITEM_TYPE_IPV6,
1656 RTE_FLOW_ITEM_TYPE_UDP,
1657 RTE_FLOW_ITEM_TYPE_ESP,
1658 RTE_FLOW_ITEM_TYPE_END,
1661 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1663 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1664 /* FDIR - support default flow type without flexible payload*/
1665 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1666 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1667 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1668 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1669 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_ipv4_esp, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_ipv4_udp_esp, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_ipv6_esp, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_ipv6_udp_esp, i40e_flow_parse_fdir_filter },
1686 /* FDIR - support default flow type with flexible payload */
1687 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1703 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1704 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1705 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1714 /* FDIR - support single vlan input set */
1715 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1729 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1730 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1731 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1732 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1751 /* FDIR - support VF item */
1752 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1775 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1776 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1777 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1778 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1779 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1780 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1781 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1782 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1783 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1784 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1785 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1786 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1787 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1788 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1789 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1790 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1791 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1792 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1793 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1794 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1795 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1796 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1797 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1798 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1799 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1800 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1801 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1802 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1803 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1804 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1805 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1806 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1807 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1808 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1809 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1810 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1811 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1812 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1813 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1814 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1815 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1816 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1817 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1818 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1819 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1820 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1821 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1822 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1824 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1825 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1826 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1827 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1829 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1830 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1831 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1832 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1833 /* MPLSoUDP & MPLSoGRE */
1834 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1835 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1836 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1837 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1839 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1840 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1841 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1842 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1844 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1845 /* L2TPv3 over IP */
1846 { pattern_fdir_ipv4_l2tpv3oip, i40e_flow_parse_fdir_filter },
1847 { pattern_fdir_ipv6_l2tpv3oip, i40e_flow_parse_fdir_filter },
1850 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1852 act = actions + index; \
1853 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1855 act = actions + index; \
1859 /* Find the first VOID or non-VOID item pointer */
1860 static const struct rte_flow_item *
1861 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1865 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1867 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1869 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1877 /* Skip all VOID items of the pattern */
1879 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1880 const struct rte_flow_item *pattern)
1882 uint32_t cpy_count = 0;
1883 const struct rte_flow_item *pb = pattern, *pe = pattern;
1886 /* Find a non-void item first */
1887 pb = i40e_find_first_item(pb, false);
1888 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1893 /* Find a void item */
1894 pe = i40e_find_first_item(pb + 1, true);
1896 cpy_count = pe - pb;
1897 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1901 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1908 /* Copy the END item. */
1909 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1912 /* Check if the pattern matches a supported item type array */
1914 i40e_match_pattern(enum rte_flow_item_type *item_array,
1915 struct rte_flow_item *pattern)
1917 struct rte_flow_item *item = pattern;
1919 while ((*item_array == item->type) &&
1920 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1925 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1926 item->type == RTE_FLOW_ITEM_TYPE_END);
1929 /* Find if there's parse filter function matched */
1930 static parse_filter_t
1931 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1933 parse_filter_t parse_filter = NULL;
1936 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1937 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1939 parse_filter = i40e_supported_patterns[i].parse_filter;
1946 return parse_filter;
1949 /* Parse attributes */
1951 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1952 struct rte_flow_error *error)
1954 /* Must be input direction */
1955 if (!attr->ingress) {
1956 rte_flow_error_set(error, EINVAL,
1957 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1958 attr, "Only support ingress.");
1964 rte_flow_error_set(error, EINVAL,
1965 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1966 attr, "Not support egress.");
1971 if (attr->priority) {
1972 rte_flow_error_set(error, EINVAL,
1973 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1974 attr, "Not support priority.");
1980 rte_flow_error_set(error, EINVAL,
1981 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1982 attr, "Not support group.");
1990 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1992 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 int qinq = dev->data->dev_conf.rxmode.offloads &
1994 DEV_RX_OFFLOAD_VLAN_EXTEND;
2004 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2007 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
2012 /* 1. Last in item should be NULL as range is not supported.
2013 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
2014 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
2015 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
2017 * 5. Ether_type mask should be 0xFFFF.
2020 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
2021 const struct rte_flow_item *pattern,
2022 struct rte_flow_error *error,
2023 struct rte_eth_ethertype_filter *filter)
2025 const struct rte_flow_item *item = pattern;
2026 const struct rte_flow_item_eth *eth_spec;
2027 const struct rte_flow_item_eth *eth_mask;
2028 enum rte_flow_item_type item_type;
2029 uint16_t outer_tpid;
2031 outer_tpid = i40e_get_outer_vlan(dev);
2033 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2035 rte_flow_error_set(error, EINVAL,
2036 RTE_FLOW_ERROR_TYPE_ITEM,
2038 "Not support range");
2041 item_type = item->type;
2042 switch (item_type) {
2043 case RTE_FLOW_ITEM_TYPE_ETH:
2044 eth_spec = item->spec;
2045 eth_mask = item->mask;
2046 /* Get the MAC info. */
2047 if (!eth_spec || !eth_mask) {
2048 rte_flow_error_set(error, EINVAL,
2049 RTE_FLOW_ERROR_TYPE_ITEM,
2051 "NULL ETH spec/mask");
2055 /* Mask bits of source MAC address must be full of 0.
2056 * Mask bits of destination MAC address must be full
2057 * of 1 or full of 0.
2059 if (!rte_is_zero_ether_addr(ð_mask->src) ||
2060 (!rte_is_zero_ether_addr(ð_mask->dst) &&
2061 !rte_is_broadcast_ether_addr(ð_mask->dst))) {
2062 rte_flow_error_set(error, EINVAL,
2063 RTE_FLOW_ERROR_TYPE_ITEM,
2065 "Invalid MAC_addr mask");
2069 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2070 rte_flow_error_set(error, EINVAL,
2071 RTE_FLOW_ERROR_TYPE_ITEM,
2073 "Invalid ethertype mask");
2077 /* If mask bits of destination MAC address
2078 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2080 if (rte_is_broadcast_ether_addr(ð_mask->dst)) {
2081 filter->mac_addr = eth_spec->dst;
2082 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2084 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2086 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2088 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2089 filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2090 filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2091 filter->ether_type == outer_tpid) {
2092 rte_flow_error_set(error, EINVAL,
2093 RTE_FLOW_ERROR_TYPE_ITEM,
2095 "Unsupported ether_type in"
2096 " control packet filter.");
2108 /* Ethertype action only supports QUEUE or DROP. */
2110 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2111 const struct rte_flow_action *actions,
2112 struct rte_flow_error *error,
2113 struct rte_eth_ethertype_filter *filter)
2115 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116 const struct rte_flow_action *act;
2117 const struct rte_flow_action_queue *act_q;
2120 /* Check if the first non-void action is QUEUE or DROP. */
2121 NEXT_ITEM_OF_ACTION(act, actions, index);
2122 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2123 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2124 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2125 act, "Not supported action.");
2129 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2131 filter->queue = act_q->index;
2132 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2133 rte_flow_error_set(error, EINVAL,
2134 RTE_FLOW_ERROR_TYPE_ACTION,
2135 act, "Invalid queue ID for"
2136 " ethertype_filter.");
2140 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2143 /* Check if the next non-void item is END */
2145 NEXT_ITEM_OF_ACTION(act, actions, index);
2146 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2147 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2148 act, "Not supported action.");
2156 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2157 const struct rte_flow_attr *attr,
2158 const struct rte_flow_item pattern[],
2159 const struct rte_flow_action actions[],
2160 struct rte_flow_error *error,
2161 union i40e_filter_t *filter)
2163 struct rte_eth_ethertype_filter *ethertype_filter =
2164 &filter->ethertype_filter;
2167 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2172 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2177 ret = i40e_flow_parse_attr(attr, error);
2181 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2187 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2188 const struct rte_flow_item_raw *raw_spec,
2189 struct rte_flow_error *error)
2191 if (!raw_spec->relative) {
2192 rte_flow_error_set(error, EINVAL,
2193 RTE_FLOW_ERROR_TYPE_ITEM,
2195 "Relative should be 1.");
2199 if (raw_spec->offset % sizeof(uint16_t)) {
2200 rte_flow_error_set(error, EINVAL,
2201 RTE_FLOW_ERROR_TYPE_ITEM,
2203 "Offset should be even.");
2207 if (raw_spec->search || raw_spec->limit) {
2208 rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ITEM,
2211 "search or limit is not supported.");
2215 if (raw_spec->offset < 0) {
2216 rte_flow_error_set(error, EINVAL,
2217 RTE_FLOW_ERROR_TYPE_ITEM,
2219 "Offset should be non-negative.");
2226 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2227 struct i40e_fdir_flex_pit *flex_pit,
2228 enum i40e_flxpld_layer_idx layer_idx,
2233 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2234 /* Check if the configuration is conflicted */
2235 if (pf->fdir.flex_pit_flag[layer_idx] &&
2236 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2237 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2238 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2241 /* Check if the configuration exists. */
2242 if (pf->fdir.flex_pit_flag[layer_idx] &&
2243 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2244 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2245 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2248 pf->fdir.flex_set[field_idx].src_offset =
2249 flex_pit->src_offset;
2250 pf->fdir.flex_set[field_idx].size =
2252 pf->fdir.flex_set[field_idx].dst_offset =
2253 flex_pit->dst_offset;
2259 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2260 enum i40e_filter_pctype pctype,
2263 struct i40e_fdir_flex_mask flex_mask;
2265 uint8_t i, nb_bitmask = 0;
2267 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2268 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2269 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2271 flex_mask.word_mask |=
2272 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2273 if (mask_tmp != UINT16_MAX) {
2274 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2275 flex_mask.bitmask[nb_bitmask].offset =
2276 i / sizeof(uint16_t);
2278 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2283 flex_mask.nb_bitmask = nb_bitmask;
2285 if (pf->fdir.flex_mask_flag[pctype] &&
2286 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2287 sizeof(struct i40e_fdir_flex_mask))))
2289 else if (pf->fdir.flex_mask_flag[pctype] &&
2290 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2291 sizeof(struct i40e_fdir_flex_mask))))
2294 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2295 sizeof(struct i40e_fdir_flex_mask));
2300 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2301 enum i40e_flxpld_layer_idx layer_idx,
2304 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2305 uint32_t flx_pit, flx_ort;
2307 uint16_t min_next_off = 0; /* in words */
2311 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2312 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2313 (layer_idx * I40E_MAX_FLXPLD_FIED);
2314 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2318 for (i = 0; i < raw_id; i++) {
2319 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2320 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2321 pf->fdir.flex_set[field_idx].size,
2322 pf->fdir.flex_set[field_idx].dst_offset);
2324 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2325 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2326 pf->fdir.flex_set[field_idx].size;
2329 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2330 /* set the non-used register obeying register's constrain */
2331 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2332 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2333 NONUSE_FLX_PIT_DEST_OFF);
2334 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2338 pf->fdir.flex_pit_flag[layer_idx] = 1;
2342 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2343 enum i40e_filter_pctype pctype)
2345 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2346 struct i40e_fdir_flex_mask *flex_mask;
2347 uint32_t flxinset, fd_mask;
2351 flex_mask = &pf->fdir.flex_mask[pctype];
2352 flxinset = (flex_mask->word_mask <<
2353 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2354 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2355 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2357 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2358 fd_mask = (flex_mask->bitmask[i].mask <<
2359 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2360 I40E_PRTQF_FD_MSK_MASK_MASK;
2361 fd_mask |= ((flex_mask->bitmask[i].offset +
2362 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2363 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2364 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2365 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2368 pf->fdir.flex_mask_flag[pctype] = 1;
2372 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2373 enum i40e_filter_pctype pctype,
2376 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2377 uint64_t inset_reg = 0;
2378 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2381 /* Check if the input set is valid */
2382 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2384 PMD_DRV_LOG(ERR, "Invalid input set");
2388 /* Check if the configuration is conflicted */
2389 if (pf->fdir.inset_flag[pctype] &&
2390 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2393 if (pf->fdir.inset_flag[pctype] &&
2394 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2397 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2398 I40E_INSET_MASK_NUM_REG);
2402 if (pf->support_multi_driver) {
2403 for (i = 0; i < num; i++)
2404 if (i40e_read_rx_ctl(hw,
2405 I40E_GLQF_FD_MSK(i, pctype)) !=
2407 PMD_DRV_LOG(ERR, "Input set setting is not"
2409 " `support-multi-driver`"
2413 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2414 if (i40e_read_rx_ctl(hw,
2415 I40E_GLQF_FD_MSK(i, pctype)) != 0) {
2416 PMD_DRV_LOG(ERR, "Input set setting is not"
2418 " `support-multi-driver`"
2424 for (i = 0; i < num; i++)
2425 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2427 /*clear unused mask registers of the pctype */
2428 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2429 i40e_check_write_reg(hw,
2430 I40E_GLQF_FD_MSK(i, pctype), 0);
2433 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2435 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2436 (uint32_t)(inset_reg & UINT32_MAX));
2437 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2438 (uint32_t)((inset_reg >>
2439 I40E_32_BIT_WIDTH) & UINT32_MAX));
2441 I40E_WRITE_FLUSH(hw);
2443 pf->fdir.input_set[pctype] = input_set;
2444 pf->fdir.inset_flag[pctype] = 1;
2449 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2450 enum rte_flow_item_type item_type,
2451 struct i40e_fdir_filter_conf *filter)
2453 struct i40e_customized_pctype *cus_pctype = NULL;
2455 switch (item_type) {
2456 case RTE_FLOW_ITEM_TYPE_GTPC:
2457 cus_pctype = i40e_find_customized_pctype(pf,
2458 I40E_CUSTOMIZED_GTPC);
2460 case RTE_FLOW_ITEM_TYPE_GTPU:
2461 if (!filter->input.flow_ext.inner_ip)
2462 cus_pctype = i40e_find_customized_pctype(pf,
2463 I40E_CUSTOMIZED_GTPU);
2464 else if (filter->input.flow_ext.iip_type ==
2465 I40E_FDIR_IPTYPE_IPV4)
2466 cus_pctype = i40e_find_customized_pctype(pf,
2467 I40E_CUSTOMIZED_GTPU_IPV4);
2468 else if (filter->input.flow_ext.iip_type ==
2469 I40E_FDIR_IPTYPE_IPV6)
2470 cus_pctype = i40e_find_customized_pctype(pf,
2471 I40E_CUSTOMIZED_GTPU_IPV6);
2473 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
2474 if (filter->input.flow_ext.oip_type == I40E_FDIR_IPTYPE_IPV4)
2475 cus_pctype = i40e_find_customized_pctype(pf,
2476 I40E_CUSTOMIZED_IPV4_L2TPV3);
2477 else if (filter->input.flow_ext.oip_type ==
2478 I40E_FDIR_IPTYPE_IPV6)
2479 cus_pctype = i40e_find_customized_pctype(pf,
2480 I40E_CUSTOMIZED_IPV6_L2TPV3);
2482 case RTE_FLOW_ITEM_TYPE_ESP:
2483 if (!filter->input.flow_ext.is_udp) {
2484 if (filter->input.flow_ext.oip_type ==
2485 I40E_FDIR_IPTYPE_IPV4)
2486 cus_pctype = i40e_find_customized_pctype(pf,
2487 I40E_CUSTOMIZED_ESP_IPV4);
2488 else if (filter->input.flow_ext.oip_type ==
2489 I40E_FDIR_IPTYPE_IPV6)
2490 cus_pctype = i40e_find_customized_pctype(pf,
2491 I40E_CUSTOMIZED_ESP_IPV6);
2493 if (filter->input.flow_ext.oip_type ==
2494 I40E_FDIR_IPTYPE_IPV4)
2495 cus_pctype = i40e_find_customized_pctype(pf,
2496 I40E_CUSTOMIZED_ESP_IPV4_UDP);
2497 else if (filter->input.flow_ext.oip_type ==
2498 I40E_FDIR_IPTYPE_IPV6)
2499 cus_pctype = i40e_find_customized_pctype(pf,
2500 I40E_CUSTOMIZED_ESP_IPV6_UDP);
2501 filter->input.flow_ext.is_udp = false;
2505 PMD_DRV_LOG(ERR, "Unsupported item type");
2509 if (cus_pctype && cus_pctype->valid)
2510 return cus_pctype->pctype;
2512 return I40E_FILTER_PCTYPE_INVALID;
2516 i40e_flow_set_filter_spi(struct i40e_fdir_filter_conf *filter,
2517 const struct rte_flow_item_esp *esp_spec)
2519 if (filter->input.flow_ext.oip_type ==
2520 I40E_FDIR_IPTYPE_IPV4) {
2521 if (filter->input.flow_ext.is_udp)
2522 filter->input.flow.esp_ipv4_udp_flow.spi =
2525 filter->input.flow.esp_ipv4_flow.spi =
2528 if (filter->input.flow_ext.oip_type ==
2529 I40E_FDIR_IPTYPE_IPV6) {
2530 if (filter->input.flow_ext.is_udp)
2531 filter->input.flow.esp_ipv6_udp_flow.spi =
2534 filter->input.flow.esp_ipv6_flow.spi =
2539 /* 1. Last in item should be NULL as range is not supported.
2540 * 2. Supported patterns: refer to array i40e_supported_patterns.
2541 * 3. Default supported flow type and input set: refer to array
2542 * valid_fdir_inset_table in i40e_ethdev.c.
2543 * 4. Mask of fields which need to be matched should be
2545 * 5. Mask of fields which needn't to be matched should be
2547 * 6. GTP profile supports GTPv1 only.
2548 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2551 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2552 const struct rte_flow_attr *attr,
2553 const struct rte_flow_item *pattern,
2554 struct rte_flow_error *error,
2555 struct i40e_fdir_filter_conf *filter)
2557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2558 const struct rte_flow_item *item = pattern;
2559 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2560 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2561 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2562 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2563 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2564 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2565 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2566 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2567 const struct rte_flow_item_esp *esp_spec, *esp_mask;
2568 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2569 const struct rte_flow_item_vf *vf_spec;
2570 const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
2573 uint64_t input_set = I40E_INSET_NONE;
2575 enum rte_flow_item_type item_type;
2576 enum rte_flow_item_type next_type;
2577 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2578 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2580 uint8_t ipv6_addr_mask[16] = {
2581 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2582 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2583 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2585 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2586 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2587 struct i40e_fdir_flex_pit flex_pit;
2588 uint8_t next_dst_off = 0;
2589 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2591 bool cfg_flex_pit = true;
2592 bool cfg_flex_msk = true;
2593 uint16_t outer_tpid;
2594 uint16_t ether_type;
2595 uint32_t vtc_flow_cpu;
2596 bool outer_ip = true;
2599 memset(off_arr, 0, sizeof(off_arr));
2600 memset(len_arr, 0, sizeof(len_arr));
2601 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2602 outer_tpid = i40e_get_outer_vlan(dev);
2603 filter->input.flow_ext.customized_pctype = false;
2604 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2606 rte_flow_error_set(error, EINVAL,
2607 RTE_FLOW_ERROR_TYPE_ITEM,
2609 "Not support range");
2612 item_type = item->type;
2613 switch (item_type) {
2614 case RTE_FLOW_ITEM_TYPE_ETH:
2615 eth_spec = item->spec;
2616 eth_mask = item->mask;
2617 next_type = (item + 1)->type;
2619 if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2620 (!eth_spec || !eth_mask)) {
2621 rte_flow_error_set(error, EINVAL,
2622 RTE_FLOW_ERROR_TYPE_ITEM,
2624 "NULL eth spec/mask.");
2628 if (eth_spec && eth_mask) {
2629 if (rte_is_broadcast_ether_addr(ð_mask->dst) &&
2630 rte_is_zero_ether_addr(ð_mask->src)) {
2631 filter->input.flow.l2_flow.dst =
2633 input_set |= I40E_INSET_DMAC;
2634 } else if (rte_is_zero_ether_addr(ð_mask->dst) &&
2635 rte_is_broadcast_ether_addr(ð_mask->src)) {
2636 filter->input.flow.l2_flow.src =
2638 input_set |= I40E_INSET_SMAC;
2639 } else if (rte_is_broadcast_ether_addr(ð_mask->dst) &&
2640 rte_is_broadcast_ether_addr(ð_mask->src)) {
2641 filter->input.flow.l2_flow.dst =
2643 filter->input.flow.l2_flow.src =
2645 input_set |= (I40E_INSET_DMAC | I40E_INSET_SMAC);
2647 rte_flow_error_set(error, EINVAL,
2648 RTE_FLOW_ERROR_TYPE_ITEM,
2650 "Invalid MAC_addr mask.");
2654 if (eth_spec && eth_mask &&
2655 next_type == RTE_FLOW_ITEM_TYPE_END) {
2656 if (eth_mask->type != RTE_BE16(0xffff)) {
2657 rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ITEM,
2660 "Invalid type mask.");
2664 ether_type = rte_be_to_cpu_16(eth_spec->type);
2666 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2667 ether_type == RTE_ETHER_TYPE_IPV4 ||
2668 ether_type == RTE_ETHER_TYPE_IPV6 ||
2669 ether_type == RTE_ETHER_TYPE_ARP ||
2670 ether_type == outer_tpid) {
2671 rte_flow_error_set(error, EINVAL,
2672 RTE_FLOW_ERROR_TYPE_ITEM,
2674 "Unsupported ether_type.");
2677 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2678 filter->input.flow.l2_flow.ether_type =
2682 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2683 layer_idx = I40E_FLXPLD_L2_IDX;
2686 case RTE_FLOW_ITEM_TYPE_VLAN:
2687 vlan_spec = item->spec;
2688 vlan_mask = item->mask;
2690 RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2691 if (vlan_spec && vlan_mask) {
2692 if (vlan_mask->tci ==
2693 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2694 input_set |= I40E_INSET_VLAN_INNER;
2695 filter->input.flow_ext.vlan_tci =
2699 if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2700 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2701 rte_flow_error_set(error, EINVAL,
2702 RTE_FLOW_ERROR_TYPE_ITEM,
2704 "Invalid inner_type"
2710 rte_be_to_cpu_16(vlan_spec->inner_type);
2712 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2713 ether_type == RTE_ETHER_TYPE_IPV6 ||
2714 ether_type == RTE_ETHER_TYPE_ARP ||
2715 ether_type == outer_tpid) {
2716 rte_flow_error_set(error, EINVAL,
2717 RTE_FLOW_ERROR_TYPE_ITEM,
2719 "Unsupported inner_type.");
2722 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2723 filter->input.flow.l2_flow.ether_type =
2724 vlan_spec->inner_type;
2727 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2728 layer_idx = I40E_FLXPLD_L2_IDX;
2731 case RTE_FLOW_ITEM_TYPE_IPV4:
2732 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2733 ipv4_spec = item->spec;
2734 ipv4_mask = item->mask;
2735 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2736 layer_idx = I40E_FLXPLD_L3_IDX;
2738 if (ipv4_spec && ipv4_mask && outer_ip) {
2739 /* Check IPv4 mask and update input set */
2740 if (ipv4_mask->hdr.version_ihl ||
2741 ipv4_mask->hdr.total_length ||
2742 ipv4_mask->hdr.packet_id ||
2743 ipv4_mask->hdr.fragment_offset ||
2744 ipv4_mask->hdr.hdr_checksum) {
2745 rte_flow_error_set(error, EINVAL,
2746 RTE_FLOW_ERROR_TYPE_ITEM,
2748 "Invalid IPv4 mask.");
2752 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2753 input_set |= I40E_INSET_IPV4_SRC;
2754 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2755 input_set |= I40E_INSET_IPV4_DST;
2756 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2757 input_set |= I40E_INSET_IPV4_TOS;
2758 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2759 input_set |= I40E_INSET_IPV4_TTL;
2760 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2761 input_set |= I40E_INSET_IPV4_PROTO;
2763 /* Check if it is fragment. */
2764 frag_off = ipv4_spec->hdr.fragment_offset;
2765 frag_off = rte_be_to_cpu_16(frag_off);
2766 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2767 frag_off & RTE_IPV4_HDR_MF_FLAG)
2768 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2770 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2771 if (input_set & (I40E_INSET_IPV4_SRC |
2772 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
2773 I40E_INSET_IPV4_TTL | I40E_INSET_IPV4_PROTO)) {
2774 rte_flow_error_set(error, EINVAL,
2775 RTE_FLOW_ERROR_TYPE_ITEM,
2777 "L2 and L3 input set are exclusive.");
2781 /* Get the filter info */
2782 filter->input.flow.ip4_flow.proto =
2783 ipv4_spec->hdr.next_proto_id;
2784 filter->input.flow.ip4_flow.tos =
2785 ipv4_spec->hdr.type_of_service;
2786 filter->input.flow.ip4_flow.ttl =
2787 ipv4_spec->hdr.time_to_live;
2788 filter->input.flow.ip4_flow.src_ip =
2789 ipv4_spec->hdr.src_addr;
2790 filter->input.flow.ip4_flow.dst_ip =
2791 ipv4_spec->hdr.dst_addr;
2793 filter->input.flow_ext.inner_ip = false;
2794 filter->input.flow_ext.oip_type =
2795 I40E_FDIR_IPTYPE_IPV4;
2797 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2798 filter->input.flow_ext.inner_ip = true;
2799 filter->input.flow_ext.iip_type =
2800 I40E_FDIR_IPTYPE_IPV4;
2801 } else if (!ipv4_spec && !ipv4_mask && outer_ip) {
2802 filter->input.flow_ext.inner_ip = false;
2803 filter->input.flow_ext.oip_type =
2804 I40E_FDIR_IPTYPE_IPV4;
2805 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2806 rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ITEM,
2809 "Invalid inner IPv4 mask.");
2817 case RTE_FLOW_ITEM_TYPE_IPV6:
2818 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2819 ipv6_spec = item->spec;
2820 ipv6_mask = item->mask;
2821 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2822 layer_idx = I40E_FLXPLD_L3_IDX;
2824 if (ipv6_spec && ipv6_mask && outer_ip) {
2825 /* Check IPv6 mask and update input set */
2826 if (ipv6_mask->hdr.payload_len) {
2827 rte_flow_error_set(error, EINVAL,
2828 RTE_FLOW_ERROR_TYPE_ITEM,
2830 "Invalid IPv6 mask");
2834 if (!memcmp(ipv6_mask->hdr.src_addr,
2836 RTE_DIM(ipv6_mask->hdr.src_addr)))
2837 input_set |= I40E_INSET_IPV6_SRC;
2838 if (!memcmp(ipv6_mask->hdr.dst_addr,
2840 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2841 input_set |= I40E_INSET_IPV6_DST;
2843 if ((ipv6_mask->hdr.vtc_flow &
2844 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2845 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2846 input_set |= I40E_INSET_IPV6_TC;
2847 if (ipv6_mask->hdr.proto == UINT8_MAX)
2848 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2849 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2850 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2852 /* Get filter info */
2854 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2855 filter->input.flow.ipv6_flow.tc =
2856 (uint8_t)(vtc_flow_cpu >>
2857 I40E_FDIR_IPv6_TC_OFFSET);
2858 filter->input.flow.ipv6_flow.proto =
2859 ipv6_spec->hdr.proto;
2860 filter->input.flow.ipv6_flow.hop_limits =
2861 ipv6_spec->hdr.hop_limits;
2863 filter->input.flow_ext.inner_ip = false;
2864 filter->input.flow_ext.oip_type =
2865 I40E_FDIR_IPTYPE_IPV6;
2867 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2868 ipv6_spec->hdr.src_addr, 16);
2869 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2870 ipv6_spec->hdr.dst_addr, 16);
2872 /* Check if it is fragment. */
2873 if (ipv6_spec->hdr.proto ==
2874 I40E_IPV6_FRAG_HEADER)
2875 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2876 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2877 filter->input.flow_ext.inner_ip = true;
2878 filter->input.flow_ext.iip_type =
2879 I40E_FDIR_IPTYPE_IPV6;
2880 } else if (!ipv6_spec && !ipv6_mask && outer_ip) {
2881 filter->input.flow_ext.inner_ip = false;
2882 filter->input.flow_ext.oip_type =
2883 I40E_FDIR_IPTYPE_IPV6;
2884 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2885 rte_flow_error_set(error, EINVAL,
2886 RTE_FLOW_ERROR_TYPE_ITEM,
2888 "Invalid inner IPv6 mask");
2895 case RTE_FLOW_ITEM_TYPE_TCP:
2896 tcp_spec = item->spec;
2897 tcp_mask = item->mask;
2899 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2901 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2902 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2904 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2905 if (tcp_spec && tcp_mask) {
2906 /* Check TCP mask and update input set */
2907 if (tcp_mask->hdr.sent_seq ||
2908 tcp_mask->hdr.recv_ack ||
2909 tcp_mask->hdr.data_off ||
2910 tcp_mask->hdr.tcp_flags ||
2911 tcp_mask->hdr.rx_win ||
2912 tcp_mask->hdr.cksum ||
2913 tcp_mask->hdr.tcp_urp) {
2914 rte_flow_error_set(error, EINVAL,
2915 RTE_FLOW_ERROR_TYPE_ITEM,
2917 "Invalid TCP mask");
2921 if (tcp_mask->hdr.src_port == UINT16_MAX)
2922 input_set |= I40E_INSET_SRC_PORT;
2923 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2924 input_set |= I40E_INSET_DST_PORT;
2926 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2928 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2929 rte_flow_error_set(error, EINVAL,
2930 RTE_FLOW_ERROR_TYPE_ITEM,
2932 "L2 and L4 input set are exclusive.");
2936 /* Get filter info */
2937 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2938 filter->input.flow.tcp4_flow.src_port =
2939 tcp_spec->hdr.src_port;
2940 filter->input.flow.tcp4_flow.dst_port =
2941 tcp_spec->hdr.dst_port;
2942 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2943 filter->input.flow.tcp6_flow.src_port =
2944 tcp_spec->hdr.src_port;
2945 filter->input.flow.tcp6_flow.dst_port =
2946 tcp_spec->hdr.dst_port;
2951 layer_idx = I40E_FLXPLD_L4_IDX;
2954 case RTE_FLOW_ITEM_TYPE_UDP:
2955 udp_spec = item->spec;
2956 udp_mask = item->mask;
2958 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2960 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2961 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2963 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2965 if (udp_spec && udp_mask) {
2966 /* Check UDP mask and update input set*/
2967 if (udp_mask->hdr.dgram_len ||
2968 udp_mask->hdr.dgram_cksum) {
2969 rte_flow_error_set(error, EINVAL,
2970 RTE_FLOW_ERROR_TYPE_ITEM,
2972 "Invalid UDP mask");
2976 if (udp_mask->hdr.src_port == UINT16_MAX)
2977 input_set |= I40E_INSET_SRC_PORT;
2978 if (udp_mask->hdr.dst_port == UINT16_MAX)
2979 input_set |= I40E_INSET_DST_PORT;
2981 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2983 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2984 rte_flow_error_set(error, EINVAL,
2985 RTE_FLOW_ERROR_TYPE_ITEM,
2987 "L2 and L4 input set are exclusive.");
2991 /* Get filter info */
2992 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2993 filter->input.flow.udp4_flow.src_port =
2994 udp_spec->hdr.src_port;
2995 filter->input.flow.udp4_flow.dst_port =
2996 udp_spec->hdr.dst_port;
2997 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2998 filter->input.flow.udp6_flow.src_port =
2999 udp_spec->hdr.src_port;
3000 filter->input.flow.udp6_flow.dst_port =
3001 udp_spec->hdr.dst_port;
3005 filter->input.flow_ext.is_udp = true;
3006 layer_idx = I40E_FLXPLD_L4_IDX;
3009 case RTE_FLOW_ITEM_TYPE_GTPC:
3010 case RTE_FLOW_ITEM_TYPE_GTPU:
3011 if (!pf->gtp_support) {
3012 rte_flow_error_set(error, EINVAL,
3013 RTE_FLOW_ERROR_TYPE_ITEM,
3015 "Unsupported protocol");
3019 gtp_spec = item->spec;
3020 gtp_mask = item->mask;
3022 if (gtp_spec && gtp_mask) {
3023 if (gtp_mask->v_pt_rsv_flags ||
3024 gtp_mask->msg_type ||
3025 gtp_mask->msg_len ||
3026 gtp_mask->teid != UINT32_MAX) {
3027 rte_flow_error_set(error, EINVAL,
3028 RTE_FLOW_ERROR_TYPE_ITEM,
3030 "Invalid GTP mask");
3034 filter->input.flow.gtp_flow.teid =
3036 filter->input.flow_ext.customized_pctype = true;
3037 cus_proto = item_type;
3040 case RTE_FLOW_ITEM_TYPE_ESP:
3041 if (!pf->esp_support) {
3042 rte_flow_error_set(error, EINVAL,
3043 RTE_FLOW_ERROR_TYPE_ITEM,
3045 "Unsupported ESP protocol");
3049 esp_spec = item->spec;
3050 esp_mask = item->mask;
3052 if (!esp_spec || !esp_mask) {
3053 rte_flow_error_set(error, EINVAL,
3054 RTE_FLOW_ERROR_TYPE_ITEM,
3056 "Invalid ESP item");
3060 if (esp_spec && esp_mask) {
3061 if (esp_mask->hdr.spi != UINT32_MAX) {
3062 rte_flow_error_set(error, EINVAL,
3063 RTE_FLOW_ERROR_TYPE_ITEM,
3065 "Invalid ESP mask");
3068 i40e_flow_set_filter_spi(filter, esp_spec);
3069 filter->input.flow_ext.customized_pctype = true;
3070 cus_proto = item_type;
3073 case RTE_FLOW_ITEM_TYPE_SCTP:
3074 sctp_spec = item->spec;
3075 sctp_mask = item->mask;
3077 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
3079 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3080 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
3082 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3084 if (sctp_spec && sctp_mask) {
3085 /* Check SCTP mask and update input set */
3086 if (sctp_mask->hdr.cksum) {
3087 rte_flow_error_set(error, EINVAL,
3088 RTE_FLOW_ERROR_TYPE_ITEM,
3090 "Invalid UDP mask");
3094 if (sctp_mask->hdr.src_port == UINT16_MAX)
3095 input_set |= I40E_INSET_SRC_PORT;
3096 if (sctp_mask->hdr.dst_port == UINT16_MAX)
3097 input_set |= I40E_INSET_DST_PORT;
3098 if (sctp_mask->hdr.tag == UINT32_MAX)
3099 input_set |= I40E_INSET_SCTP_VT;
3101 /* Get filter info */
3102 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3103 filter->input.flow.sctp4_flow.src_port =
3104 sctp_spec->hdr.src_port;
3105 filter->input.flow.sctp4_flow.dst_port =
3106 sctp_spec->hdr.dst_port;
3107 filter->input.flow.sctp4_flow.verify_tag
3108 = sctp_spec->hdr.tag;
3109 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3110 filter->input.flow.sctp6_flow.src_port =
3111 sctp_spec->hdr.src_port;
3112 filter->input.flow.sctp6_flow.dst_port =
3113 sctp_spec->hdr.dst_port;
3114 filter->input.flow.sctp6_flow.verify_tag
3115 = sctp_spec->hdr.tag;
3119 layer_idx = I40E_FLXPLD_L4_IDX;
3122 case RTE_FLOW_ITEM_TYPE_RAW:
3123 raw_spec = item->spec;
3124 raw_mask = item->mask;
3126 if (!raw_spec || !raw_mask) {
3127 rte_flow_error_set(error, EINVAL,
3128 RTE_FLOW_ERROR_TYPE_ITEM,
3130 "NULL RAW spec/mask");
3134 if (pf->support_multi_driver) {
3135 rte_flow_error_set(error, ENOTSUP,
3136 RTE_FLOW_ERROR_TYPE_ITEM,
3138 "Unsupported flexible payload.");
3142 ret = i40e_flow_check_raw_item(item, raw_spec, error);
3146 off_arr[raw_id] = raw_spec->offset;
3147 len_arr[raw_id] = raw_spec->length;
3150 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
3152 raw_spec->length / sizeof(uint16_t);
3153 flex_pit.dst_offset =
3154 next_dst_off / sizeof(uint16_t);
3156 for (i = 0; i <= raw_id; i++) {
3158 flex_pit.src_offset +=
3162 flex_pit.src_offset +=
3163 (off_arr[i] + len_arr[i]) /
3165 flex_size += len_arr[i];
3167 if (((flex_pit.src_offset + flex_pit.size) >=
3168 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
3169 flex_size > I40E_FDIR_MAX_FLEXLEN) {
3170 rte_flow_error_set(error, EINVAL,
3171 RTE_FLOW_ERROR_TYPE_ITEM,
3173 "Exceeds maxmial payload limit.");
3177 /* Store flex pit to SW */
3178 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
3181 rte_flow_error_set(error, EINVAL,
3182 RTE_FLOW_ERROR_TYPE_ITEM,
3184 "Conflict with the first flexible rule.");
3187 cfg_flex_pit = false;
3189 for (i = 0; i < raw_spec->length; i++) {
3190 j = i + next_dst_off;
3191 filter->input.flow_ext.flexbytes[j] =
3192 raw_spec->pattern[i];
3193 flex_mask[j] = raw_mask->pattern[i];
3196 next_dst_off += raw_spec->length;
3199 case RTE_FLOW_ITEM_TYPE_VF:
3200 vf_spec = item->spec;
3201 if (!attr->transfer) {
3202 rte_flow_error_set(error, ENOTSUP,
3203 RTE_FLOW_ERROR_TYPE_ITEM,
3205 "Matching VF traffic"
3206 " without affecting it"
3207 " (transfer attribute)"
3211 filter->input.flow_ext.is_vf = 1;
3212 filter->input.flow_ext.dst_id = vf_spec->id;
3213 if (filter->input.flow_ext.is_vf &&
3214 filter->input.flow_ext.dst_id >= pf->vf_num) {
3215 rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ITEM,
3218 "Invalid VF ID for FDIR.");
3222 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
3223 l2tpv3oip_spec = item->spec;
3224 l2tpv3oip_mask = item->mask;
3226 if (!l2tpv3oip_spec || !l2tpv3oip_mask)
3229 if (l2tpv3oip_mask->session_id != UINT32_MAX) {
3230 rte_flow_error_set(error, EINVAL,
3231 RTE_FLOW_ERROR_TYPE_ITEM,
3233 "Invalid L2TPv3 mask");
3237 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3238 filter->input.flow.ip4_l2tpv3oip_flow.session_id =
3239 l2tpv3oip_spec->session_id;
3240 filter->input.flow_ext.oip_type =
3241 I40E_FDIR_IPTYPE_IPV4;
3242 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3243 filter->input.flow.ip6_l2tpv3oip_flow.session_id =
3244 l2tpv3oip_spec->session_id;
3245 filter->input.flow_ext.oip_type =
3246 I40E_FDIR_IPTYPE_IPV6;
3249 filter->input.flow_ext.customized_pctype = true;
3250 cus_proto = item_type;
3257 /* Get customized pctype value */
3258 if (filter->input.flow_ext.customized_pctype) {
3259 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
3260 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3261 rte_flow_error_set(error, EINVAL,
3262 RTE_FLOW_ERROR_TYPE_ITEM,
3264 "Unsupported pctype");
3269 /* If customized pctype is not used, set fdir configuration.*/
3270 if (!filter->input.flow_ext.customized_pctype) {
3271 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3273 rte_flow_error_set(error, EINVAL,
3274 RTE_FLOW_ERROR_TYPE_ITEM, item,
3275 "Conflict with the first rule's input set.");
3277 } else if (ret == -EINVAL) {
3278 rte_flow_error_set(error, EINVAL,
3279 RTE_FLOW_ERROR_TYPE_ITEM, item,
3280 "Invalid pattern mask.");
3284 /* Store flex mask to SW */
3285 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3287 rte_flow_error_set(error, EINVAL,
3288 RTE_FLOW_ERROR_TYPE_ITEM,
3290 "Exceed maximal number of bitmasks");
3292 } else if (ret == -2) {
3293 rte_flow_error_set(error, EINVAL,
3294 RTE_FLOW_ERROR_TYPE_ITEM,
3296 "Conflict with the first flexible rule");
3299 cfg_flex_msk = false;
3302 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3305 i40e_flow_set_fdir_flex_msk(pf, pctype);
3308 filter->input.pctype = pctype;
3313 /* Parse to get the action info of a FDIR filter.
3314 * FDIR action supports QUEUE or (QUEUE + MARK).
3317 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3318 const struct rte_flow_action *actions,
3319 struct rte_flow_error *error,
3320 struct i40e_fdir_filter_conf *filter)
3322 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323 const struct rte_flow_action *act;
3324 const struct rte_flow_action_queue *act_q;
3325 const struct rte_flow_action_mark *mark_spec = NULL;
3328 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3329 NEXT_ITEM_OF_ACTION(act, actions, index);
3330 switch (act->type) {
3331 case RTE_FLOW_ACTION_TYPE_QUEUE:
3333 filter->action.rx_queue = act_q->index;
3334 if ((!filter->input.flow_ext.is_vf &&
3335 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3336 (filter->input.flow_ext.is_vf &&
3337 filter->action.rx_queue >= pf->vf_nb_qps)) {
3338 rte_flow_error_set(error, EINVAL,
3339 RTE_FLOW_ERROR_TYPE_ACTION, act,
3340 "Invalid queue ID for FDIR.");
3343 filter->action.behavior = I40E_FDIR_ACCEPT;
3345 case RTE_FLOW_ACTION_TYPE_DROP:
3346 filter->action.behavior = I40E_FDIR_REJECT;
3348 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3349 filter->action.behavior = I40E_FDIR_PASSTHRU;
3351 case RTE_FLOW_ACTION_TYPE_MARK:
3352 filter->action.behavior = I40E_FDIR_PASSTHRU;
3353 mark_spec = act->conf;
3354 filter->action.report_status = I40E_FDIR_REPORT_ID;
3355 filter->soft_id = mark_spec->id;
3358 rte_flow_error_set(error, EINVAL,
3359 RTE_FLOW_ERROR_TYPE_ACTION, act,
3364 /* Check if the next non-void item is MARK or FLAG or END. */
3366 NEXT_ITEM_OF_ACTION(act, actions, index);
3367 switch (act->type) {
3368 case RTE_FLOW_ACTION_TYPE_MARK:
3370 /* Double MARK actions requested */
3371 rte_flow_error_set(error, EINVAL,
3372 RTE_FLOW_ERROR_TYPE_ACTION, act,
3376 mark_spec = act->conf;
3377 filter->action.report_status = I40E_FDIR_REPORT_ID;
3378 filter->soft_id = mark_spec->id;
3380 case RTE_FLOW_ACTION_TYPE_FLAG:
3382 /* MARK + FLAG not supported */
3383 rte_flow_error_set(error, EINVAL,
3384 RTE_FLOW_ERROR_TYPE_ACTION, act,
3388 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3390 case RTE_FLOW_ACTION_TYPE_RSS:
3391 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3392 /* RSS filter won't be next if FDIR did not pass thru */
3393 rte_flow_error_set(error, EINVAL,
3394 RTE_FLOW_ERROR_TYPE_ACTION, act,
3399 case RTE_FLOW_ACTION_TYPE_END:
3402 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3403 act, "Invalid action.");
3407 /* Check if the next non-void item is END */
3409 NEXT_ITEM_OF_ACTION(act, actions, index);
3410 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3411 rte_flow_error_set(error, EINVAL,
3412 RTE_FLOW_ERROR_TYPE_ACTION,
3413 act, "Invalid action.");
3421 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3422 const struct rte_flow_attr *attr,
3423 const struct rte_flow_item pattern[],
3424 const struct rte_flow_action actions[],
3425 struct rte_flow_error *error,
3426 union i40e_filter_t *filter)
3428 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3429 struct i40e_fdir_filter_conf *fdir_filter =
3430 &filter->fdir_filter;
3433 ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3438 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3442 ret = i40e_flow_parse_attr(attr, error);
3446 cons_filter_type = RTE_ETH_FILTER_FDIR;
3448 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT ||
3449 pf->fdir.fdir_vsi == NULL) {
3450 /* Enable fdir when fdir flow is added at first time. */
3451 ret = i40e_fdir_setup(pf);
3452 if (ret != I40E_SUCCESS) {
3453 rte_flow_error_set(error, ENOTSUP,
3454 RTE_FLOW_ERROR_TYPE_HANDLE,
3455 NULL, "Failed to setup fdir.");
3458 ret = i40e_fdir_configure(dev);
3460 rte_flow_error_set(error, ENOTSUP,
3461 RTE_FLOW_ERROR_TYPE_HANDLE,
3462 NULL, "Failed to configure fdir.");
3466 dev->data->dev_conf.fdir_conf.mode = RTE_FDIR_MODE_PERFECT;
3471 i40e_fdir_teardown(pf);
3475 /* Parse to get the action info of a tunnel filter
3476 * Tunnel action only supports PF, VF and QUEUE.
3479 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3480 const struct rte_flow_action *actions,
3481 struct rte_flow_error *error,
3482 struct i40e_tunnel_filter_conf *filter)
3484 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3485 const struct rte_flow_action *act;
3486 const struct rte_flow_action_queue *act_q;
3487 const struct rte_flow_action_vf *act_vf;
3490 /* Check if the first non-void action is PF or VF. */
3491 NEXT_ITEM_OF_ACTION(act, actions, index);
3492 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3493 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3494 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3495 act, "Not supported action.");
3499 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3501 filter->vf_id = act_vf->id;
3502 filter->is_to_vf = 1;
3503 if (filter->vf_id >= pf->vf_num) {
3504 rte_flow_error_set(error, EINVAL,
3505 RTE_FLOW_ERROR_TYPE_ACTION,
3506 act, "Invalid VF ID for tunnel filter");
3511 /* Check if the next non-void item is QUEUE */
3513 NEXT_ITEM_OF_ACTION(act, actions, index);
3514 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3516 filter->queue_id = act_q->index;
3517 if ((!filter->is_to_vf) &&
3518 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3519 rte_flow_error_set(error, EINVAL,
3520 RTE_FLOW_ERROR_TYPE_ACTION,
3521 act, "Invalid queue ID for tunnel filter");
3523 } else if (filter->is_to_vf &&
3524 (filter->queue_id >= pf->vf_nb_qps)) {
3525 rte_flow_error_set(error, EINVAL,
3526 RTE_FLOW_ERROR_TYPE_ACTION,
3527 act, "Invalid queue ID for tunnel filter");
3532 /* Check if the next non-void item is END */
3534 NEXT_ITEM_OF_ACTION(act, actions, index);
3535 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3536 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3537 act, "Not supported action.");
3544 static uint16_t i40e_supported_tunnel_filter_types[] = {
3545 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3546 ETH_TUNNEL_FILTER_IVLAN,
3547 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3548 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3549 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3550 ETH_TUNNEL_FILTER_IMAC,
3551 ETH_TUNNEL_FILTER_IMAC,
3555 i40e_check_tunnel_filter_type(uint8_t filter_type)
3559 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3560 if (filter_type == i40e_supported_tunnel_filter_types[i])
3567 /* 1. Last in item should be NULL as range is not supported.
3568 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3569 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3570 * 3. Mask of fields which need to be matched should be
3572 * 4. Mask of fields which needn't to be matched should be
3576 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3577 const struct rte_flow_item *pattern,
3578 struct rte_flow_error *error,
3579 struct i40e_tunnel_filter_conf *filter)
3581 const struct rte_flow_item *item = pattern;
3582 const struct rte_flow_item_eth *eth_spec;
3583 const struct rte_flow_item_eth *eth_mask;
3584 const struct rte_flow_item_vxlan *vxlan_spec;
3585 const struct rte_flow_item_vxlan *vxlan_mask;
3586 const struct rte_flow_item_vlan *vlan_spec;
3587 const struct rte_flow_item_vlan *vlan_mask;
3588 uint8_t filter_type = 0;
3589 bool is_vni_masked = 0;
3590 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3591 enum rte_flow_item_type item_type;
3592 bool vxlan_flag = 0;
3593 uint32_t tenant_id_be = 0;
3596 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3598 rte_flow_error_set(error, EINVAL,
3599 RTE_FLOW_ERROR_TYPE_ITEM,
3601 "Not support range");
3604 item_type = item->type;
3605 switch (item_type) {
3606 case RTE_FLOW_ITEM_TYPE_ETH:
3607 eth_spec = item->spec;
3608 eth_mask = item->mask;
3610 /* Check if ETH item is used for place holder.
3611 * If yes, both spec and mask should be NULL.
3612 * If no, both spec and mask shouldn't be NULL.
3614 if ((!eth_spec && eth_mask) ||
3615 (eth_spec && !eth_mask)) {
3616 rte_flow_error_set(error, EINVAL,
3617 RTE_FLOW_ERROR_TYPE_ITEM,
3619 "Invalid ether spec/mask");
3623 if (eth_spec && eth_mask) {
3624 /* DST address of inner MAC shouldn't be masked.
3625 * SRC address of Inner MAC should be masked.
3627 if (!rte_is_broadcast_ether_addr(ð_mask->dst) ||
3628 !rte_is_zero_ether_addr(ð_mask->src) ||
3630 rte_flow_error_set(error, EINVAL,
3631 RTE_FLOW_ERROR_TYPE_ITEM,
3633 "Invalid ether spec/mask");
3638 rte_memcpy(&filter->outer_mac,
3640 RTE_ETHER_ADDR_LEN);
3641 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3643 rte_memcpy(&filter->inner_mac,
3645 RTE_ETHER_ADDR_LEN);
3646 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3650 case RTE_FLOW_ITEM_TYPE_VLAN:
3651 vlan_spec = item->spec;
3652 vlan_mask = item->mask;
3653 if (!(vlan_spec && vlan_mask) ||
3654 vlan_mask->inner_type) {
3655 rte_flow_error_set(error, EINVAL,
3656 RTE_FLOW_ERROR_TYPE_ITEM,
3658 "Invalid vlan item");
3662 if (vlan_spec && vlan_mask) {
3663 if (vlan_mask->tci ==
3664 rte_cpu_to_be_16(I40E_TCI_MASK))
3665 filter->inner_vlan =
3666 rte_be_to_cpu_16(vlan_spec->tci) &
3668 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3671 case RTE_FLOW_ITEM_TYPE_IPV4:
3672 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3673 /* IPv4 is used to describe protocol,
3674 * spec and mask should be NULL.
3676 if (item->spec || item->mask) {
3677 rte_flow_error_set(error, EINVAL,
3678 RTE_FLOW_ERROR_TYPE_ITEM,
3680 "Invalid IPv4 item");
3684 case RTE_FLOW_ITEM_TYPE_IPV6:
3685 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3686 /* IPv6 is used to describe protocol,
3687 * spec and mask should be NULL.
3689 if (item->spec || item->mask) {
3690 rte_flow_error_set(error, EINVAL,
3691 RTE_FLOW_ERROR_TYPE_ITEM,
3693 "Invalid IPv6 item");
3697 case RTE_FLOW_ITEM_TYPE_UDP:
3698 /* UDP is used to describe protocol,
3699 * spec and mask should be NULL.
3701 if (item->spec || item->mask) {
3702 rte_flow_error_set(error, EINVAL,
3703 RTE_FLOW_ERROR_TYPE_ITEM,
3705 "Invalid UDP item");
3709 case RTE_FLOW_ITEM_TYPE_VXLAN:
3710 vxlan_spec = item->spec;
3711 vxlan_mask = item->mask;
3712 /* Check if VXLAN item is used to describe protocol.
3713 * If yes, both spec and mask should be NULL.
3714 * If no, both spec and mask shouldn't be NULL.
3716 if ((!vxlan_spec && vxlan_mask) ||
3717 (vxlan_spec && !vxlan_mask)) {
3718 rte_flow_error_set(error, EINVAL,
3719 RTE_FLOW_ERROR_TYPE_ITEM,
3721 "Invalid VXLAN item");
3725 /* Check if VNI is masked. */
3726 if (vxlan_spec && vxlan_mask) {
3728 !!memcmp(vxlan_mask->vni, vni_mask,
3730 if (is_vni_masked) {
3731 rte_flow_error_set(error, EINVAL,
3732 RTE_FLOW_ERROR_TYPE_ITEM,
3734 "Invalid VNI mask");
3738 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3739 vxlan_spec->vni, 3);
3741 rte_be_to_cpu_32(tenant_id_be);
3742 filter_type |= ETH_TUNNEL_FILTER_TENID;
3752 ret = i40e_check_tunnel_filter_type(filter_type);
3754 rte_flow_error_set(error, EINVAL,
3755 RTE_FLOW_ERROR_TYPE_ITEM,
3757 "Invalid filter type");
3760 filter->filter_type = filter_type;
3762 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3768 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3769 const struct rte_flow_attr *attr,
3770 const struct rte_flow_item pattern[],
3771 const struct rte_flow_action actions[],
3772 struct rte_flow_error *error,
3773 union i40e_filter_t *filter)
3775 struct i40e_tunnel_filter_conf *tunnel_filter =
3776 &filter->consistent_tunnel_filter;
3779 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3780 error, tunnel_filter);
3784 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3788 ret = i40e_flow_parse_attr(attr, error);
3792 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3797 /* 1. Last in item should be NULL as range is not supported.
3798 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3799 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3800 * 3. Mask of fields which need to be matched should be
3802 * 4. Mask of fields which needn't to be matched should be
3806 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3807 const struct rte_flow_item *pattern,
3808 struct rte_flow_error *error,
3809 struct i40e_tunnel_filter_conf *filter)
3811 const struct rte_flow_item *item = pattern;
3812 const struct rte_flow_item_eth *eth_spec;
3813 const struct rte_flow_item_eth *eth_mask;
3814 const struct rte_flow_item_nvgre *nvgre_spec;
3815 const struct rte_flow_item_nvgre *nvgre_mask;
3816 const struct rte_flow_item_vlan *vlan_spec;
3817 const struct rte_flow_item_vlan *vlan_mask;
3818 enum rte_flow_item_type item_type;
3819 uint8_t filter_type = 0;
3820 bool is_tni_masked = 0;
3821 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3822 bool nvgre_flag = 0;
3823 uint32_t tenant_id_be = 0;
3826 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3828 rte_flow_error_set(error, EINVAL,
3829 RTE_FLOW_ERROR_TYPE_ITEM,
3831 "Not support range");
3834 item_type = item->type;
3835 switch (item_type) {
3836 case RTE_FLOW_ITEM_TYPE_ETH:
3837 eth_spec = item->spec;
3838 eth_mask = item->mask;
3840 /* Check if ETH item is used for place holder.
3841 * If yes, both spec and mask should be NULL.
3842 * If no, both spec and mask shouldn't be NULL.
3844 if ((!eth_spec && eth_mask) ||
3845 (eth_spec && !eth_mask)) {
3846 rte_flow_error_set(error, EINVAL,
3847 RTE_FLOW_ERROR_TYPE_ITEM,
3849 "Invalid ether spec/mask");
3853 if (eth_spec && eth_mask) {
3854 /* DST address of inner MAC shouldn't be masked.
3855 * SRC address of Inner MAC should be masked.
3857 if (!rte_is_broadcast_ether_addr(ð_mask->dst) ||
3858 !rte_is_zero_ether_addr(ð_mask->src) ||
3860 rte_flow_error_set(error, EINVAL,
3861 RTE_FLOW_ERROR_TYPE_ITEM,
3863 "Invalid ether spec/mask");
3868 rte_memcpy(&filter->outer_mac,
3870 RTE_ETHER_ADDR_LEN);
3871 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3873 rte_memcpy(&filter->inner_mac,
3875 RTE_ETHER_ADDR_LEN);
3876 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3881 case RTE_FLOW_ITEM_TYPE_VLAN:
3882 vlan_spec = item->spec;
3883 vlan_mask = item->mask;
3884 if (!(vlan_spec && vlan_mask) ||
3885 vlan_mask->inner_type) {
3886 rte_flow_error_set(error, EINVAL,
3887 RTE_FLOW_ERROR_TYPE_ITEM,
3889 "Invalid vlan item");
3893 if (vlan_spec && vlan_mask) {
3894 if (vlan_mask->tci ==
3895 rte_cpu_to_be_16(I40E_TCI_MASK))
3896 filter->inner_vlan =
3897 rte_be_to_cpu_16(vlan_spec->tci) &
3899 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3902 case RTE_FLOW_ITEM_TYPE_IPV4:
3903 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3904 /* IPv4 is used to describe protocol,
3905 * spec and mask should be NULL.
3907 if (item->spec || item->mask) {
3908 rte_flow_error_set(error, EINVAL,
3909 RTE_FLOW_ERROR_TYPE_ITEM,
3911 "Invalid IPv4 item");
3915 case RTE_FLOW_ITEM_TYPE_IPV6:
3916 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3917 /* IPv6 is used to describe protocol,
3918 * spec and mask should be NULL.
3920 if (item->spec || item->mask) {
3921 rte_flow_error_set(error, EINVAL,
3922 RTE_FLOW_ERROR_TYPE_ITEM,
3924 "Invalid IPv6 item");
3928 case RTE_FLOW_ITEM_TYPE_NVGRE:
3929 nvgre_spec = item->spec;
3930 nvgre_mask = item->mask;
3931 /* Check if NVGRE item is used to describe protocol.
3932 * If yes, both spec and mask should be NULL.
3933 * If no, both spec and mask shouldn't be NULL.
3935 if ((!nvgre_spec && nvgre_mask) ||
3936 (nvgre_spec && !nvgre_mask)) {
3937 rte_flow_error_set(error, EINVAL,
3938 RTE_FLOW_ERROR_TYPE_ITEM,
3940 "Invalid NVGRE item");
3944 if (nvgre_spec && nvgre_mask) {
3946 !!memcmp(nvgre_mask->tni, tni_mask,
3948 if (is_tni_masked) {
3949 rte_flow_error_set(error, EINVAL,
3950 RTE_FLOW_ERROR_TYPE_ITEM,
3952 "Invalid TNI mask");
3955 if (nvgre_mask->protocol &&
3956 nvgre_mask->protocol != 0xFFFF) {
3957 rte_flow_error_set(error, EINVAL,
3958 RTE_FLOW_ERROR_TYPE_ITEM,
3960 "Invalid NVGRE item");
3963 if (nvgre_mask->c_k_s_rsvd0_ver &&
3964 nvgre_mask->c_k_s_rsvd0_ver !=
3965 rte_cpu_to_be_16(0xFFFF)) {
3966 rte_flow_error_set(error, EINVAL,
3967 RTE_FLOW_ERROR_TYPE_ITEM,
3969 "Invalid NVGRE item");
3972 if (nvgre_spec->c_k_s_rsvd0_ver !=
3973 rte_cpu_to_be_16(0x2000) &&
3974 nvgre_mask->c_k_s_rsvd0_ver) {
3975 rte_flow_error_set(error, EINVAL,
3976 RTE_FLOW_ERROR_TYPE_ITEM,
3978 "Invalid NVGRE item");
3981 if (nvgre_mask->protocol &&
3982 nvgre_spec->protocol !=
3983 rte_cpu_to_be_16(0x6558)) {
3984 rte_flow_error_set(error, EINVAL,
3985 RTE_FLOW_ERROR_TYPE_ITEM,
3987 "Invalid NVGRE item");
3990 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3991 nvgre_spec->tni, 3);
3993 rte_be_to_cpu_32(tenant_id_be);
3994 filter_type |= ETH_TUNNEL_FILTER_TENID;
4004 ret = i40e_check_tunnel_filter_type(filter_type);
4006 rte_flow_error_set(error, EINVAL,
4007 RTE_FLOW_ERROR_TYPE_ITEM,
4009 "Invalid filter type");
4012 filter->filter_type = filter_type;
4014 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
4020 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
4021 const struct rte_flow_attr *attr,
4022 const struct rte_flow_item pattern[],
4023 const struct rte_flow_action actions[],
4024 struct rte_flow_error *error,
4025 union i40e_filter_t *filter)
4027 struct i40e_tunnel_filter_conf *tunnel_filter =
4028 &filter->consistent_tunnel_filter;
4031 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
4032 error, tunnel_filter);
4036 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4040 ret = i40e_flow_parse_attr(attr, error);
4044 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4049 /* 1. Last in item should be NULL as range is not supported.
4050 * 2. Supported filter types: MPLS label.
4051 * 3. Mask of fields which need to be matched should be
4053 * 4. Mask of fields which needn't to be matched should be
4057 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
4058 const struct rte_flow_item *pattern,
4059 struct rte_flow_error *error,
4060 struct i40e_tunnel_filter_conf *filter)
4062 const struct rte_flow_item *item = pattern;
4063 const struct rte_flow_item_mpls *mpls_spec;
4064 const struct rte_flow_item_mpls *mpls_mask;
4065 enum rte_flow_item_type item_type;
4066 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
4067 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
4068 uint32_t label_be = 0;
4070 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4072 rte_flow_error_set(error, EINVAL,
4073 RTE_FLOW_ERROR_TYPE_ITEM,
4075 "Not support range");
4078 item_type = item->type;
4079 switch (item_type) {
4080 case RTE_FLOW_ITEM_TYPE_ETH:
4081 if (item->spec || item->mask) {
4082 rte_flow_error_set(error, EINVAL,
4083 RTE_FLOW_ERROR_TYPE_ITEM,
4085 "Invalid ETH item");
4089 case RTE_FLOW_ITEM_TYPE_IPV4:
4090 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4091 /* IPv4 is used to describe protocol,
4092 * spec and mask should be NULL.
4094 if (item->spec || item->mask) {
4095 rte_flow_error_set(error, EINVAL,
4096 RTE_FLOW_ERROR_TYPE_ITEM,
4098 "Invalid IPv4 item");
4102 case RTE_FLOW_ITEM_TYPE_IPV6:
4103 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
4104 /* IPv6 is used to describe protocol,
4105 * spec and mask should be NULL.
4107 if (item->spec || item->mask) {
4108 rte_flow_error_set(error, EINVAL,
4109 RTE_FLOW_ERROR_TYPE_ITEM,
4111 "Invalid IPv6 item");
4115 case RTE_FLOW_ITEM_TYPE_UDP:
4116 /* UDP is used to describe protocol,
4117 * spec and mask should be NULL.
4119 if (item->spec || item->mask) {
4120 rte_flow_error_set(error, EINVAL,
4121 RTE_FLOW_ERROR_TYPE_ITEM,
4123 "Invalid UDP item");
4128 case RTE_FLOW_ITEM_TYPE_GRE:
4129 /* GRE is used to describe protocol,
4130 * spec and mask should be NULL.
4132 if (item->spec || item->mask) {
4133 rte_flow_error_set(error, EINVAL,
4134 RTE_FLOW_ERROR_TYPE_ITEM,
4136 "Invalid GRE item");
4140 case RTE_FLOW_ITEM_TYPE_MPLS:
4141 mpls_spec = item->spec;
4142 mpls_mask = item->mask;
4144 if (!mpls_spec || !mpls_mask) {
4145 rte_flow_error_set(error, EINVAL,
4146 RTE_FLOW_ERROR_TYPE_ITEM,
4148 "Invalid MPLS item");
4152 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
4153 rte_flow_error_set(error, EINVAL,
4154 RTE_FLOW_ERROR_TYPE_ITEM,
4156 "Invalid MPLS label mask");
4159 rte_memcpy(((uint8_t *)&label_be + 1),
4160 mpls_spec->label_tc_s, 3);
4161 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
4169 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
4171 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
4177 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
4178 const struct rte_flow_attr *attr,
4179 const struct rte_flow_item pattern[],
4180 const struct rte_flow_action actions[],
4181 struct rte_flow_error *error,
4182 union i40e_filter_t *filter)
4184 struct i40e_tunnel_filter_conf *tunnel_filter =
4185 &filter->consistent_tunnel_filter;
4188 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
4189 error, tunnel_filter);
4193 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4197 ret = i40e_flow_parse_attr(attr, error);
4201 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4206 /* 1. Last in item should be NULL as range is not supported.
4207 * 2. Supported filter types: GTP TEID.
4208 * 3. Mask of fields which need to be matched should be
4210 * 4. Mask of fields which needn't to be matched should be
4212 * 5. GTP profile supports GTPv1 only.
4213 * 6. GTP-C response message ('source_port' = 2123) is not supported.
4216 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
4217 const struct rte_flow_item *pattern,
4218 struct rte_flow_error *error,
4219 struct i40e_tunnel_filter_conf *filter)
4221 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4222 const struct rte_flow_item *item = pattern;
4223 const struct rte_flow_item_gtp *gtp_spec;
4224 const struct rte_flow_item_gtp *gtp_mask;
4225 enum rte_flow_item_type item_type;
4227 if (!pf->gtp_support) {
4228 rte_flow_error_set(error, EINVAL,
4229 RTE_FLOW_ERROR_TYPE_ITEM,
4231 "GTP is not supported by default.");
4235 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4237 rte_flow_error_set(error, EINVAL,
4238 RTE_FLOW_ERROR_TYPE_ITEM,
4240 "Not support range");
4243 item_type = item->type;
4244 switch (item_type) {
4245 case RTE_FLOW_ITEM_TYPE_ETH:
4246 if (item->spec || item->mask) {
4247 rte_flow_error_set(error, EINVAL,
4248 RTE_FLOW_ERROR_TYPE_ITEM,
4250 "Invalid ETH item");
4254 case RTE_FLOW_ITEM_TYPE_IPV4:
4255 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4256 /* IPv4 is used to describe protocol,
4257 * spec and mask should be NULL.
4259 if (item->spec || item->mask) {
4260 rte_flow_error_set(error, EINVAL,
4261 RTE_FLOW_ERROR_TYPE_ITEM,
4263 "Invalid IPv4 item");
4267 case RTE_FLOW_ITEM_TYPE_UDP:
4268 if (item->spec || item->mask) {
4269 rte_flow_error_set(error, EINVAL,
4270 RTE_FLOW_ERROR_TYPE_ITEM,
4272 "Invalid UDP item");
4276 case RTE_FLOW_ITEM_TYPE_GTPC:
4277 case RTE_FLOW_ITEM_TYPE_GTPU:
4278 gtp_spec = item->spec;
4279 gtp_mask = item->mask;
4281 if (!gtp_spec || !gtp_mask) {
4282 rte_flow_error_set(error, EINVAL,
4283 RTE_FLOW_ERROR_TYPE_ITEM,
4285 "Invalid GTP item");
4289 if (gtp_mask->v_pt_rsv_flags ||
4290 gtp_mask->msg_type ||
4291 gtp_mask->msg_len ||
4292 gtp_mask->teid != UINT32_MAX) {
4293 rte_flow_error_set(error, EINVAL,
4294 RTE_FLOW_ERROR_TYPE_ITEM,
4296 "Invalid GTP mask");
4300 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4301 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4302 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4303 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4305 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4317 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4318 const struct rte_flow_attr *attr,
4319 const struct rte_flow_item pattern[],
4320 const struct rte_flow_action actions[],
4321 struct rte_flow_error *error,
4322 union i40e_filter_t *filter)
4324 struct i40e_tunnel_filter_conf *tunnel_filter =
4325 &filter->consistent_tunnel_filter;
4328 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4329 error, tunnel_filter);
4333 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4337 ret = i40e_flow_parse_attr(attr, error);
4341 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4346 /* 1. Last in item should be NULL as range is not supported.
4347 * 2. Supported filter types: QINQ.
4348 * 3. Mask of fields which need to be matched should be
4350 * 4. Mask of fields which needn't to be matched should be
4354 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4355 const struct rte_flow_item *pattern,
4356 struct rte_flow_error *error,
4357 struct i40e_tunnel_filter_conf *filter)
4359 const struct rte_flow_item *item = pattern;
4360 const struct rte_flow_item_vlan *vlan_spec = NULL;
4361 const struct rte_flow_item_vlan *vlan_mask = NULL;
4362 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4363 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4364 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4365 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4367 enum rte_flow_item_type item_type;
4370 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4372 rte_flow_error_set(error, EINVAL,
4373 RTE_FLOW_ERROR_TYPE_ITEM,
4375 "Not support range");
4378 item_type = item->type;
4379 switch (item_type) {
4380 case RTE_FLOW_ITEM_TYPE_ETH:
4381 if (item->spec || item->mask) {
4382 rte_flow_error_set(error, EINVAL,
4383 RTE_FLOW_ERROR_TYPE_ITEM,
4385 "Invalid ETH item");
4389 case RTE_FLOW_ITEM_TYPE_VLAN:
4390 vlan_spec = item->spec;
4391 vlan_mask = item->mask;
4393 if (!(vlan_spec && vlan_mask) ||
4394 vlan_mask->inner_type) {
4395 rte_flow_error_set(error, EINVAL,
4396 RTE_FLOW_ERROR_TYPE_ITEM,
4398 "Invalid vlan item");
4403 o_vlan_spec = vlan_spec;
4404 o_vlan_mask = vlan_mask;
4407 i_vlan_spec = vlan_spec;
4408 i_vlan_mask = vlan_mask;
4418 /* Get filter specification */
4419 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4420 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4421 (i_vlan_mask != NULL) &&
4422 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4423 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4425 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4428 rte_flow_error_set(error, EINVAL,
4429 RTE_FLOW_ERROR_TYPE_ITEM,
4431 "Invalid filter type");
4435 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4440 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4441 const struct rte_flow_attr *attr,
4442 const struct rte_flow_item pattern[],
4443 const struct rte_flow_action actions[],
4444 struct rte_flow_error *error,
4445 union i40e_filter_t *filter)
4447 struct i40e_tunnel_filter_conf *tunnel_filter =
4448 &filter->consistent_tunnel_filter;
4451 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4452 error, tunnel_filter);
4456 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4460 ret = i40e_flow_parse_attr(attr, error);
4464 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4470 * This function is used to do configuration i40e existing RSS with rte_flow.
4471 * It also enable queue region configuration using flow API for i40e.
4472 * pattern can be used indicate what parameters will be include in flow,
4473 * like user_priority or flowtype for queue region or HASH function for RSS.
4474 * Action is used to transmit parameter like queue index and HASH
4475 * function for RSS, or flowtype for queue region configuration.
4478 * Case 1: only ETH, indicate flowtype for queue region will be parsed.
4479 * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4480 * Case 3: none, indicate RSS related will be parsed in action.
4481 * Any pattern other the ETH or VLAN will be treated as invalid except END.
4482 * So, pattern choice is depened on the purpose of configuration of
4485 * action RSS will be uaed to transmit valid parameter with
4486 * struct rte_flow_action_rss for all the 3 case.
4489 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4490 const struct rte_flow_item *pattern,
4491 struct rte_flow_error *error,
4492 uint8_t *action_flag,
4493 struct i40e_queue_regions *info)
4495 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4496 const struct rte_flow_item *item = pattern;
4497 enum rte_flow_item_type item_type;
4499 if (item->type == RTE_FLOW_ITEM_TYPE_END)
4502 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4504 rte_flow_error_set(error, EINVAL,
4505 RTE_FLOW_ERROR_TYPE_ITEM,
4507 "Not support range");
4510 item_type = item->type;
4511 switch (item_type) {
4512 case RTE_FLOW_ITEM_TYPE_ETH:
4515 case RTE_FLOW_ITEM_TYPE_VLAN:
4516 vlan_spec = item->spec;
4517 vlan_mask = item->mask;
4518 if (vlan_spec && vlan_mask) {
4519 if (vlan_mask->tci ==
4520 rte_cpu_to_be_16(I40E_TCI_MASK)) {
4521 info->region[0].user_priority[0] =
4523 vlan_spec->tci) >> 13) & 0x7;
4524 info->region[0].user_priority_num = 1;
4525 info->queue_region_number = 1;
4531 rte_flow_error_set(error, EINVAL,
4532 RTE_FLOW_ERROR_TYPE_ITEM,
4534 "Not support range");
4543 * This function is used to parse rss queue index, total queue number and
4544 * hash functions, If the purpose of this configuration is for queue region
4545 * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4546 * In queue region configuration, it also need to parse hardware flowtype
4547 * and user_priority from configuration, it will also cheeck the validity
4548 * of these parameters. For example, The queue region sizes should
4549 * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4550 * hw_flowtype or PCTYPE max index should be 63, the user priority
4551 * max index should be 7, and so on. And also, queue index should be
4552 * continuous sequence and queue region index should be part of rss
4553 * queue index for this port.
4556 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4557 const struct rte_flow_action *actions,
4558 struct rte_flow_error *error,
4559 uint8_t action_flag,
4560 struct i40e_queue_regions *conf_info,
4561 union i40e_filter_t *filter)
4563 const struct rte_flow_action *act;
4564 const struct rte_flow_action_rss *rss;
4565 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4566 struct i40e_queue_regions *info = &pf->queue_region;
4567 struct i40e_rte_flow_rss_conf *rss_config =
4569 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4570 uint16_t i, j, n, tmp;
4572 uint64_t hf_bit = 1;
4574 NEXT_ITEM_OF_ACTION(act, actions, index);
4578 * rss only supports forwarding,
4579 * check if the first not void action is RSS.
4581 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4582 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4583 rte_flow_error_set(error, EINVAL,
4584 RTE_FLOW_ERROR_TYPE_ACTION,
4585 act, "Not supported action.");
4590 for (n = 0; n < 64; n++) {
4591 if (rss->types & (hf_bit << n)) {
4592 conf_info->region[0].hw_flowtype[0] = n;
4593 conf_info->region[0].flowtype_num = 1;
4594 conf_info->queue_region_number = 1;
4601 * Do some queue region related parameters check
4602 * in order to keep queue index for queue region to be
4603 * continuous sequence and also to be part of RSS
4604 * queue index for this port.
4606 if (conf_info->queue_region_number) {
4607 for (i = 0; i < rss->queue_num; i++) {
4608 for (j = 0; j < rss_info->conf.queue_num; j++) {
4609 if (rss->queue[i] == rss_info->conf.queue[j])
4612 if (j == rss_info->conf.queue_num) {
4613 rte_flow_error_set(error, EINVAL,
4614 RTE_FLOW_ERROR_TYPE_ACTION,
4621 for (i = 0; i < rss->queue_num - 1; i++) {
4622 if (rss->queue[i + 1] != rss->queue[i] + 1) {
4623 rte_flow_error_set(error, EINVAL,
4624 RTE_FLOW_ERROR_TYPE_ACTION,
4632 /* Parse queue region related parameters from configuration */
4633 for (n = 0; n < conf_info->queue_region_number; n++) {
4634 if (conf_info->region[n].user_priority_num ||
4635 conf_info->region[n].flowtype_num) {
4636 if (!((rte_is_power_of_2(rss->queue_num)) &&
4637 rss->queue_num <= 64)) {
4638 rte_flow_error_set(error, EINVAL,
4639 RTE_FLOW_ERROR_TYPE_ACTION,
4641 "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4642 "total number of queues do not exceed the VSI allocation");
4646 if (conf_info->region[n].user_priority[n] >=
4647 I40E_MAX_USER_PRIORITY) {
4648 rte_flow_error_set(error, EINVAL,
4649 RTE_FLOW_ERROR_TYPE_ACTION,
4651 "the user priority max index is 7");
4655 if (conf_info->region[n].hw_flowtype[n] >=
4656 I40E_FILTER_PCTYPE_MAX) {
4657 rte_flow_error_set(error, EINVAL,
4658 RTE_FLOW_ERROR_TYPE_ACTION,
4660 "the hw_flowtype or PCTYPE max index is 63");
4664 for (i = 0; i < info->queue_region_number; i++) {
4665 if (info->region[i].queue_num ==
4667 info->region[i].queue_start_index ==
4672 if (i == info->queue_region_number) {
4673 if (i > I40E_REGION_MAX_INDEX) {
4674 rte_flow_error_set(error, EINVAL,
4675 RTE_FLOW_ERROR_TYPE_ACTION,
4677 "the queue region max index is 7");
4681 info->region[i].queue_num =
4683 info->region[i].queue_start_index =
4685 info->region[i].region_id =
4686 info->queue_region_number;
4688 j = info->region[i].user_priority_num;
4689 tmp = conf_info->region[n].user_priority[0];
4690 if (conf_info->region[n].user_priority_num) {
4691 info->region[i].user_priority[j] = tmp;
4692 info->region[i].user_priority_num++;
4695 j = info->region[i].flowtype_num;
4696 tmp = conf_info->region[n].hw_flowtype[0];
4697 if (conf_info->region[n].flowtype_num) {
4698 info->region[i].hw_flowtype[j] = tmp;
4699 info->region[i].flowtype_num++;
4701 info->queue_region_number++;
4703 j = info->region[i].user_priority_num;
4704 tmp = conf_info->region[n].user_priority[0];
4705 if (conf_info->region[n].user_priority_num) {
4706 info->region[i].user_priority[j] = tmp;
4707 info->region[i].user_priority_num++;
4710 j = info->region[i].flowtype_num;
4711 tmp = conf_info->region[n].hw_flowtype[0];
4712 if (conf_info->region[n].flowtype_num) {
4713 info->region[i].hw_flowtype[j] = tmp;
4714 info->region[i].flowtype_num++;
4719 rss_config->queue_region_conf = TRUE;
4723 * Return function if this flow is used for queue region configuration
4725 if (rss_config->queue_region_conf)
4728 if (!rss || !rss->queue_num) {
4729 rte_flow_error_set(error, EINVAL,
4730 RTE_FLOW_ERROR_TYPE_ACTION,
4736 for (n = 0; n < rss->queue_num; n++) {
4737 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4738 rte_flow_error_set(error, EINVAL,
4739 RTE_FLOW_ERROR_TYPE_ACTION,
4741 "queue id > max number of queues");
4746 if (rss_info->conf.queue_num) {
4747 rte_flow_error_set(error, EINVAL,
4748 RTE_FLOW_ERROR_TYPE_ACTION,
4750 "rss only allow one valid rule");
4754 /* Parse RSS related parameters from configuration */
4755 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4756 return rte_flow_error_set
4757 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4758 "non-default RSS hash functions are not supported");
4760 return rte_flow_error_set
4761 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4762 "a nonzero RSS encapsulation level is not supported");
4763 if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4764 return rte_flow_error_set
4765 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4766 "RSS hash key too large");
4767 if (rss->queue_num > RTE_DIM(rss_config->queue))
4768 return rte_flow_error_set
4769 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4770 "too many queues for RSS context");
4771 if (i40e_rss_conf_init(rss_config, rss))
4772 return rte_flow_error_set
4773 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4774 "RSS context initialization failure");
4778 /* check if the next not void action is END */
4779 NEXT_ITEM_OF_ACTION(act, actions, index);
4780 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4781 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4782 rte_flow_error_set(error, EINVAL,
4783 RTE_FLOW_ERROR_TYPE_ACTION,
4784 act, "Not supported action.");
4787 rss_config->queue_region_conf = FALSE;
4793 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4794 const struct rte_flow_attr *attr,
4795 const struct rte_flow_item pattern[],
4796 const struct rte_flow_action actions[],
4797 union i40e_filter_t *filter,
4798 struct rte_flow_error *error)
4801 struct i40e_queue_regions info;
4802 uint8_t action_flag = 0;
4804 memset(&info, 0, sizeof(struct i40e_queue_regions));
4806 ret = i40e_flow_parse_rss_pattern(dev, pattern,
4807 error, &action_flag, &info);
4811 ret = i40e_flow_parse_rss_action(dev, actions, error,
4812 action_flag, &info, filter);
4816 ret = i40e_flow_parse_attr(attr, error);
4820 cons_filter_type = RTE_ETH_FILTER_HASH;
4826 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4827 struct i40e_rte_flow_rss_conf *conf)
4829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4830 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833 if (conf->queue_region_conf) {
4834 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4835 conf->queue_region_conf = 0;
4837 ret = i40e_config_rss_filter(pf, conf, 1);
4843 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4844 struct i40e_rte_flow_rss_conf *conf)
4846 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4847 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4851 i40e_config_rss_filter(pf, conf, 0);
4856 i40e_flow_validate(struct rte_eth_dev *dev,
4857 const struct rte_flow_attr *attr,
4858 const struct rte_flow_item pattern[],
4859 const struct rte_flow_action actions[],
4860 struct rte_flow_error *error)
4862 struct rte_flow_item *items; /* internal pattern w/o VOID items */
4863 parse_filter_t parse_filter;
4864 uint32_t item_num = 0; /* non-void item number of pattern*/
4867 int ret = I40E_NOT_SUPPORTED;
4870 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4871 NULL, "NULL pattern.");
4876 rte_flow_error_set(error, EINVAL,
4877 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4878 NULL, "NULL action.");
4883 rte_flow_error_set(error, EINVAL,
4884 RTE_FLOW_ERROR_TYPE_ATTR,
4885 NULL, "NULL attribute.");
4889 memset(&cons_filter, 0, sizeof(cons_filter));
4891 /* Get the non-void item of action */
4892 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4895 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4896 ret = i40e_parse_rss_filter(dev, attr, pattern,
4897 actions, &cons_filter, error);
4902 /* Get the non-void item number of pattern */
4903 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4904 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4910 items = rte_zmalloc("i40e_pattern",
4911 item_num * sizeof(struct rte_flow_item), 0);
4913 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4914 NULL, "No memory for PMD internal items.");
4918 i40e_pattern_skip_void_item(items, pattern);
4922 parse_filter = i40e_find_parse_filter_func(items, &i);
4923 if (!parse_filter && !flag) {
4924 rte_flow_error_set(error, EINVAL,
4925 RTE_FLOW_ERROR_TYPE_ITEM,
4926 pattern, "Unsupported pattern");
4931 ret = parse_filter(dev, attr, items, actions,
4932 error, &cons_filter);
4934 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4941 static struct rte_flow *
4942 i40e_flow_create(struct rte_eth_dev *dev,
4943 const struct rte_flow_attr *attr,
4944 const struct rte_flow_item pattern[],
4945 const struct rte_flow_action actions[],
4946 struct rte_flow_error *error)
4948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4949 struct rte_flow *flow;
4952 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4954 rte_flow_error_set(error, ENOMEM,
4955 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4956 "Failed to allocate memory");
4960 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4964 switch (cons_filter_type) {
4965 case RTE_ETH_FILTER_ETHERTYPE:
4966 ret = i40e_ethertype_filter_set(pf,
4967 &cons_filter.ethertype_filter, 1);
4970 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4971 i40e_ethertype_filter_list);
4973 case RTE_ETH_FILTER_FDIR:
4974 ret = i40e_flow_add_del_fdir_filter(dev,
4975 &cons_filter.fdir_filter, 1);
4978 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4979 i40e_fdir_filter_list);
4981 case RTE_ETH_FILTER_TUNNEL:
4982 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4983 &cons_filter.consistent_tunnel_filter, 1);
4986 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4987 i40e_tunnel_filter_list);
4989 case RTE_ETH_FILTER_HASH:
4990 ret = i40e_config_rss_filter_set(dev,
4991 &cons_filter.rss_conf);
4994 flow->rule = &pf->rss_info;
5000 flow->filter_type = cons_filter_type;
5001 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
5005 rte_flow_error_set(error, -ret,
5006 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5007 "Failed to create flow.");
5013 i40e_flow_destroy(struct rte_eth_dev *dev,
5014 struct rte_flow *flow,
5015 struct rte_flow_error *error)
5017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5018 enum rte_filter_type filter_type = flow->filter_type;
5021 switch (filter_type) {
5022 case RTE_ETH_FILTER_ETHERTYPE:
5023 ret = i40e_flow_destroy_ethertype_filter(pf,
5024 (struct i40e_ethertype_filter *)flow->rule);
5026 case RTE_ETH_FILTER_TUNNEL:
5027 ret = i40e_flow_destroy_tunnel_filter(pf,
5028 (struct i40e_tunnel_filter *)flow->rule);
5030 case RTE_ETH_FILTER_FDIR:
5031 ret = i40e_flow_add_del_fdir_filter(dev,
5032 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
5034 /* If the last flow is destroyed, disable fdir. */
5035 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) {
5036 i40e_fdir_teardown(pf);
5037 dev->data->dev_conf.fdir_conf.mode =
5039 i40e_fdir_rx_proc_enable(dev, 0);
5042 case RTE_ETH_FILTER_HASH:
5043 ret = i40e_config_rss_filter_del(dev,
5044 (struct i40e_rte_flow_rss_conf *)flow->rule);
5047 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5054 TAILQ_REMOVE(&pf->flow_list, flow, node);
5057 rte_flow_error_set(error, -ret,
5058 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5059 "Failed to destroy flow.");
5065 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
5066 struct i40e_ethertype_filter *filter)
5068 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5069 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
5070 struct i40e_ethertype_filter *node;
5071 struct i40e_control_filter_stats stats;
5075 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5076 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5077 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5078 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5079 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5081 memset(&stats, 0, sizeof(stats));
5082 ret = i40e_aq_add_rem_control_packet_filter(hw,
5083 filter->input.mac_addr.addr_bytes,
5084 filter->input.ether_type,
5085 flags, pf->main_vsi->seid,
5086 filter->queue, 0, &stats, NULL);
5090 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
5094 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
5100 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
5101 struct i40e_tunnel_filter *filter)
5103 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5104 struct i40e_vsi *vsi;
5105 struct i40e_pf_vf *vf;
5106 struct i40e_aqc_cloud_filters_element_bb cld_filter;
5107 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
5108 struct i40e_tunnel_filter *node;
5109 bool big_buffer = 0;
5112 memset(&cld_filter, 0, sizeof(cld_filter));
5113 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
5114 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
5115 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
5116 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
5117 cld_filter.element.inner_vlan = filter->input.inner_vlan;
5118 cld_filter.element.flags = filter->input.flags;
5119 cld_filter.element.tenant_id = filter->input.tenant_id;
5120 cld_filter.element.queue_number = filter->queue;
5121 rte_memcpy(cld_filter.general_fields,
5122 filter->input.general_fields,
5123 sizeof(cld_filter.general_fields));
5125 if (!filter->is_to_vf)
5128 vf = &pf->vfs[filter->vf_id];
5132 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
5133 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
5134 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
5135 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
5136 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
5137 I40E_AQC_ADD_CLOUD_FILTER_0X10))
5141 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
5144 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
5145 &cld_filter.element, 1);
5149 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
5153 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
5159 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
5161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5164 ret = i40e_flow_flush_fdir_filter(pf);
5166 rte_flow_error_set(error, -ret,
5167 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5168 "Failed to flush FDIR flows.");
5172 ret = i40e_flow_flush_ethertype_filter(pf);
5174 rte_flow_error_set(error, -ret,
5175 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5176 "Failed to ethertype flush flows.");
5180 ret = i40e_flow_flush_tunnel_filter(pf);
5182 rte_flow_error_set(error, -ret,
5183 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5184 "Failed to flush tunnel flows.");
5188 ret = i40e_flow_flush_rss_filter(dev);
5190 rte_flow_error_set(error, -ret,
5191 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5192 "Failed to flush rss flows.");
5196 /* Disable FDIR processing as all FDIR rules are now flushed */
5197 i40e_fdir_rx_proc_enable(dev, 0);
5203 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
5205 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5206 struct i40e_fdir_info *fdir_info = &pf->fdir;
5207 struct i40e_fdir_filter *fdir_filter;
5208 enum i40e_filter_pctype pctype;
5209 struct rte_flow *flow;
5213 ret = i40e_fdir_flush(dev);
5215 /* Delete FDIR filters in FDIR list. */
5216 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
5217 ret = i40e_sw_fdir_filter_del(pf,
5218 &fdir_filter->fdir.input);
5223 /* Delete FDIR flows in flow list. */
5224 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5225 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
5226 TAILQ_REMOVE(&pf->flow_list, flow, node);
5231 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5232 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
5233 pf->fdir.inset_flag[pctype] = 0;
5236 i40e_fdir_teardown(pf);
5241 /* Flush all ethertype filters */
5243 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
5245 struct i40e_ethertype_filter_list
5246 *ethertype_list = &pf->ethertype.ethertype_list;
5247 struct i40e_ethertype_filter *filter;
5248 struct rte_flow *flow;
5252 while ((filter = TAILQ_FIRST(ethertype_list))) {
5253 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
5258 /* Delete ethertype flows in flow list. */
5259 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5260 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
5261 TAILQ_REMOVE(&pf->flow_list, flow, node);
5269 /* Flush all tunnel filters */
5271 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5273 struct i40e_tunnel_filter_list
5274 *tunnel_list = &pf->tunnel.tunnel_list;
5275 struct i40e_tunnel_filter *filter;
5276 struct rte_flow *flow;
5280 while ((filter = TAILQ_FIRST(tunnel_list))) {
5281 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5286 /* Delete tunnel flows in flow list. */
5287 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5288 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5289 TAILQ_REMOVE(&pf->flow_list, flow, node);
5297 /* remove the rss filter */
5299 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5302 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
5303 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5304 int32_t ret = -EINVAL;
5306 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5308 if (rss_info->conf.queue_num)
5309 ret = i40e_config_rss_filter(pf, rss_info, FALSE);