4 * Copyright (c) 2016-2017 Intel Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Intel Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/queue.h>
41 #include <rte_ether.h>
42 #include <rte_ethdev.h>
44 #include <rte_memzone.h>
45 #include <rte_malloc.h>
46 #include <rte_eth_ctrl.h>
47 #include <rte_tailq.h>
48 #include <rte_flow_driver.h>
50 #include "i40e_logs.h"
51 #include "base/i40e_type.h"
52 #include "base/i40e_prototype.h"
53 #include "i40e_ethdev.h"
55 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
56 #define I40E_IPV6_FRAG_HEADER 44
57 #define I40E_TENANT_ARRAY_NUM 3
58 #define I40E_TCI_MASK 0xFFFF
60 static int i40e_flow_validate(struct rte_eth_dev *dev,
61 const struct rte_flow_attr *attr,
62 const struct rte_flow_item pattern[],
63 const struct rte_flow_action actions[],
64 struct rte_flow_error *error);
65 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
66 const struct rte_flow_attr *attr,
67 const struct rte_flow_item pattern[],
68 const struct rte_flow_action actions[],
69 struct rte_flow_error *error);
70 static int i40e_flow_destroy(struct rte_eth_dev *dev,
71 struct rte_flow *flow,
72 struct rte_flow_error *error);
73 static int i40e_flow_flush(struct rte_eth_dev *dev,
74 struct rte_flow_error *error);
76 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
77 const struct rte_flow_item *pattern,
78 struct rte_flow_error *error,
79 struct rte_eth_ethertype_filter *filter);
80 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
81 const struct rte_flow_action *actions,
82 struct rte_flow_error *error,
83 struct rte_eth_ethertype_filter *filter);
84 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
85 const struct rte_flow_item *pattern,
86 struct rte_flow_error *error,
87 struct rte_eth_fdir_filter *filter);
88 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
89 const struct rte_flow_action *actions,
90 struct rte_flow_error *error,
91 struct rte_eth_fdir_filter *filter);
92 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
93 const struct rte_flow_action *actions,
94 struct rte_flow_error *error,
95 struct i40e_tunnel_filter_conf *filter);
96 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
97 struct rte_flow_error *error);
98 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
99 const struct rte_flow_attr *attr,
100 const struct rte_flow_item pattern[],
101 const struct rte_flow_action actions[],
102 struct rte_flow_error *error,
103 union i40e_filter_t *filter);
104 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
105 const struct rte_flow_attr *attr,
106 const struct rte_flow_item pattern[],
107 const struct rte_flow_action actions[],
108 struct rte_flow_error *error,
109 union i40e_filter_t *filter);
110 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
111 const struct rte_flow_attr *attr,
112 const struct rte_flow_item pattern[],
113 const struct rte_flow_action actions[],
114 struct rte_flow_error *error,
115 union i40e_filter_t *filter);
116 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
117 const struct rte_flow_attr *attr,
118 const struct rte_flow_item pattern[],
119 const struct rte_flow_action actions[],
120 struct rte_flow_error *error,
121 union i40e_filter_t *filter);
122 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
123 const struct rte_flow_attr *attr,
124 const struct rte_flow_item pattern[],
125 const struct rte_flow_action actions[],
126 struct rte_flow_error *error,
127 union i40e_filter_t *filter);
128 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
129 struct i40e_ethertype_filter *filter);
130 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
131 struct i40e_tunnel_filter *filter);
132 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
133 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
134 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
136 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
137 const struct rte_flow_attr *attr,
138 const struct rte_flow_item pattern[],
139 const struct rte_flow_action actions[],
140 struct rte_flow_error *error,
141 union i40e_filter_t *filter);
143 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
144 const struct rte_flow_item *pattern,
145 struct rte_flow_error *error,
146 struct i40e_tunnel_filter_conf *filter);
148 const struct rte_flow_ops i40e_flow_ops = {
149 .validate = i40e_flow_validate,
150 .create = i40e_flow_create,
151 .destroy = i40e_flow_destroy,
152 .flush = i40e_flow_flush,
155 union i40e_filter_t cons_filter;
156 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
158 /* Pattern matched ethertype filter */
159 static enum rte_flow_item_type pattern_ethertype[] = {
160 RTE_FLOW_ITEM_TYPE_ETH,
161 RTE_FLOW_ITEM_TYPE_END,
164 /* Pattern matched flow director filter */
165 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
166 RTE_FLOW_ITEM_TYPE_ETH,
167 RTE_FLOW_ITEM_TYPE_IPV4,
168 RTE_FLOW_ITEM_TYPE_END,
171 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
172 RTE_FLOW_ITEM_TYPE_ETH,
173 RTE_FLOW_ITEM_TYPE_IPV4,
174 RTE_FLOW_ITEM_TYPE_UDP,
175 RTE_FLOW_ITEM_TYPE_END,
178 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
179 RTE_FLOW_ITEM_TYPE_ETH,
180 RTE_FLOW_ITEM_TYPE_IPV4,
181 RTE_FLOW_ITEM_TYPE_TCP,
182 RTE_FLOW_ITEM_TYPE_END,
185 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
186 RTE_FLOW_ITEM_TYPE_ETH,
187 RTE_FLOW_ITEM_TYPE_IPV4,
188 RTE_FLOW_ITEM_TYPE_SCTP,
189 RTE_FLOW_ITEM_TYPE_END,
192 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
193 RTE_FLOW_ITEM_TYPE_ETH,
194 RTE_FLOW_ITEM_TYPE_IPV6,
195 RTE_FLOW_ITEM_TYPE_END,
198 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
199 RTE_FLOW_ITEM_TYPE_ETH,
200 RTE_FLOW_ITEM_TYPE_IPV6,
201 RTE_FLOW_ITEM_TYPE_UDP,
202 RTE_FLOW_ITEM_TYPE_END,
205 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
206 RTE_FLOW_ITEM_TYPE_ETH,
207 RTE_FLOW_ITEM_TYPE_IPV6,
208 RTE_FLOW_ITEM_TYPE_TCP,
209 RTE_FLOW_ITEM_TYPE_END,
212 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
213 RTE_FLOW_ITEM_TYPE_ETH,
214 RTE_FLOW_ITEM_TYPE_IPV6,
215 RTE_FLOW_ITEM_TYPE_SCTP,
216 RTE_FLOW_ITEM_TYPE_END,
219 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
220 RTE_FLOW_ITEM_TYPE_ETH,
221 RTE_FLOW_ITEM_TYPE_RAW,
222 RTE_FLOW_ITEM_TYPE_END,
225 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
226 RTE_FLOW_ITEM_TYPE_ETH,
227 RTE_FLOW_ITEM_TYPE_RAW,
228 RTE_FLOW_ITEM_TYPE_RAW,
229 RTE_FLOW_ITEM_TYPE_END,
232 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
233 RTE_FLOW_ITEM_TYPE_ETH,
234 RTE_FLOW_ITEM_TYPE_RAW,
235 RTE_FLOW_ITEM_TYPE_RAW,
236 RTE_FLOW_ITEM_TYPE_RAW,
237 RTE_FLOW_ITEM_TYPE_END,
240 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
241 RTE_FLOW_ITEM_TYPE_ETH,
242 RTE_FLOW_ITEM_TYPE_IPV4,
243 RTE_FLOW_ITEM_TYPE_RAW,
244 RTE_FLOW_ITEM_TYPE_END,
247 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
248 RTE_FLOW_ITEM_TYPE_ETH,
249 RTE_FLOW_ITEM_TYPE_IPV4,
250 RTE_FLOW_ITEM_TYPE_RAW,
251 RTE_FLOW_ITEM_TYPE_RAW,
252 RTE_FLOW_ITEM_TYPE_END,
255 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
256 RTE_FLOW_ITEM_TYPE_ETH,
257 RTE_FLOW_ITEM_TYPE_IPV4,
258 RTE_FLOW_ITEM_TYPE_RAW,
259 RTE_FLOW_ITEM_TYPE_RAW,
260 RTE_FLOW_ITEM_TYPE_RAW,
261 RTE_FLOW_ITEM_TYPE_END,
264 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
265 RTE_FLOW_ITEM_TYPE_ETH,
266 RTE_FLOW_ITEM_TYPE_IPV4,
267 RTE_FLOW_ITEM_TYPE_UDP,
268 RTE_FLOW_ITEM_TYPE_RAW,
269 RTE_FLOW_ITEM_TYPE_END,
272 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
273 RTE_FLOW_ITEM_TYPE_ETH,
274 RTE_FLOW_ITEM_TYPE_IPV4,
275 RTE_FLOW_ITEM_TYPE_UDP,
276 RTE_FLOW_ITEM_TYPE_RAW,
277 RTE_FLOW_ITEM_TYPE_RAW,
278 RTE_FLOW_ITEM_TYPE_END,
281 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
282 RTE_FLOW_ITEM_TYPE_ETH,
283 RTE_FLOW_ITEM_TYPE_IPV4,
284 RTE_FLOW_ITEM_TYPE_UDP,
285 RTE_FLOW_ITEM_TYPE_RAW,
286 RTE_FLOW_ITEM_TYPE_RAW,
287 RTE_FLOW_ITEM_TYPE_RAW,
288 RTE_FLOW_ITEM_TYPE_END,
291 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
292 RTE_FLOW_ITEM_TYPE_ETH,
293 RTE_FLOW_ITEM_TYPE_IPV4,
294 RTE_FLOW_ITEM_TYPE_TCP,
295 RTE_FLOW_ITEM_TYPE_RAW,
296 RTE_FLOW_ITEM_TYPE_END,
299 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
300 RTE_FLOW_ITEM_TYPE_ETH,
301 RTE_FLOW_ITEM_TYPE_IPV4,
302 RTE_FLOW_ITEM_TYPE_TCP,
303 RTE_FLOW_ITEM_TYPE_RAW,
304 RTE_FLOW_ITEM_TYPE_RAW,
305 RTE_FLOW_ITEM_TYPE_END,
308 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
309 RTE_FLOW_ITEM_TYPE_ETH,
310 RTE_FLOW_ITEM_TYPE_IPV4,
311 RTE_FLOW_ITEM_TYPE_TCP,
312 RTE_FLOW_ITEM_TYPE_RAW,
313 RTE_FLOW_ITEM_TYPE_RAW,
314 RTE_FLOW_ITEM_TYPE_RAW,
315 RTE_FLOW_ITEM_TYPE_END,
318 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
319 RTE_FLOW_ITEM_TYPE_ETH,
320 RTE_FLOW_ITEM_TYPE_IPV4,
321 RTE_FLOW_ITEM_TYPE_SCTP,
322 RTE_FLOW_ITEM_TYPE_RAW,
323 RTE_FLOW_ITEM_TYPE_END,
326 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
327 RTE_FLOW_ITEM_TYPE_ETH,
328 RTE_FLOW_ITEM_TYPE_IPV4,
329 RTE_FLOW_ITEM_TYPE_SCTP,
330 RTE_FLOW_ITEM_TYPE_RAW,
331 RTE_FLOW_ITEM_TYPE_RAW,
332 RTE_FLOW_ITEM_TYPE_END,
335 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
336 RTE_FLOW_ITEM_TYPE_ETH,
337 RTE_FLOW_ITEM_TYPE_IPV4,
338 RTE_FLOW_ITEM_TYPE_SCTP,
339 RTE_FLOW_ITEM_TYPE_RAW,
340 RTE_FLOW_ITEM_TYPE_RAW,
341 RTE_FLOW_ITEM_TYPE_RAW,
342 RTE_FLOW_ITEM_TYPE_END,
345 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
346 RTE_FLOW_ITEM_TYPE_ETH,
347 RTE_FLOW_ITEM_TYPE_IPV6,
348 RTE_FLOW_ITEM_TYPE_RAW,
349 RTE_FLOW_ITEM_TYPE_END,
352 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
353 RTE_FLOW_ITEM_TYPE_ETH,
354 RTE_FLOW_ITEM_TYPE_IPV6,
355 RTE_FLOW_ITEM_TYPE_RAW,
356 RTE_FLOW_ITEM_TYPE_RAW,
357 RTE_FLOW_ITEM_TYPE_END,
360 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
361 RTE_FLOW_ITEM_TYPE_ETH,
362 RTE_FLOW_ITEM_TYPE_IPV6,
363 RTE_FLOW_ITEM_TYPE_RAW,
364 RTE_FLOW_ITEM_TYPE_RAW,
365 RTE_FLOW_ITEM_TYPE_RAW,
366 RTE_FLOW_ITEM_TYPE_END,
369 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
370 RTE_FLOW_ITEM_TYPE_ETH,
371 RTE_FLOW_ITEM_TYPE_IPV6,
372 RTE_FLOW_ITEM_TYPE_UDP,
373 RTE_FLOW_ITEM_TYPE_RAW,
374 RTE_FLOW_ITEM_TYPE_END,
377 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
378 RTE_FLOW_ITEM_TYPE_ETH,
379 RTE_FLOW_ITEM_TYPE_IPV6,
380 RTE_FLOW_ITEM_TYPE_UDP,
381 RTE_FLOW_ITEM_TYPE_RAW,
382 RTE_FLOW_ITEM_TYPE_RAW,
383 RTE_FLOW_ITEM_TYPE_END,
386 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
387 RTE_FLOW_ITEM_TYPE_ETH,
388 RTE_FLOW_ITEM_TYPE_IPV6,
389 RTE_FLOW_ITEM_TYPE_UDP,
390 RTE_FLOW_ITEM_TYPE_RAW,
391 RTE_FLOW_ITEM_TYPE_RAW,
392 RTE_FLOW_ITEM_TYPE_RAW,
393 RTE_FLOW_ITEM_TYPE_END,
396 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
397 RTE_FLOW_ITEM_TYPE_ETH,
398 RTE_FLOW_ITEM_TYPE_IPV6,
399 RTE_FLOW_ITEM_TYPE_TCP,
400 RTE_FLOW_ITEM_TYPE_RAW,
401 RTE_FLOW_ITEM_TYPE_END,
404 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
405 RTE_FLOW_ITEM_TYPE_ETH,
406 RTE_FLOW_ITEM_TYPE_IPV6,
407 RTE_FLOW_ITEM_TYPE_TCP,
408 RTE_FLOW_ITEM_TYPE_RAW,
409 RTE_FLOW_ITEM_TYPE_RAW,
410 RTE_FLOW_ITEM_TYPE_END,
413 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
414 RTE_FLOW_ITEM_TYPE_ETH,
415 RTE_FLOW_ITEM_TYPE_IPV6,
416 RTE_FLOW_ITEM_TYPE_TCP,
417 RTE_FLOW_ITEM_TYPE_RAW,
418 RTE_FLOW_ITEM_TYPE_RAW,
419 RTE_FLOW_ITEM_TYPE_RAW,
420 RTE_FLOW_ITEM_TYPE_END,
423 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
424 RTE_FLOW_ITEM_TYPE_ETH,
425 RTE_FLOW_ITEM_TYPE_IPV6,
426 RTE_FLOW_ITEM_TYPE_SCTP,
427 RTE_FLOW_ITEM_TYPE_RAW,
428 RTE_FLOW_ITEM_TYPE_END,
431 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
432 RTE_FLOW_ITEM_TYPE_ETH,
433 RTE_FLOW_ITEM_TYPE_IPV6,
434 RTE_FLOW_ITEM_TYPE_SCTP,
435 RTE_FLOW_ITEM_TYPE_RAW,
436 RTE_FLOW_ITEM_TYPE_RAW,
437 RTE_FLOW_ITEM_TYPE_END,
440 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
441 RTE_FLOW_ITEM_TYPE_ETH,
442 RTE_FLOW_ITEM_TYPE_IPV6,
443 RTE_FLOW_ITEM_TYPE_SCTP,
444 RTE_FLOW_ITEM_TYPE_RAW,
445 RTE_FLOW_ITEM_TYPE_RAW,
446 RTE_FLOW_ITEM_TYPE_RAW,
447 RTE_FLOW_ITEM_TYPE_END,
450 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
451 RTE_FLOW_ITEM_TYPE_ETH,
452 RTE_FLOW_ITEM_TYPE_VLAN,
453 RTE_FLOW_ITEM_TYPE_END,
456 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
457 RTE_FLOW_ITEM_TYPE_ETH,
458 RTE_FLOW_ITEM_TYPE_VLAN,
459 RTE_FLOW_ITEM_TYPE_IPV4,
460 RTE_FLOW_ITEM_TYPE_END,
463 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
464 RTE_FLOW_ITEM_TYPE_ETH,
465 RTE_FLOW_ITEM_TYPE_VLAN,
466 RTE_FLOW_ITEM_TYPE_IPV4,
467 RTE_FLOW_ITEM_TYPE_UDP,
468 RTE_FLOW_ITEM_TYPE_END,
471 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
472 RTE_FLOW_ITEM_TYPE_ETH,
473 RTE_FLOW_ITEM_TYPE_VLAN,
474 RTE_FLOW_ITEM_TYPE_IPV4,
475 RTE_FLOW_ITEM_TYPE_TCP,
476 RTE_FLOW_ITEM_TYPE_END,
479 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
480 RTE_FLOW_ITEM_TYPE_ETH,
481 RTE_FLOW_ITEM_TYPE_VLAN,
482 RTE_FLOW_ITEM_TYPE_IPV4,
483 RTE_FLOW_ITEM_TYPE_SCTP,
484 RTE_FLOW_ITEM_TYPE_END,
487 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
488 RTE_FLOW_ITEM_TYPE_ETH,
489 RTE_FLOW_ITEM_TYPE_VLAN,
490 RTE_FLOW_ITEM_TYPE_IPV6,
491 RTE_FLOW_ITEM_TYPE_END,
494 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
495 RTE_FLOW_ITEM_TYPE_ETH,
496 RTE_FLOW_ITEM_TYPE_VLAN,
497 RTE_FLOW_ITEM_TYPE_IPV6,
498 RTE_FLOW_ITEM_TYPE_UDP,
499 RTE_FLOW_ITEM_TYPE_END,
502 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
503 RTE_FLOW_ITEM_TYPE_ETH,
504 RTE_FLOW_ITEM_TYPE_VLAN,
505 RTE_FLOW_ITEM_TYPE_IPV6,
506 RTE_FLOW_ITEM_TYPE_TCP,
507 RTE_FLOW_ITEM_TYPE_END,
510 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
511 RTE_FLOW_ITEM_TYPE_ETH,
512 RTE_FLOW_ITEM_TYPE_VLAN,
513 RTE_FLOW_ITEM_TYPE_IPV6,
514 RTE_FLOW_ITEM_TYPE_SCTP,
515 RTE_FLOW_ITEM_TYPE_END,
518 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
519 RTE_FLOW_ITEM_TYPE_ETH,
520 RTE_FLOW_ITEM_TYPE_VLAN,
521 RTE_FLOW_ITEM_TYPE_RAW,
522 RTE_FLOW_ITEM_TYPE_END,
525 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
526 RTE_FLOW_ITEM_TYPE_ETH,
527 RTE_FLOW_ITEM_TYPE_VLAN,
528 RTE_FLOW_ITEM_TYPE_RAW,
529 RTE_FLOW_ITEM_TYPE_RAW,
530 RTE_FLOW_ITEM_TYPE_END,
533 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
534 RTE_FLOW_ITEM_TYPE_ETH,
535 RTE_FLOW_ITEM_TYPE_VLAN,
536 RTE_FLOW_ITEM_TYPE_RAW,
537 RTE_FLOW_ITEM_TYPE_RAW,
538 RTE_FLOW_ITEM_TYPE_RAW,
539 RTE_FLOW_ITEM_TYPE_END,
542 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
543 RTE_FLOW_ITEM_TYPE_ETH,
544 RTE_FLOW_ITEM_TYPE_VLAN,
545 RTE_FLOW_ITEM_TYPE_IPV4,
546 RTE_FLOW_ITEM_TYPE_RAW,
547 RTE_FLOW_ITEM_TYPE_END,
550 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
551 RTE_FLOW_ITEM_TYPE_ETH,
552 RTE_FLOW_ITEM_TYPE_VLAN,
553 RTE_FLOW_ITEM_TYPE_IPV4,
554 RTE_FLOW_ITEM_TYPE_RAW,
555 RTE_FLOW_ITEM_TYPE_RAW,
556 RTE_FLOW_ITEM_TYPE_END,
559 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
560 RTE_FLOW_ITEM_TYPE_ETH,
561 RTE_FLOW_ITEM_TYPE_VLAN,
562 RTE_FLOW_ITEM_TYPE_IPV4,
563 RTE_FLOW_ITEM_TYPE_RAW,
564 RTE_FLOW_ITEM_TYPE_RAW,
565 RTE_FLOW_ITEM_TYPE_RAW,
566 RTE_FLOW_ITEM_TYPE_END,
569 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
570 RTE_FLOW_ITEM_TYPE_ETH,
571 RTE_FLOW_ITEM_TYPE_VLAN,
572 RTE_FLOW_ITEM_TYPE_IPV4,
573 RTE_FLOW_ITEM_TYPE_UDP,
574 RTE_FLOW_ITEM_TYPE_RAW,
575 RTE_FLOW_ITEM_TYPE_END,
578 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
579 RTE_FLOW_ITEM_TYPE_ETH,
580 RTE_FLOW_ITEM_TYPE_VLAN,
581 RTE_FLOW_ITEM_TYPE_IPV4,
582 RTE_FLOW_ITEM_TYPE_UDP,
583 RTE_FLOW_ITEM_TYPE_RAW,
584 RTE_FLOW_ITEM_TYPE_RAW,
585 RTE_FLOW_ITEM_TYPE_END,
588 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
589 RTE_FLOW_ITEM_TYPE_ETH,
590 RTE_FLOW_ITEM_TYPE_VLAN,
591 RTE_FLOW_ITEM_TYPE_IPV4,
592 RTE_FLOW_ITEM_TYPE_UDP,
593 RTE_FLOW_ITEM_TYPE_RAW,
594 RTE_FLOW_ITEM_TYPE_RAW,
595 RTE_FLOW_ITEM_TYPE_RAW,
596 RTE_FLOW_ITEM_TYPE_END,
599 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
600 RTE_FLOW_ITEM_TYPE_ETH,
601 RTE_FLOW_ITEM_TYPE_VLAN,
602 RTE_FLOW_ITEM_TYPE_IPV4,
603 RTE_FLOW_ITEM_TYPE_TCP,
604 RTE_FLOW_ITEM_TYPE_RAW,
605 RTE_FLOW_ITEM_TYPE_END,
608 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
609 RTE_FLOW_ITEM_TYPE_ETH,
610 RTE_FLOW_ITEM_TYPE_VLAN,
611 RTE_FLOW_ITEM_TYPE_IPV4,
612 RTE_FLOW_ITEM_TYPE_TCP,
613 RTE_FLOW_ITEM_TYPE_RAW,
614 RTE_FLOW_ITEM_TYPE_RAW,
615 RTE_FLOW_ITEM_TYPE_END,
618 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
619 RTE_FLOW_ITEM_TYPE_ETH,
620 RTE_FLOW_ITEM_TYPE_VLAN,
621 RTE_FLOW_ITEM_TYPE_IPV4,
622 RTE_FLOW_ITEM_TYPE_TCP,
623 RTE_FLOW_ITEM_TYPE_RAW,
624 RTE_FLOW_ITEM_TYPE_RAW,
625 RTE_FLOW_ITEM_TYPE_RAW,
626 RTE_FLOW_ITEM_TYPE_END,
629 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
630 RTE_FLOW_ITEM_TYPE_ETH,
631 RTE_FLOW_ITEM_TYPE_VLAN,
632 RTE_FLOW_ITEM_TYPE_IPV4,
633 RTE_FLOW_ITEM_TYPE_SCTP,
634 RTE_FLOW_ITEM_TYPE_RAW,
635 RTE_FLOW_ITEM_TYPE_END,
638 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
639 RTE_FLOW_ITEM_TYPE_ETH,
640 RTE_FLOW_ITEM_TYPE_VLAN,
641 RTE_FLOW_ITEM_TYPE_IPV4,
642 RTE_FLOW_ITEM_TYPE_SCTP,
643 RTE_FLOW_ITEM_TYPE_RAW,
644 RTE_FLOW_ITEM_TYPE_RAW,
645 RTE_FLOW_ITEM_TYPE_END,
648 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
649 RTE_FLOW_ITEM_TYPE_ETH,
650 RTE_FLOW_ITEM_TYPE_VLAN,
651 RTE_FLOW_ITEM_TYPE_IPV4,
652 RTE_FLOW_ITEM_TYPE_SCTP,
653 RTE_FLOW_ITEM_TYPE_RAW,
654 RTE_FLOW_ITEM_TYPE_RAW,
655 RTE_FLOW_ITEM_TYPE_RAW,
656 RTE_FLOW_ITEM_TYPE_END,
659 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
660 RTE_FLOW_ITEM_TYPE_ETH,
661 RTE_FLOW_ITEM_TYPE_VLAN,
662 RTE_FLOW_ITEM_TYPE_IPV6,
663 RTE_FLOW_ITEM_TYPE_RAW,
664 RTE_FLOW_ITEM_TYPE_END,
667 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
668 RTE_FLOW_ITEM_TYPE_ETH,
669 RTE_FLOW_ITEM_TYPE_VLAN,
670 RTE_FLOW_ITEM_TYPE_IPV6,
671 RTE_FLOW_ITEM_TYPE_RAW,
672 RTE_FLOW_ITEM_TYPE_RAW,
673 RTE_FLOW_ITEM_TYPE_END,
676 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
677 RTE_FLOW_ITEM_TYPE_ETH,
678 RTE_FLOW_ITEM_TYPE_VLAN,
679 RTE_FLOW_ITEM_TYPE_IPV6,
680 RTE_FLOW_ITEM_TYPE_RAW,
681 RTE_FLOW_ITEM_TYPE_RAW,
682 RTE_FLOW_ITEM_TYPE_RAW,
683 RTE_FLOW_ITEM_TYPE_END,
686 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
687 RTE_FLOW_ITEM_TYPE_ETH,
688 RTE_FLOW_ITEM_TYPE_VLAN,
689 RTE_FLOW_ITEM_TYPE_IPV6,
690 RTE_FLOW_ITEM_TYPE_UDP,
691 RTE_FLOW_ITEM_TYPE_RAW,
692 RTE_FLOW_ITEM_TYPE_END,
695 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
696 RTE_FLOW_ITEM_TYPE_ETH,
697 RTE_FLOW_ITEM_TYPE_VLAN,
698 RTE_FLOW_ITEM_TYPE_IPV6,
699 RTE_FLOW_ITEM_TYPE_UDP,
700 RTE_FLOW_ITEM_TYPE_RAW,
701 RTE_FLOW_ITEM_TYPE_RAW,
702 RTE_FLOW_ITEM_TYPE_END,
705 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
706 RTE_FLOW_ITEM_TYPE_ETH,
707 RTE_FLOW_ITEM_TYPE_VLAN,
708 RTE_FLOW_ITEM_TYPE_IPV6,
709 RTE_FLOW_ITEM_TYPE_UDP,
710 RTE_FLOW_ITEM_TYPE_RAW,
711 RTE_FLOW_ITEM_TYPE_RAW,
712 RTE_FLOW_ITEM_TYPE_RAW,
713 RTE_FLOW_ITEM_TYPE_END,
716 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
717 RTE_FLOW_ITEM_TYPE_ETH,
718 RTE_FLOW_ITEM_TYPE_VLAN,
719 RTE_FLOW_ITEM_TYPE_IPV6,
720 RTE_FLOW_ITEM_TYPE_TCP,
721 RTE_FLOW_ITEM_TYPE_RAW,
722 RTE_FLOW_ITEM_TYPE_END,
725 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
726 RTE_FLOW_ITEM_TYPE_ETH,
727 RTE_FLOW_ITEM_TYPE_VLAN,
728 RTE_FLOW_ITEM_TYPE_IPV6,
729 RTE_FLOW_ITEM_TYPE_TCP,
730 RTE_FLOW_ITEM_TYPE_RAW,
731 RTE_FLOW_ITEM_TYPE_RAW,
732 RTE_FLOW_ITEM_TYPE_END,
735 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
736 RTE_FLOW_ITEM_TYPE_ETH,
737 RTE_FLOW_ITEM_TYPE_VLAN,
738 RTE_FLOW_ITEM_TYPE_IPV6,
739 RTE_FLOW_ITEM_TYPE_TCP,
740 RTE_FLOW_ITEM_TYPE_RAW,
741 RTE_FLOW_ITEM_TYPE_RAW,
742 RTE_FLOW_ITEM_TYPE_RAW,
743 RTE_FLOW_ITEM_TYPE_END,
746 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
747 RTE_FLOW_ITEM_TYPE_ETH,
748 RTE_FLOW_ITEM_TYPE_VLAN,
749 RTE_FLOW_ITEM_TYPE_IPV6,
750 RTE_FLOW_ITEM_TYPE_SCTP,
751 RTE_FLOW_ITEM_TYPE_RAW,
752 RTE_FLOW_ITEM_TYPE_END,
755 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
756 RTE_FLOW_ITEM_TYPE_ETH,
757 RTE_FLOW_ITEM_TYPE_VLAN,
758 RTE_FLOW_ITEM_TYPE_IPV6,
759 RTE_FLOW_ITEM_TYPE_SCTP,
760 RTE_FLOW_ITEM_TYPE_RAW,
761 RTE_FLOW_ITEM_TYPE_RAW,
762 RTE_FLOW_ITEM_TYPE_END,
765 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
766 RTE_FLOW_ITEM_TYPE_ETH,
767 RTE_FLOW_ITEM_TYPE_VLAN,
768 RTE_FLOW_ITEM_TYPE_IPV6,
769 RTE_FLOW_ITEM_TYPE_SCTP,
770 RTE_FLOW_ITEM_TYPE_RAW,
771 RTE_FLOW_ITEM_TYPE_RAW,
772 RTE_FLOW_ITEM_TYPE_RAW,
773 RTE_FLOW_ITEM_TYPE_END,
776 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
777 RTE_FLOW_ITEM_TYPE_ETH,
778 RTE_FLOW_ITEM_TYPE_IPV4,
779 RTE_FLOW_ITEM_TYPE_VF,
780 RTE_FLOW_ITEM_TYPE_END,
783 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
784 RTE_FLOW_ITEM_TYPE_ETH,
785 RTE_FLOW_ITEM_TYPE_IPV4,
786 RTE_FLOW_ITEM_TYPE_UDP,
787 RTE_FLOW_ITEM_TYPE_VF,
788 RTE_FLOW_ITEM_TYPE_END,
791 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
792 RTE_FLOW_ITEM_TYPE_ETH,
793 RTE_FLOW_ITEM_TYPE_IPV4,
794 RTE_FLOW_ITEM_TYPE_TCP,
795 RTE_FLOW_ITEM_TYPE_VF,
796 RTE_FLOW_ITEM_TYPE_END,
799 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
800 RTE_FLOW_ITEM_TYPE_ETH,
801 RTE_FLOW_ITEM_TYPE_IPV4,
802 RTE_FLOW_ITEM_TYPE_SCTP,
803 RTE_FLOW_ITEM_TYPE_VF,
804 RTE_FLOW_ITEM_TYPE_END,
807 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
808 RTE_FLOW_ITEM_TYPE_ETH,
809 RTE_FLOW_ITEM_TYPE_IPV6,
810 RTE_FLOW_ITEM_TYPE_VF,
811 RTE_FLOW_ITEM_TYPE_END,
814 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
815 RTE_FLOW_ITEM_TYPE_ETH,
816 RTE_FLOW_ITEM_TYPE_IPV6,
817 RTE_FLOW_ITEM_TYPE_UDP,
818 RTE_FLOW_ITEM_TYPE_VF,
819 RTE_FLOW_ITEM_TYPE_END,
822 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
823 RTE_FLOW_ITEM_TYPE_ETH,
824 RTE_FLOW_ITEM_TYPE_IPV6,
825 RTE_FLOW_ITEM_TYPE_TCP,
826 RTE_FLOW_ITEM_TYPE_VF,
827 RTE_FLOW_ITEM_TYPE_END,
830 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
831 RTE_FLOW_ITEM_TYPE_ETH,
832 RTE_FLOW_ITEM_TYPE_IPV6,
833 RTE_FLOW_ITEM_TYPE_SCTP,
834 RTE_FLOW_ITEM_TYPE_VF,
835 RTE_FLOW_ITEM_TYPE_END,
838 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
839 RTE_FLOW_ITEM_TYPE_ETH,
840 RTE_FLOW_ITEM_TYPE_RAW,
841 RTE_FLOW_ITEM_TYPE_VF,
842 RTE_FLOW_ITEM_TYPE_END,
845 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
846 RTE_FLOW_ITEM_TYPE_ETH,
847 RTE_FLOW_ITEM_TYPE_RAW,
848 RTE_FLOW_ITEM_TYPE_RAW,
849 RTE_FLOW_ITEM_TYPE_VF,
850 RTE_FLOW_ITEM_TYPE_END,
853 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
854 RTE_FLOW_ITEM_TYPE_ETH,
855 RTE_FLOW_ITEM_TYPE_RAW,
856 RTE_FLOW_ITEM_TYPE_RAW,
857 RTE_FLOW_ITEM_TYPE_RAW,
858 RTE_FLOW_ITEM_TYPE_VF,
859 RTE_FLOW_ITEM_TYPE_END,
862 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
863 RTE_FLOW_ITEM_TYPE_ETH,
864 RTE_FLOW_ITEM_TYPE_IPV4,
865 RTE_FLOW_ITEM_TYPE_RAW,
866 RTE_FLOW_ITEM_TYPE_VF,
867 RTE_FLOW_ITEM_TYPE_END,
870 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
871 RTE_FLOW_ITEM_TYPE_ETH,
872 RTE_FLOW_ITEM_TYPE_IPV4,
873 RTE_FLOW_ITEM_TYPE_RAW,
874 RTE_FLOW_ITEM_TYPE_RAW,
875 RTE_FLOW_ITEM_TYPE_VF,
876 RTE_FLOW_ITEM_TYPE_END,
879 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
880 RTE_FLOW_ITEM_TYPE_ETH,
881 RTE_FLOW_ITEM_TYPE_IPV4,
882 RTE_FLOW_ITEM_TYPE_RAW,
883 RTE_FLOW_ITEM_TYPE_RAW,
884 RTE_FLOW_ITEM_TYPE_RAW,
885 RTE_FLOW_ITEM_TYPE_VF,
886 RTE_FLOW_ITEM_TYPE_END,
889 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
890 RTE_FLOW_ITEM_TYPE_ETH,
891 RTE_FLOW_ITEM_TYPE_IPV4,
892 RTE_FLOW_ITEM_TYPE_UDP,
893 RTE_FLOW_ITEM_TYPE_RAW,
894 RTE_FLOW_ITEM_TYPE_VF,
895 RTE_FLOW_ITEM_TYPE_END,
898 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
899 RTE_FLOW_ITEM_TYPE_ETH,
900 RTE_FLOW_ITEM_TYPE_IPV4,
901 RTE_FLOW_ITEM_TYPE_UDP,
902 RTE_FLOW_ITEM_TYPE_RAW,
903 RTE_FLOW_ITEM_TYPE_RAW,
904 RTE_FLOW_ITEM_TYPE_VF,
905 RTE_FLOW_ITEM_TYPE_END,
908 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
909 RTE_FLOW_ITEM_TYPE_ETH,
910 RTE_FLOW_ITEM_TYPE_IPV4,
911 RTE_FLOW_ITEM_TYPE_UDP,
912 RTE_FLOW_ITEM_TYPE_RAW,
913 RTE_FLOW_ITEM_TYPE_RAW,
914 RTE_FLOW_ITEM_TYPE_RAW,
915 RTE_FLOW_ITEM_TYPE_VF,
916 RTE_FLOW_ITEM_TYPE_END,
919 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
920 RTE_FLOW_ITEM_TYPE_ETH,
921 RTE_FLOW_ITEM_TYPE_IPV4,
922 RTE_FLOW_ITEM_TYPE_TCP,
923 RTE_FLOW_ITEM_TYPE_RAW,
924 RTE_FLOW_ITEM_TYPE_VF,
925 RTE_FLOW_ITEM_TYPE_END,
928 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
929 RTE_FLOW_ITEM_TYPE_ETH,
930 RTE_FLOW_ITEM_TYPE_IPV4,
931 RTE_FLOW_ITEM_TYPE_TCP,
932 RTE_FLOW_ITEM_TYPE_RAW,
933 RTE_FLOW_ITEM_TYPE_RAW,
934 RTE_FLOW_ITEM_TYPE_VF,
935 RTE_FLOW_ITEM_TYPE_END,
938 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
939 RTE_FLOW_ITEM_TYPE_ETH,
940 RTE_FLOW_ITEM_TYPE_IPV4,
941 RTE_FLOW_ITEM_TYPE_TCP,
942 RTE_FLOW_ITEM_TYPE_RAW,
943 RTE_FLOW_ITEM_TYPE_RAW,
944 RTE_FLOW_ITEM_TYPE_RAW,
945 RTE_FLOW_ITEM_TYPE_VF,
946 RTE_FLOW_ITEM_TYPE_END,
949 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
950 RTE_FLOW_ITEM_TYPE_ETH,
951 RTE_FLOW_ITEM_TYPE_IPV4,
952 RTE_FLOW_ITEM_TYPE_SCTP,
953 RTE_FLOW_ITEM_TYPE_RAW,
954 RTE_FLOW_ITEM_TYPE_VF,
955 RTE_FLOW_ITEM_TYPE_END,
958 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
959 RTE_FLOW_ITEM_TYPE_ETH,
960 RTE_FLOW_ITEM_TYPE_IPV4,
961 RTE_FLOW_ITEM_TYPE_SCTP,
962 RTE_FLOW_ITEM_TYPE_RAW,
963 RTE_FLOW_ITEM_TYPE_RAW,
964 RTE_FLOW_ITEM_TYPE_VF,
965 RTE_FLOW_ITEM_TYPE_END,
968 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
969 RTE_FLOW_ITEM_TYPE_ETH,
970 RTE_FLOW_ITEM_TYPE_IPV4,
971 RTE_FLOW_ITEM_TYPE_SCTP,
972 RTE_FLOW_ITEM_TYPE_RAW,
973 RTE_FLOW_ITEM_TYPE_RAW,
974 RTE_FLOW_ITEM_TYPE_RAW,
975 RTE_FLOW_ITEM_TYPE_VF,
976 RTE_FLOW_ITEM_TYPE_END,
979 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
980 RTE_FLOW_ITEM_TYPE_ETH,
981 RTE_FLOW_ITEM_TYPE_IPV6,
982 RTE_FLOW_ITEM_TYPE_RAW,
983 RTE_FLOW_ITEM_TYPE_VF,
984 RTE_FLOW_ITEM_TYPE_END,
987 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
988 RTE_FLOW_ITEM_TYPE_ETH,
989 RTE_FLOW_ITEM_TYPE_IPV6,
990 RTE_FLOW_ITEM_TYPE_RAW,
991 RTE_FLOW_ITEM_TYPE_RAW,
992 RTE_FLOW_ITEM_TYPE_VF,
993 RTE_FLOW_ITEM_TYPE_END,
996 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
997 RTE_FLOW_ITEM_TYPE_ETH,
998 RTE_FLOW_ITEM_TYPE_IPV6,
999 RTE_FLOW_ITEM_TYPE_RAW,
1000 RTE_FLOW_ITEM_TYPE_RAW,
1001 RTE_FLOW_ITEM_TYPE_RAW,
1002 RTE_FLOW_ITEM_TYPE_VF,
1003 RTE_FLOW_ITEM_TYPE_END,
1006 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1007 RTE_FLOW_ITEM_TYPE_ETH,
1008 RTE_FLOW_ITEM_TYPE_IPV6,
1009 RTE_FLOW_ITEM_TYPE_UDP,
1010 RTE_FLOW_ITEM_TYPE_RAW,
1011 RTE_FLOW_ITEM_TYPE_VF,
1012 RTE_FLOW_ITEM_TYPE_END,
1015 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1016 RTE_FLOW_ITEM_TYPE_ETH,
1017 RTE_FLOW_ITEM_TYPE_IPV6,
1018 RTE_FLOW_ITEM_TYPE_UDP,
1019 RTE_FLOW_ITEM_TYPE_RAW,
1020 RTE_FLOW_ITEM_TYPE_RAW,
1021 RTE_FLOW_ITEM_TYPE_VF,
1022 RTE_FLOW_ITEM_TYPE_END,
1025 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1026 RTE_FLOW_ITEM_TYPE_ETH,
1027 RTE_FLOW_ITEM_TYPE_IPV6,
1028 RTE_FLOW_ITEM_TYPE_UDP,
1029 RTE_FLOW_ITEM_TYPE_RAW,
1030 RTE_FLOW_ITEM_TYPE_RAW,
1031 RTE_FLOW_ITEM_TYPE_RAW,
1032 RTE_FLOW_ITEM_TYPE_VF,
1033 RTE_FLOW_ITEM_TYPE_END,
1036 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1037 RTE_FLOW_ITEM_TYPE_ETH,
1038 RTE_FLOW_ITEM_TYPE_IPV6,
1039 RTE_FLOW_ITEM_TYPE_TCP,
1040 RTE_FLOW_ITEM_TYPE_RAW,
1041 RTE_FLOW_ITEM_TYPE_VF,
1042 RTE_FLOW_ITEM_TYPE_END,
1045 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1046 RTE_FLOW_ITEM_TYPE_ETH,
1047 RTE_FLOW_ITEM_TYPE_IPV6,
1048 RTE_FLOW_ITEM_TYPE_TCP,
1049 RTE_FLOW_ITEM_TYPE_RAW,
1050 RTE_FLOW_ITEM_TYPE_RAW,
1051 RTE_FLOW_ITEM_TYPE_VF,
1052 RTE_FLOW_ITEM_TYPE_END,
1055 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1056 RTE_FLOW_ITEM_TYPE_ETH,
1057 RTE_FLOW_ITEM_TYPE_IPV6,
1058 RTE_FLOW_ITEM_TYPE_TCP,
1059 RTE_FLOW_ITEM_TYPE_RAW,
1060 RTE_FLOW_ITEM_TYPE_RAW,
1061 RTE_FLOW_ITEM_TYPE_RAW,
1062 RTE_FLOW_ITEM_TYPE_VF,
1063 RTE_FLOW_ITEM_TYPE_END,
1066 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1067 RTE_FLOW_ITEM_TYPE_ETH,
1068 RTE_FLOW_ITEM_TYPE_IPV6,
1069 RTE_FLOW_ITEM_TYPE_SCTP,
1070 RTE_FLOW_ITEM_TYPE_RAW,
1071 RTE_FLOW_ITEM_TYPE_VF,
1072 RTE_FLOW_ITEM_TYPE_END,
1075 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1076 RTE_FLOW_ITEM_TYPE_ETH,
1077 RTE_FLOW_ITEM_TYPE_IPV6,
1078 RTE_FLOW_ITEM_TYPE_SCTP,
1079 RTE_FLOW_ITEM_TYPE_RAW,
1080 RTE_FLOW_ITEM_TYPE_RAW,
1081 RTE_FLOW_ITEM_TYPE_VF,
1082 RTE_FLOW_ITEM_TYPE_END,
1085 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1086 RTE_FLOW_ITEM_TYPE_ETH,
1087 RTE_FLOW_ITEM_TYPE_IPV6,
1088 RTE_FLOW_ITEM_TYPE_SCTP,
1089 RTE_FLOW_ITEM_TYPE_RAW,
1090 RTE_FLOW_ITEM_TYPE_RAW,
1091 RTE_FLOW_ITEM_TYPE_RAW,
1092 RTE_FLOW_ITEM_TYPE_VF,
1093 RTE_FLOW_ITEM_TYPE_END,
1096 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1097 RTE_FLOW_ITEM_TYPE_ETH,
1098 RTE_FLOW_ITEM_TYPE_VLAN,
1099 RTE_FLOW_ITEM_TYPE_VF,
1100 RTE_FLOW_ITEM_TYPE_END,
1103 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1104 RTE_FLOW_ITEM_TYPE_ETH,
1105 RTE_FLOW_ITEM_TYPE_VLAN,
1106 RTE_FLOW_ITEM_TYPE_IPV4,
1107 RTE_FLOW_ITEM_TYPE_VF,
1108 RTE_FLOW_ITEM_TYPE_END,
1111 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1112 RTE_FLOW_ITEM_TYPE_ETH,
1113 RTE_FLOW_ITEM_TYPE_VLAN,
1114 RTE_FLOW_ITEM_TYPE_IPV4,
1115 RTE_FLOW_ITEM_TYPE_UDP,
1116 RTE_FLOW_ITEM_TYPE_VF,
1117 RTE_FLOW_ITEM_TYPE_END,
1120 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1121 RTE_FLOW_ITEM_TYPE_ETH,
1122 RTE_FLOW_ITEM_TYPE_VLAN,
1123 RTE_FLOW_ITEM_TYPE_IPV4,
1124 RTE_FLOW_ITEM_TYPE_TCP,
1125 RTE_FLOW_ITEM_TYPE_VF,
1126 RTE_FLOW_ITEM_TYPE_END,
1129 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1130 RTE_FLOW_ITEM_TYPE_ETH,
1131 RTE_FLOW_ITEM_TYPE_VLAN,
1132 RTE_FLOW_ITEM_TYPE_IPV4,
1133 RTE_FLOW_ITEM_TYPE_SCTP,
1134 RTE_FLOW_ITEM_TYPE_VF,
1135 RTE_FLOW_ITEM_TYPE_END,
1138 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1139 RTE_FLOW_ITEM_TYPE_ETH,
1140 RTE_FLOW_ITEM_TYPE_VLAN,
1141 RTE_FLOW_ITEM_TYPE_IPV6,
1142 RTE_FLOW_ITEM_TYPE_VF,
1143 RTE_FLOW_ITEM_TYPE_END,
1146 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1147 RTE_FLOW_ITEM_TYPE_ETH,
1148 RTE_FLOW_ITEM_TYPE_VLAN,
1149 RTE_FLOW_ITEM_TYPE_IPV6,
1150 RTE_FLOW_ITEM_TYPE_UDP,
1151 RTE_FLOW_ITEM_TYPE_VF,
1152 RTE_FLOW_ITEM_TYPE_END,
1155 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1156 RTE_FLOW_ITEM_TYPE_ETH,
1157 RTE_FLOW_ITEM_TYPE_VLAN,
1158 RTE_FLOW_ITEM_TYPE_IPV6,
1159 RTE_FLOW_ITEM_TYPE_TCP,
1160 RTE_FLOW_ITEM_TYPE_VF,
1161 RTE_FLOW_ITEM_TYPE_END,
1164 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1165 RTE_FLOW_ITEM_TYPE_ETH,
1166 RTE_FLOW_ITEM_TYPE_VLAN,
1167 RTE_FLOW_ITEM_TYPE_IPV6,
1168 RTE_FLOW_ITEM_TYPE_SCTP,
1169 RTE_FLOW_ITEM_TYPE_VF,
1170 RTE_FLOW_ITEM_TYPE_END,
1173 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1174 RTE_FLOW_ITEM_TYPE_ETH,
1175 RTE_FLOW_ITEM_TYPE_VLAN,
1176 RTE_FLOW_ITEM_TYPE_RAW,
1177 RTE_FLOW_ITEM_TYPE_VF,
1178 RTE_FLOW_ITEM_TYPE_END,
1181 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1182 RTE_FLOW_ITEM_TYPE_ETH,
1183 RTE_FLOW_ITEM_TYPE_VLAN,
1184 RTE_FLOW_ITEM_TYPE_RAW,
1185 RTE_FLOW_ITEM_TYPE_RAW,
1186 RTE_FLOW_ITEM_TYPE_VF,
1187 RTE_FLOW_ITEM_TYPE_END,
1190 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1191 RTE_FLOW_ITEM_TYPE_ETH,
1192 RTE_FLOW_ITEM_TYPE_VLAN,
1193 RTE_FLOW_ITEM_TYPE_RAW,
1194 RTE_FLOW_ITEM_TYPE_RAW,
1195 RTE_FLOW_ITEM_TYPE_RAW,
1196 RTE_FLOW_ITEM_TYPE_VF,
1197 RTE_FLOW_ITEM_TYPE_END,
1200 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1201 RTE_FLOW_ITEM_TYPE_ETH,
1202 RTE_FLOW_ITEM_TYPE_VLAN,
1203 RTE_FLOW_ITEM_TYPE_IPV4,
1204 RTE_FLOW_ITEM_TYPE_RAW,
1205 RTE_FLOW_ITEM_TYPE_VF,
1206 RTE_FLOW_ITEM_TYPE_END,
1209 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1210 RTE_FLOW_ITEM_TYPE_ETH,
1211 RTE_FLOW_ITEM_TYPE_VLAN,
1212 RTE_FLOW_ITEM_TYPE_IPV4,
1213 RTE_FLOW_ITEM_TYPE_RAW,
1214 RTE_FLOW_ITEM_TYPE_RAW,
1215 RTE_FLOW_ITEM_TYPE_VF,
1216 RTE_FLOW_ITEM_TYPE_END,
1219 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1220 RTE_FLOW_ITEM_TYPE_ETH,
1221 RTE_FLOW_ITEM_TYPE_VLAN,
1222 RTE_FLOW_ITEM_TYPE_IPV4,
1223 RTE_FLOW_ITEM_TYPE_RAW,
1224 RTE_FLOW_ITEM_TYPE_RAW,
1225 RTE_FLOW_ITEM_TYPE_RAW,
1226 RTE_FLOW_ITEM_TYPE_VF,
1227 RTE_FLOW_ITEM_TYPE_END,
1230 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1231 RTE_FLOW_ITEM_TYPE_ETH,
1232 RTE_FLOW_ITEM_TYPE_VLAN,
1233 RTE_FLOW_ITEM_TYPE_IPV4,
1234 RTE_FLOW_ITEM_TYPE_UDP,
1235 RTE_FLOW_ITEM_TYPE_RAW,
1236 RTE_FLOW_ITEM_TYPE_VF,
1237 RTE_FLOW_ITEM_TYPE_END,
1240 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1241 RTE_FLOW_ITEM_TYPE_ETH,
1242 RTE_FLOW_ITEM_TYPE_VLAN,
1243 RTE_FLOW_ITEM_TYPE_IPV4,
1244 RTE_FLOW_ITEM_TYPE_UDP,
1245 RTE_FLOW_ITEM_TYPE_RAW,
1246 RTE_FLOW_ITEM_TYPE_RAW,
1247 RTE_FLOW_ITEM_TYPE_VF,
1248 RTE_FLOW_ITEM_TYPE_END,
1251 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1252 RTE_FLOW_ITEM_TYPE_ETH,
1253 RTE_FLOW_ITEM_TYPE_VLAN,
1254 RTE_FLOW_ITEM_TYPE_IPV4,
1255 RTE_FLOW_ITEM_TYPE_UDP,
1256 RTE_FLOW_ITEM_TYPE_RAW,
1257 RTE_FLOW_ITEM_TYPE_RAW,
1258 RTE_FLOW_ITEM_TYPE_RAW,
1259 RTE_FLOW_ITEM_TYPE_VF,
1260 RTE_FLOW_ITEM_TYPE_END,
1263 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1264 RTE_FLOW_ITEM_TYPE_ETH,
1265 RTE_FLOW_ITEM_TYPE_VLAN,
1266 RTE_FLOW_ITEM_TYPE_IPV4,
1267 RTE_FLOW_ITEM_TYPE_TCP,
1268 RTE_FLOW_ITEM_TYPE_RAW,
1269 RTE_FLOW_ITEM_TYPE_VF,
1270 RTE_FLOW_ITEM_TYPE_END,
1273 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1274 RTE_FLOW_ITEM_TYPE_ETH,
1275 RTE_FLOW_ITEM_TYPE_VLAN,
1276 RTE_FLOW_ITEM_TYPE_IPV4,
1277 RTE_FLOW_ITEM_TYPE_TCP,
1278 RTE_FLOW_ITEM_TYPE_RAW,
1279 RTE_FLOW_ITEM_TYPE_RAW,
1280 RTE_FLOW_ITEM_TYPE_VF,
1281 RTE_FLOW_ITEM_TYPE_END,
1284 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1285 RTE_FLOW_ITEM_TYPE_ETH,
1286 RTE_FLOW_ITEM_TYPE_VLAN,
1287 RTE_FLOW_ITEM_TYPE_IPV4,
1288 RTE_FLOW_ITEM_TYPE_TCP,
1289 RTE_FLOW_ITEM_TYPE_RAW,
1290 RTE_FLOW_ITEM_TYPE_RAW,
1291 RTE_FLOW_ITEM_TYPE_RAW,
1292 RTE_FLOW_ITEM_TYPE_VF,
1293 RTE_FLOW_ITEM_TYPE_END,
1296 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1297 RTE_FLOW_ITEM_TYPE_ETH,
1298 RTE_FLOW_ITEM_TYPE_VLAN,
1299 RTE_FLOW_ITEM_TYPE_IPV4,
1300 RTE_FLOW_ITEM_TYPE_SCTP,
1301 RTE_FLOW_ITEM_TYPE_RAW,
1302 RTE_FLOW_ITEM_TYPE_VF,
1303 RTE_FLOW_ITEM_TYPE_END,
1306 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1307 RTE_FLOW_ITEM_TYPE_ETH,
1308 RTE_FLOW_ITEM_TYPE_VLAN,
1309 RTE_FLOW_ITEM_TYPE_IPV4,
1310 RTE_FLOW_ITEM_TYPE_SCTP,
1311 RTE_FLOW_ITEM_TYPE_RAW,
1312 RTE_FLOW_ITEM_TYPE_RAW,
1313 RTE_FLOW_ITEM_TYPE_VF,
1314 RTE_FLOW_ITEM_TYPE_END,
1317 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1318 RTE_FLOW_ITEM_TYPE_ETH,
1319 RTE_FLOW_ITEM_TYPE_VLAN,
1320 RTE_FLOW_ITEM_TYPE_IPV4,
1321 RTE_FLOW_ITEM_TYPE_SCTP,
1322 RTE_FLOW_ITEM_TYPE_RAW,
1323 RTE_FLOW_ITEM_TYPE_RAW,
1324 RTE_FLOW_ITEM_TYPE_RAW,
1325 RTE_FLOW_ITEM_TYPE_VF,
1326 RTE_FLOW_ITEM_TYPE_END,
1329 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1330 RTE_FLOW_ITEM_TYPE_ETH,
1331 RTE_FLOW_ITEM_TYPE_VLAN,
1332 RTE_FLOW_ITEM_TYPE_IPV6,
1333 RTE_FLOW_ITEM_TYPE_RAW,
1334 RTE_FLOW_ITEM_TYPE_VF,
1335 RTE_FLOW_ITEM_TYPE_END,
1338 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1339 RTE_FLOW_ITEM_TYPE_ETH,
1340 RTE_FLOW_ITEM_TYPE_VLAN,
1341 RTE_FLOW_ITEM_TYPE_IPV6,
1342 RTE_FLOW_ITEM_TYPE_RAW,
1343 RTE_FLOW_ITEM_TYPE_RAW,
1344 RTE_FLOW_ITEM_TYPE_VF,
1345 RTE_FLOW_ITEM_TYPE_END,
1348 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1349 RTE_FLOW_ITEM_TYPE_ETH,
1350 RTE_FLOW_ITEM_TYPE_VLAN,
1351 RTE_FLOW_ITEM_TYPE_IPV6,
1352 RTE_FLOW_ITEM_TYPE_RAW,
1353 RTE_FLOW_ITEM_TYPE_RAW,
1354 RTE_FLOW_ITEM_TYPE_RAW,
1355 RTE_FLOW_ITEM_TYPE_VF,
1356 RTE_FLOW_ITEM_TYPE_END,
1359 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1360 RTE_FLOW_ITEM_TYPE_ETH,
1361 RTE_FLOW_ITEM_TYPE_VLAN,
1362 RTE_FLOW_ITEM_TYPE_IPV6,
1363 RTE_FLOW_ITEM_TYPE_UDP,
1364 RTE_FLOW_ITEM_TYPE_RAW,
1365 RTE_FLOW_ITEM_TYPE_VF,
1366 RTE_FLOW_ITEM_TYPE_END,
1369 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1370 RTE_FLOW_ITEM_TYPE_ETH,
1371 RTE_FLOW_ITEM_TYPE_VLAN,
1372 RTE_FLOW_ITEM_TYPE_IPV6,
1373 RTE_FLOW_ITEM_TYPE_UDP,
1374 RTE_FLOW_ITEM_TYPE_RAW,
1375 RTE_FLOW_ITEM_TYPE_RAW,
1376 RTE_FLOW_ITEM_TYPE_VF,
1377 RTE_FLOW_ITEM_TYPE_END,
1380 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1381 RTE_FLOW_ITEM_TYPE_ETH,
1382 RTE_FLOW_ITEM_TYPE_VLAN,
1383 RTE_FLOW_ITEM_TYPE_IPV6,
1384 RTE_FLOW_ITEM_TYPE_UDP,
1385 RTE_FLOW_ITEM_TYPE_RAW,
1386 RTE_FLOW_ITEM_TYPE_RAW,
1387 RTE_FLOW_ITEM_TYPE_RAW,
1388 RTE_FLOW_ITEM_TYPE_VF,
1389 RTE_FLOW_ITEM_TYPE_END,
1392 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1393 RTE_FLOW_ITEM_TYPE_ETH,
1394 RTE_FLOW_ITEM_TYPE_VLAN,
1395 RTE_FLOW_ITEM_TYPE_IPV6,
1396 RTE_FLOW_ITEM_TYPE_TCP,
1397 RTE_FLOW_ITEM_TYPE_RAW,
1398 RTE_FLOW_ITEM_TYPE_VF,
1399 RTE_FLOW_ITEM_TYPE_END,
1402 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1403 RTE_FLOW_ITEM_TYPE_ETH,
1404 RTE_FLOW_ITEM_TYPE_VLAN,
1405 RTE_FLOW_ITEM_TYPE_IPV6,
1406 RTE_FLOW_ITEM_TYPE_TCP,
1407 RTE_FLOW_ITEM_TYPE_RAW,
1408 RTE_FLOW_ITEM_TYPE_RAW,
1409 RTE_FLOW_ITEM_TYPE_VF,
1410 RTE_FLOW_ITEM_TYPE_END,
1413 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1414 RTE_FLOW_ITEM_TYPE_ETH,
1415 RTE_FLOW_ITEM_TYPE_VLAN,
1416 RTE_FLOW_ITEM_TYPE_IPV6,
1417 RTE_FLOW_ITEM_TYPE_TCP,
1418 RTE_FLOW_ITEM_TYPE_RAW,
1419 RTE_FLOW_ITEM_TYPE_RAW,
1420 RTE_FLOW_ITEM_TYPE_RAW,
1421 RTE_FLOW_ITEM_TYPE_VF,
1422 RTE_FLOW_ITEM_TYPE_END,
1425 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1426 RTE_FLOW_ITEM_TYPE_ETH,
1427 RTE_FLOW_ITEM_TYPE_VLAN,
1428 RTE_FLOW_ITEM_TYPE_IPV6,
1429 RTE_FLOW_ITEM_TYPE_SCTP,
1430 RTE_FLOW_ITEM_TYPE_RAW,
1431 RTE_FLOW_ITEM_TYPE_VF,
1432 RTE_FLOW_ITEM_TYPE_END,
1435 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1436 RTE_FLOW_ITEM_TYPE_ETH,
1437 RTE_FLOW_ITEM_TYPE_VLAN,
1438 RTE_FLOW_ITEM_TYPE_IPV6,
1439 RTE_FLOW_ITEM_TYPE_SCTP,
1440 RTE_FLOW_ITEM_TYPE_RAW,
1441 RTE_FLOW_ITEM_TYPE_RAW,
1442 RTE_FLOW_ITEM_TYPE_VF,
1443 RTE_FLOW_ITEM_TYPE_END,
1446 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1447 RTE_FLOW_ITEM_TYPE_ETH,
1448 RTE_FLOW_ITEM_TYPE_VLAN,
1449 RTE_FLOW_ITEM_TYPE_IPV6,
1450 RTE_FLOW_ITEM_TYPE_SCTP,
1451 RTE_FLOW_ITEM_TYPE_RAW,
1452 RTE_FLOW_ITEM_TYPE_RAW,
1453 RTE_FLOW_ITEM_TYPE_RAW,
1454 RTE_FLOW_ITEM_TYPE_VF,
1455 RTE_FLOW_ITEM_TYPE_END,
1458 /* Pattern matched tunnel filter */
1459 static enum rte_flow_item_type pattern_vxlan_1[] = {
1460 RTE_FLOW_ITEM_TYPE_ETH,
1461 RTE_FLOW_ITEM_TYPE_IPV4,
1462 RTE_FLOW_ITEM_TYPE_UDP,
1463 RTE_FLOW_ITEM_TYPE_VXLAN,
1464 RTE_FLOW_ITEM_TYPE_ETH,
1465 RTE_FLOW_ITEM_TYPE_END,
1468 static enum rte_flow_item_type pattern_vxlan_2[] = {
1469 RTE_FLOW_ITEM_TYPE_ETH,
1470 RTE_FLOW_ITEM_TYPE_IPV6,
1471 RTE_FLOW_ITEM_TYPE_UDP,
1472 RTE_FLOW_ITEM_TYPE_VXLAN,
1473 RTE_FLOW_ITEM_TYPE_ETH,
1474 RTE_FLOW_ITEM_TYPE_END,
1477 static enum rte_flow_item_type pattern_vxlan_3[] = {
1478 RTE_FLOW_ITEM_TYPE_ETH,
1479 RTE_FLOW_ITEM_TYPE_IPV4,
1480 RTE_FLOW_ITEM_TYPE_UDP,
1481 RTE_FLOW_ITEM_TYPE_VXLAN,
1482 RTE_FLOW_ITEM_TYPE_ETH,
1483 RTE_FLOW_ITEM_TYPE_VLAN,
1484 RTE_FLOW_ITEM_TYPE_END,
1487 static enum rte_flow_item_type pattern_vxlan_4[] = {
1488 RTE_FLOW_ITEM_TYPE_ETH,
1489 RTE_FLOW_ITEM_TYPE_IPV6,
1490 RTE_FLOW_ITEM_TYPE_UDP,
1491 RTE_FLOW_ITEM_TYPE_VXLAN,
1492 RTE_FLOW_ITEM_TYPE_ETH,
1493 RTE_FLOW_ITEM_TYPE_VLAN,
1494 RTE_FLOW_ITEM_TYPE_END,
1497 static enum rte_flow_item_type pattern_nvgre_1[] = {
1498 RTE_FLOW_ITEM_TYPE_ETH,
1499 RTE_FLOW_ITEM_TYPE_IPV4,
1500 RTE_FLOW_ITEM_TYPE_NVGRE,
1501 RTE_FLOW_ITEM_TYPE_ETH,
1502 RTE_FLOW_ITEM_TYPE_END,
1505 static enum rte_flow_item_type pattern_nvgre_2[] = {
1506 RTE_FLOW_ITEM_TYPE_ETH,
1507 RTE_FLOW_ITEM_TYPE_IPV6,
1508 RTE_FLOW_ITEM_TYPE_NVGRE,
1509 RTE_FLOW_ITEM_TYPE_ETH,
1510 RTE_FLOW_ITEM_TYPE_END,
1513 static enum rte_flow_item_type pattern_nvgre_3[] = {
1514 RTE_FLOW_ITEM_TYPE_ETH,
1515 RTE_FLOW_ITEM_TYPE_IPV4,
1516 RTE_FLOW_ITEM_TYPE_NVGRE,
1517 RTE_FLOW_ITEM_TYPE_ETH,
1518 RTE_FLOW_ITEM_TYPE_VLAN,
1519 RTE_FLOW_ITEM_TYPE_END,
1522 static enum rte_flow_item_type pattern_nvgre_4[] = {
1523 RTE_FLOW_ITEM_TYPE_ETH,
1524 RTE_FLOW_ITEM_TYPE_IPV6,
1525 RTE_FLOW_ITEM_TYPE_NVGRE,
1526 RTE_FLOW_ITEM_TYPE_ETH,
1527 RTE_FLOW_ITEM_TYPE_VLAN,
1528 RTE_FLOW_ITEM_TYPE_END,
1531 static enum rte_flow_item_type pattern_mpls_1[] = {
1532 RTE_FLOW_ITEM_TYPE_ETH,
1533 RTE_FLOW_ITEM_TYPE_IPV4,
1534 RTE_FLOW_ITEM_TYPE_UDP,
1535 RTE_FLOW_ITEM_TYPE_MPLS,
1536 RTE_FLOW_ITEM_TYPE_END,
1539 static enum rte_flow_item_type pattern_mpls_2[] = {
1540 RTE_FLOW_ITEM_TYPE_ETH,
1541 RTE_FLOW_ITEM_TYPE_IPV6,
1542 RTE_FLOW_ITEM_TYPE_UDP,
1543 RTE_FLOW_ITEM_TYPE_MPLS,
1544 RTE_FLOW_ITEM_TYPE_END,
1547 static enum rte_flow_item_type pattern_mpls_3[] = {
1548 RTE_FLOW_ITEM_TYPE_ETH,
1549 RTE_FLOW_ITEM_TYPE_IPV4,
1550 RTE_FLOW_ITEM_TYPE_GRE,
1551 RTE_FLOW_ITEM_TYPE_MPLS,
1552 RTE_FLOW_ITEM_TYPE_END,
1555 static enum rte_flow_item_type pattern_mpls_4[] = {
1556 RTE_FLOW_ITEM_TYPE_ETH,
1557 RTE_FLOW_ITEM_TYPE_IPV6,
1558 RTE_FLOW_ITEM_TYPE_GRE,
1559 RTE_FLOW_ITEM_TYPE_MPLS,
1560 RTE_FLOW_ITEM_TYPE_END,
1563 static enum rte_flow_item_type pattern_qinq_1[] = {
1564 RTE_FLOW_ITEM_TYPE_ETH,
1565 RTE_FLOW_ITEM_TYPE_VLAN,
1566 RTE_FLOW_ITEM_TYPE_VLAN,
1567 RTE_FLOW_ITEM_TYPE_END,
1570 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1572 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1573 /* FDIR - support default flow type without flexible payload*/
1574 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1575 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1576 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1577 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1578 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1579 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1580 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1581 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1582 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1583 /* FDIR - support default flow type with flexible payload */
1584 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1585 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1586 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1587 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1588 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1589 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1590 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1591 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1592 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1593 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1594 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1595 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1596 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1597 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1598 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1599 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1600 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1601 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1602 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1603 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1604 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1605 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1606 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1607 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1608 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1609 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1610 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1611 /* FDIR - support single vlan input set */
1612 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1613 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1614 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1615 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1616 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1617 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1618 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1619 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1620 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1621 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1622 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1623 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1624 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1625 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1626 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1627 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1628 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1629 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1630 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1631 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1632 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1633 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1634 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1635 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1636 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1637 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1638 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1639 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1640 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1641 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1642 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1643 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1644 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1645 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1646 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1647 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1648 /* FDIR - support VF item */
1649 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1650 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1651 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1652 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1653 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1654 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1655 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1656 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1657 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1658 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1659 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1660 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1661 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1662 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1663 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1664 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1665 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1666 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1667 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1668 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1669 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1703 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1704 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1705 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1706 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1721 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1722 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1723 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1724 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1726 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1727 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1728 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1729 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1730 /* MPLSoUDP & MPLSoGRE */
1731 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1732 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1733 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1734 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1736 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1739 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1741 act = actions + index; \
1742 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1744 act = actions + index; \
1748 /* Find the first VOID or non-VOID item pointer */
1749 static const struct rte_flow_item *
1750 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1754 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1756 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1758 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1766 /* Skip all VOID items of the pattern */
1768 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1769 const struct rte_flow_item *pattern)
1771 uint32_t cpy_count = 0;
1772 const struct rte_flow_item *pb = pattern, *pe = pattern;
1775 /* Find a non-void item first */
1776 pb = i40e_find_first_item(pb, false);
1777 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1782 /* Find a void item */
1783 pe = i40e_find_first_item(pb + 1, true);
1785 cpy_count = pe - pb;
1786 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1790 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1797 /* Copy the END item. */
1798 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1801 /* Check if the pattern matches a supported item type array */
1803 i40e_match_pattern(enum rte_flow_item_type *item_array,
1804 struct rte_flow_item *pattern)
1806 struct rte_flow_item *item = pattern;
1808 while ((*item_array == item->type) &&
1809 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1814 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1815 item->type == RTE_FLOW_ITEM_TYPE_END);
1818 /* Find if there's parse filter function matched */
1819 static parse_filter_t
1820 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1822 parse_filter_t parse_filter = NULL;
1825 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1826 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1828 parse_filter = i40e_supported_patterns[i].parse_filter;
1835 return parse_filter;
1838 /* Parse attributes */
1840 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1841 struct rte_flow_error *error)
1843 /* Must be input direction */
1844 if (!attr->ingress) {
1845 rte_flow_error_set(error, EINVAL,
1846 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1847 attr, "Only support ingress.");
1853 rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1855 attr, "Not support egress.");
1860 if (attr->priority) {
1861 rte_flow_error_set(error, EINVAL,
1862 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1863 attr, "Not support priority.");
1869 rte_flow_error_set(error, EINVAL,
1870 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1871 attr, "Not support group.");
1879 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1881 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1892 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1895 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1900 /* 1. Last in item should be NULL as range is not supported.
1901 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1902 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1903 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1905 * 5. Ether_type mask should be 0xFFFF.
1908 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1909 const struct rte_flow_item *pattern,
1910 struct rte_flow_error *error,
1911 struct rte_eth_ethertype_filter *filter)
1913 const struct rte_flow_item *item = pattern;
1914 const struct rte_flow_item_eth *eth_spec;
1915 const struct rte_flow_item_eth *eth_mask;
1916 enum rte_flow_item_type item_type;
1917 uint16_t outer_tpid;
1919 outer_tpid = i40e_get_outer_vlan(dev);
1921 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1923 rte_flow_error_set(error, EINVAL,
1924 RTE_FLOW_ERROR_TYPE_ITEM,
1926 "Not support range");
1929 item_type = item->type;
1930 switch (item_type) {
1931 case RTE_FLOW_ITEM_TYPE_ETH:
1932 eth_spec = (const struct rte_flow_item_eth *)item->spec;
1933 eth_mask = (const struct rte_flow_item_eth *)item->mask;
1934 /* Get the MAC info. */
1935 if (!eth_spec || !eth_mask) {
1936 rte_flow_error_set(error, EINVAL,
1937 RTE_FLOW_ERROR_TYPE_ITEM,
1939 "NULL ETH spec/mask");
1943 /* Mask bits of source MAC address must be full of 0.
1944 * Mask bits of destination MAC address must be full
1945 * of 1 or full of 0.
1947 if (!is_zero_ether_addr(ð_mask->src) ||
1948 (!is_zero_ether_addr(ð_mask->dst) &&
1949 !is_broadcast_ether_addr(ð_mask->dst))) {
1950 rte_flow_error_set(error, EINVAL,
1951 RTE_FLOW_ERROR_TYPE_ITEM,
1953 "Invalid MAC_addr mask");
1957 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
1958 rte_flow_error_set(error, EINVAL,
1959 RTE_FLOW_ERROR_TYPE_ITEM,
1961 "Invalid ethertype mask");
1965 /* If mask bits of destination MAC address
1966 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
1968 if (is_broadcast_ether_addr(ð_mask->dst)) {
1969 filter->mac_addr = eth_spec->dst;
1970 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
1972 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
1974 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
1976 if (filter->ether_type == ETHER_TYPE_IPv4 ||
1977 filter->ether_type == ETHER_TYPE_IPv6 ||
1978 filter->ether_type == ETHER_TYPE_LLDP ||
1979 filter->ether_type == outer_tpid) {
1980 rte_flow_error_set(error, EINVAL,
1981 RTE_FLOW_ERROR_TYPE_ITEM,
1983 "Unsupported ether_type in"
1984 " control packet filter.");
1996 /* Ethertype action only supports QUEUE or DROP. */
1998 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
1999 const struct rte_flow_action *actions,
2000 struct rte_flow_error *error,
2001 struct rte_eth_ethertype_filter *filter)
2003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2004 const struct rte_flow_action *act;
2005 const struct rte_flow_action_queue *act_q;
2008 /* Check if the first non-void action is QUEUE or DROP. */
2009 NEXT_ITEM_OF_ACTION(act, actions, index);
2010 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2011 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2012 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2013 act, "Not supported action.");
2017 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2018 act_q = (const struct rte_flow_action_queue *)act->conf;
2019 filter->queue = act_q->index;
2020 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2021 rte_flow_error_set(error, EINVAL,
2022 RTE_FLOW_ERROR_TYPE_ACTION,
2023 act, "Invalid queue ID for"
2024 " ethertype_filter.");
2028 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2031 /* Check if the next non-void item is END */
2033 NEXT_ITEM_OF_ACTION(act, actions, index);
2034 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2035 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2036 act, "Not supported action.");
2044 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2045 const struct rte_flow_attr *attr,
2046 const struct rte_flow_item pattern[],
2047 const struct rte_flow_action actions[],
2048 struct rte_flow_error *error,
2049 union i40e_filter_t *filter)
2051 struct rte_eth_ethertype_filter *ethertype_filter =
2052 &filter->ethertype_filter;
2055 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2060 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2065 ret = i40e_flow_parse_attr(attr, error);
2069 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2075 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2076 const struct rte_flow_item_raw *raw_spec,
2077 struct rte_flow_error *error)
2079 if (!raw_spec->relative) {
2080 rte_flow_error_set(error, EINVAL,
2081 RTE_FLOW_ERROR_TYPE_ITEM,
2083 "Relative should be 1.");
2087 if (raw_spec->offset % sizeof(uint16_t)) {
2088 rte_flow_error_set(error, EINVAL,
2089 RTE_FLOW_ERROR_TYPE_ITEM,
2091 "Offset should be even.");
2095 if (raw_spec->search || raw_spec->limit) {
2096 rte_flow_error_set(error, EINVAL,
2097 RTE_FLOW_ERROR_TYPE_ITEM,
2099 "search or limit is not supported.");
2103 if (raw_spec->offset < 0) {
2104 rte_flow_error_set(error, EINVAL,
2105 RTE_FLOW_ERROR_TYPE_ITEM,
2107 "Offset should be non-negative.");
2114 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2115 struct i40e_fdir_flex_pit *flex_pit,
2116 enum i40e_flxpld_layer_idx layer_idx,
2121 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2122 /* Check if the configuration is conflicted */
2123 if (pf->fdir.flex_pit_flag[layer_idx] &&
2124 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2125 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2126 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2129 /* Check if the configuration exists. */
2130 if (pf->fdir.flex_pit_flag[layer_idx] &&
2131 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2132 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2133 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2136 pf->fdir.flex_set[field_idx].src_offset =
2137 flex_pit->src_offset;
2138 pf->fdir.flex_set[field_idx].size =
2140 pf->fdir.flex_set[field_idx].dst_offset =
2141 flex_pit->dst_offset;
2147 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2148 enum i40e_filter_pctype pctype,
2151 struct i40e_fdir_flex_mask flex_mask;
2153 uint8_t i, nb_bitmask = 0;
2155 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2156 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2157 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2159 flex_mask.word_mask |=
2160 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2161 if (mask_tmp != UINT16_MAX) {
2162 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2163 flex_mask.bitmask[nb_bitmask].offset =
2164 i / sizeof(uint16_t);
2166 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2171 flex_mask.nb_bitmask = nb_bitmask;
2173 if (pf->fdir.flex_mask_flag[pctype] &&
2174 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2175 sizeof(struct i40e_fdir_flex_mask))))
2177 else if (pf->fdir.flex_mask_flag[pctype] &&
2178 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2179 sizeof(struct i40e_fdir_flex_mask))))
2182 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2183 sizeof(struct i40e_fdir_flex_mask));
2188 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2189 enum i40e_flxpld_layer_idx layer_idx,
2192 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2195 uint16_t min_next_off = 0; /* in words */
2199 for (i = 0; i < raw_id; i++) {
2200 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2201 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2202 pf->fdir.flex_set[field_idx].size,
2203 pf->fdir.flex_set[field_idx].dst_offset);
2205 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2206 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2207 pf->fdir.flex_set[field_idx].size;
2210 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2211 /* set the non-used register obeying register's constrain */
2212 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2213 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2214 NONUSE_FLX_PIT_DEST_OFF);
2215 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2219 pf->fdir.flex_pit_flag[layer_idx] = 1;
2223 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2224 enum i40e_filter_pctype pctype)
2226 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2227 struct i40e_fdir_flex_mask *flex_mask;
2228 uint32_t flxinset, fd_mask;
2232 flex_mask = &pf->fdir.flex_mask[pctype];
2233 flxinset = (flex_mask->word_mask <<
2234 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2235 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2236 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2238 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2239 fd_mask = (flex_mask->bitmask[i].mask <<
2240 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2241 I40E_PRTQF_FD_MSK_MASK_MASK;
2242 fd_mask |= ((flex_mask->bitmask[i].offset +
2243 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2244 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2245 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2246 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2249 pf->fdir.flex_mask_flag[pctype] = 1;
2253 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2254 enum i40e_filter_pctype pctype,
2257 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2258 uint64_t inset_reg = 0;
2259 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2262 /* Check if the input set is valid */
2263 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2265 PMD_DRV_LOG(ERR, "Invalid input set");
2269 /* Check if the configuration is conflicted */
2270 if (pf->fdir.inset_flag[pctype] &&
2271 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2274 if (pf->fdir.inset_flag[pctype] &&
2275 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2278 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2279 I40E_INSET_MASK_NUM_REG);
2283 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2285 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2286 (uint32_t)(inset_reg & UINT32_MAX));
2287 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2288 (uint32_t)((inset_reg >>
2289 I40E_32_BIT_WIDTH) & UINT32_MAX));
2291 for (i = 0; i < num; i++)
2292 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2295 /*clear unused mask registers of the pctype */
2296 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2297 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2298 I40E_WRITE_FLUSH(hw);
2300 pf->fdir.input_set[pctype] = input_set;
2301 pf->fdir.inset_flag[pctype] = 1;
2305 /* 1. Last in item should be NULL as range is not supported.
2306 * 2. Supported patterns: refer to array i40e_supported_patterns.
2307 * 3. Supported flow type and input set: refer to array
2308 * valid_fdir_inset_table in i40e_ethdev.c.
2309 * 4. Mask of fields which need to be matched should be
2311 * 5. Mask of fields which needn't to be matched should be
2315 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2316 const struct rte_flow_item *pattern,
2317 struct rte_flow_error *error,
2318 struct rte_eth_fdir_filter *filter)
2320 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2321 const struct rte_flow_item *item = pattern;
2322 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2323 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2324 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2325 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2326 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2327 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2328 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2329 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2330 const struct rte_flow_item_vf *vf_spec;
2332 uint32_t flow_type = RTE_ETH_FLOW_UNKNOWN;
2333 enum i40e_filter_pctype pctype;
2334 uint64_t input_set = I40E_INSET_NONE;
2336 enum rte_flow_item_type item_type;
2337 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2339 uint8_t ipv6_addr_mask[16] = {
2340 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2341 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2342 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2344 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2345 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2346 struct i40e_fdir_flex_pit flex_pit;
2347 uint8_t next_dst_off = 0;
2348 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2350 bool cfg_flex_pit = true;
2351 bool cfg_flex_msk = true;
2352 uint16_t outer_tpid;
2353 uint16_t ether_type;
2354 uint32_t vtc_flow_cpu;
2357 memset(off_arr, 0, sizeof(off_arr));
2358 memset(len_arr, 0, sizeof(len_arr));
2359 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2360 outer_tpid = i40e_get_outer_vlan(dev);
2361 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2363 rte_flow_error_set(error, EINVAL,
2364 RTE_FLOW_ERROR_TYPE_ITEM,
2366 "Not support range");
2369 item_type = item->type;
2370 switch (item_type) {
2371 case RTE_FLOW_ITEM_TYPE_ETH:
2372 eth_spec = (const struct rte_flow_item_eth *)item->spec;
2373 eth_mask = (const struct rte_flow_item_eth *)item->mask;
2375 if (eth_spec && eth_mask) {
2376 if (!is_zero_ether_addr(ð_mask->src) ||
2377 !is_zero_ether_addr(ð_mask->dst)) {
2378 rte_flow_error_set(error, EINVAL,
2379 RTE_FLOW_ERROR_TYPE_ITEM,
2381 "Invalid MAC_addr mask.");
2385 if ((eth_mask->type & UINT16_MAX) ==
2387 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2388 filter->input.flow.l2_flow.ether_type =
2392 ether_type = rte_be_to_cpu_16(eth_spec->type);
2393 if (ether_type == ETHER_TYPE_IPv4 ||
2394 ether_type == ETHER_TYPE_IPv6 ||
2395 ether_type == ETHER_TYPE_ARP ||
2396 ether_type == outer_tpid) {
2397 rte_flow_error_set(error, EINVAL,
2398 RTE_FLOW_ERROR_TYPE_ITEM,
2400 "Unsupported ether_type.");
2405 flow_type = RTE_ETH_FLOW_L2_PAYLOAD;
2406 layer_idx = I40E_FLXPLD_L2_IDX;
2409 case RTE_FLOW_ITEM_TYPE_VLAN:
2411 (const struct rte_flow_item_vlan *)item->spec;
2413 (const struct rte_flow_item_vlan *)item->mask;
2414 if (vlan_spec && vlan_mask) {
2415 if (vlan_mask->tci ==
2416 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2417 input_set |= I40E_INSET_VLAN_INNER;
2418 filter->input.flow_ext.vlan_tci =
2423 flow_type = RTE_ETH_FLOW_L2_PAYLOAD;
2424 layer_idx = I40E_FLXPLD_L2_IDX;
2427 case RTE_FLOW_ITEM_TYPE_IPV4:
2428 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2430 (const struct rte_flow_item_ipv4 *)item->spec;
2432 (const struct rte_flow_item_ipv4 *)item->mask;
2434 if (ipv4_spec && ipv4_mask) {
2435 /* Check IPv4 mask and update input set */
2436 if (ipv4_mask->hdr.version_ihl ||
2437 ipv4_mask->hdr.total_length ||
2438 ipv4_mask->hdr.packet_id ||
2439 ipv4_mask->hdr.fragment_offset ||
2440 ipv4_mask->hdr.hdr_checksum) {
2441 rte_flow_error_set(error, EINVAL,
2442 RTE_FLOW_ERROR_TYPE_ITEM,
2444 "Invalid IPv4 mask.");
2448 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2449 input_set |= I40E_INSET_IPV4_SRC;
2450 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2451 input_set |= I40E_INSET_IPV4_DST;
2452 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2453 input_set |= I40E_INSET_IPV4_TOS;
2454 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2455 input_set |= I40E_INSET_IPV4_TTL;
2456 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2457 input_set |= I40E_INSET_IPV4_PROTO;
2459 /* Get filter info */
2460 flow_type = RTE_ETH_FLOW_NONFRAG_IPV4_OTHER;
2461 /* Check if it is fragment. */
2462 frag_off = ipv4_spec->hdr.fragment_offset;
2463 frag_off = rte_be_to_cpu_16(frag_off);
2464 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2465 frag_off & IPV4_HDR_MF_FLAG)
2466 flow_type = RTE_ETH_FLOW_FRAG_IPV4;
2468 /* Get the filter info */
2469 filter->input.flow.ip4_flow.proto =
2470 ipv4_spec->hdr.next_proto_id;
2471 filter->input.flow.ip4_flow.tos =
2472 ipv4_spec->hdr.type_of_service;
2473 filter->input.flow.ip4_flow.ttl =
2474 ipv4_spec->hdr.time_to_live;
2475 filter->input.flow.ip4_flow.src_ip =
2476 ipv4_spec->hdr.src_addr;
2477 filter->input.flow.ip4_flow.dst_ip =
2478 ipv4_spec->hdr.dst_addr;
2481 layer_idx = I40E_FLXPLD_L3_IDX;
2484 case RTE_FLOW_ITEM_TYPE_IPV6:
2485 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2487 (const struct rte_flow_item_ipv6 *)item->spec;
2489 (const struct rte_flow_item_ipv6 *)item->mask;
2491 if (ipv6_spec && ipv6_mask) {
2492 /* Check IPv6 mask and update input set */
2493 if (ipv6_mask->hdr.payload_len) {
2494 rte_flow_error_set(error, EINVAL,
2495 RTE_FLOW_ERROR_TYPE_ITEM,
2497 "Invalid IPv6 mask");
2501 if (!memcmp(ipv6_mask->hdr.src_addr,
2503 RTE_DIM(ipv6_mask->hdr.src_addr)))
2504 input_set |= I40E_INSET_IPV6_SRC;
2505 if (!memcmp(ipv6_mask->hdr.dst_addr,
2507 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2508 input_set |= I40E_INSET_IPV6_DST;
2510 if ((ipv6_mask->hdr.vtc_flow &
2511 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2512 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2513 input_set |= I40E_INSET_IPV6_TC;
2514 if (ipv6_mask->hdr.proto == UINT8_MAX)
2515 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2516 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2517 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2519 /* Get filter info */
2521 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2522 filter->input.flow.ipv6_flow.tc =
2523 (uint8_t)(vtc_flow_cpu >>
2524 I40E_FDIR_IPv6_TC_OFFSET);
2525 filter->input.flow.ipv6_flow.proto =
2526 ipv6_spec->hdr.proto;
2527 filter->input.flow.ipv6_flow.hop_limits =
2528 ipv6_spec->hdr.hop_limits;
2530 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2531 ipv6_spec->hdr.src_addr, 16);
2532 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2533 ipv6_spec->hdr.dst_addr, 16);
2535 /* Check if it is fragment. */
2536 if (ipv6_spec->hdr.proto ==
2537 I40E_IPV6_FRAG_HEADER)
2539 RTE_ETH_FLOW_FRAG_IPV6;
2542 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER;
2545 layer_idx = I40E_FLXPLD_L3_IDX;
2548 case RTE_FLOW_ITEM_TYPE_TCP:
2549 tcp_spec = (const struct rte_flow_item_tcp *)item->spec;
2550 tcp_mask = (const struct rte_flow_item_tcp *)item->mask;
2552 if (tcp_spec && tcp_mask) {
2553 /* Check TCP mask and update input set */
2554 if (tcp_mask->hdr.sent_seq ||
2555 tcp_mask->hdr.recv_ack ||
2556 tcp_mask->hdr.data_off ||
2557 tcp_mask->hdr.tcp_flags ||
2558 tcp_mask->hdr.rx_win ||
2559 tcp_mask->hdr.cksum ||
2560 tcp_mask->hdr.tcp_urp) {
2561 rte_flow_error_set(error, EINVAL,
2562 RTE_FLOW_ERROR_TYPE_ITEM,
2564 "Invalid TCP mask");
2568 if (tcp_mask->hdr.src_port == UINT16_MAX)
2569 input_set |= I40E_INSET_SRC_PORT;
2570 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2571 input_set |= I40E_INSET_DST_PORT;
2573 /* Get filter info */
2574 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2576 RTE_ETH_FLOW_NONFRAG_IPV4_TCP;
2577 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2579 RTE_ETH_FLOW_NONFRAG_IPV6_TCP;
2581 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2582 filter->input.flow.tcp4_flow.src_port =
2583 tcp_spec->hdr.src_port;
2584 filter->input.flow.tcp4_flow.dst_port =
2585 tcp_spec->hdr.dst_port;
2586 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2587 filter->input.flow.tcp6_flow.src_port =
2588 tcp_spec->hdr.src_port;
2589 filter->input.flow.tcp6_flow.dst_port =
2590 tcp_spec->hdr.dst_port;
2594 layer_idx = I40E_FLXPLD_L4_IDX;
2597 case RTE_FLOW_ITEM_TYPE_UDP:
2598 udp_spec = (const struct rte_flow_item_udp *)item->spec;
2599 udp_mask = (const struct rte_flow_item_udp *)item->mask;
2601 if (udp_spec && udp_mask) {
2602 /* Check UDP mask and update input set*/
2603 if (udp_mask->hdr.dgram_len ||
2604 udp_mask->hdr.dgram_cksum) {
2605 rte_flow_error_set(error, EINVAL,
2606 RTE_FLOW_ERROR_TYPE_ITEM,
2608 "Invalid UDP mask");
2612 if (udp_mask->hdr.src_port == UINT16_MAX)
2613 input_set |= I40E_INSET_SRC_PORT;
2614 if (udp_mask->hdr.dst_port == UINT16_MAX)
2615 input_set |= I40E_INSET_DST_PORT;
2617 /* Get filter info */
2618 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2620 RTE_ETH_FLOW_NONFRAG_IPV4_UDP;
2621 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2623 RTE_ETH_FLOW_NONFRAG_IPV6_UDP;
2625 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2626 filter->input.flow.udp4_flow.src_port =
2627 udp_spec->hdr.src_port;
2628 filter->input.flow.udp4_flow.dst_port =
2629 udp_spec->hdr.dst_port;
2630 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2631 filter->input.flow.udp6_flow.src_port =
2632 udp_spec->hdr.src_port;
2633 filter->input.flow.udp6_flow.dst_port =
2634 udp_spec->hdr.dst_port;
2638 layer_idx = I40E_FLXPLD_L4_IDX;
2641 case RTE_FLOW_ITEM_TYPE_SCTP:
2643 (const struct rte_flow_item_sctp *)item->spec;
2645 (const struct rte_flow_item_sctp *)item->mask;
2647 if (sctp_spec && sctp_mask) {
2648 /* Check SCTP mask and update input set */
2649 if (sctp_mask->hdr.cksum) {
2650 rte_flow_error_set(error, EINVAL,
2651 RTE_FLOW_ERROR_TYPE_ITEM,
2653 "Invalid UDP mask");
2657 if (sctp_mask->hdr.src_port == UINT16_MAX)
2658 input_set |= I40E_INSET_SRC_PORT;
2659 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2660 input_set |= I40E_INSET_DST_PORT;
2661 if (sctp_mask->hdr.tag == UINT32_MAX)
2662 input_set |= I40E_INSET_SCTP_VT;
2664 /* Get filter info */
2665 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2667 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP;
2668 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2670 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP;
2672 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2673 filter->input.flow.sctp4_flow.src_port =
2674 sctp_spec->hdr.src_port;
2675 filter->input.flow.sctp4_flow.dst_port =
2676 sctp_spec->hdr.dst_port;
2677 filter->input.flow.sctp4_flow.verify_tag
2678 = sctp_spec->hdr.tag;
2679 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2680 filter->input.flow.sctp6_flow.src_port =
2681 sctp_spec->hdr.src_port;
2682 filter->input.flow.sctp6_flow.dst_port =
2683 sctp_spec->hdr.dst_port;
2684 filter->input.flow.sctp6_flow.verify_tag
2685 = sctp_spec->hdr.tag;
2689 layer_idx = I40E_FLXPLD_L4_IDX;
2692 case RTE_FLOW_ITEM_TYPE_RAW:
2693 raw_spec = (const struct rte_flow_item_raw *)item->spec;
2694 raw_mask = (const struct rte_flow_item_raw *)item->mask;
2696 if (!raw_spec || !raw_mask) {
2697 rte_flow_error_set(error, EINVAL,
2698 RTE_FLOW_ERROR_TYPE_ITEM,
2700 "NULL RAW spec/mask");
2704 ret = i40e_flow_check_raw_item(item, raw_spec, error);
2708 off_arr[raw_id] = raw_spec->offset;
2709 len_arr[raw_id] = raw_spec->length;
2712 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2714 raw_spec->length / sizeof(uint16_t);
2715 flex_pit.dst_offset =
2716 next_dst_off / sizeof(uint16_t);
2718 for (i = 0; i <= raw_id; i++) {
2720 flex_pit.src_offset +=
2724 flex_pit.src_offset +=
2725 (off_arr[i] + len_arr[i]) /
2727 flex_size += len_arr[i];
2729 if (((flex_pit.src_offset + flex_pit.size) >=
2730 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2731 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2732 rte_flow_error_set(error, EINVAL,
2733 RTE_FLOW_ERROR_TYPE_ITEM,
2735 "Exceeds maxmial payload limit.");
2739 /* Store flex pit to SW */
2740 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2743 rte_flow_error_set(error, EINVAL,
2744 RTE_FLOW_ERROR_TYPE_ITEM,
2746 "Conflict with the first flexible rule.");
2749 cfg_flex_pit = false;
2751 for (i = 0; i < raw_spec->length; i++) {
2752 j = i + next_dst_off;
2753 filter->input.flow_ext.flexbytes[j] =
2754 raw_spec->pattern[i];
2755 flex_mask[j] = raw_mask->pattern[i];
2758 next_dst_off += raw_spec->length;
2761 case RTE_FLOW_ITEM_TYPE_VF:
2762 vf_spec = (const struct rte_flow_item_vf *)item->spec;
2763 filter->input.flow_ext.is_vf = 1;
2764 filter->input.flow_ext.dst_id = vf_spec->id;
2765 if (filter->input.flow_ext.is_vf &&
2766 filter->input.flow_ext.dst_id >= pf->vf_num) {
2767 rte_flow_error_set(error, EINVAL,
2768 RTE_FLOW_ERROR_TYPE_ITEM,
2770 "Invalid VF ID for FDIR.");
2779 pctype = i40e_flowtype_to_pctype(flow_type);
2780 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
2781 rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ITEM, item,
2783 "Unsupported flow type");
2787 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2789 rte_flow_error_set(error, EINVAL,
2790 RTE_FLOW_ERROR_TYPE_ITEM, item,
2791 "Conflict with the first rule's input set.");
2793 } else if (ret == -EINVAL) {
2794 rte_flow_error_set(error, EINVAL,
2795 RTE_FLOW_ERROR_TYPE_ITEM, item,
2796 "Invalid pattern mask.");
2800 filter->input.flow_type = flow_type;
2802 /* Store flex mask to SW */
2803 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2805 rte_flow_error_set(error, EINVAL,
2806 RTE_FLOW_ERROR_TYPE_ITEM,
2808 "Exceed maximal number of bitmasks");
2810 } else if (ret == -2) {
2811 rte_flow_error_set(error, EINVAL,
2812 RTE_FLOW_ERROR_TYPE_ITEM,
2814 "Conflict with the first flexible rule");
2817 cfg_flex_msk = false;
2820 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2823 i40e_flow_set_fdir_flex_msk(pf, pctype);
2828 /* Parse to get the action info of a FDIR filter.
2829 * FDIR action supports QUEUE or (QUEUE + MARK).
2832 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2833 const struct rte_flow_action *actions,
2834 struct rte_flow_error *error,
2835 struct rte_eth_fdir_filter *filter)
2837 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2838 const struct rte_flow_action *act;
2839 const struct rte_flow_action_queue *act_q;
2840 const struct rte_flow_action_mark *mark_spec;
2843 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
2844 NEXT_ITEM_OF_ACTION(act, actions, index);
2845 switch (act->type) {
2846 case RTE_FLOW_ACTION_TYPE_QUEUE:
2847 act_q = (const struct rte_flow_action_queue *)act->conf;
2848 filter->action.rx_queue = act_q->index;
2849 if ((!filter->input.flow_ext.is_vf &&
2850 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
2851 (filter->input.flow_ext.is_vf &&
2852 filter->action.rx_queue >= pf->vf_nb_qps)) {
2853 rte_flow_error_set(error, EINVAL,
2854 RTE_FLOW_ERROR_TYPE_ACTION, act,
2855 "Invalid queue ID for FDIR.");
2858 filter->action.behavior = RTE_ETH_FDIR_ACCEPT;
2860 case RTE_FLOW_ACTION_TYPE_DROP:
2861 filter->action.behavior = RTE_ETH_FDIR_REJECT;
2863 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
2864 filter->action.behavior = RTE_ETH_FDIR_PASSTHRU;
2867 rte_flow_error_set(error, EINVAL,
2868 RTE_FLOW_ERROR_TYPE_ACTION, act,
2873 /* Check if the next non-void item is MARK or FLAG or END. */
2875 NEXT_ITEM_OF_ACTION(act, actions, index);
2876 switch (act->type) {
2877 case RTE_FLOW_ACTION_TYPE_MARK:
2878 mark_spec = (const struct rte_flow_action_mark *)act->conf;
2879 filter->action.report_status = RTE_ETH_FDIR_REPORT_ID;
2880 filter->soft_id = mark_spec->id;
2882 case RTE_FLOW_ACTION_TYPE_FLAG:
2883 filter->action.report_status = RTE_ETH_FDIR_NO_REPORT_STATUS;
2885 case RTE_FLOW_ACTION_TYPE_END:
2888 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2889 act, "Invalid action.");
2893 /* Check if the next non-void item is END */
2895 NEXT_ITEM_OF_ACTION(act, actions, index);
2896 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2897 rte_flow_error_set(error, EINVAL,
2898 RTE_FLOW_ERROR_TYPE_ACTION,
2899 act, "Invalid action.");
2907 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
2908 const struct rte_flow_attr *attr,
2909 const struct rte_flow_item pattern[],
2910 const struct rte_flow_action actions[],
2911 struct rte_flow_error *error,
2912 union i40e_filter_t *filter)
2914 struct rte_eth_fdir_filter *fdir_filter =
2915 &filter->fdir_filter;
2918 ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
2922 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
2926 ret = i40e_flow_parse_attr(attr, error);
2930 cons_filter_type = RTE_ETH_FILTER_FDIR;
2932 if (dev->data->dev_conf.fdir_conf.mode !=
2933 RTE_FDIR_MODE_PERFECT) {
2934 rte_flow_error_set(error, ENOTSUP,
2935 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2937 "Check the mode in fdir_conf.");
2944 /* Parse to get the action info of a tunnel filter
2945 * Tunnel action only supports PF, VF and QUEUE.
2948 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
2949 const struct rte_flow_action *actions,
2950 struct rte_flow_error *error,
2951 struct i40e_tunnel_filter_conf *filter)
2953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2954 const struct rte_flow_action *act;
2955 const struct rte_flow_action_queue *act_q;
2956 const struct rte_flow_action_vf *act_vf;
2959 /* Check if the first non-void action is PF or VF. */
2960 NEXT_ITEM_OF_ACTION(act, actions, index);
2961 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
2962 act->type != RTE_FLOW_ACTION_TYPE_VF) {
2963 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2964 act, "Not supported action.");
2968 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
2969 act_vf = (const struct rte_flow_action_vf *)act->conf;
2970 filter->vf_id = act_vf->id;
2971 filter->is_to_vf = 1;
2972 if (filter->vf_id >= pf->vf_num) {
2973 rte_flow_error_set(error, EINVAL,
2974 RTE_FLOW_ERROR_TYPE_ACTION,
2975 act, "Invalid VF ID for tunnel filter");
2980 /* Check if the next non-void item is QUEUE */
2982 NEXT_ITEM_OF_ACTION(act, actions, index);
2983 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2984 act_q = (const struct rte_flow_action_queue *)act->conf;
2985 filter->queue_id = act_q->index;
2986 if ((!filter->is_to_vf) &&
2987 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
2988 rte_flow_error_set(error, EINVAL,
2989 RTE_FLOW_ERROR_TYPE_ACTION,
2990 act, "Invalid queue ID for tunnel filter");
2992 } else if (filter->is_to_vf &&
2993 (filter->queue_id >= pf->vf_nb_qps)) {
2994 rte_flow_error_set(error, EINVAL,
2995 RTE_FLOW_ERROR_TYPE_ACTION,
2996 act, "Invalid queue ID for tunnel filter");
3001 /* Check if the next non-void item is END */
3003 NEXT_ITEM_OF_ACTION(act, actions, index);
3004 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3005 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3006 act, "Not supported action.");
3013 static uint16_t i40e_supported_tunnel_filter_types[] = {
3014 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3015 ETH_TUNNEL_FILTER_IVLAN,
3016 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3017 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3018 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3019 ETH_TUNNEL_FILTER_IMAC,
3020 ETH_TUNNEL_FILTER_IMAC,
3024 i40e_check_tunnel_filter_type(uint8_t filter_type)
3028 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3029 if (filter_type == i40e_supported_tunnel_filter_types[i])
3036 /* 1. Last in item should be NULL as range is not supported.
3037 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3038 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3039 * 3. Mask of fields which need to be matched should be
3041 * 4. Mask of fields which needn't to be matched should be
3045 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3046 const struct rte_flow_item *pattern,
3047 struct rte_flow_error *error,
3048 struct i40e_tunnel_filter_conf *filter)
3050 const struct rte_flow_item *item = pattern;
3051 const struct rte_flow_item_eth *eth_spec;
3052 const struct rte_flow_item_eth *eth_mask;
3053 const struct rte_flow_item_vxlan *vxlan_spec;
3054 const struct rte_flow_item_vxlan *vxlan_mask;
3055 const struct rte_flow_item_vlan *vlan_spec;
3056 const struct rte_flow_item_vlan *vlan_mask;
3057 uint8_t filter_type = 0;
3058 bool is_vni_masked = 0;
3059 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3060 enum rte_flow_item_type item_type;
3061 bool vxlan_flag = 0;
3062 uint32_t tenant_id_be = 0;
3065 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3067 rte_flow_error_set(error, EINVAL,
3068 RTE_FLOW_ERROR_TYPE_ITEM,
3070 "Not support range");
3073 item_type = item->type;
3074 switch (item_type) {
3075 case RTE_FLOW_ITEM_TYPE_ETH:
3076 eth_spec = (const struct rte_flow_item_eth *)item->spec;
3077 eth_mask = (const struct rte_flow_item_eth *)item->mask;
3079 /* Check if ETH item is used for place holder.
3080 * If yes, both spec and mask should be NULL.
3081 * If no, both spec and mask shouldn't be NULL.
3083 if ((!eth_spec && eth_mask) ||
3084 (eth_spec && !eth_mask)) {
3085 rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ITEM,
3088 "Invalid ether spec/mask");
3092 if (eth_spec && eth_mask) {
3093 /* DST address of inner MAC shouldn't be masked.
3094 * SRC address of Inner MAC should be masked.
3096 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3097 !is_zero_ether_addr(ð_mask->src) ||
3099 rte_flow_error_set(error, EINVAL,
3100 RTE_FLOW_ERROR_TYPE_ITEM,
3102 "Invalid ether spec/mask");
3107 rte_memcpy(&filter->outer_mac,
3110 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3112 rte_memcpy(&filter->inner_mac,
3115 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3119 case RTE_FLOW_ITEM_TYPE_VLAN:
3121 (const struct rte_flow_item_vlan *)item->spec;
3123 (const struct rte_flow_item_vlan *)item->mask;
3124 if (!(vlan_spec && vlan_mask)) {
3125 rte_flow_error_set(error, EINVAL,
3126 RTE_FLOW_ERROR_TYPE_ITEM,
3128 "Invalid vlan item");
3132 if (vlan_spec && vlan_mask) {
3133 if (vlan_mask->tci ==
3134 rte_cpu_to_be_16(I40E_TCI_MASK))
3135 filter->inner_vlan =
3136 rte_be_to_cpu_16(vlan_spec->tci) &
3138 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3141 case RTE_FLOW_ITEM_TYPE_IPV4:
3142 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3143 /* IPv4 is used to describe protocol,
3144 * spec and mask should be NULL.
3146 if (item->spec || item->mask) {
3147 rte_flow_error_set(error, EINVAL,
3148 RTE_FLOW_ERROR_TYPE_ITEM,
3150 "Invalid IPv4 item");
3154 case RTE_FLOW_ITEM_TYPE_IPV6:
3155 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3156 /* IPv6 is used to describe protocol,
3157 * spec and mask should be NULL.
3159 if (item->spec || item->mask) {
3160 rte_flow_error_set(error, EINVAL,
3161 RTE_FLOW_ERROR_TYPE_ITEM,
3163 "Invalid IPv6 item");
3167 case RTE_FLOW_ITEM_TYPE_UDP:
3168 /* UDP is used to describe protocol,
3169 * spec and mask should be NULL.
3171 if (item->spec || item->mask) {
3172 rte_flow_error_set(error, EINVAL,
3173 RTE_FLOW_ERROR_TYPE_ITEM,
3175 "Invalid UDP item");
3179 case RTE_FLOW_ITEM_TYPE_VXLAN:
3181 (const struct rte_flow_item_vxlan *)item->spec;
3183 (const struct rte_flow_item_vxlan *)item->mask;
3184 /* Check if VXLAN item is used to describe protocol.
3185 * If yes, both spec and mask should be NULL.
3186 * If no, both spec and mask shouldn't be NULL.
3188 if ((!vxlan_spec && vxlan_mask) ||
3189 (vxlan_spec && !vxlan_mask)) {
3190 rte_flow_error_set(error, EINVAL,
3191 RTE_FLOW_ERROR_TYPE_ITEM,
3193 "Invalid VXLAN item");
3197 /* Check if VNI is masked. */
3198 if (vxlan_spec && vxlan_mask) {
3200 !!memcmp(vxlan_mask->vni, vni_mask,
3202 if (is_vni_masked) {
3203 rte_flow_error_set(error, EINVAL,
3204 RTE_FLOW_ERROR_TYPE_ITEM,
3206 "Invalid VNI mask");
3210 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3211 vxlan_spec->vni, 3);
3213 rte_be_to_cpu_32(tenant_id_be);
3214 filter_type |= ETH_TUNNEL_FILTER_TENID;
3224 ret = i40e_check_tunnel_filter_type(filter_type);
3226 rte_flow_error_set(error, EINVAL,
3227 RTE_FLOW_ERROR_TYPE_ITEM,
3229 "Invalid filter type");
3232 filter->filter_type = filter_type;
3234 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3240 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3241 const struct rte_flow_attr *attr,
3242 const struct rte_flow_item pattern[],
3243 const struct rte_flow_action actions[],
3244 struct rte_flow_error *error,
3245 union i40e_filter_t *filter)
3247 struct i40e_tunnel_filter_conf *tunnel_filter =
3248 &filter->consistent_tunnel_filter;
3251 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3252 error, tunnel_filter);
3256 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3260 ret = i40e_flow_parse_attr(attr, error);
3264 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3269 /* 1. Last in item should be NULL as range is not supported.
3270 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3271 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3272 * 3. Mask of fields which need to be matched should be
3274 * 4. Mask of fields which needn't to be matched should be
3278 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3279 const struct rte_flow_item *pattern,
3280 struct rte_flow_error *error,
3281 struct i40e_tunnel_filter_conf *filter)
3283 const struct rte_flow_item *item = pattern;
3284 const struct rte_flow_item_eth *eth_spec;
3285 const struct rte_flow_item_eth *eth_mask;
3286 const struct rte_flow_item_nvgre *nvgre_spec;
3287 const struct rte_flow_item_nvgre *nvgre_mask;
3288 const struct rte_flow_item_vlan *vlan_spec;
3289 const struct rte_flow_item_vlan *vlan_mask;
3290 enum rte_flow_item_type item_type;
3291 uint8_t filter_type = 0;
3292 bool is_tni_masked = 0;
3293 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3294 bool nvgre_flag = 0;
3295 uint32_t tenant_id_be = 0;
3298 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3300 rte_flow_error_set(error, EINVAL,
3301 RTE_FLOW_ERROR_TYPE_ITEM,
3303 "Not support range");
3306 item_type = item->type;
3307 switch (item_type) {
3308 case RTE_FLOW_ITEM_TYPE_ETH:
3309 eth_spec = (const struct rte_flow_item_eth *)item->spec;
3310 eth_mask = (const struct rte_flow_item_eth *)item->mask;
3312 /* Check if ETH item is used for place holder.
3313 * If yes, both spec and mask should be NULL.
3314 * If no, both spec and mask shouldn't be NULL.
3316 if ((!eth_spec && eth_mask) ||
3317 (eth_spec && !eth_mask)) {
3318 rte_flow_error_set(error, EINVAL,
3319 RTE_FLOW_ERROR_TYPE_ITEM,
3321 "Invalid ether spec/mask");
3325 if (eth_spec && eth_mask) {
3326 /* DST address of inner MAC shouldn't be masked.
3327 * SRC address of Inner MAC should be masked.
3329 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3330 !is_zero_ether_addr(ð_mask->src) ||
3332 rte_flow_error_set(error, EINVAL,
3333 RTE_FLOW_ERROR_TYPE_ITEM,
3335 "Invalid ether spec/mask");
3340 rte_memcpy(&filter->outer_mac,
3343 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3345 rte_memcpy(&filter->inner_mac,
3348 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3353 case RTE_FLOW_ITEM_TYPE_VLAN:
3355 (const struct rte_flow_item_vlan *)item->spec;
3357 (const struct rte_flow_item_vlan *)item->mask;
3358 if (!(vlan_spec && vlan_mask)) {
3359 rte_flow_error_set(error, EINVAL,
3360 RTE_FLOW_ERROR_TYPE_ITEM,
3362 "Invalid vlan item");
3366 if (vlan_spec && vlan_mask) {
3367 if (vlan_mask->tci ==
3368 rte_cpu_to_be_16(I40E_TCI_MASK))
3369 filter->inner_vlan =
3370 rte_be_to_cpu_16(vlan_spec->tci) &
3372 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3375 case RTE_FLOW_ITEM_TYPE_IPV4:
3376 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3377 /* IPv4 is used to describe protocol,
3378 * spec and mask should be NULL.
3380 if (item->spec || item->mask) {
3381 rte_flow_error_set(error, EINVAL,
3382 RTE_FLOW_ERROR_TYPE_ITEM,
3384 "Invalid IPv4 item");
3388 case RTE_FLOW_ITEM_TYPE_IPV6:
3389 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3390 /* IPv6 is used to describe protocol,
3391 * spec and mask should be NULL.
3393 if (item->spec || item->mask) {
3394 rte_flow_error_set(error, EINVAL,
3395 RTE_FLOW_ERROR_TYPE_ITEM,
3397 "Invalid IPv6 item");
3401 case RTE_FLOW_ITEM_TYPE_NVGRE:
3403 (const struct rte_flow_item_nvgre *)item->spec;
3405 (const struct rte_flow_item_nvgre *)item->mask;
3406 /* Check if NVGRE item is used to describe protocol.
3407 * If yes, both spec and mask should be NULL.
3408 * If no, both spec and mask shouldn't be NULL.
3410 if ((!nvgre_spec && nvgre_mask) ||
3411 (nvgre_spec && !nvgre_mask)) {
3412 rte_flow_error_set(error, EINVAL,
3413 RTE_FLOW_ERROR_TYPE_ITEM,
3415 "Invalid NVGRE item");
3419 if (nvgre_spec && nvgre_mask) {
3421 !!memcmp(nvgre_mask->tni, tni_mask,
3423 if (is_tni_masked) {
3424 rte_flow_error_set(error, EINVAL,
3425 RTE_FLOW_ERROR_TYPE_ITEM,
3427 "Invalid TNI mask");
3430 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3431 nvgre_spec->tni, 3);
3433 rte_be_to_cpu_32(tenant_id_be);
3434 filter_type |= ETH_TUNNEL_FILTER_TENID;
3444 ret = i40e_check_tunnel_filter_type(filter_type);
3446 rte_flow_error_set(error, EINVAL,
3447 RTE_FLOW_ERROR_TYPE_ITEM,
3449 "Invalid filter type");
3452 filter->filter_type = filter_type;
3454 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3460 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3461 const struct rte_flow_attr *attr,
3462 const struct rte_flow_item pattern[],
3463 const struct rte_flow_action actions[],
3464 struct rte_flow_error *error,
3465 union i40e_filter_t *filter)
3467 struct i40e_tunnel_filter_conf *tunnel_filter =
3468 &filter->consistent_tunnel_filter;
3471 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3472 error, tunnel_filter);
3476 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3480 ret = i40e_flow_parse_attr(attr, error);
3484 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3489 /* 1. Last in item should be NULL as range is not supported.
3490 * 2. Supported filter types: MPLS label.
3491 * 3. Mask of fields which need to be matched should be
3493 * 4. Mask of fields which needn't to be matched should be
3497 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3498 const struct rte_flow_item *pattern,
3499 struct rte_flow_error *error,
3500 struct i40e_tunnel_filter_conf *filter)
3502 const struct rte_flow_item *item = pattern;
3503 const struct rte_flow_item_mpls *mpls_spec;
3504 const struct rte_flow_item_mpls *mpls_mask;
3505 enum rte_flow_item_type item_type;
3506 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3507 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3508 uint32_t label_be = 0;
3510 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3512 rte_flow_error_set(error, EINVAL,
3513 RTE_FLOW_ERROR_TYPE_ITEM,
3515 "Not support range");
3518 item_type = item->type;
3519 switch (item_type) {
3520 case RTE_FLOW_ITEM_TYPE_ETH:
3521 if (item->spec || item->mask) {
3522 rte_flow_error_set(error, EINVAL,
3523 RTE_FLOW_ERROR_TYPE_ITEM,
3525 "Invalid ETH item");
3529 case RTE_FLOW_ITEM_TYPE_IPV4:
3530 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3531 /* IPv4 is used to describe protocol,
3532 * spec and mask should be NULL.
3534 if (item->spec || item->mask) {
3535 rte_flow_error_set(error, EINVAL,
3536 RTE_FLOW_ERROR_TYPE_ITEM,
3538 "Invalid IPv4 item");
3542 case RTE_FLOW_ITEM_TYPE_IPV6:
3543 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3544 /* IPv6 is used to describe protocol,
3545 * spec and mask should be NULL.
3547 if (item->spec || item->mask) {
3548 rte_flow_error_set(error, EINVAL,
3549 RTE_FLOW_ERROR_TYPE_ITEM,
3551 "Invalid IPv6 item");
3555 case RTE_FLOW_ITEM_TYPE_UDP:
3556 /* UDP is used to describe protocol,
3557 * spec and mask should be NULL.
3559 if (item->spec || item->mask) {
3560 rte_flow_error_set(error, EINVAL,
3561 RTE_FLOW_ERROR_TYPE_ITEM,
3563 "Invalid UDP item");
3568 case RTE_FLOW_ITEM_TYPE_GRE:
3569 /* GRE is used to describe protocol,
3570 * spec and mask should be NULL.
3572 if (item->spec || item->mask) {
3573 rte_flow_error_set(error, EINVAL,
3574 RTE_FLOW_ERROR_TYPE_ITEM,
3576 "Invalid GRE item");
3580 case RTE_FLOW_ITEM_TYPE_MPLS:
3582 (const struct rte_flow_item_mpls *)item->spec;
3584 (const struct rte_flow_item_mpls *)item->mask;
3586 if (!mpls_spec || !mpls_mask) {
3587 rte_flow_error_set(error, EINVAL,
3588 RTE_FLOW_ERROR_TYPE_ITEM,
3590 "Invalid MPLS item");
3594 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3595 rte_flow_error_set(error, EINVAL,
3596 RTE_FLOW_ERROR_TYPE_ITEM,
3598 "Invalid MPLS label mask");
3601 rte_memcpy(((uint8_t *)&label_be + 1),
3602 mpls_spec->label_tc_s, 3);
3603 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3611 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3613 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3619 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3620 const struct rte_flow_attr *attr,
3621 const struct rte_flow_item pattern[],
3622 const struct rte_flow_action actions[],
3623 struct rte_flow_error *error,
3624 union i40e_filter_t *filter)
3626 struct i40e_tunnel_filter_conf *tunnel_filter =
3627 &filter->consistent_tunnel_filter;
3630 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3631 error, tunnel_filter);
3635 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3639 ret = i40e_flow_parse_attr(attr, error);
3643 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3648 /* 1. Last in item should be NULL as range is not supported.
3649 * 2. Supported filter types: QINQ.
3650 * 3. Mask of fields which need to be matched should be
3652 * 4. Mask of fields which needn't to be matched should be
3656 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3657 const struct rte_flow_item *pattern,
3658 struct rte_flow_error *error,
3659 struct i40e_tunnel_filter_conf *filter)
3661 const struct rte_flow_item *item = pattern;
3662 const struct rte_flow_item_vlan *vlan_spec = NULL;
3663 const struct rte_flow_item_vlan *vlan_mask = NULL;
3664 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3665 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3666 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3667 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3669 enum rte_flow_item_type item_type;
3672 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3674 rte_flow_error_set(error, EINVAL,
3675 RTE_FLOW_ERROR_TYPE_ITEM,
3677 "Not support range");
3680 item_type = item->type;
3681 switch (item_type) {
3682 case RTE_FLOW_ITEM_TYPE_ETH:
3683 if (item->spec || item->mask) {
3684 rte_flow_error_set(error, EINVAL,
3685 RTE_FLOW_ERROR_TYPE_ITEM,
3687 "Invalid ETH item");
3691 case RTE_FLOW_ITEM_TYPE_VLAN:
3693 (const struct rte_flow_item_vlan *)item->spec;
3695 (const struct rte_flow_item_vlan *)item->mask;
3697 if (!(vlan_spec && vlan_mask)) {
3698 rte_flow_error_set(error, EINVAL,
3699 RTE_FLOW_ERROR_TYPE_ITEM,
3701 "Invalid vlan item");
3706 o_vlan_spec = vlan_spec;
3707 o_vlan_mask = vlan_mask;
3710 i_vlan_spec = vlan_spec;
3711 i_vlan_mask = vlan_mask;
3721 /* Get filter specification */
3722 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
3723 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
3724 (i_vlan_mask != NULL) &&
3725 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
3726 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
3728 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
3731 rte_flow_error_set(error, EINVAL,
3732 RTE_FLOW_ERROR_TYPE_ITEM,
3734 "Invalid filter type");
3738 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
3743 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
3744 const struct rte_flow_attr *attr,
3745 const struct rte_flow_item pattern[],
3746 const struct rte_flow_action actions[],
3747 struct rte_flow_error *error,
3748 union i40e_filter_t *filter)
3750 struct i40e_tunnel_filter_conf *tunnel_filter =
3751 &filter->consistent_tunnel_filter;
3754 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
3755 error, tunnel_filter);
3759 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3763 ret = i40e_flow_parse_attr(attr, error);
3767 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3773 i40e_flow_validate(struct rte_eth_dev *dev,
3774 const struct rte_flow_attr *attr,
3775 const struct rte_flow_item pattern[],
3776 const struct rte_flow_action actions[],
3777 struct rte_flow_error *error)
3779 struct rte_flow_item *items; /* internal pattern w/o VOID items */
3780 parse_filter_t parse_filter;
3781 uint32_t item_num = 0; /* non-void item number of pattern*/
3784 int ret = I40E_NOT_SUPPORTED;
3787 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
3788 NULL, "NULL pattern.");
3793 rte_flow_error_set(error, EINVAL,
3794 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
3795 NULL, "NULL action.");
3800 rte_flow_error_set(error, EINVAL,
3801 RTE_FLOW_ERROR_TYPE_ATTR,
3802 NULL, "NULL attribute.");
3806 memset(&cons_filter, 0, sizeof(cons_filter));
3808 /* Get the non-void item number of pattern */
3809 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
3810 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
3816 items = rte_zmalloc("i40e_pattern",
3817 item_num * sizeof(struct rte_flow_item), 0);
3819 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
3820 NULL, "No memory for PMD internal items.");
3824 i40e_pattern_skip_void_item(items, pattern);
3828 parse_filter = i40e_find_parse_filter_func(items, &i);
3829 if (!parse_filter && !flag) {
3830 rte_flow_error_set(error, EINVAL,
3831 RTE_FLOW_ERROR_TYPE_ITEM,
3832 pattern, "Unsupported pattern");
3837 ret = parse_filter(dev, attr, items, actions,
3838 error, &cons_filter);
3840 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
3847 static struct rte_flow *
3848 i40e_flow_create(struct rte_eth_dev *dev,
3849 const struct rte_flow_attr *attr,
3850 const struct rte_flow_item pattern[],
3851 const struct rte_flow_action actions[],
3852 struct rte_flow_error *error)
3854 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3855 struct rte_flow *flow;
3858 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
3860 rte_flow_error_set(error, ENOMEM,
3861 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
3862 "Failed to allocate memory");
3866 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
3870 switch (cons_filter_type) {
3871 case RTE_ETH_FILTER_ETHERTYPE:
3872 ret = i40e_ethertype_filter_set(pf,
3873 &cons_filter.ethertype_filter, 1);
3876 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
3877 i40e_ethertype_filter_list);
3879 case RTE_ETH_FILTER_FDIR:
3880 ret = i40e_add_del_fdir_filter(dev,
3881 &cons_filter.fdir_filter, 1);
3884 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
3885 i40e_fdir_filter_list);
3887 case RTE_ETH_FILTER_TUNNEL:
3888 ret = i40e_dev_consistent_tunnel_filter_set(pf,
3889 &cons_filter.consistent_tunnel_filter, 1);
3892 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
3893 i40e_tunnel_filter_list);
3899 flow->filter_type = cons_filter_type;
3900 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
3904 rte_flow_error_set(error, -ret,
3905 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
3906 "Failed to create flow.");
3912 i40e_flow_destroy(struct rte_eth_dev *dev,
3913 struct rte_flow *flow,
3914 struct rte_flow_error *error)
3916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3917 enum rte_filter_type filter_type = flow->filter_type;
3920 switch (filter_type) {
3921 case RTE_ETH_FILTER_ETHERTYPE:
3922 ret = i40e_flow_destroy_ethertype_filter(pf,
3923 (struct i40e_ethertype_filter *)flow->rule);
3925 case RTE_ETH_FILTER_TUNNEL:
3926 ret = i40e_flow_destroy_tunnel_filter(pf,
3927 (struct i40e_tunnel_filter *)flow->rule);
3929 case RTE_ETH_FILTER_FDIR:
3930 ret = i40e_add_del_fdir_filter(dev,
3931 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
3934 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3941 TAILQ_REMOVE(&pf->flow_list, flow, node);
3944 rte_flow_error_set(error, -ret,
3945 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
3946 "Failed to destroy flow.");
3952 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
3953 struct i40e_ethertype_filter *filter)
3955 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
3957 struct i40e_ethertype_filter *node;
3958 struct i40e_control_filter_stats stats;
3962 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
3963 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
3964 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
3965 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
3966 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
3968 memset(&stats, 0, sizeof(stats));
3969 ret = i40e_aq_add_rem_control_packet_filter(hw,
3970 filter->input.mac_addr.addr_bytes,
3971 filter->input.ether_type,
3972 flags, pf->main_vsi->seid,
3973 filter->queue, 0, &stats, NULL);
3977 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
3981 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
3987 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
3988 struct i40e_tunnel_filter *filter)
3990 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3991 struct i40e_vsi *vsi;
3992 struct i40e_pf_vf *vf;
3993 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
3994 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
3995 struct i40e_tunnel_filter *node;
3996 bool big_buffer = 0;
3999 memset(&cld_filter, 0, sizeof(cld_filter));
4000 ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4001 (struct ether_addr *)&cld_filter.element.outer_mac);
4002 ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4003 (struct ether_addr *)&cld_filter.element.inner_mac);
4004 cld_filter.element.inner_vlan = filter->input.inner_vlan;
4005 cld_filter.element.flags = filter->input.flags;
4006 cld_filter.element.tenant_id = filter->input.tenant_id;
4007 cld_filter.element.queue_number = filter->queue;
4008 rte_memcpy(cld_filter.general_fields,
4009 filter->input.general_fields,
4010 sizeof(cld_filter.general_fields));
4012 if (!filter->is_to_vf)
4015 vf = &pf->vfs[filter->vf_id];
4019 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
4020 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
4021 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
4022 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
4023 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
4024 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
4028 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4031 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4032 &cld_filter.element, 1);
4036 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4040 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4046 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4051 ret = i40e_flow_flush_fdir_filter(pf);
4053 rte_flow_error_set(error, -ret,
4054 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4055 "Failed to flush FDIR flows.");
4059 ret = i40e_flow_flush_ethertype_filter(pf);
4061 rte_flow_error_set(error, -ret,
4062 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4063 "Failed to ethertype flush flows.");
4067 ret = i40e_flow_flush_tunnel_filter(pf);
4069 rte_flow_error_set(error, -ret,
4070 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4071 "Failed to flush tunnel flows.");
4079 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4081 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4082 struct i40e_fdir_info *fdir_info = &pf->fdir;
4083 struct i40e_fdir_filter *fdir_filter;
4084 struct rte_flow *flow;
4088 ret = i40e_fdir_flush(dev);
4090 /* Delete FDIR filters in FDIR list. */
4091 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4092 ret = i40e_sw_fdir_filter_del(pf,
4093 &fdir_filter->fdir.input);
4098 /* Delete FDIR flows in flow list. */
4099 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4100 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4101 TAILQ_REMOVE(&pf->flow_list, flow, node);
4110 /* Flush all ethertype filters */
4112 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4114 struct i40e_ethertype_filter_list
4115 *ethertype_list = &pf->ethertype.ethertype_list;
4116 struct i40e_ethertype_filter *filter;
4117 struct rte_flow *flow;
4121 while ((filter = TAILQ_FIRST(ethertype_list))) {
4122 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4127 /* Delete ethertype flows in flow list. */
4128 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4129 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4130 TAILQ_REMOVE(&pf->flow_list, flow, node);
4138 /* Flush all tunnel filters */
4140 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4142 struct i40e_tunnel_filter_list
4143 *tunnel_list = &pf->tunnel.tunnel_list;
4144 struct i40e_tunnel_filter *filter;
4145 struct rte_flow *flow;
4149 while ((filter = TAILQ_FIRST(tunnel_list))) {
4150 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4155 /* Delete tunnel flows in flow list. */
4156 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4157 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4158 TAILQ_REMOVE(&pf->flow_list, flow, node);