1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
13 #include <rte_debug.h>
14 #include <rte_ether.h>
15 #include <rte_ethdev_driver.h>
17 #include <rte_malloc.h>
18 #include <rte_eth_ctrl.h>
19 #include <rte_tailq.h>
20 #include <rte_flow_driver.h>
22 #include "i40e_logs.h"
23 #include "base/i40e_type.h"
24 #include "base/i40e_prototype.h"
25 #include "i40e_ethdev.h"
27 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
28 #define I40E_IPV6_FRAG_HEADER 44
29 #define I40E_TENANT_ARRAY_NUM 3
30 #define I40E_TCI_MASK 0xFFFF
32 static int i40e_flow_validate(struct rte_eth_dev *dev,
33 const struct rte_flow_attr *attr,
34 const struct rte_flow_item pattern[],
35 const struct rte_flow_action actions[],
36 struct rte_flow_error *error);
37 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
38 const struct rte_flow_attr *attr,
39 const struct rte_flow_item pattern[],
40 const struct rte_flow_action actions[],
41 struct rte_flow_error *error);
42 static int i40e_flow_destroy(struct rte_eth_dev *dev,
43 struct rte_flow *flow,
44 struct rte_flow_error *error);
45 static int i40e_flow_flush(struct rte_eth_dev *dev,
46 struct rte_flow_error *error);
48 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
49 const struct rte_flow_item *pattern,
50 struct rte_flow_error *error,
51 struct rte_eth_ethertype_filter *filter);
52 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
53 const struct rte_flow_action *actions,
54 struct rte_flow_error *error,
55 struct rte_eth_ethertype_filter *filter);
56 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
57 const struct rte_flow_attr *attr,
58 const struct rte_flow_item *pattern,
59 struct rte_flow_error *error,
60 struct i40e_fdir_filter_conf *filter);
61 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
62 const struct rte_flow_action *actions,
63 struct rte_flow_error *error,
64 struct i40e_fdir_filter_conf *filter);
65 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
66 const struct rte_flow_action *actions,
67 struct rte_flow_error *error,
68 struct i40e_tunnel_filter_conf *filter);
69 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
70 struct rte_flow_error *error);
71 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
72 const struct rte_flow_attr *attr,
73 const struct rte_flow_item pattern[],
74 const struct rte_flow_action actions[],
75 struct rte_flow_error *error,
76 union i40e_filter_t *filter);
77 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
78 const struct rte_flow_attr *attr,
79 const struct rte_flow_item pattern[],
80 const struct rte_flow_action actions[],
81 struct rte_flow_error *error,
82 union i40e_filter_t *filter);
83 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
84 const struct rte_flow_attr *attr,
85 const struct rte_flow_item pattern[],
86 const struct rte_flow_action actions[],
87 struct rte_flow_error *error,
88 union i40e_filter_t *filter);
89 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
90 const struct rte_flow_attr *attr,
91 const struct rte_flow_item pattern[],
92 const struct rte_flow_action actions[],
93 struct rte_flow_error *error,
94 union i40e_filter_t *filter);
95 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
96 const struct rte_flow_attr *attr,
97 const struct rte_flow_item pattern[],
98 const struct rte_flow_action actions[],
99 struct rte_flow_error *error,
100 union i40e_filter_t *filter);
101 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
102 const struct rte_flow_attr *attr,
103 const struct rte_flow_item pattern[],
104 const struct rte_flow_action actions[],
105 struct rte_flow_error *error,
106 union i40e_filter_t *filter);
107 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
108 struct i40e_ethertype_filter *filter);
109 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
110 struct i40e_tunnel_filter *filter);
111 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
112 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
113 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
115 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
117 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
118 const struct rte_flow_attr *attr,
119 const struct rte_flow_item pattern[],
120 const struct rte_flow_action actions[],
121 struct rte_flow_error *error,
122 union i40e_filter_t *filter);
124 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
125 const struct rte_flow_item *pattern,
126 struct rte_flow_error *error,
127 struct i40e_tunnel_filter_conf *filter);
129 const struct rte_flow_ops i40e_flow_ops = {
130 .validate = i40e_flow_validate,
131 .create = i40e_flow_create,
132 .destroy = i40e_flow_destroy,
133 .flush = i40e_flow_flush,
136 union i40e_filter_t cons_filter;
137 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
139 /* Pattern matched ethertype filter */
140 static enum rte_flow_item_type pattern_ethertype[] = {
141 RTE_FLOW_ITEM_TYPE_ETH,
142 RTE_FLOW_ITEM_TYPE_END,
145 /* Pattern matched flow director filter */
146 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
147 RTE_FLOW_ITEM_TYPE_ETH,
148 RTE_FLOW_ITEM_TYPE_IPV4,
149 RTE_FLOW_ITEM_TYPE_END,
152 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
153 RTE_FLOW_ITEM_TYPE_ETH,
154 RTE_FLOW_ITEM_TYPE_IPV4,
155 RTE_FLOW_ITEM_TYPE_UDP,
156 RTE_FLOW_ITEM_TYPE_END,
159 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
160 RTE_FLOW_ITEM_TYPE_ETH,
161 RTE_FLOW_ITEM_TYPE_IPV4,
162 RTE_FLOW_ITEM_TYPE_TCP,
163 RTE_FLOW_ITEM_TYPE_END,
166 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
167 RTE_FLOW_ITEM_TYPE_ETH,
168 RTE_FLOW_ITEM_TYPE_IPV4,
169 RTE_FLOW_ITEM_TYPE_SCTP,
170 RTE_FLOW_ITEM_TYPE_END,
173 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
174 RTE_FLOW_ITEM_TYPE_ETH,
175 RTE_FLOW_ITEM_TYPE_IPV4,
176 RTE_FLOW_ITEM_TYPE_UDP,
177 RTE_FLOW_ITEM_TYPE_GTPC,
178 RTE_FLOW_ITEM_TYPE_END,
181 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
182 RTE_FLOW_ITEM_TYPE_ETH,
183 RTE_FLOW_ITEM_TYPE_IPV4,
184 RTE_FLOW_ITEM_TYPE_UDP,
185 RTE_FLOW_ITEM_TYPE_GTPU,
186 RTE_FLOW_ITEM_TYPE_END,
189 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
190 RTE_FLOW_ITEM_TYPE_ETH,
191 RTE_FLOW_ITEM_TYPE_IPV4,
192 RTE_FLOW_ITEM_TYPE_UDP,
193 RTE_FLOW_ITEM_TYPE_GTPU,
194 RTE_FLOW_ITEM_TYPE_IPV4,
195 RTE_FLOW_ITEM_TYPE_END,
198 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
199 RTE_FLOW_ITEM_TYPE_ETH,
200 RTE_FLOW_ITEM_TYPE_IPV4,
201 RTE_FLOW_ITEM_TYPE_UDP,
202 RTE_FLOW_ITEM_TYPE_GTPU,
203 RTE_FLOW_ITEM_TYPE_IPV6,
204 RTE_FLOW_ITEM_TYPE_END,
207 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
208 RTE_FLOW_ITEM_TYPE_ETH,
209 RTE_FLOW_ITEM_TYPE_IPV6,
210 RTE_FLOW_ITEM_TYPE_END,
213 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
214 RTE_FLOW_ITEM_TYPE_ETH,
215 RTE_FLOW_ITEM_TYPE_IPV6,
216 RTE_FLOW_ITEM_TYPE_UDP,
217 RTE_FLOW_ITEM_TYPE_END,
220 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
221 RTE_FLOW_ITEM_TYPE_ETH,
222 RTE_FLOW_ITEM_TYPE_IPV6,
223 RTE_FLOW_ITEM_TYPE_TCP,
224 RTE_FLOW_ITEM_TYPE_END,
227 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
228 RTE_FLOW_ITEM_TYPE_ETH,
229 RTE_FLOW_ITEM_TYPE_IPV6,
230 RTE_FLOW_ITEM_TYPE_SCTP,
231 RTE_FLOW_ITEM_TYPE_END,
234 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
235 RTE_FLOW_ITEM_TYPE_ETH,
236 RTE_FLOW_ITEM_TYPE_IPV6,
237 RTE_FLOW_ITEM_TYPE_UDP,
238 RTE_FLOW_ITEM_TYPE_GTPC,
239 RTE_FLOW_ITEM_TYPE_END,
242 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
243 RTE_FLOW_ITEM_TYPE_ETH,
244 RTE_FLOW_ITEM_TYPE_IPV6,
245 RTE_FLOW_ITEM_TYPE_UDP,
246 RTE_FLOW_ITEM_TYPE_GTPU,
247 RTE_FLOW_ITEM_TYPE_END,
250 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
251 RTE_FLOW_ITEM_TYPE_ETH,
252 RTE_FLOW_ITEM_TYPE_IPV6,
253 RTE_FLOW_ITEM_TYPE_UDP,
254 RTE_FLOW_ITEM_TYPE_GTPU,
255 RTE_FLOW_ITEM_TYPE_IPV4,
256 RTE_FLOW_ITEM_TYPE_END,
259 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
260 RTE_FLOW_ITEM_TYPE_ETH,
261 RTE_FLOW_ITEM_TYPE_IPV6,
262 RTE_FLOW_ITEM_TYPE_UDP,
263 RTE_FLOW_ITEM_TYPE_GTPU,
264 RTE_FLOW_ITEM_TYPE_IPV6,
265 RTE_FLOW_ITEM_TYPE_END,
268 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
269 RTE_FLOW_ITEM_TYPE_ETH,
270 RTE_FLOW_ITEM_TYPE_RAW,
271 RTE_FLOW_ITEM_TYPE_END,
274 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
275 RTE_FLOW_ITEM_TYPE_ETH,
276 RTE_FLOW_ITEM_TYPE_RAW,
277 RTE_FLOW_ITEM_TYPE_RAW,
278 RTE_FLOW_ITEM_TYPE_END,
281 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
282 RTE_FLOW_ITEM_TYPE_ETH,
283 RTE_FLOW_ITEM_TYPE_RAW,
284 RTE_FLOW_ITEM_TYPE_RAW,
285 RTE_FLOW_ITEM_TYPE_RAW,
286 RTE_FLOW_ITEM_TYPE_END,
289 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
290 RTE_FLOW_ITEM_TYPE_ETH,
291 RTE_FLOW_ITEM_TYPE_IPV4,
292 RTE_FLOW_ITEM_TYPE_RAW,
293 RTE_FLOW_ITEM_TYPE_END,
296 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
297 RTE_FLOW_ITEM_TYPE_ETH,
298 RTE_FLOW_ITEM_TYPE_IPV4,
299 RTE_FLOW_ITEM_TYPE_RAW,
300 RTE_FLOW_ITEM_TYPE_RAW,
301 RTE_FLOW_ITEM_TYPE_END,
304 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
305 RTE_FLOW_ITEM_TYPE_ETH,
306 RTE_FLOW_ITEM_TYPE_IPV4,
307 RTE_FLOW_ITEM_TYPE_RAW,
308 RTE_FLOW_ITEM_TYPE_RAW,
309 RTE_FLOW_ITEM_TYPE_RAW,
310 RTE_FLOW_ITEM_TYPE_END,
313 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
314 RTE_FLOW_ITEM_TYPE_ETH,
315 RTE_FLOW_ITEM_TYPE_IPV4,
316 RTE_FLOW_ITEM_TYPE_UDP,
317 RTE_FLOW_ITEM_TYPE_RAW,
318 RTE_FLOW_ITEM_TYPE_END,
321 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
322 RTE_FLOW_ITEM_TYPE_ETH,
323 RTE_FLOW_ITEM_TYPE_IPV4,
324 RTE_FLOW_ITEM_TYPE_UDP,
325 RTE_FLOW_ITEM_TYPE_RAW,
326 RTE_FLOW_ITEM_TYPE_RAW,
327 RTE_FLOW_ITEM_TYPE_END,
330 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
331 RTE_FLOW_ITEM_TYPE_ETH,
332 RTE_FLOW_ITEM_TYPE_IPV4,
333 RTE_FLOW_ITEM_TYPE_UDP,
334 RTE_FLOW_ITEM_TYPE_RAW,
335 RTE_FLOW_ITEM_TYPE_RAW,
336 RTE_FLOW_ITEM_TYPE_RAW,
337 RTE_FLOW_ITEM_TYPE_END,
340 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
341 RTE_FLOW_ITEM_TYPE_ETH,
342 RTE_FLOW_ITEM_TYPE_IPV4,
343 RTE_FLOW_ITEM_TYPE_TCP,
344 RTE_FLOW_ITEM_TYPE_RAW,
345 RTE_FLOW_ITEM_TYPE_END,
348 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
349 RTE_FLOW_ITEM_TYPE_ETH,
350 RTE_FLOW_ITEM_TYPE_IPV4,
351 RTE_FLOW_ITEM_TYPE_TCP,
352 RTE_FLOW_ITEM_TYPE_RAW,
353 RTE_FLOW_ITEM_TYPE_RAW,
354 RTE_FLOW_ITEM_TYPE_END,
357 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
358 RTE_FLOW_ITEM_TYPE_ETH,
359 RTE_FLOW_ITEM_TYPE_IPV4,
360 RTE_FLOW_ITEM_TYPE_TCP,
361 RTE_FLOW_ITEM_TYPE_RAW,
362 RTE_FLOW_ITEM_TYPE_RAW,
363 RTE_FLOW_ITEM_TYPE_RAW,
364 RTE_FLOW_ITEM_TYPE_END,
367 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
368 RTE_FLOW_ITEM_TYPE_ETH,
369 RTE_FLOW_ITEM_TYPE_IPV4,
370 RTE_FLOW_ITEM_TYPE_SCTP,
371 RTE_FLOW_ITEM_TYPE_RAW,
372 RTE_FLOW_ITEM_TYPE_END,
375 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
376 RTE_FLOW_ITEM_TYPE_ETH,
377 RTE_FLOW_ITEM_TYPE_IPV4,
378 RTE_FLOW_ITEM_TYPE_SCTP,
379 RTE_FLOW_ITEM_TYPE_RAW,
380 RTE_FLOW_ITEM_TYPE_RAW,
381 RTE_FLOW_ITEM_TYPE_END,
384 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
385 RTE_FLOW_ITEM_TYPE_ETH,
386 RTE_FLOW_ITEM_TYPE_IPV4,
387 RTE_FLOW_ITEM_TYPE_SCTP,
388 RTE_FLOW_ITEM_TYPE_RAW,
389 RTE_FLOW_ITEM_TYPE_RAW,
390 RTE_FLOW_ITEM_TYPE_RAW,
391 RTE_FLOW_ITEM_TYPE_END,
394 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
395 RTE_FLOW_ITEM_TYPE_ETH,
396 RTE_FLOW_ITEM_TYPE_IPV6,
397 RTE_FLOW_ITEM_TYPE_RAW,
398 RTE_FLOW_ITEM_TYPE_END,
401 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
402 RTE_FLOW_ITEM_TYPE_ETH,
403 RTE_FLOW_ITEM_TYPE_IPV6,
404 RTE_FLOW_ITEM_TYPE_RAW,
405 RTE_FLOW_ITEM_TYPE_RAW,
406 RTE_FLOW_ITEM_TYPE_END,
409 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
410 RTE_FLOW_ITEM_TYPE_ETH,
411 RTE_FLOW_ITEM_TYPE_IPV6,
412 RTE_FLOW_ITEM_TYPE_RAW,
413 RTE_FLOW_ITEM_TYPE_RAW,
414 RTE_FLOW_ITEM_TYPE_RAW,
415 RTE_FLOW_ITEM_TYPE_END,
418 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
419 RTE_FLOW_ITEM_TYPE_ETH,
420 RTE_FLOW_ITEM_TYPE_IPV6,
421 RTE_FLOW_ITEM_TYPE_UDP,
422 RTE_FLOW_ITEM_TYPE_RAW,
423 RTE_FLOW_ITEM_TYPE_END,
426 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
427 RTE_FLOW_ITEM_TYPE_ETH,
428 RTE_FLOW_ITEM_TYPE_IPV6,
429 RTE_FLOW_ITEM_TYPE_UDP,
430 RTE_FLOW_ITEM_TYPE_RAW,
431 RTE_FLOW_ITEM_TYPE_RAW,
432 RTE_FLOW_ITEM_TYPE_END,
435 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
436 RTE_FLOW_ITEM_TYPE_ETH,
437 RTE_FLOW_ITEM_TYPE_IPV6,
438 RTE_FLOW_ITEM_TYPE_UDP,
439 RTE_FLOW_ITEM_TYPE_RAW,
440 RTE_FLOW_ITEM_TYPE_RAW,
441 RTE_FLOW_ITEM_TYPE_RAW,
442 RTE_FLOW_ITEM_TYPE_END,
445 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
446 RTE_FLOW_ITEM_TYPE_ETH,
447 RTE_FLOW_ITEM_TYPE_IPV6,
448 RTE_FLOW_ITEM_TYPE_TCP,
449 RTE_FLOW_ITEM_TYPE_RAW,
450 RTE_FLOW_ITEM_TYPE_END,
453 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
454 RTE_FLOW_ITEM_TYPE_ETH,
455 RTE_FLOW_ITEM_TYPE_IPV6,
456 RTE_FLOW_ITEM_TYPE_TCP,
457 RTE_FLOW_ITEM_TYPE_RAW,
458 RTE_FLOW_ITEM_TYPE_RAW,
459 RTE_FLOW_ITEM_TYPE_END,
462 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
463 RTE_FLOW_ITEM_TYPE_ETH,
464 RTE_FLOW_ITEM_TYPE_IPV6,
465 RTE_FLOW_ITEM_TYPE_TCP,
466 RTE_FLOW_ITEM_TYPE_RAW,
467 RTE_FLOW_ITEM_TYPE_RAW,
468 RTE_FLOW_ITEM_TYPE_RAW,
469 RTE_FLOW_ITEM_TYPE_END,
472 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
473 RTE_FLOW_ITEM_TYPE_ETH,
474 RTE_FLOW_ITEM_TYPE_IPV6,
475 RTE_FLOW_ITEM_TYPE_SCTP,
476 RTE_FLOW_ITEM_TYPE_RAW,
477 RTE_FLOW_ITEM_TYPE_END,
480 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
481 RTE_FLOW_ITEM_TYPE_ETH,
482 RTE_FLOW_ITEM_TYPE_IPV6,
483 RTE_FLOW_ITEM_TYPE_SCTP,
484 RTE_FLOW_ITEM_TYPE_RAW,
485 RTE_FLOW_ITEM_TYPE_RAW,
486 RTE_FLOW_ITEM_TYPE_END,
489 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
490 RTE_FLOW_ITEM_TYPE_ETH,
491 RTE_FLOW_ITEM_TYPE_IPV6,
492 RTE_FLOW_ITEM_TYPE_SCTP,
493 RTE_FLOW_ITEM_TYPE_RAW,
494 RTE_FLOW_ITEM_TYPE_RAW,
495 RTE_FLOW_ITEM_TYPE_RAW,
496 RTE_FLOW_ITEM_TYPE_END,
499 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
500 RTE_FLOW_ITEM_TYPE_ETH,
501 RTE_FLOW_ITEM_TYPE_VLAN,
502 RTE_FLOW_ITEM_TYPE_END,
505 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
506 RTE_FLOW_ITEM_TYPE_ETH,
507 RTE_FLOW_ITEM_TYPE_VLAN,
508 RTE_FLOW_ITEM_TYPE_IPV4,
509 RTE_FLOW_ITEM_TYPE_END,
512 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
513 RTE_FLOW_ITEM_TYPE_ETH,
514 RTE_FLOW_ITEM_TYPE_VLAN,
515 RTE_FLOW_ITEM_TYPE_IPV4,
516 RTE_FLOW_ITEM_TYPE_UDP,
517 RTE_FLOW_ITEM_TYPE_END,
520 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
521 RTE_FLOW_ITEM_TYPE_ETH,
522 RTE_FLOW_ITEM_TYPE_VLAN,
523 RTE_FLOW_ITEM_TYPE_IPV4,
524 RTE_FLOW_ITEM_TYPE_TCP,
525 RTE_FLOW_ITEM_TYPE_END,
528 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
529 RTE_FLOW_ITEM_TYPE_ETH,
530 RTE_FLOW_ITEM_TYPE_VLAN,
531 RTE_FLOW_ITEM_TYPE_IPV4,
532 RTE_FLOW_ITEM_TYPE_SCTP,
533 RTE_FLOW_ITEM_TYPE_END,
536 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
537 RTE_FLOW_ITEM_TYPE_ETH,
538 RTE_FLOW_ITEM_TYPE_VLAN,
539 RTE_FLOW_ITEM_TYPE_IPV6,
540 RTE_FLOW_ITEM_TYPE_END,
543 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
544 RTE_FLOW_ITEM_TYPE_ETH,
545 RTE_FLOW_ITEM_TYPE_VLAN,
546 RTE_FLOW_ITEM_TYPE_IPV6,
547 RTE_FLOW_ITEM_TYPE_UDP,
548 RTE_FLOW_ITEM_TYPE_END,
551 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
552 RTE_FLOW_ITEM_TYPE_ETH,
553 RTE_FLOW_ITEM_TYPE_VLAN,
554 RTE_FLOW_ITEM_TYPE_IPV6,
555 RTE_FLOW_ITEM_TYPE_TCP,
556 RTE_FLOW_ITEM_TYPE_END,
559 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
560 RTE_FLOW_ITEM_TYPE_ETH,
561 RTE_FLOW_ITEM_TYPE_VLAN,
562 RTE_FLOW_ITEM_TYPE_IPV6,
563 RTE_FLOW_ITEM_TYPE_SCTP,
564 RTE_FLOW_ITEM_TYPE_END,
567 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
568 RTE_FLOW_ITEM_TYPE_ETH,
569 RTE_FLOW_ITEM_TYPE_VLAN,
570 RTE_FLOW_ITEM_TYPE_RAW,
571 RTE_FLOW_ITEM_TYPE_END,
574 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
575 RTE_FLOW_ITEM_TYPE_ETH,
576 RTE_FLOW_ITEM_TYPE_VLAN,
577 RTE_FLOW_ITEM_TYPE_RAW,
578 RTE_FLOW_ITEM_TYPE_RAW,
579 RTE_FLOW_ITEM_TYPE_END,
582 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
583 RTE_FLOW_ITEM_TYPE_ETH,
584 RTE_FLOW_ITEM_TYPE_VLAN,
585 RTE_FLOW_ITEM_TYPE_RAW,
586 RTE_FLOW_ITEM_TYPE_RAW,
587 RTE_FLOW_ITEM_TYPE_RAW,
588 RTE_FLOW_ITEM_TYPE_END,
591 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
592 RTE_FLOW_ITEM_TYPE_ETH,
593 RTE_FLOW_ITEM_TYPE_VLAN,
594 RTE_FLOW_ITEM_TYPE_IPV4,
595 RTE_FLOW_ITEM_TYPE_RAW,
596 RTE_FLOW_ITEM_TYPE_END,
599 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
600 RTE_FLOW_ITEM_TYPE_ETH,
601 RTE_FLOW_ITEM_TYPE_VLAN,
602 RTE_FLOW_ITEM_TYPE_IPV4,
603 RTE_FLOW_ITEM_TYPE_RAW,
604 RTE_FLOW_ITEM_TYPE_RAW,
605 RTE_FLOW_ITEM_TYPE_END,
608 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
609 RTE_FLOW_ITEM_TYPE_ETH,
610 RTE_FLOW_ITEM_TYPE_VLAN,
611 RTE_FLOW_ITEM_TYPE_IPV4,
612 RTE_FLOW_ITEM_TYPE_RAW,
613 RTE_FLOW_ITEM_TYPE_RAW,
614 RTE_FLOW_ITEM_TYPE_RAW,
615 RTE_FLOW_ITEM_TYPE_END,
618 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
619 RTE_FLOW_ITEM_TYPE_ETH,
620 RTE_FLOW_ITEM_TYPE_VLAN,
621 RTE_FLOW_ITEM_TYPE_IPV4,
622 RTE_FLOW_ITEM_TYPE_UDP,
623 RTE_FLOW_ITEM_TYPE_RAW,
624 RTE_FLOW_ITEM_TYPE_END,
627 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
628 RTE_FLOW_ITEM_TYPE_ETH,
629 RTE_FLOW_ITEM_TYPE_VLAN,
630 RTE_FLOW_ITEM_TYPE_IPV4,
631 RTE_FLOW_ITEM_TYPE_UDP,
632 RTE_FLOW_ITEM_TYPE_RAW,
633 RTE_FLOW_ITEM_TYPE_RAW,
634 RTE_FLOW_ITEM_TYPE_END,
637 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
638 RTE_FLOW_ITEM_TYPE_ETH,
639 RTE_FLOW_ITEM_TYPE_VLAN,
640 RTE_FLOW_ITEM_TYPE_IPV4,
641 RTE_FLOW_ITEM_TYPE_UDP,
642 RTE_FLOW_ITEM_TYPE_RAW,
643 RTE_FLOW_ITEM_TYPE_RAW,
644 RTE_FLOW_ITEM_TYPE_RAW,
645 RTE_FLOW_ITEM_TYPE_END,
648 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
649 RTE_FLOW_ITEM_TYPE_ETH,
650 RTE_FLOW_ITEM_TYPE_VLAN,
651 RTE_FLOW_ITEM_TYPE_IPV4,
652 RTE_FLOW_ITEM_TYPE_TCP,
653 RTE_FLOW_ITEM_TYPE_RAW,
654 RTE_FLOW_ITEM_TYPE_END,
657 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
658 RTE_FLOW_ITEM_TYPE_ETH,
659 RTE_FLOW_ITEM_TYPE_VLAN,
660 RTE_FLOW_ITEM_TYPE_IPV4,
661 RTE_FLOW_ITEM_TYPE_TCP,
662 RTE_FLOW_ITEM_TYPE_RAW,
663 RTE_FLOW_ITEM_TYPE_RAW,
664 RTE_FLOW_ITEM_TYPE_END,
667 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
668 RTE_FLOW_ITEM_TYPE_ETH,
669 RTE_FLOW_ITEM_TYPE_VLAN,
670 RTE_FLOW_ITEM_TYPE_IPV4,
671 RTE_FLOW_ITEM_TYPE_TCP,
672 RTE_FLOW_ITEM_TYPE_RAW,
673 RTE_FLOW_ITEM_TYPE_RAW,
674 RTE_FLOW_ITEM_TYPE_RAW,
675 RTE_FLOW_ITEM_TYPE_END,
678 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
679 RTE_FLOW_ITEM_TYPE_ETH,
680 RTE_FLOW_ITEM_TYPE_VLAN,
681 RTE_FLOW_ITEM_TYPE_IPV4,
682 RTE_FLOW_ITEM_TYPE_SCTP,
683 RTE_FLOW_ITEM_TYPE_RAW,
684 RTE_FLOW_ITEM_TYPE_END,
687 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
688 RTE_FLOW_ITEM_TYPE_ETH,
689 RTE_FLOW_ITEM_TYPE_VLAN,
690 RTE_FLOW_ITEM_TYPE_IPV4,
691 RTE_FLOW_ITEM_TYPE_SCTP,
692 RTE_FLOW_ITEM_TYPE_RAW,
693 RTE_FLOW_ITEM_TYPE_RAW,
694 RTE_FLOW_ITEM_TYPE_END,
697 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
698 RTE_FLOW_ITEM_TYPE_ETH,
699 RTE_FLOW_ITEM_TYPE_VLAN,
700 RTE_FLOW_ITEM_TYPE_IPV4,
701 RTE_FLOW_ITEM_TYPE_SCTP,
702 RTE_FLOW_ITEM_TYPE_RAW,
703 RTE_FLOW_ITEM_TYPE_RAW,
704 RTE_FLOW_ITEM_TYPE_RAW,
705 RTE_FLOW_ITEM_TYPE_END,
708 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
709 RTE_FLOW_ITEM_TYPE_ETH,
710 RTE_FLOW_ITEM_TYPE_VLAN,
711 RTE_FLOW_ITEM_TYPE_IPV6,
712 RTE_FLOW_ITEM_TYPE_RAW,
713 RTE_FLOW_ITEM_TYPE_END,
716 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
717 RTE_FLOW_ITEM_TYPE_ETH,
718 RTE_FLOW_ITEM_TYPE_VLAN,
719 RTE_FLOW_ITEM_TYPE_IPV6,
720 RTE_FLOW_ITEM_TYPE_RAW,
721 RTE_FLOW_ITEM_TYPE_RAW,
722 RTE_FLOW_ITEM_TYPE_END,
725 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
726 RTE_FLOW_ITEM_TYPE_ETH,
727 RTE_FLOW_ITEM_TYPE_VLAN,
728 RTE_FLOW_ITEM_TYPE_IPV6,
729 RTE_FLOW_ITEM_TYPE_RAW,
730 RTE_FLOW_ITEM_TYPE_RAW,
731 RTE_FLOW_ITEM_TYPE_RAW,
732 RTE_FLOW_ITEM_TYPE_END,
735 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
736 RTE_FLOW_ITEM_TYPE_ETH,
737 RTE_FLOW_ITEM_TYPE_VLAN,
738 RTE_FLOW_ITEM_TYPE_IPV6,
739 RTE_FLOW_ITEM_TYPE_UDP,
740 RTE_FLOW_ITEM_TYPE_RAW,
741 RTE_FLOW_ITEM_TYPE_END,
744 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
745 RTE_FLOW_ITEM_TYPE_ETH,
746 RTE_FLOW_ITEM_TYPE_VLAN,
747 RTE_FLOW_ITEM_TYPE_IPV6,
748 RTE_FLOW_ITEM_TYPE_UDP,
749 RTE_FLOW_ITEM_TYPE_RAW,
750 RTE_FLOW_ITEM_TYPE_RAW,
751 RTE_FLOW_ITEM_TYPE_END,
754 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
755 RTE_FLOW_ITEM_TYPE_ETH,
756 RTE_FLOW_ITEM_TYPE_VLAN,
757 RTE_FLOW_ITEM_TYPE_IPV6,
758 RTE_FLOW_ITEM_TYPE_UDP,
759 RTE_FLOW_ITEM_TYPE_RAW,
760 RTE_FLOW_ITEM_TYPE_RAW,
761 RTE_FLOW_ITEM_TYPE_RAW,
762 RTE_FLOW_ITEM_TYPE_END,
765 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
766 RTE_FLOW_ITEM_TYPE_ETH,
767 RTE_FLOW_ITEM_TYPE_VLAN,
768 RTE_FLOW_ITEM_TYPE_IPV6,
769 RTE_FLOW_ITEM_TYPE_TCP,
770 RTE_FLOW_ITEM_TYPE_RAW,
771 RTE_FLOW_ITEM_TYPE_END,
774 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
775 RTE_FLOW_ITEM_TYPE_ETH,
776 RTE_FLOW_ITEM_TYPE_VLAN,
777 RTE_FLOW_ITEM_TYPE_IPV6,
778 RTE_FLOW_ITEM_TYPE_TCP,
779 RTE_FLOW_ITEM_TYPE_RAW,
780 RTE_FLOW_ITEM_TYPE_RAW,
781 RTE_FLOW_ITEM_TYPE_END,
784 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
785 RTE_FLOW_ITEM_TYPE_ETH,
786 RTE_FLOW_ITEM_TYPE_VLAN,
787 RTE_FLOW_ITEM_TYPE_IPV6,
788 RTE_FLOW_ITEM_TYPE_TCP,
789 RTE_FLOW_ITEM_TYPE_RAW,
790 RTE_FLOW_ITEM_TYPE_RAW,
791 RTE_FLOW_ITEM_TYPE_RAW,
792 RTE_FLOW_ITEM_TYPE_END,
795 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
796 RTE_FLOW_ITEM_TYPE_ETH,
797 RTE_FLOW_ITEM_TYPE_VLAN,
798 RTE_FLOW_ITEM_TYPE_IPV6,
799 RTE_FLOW_ITEM_TYPE_SCTP,
800 RTE_FLOW_ITEM_TYPE_RAW,
801 RTE_FLOW_ITEM_TYPE_END,
804 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
805 RTE_FLOW_ITEM_TYPE_ETH,
806 RTE_FLOW_ITEM_TYPE_VLAN,
807 RTE_FLOW_ITEM_TYPE_IPV6,
808 RTE_FLOW_ITEM_TYPE_SCTP,
809 RTE_FLOW_ITEM_TYPE_RAW,
810 RTE_FLOW_ITEM_TYPE_RAW,
811 RTE_FLOW_ITEM_TYPE_END,
814 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
815 RTE_FLOW_ITEM_TYPE_ETH,
816 RTE_FLOW_ITEM_TYPE_VLAN,
817 RTE_FLOW_ITEM_TYPE_IPV6,
818 RTE_FLOW_ITEM_TYPE_SCTP,
819 RTE_FLOW_ITEM_TYPE_RAW,
820 RTE_FLOW_ITEM_TYPE_RAW,
821 RTE_FLOW_ITEM_TYPE_RAW,
822 RTE_FLOW_ITEM_TYPE_END,
825 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
826 RTE_FLOW_ITEM_TYPE_ETH,
827 RTE_FLOW_ITEM_TYPE_IPV4,
828 RTE_FLOW_ITEM_TYPE_VF,
829 RTE_FLOW_ITEM_TYPE_END,
832 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
833 RTE_FLOW_ITEM_TYPE_ETH,
834 RTE_FLOW_ITEM_TYPE_IPV4,
835 RTE_FLOW_ITEM_TYPE_UDP,
836 RTE_FLOW_ITEM_TYPE_VF,
837 RTE_FLOW_ITEM_TYPE_END,
840 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
841 RTE_FLOW_ITEM_TYPE_ETH,
842 RTE_FLOW_ITEM_TYPE_IPV4,
843 RTE_FLOW_ITEM_TYPE_TCP,
844 RTE_FLOW_ITEM_TYPE_VF,
845 RTE_FLOW_ITEM_TYPE_END,
848 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
849 RTE_FLOW_ITEM_TYPE_ETH,
850 RTE_FLOW_ITEM_TYPE_IPV4,
851 RTE_FLOW_ITEM_TYPE_SCTP,
852 RTE_FLOW_ITEM_TYPE_VF,
853 RTE_FLOW_ITEM_TYPE_END,
856 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
857 RTE_FLOW_ITEM_TYPE_ETH,
858 RTE_FLOW_ITEM_TYPE_IPV6,
859 RTE_FLOW_ITEM_TYPE_VF,
860 RTE_FLOW_ITEM_TYPE_END,
863 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
864 RTE_FLOW_ITEM_TYPE_ETH,
865 RTE_FLOW_ITEM_TYPE_IPV6,
866 RTE_FLOW_ITEM_TYPE_UDP,
867 RTE_FLOW_ITEM_TYPE_VF,
868 RTE_FLOW_ITEM_TYPE_END,
871 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
872 RTE_FLOW_ITEM_TYPE_ETH,
873 RTE_FLOW_ITEM_TYPE_IPV6,
874 RTE_FLOW_ITEM_TYPE_TCP,
875 RTE_FLOW_ITEM_TYPE_VF,
876 RTE_FLOW_ITEM_TYPE_END,
879 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
880 RTE_FLOW_ITEM_TYPE_ETH,
881 RTE_FLOW_ITEM_TYPE_IPV6,
882 RTE_FLOW_ITEM_TYPE_SCTP,
883 RTE_FLOW_ITEM_TYPE_VF,
884 RTE_FLOW_ITEM_TYPE_END,
887 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
888 RTE_FLOW_ITEM_TYPE_ETH,
889 RTE_FLOW_ITEM_TYPE_RAW,
890 RTE_FLOW_ITEM_TYPE_VF,
891 RTE_FLOW_ITEM_TYPE_END,
894 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
895 RTE_FLOW_ITEM_TYPE_ETH,
896 RTE_FLOW_ITEM_TYPE_RAW,
897 RTE_FLOW_ITEM_TYPE_RAW,
898 RTE_FLOW_ITEM_TYPE_VF,
899 RTE_FLOW_ITEM_TYPE_END,
902 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
903 RTE_FLOW_ITEM_TYPE_ETH,
904 RTE_FLOW_ITEM_TYPE_RAW,
905 RTE_FLOW_ITEM_TYPE_RAW,
906 RTE_FLOW_ITEM_TYPE_RAW,
907 RTE_FLOW_ITEM_TYPE_VF,
908 RTE_FLOW_ITEM_TYPE_END,
911 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
912 RTE_FLOW_ITEM_TYPE_ETH,
913 RTE_FLOW_ITEM_TYPE_IPV4,
914 RTE_FLOW_ITEM_TYPE_RAW,
915 RTE_FLOW_ITEM_TYPE_VF,
916 RTE_FLOW_ITEM_TYPE_END,
919 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
920 RTE_FLOW_ITEM_TYPE_ETH,
921 RTE_FLOW_ITEM_TYPE_IPV4,
922 RTE_FLOW_ITEM_TYPE_RAW,
923 RTE_FLOW_ITEM_TYPE_RAW,
924 RTE_FLOW_ITEM_TYPE_VF,
925 RTE_FLOW_ITEM_TYPE_END,
928 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
929 RTE_FLOW_ITEM_TYPE_ETH,
930 RTE_FLOW_ITEM_TYPE_IPV4,
931 RTE_FLOW_ITEM_TYPE_RAW,
932 RTE_FLOW_ITEM_TYPE_RAW,
933 RTE_FLOW_ITEM_TYPE_RAW,
934 RTE_FLOW_ITEM_TYPE_VF,
935 RTE_FLOW_ITEM_TYPE_END,
938 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
939 RTE_FLOW_ITEM_TYPE_ETH,
940 RTE_FLOW_ITEM_TYPE_IPV4,
941 RTE_FLOW_ITEM_TYPE_UDP,
942 RTE_FLOW_ITEM_TYPE_RAW,
943 RTE_FLOW_ITEM_TYPE_VF,
944 RTE_FLOW_ITEM_TYPE_END,
947 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
948 RTE_FLOW_ITEM_TYPE_ETH,
949 RTE_FLOW_ITEM_TYPE_IPV4,
950 RTE_FLOW_ITEM_TYPE_UDP,
951 RTE_FLOW_ITEM_TYPE_RAW,
952 RTE_FLOW_ITEM_TYPE_RAW,
953 RTE_FLOW_ITEM_TYPE_VF,
954 RTE_FLOW_ITEM_TYPE_END,
957 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
958 RTE_FLOW_ITEM_TYPE_ETH,
959 RTE_FLOW_ITEM_TYPE_IPV4,
960 RTE_FLOW_ITEM_TYPE_UDP,
961 RTE_FLOW_ITEM_TYPE_RAW,
962 RTE_FLOW_ITEM_TYPE_RAW,
963 RTE_FLOW_ITEM_TYPE_RAW,
964 RTE_FLOW_ITEM_TYPE_VF,
965 RTE_FLOW_ITEM_TYPE_END,
968 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
969 RTE_FLOW_ITEM_TYPE_ETH,
970 RTE_FLOW_ITEM_TYPE_IPV4,
971 RTE_FLOW_ITEM_TYPE_TCP,
972 RTE_FLOW_ITEM_TYPE_RAW,
973 RTE_FLOW_ITEM_TYPE_VF,
974 RTE_FLOW_ITEM_TYPE_END,
977 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
978 RTE_FLOW_ITEM_TYPE_ETH,
979 RTE_FLOW_ITEM_TYPE_IPV4,
980 RTE_FLOW_ITEM_TYPE_TCP,
981 RTE_FLOW_ITEM_TYPE_RAW,
982 RTE_FLOW_ITEM_TYPE_RAW,
983 RTE_FLOW_ITEM_TYPE_VF,
984 RTE_FLOW_ITEM_TYPE_END,
987 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
988 RTE_FLOW_ITEM_TYPE_ETH,
989 RTE_FLOW_ITEM_TYPE_IPV4,
990 RTE_FLOW_ITEM_TYPE_TCP,
991 RTE_FLOW_ITEM_TYPE_RAW,
992 RTE_FLOW_ITEM_TYPE_RAW,
993 RTE_FLOW_ITEM_TYPE_RAW,
994 RTE_FLOW_ITEM_TYPE_VF,
995 RTE_FLOW_ITEM_TYPE_END,
998 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
999 RTE_FLOW_ITEM_TYPE_ETH,
1000 RTE_FLOW_ITEM_TYPE_IPV4,
1001 RTE_FLOW_ITEM_TYPE_SCTP,
1002 RTE_FLOW_ITEM_TYPE_RAW,
1003 RTE_FLOW_ITEM_TYPE_VF,
1004 RTE_FLOW_ITEM_TYPE_END,
1007 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1008 RTE_FLOW_ITEM_TYPE_ETH,
1009 RTE_FLOW_ITEM_TYPE_IPV4,
1010 RTE_FLOW_ITEM_TYPE_SCTP,
1011 RTE_FLOW_ITEM_TYPE_RAW,
1012 RTE_FLOW_ITEM_TYPE_RAW,
1013 RTE_FLOW_ITEM_TYPE_VF,
1014 RTE_FLOW_ITEM_TYPE_END,
1017 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1018 RTE_FLOW_ITEM_TYPE_ETH,
1019 RTE_FLOW_ITEM_TYPE_IPV4,
1020 RTE_FLOW_ITEM_TYPE_SCTP,
1021 RTE_FLOW_ITEM_TYPE_RAW,
1022 RTE_FLOW_ITEM_TYPE_RAW,
1023 RTE_FLOW_ITEM_TYPE_RAW,
1024 RTE_FLOW_ITEM_TYPE_VF,
1025 RTE_FLOW_ITEM_TYPE_END,
1028 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1029 RTE_FLOW_ITEM_TYPE_ETH,
1030 RTE_FLOW_ITEM_TYPE_IPV6,
1031 RTE_FLOW_ITEM_TYPE_RAW,
1032 RTE_FLOW_ITEM_TYPE_VF,
1033 RTE_FLOW_ITEM_TYPE_END,
1036 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1037 RTE_FLOW_ITEM_TYPE_ETH,
1038 RTE_FLOW_ITEM_TYPE_IPV6,
1039 RTE_FLOW_ITEM_TYPE_RAW,
1040 RTE_FLOW_ITEM_TYPE_RAW,
1041 RTE_FLOW_ITEM_TYPE_VF,
1042 RTE_FLOW_ITEM_TYPE_END,
1045 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1046 RTE_FLOW_ITEM_TYPE_ETH,
1047 RTE_FLOW_ITEM_TYPE_IPV6,
1048 RTE_FLOW_ITEM_TYPE_RAW,
1049 RTE_FLOW_ITEM_TYPE_RAW,
1050 RTE_FLOW_ITEM_TYPE_RAW,
1051 RTE_FLOW_ITEM_TYPE_VF,
1052 RTE_FLOW_ITEM_TYPE_END,
1055 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1056 RTE_FLOW_ITEM_TYPE_ETH,
1057 RTE_FLOW_ITEM_TYPE_IPV6,
1058 RTE_FLOW_ITEM_TYPE_UDP,
1059 RTE_FLOW_ITEM_TYPE_RAW,
1060 RTE_FLOW_ITEM_TYPE_VF,
1061 RTE_FLOW_ITEM_TYPE_END,
1064 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1065 RTE_FLOW_ITEM_TYPE_ETH,
1066 RTE_FLOW_ITEM_TYPE_IPV6,
1067 RTE_FLOW_ITEM_TYPE_UDP,
1068 RTE_FLOW_ITEM_TYPE_RAW,
1069 RTE_FLOW_ITEM_TYPE_RAW,
1070 RTE_FLOW_ITEM_TYPE_VF,
1071 RTE_FLOW_ITEM_TYPE_END,
1074 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1075 RTE_FLOW_ITEM_TYPE_ETH,
1076 RTE_FLOW_ITEM_TYPE_IPV6,
1077 RTE_FLOW_ITEM_TYPE_UDP,
1078 RTE_FLOW_ITEM_TYPE_RAW,
1079 RTE_FLOW_ITEM_TYPE_RAW,
1080 RTE_FLOW_ITEM_TYPE_RAW,
1081 RTE_FLOW_ITEM_TYPE_VF,
1082 RTE_FLOW_ITEM_TYPE_END,
1085 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1086 RTE_FLOW_ITEM_TYPE_ETH,
1087 RTE_FLOW_ITEM_TYPE_IPV6,
1088 RTE_FLOW_ITEM_TYPE_TCP,
1089 RTE_FLOW_ITEM_TYPE_RAW,
1090 RTE_FLOW_ITEM_TYPE_VF,
1091 RTE_FLOW_ITEM_TYPE_END,
1094 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1095 RTE_FLOW_ITEM_TYPE_ETH,
1096 RTE_FLOW_ITEM_TYPE_IPV6,
1097 RTE_FLOW_ITEM_TYPE_TCP,
1098 RTE_FLOW_ITEM_TYPE_RAW,
1099 RTE_FLOW_ITEM_TYPE_RAW,
1100 RTE_FLOW_ITEM_TYPE_VF,
1101 RTE_FLOW_ITEM_TYPE_END,
1104 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1105 RTE_FLOW_ITEM_TYPE_ETH,
1106 RTE_FLOW_ITEM_TYPE_IPV6,
1107 RTE_FLOW_ITEM_TYPE_TCP,
1108 RTE_FLOW_ITEM_TYPE_RAW,
1109 RTE_FLOW_ITEM_TYPE_RAW,
1110 RTE_FLOW_ITEM_TYPE_RAW,
1111 RTE_FLOW_ITEM_TYPE_VF,
1112 RTE_FLOW_ITEM_TYPE_END,
1115 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1116 RTE_FLOW_ITEM_TYPE_ETH,
1117 RTE_FLOW_ITEM_TYPE_IPV6,
1118 RTE_FLOW_ITEM_TYPE_SCTP,
1119 RTE_FLOW_ITEM_TYPE_RAW,
1120 RTE_FLOW_ITEM_TYPE_VF,
1121 RTE_FLOW_ITEM_TYPE_END,
1124 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1125 RTE_FLOW_ITEM_TYPE_ETH,
1126 RTE_FLOW_ITEM_TYPE_IPV6,
1127 RTE_FLOW_ITEM_TYPE_SCTP,
1128 RTE_FLOW_ITEM_TYPE_RAW,
1129 RTE_FLOW_ITEM_TYPE_RAW,
1130 RTE_FLOW_ITEM_TYPE_VF,
1131 RTE_FLOW_ITEM_TYPE_END,
1134 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1135 RTE_FLOW_ITEM_TYPE_ETH,
1136 RTE_FLOW_ITEM_TYPE_IPV6,
1137 RTE_FLOW_ITEM_TYPE_SCTP,
1138 RTE_FLOW_ITEM_TYPE_RAW,
1139 RTE_FLOW_ITEM_TYPE_RAW,
1140 RTE_FLOW_ITEM_TYPE_RAW,
1141 RTE_FLOW_ITEM_TYPE_VF,
1142 RTE_FLOW_ITEM_TYPE_END,
1145 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1146 RTE_FLOW_ITEM_TYPE_ETH,
1147 RTE_FLOW_ITEM_TYPE_VLAN,
1148 RTE_FLOW_ITEM_TYPE_VF,
1149 RTE_FLOW_ITEM_TYPE_END,
1152 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1153 RTE_FLOW_ITEM_TYPE_ETH,
1154 RTE_FLOW_ITEM_TYPE_VLAN,
1155 RTE_FLOW_ITEM_TYPE_IPV4,
1156 RTE_FLOW_ITEM_TYPE_VF,
1157 RTE_FLOW_ITEM_TYPE_END,
1160 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1161 RTE_FLOW_ITEM_TYPE_ETH,
1162 RTE_FLOW_ITEM_TYPE_VLAN,
1163 RTE_FLOW_ITEM_TYPE_IPV4,
1164 RTE_FLOW_ITEM_TYPE_UDP,
1165 RTE_FLOW_ITEM_TYPE_VF,
1166 RTE_FLOW_ITEM_TYPE_END,
1169 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1170 RTE_FLOW_ITEM_TYPE_ETH,
1171 RTE_FLOW_ITEM_TYPE_VLAN,
1172 RTE_FLOW_ITEM_TYPE_IPV4,
1173 RTE_FLOW_ITEM_TYPE_TCP,
1174 RTE_FLOW_ITEM_TYPE_VF,
1175 RTE_FLOW_ITEM_TYPE_END,
1178 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1179 RTE_FLOW_ITEM_TYPE_ETH,
1180 RTE_FLOW_ITEM_TYPE_VLAN,
1181 RTE_FLOW_ITEM_TYPE_IPV4,
1182 RTE_FLOW_ITEM_TYPE_SCTP,
1183 RTE_FLOW_ITEM_TYPE_VF,
1184 RTE_FLOW_ITEM_TYPE_END,
1187 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1188 RTE_FLOW_ITEM_TYPE_ETH,
1189 RTE_FLOW_ITEM_TYPE_VLAN,
1190 RTE_FLOW_ITEM_TYPE_IPV6,
1191 RTE_FLOW_ITEM_TYPE_VF,
1192 RTE_FLOW_ITEM_TYPE_END,
1195 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1196 RTE_FLOW_ITEM_TYPE_ETH,
1197 RTE_FLOW_ITEM_TYPE_VLAN,
1198 RTE_FLOW_ITEM_TYPE_IPV6,
1199 RTE_FLOW_ITEM_TYPE_UDP,
1200 RTE_FLOW_ITEM_TYPE_VF,
1201 RTE_FLOW_ITEM_TYPE_END,
1204 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1205 RTE_FLOW_ITEM_TYPE_ETH,
1206 RTE_FLOW_ITEM_TYPE_VLAN,
1207 RTE_FLOW_ITEM_TYPE_IPV6,
1208 RTE_FLOW_ITEM_TYPE_TCP,
1209 RTE_FLOW_ITEM_TYPE_VF,
1210 RTE_FLOW_ITEM_TYPE_END,
1213 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1214 RTE_FLOW_ITEM_TYPE_ETH,
1215 RTE_FLOW_ITEM_TYPE_VLAN,
1216 RTE_FLOW_ITEM_TYPE_IPV6,
1217 RTE_FLOW_ITEM_TYPE_SCTP,
1218 RTE_FLOW_ITEM_TYPE_VF,
1219 RTE_FLOW_ITEM_TYPE_END,
1222 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1223 RTE_FLOW_ITEM_TYPE_ETH,
1224 RTE_FLOW_ITEM_TYPE_VLAN,
1225 RTE_FLOW_ITEM_TYPE_RAW,
1226 RTE_FLOW_ITEM_TYPE_VF,
1227 RTE_FLOW_ITEM_TYPE_END,
1230 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1231 RTE_FLOW_ITEM_TYPE_ETH,
1232 RTE_FLOW_ITEM_TYPE_VLAN,
1233 RTE_FLOW_ITEM_TYPE_RAW,
1234 RTE_FLOW_ITEM_TYPE_RAW,
1235 RTE_FLOW_ITEM_TYPE_VF,
1236 RTE_FLOW_ITEM_TYPE_END,
1239 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1240 RTE_FLOW_ITEM_TYPE_ETH,
1241 RTE_FLOW_ITEM_TYPE_VLAN,
1242 RTE_FLOW_ITEM_TYPE_RAW,
1243 RTE_FLOW_ITEM_TYPE_RAW,
1244 RTE_FLOW_ITEM_TYPE_RAW,
1245 RTE_FLOW_ITEM_TYPE_VF,
1246 RTE_FLOW_ITEM_TYPE_END,
1249 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1250 RTE_FLOW_ITEM_TYPE_ETH,
1251 RTE_FLOW_ITEM_TYPE_VLAN,
1252 RTE_FLOW_ITEM_TYPE_IPV4,
1253 RTE_FLOW_ITEM_TYPE_RAW,
1254 RTE_FLOW_ITEM_TYPE_VF,
1255 RTE_FLOW_ITEM_TYPE_END,
1258 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1259 RTE_FLOW_ITEM_TYPE_ETH,
1260 RTE_FLOW_ITEM_TYPE_VLAN,
1261 RTE_FLOW_ITEM_TYPE_IPV4,
1262 RTE_FLOW_ITEM_TYPE_RAW,
1263 RTE_FLOW_ITEM_TYPE_RAW,
1264 RTE_FLOW_ITEM_TYPE_VF,
1265 RTE_FLOW_ITEM_TYPE_END,
1268 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1269 RTE_FLOW_ITEM_TYPE_ETH,
1270 RTE_FLOW_ITEM_TYPE_VLAN,
1271 RTE_FLOW_ITEM_TYPE_IPV4,
1272 RTE_FLOW_ITEM_TYPE_RAW,
1273 RTE_FLOW_ITEM_TYPE_RAW,
1274 RTE_FLOW_ITEM_TYPE_RAW,
1275 RTE_FLOW_ITEM_TYPE_VF,
1276 RTE_FLOW_ITEM_TYPE_END,
1279 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1280 RTE_FLOW_ITEM_TYPE_ETH,
1281 RTE_FLOW_ITEM_TYPE_VLAN,
1282 RTE_FLOW_ITEM_TYPE_IPV4,
1283 RTE_FLOW_ITEM_TYPE_UDP,
1284 RTE_FLOW_ITEM_TYPE_RAW,
1285 RTE_FLOW_ITEM_TYPE_VF,
1286 RTE_FLOW_ITEM_TYPE_END,
1289 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1290 RTE_FLOW_ITEM_TYPE_ETH,
1291 RTE_FLOW_ITEM_TYPE_VLAN,
1292 RTE_FLOW_ITEM_TYPE_IPV4,
1293 RTE_FLOW_ITEM_TYPE_UDP,
1294 RTE_FLOW_ITEM_TYPE_RAW,
1295 RTE_FLOW_ITEM_TYPE_RAW,
1296 RTE_FLOW_ITEM_TYPE_VF,
1297 RTE_FLOW_ITEM_TYPE_END,
1300 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1301 RTE_FLOW_ITEM_TYPE_ETH,
1302 RTE_FLOW_ITEM_TYPE_VLAN,
1303 RTE_FLOW_ITEM_TYPE_IPV4,
1304 RTE_FLOW_ITEM_TYPE_UDP,
1305 RTE_FLOW_ITEM_TYPE_RAW,
1306 RTE_FLOW_ITEM_TYPE_RAW,
1307 RTE_FLOW_ITEM_TYPE_RAW,
1308 RTE_FLOW_ITEM_TYPE_VF,
1309 RTE_FLOW_ITEM_TYPE_END,
1312 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1313 RTE_FLOW_ITEM_TYPE_ETH,
1314 RTE_FLOW_ITEM_TYPE_VLAN,
1315 RTE_FLOW_ITEM_TYPE_IPV4,
1316 RTE_FLOW_ITEM_TYPE_TCP,
1317 RTE_FLOW_ITEM_TYPE_RAW,
1318 RTE_FLOW_ITEM_TYPE_VF,
1319 RTE_FLOW_ITEM_TYPE_END,
1322 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1323 RTE_FLOW_ITEM_TYPE_ETH,
1324 RTE_FLOW_ITEM_TYPE_VLAN,
1325 RTE_FLOW_ITEM_TYPE_IPV4,
1326 RTE_FLOW_ITEM_TYPE_TCP,
1327 RTE_FLOW_ITEM_TYPE_RAW,
1328 RTE_FLOW_ITEM_TYPE_RAW,
1329 RTE_FLOW_ITEM_TYPE_VF,
1330 RTE_FLOW_ITEM_TYPE_END,
1333 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1334 RTE_FLOW_ITEM_TYPE_ETH,
1335 RTE_FLOW_ITEM_TYPE_VLAN,
1336 RTE_FLOW_ITEM_TYPE_IPV4,
1337 RTE_FLOW_ITEM_TYPE_TCP,
1338 RTE_FLOW_ITEM_TYPE_RAW,
1339 RTE_FLOW_ITEM_TYPE_RAW,
1340 RTE_FLOW_ITEM_TYPE_RAW,
1341 RTE_FLOW_ITEM_TYPE_VF,
1342 RTE_FLOW_ITEM_TYPE_END,
1345 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1346 RTE_FLOW_ITEM_TYPE_ETH,
1347 RTE_FLOW_ITEM_TYPE_VLAN,
1348 RTE_FLOW_ITEM_TYPE_IPV4,
1349 RTE_FLOW_ITEM_TYPE_SCTP,
1350 RTE_FLOW_ITEM_TYPE_RAW,
1351 RTE_FLOW_ITEM_TYPE_VF,
1352 RTE_FLOW_ITEM_TYPE_END,
1355 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1356 RTE_FLOW_ITEM_TYPE_ETH,
1357 RTE_FLOW_ITEM_TYPE_VLAN,
1358 RTE_FLOW_ITEM_TYPE_IPV4,
1359 RTE_FLOW_ITEM_TYPE_SCTP,
1360 RTE_FLOW_ITEM_TYPE_RAW,
1361 RTE_FLOW_ITEM_TYPE_RAW,
1362 RTE_FLOW_ITEM_TYPE_VF,
1363 RTE_FLOW_ITEM_TYPE_END,
1366 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1367 RTE_FLOW_ITEM_TYPE_ETH,
1368 RTE_FLOW_ITEM_TYPE_VLAN,
1369 RTE_FLOW_ITEM_TYPE_IPV4,
1370 RTE_FLOW_ITEM_TYPE_SCTP,
1371 RTE_FLOW_ITEM_TYPE_RAW,
1372 RTE_FLOW_ITEM_TYPE_RAW,
1373 RTE_FLOW_ITEM_TYPE_RAW,
1374 RTE_FLOW_ITEM_TYPE_VF,
1375 RTE_FLOW_ITEM_TYPE_END,
1378 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1379 RTE_FLOW_ITEM_TYPE_ETH,
1380 RTE_FLOW_ITEM_TYPE_VLAN,
1381 RTE_FLOW_ITEM_TYPE_IPV6,
1382 RTE_FLOW_ITEM_TYPE_RAW,
1383 RTE_FLOW_ITEM_TYPE_VF,
1384 RTE_FLOW_ITEM_TYPE_END,
1387 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1388 RTE_FLOW_ITEM_TYPE_ETH,
1389 RTE_FLOW_ITEM_TYPE_VLAN,
1390 RTE_FLOW_ITEM_TYPE_IPV6,
1391 RTE_FLOW_ITEM_TYPE_RAW,
1392 RTE_FLOW_ITEM_TYPE_RAW,
1393 RTE_FLOW_ITEM_TYPE_VF,
1394 RTE_FLOW_ITEM_TYPE_END,
1397 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1398 RTE_FLOW_ITEM_TYPE_ETH,
1399 RTE_FLOW_ITEM_TYPE_VLAN,
1400 RTE_FLOW_ITEM_TYPE_IPV6,
1401 RTE_FLOW_ITEM_TYPE_RAW,
1402 RTE_FLOW_ITEM_TYPE_RAW,
1403 RTE_FLOW_ITEM_TYPE_RAW,
1404 RTE_FLOW_ITEM_TYPE_VF,
1405 RTE_FLOW_ITEM_TYPE_END,
1408 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1409 RTE_FLOW_ITEM_TYPE_ETH,
1410 RTE_FLOW_ITEM_TYPE_VLAN,
1411 RTE_FLOW_ITEM_TYPE_IPV6,
1412 RTE_FLOW_ITEM_TYPE_UDP,
1413 RTE_FLOW_ITEM_TYPE_RAW,
1414 RTE_FLOW_ITEM_TYPE_VF,
1415 RTE_FLOW_ITEM_TYPE_END,
1418 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1419 RTE_FLOW_ITEM_TYPE_ETH,
1420 RTE_FLOW_ITEM_TYPE_VLAN,
1421 RTE_FLOW_ITEM_TYPE_IPV6,
1422 RTE_FLOW_ITEM_TYPE_UDP,
1423 RTE_FLOW_ITEM_TYPE_RAW,
1424 RTE_FLOW_ITEM_TYPE_RAW,
1425 RTE_FLOW_ITEM_TYPE_VF,
1426 RTE_FLOW_ITEM_TYPE_END,
1429 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1430 RTE_FLOW_ITEM_TYPE_ETH,
1431 RTE_FLOW_ITEM_TYPE_VLAN,
1432 RTE_FLOW_ITEM_TYPE_IPV6,
1433 RTE_FLOW_ITEM_TYPE_UDP,
1434 RTE_FLOW_ITEM_TYPE_RAW,
1435 RTE_FLOW_ITEM_TYPE_RAW,
1436 RTE_FLOW_ITEM_TYPE_RAW,
1437 RTE_FLOW_ITEM_TYPE_VF,
1438 RTE_FLOW_ITEM_TYPE_END,
1441 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1442 RTE_FLOW_ITEM_TYPE_ETH,
1443 RTE_FLOW_ITEM_TYPE_VLAN,
1444 RTE_FLOW_ITEM_TYPE_IPV6,
1445 RTE_FLOW_ITEM_TYPE_TCP,
1446 RTE_FLOW_ITEM_TYPE_RAW,
1447 RTE_FLOW_ITEM_TYPE_VF,
1448 RTE_FLOW_ITEM_TYPE_END,
1451 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1452 RTE_FLOW_ITEM_TYPE_ETH,
1453 RTE_FLOW_ITEM_TYPE_VLAN,
1454 RTE_FLOW_ITEM_TYPE_IPV6,
1455 RTE_FLOW_ITEM_TYPE_TCP,
1456 RTE_FLOW_ITEM_TYPE_RAW,
1457 RTE_FLOW_ITEM_TYPE_RAW,
1458 RTE_FLOW_ITEM_TYPE_VF,
1459 RTE_FLOW_ITEM_TYPE_END,
1462 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1463 RTE_FLOW_ITEM_TYPE_ETH,
1464 RTE_FLOW_ITEM_TYPE_VLAN,
1465 RTE_FLOW_ITEM_TYPE_IPV6,
1466 RTE_FLOW_ITEM_TYPE_TCP,
1467 RTE_FLOW_ITEM_TYPE_RAW,
1468 RTE_FLOW_ITEM_TYPE_RAW,
1469 RTE_FLOW_ITEM_TYPE_RAW,
1470 RTE_FLOW_ITEM_TYPE_VF,
1471 RTE_FLOW_ITEM_TYPE_END,
1474 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1475 RTE_FLOW_ITEM_TYPE_ETH,
1476 RTE_FLOW_ITEM_TYPE_VLAN,
1477 RTE_FLOW_ITEM_TYPE_IPV6,
1478 RTE_FLOW_ITEM_TYPE_SCTP,
1479 RTE_FLOW_ITEM_TYPE_RAW,
1480 RTE_FLOW_ITEM_TYPE_VF,
1481 RTE_FLOW_ITEM_TYPE_END,
1484 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1485 RTE_FLOW_ITEM_TYPE_ETH,
1486 RTE_FLOW_ITEM_TYPE_VLAN,
1487 RTE_FLOW_ITEM_TYPE_IPV6,
1488 RTE_FLOW_ITEM_TYPE_SCTP,
1489 RTE_FLOW_ITEM_TYPE_RAW,
1490 RTE_FLOW_ITEM_TYPE_RAW,
1491 RTE_FLOW_ITEM_TYPE_VF,
1492 RTE_FLOW_ITEM_TYPE_END,
1495 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1496 RTE_FLOW_ITEM_TYPE_ETH,
1497 RTE_FLOW_ITEM_TYPE_VLAN,
1498 RTE_FLOW_ITEM_TYPE_IPV6,
1499 RTE_FLOW_ITEM_TYPE_SCTP,
1500 RTE_FLOW_ITEM_TYPE_RAW,
1501 RTE_FLOW_ITEM_TYPE_RAW,
1502 RTE_FLOW_ITEM_TYPE_RAW,
1503 RTE_FLOW_ITEM_TYPE_VF,
1504 RTE_FLOW_ITEM_TYPE_END,
1507 /* Pattern matched tunnel filter */
1508 static enum rte_flow_item_type pattern_vxlan_1[] = {
1509 RTE_FLOW_ITEM_TYPE_ETH,
1510 RTE_FLOW_ITEM_TYPE_IPV4,
1511 RTE_FLOW_ITEM_TYPE_UDP,
1512 RTE_FLOW_ITEM_TYPE_VXLAN,
1513 RTE_FLOW_ITEM_TYPE_ETH,
1514 RTE_FLOW_ITEM_TYPE_END,
1517 static enum rte_flow_item_type pattern_vxlan_2[] = {
1518 RTE_FLOW_ITEM_TYPE_ETH,
1519 RTE_FLOW_ITEM_TYPE_IPV6,
1520 RTE_FLOW_ITEM_TYPE_UDP,
1521 RTE_FLOW_ITEM_TYPE_VXLAN,
1522 RTE_FLOW_ITEM_TYPE_ETH,
1523 RTE_FLOW_ITEM_TYPE_END,
1526 static enum rte_flow_item_type pattern_vxlan_3[] = {
1527 RTE_FLOW_ITEM_TYPE_ETH,
1528 RTE_FLOW_ITEM_TYPE_IPV4,
1529 RTE_FLOW_ITEM_TYPE_UDP,
1530 RTE_FLOW_ITEM_TYPE_VXLAN,
1531 RTE_FLOW_ITEM_TYPE_ETH,
1532 RTE_FLOW_ITEM_TYPE_VLAN,
1533 RTE_FLOW_ITEM_TYPE_END,
1536 static enum rte_flow_item_type pattern_vxlan_4[] = {
1537 RTE_FLOW_ITEM_TYPE_ETH,
1538 RTE_FLOW_ITEM_TYPE_IPV6,
1539 RTE_FLOW_ITEM_TYPE_UDP,
1540 RTE_FLOW_ITEM_TYPE_VXLAN,
1541 RTE_FLOW_ITEM_TYPE_ETH,
1542 RTE_FLOW_ITEM_TYPE_VLAN,
1543 RTE_FLOW_ITEM_TYPE_END,
1546 static enum rte_flow_item_type pattern_nvgre_1[] = {
1547 RTE_FLOW_ITEM_TYPE_ETH,
1548 RTE_FLOW_ITEM_TYPE_IPV4,
1549 RTE_FLOW_ITEM_TYPE_NVGRE,
1550 RTE_FLOW_ITEM_TYPE_ETH,
1551 RTE_FLOW_ITEM_TYPE_END,
1554 static enum rte_flow_item_type pattern_nvgre_2[] = {
1555 RTE_FLOW_ITEM_TYPE_ETH,
1556 RTE_FLOW_ITEM_TYPE_IPV6,
1557 RTE_FLOW_ITEM_TYPE_NVGRE,
1558 RTE_FLOW_ITEM_TYPE_ETH,
1559 RTE_FLOW_ITEM_TYPE_END,
1562 static enum rte_flow_item_type pattern_nvgre_3[] = {
1563 RTE_FLOW_ITEM_TYPE_ETH,
1564 RTE_FLOW_ITEM_TYPE_IPV4,
1565 RTE_FLOW_ITEM_TYPE_NVGRE,
1566 RTE_FLOW_ITEM_TYPE_ETH,
1567 RTE_FLOW_ITEM_TYPE_VLAN,
1568 RTE_FLOW_ITEM_TYPE_END,
1571 static enum rte_flow_item_type pattern_nvgre_4[] = {
1572 RTE_FLOW_ITEM_TYPE_ETH,
1573 RTE_FLOW_ITEM_TYPE_IPV6,
1574 RTE_FLOW_ITEM_TYPE_NVGRE,
1575 RTE_FLOW_ITEM_TYPE_ETH,
1576 RTE_FLOW_ITEM_TYPE_VLAN,
1577 RTE_FLOW_ITEM_TYPE_END,
1580 static enum rte_flow_item_type pattern_mpls_1[] = {
1581 RTE_FLOW_ITEM_TYPE_ETH,
1582 RTE_FLOW_ITEM_TYPE_IPV4,
1583 RTE_FLOW_ITEM_TYPE_UDP,
1584 RTE_FLOW_ITEM_TYPE_MPLS,
1585 RTE_FLOW_ITEM_TYPE_END,
1588 static enum rte_flow_item_type pattern_mpls_2[] = {
1589 RTE_FLOW_ITEM_TYPE_ETH,
1590 RTE_FLOW_ITEM_TYPE_IPV6,
1591 RTE_FLOW_ITEM_TYPE_UDP,
1592 RTE_FLOW_ITEM_TYPE_MPLS,
1593 RTE_FLOW_ITEM_TYPE_END,
1596 static enum rte_flow_item_type pattern_mpls_3[] = {
1597 RTE_FLOW_ITEM_TYPE_ETH,
1598 RTE_FLOW_ITEM_TYPE_IPV4,
1599 RTE_FLOW_ITEM_TYPE_GRE,
1600 RTE_FLOW_ITEM_TYPE_MPLS,
1601 RTE_FLOW_ITEM_TYPE_END,
1604 static enum rte_flow_item_type pattern_mpls_4[] = {
1605 RTE_FLOW_ITEM_TYPE_ETH,
1606 RTE_FLOW_ITEM_TYPE_IPV6,
1607 RTE_FLOW_ITEM_TYPE_GRE,
1608 RTE_FLOW_ITEM_TYPE_MPLS,
1609 RTE_FLOW_ITEM_TYPE_END,
1612 static enum rte_flow_item_type pattern_qinq_1[] = {
1613 RTE_FLOW_ITEM_TYPE_ETH,
1614 RTE_FLOW_ITEM_TYPE_VLAN,
1615 RTE_FLOW_ITEM_TYPE_VLAN,
1616 RTE_FLOW_ITEM_TYPE_END,
1619 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1621 { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1622 /* FDIR - support default flow type without flexible payload*/
1623 { pattern_ethertype, i40e_flow_parse_fdir_filter },
1624 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1625 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1626 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1627 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1628 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1629 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1630 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1631 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1632 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1633 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1634 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1635 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1636 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1637 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1638 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1639 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1640 /* FDIR - support default flow type with flexible payload */
1641 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1642 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1643 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1644 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1645 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1646 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1647 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1648 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1649 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1650 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1651 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1652 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1653 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1654 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1655 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1656 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1657 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1658 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1659 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1660 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1661 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1662 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1663 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1664 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1665 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1666 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1667 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1668 /* FDIR - support single vlan input set */
1669 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1670 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1671 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1672 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1673 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1674 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1675 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1676 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1677 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1678 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1679 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1680 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1681 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1682 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1683 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1684 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1685 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1686 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1687 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1688 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1689 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1690 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1691 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1692 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1693 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1694 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1695 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1696 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1697 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1698 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1699 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1700 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1701 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1702 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1703 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1704 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1705 /* FDIR - support VF item */
1706 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1707 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1708 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1709 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1710 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1711 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1712 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1713 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1714 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1715 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1716 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1717 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1718 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1719 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1720 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1721 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1722 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1723 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1724 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1725 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1726 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1727 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1728 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1729 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1730 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1731 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1732 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1733 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1734 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1735 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1736 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1737 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1738 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1739 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1740 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1741 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1742 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1743 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1744 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1745 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1746 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1747 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1748 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1749 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1750 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1751 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1752 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1753 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1754 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1755 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1756 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1757 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1758 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1759 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1760 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1761 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1762 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1763 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1764 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1765 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1766 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1767 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1768 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1769 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1770 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1771 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1772 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1773 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1774 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1775 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1776 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1778 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1779 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1780 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1781 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1783 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1784 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1785 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1786 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1787 /* MPLSoUDP & MPLSoGRE */
1788 { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1789 { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1790 { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1791 { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1793 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1794 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1795 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1796 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1798 { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1801 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1803 act = actions + index; \
1804 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1806 act = actions + index; \
1810 /* Find the first VOID or non-VOID item pointer */
1811 static const struct rte_flow_item *
1812 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1816 while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1818 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1820 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1828 /* Skip all VOID items of the pattern */
1830 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1831 const struct rte_flow_item *pattern)
1833 uint32_t cpy_count = 0;
1834 const struct rte_flow_item *pb = pattern, *pe = pattern;
1837 /* Find a non-void item first */
1838 pb = i40e_find_first_item(pb, false);
1839 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1844 /* Find a void item */
1845 pe = i40e_find_first_item(pb + 1, true);
1847 cpy_count = pe - pb;
1848 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1852 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1859 /* Copy the END item. */
1860 rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1863 /* Check if the pattern matches a supported item type array */
1865 i40e_match_pattern(enum rte_flow_item_type *item_array,
1866 struct rte_flow_item *pattern)
1868 struct rte_flow_item *item = pattern;
1870 while ((*item_array == item->type) &&
1871 (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1876 return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1877 item->type == RTE_FLOW_ITEM_TYPE_END);
1880 /* Find if there's parse filter function matched */
1881 static parse_filter_t
1882 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1884 parse_filter_t parse_filter = NULL;
1887 for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1888 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1890 parse_filter = i40e_supported_patterns[i].parse_filter;
1897 return parse_filter;
1900 /* Parse attributes */
1902 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1903 struct rte_flow_error *error)
1905 /* Must be input direction */
1906 if (!attr->ingress) {
1907 rte_flow_error_set(error, EINVAL,
1908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1909 attr, "Only support ingress.");
1915 rte_flow_error_set(error, EINVAL,
1916 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1917 attr, "Not support egress.");
1922 if (attr->priority) {
1923 rte_flow_error_set(error, EINVAL,
1924 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1925 attr, "Not support priority.");
1931 rte_flow_error_set(error, EINVAL,
1932 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1933 attr, "Not support group.");
1941 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944 int qinq = dev->data->dev_conf.rxmode.offloads &
1945 DEV_RX_OFFLOAD_VLAN_EXTEND;
1955 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1958 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1963 /* 1. Last in item should be NULL as range is not supported.
1964 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1965 * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1966 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1968 * 5. Ether_type mask should be 0xFFFF.
1971 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1972 const struct rte_flow_item *pattern,
1973 struct rte_flow_error *error,
1974 struct rte_eth_ethertype_filter *filter)
1976 const struct rte_flow_item *item = pattern;
1977 const struct rte_flow_item_eth *eth_spec;
1978 const struct rte_flow_item_eth *eth_mask;
1979 enum rte_flow_item_type item_type;
1980 uint16_t outer_tpid;
1982 outer_tpid = i40e_get_outer_vlan(dev);
1984 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1986 rte_flow_error_set(error, EINVAL,
1987 RTE_FLOW_ERROR_TYPE_ITEM,
1989 "Not support range");
1992 item_type = item->type;
1993 switch (item_type) {
1994 case RTE_FLOW_ITEM_TYPE_ETH:
1995 eth_spec = item->spec;
1996 eth_mask = item->mask;
1997 /* Get the MAC info. */
1998 if (!eth_spec || !eth_mask) {
1999 rte_flow_error_set(error, EINVAL,
2000 RTE_FLOW_ERROR_TYPE_ITEM,
2002 "NULL ETH spec/mask");
2006 /* Mask bits of source MAC address must be full of 0.
2007 * Mask bits of destination MAC address must be full
2008 * of 1 or full of 0.
2010 if (!is_zero_ether_addr(ð_mask->src) ||
2011 (!is_zero_ether_addr(ð_mask->dst) &&
2012 !is_broadcast_ether_addr(ð_mask->dst))) {
2013 rte_flow_error_set(error, EINVAL,
2014 RTE_FLOW_ERROR_TYPE_ITEM,
2016 "Invalid MAC_addr mask");
2020 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2021 rte_flow_error_set(error, EINVAL,
2022 RTE_FLOW_ERROR_TYPE_ITEM,
2024 "Invalid ethertype mask");
2028 /* If mask bits of destination MAC address
2029 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2031 if (is_broadcast_ether_addr(ð_mask->dst)) {
2032 filter->mac_addr = eth_spec->dst;
2033 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2035 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2037 filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2039 if (filter->ether_type == ETHER_TYPE_IPv4 ||
2040 filter->ether_type == ETHER_TYPE_IPv6 ||
2041 filter->ether_type == ETHER_TYPE_LLDP ||
2042 filter->ether_type == outer_tpid) {
2043 rte_flow_error_set(error, EINVAL,
2044 RTE_FLOW_ERROR_TYPE_ITEM,
2046 "Unsupported ether_type in"
2047 " control packet filter.");
2059 /* Ethertype action only supports QUEUE or DROP. */
2061 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2062 const struct rte_flow_action *actions,
2063 struct rte_flow_error *error,
2064 struct rte_eth_ethertype_filter *filter)
2066 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2067 const struct rte_flow_action *act;
2068 const struct rte_flow_action_queue *act_q;
2071 /* Check if the first non-void action is QUEUE or DROP. */
2072 NEXT_ITEM_OF_ACTION(act, actions, index);
2073 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2074 act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2075 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2076 act, "Not supported action.");
2080 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2082 filter->queue = act_q->index;
2083 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2084 rte_flow_error_set(error, EINVAL,
2085 RTE_FLOW_ERROR_TYPE_ACTION,
2086 act, "Invalid queue ID for"
2087 " ethertype_filter.");
2091 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2094 /* Check if the next non-void item is END */
2096 NEXT_ITEM_OF_ACTION(act, actions, index);
2097 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2098 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2099 act, "Not supported action.");
2107 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2108 const struct rte_flow_attr *attr,
2109 const struct rte_flow_item pattern[],
2110 const struct rte_flow_action actions[],
2111 struct rte_flow_error *error,
2112 union i40e_filter_t *filter)
2114 struct rte_eth_ethertype_filter *ethertype_filter =
2115 &filter->ethertype_filter;
2118 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2123 ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2128 ret = i40e_flow_parse_attr(attr, error);
2132 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2138 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2139 const struct rte_flow_item_raw *raw_spec,
2140 struct rte_flow_error *error)
2142 if (!raw_spec->relative) {
2143 rte_flow_error_set(error, EINVAL,
2144 RTE_FLOW_ERROR_TYPE_ITEM,
2146 "Relative should be 1.");
2150 if (raw_spec->offset % sizeof(uint16_t)) {
2151 rte_flow_error_set(error, EINVAL,
2152 RTE_FLOW_ERROR_TYPE_ITEM,
2154 "Offset should be even.");
2158 if (raw_spec->search || raw_spec->limit) {
2159 rte_flow_error_set(error, EINVAL,
2160 RTE_FLOW_ERROR_TYPE_ITEM,
2162 "search or limit is not supported.");
2166 if (raw_spec->offset < 0) {
2167 rte_flow_error_set(error, EINVAL,
2168 RTE_FLOW_ERROR_TYPE_ITEM,
2170 "Offset should be non-negative.");
2177 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2178 struct i40e_fdir_flex_pit *flex_pit,
2179 enum i40e_flxpld_layer_idx layer_idx,
2184 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2185 /* Check if the configuration is conflicted */
2186 if (pf->fdir.flex_pit_flag[layer_idx] &&
2187 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2188 pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2189 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2192 /* Check if the configuration exists. */
2193 if (pf->fdir.flex_pit_flag[layer_idx] &&
2194 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2195 pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2196 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2199 pf->fdir.flex_set[field_idx].src_offset =
2200 flex_pit->src_offset;
2201 pf->fdir.flex_set[field_idx].size =
2203 pf->fdir.flex_set[field_idx].dst_offset =
2204 flex_pit->dst_offset;
2210 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2211 enum i40e_filter_pctype pctype,
2214 struct i40e_fdir_flex_mask flex_mask;
2216 uint8_t i, nb_bitmask = 0;
2218 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2219 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2220 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2222 flex_mask.word_mask |=
2223 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2224 if (mask_tmp != UINT16_MAX) {
2225 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2226 flex_mask.bitmask[nb_bitmask].offset =
2227 i / sizeof(uint16_t);
2229 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2234 flex_mask.nb_bitmask = nb_bitmask;
2236 if (pf->fdir.flex_mask_flag[pctype] &&
2237 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2238 sizeof(struct i40e_fdir_flex_mask))))
2240 else if (pf->fdir.flex_mask_flag[pctype] &&
2241 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2242 sizeof(struct i40e_fdir_flex_mask))))
2245 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2246 sizeof(struct i40e_fdir_flex_mask));
2251 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2252 enum i40e_flxpld_layer_idx layer_idx,
2255 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2256 uint32_t flx_pit, flx_ort;
2258 uint16_t min_next_off = 0; /* in words */
2262 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2263 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2264 (layer_idx * I40E_MAX_FLXPLD_FIED);
2265 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2269 for (i = 0; i < raw_id; i++) {
2270 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2271 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2272 pf->fdir.flex_set[field_idx].size,
2273 pf->fdir.flex_set[field_idx].dst_offset);
2275 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2276 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2277 pf->fdir.flex_set[field_idx].size;
2280 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2281 /* set the non-used register obeying register's constrain */
2282 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2283 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2284 NONUSE_FLX_PIT_DEST_OFF);
2285 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2289 pf->fdir.flex_pit_flag[layer_idx] = 1;
2293 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2294 enum i40e_filter_pctype pctype)
2296 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2297 struct i40e_fdir_flex_mask *flex_mask;
2298 uint32_t flxinset, fd_mask;
2302 flex_mask = &pf->fdir.flex_mask[pctype];
2303 flxinset = (flex_mask->word_mask <<
2304 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2305 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2306 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2308 for (i = 0; i < flex_mask->nb_bitmask; i++) {
2309 fd_mask = (flex_mask->bitmask[i].mask <<
2310 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2311 I40E_PRTQF_FD_MSK_MASK_MASK;
2312 fd_mask |= ((flex_mask->bitmask[i].offset +
2313 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2314 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2315 I40E_PRTQF_FD_MSK_OFFSET_MASK;
2316 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2319 pf->fdir.flex_mask_flag[pctype] = 1;
2323 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2324 enum i40e_filter_pctype pctype,
2327 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2328 uint64_t inset_reg = 0;
2329 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2332 /* Check if the input set is valid */
2333 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2335 PMD_DRV_LOG(ERR, "Invalid input set");
2339 /* Check if the configuration is conflicted */
2340 if (pf->fdir.inset_flag[pctype] &&
2341 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2344 if (pf->fdir.inset_flag[pctype] &&
2345 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2348 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2349 I40E_INSET_MASK_NUM_REG);
2353 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2355 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2356 (uint32_t)(inset_reg & UINT32_MAX));
2357 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2358 (uint32_t)((inset_reg >>
2359 I40E_32_BIT_WIDTH) & UINT32_MAX));
2361 for (i = 0; i < num; i++)
2362 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2365 /*clear unused mask registers of the pctype */
2366 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2367 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2368 I40E_WRITE_FLUSH(hw);
2370 pf->fdir.input_set[pctype] = input_set;
2371 pf->fdir.inset_flag[pctype] = 1;
2376 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2377 enum rte_flow_item_type item_type,
2378 struct i40e_fdir_filter_conf *filter)
2380 struct i40e_customized_pctype *cus_pctype = NULL;
2382 switch (item_type) {
2383 case RTE_FLOW_ITEM_TYPE_GTPC:
2384 cus_pctype = i40e_find_customized_pctype(pf,
2385 I40E_CUSTOMIZED_GTPC);
2387 case RTE_FLOW_ITEM_TYPE_GTPU:
2388 if (!filter->input.flow_ext.inner_ip)
2389 cus_pctype = i40e_find_customized_pctype(pf,
2390 I40E_CUSTOMIZED_GTPU);
2391 else if (filter->input.flow_ext.iip_type ==
2392 I40E_FDIR_IPTYPE_IPV4)
2393 cus_pctype = i40e_find_customized_pctype(pf,
2394 I40E_CUSTOMIZED_GTPU_IPV4);
2395 else if (filter->input.flow_ext.iip_type ==
2396 I40E_FDIR_IPTYPE_IPV6)
2397 cus_pctype = i40e_find_customized_pctype(pf,
2398 I40E_CUSTOMIZED_GTPU_IPV6);
2401 PMD_DRV_LOG(ERR, "Unsupported item type");
2405 if (cus_pctype && cus_pctype->valid)
2406 return cus_pctype->pctype;
2408 return I40E_FILTER_PCTYPE_INVALID;
2411 /* 1. Last in item should be NULL as range is not supported.
2412 * 2. Supported patterns: refer to array i40e_supported_patterns.
2413 * 3. Default supported flow type and input set: refer to array
2414 * valid_fdir_inset_table in i40e_ethdev.c.
2415 * 4. Mask of fields which need to be matched should be
2417 * 5. Mask of fields which needn't to be matched should be
2419 * 6. GTP profile supports GTPv1 only.
2420 * 7. GTP-C response message ('source_port' = 2123) is not supported.
2423 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2424 const struct rte_flow_attr *attr,
2425 const struct rte_flow_item *pattern,
2426 struct rte_flow_error *error,
2427 struct i40e_fdir_filter_conf *filter)
2429 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2430 const struct rte_flow_item *item = pattern;
2431 const struct rte_flow_item_eth *eth_spec, *eth_mask;
2432 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2433 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2434 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2435 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2436 const struct rte_flow_item_udp *udp_spec, *udp_mask;
2437 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2438 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2439 const struct rte_flow_item_raw *raw_spec, *raw_mask;
2440 const struct rte_flow_item_vf *vf_spec;
2443 uint64_t input_set = I40E_INSET_NONE;
2445 enum rte_flow_item_type item_type;
2446 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2447 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2449 uint8_t ipv6_addr_mask[16] = {
2450 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2451 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2452 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2454 int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2455 uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2456 struct i40e_fdir_flex_pit flex_pit;
2457 uint8_t next_dst_off = 0;
2458 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2460 bool cfg_flex_pit = true;
2461 bool cfg_flex_msk = true;
2462 uint16_t outer_tpid;
2463 uint16_t ether_type;
2464 uint32_t vtc_flow_cpu;
2465 bool outer_ip = true;
2468 memset(off_arr, 0, sizeof(off_arr));
2469 memset(len_arr, 0, sizeof(len_arr));
2470 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2471 outer_tpid = i40e_get_outer_vlan(dev);
2472 filter->input.flow_ext.customized_pctype = false;
2473 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2475 rte_flow_error_set(error, EINVAL,
2476 RTE_FLOW_ERROR_TYPE_ITEM,
2478 "Not support range");
2481 item_type = item->type;
2482 switch (item_type) {
2483 case RTE_FLOW_ITEM_TYPE_ETH:
2484 eth_spec = item->spec;
2485 eth_mask = item->mask;
2487 if (eth_spec && eth_mask) {
2488 if (!is_zero_ether_addr(ð_mask->src) ||
2489 !is_zero_ether_addr(ð_mask->dst)) {
2490 rte_flow_error_set(error, EINVAL,
2491 RTE_FLOW_ERROR_TYPE_ITEM,
2493 "Invalid MAC_addr mask.");
2497 if (eth_spec && eth_mask && eth_mask->type) {
2498 enum rte_flow_item_type next = (item + 1)->type;
2500 if (eth_mask->type != RTE_BE16(0xffff)) {
2501 rte_flow_error_set(error, EINVAL,
2502 RTE_FLOW_ERROR_TYPE_ITEM,
2504 "Invalid type mask.");
2508 ether_type = rte_be_to_cpu_16(eth_spec->type);
2510 if (next == RTE_FLOW_ITEM_TYPE_VLAN ||
2511 ether_type == ETHER_TYPE_IPv4 ||
2512 ether_type == ETHER_TYPE_IPv6 ||
2513 ether_type == ETHER_TYPE_ARP ||
2514 ether_type == outer_tpid) {
2515 rte_flow_error_set(error, EINVAL,
2516 RTE_FLOW_ERROR_TYPE_ITEM,
2518 "Unsupported ether_type.");
2521 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2522 filter->input.flow.l2_flow.ether_type =
2526 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2527 layer_idx = I40E_FLXPLD_L2_IDX;
2530 case RTE_FLOW_ITEM_TYPE_VLAN:
2531 vlan_spec = item->spec;
2532 vlan_mask = item->mask;
2534 RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2535 if (vlan_spec && vlan_mask) {
2536 if (vlan_mask->tci ==
2537 rte_cpu_to_be_16(I40E_TCI_MASK)) {
2538 input_set |= I40E_INSET_VLAN_INNER;
2539 filter->input.flow_ext.vlan_tci =
2543 if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2544 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2545 rte_flow_error_set(error, EINVAL,
2546 RTE_FLOW_ERROR_TYPE_ITEM,
2548 "Invalid inner_type"
2554 rte_be_to_cpu_16(vlan_spec->inner_type);
2556 if (ether_type == ETHER_TYPE_IPv4 ||
2557 ether_type == ETHER_TYPE_IPv6 ||
2558 ether_type == ETHER_TYPE_ARP ||
2559 ether_type == outer_tpid) {
2560 rte_flow_error_set(error, EINVAL,
2561 RTE_FLOW_ERROR_TYPE_ITEM,
2563 "Unsupported inner_type.");
2566 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2567 filter->input.flow.l2_flow.ether_type =
2568 vlan_spec->inner_type;
2571 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2572 layer_idx = I40E_FLXPLD_L2_IDX;
2575 case RTE_FLOW_ITEM_TYPE_IPV4:
2576 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2577 ipv4_spec = item->spec;
2578 ipv4_mask = item->mask;
2579 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2580 layer_idx = I40E_FLXPLD_L3_IDX;
2582 if (ipv4_spec && ipv4_mask && outer_ip) {
2583 /* Check IPv4 mask and update input set */
2584 if (ipv4_mask->hdr.version_ihl ||
2585 ipv4_mask->hdr.total_length ||
2586 ipv4_mask->hdr.packet_id ||
2587 ipv4_mask->hdr.fragment_offset ||
2588 ipv4_mask->hdr.hdr_checksum) {
2589 rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM,
2592 "Invalid IPv4 mask.");
2596 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2597 input_set |= I40E_INSET_IPV4_SRC;
2598 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2599 input_set |= I40E_INSET_IPV4_DST;
2600 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2601 input_set |= I40E_INSET_IPV4_TOS;
2602 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2603 input_set |= I40E_INSET_IPV4_TTL;
2604 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2605 input_set |= I40E_INSET_IPV4_PROTO;
2607 /* Check if it is fragment. */
2608 frag_off = ipv4_spec->hdr.fragment_offset;
2609 frag_off = rte_be_to_cpu_16(frag_off);
2610 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2611 frag_off & IPV4_HDR_MF_FLAG)
2612 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2614 /* Get the filter info */
2615 filter->input.flow.ip4_flow.proto =
2616 ipv4_spec->hdr.next_proto_id;
2617 filter->input.flow.ip4_flow.tos =
2618 ipv4_spec->hdr.type_of_service;
2619 filter->input.flow.ip4_flow.ttl =
2620 ipv4_spec->hdr.time_to_live;
2621 filter->input.flow.ip4_flow.src_ip =
2622 ipv4_spec->hdr.src_addr;
2623 filter->input.flow.ip4_flow.dst_ip =
2624 ipv4_spec->hdr.dst_addr;
2625 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2626 filter->input.flow_ext.inner_ip = true;
2627 filter->input.flow_ext.iip_type =
2628 I40E_FDIR_IPTYPE_IPV4;
2629 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2630 rte_flow_error_set(error, EINVAL,
2631 RTE_FLOW_ERROR_TYPE_ITEM,
2633 "Invalid inner IPv4 mask.");
2641 case RTE_FLOW_ITEM_TYPE_IPV6:
2642 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2643 ipv6_spec = item->spec;
2644 ipv6_mask = item->mask;
2645 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2646 layer_idx = I40E_FLXPLD_L3_IDX;
2648 if (ipv6_spec && ipv6_mask && outer_ip) {
2649 /* Check IPv6 mask and update input set */
2650 if (ipv6_mask->hdr.payload_len) {
2651 rte_flow_error_set(error, EINVAL,
2652 RTE_FLOW_ERROR_TYPE_ITEM,
2654 "Invalid IPv6 mask");
2658 if (!memcmp(ipv6_mask->hdr.src_addr,
2660 RTE_DIM(ipv6_mask->hdr.src_addr)))
2661 input_set |= I40E_INSET_IPV6_SRC;
2662 if (!memcmp(ipv6_mask->hdr.dst_addr,
2664 RTE_DIM(ipv6_mask->hdr.dst_addr)))
2665 input_set |= I40E_INSET_IPV6_DST;
2667 if ((ipv6_mask->hdr.vtc_flow &
2668 rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2669 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2670 input_set |= I40E_INSET_IPV6_TC;
2671 if (ipv6_mask->hdr.proto == UINT8_MAX)
2672 input_set |= I40E_INSET_IPV6_NEXT_HDR;
2673 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2674 input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2676 /* Get filter info */
2678 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2679 filter->input.flow.ipv6_flow.tc =
2680 (uint8_t)(vtc_flow_cpu >>
2681 I40E_FDIR_IPv6_TC_OFFSET);
2682 filter->input.flow.ipv6_flow.proto =
2683 ipv6_spec->hdr.proto;
2684 filter->input.flow.ipv6_flow.hop_limits =
2685 ipv6_spec->hdr.hop_limits;
2687 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2688 ipv6_spec->hdr.src_addr, 16);
2689 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2690 ipv6_spec->hdr.dst_addr, 16);
2692 /* Check if it is fragment. */
2693 if (ipv6_spec->hdr.proto ==
2694 I40E_IPV6_FRAG_HEADER)
2695 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2696 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2697 filter->input.flow_ext.inner_ip = true;
2698 filter->input.flow_ext.iip_type =
2699 I40E_FDIR_IPTYPE_IPV6;
2700 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2701 rte_flow_error_set(error, EINVAL,
2702 RTE_FLOW_ERROR_TYPE_ITEM,
2704 "Invalid inner IPv6 mask");
2711 case RTE_FLOW_ITEM_TYPE_TCP:
2712 tcp_spec = item->spec;
2713 tcp_mask = item->mask;
2715 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2717 I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2718 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2720 I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2721 if (tcp_spec && tcp_mask) {
2722 /* Check TCP mask and update input set */
2723 if (tcp_mask->hdr.sent_seq ||
2724 tcp_mask->hdr.recv_ack ||
2725 tcp_mask->hdr.data_off ||
2726 tcp_mask->hdr.tcp_flags ||
2727 tcp_mask->hdr.rx_win ||
2728 tcp_mask->hdr.cksum ||
2729 tcp_mask->hdr.tcp_urp) {
2730 rte_flow_error_set(error, EINVAL,
2731 RTE_FLOW_ERROR_TYPE_ITEM,
2733 "Invalid TCP mask");
2737 if (tcp_mask->hdr.src_port == UINT16_MAX)
2738 input_set |= I40E_INSET_SRC_PORT;
2739 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2740 input_set |= I40E_INSET_DST_PORT;
2742 /* Get filter info */
2743 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2744 filter->input.flow.tcp4_flow.src_port =
2745 tcp_spec->hdr.src_port;
2746 filter->input.flow.tcp4_flow.dst_port =
2747 tcp_spec->hdr.dst_port;
2748 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2749 filter->input.flow.tcp6_flow.src_port =
2750 tcp_spec->hdr.src_port;
2751 filter->input.flow.tcp6_flow.dst_port =
2752 tcp_spec->hdr.dst_port;
2756 layer_idx = I40E_FLXPLD_L4_IDX;
2759 case RTE_FLOW_ITEM_TYPE_UDP:
2760 udp_spec = item->spec;
2761 udp_mask = item->mask;
2763 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2765 I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2766 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2768 I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2770 if (udp_spec && udp_mask) {
2771 /* Check UDP mask and update input set*/
2772 if (udp_mask->hdr.dgram_len ||
2773 udp_mask->hdr.dgram_cksum) {
2774 rte_flow_error_set(error, EINVAL,
2775 RTE_FLOW_ERROR_TYPE_ITEM,
2777 "Invalid UDP mask");
2781 if (udp_mask->hdr.src_port == UINT16_MAX)
2782 input_set |= I40E_INSET_SRC_PORT;
2783 if (udp_mask->hdr.dst_port == UINT16_MAX)
2784 input_set |= I40E_INSET_DST_PORT;
2786 /* Get filter info */
2787 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2788 filter->input.flow.udp4_flow.src_port =
2789 udp_spec->hdr.src_port;
2790 filter->input.flow.udp4_flow.dst_port =
2791 udp_spec->hdr.dst_port;
2792 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2793 filter->input.flow.udp6_flow.src_port =
2794 udp_spec->hdr.src_port;
2795 filter->input.flow.udp6_flow.dst_port =
2796 udp_spec->hdr.dst_port;
2800 layer_idx = I40E_FLXPLD_L4_IDX;
2803 case RTE_FLOW_ITEM_TYPE_GTPC:
2804 case RTE_FLOW_ITEM_TYPE_GTPU:
2805 if (!pf->gtp_support) {
2806 rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ITEM,
2809 "Unsupported protocol");
2813 gtp_spec = item->spec;
2814 gtp_mask = item->mask;
2816 if (gtp_spec && gtp_mask) {
2817 if (gtp_mask->v_pt_rsv_flags ||
2818 gtp_mask->msg_type ||
2819 gtp_mask->msg_len ||
2820 gtp_mask->teid != UINT32_MAX) {
2821 rte_flow_error_set(error, EINVAL,
2822 RTE_FLOW_ERROR_TYPE_ITEM,
2824 "Invalid GTP mask");
2828 filter->input.flow.gtp_flow.teid =
2830 filter->input.flow_ext.customized_pctype = true;
2831 cus_proto = item_type;
2834 case RTE_FLOW_ITEM_TYPE_SCTP:
2835 sctp_spec = item->spec;
2836 sctp_mask = item->mask;
2838 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2840 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2841 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2843 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2845 if (sctp_spec && sctp_mask) {
2846 /* Check SCTP mask and update input set */
2847 if (sctp_mask->hdr.cksum) {
2848 rte_flow_error_set(error, EINVAL,
2849 RTE_FLOW_ERROR_TYPE_ITEM,
2851 "Invalid UDP mask");
2855 if (sctp_mask->hdr.src_port == UINT16_MAX)
2856 input_set |= I40E_INSET_SRC_PORT;
2857 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2858 input_set |= I40E_INSET_DST_PORT;
2859 if (sctp_mask->hdr.tag == UINT32_MAX)
2860 input_set |= I40E_INSET_SCTP_VT;
2862 /* Get filter info */
2863 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2864 filter->input.flow.sctp4_flow.src_port =
2865 sctp_spec->hdr.src_port;
2866 filter->input.flow.sctp4_flow.dst_port =
2867 sctp_spec->hdr.dst_port;
2868 filter->input.flow.sctp4_flow.verify_tag
2869 = sctp_spec->hdr.tag;
2870 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2871 filter->input.flow.sctp6_flow.src_port =
2872 sctp_spec->hdr.src_port;
2873 filter->input.flow.sctp6_flow.dst_port =
2874 sctp_spec->hdr.dst_port;
2875 filter->input.flow.sctp6_flow.verify_tag
2876 = sctp_spec->hdr.tag;
2880 layer_idx = I40E_FLXPLD_L4_IDX;
2883 case RTE_FLOW_ITEM_TYPE_RAW:
2884 raw_spec = item->spec;
2885 raw_mask = item->mask;
2887 if (!raw_spec || !raw_mask) {
2888 rte_flow_error_set(error, EINVAL,
2889 RTE_FLOW_ERROR_TYPE_ITEM,
2891 "NULL RAW spec/mask");
2895 if (pf->support_multi_driver) {
2896 rte_flow_error_set(error, ENOTSUP,
2897 RTE_FLOW_ERROR_TYPE_ITEM,
2899 "Unsupported flexible payload.");
2903 ret = i40e_flow_check_raw_item(item, raw_spec, error);
2907 off_arr[raw_id] = raw_spec->offset;
2908 len_arr[raw_id] = raw_spec->length;
2911 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2913 raw_spec->length / sizeof(uint16_t);
2914 flex_pit.dst_offset =
2915 next_dst_off / sizeof(uint16_t);
2917 for (i = 0; i <= raw_id; i++) {
2919 flex_pit.src_offset +=
2923 flex_pit.src_offset +=
2924 (off_arr[i] + len_arr[i]) /
2926 flex_size += len_arr[i];
2928 if (((flex_pit.src_offset + flex_pit.size) >=
2929 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2930 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2931 rte_flow_error_set(error, EINVAL,
2932 RTE_FLOW_ERROR_TYPE_ITEM,
2934 "Exceeds maxmial payload limit.");
2938 /* Store flex pit to SW */
2939 ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2942 rte_flow_error_set(error, EINVAL,
2943 RTE_FLOW_ERROR_TYPE_ITEM,
2945 "Conflict with the first flexible rule.");
2948 cfg_flex_pit = false;
2950 for (i = 0; i < raw_spec->length; i++) {
2951 j = i + next_dst_off;
2952 filter->input.flow_ext.flexbytes[j] =
2953 raw_spec->pattern[i];
2954 flex_mask[j] = raw_mask->pattern[i];
2957 next_dst_off += raw_spec->length;
2960 case RTE_FLOW_ITEM_TYPE_VF:
2961 vf_spec = item->spec;
2962 if (!attr->transfer) {
2963 rte_flow_error_set(error, ENOTSUP,
2964 RTE_FLOW_ERROR_TYPE_ITEM,
2966 "Matching VF traffic"
2967 " without affecting it"
2968 " (transfer attribute)"
2972 filter->input.flow_ext.is_vf = 1;
2973 filter->input.flow_ext.dst_id = vf_spec->id;
2974 if (filter->input.flow_ext.is_vf &&
2975 filter->input.flow_ext.dst_id >= pf->vf_num) {
2976 rte_flow_error_set(error, EINVAL,
2977 RTE_FLOW_ERROR_TYPE_ITEM,
2979 "Invalid VF ID for FDIR.");
2988 /* Get customized pctype value */
2989 if (filter->input.flow_ext.customized_pctype) {
2990 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2991 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2992 rte_flow_error_set(error, EINVAL,
2993 RTE_FLOW_ERROR_TYPE_ITEM,
2995 "Unsupported pctype");
3000 /* If customized pctype is not used, set fdir configuration.*/
3001 if (!filter->input.flow_ext.customized_pctype) {
3002 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3004 rte_flow_error_set(error, EINVAL,
3005 RTE_FLOW_ERROR_TYPE_ITEM, item,
3006 "Conflict with the first rule's input set.");
3008 } else if (ret == -EINVAL) {
3009 rte_flow_error_set(error, EINVAL,
3010 RTE_FLOW_ERROR_TYPE_ITEM, item,
3011 "Invalid pattern mask.");
3015 /* Store flex mask to SW */
3016 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3018 rte_flow_error_set(error, EINVAL,
3019 RTE_FLOW_ERROR_TYPE_ITEM,
3021 "Exceed maximal number of bitmasks");
3023 } else if (ret == -2) {
3024 rte_flow_error_set(error, EINVAL,
3025 RTE_FLOW_ERROR_TYPE_ITEM,
3027 "Conflict with the first flexible rule");
3030 cfg_flex_msk = false;
3033 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3036 i40e_flow_set_fdir_flex_msk(pf, pctype);
3039 filter->input.pctype = pctype;
3044 /* Parse to get the action info of a FDIR filter.
3045 * FDIR action supports QUEUE or (QUEUE + MARK).
3048 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3049 const struct rte_flow_action *actions,
3050 struct rte_flow_error *error,
3051 struct i40e_fdir_filter_conf *filter)
3053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3054 const struct rte_flow_action *act;
3055 const struct rte_flow_action_queue *act_q;
3056 const struct rte_flow_action_mark *mark_spec;
3059 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3060 NEXT_ITEM_OF_ACTION(act, actions, index);
3061 switch (act->type) {
3062 case RTE_FLOW_ACTION_TYPE_QUEUE:
3064 filter->action.rx_queue = act_q->index;
3065 if ((!filter->input.flow_ext.is_vf &&
3066 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3067 (filter->input.flow_ext.is_vf &&
3068 filter->action.rx_queue >= pf->vf_nb_qps)) {
3069 rte_flow_error_set(error, EINVAL,
3070 RTE_FLOW_ERROR_TYPE_ACTION, act,
3071 "Invalid queue ID for FDIR.");
3074 filter->action.behavior = I40E_FDIR_ACCEPT;
3076 case RTE_FLOW_ACTION_TYPE_DROP:
3077 filter->action.behavior = I40E_FDIR_REJECT;
3079 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3080 filter->action.behavior = I40E_FDIR_PASSTHRU;
3083 rte_flow_error_set(error, EINVAL,
3084 RTE_FLOW_ERROR_TYPE_ACTION, act,
3089 /* Check if the next non-void item is MARK or FLAG or END. */
3091 NEXT_ITEM_OF_ACTION(act, actions, index);
3092 switch (act->type) {
3093 case RTE_FLOW_ACTION_TYPE_MARK:
3094 mark_spec = act->conf;
3095 filter->action.report_status = I40E_FDIR_REPORT_ID;
3096 filter->soft_id = mark_spec->id;
3098 case RTE_FLOW_ACTION_TYPE_FLAG:
3099 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3101 case RTE_FLOW_ACTION_TYPE_END:
3104 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3105 act, "Invalid action.");
3109 /* Check if the next non-void item is END */
3111 NEXT_ITEM_OF_ACTION(act, actions, index);
3112 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3113 rte_flow_error_set(error, EINVAL,
3114 RTE_FLOW_ERROR_TYPE_ACTION,
3115 act, "Invalid action.");
3123 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3124 const struct rte_flow_attr *attr,
3125 const struct rte_flow_item pattern[],
3126 const struct rte_flow_action actions[],
3127 struct rte_flow_error *error,
3128 union i40e_filter_t *filter)
3130 struct i40e_fdir_filter_conf *fdir_filter =
3131 &filter->fdir_filter;
3134 ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3139 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3143 ret = i40e_flow_parse_attr(attr, error);
3147 cons_filter_type = RTE_ETH_FILTER_FDIR;
3149 if (dev->data->dev_conf.fdir_conf.mode !=
3150 RTE_FDIR_MODE_PERFECT) {
3151 rte_flow_error_set(error, ENOTSUP,
3152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3154 "Check the mode in fdir_conf.");
3161 /* Parse to get the action info of a tunnel filter
3162 * Tunnel action only supports PF, VF and QUEUE.
3165 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3166 const struct rte_flow_action *actions,
3167 struct rte_flow_error *error,
3168 struct i40e_tunnel_filter_conf *filter)
3170 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 const struct rte_flow_action *act;
3172 const struct rte_flow_action_queue *act_q;
3173 const struct rte_flow_action_vf *act_vf;
3176 /* Check if the first non-void action is PF or VF. */
3177 NEXT_ITEM_OF_ACTION(act, actions, index);
3178 if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3179 act->type != RTE_FLOW_ACTION_TYPE_VF) {
3180 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3181 act, "Not supported action.");
3185 if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3187 filter->vf_id = act_vf->id;
3188 filter->is_to_vf = 1;
3189 if (filter->vf_id >= pf->vf_num) {
3190 rte_flow_error_set(error, EINVAL,
3191 RTE_FLOW_ERROR_TYPE_ACTION,
3192 act, "Invalid VF ID for tunnel filter");
3197 /* Check if the next non-void item is QUEUE */
3199 NEXT_ITEM_OF_ACTION(act, actions, index);
3200 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3202 filter->queue_id = act_q->index;
3203 if ((!filter->is_to_vf) &&
3204 (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3205 rte_flow_error_set(error, EINVAL,
3206 RTE_FLOW_ERROR_TYPE_ACTION,
3207 act, "Invalid queue ID for tunnel filter");
3209 } else if (filter->is_to_vf &&
3210 (filter->queue_id >= pf->vf_nb_qps)) {
3211 rte_flow_error_set(error, EINVAL,
3212 RTE_FLOW_ERROR_TYPE_ACTION,
3213 act, "Invalid queue ID for tunnel filter");
3218 /* Check if the next non-void item is END */
3220 NEXT_ITEM_OF_ACTION(act, actions, index);
3221 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3222 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3223 act, "Not supported action.");
3230 static uint16_t i40e_supported_tunnel_filter_types[] = {
3231 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3232 ETH_TUNNEL_FILTER_IVLAN,
3233 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3234 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3235 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3236 ETH_TUNNEL_FILTER_IMAC,
3237 ETH_TUNNEL_FILTER_IMAC,
3241 i40e_check_tunnel_filter_type(uint8_t filter_type)
3245 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3246 if (filter_type == i40e_supported_tunnel_filter_types[i])
3253 /* 1. Last in item should be NULL as range is not supported.
3254 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3255 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3256 * 3. Mask of fields which need to be matched should be
3258 * 4. Mask of fields which needn't to be matched should be
3262 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3263 const struct rte_flow_item *pattern,
3264 struct rte_flow_error *error,
3265 struct i40e_tunnel_filter_conf *filter)
3267 const struct rte_flow_item *item = pattern;
3268 const struct rte_flow_item_eth *eth_spec;
3269 const struct rte_flow_item_eth *eth_mask;
3270 const struct rte_flow_item_vxlan *vxlan_spec;
3271 const struct rte_flow_item_vxlan *vxlan_mask;
3272 const struct rte_flow_item_vlan *vlan_spec;
3273 const struct rte_flow_item_vlan *vlan_mask;
3274 uint8_t filter_type = 0;
3275 bool is_vni_masked = 0;
3276 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3277 enum rte_flow_item_type item_type;
3278 bool vxlan_flag = 0;
3279 uint32_t tenant_id_be = 0;
3282 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3284 rte_flow_error_set(error, EINVAL,
3285 RTE_FLOW_ERROR_TYPE_ITEM,
3287 "Not support range");
3290 item_type = item->type;
3291 switch (item_type) {
3292 case RTE_FLOW_ITEM_TYPE_ETH:
3293 eth_spec = item->spec;
3294 eth_mask = item->mask;
3296 /* Check if ETH item is used for place holder.
3297 * If yes, both spec and mask should be NULL.
3298 * If no, both spec and mask shouldn't be NULL.
3300 if ((!eth_spec && eth_mask) ||
3301 (eth_spec && !eth_mask)) {
3302 rte_flow_error_set(error, EINVAL,
3303 RTE_FLOW_ERROR_TYPE_ITEM,
3305 "Invalid ether spec/mask");
3309 if (eth_spec && eth_mask) {
3310 /* DST address of inner MAC shouldn't be masked.
3311 * SRC address of Inner MAC should be masked.
3313 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3314 !is_zero_ether_addr(ð_mask->src) ||
3316 rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ITEM,
3319 "Invalid ether spec/mask");
3324 rte_memcpy(&filter->outer_mac,
3327 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3329 rte_memcpy(&filter->inner_mac,
3332 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3336 case RTE_FLOW_ITEM_TYPE_VLAN:
3337 vlan_spec = item->spec;
3338 vlan_mask = item->mask;
3339 if (!(vlan_spec && vlan_mask) ||
3340 vlan_mask->inner_type) {
3341 rte_flow_error_set(error, EINVAL,
3342 RTE_FLOW_ERROR_TYPE_ITEM,
3344 "Invalid vlan item");
3348 if (vlan_spec && vlan_mask) {
3349 if (vlan_mask->tci ==
3350 rte_cpu_to_be_16(I40E_TCI_MASK))
3351 filter->inner_vlan =
3352 rte_be_to_cpu_16(vlan_spec->tci) &
3354 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3357 case RTE_FLOW_ITEM_TYPE_IPV4:
3358 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3359 /* IPv4 is used to describe protocol,
3360 * spec and mask should be NULL.
3362 if (item->spec || item->mask) {
3363 rte_flow_error_set(error, EINVAL,
3364 RTE_FLOW_ERROR_TYPE_ITEM,
3366 "Invalid IPv4 item");
3370 case RTE_FLOW_ITEM_TYPE_IPV6:
3371 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3372 /* IPv6 is used to describe protocol,
3373 * spec and mask should be NULL.
3375 if (item->spec || item->mask) {
3376 rte_flow_error_set(error, EINVAL,
3377 RTE_FLOW_ERROR_TYPE_ITEM,
3379 "Invalid IPv6 item");
3383 case RTE_FLOW_ITEM_TYPE_UDP:
3384 /* UDP is used to describe protocol,
3385 * spec and mask should be NULL.
3387 if (item->spec || item->mask) {
3388 rte_flow_error_set(error, EINVAL,
3389 RTE_FLOW_ERROR_TYPE_ITEM,
3391 "Invalid UDP item");
3395 case RTE_FLOW_ITEM_TYPE_VXLAN:
3396 vxlan_spec = item->spec;
3397 vxlan_mask = item->mask;
3398 /* Check if VXLAN item is used to describe protocol.
3399 * If yes, both spec and mask should be NULL.
3400 * If no, both spec and mask shouldn't be NULL.
3402 if ((!vxlan_spec && vxlan_mask) ||
3403 (vxlan_spec && !vxlan_mask)) {
3404 rte_flow_error_set(error, EINVAL,
3405 RTE_FLOW_ERROR_TYPE_ITEM,
3407 "Invalid VXLAN item");
3411 /* Check if VNI is masked. */
3412 if (vxlan_spec && vxlan_mask) {
3414 !!memcmp(vxlan_mask->vni, vni_mask,
3416 if (is_vni_masked) {
3417 rte_flow_error_set(error, EINVAL,
3418 RTE_FLOW_ERROR_TYPE_ITEM,
3420 "Invalid VNI mask");
3424 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3425 vxlan_spec->vni, 3);
3427 rte_be_to_cpu_32(tenant_id_be);
3428 filter_type |= ETH_TUNNEL_FILTER_TENID;
3438 ret = i40e_check_tunnel_filter_type(filter_type);
3440 rte_flow_error_set(error, EINVAL,
3441 RTE_FLOW_ERROR_TYPE_ITEM,
3443 "Invalid filter type");
3446 filter->filter_type = filter_type;
3448 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3454 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3455 const struct rte_flow_attr *attr,
3456 const struct rte_flow_item pattern[],
3457 const struct rte_flow_action actions[],
3458 struct rte_flow_error *error,
3459 union i40e_filter_t *filter)
3461 struct i40e_tunnel_filter_conf *tunnel_filter =
3462 &filter->consistent_tunnel_filter;
3465 ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3466 error, tunnel_filter);
3470 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3474 ret = i40e_flow_parse_attr(attr, error);
3478 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3483 /* 1. Last in item should be NULL as range is not supported.
3484 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3485 * IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3486 * 3. Mask of fields which need to be matched should be
3488 * 4. Mask of fields which needn't to be matched should be
3492 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3493 const struct rte_flow_item *pattern,
3494 struct rte_flow_error *error,
3495 struct i40e_tunnel_filter_conf *filter)
3497 const struct rte_flow_item *item = pattern;
3498 const struct rte_flow_item_eth *eth_spec;
3499 const struct rte_flow_item_eth *eth_mask;
3500 const struct rte_flow_item_nvgre *nvgre_spec;
3501 const struct rte_flow_item_nvgre *nvgre_mask;
3502 const struct rte_flow_item_vlan *vlan_spec;
3503 const struct rte_flow_item_vlan *vlan_mask;
3504 enum rte_flow_item_type item_type;
3505 uint8_t filter_type = 0;
3506 bool is_tni_masked = 0;
3507 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3508 bool nvgre_flag = 0;
3509 uint32_t tenant_id_be = 0;
3512 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3514 rte_flow_error_set(error, EINVAL,
3515 RTE_FLOW_ERROR_TYPE_ITEM,
3517 "Not support range");
3520 item_type = item->type;
3521 switch (item_type) {
3522 case RTE_FLOW_ITEM_TYPE_ETH:
3523 eth_spec = item->spec;
3524 eth_mask = item->mask;
3526 /* Check if ETH item is used for place holder.
3527 * If yes, both spec and mask should be NULL.
3528 * If no, both spec and mask shouldn't be NULL.
3530 if ((!eth_spec && eth_mask) ||
3531 (eth_spec && !eth_mask)) {
3532 rte_flow_error_set(error, EINVAL,
3533 RTE_FLOW_ERROR_TYPE_ITEM,
3535 "Invalid ether spec/mask");
3539 if (eth_spec && eth_mask) {
3540 /* DST address of inner MAC shouldn't be masked.
3541 * SRC address of Inner MAC should be masked.
3543 if (!is_broadcast_ether_addr(ð_mask->dst) ||
3544 !is_zero_ether_addr(ð_mask->src) ||
3546 rte_flow_error_set(error, EINVAL,
3547 RTE_FLOW_ERROR_TYPE_ITEM,
3549 "Invalid ether spec/mask");
3554 rte_memcpy(&filter->outer_mac,
3557 filter_type |= ETH_TUNNEL_FILTER_OMAC;
3559 rte_memcpy(&filter->inner_mac,
3562 filter_type |= ETH_TUNNEL_FILTER_IMAC;
3567 case RTE_FLOW_ITEM_TYPE_VLAN:
3568 vlan_spec = item->spec;
3569 vlan_mask = item->mask;
3570 if (!(vlan_spec && vlan_mask) ||
3571 vlan_mask->inner_type) {
3572 rte_flow_error_set(error, EINVAL,
3573 RTE_FLOW_ERROR_TYPE_ITEM,
3575 "Invalid vlan item");
3579 if (vlan_spec && vlan_mask) {
3580 if (vlan_mask->tci ==
3581 rte_cpu_to_be_16(I40E_TCI_MASK))
3582 filter->inner_vlan =
3583 rte_be_to_cpu_16(vlan_spec->tci) &
3585 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3588 case RTE_FLOW_ITEM_TYPE_IPV4:
3589 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3590 /* IPv4 is used to describe protocol,
3591 * spec and mask should be NULL.
3593 if (item->spec || item->mask) {
3594 rte_flow_error_set(error, EINVAL,
3595 RTE_FLOW_ERROR_TYPE_ITEM,
3597 "Invalid IPv4 item");
3601 case RTE_FLOW_ITEM_TYPE_IPV6:
3602 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3603 /* IPv6 is used to describe protocol,
3604 * spec and mask should be NULL.
3606 if (item->spec || item->mask) {
3607 rte_flow_error_set(error, EINVAL,
3608 RTE_FLOW_ERROR_TYPE_ITEM,
3610 "Invalid IPv6 item");
3614 case RTE_FLOW_ITEM_TYPE_NVGRE:
3615 nvgre_spec = item->spec;
3616 nvgre_mask = item->mask;
3617 /* Check if NVGRE item is used to describe protocol.
3618 * If yes, both spec and mask should be NULL.
3619 * If no, both spec and mask shouldn't be NULL.
3621 if ((!nvgre_spec && nvgre_mask) ||
3622 (nvgre_spec && !nvgre_mask)) {
3623 rte_flow_error_set(error, EINVAL,
3624 RTE_FLOW_ERROR_TYPE_ITEM,
3626 "Invalid NVGRE item");
3630 if (nvgre_spec && nvgre_mask) {
3632 !!memcmp(nvgre_mask->tni, tni_mask,
3634 if (is_tni_masked) {
3635 rte_flow_error_set(error, EINVAL,
3636 RTE_FLOW_ERROR_TYPE_ITEM,
3638 "Invalid TNI mask");
3641 if (nvgre_mask->protocol &&
3642 nvgre_mask->protocol != 0xFFFF) {
3643 rte_flow_error_set(error, EINVAL,
3644 RTE_FLOW_ERROR_TYPE_ITEM,
3646 "Invalid NVGRE item");
3649 if (nvgre_mask->c_k_s_rsvd0_ver &&
3650 nvgre_mask->c_k_s_rsvd0_ver !=
3651 rte_cpu_to_be_16(0xFFFF)) {
3652 rte_flow_error_set(error, EINVAL,
3653 RTE_FLOW_ERROR_TYPE_ITEM,
3655 "Invalid NVGRE item");
3658 if (nvgre_spec->c_k_s_rsvd0_ver !=
3659 rte_cpu_to_be_16(0x2000) &&
3660 nvgre_mask->c_k_s_rsvd0_ver) {
3661 rte_flow_error_set(error, EINVAL,
3662 RTE_FLOW_ERROR_TYPE_ITEM,
3664 "Invalid NVGRE item");
3667 if (nvgre_mask->protocol &&
3668 nvgre_spec->protocol !=
3669 rte_cpu_to_be_16(0x6558)) {
3670 rte_flow_error_set(error, EINVAL,
3671 RTE_FLOW_ERROR_TYPE_ITEM,
3673 "Invalid NVGRE item");
3676 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3677 nvgre_spec->tni, 3);
3679 rte_be_to_cpu_32(tenant_id_be);
3680 filter_type |= ETH_TUNNEL_FILTER_TENID;
3690 ret = i40e_check_tunnel_filter_type(filter_type);
3692 rte_flow_error_set(error, EINVAL,
3693 RTE_FLOW_ERROR_TYPE_ITEM,
3695 "Invalid filter type");
3698 filter->filter_type = filter_type;
3700 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3706 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3707 const struct rte_flow_attr *attr,
3708 const struct rte_flow_item pattern[],
3709 const struct rte_flow_action actions[],
3710 struct rte_flow_error *error,
3711 union i40e_filter_t *filter)
3713 struct i40e_tunnel_filter_conf *tunnel_filter =
3714 &filter->consistent_tunnel_filter;
3717 ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3718 error, tunnel_filter);
3722 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3726 ret = i40e_flow_parse_attr(attr, error);
3730 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3735 /* 1. Last in item should be NULL as range is not supported.
3736 * 2. Supported filter types: MPLS label.
3737 * 3. Mask of fields which need to be matched should be
3739 * 4. Mask of fields which needn't to be matched should be
3743 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3744 const struct rte_flow_item *pattern,
3745 struct rte_flow_error *error,
3746 struct i40e_tunnel_filter_conf *filter)
3748 const struct rte_flow_item *item = pattern;
3749 const struct rte_flow_item_mpls *mpls_spec;
3750 const struct rte_flow_item_mpls *mpls_mask;
3751 enum rte_flow_item_type item_type;
3752 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3753 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3754 uint32_t label_be = 0;
3756 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3758 rte_flow_error_set(error, EINVAL,
3759 RTE_FLOW_ERROR_TYPE_ITEM,
3761 "Not support range");
3764 item_type = item->type;
3765 switch (item_type) {
3766 case RTE_FLOW_ITEM_TYPE_ETH:
3767 if (item->spec || item->mask) {
3768 rte_flow_error_set(error, EINVAL,
3769 RTE_FLOW_ERROR_TYPE_ITEM,
3771 "Invalid ETH item");
3775 case RTE_FLOW_ITEM_TYPE_IPV4:
3776 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3777 /* IPv4 is used to describe protocol,
3778 * spec and mask should be NULL.
3780 if (item->spec || item->mask) {
3781 rte_flow_error_set(error, EINVAL,
3782 RTE_FLOW_ERROR_TYPE_ITEM,
3784 "Invalid IPv4 item");
3788 case RTE_FLOW_ITEM_TYPE_IPV6:
3789 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3790 /* IPv6 is used to describe protocol,
3791 * spec and mask should be NULL.
3793 if (item->spec || item->mask) {
3794 rte_flow_error_set(error, EINVAL,
3795 RTE_FLOW_ERROR_TYPE_ITEM,
3797 "Invalid IPv6 item");
3801 case RTE_FLOW_ITEM_TYPE_UDP:
3802 /* UDP is used to describe protocol,
3803 * spec and mask should be NULL.
3805 if (item->spec || item->mask) {
3806 rte_flow_error_set(error, EINVAL,
3807 RTE_FLOW_ERROR_TYPE_ITEM,
3809 "Invalid UDP item");
3814 case RTE_FLOW_ITEM_TYPE_GRE:
3815 /* GRE is used to describe protocol,
3816 * spec and mask should be NULL.
3818 if (item->spec || item->mask) {
3819 rte_flow_error_set(error, EINVAL,
3820 RTE_FLOW_ERROR_TYPE_ITEM,
3822 "Invalid GRE item");
3826 case RTE_FLOW_ITEM_TYPE_MPLS:
3827 mpls_spec = item->spec;
3828 mpls_mask = item->mask;
3830 if (!mpls_spec || !mpls_mask) {
3831 rte_flow_error_set(error, EINVAL,
3832 RTE_FLOW_ERROR_TYPE_ITEM,
3834 "Invalid MPLS item");
3838 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3839 rte_flow_error_set(error, EINVAL,
3840 RTE_FLOW_ERROR_TYPE_ITEM,
3842 "Invalid MPLS label mask");
3845 rte_memcpy(((uint8_t *)&label_be + 1),
3846 mpls_spec->label_tc_s, 3);
3847 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3855 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3857 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3863 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3864 const struct rte_flow_attr *attr,
3865 const struct rte_flow_item pattern[],
3866 const struct rte_flow_action actions[],
3867 struct rte_flow_error *error,
3868 union i40e_filter_t *filter)
3870 struct i40e_tunnel_filter_conf *tunnel_filter =
3871 &filter->consistent_tunnel_filter;
3874 ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3875 error, tunnel_filter);
3879 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3883 ret = i40e_flow_parse_attr(attr, error);
3887 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3892 /* 1. Last in item should be NULL as range is not supported.
3893 * 2. Supported filter types: GTP TEID.
3894 * 3. Mask of fields which need to be matched should be
3896 * 4. Mask of fields which needn't to be matched should be
3898 * 5. GTP profile supports GTPv1 only.
3899 * 6. GTP-C response message ('source_port' = 2123) is not supported.
3902 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3903 const struct rte_flow_item *pattern,
3904 struct rte_flow_error *error,
3905 struct i40e_tunnel_filter_conf *filter)
3907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3908 const struct rte_flow_item *item = pattern;
3909 const struct rte_flow_item_gtp *gtp_spec;
3910 const struct rte_flow_item_gtp *gtp_mask;
3911 enum rte_flow_item_type item_type;
3913 if (!pf->gtp_support) {
3914 rte_flow_error_set(error, EINVAL,
3915 RTE_FLOW_ERROR_TYPE_ITEM,
3917 "GTP is not supported by default.");
3921 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3923 rte_flow_error_set(error, EINVAL,
3924 RTE_FLOW_ERROR_TYPE_ITEM,
3926 "Not support range");
3929 item_type = item->type;
3930 switch (item_type) {
3931 case RTE_FLOW_ITEM_TYPE_ETH:
3932 if (item->spec || item->mask) {
3933 rte_flow_error_set(error, EINVAL,
3934 RTE_FLOW_ERROR_TYPE_ITEM,
3936 "Invalid ETH item");
3940 case RTE_FLOW_ITEM_TYPE_IPV4:
3941 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3942 /* IPv4 is used to describe protocol,
3943 * spec and mask should be NULL.
3945 if (item->spec || item->mask) {
3946 rte_flow_error_set(error, EINVAL,
3947 RTE_FLOW_ERROR_TYPE_ITEM,
3949 "Invalid IPv4 item");
3953 case RTE_FLOW_ITEM_TYPE_UDP:
3954 if (item->spec || item->mask) {
3955 rte_flow_error_set(error, EINVAL,
3956 RTE_FLOW_ERROR_TYPE_ITEM,
3958 "Invalid UDP item");
3962 case RTE_FLOW_ITEM_TYPE_GTPC:
3963 case RTE_FLOW_ITEM_TYPE_GTPU:
3964 gtp_spec = item->spec;
3965 gtp_mask = item->mask;
3967 if (!gtp_spec || !gtp_mask) {
3968 rte_flow_error_set(error, EINVAL,
3969 RTE_FLOW_ERROR_TYPE_ITEM,
3971 "Invalid GTP item");
3975 if (gtp_mask->v_pt_rsv_flags ||
3976 gtp_mask->msg_type ||
3977 gtp_mask->msg_len ||
3978 gtp_mask->teid != UINT32_MAX) {
3979 rte_flow_error_set(error, EINVAL,
3980 RTE_FLOW_ERROR_TYPE_ITEM,
3982 "Invalid GTP mask");
3986 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3987 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3988 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3989 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3991 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4003 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4004 const struct rte_flow_attr *attr,
4005 const struct rte_flow_item pattern[],
4006 const struct rte_flow_action actions[],
4007 struct rte_flow_error *error,
4008 union i40e_filter_t *filter)
4010 struct i40e_tunnel_filter_conf *tunnel_filter =
4011 &filter->consistent_tunnel_filter;
4014 ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4015 error, tunnel_filter);
4019 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4023 ret = i40e_flow_parse_attr(attr, error);
4027 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4032 /* 1. Last in item should be NULL as range is not supported.
4033 * 2. Supported filter types: QINQ.
4034 * 3. Mask of fields which need to be matched should be
4036 * 4. Mask of fields which needn't to be matched should be
4040 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4041 const struct rte_flow_item *pattern,
4042 struct rte_flow_error *error,
4043 struct i40e_tunnel_filter_conf *filter)
4045 const struct rte_flow_item *item = pattern;
4046 const struct rte_flow_item_vlan *vlan_spec = NULL;
4047 const struct rte_flow_item_vlan *vlan_mask = NULL;
4048 const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4049 const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4050 const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4051 const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4053 enum rte_flow_item_type item_type;
4056 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4058 rte_flow_error_set(error, EINVAL,
4059 RTE_FLOW_ERROR_TYPE_ITEM,
4061 "Not support range");
4064 item_type = item->type;
4065 switch (item_type) {
4066 case RTE_FLOW_ITEM_TYPE_ETH:
4067 if (item->spec || item->mask) {
4068 rte_flow_error_set(error, EINVAL,
4069 RTE_FLOW_ERROR_TYPE_ITEM,
4071 "Invalid ETH item");
4075 case RTE_FLOW_ITEM_TYPE_VLAN:
4076 vlan_spec = item->spec;
4077 vlan_mask = item->mask;
4079 if (!(vlan_spec && vlan_mask) ||
4080 vlan_mask->inner_type) {
4081 rte_flow_error_set(error, EINVAL,
4082 RTE_FLOW_ERROR_TYPE_ITEM,
4084 "Invalid vlan item");
4089 o_vlan_spec = vlan_spec;
4090 o_vlan_mask = vlan_mask;
4093 i_vlan_spec = vlan_spec;
4094 i_vlan_mask = vlan_mask;
4104 /* Get filter specification */
4105 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4106 rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4107 (i_vlan_mask != NULL) &&
4108 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4109 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4111 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4114 rte_flow_error_set(error, EINVAL,
4115 RTE_FLOW_ERROR_TYPE_ITEM,
4117 "Invalid filter type");
4121 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4126 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4127 const struct rte_flow_attr *attr,
4128 const struct rte_flow_item pattern[],
4129 const struct rte_flow_action actions[],
4130 struct rte_flow_error *error,
4131 union i40e_filter_t *filter)
4133 struct i40e_tunnel_filter_conf *tunnel_filter =
4134 &filter->consistent_tunnel_filter;
4137 ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4138 error, tunnel_filter);
4142 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4146 ret = i40e_flow_parse_attr(attr, error);
4150 cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4156 * This function is used to do configuration i40e existing RSS with rte_flow.
4157 * It also enable queue region configuration using flow API for i40e.
4158 * pattern can be used indicate what parameters will be include in flow,
4159 * like user_priority or flowtype for queue region or HASH function for RSS.
4160 * Action is used to transmit parameter like queue index and HASH
4161 * function for RSS, or flowtype for queue region configuration.
4164 * Case 1: only ETH, indicate flowtype for queue region will be parsed.
4165 * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4166 * Case 3: none, indicate RSS related will be parsed in action.
4167 * Any pattern other the ETH or VLAN will be treated as invalid except END.
4168 * So, pattern choice is depened on the purpose of configuration of
4171 * action RSS will be uaed to transmit valid parameter with
4172 * struct rte_flow_action_rss for all the 3 case.
4175 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4176 const struct rte_flow_item *pattern,
4177 struct rte_flow_error *error,
4178 uint8_t *action_flag,
4179 struct i40e_queue_regions *info)
4181 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4182 const struct rte_flow_item *item = pattern;
4183 enum rte_flow_item_type item_type;
4185 if (item->type == RTE_FLOW_ITEM_TYPE_END)
4188 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4190 rte_flow_error_set(error, EINVAL,
4191 RTE_FLOW_ERROR_TYPE_ITEM,
4193 "Not support range");
4196 item_type = item->type;
4197 switch (item_type) {
4198 case RTE_FLOW_ITEM_TYPE_ETH:
4201 case RTE_FLOW_ITEM_TYPE_VLAN:
4202 vlan_spec = item->spec;
4203 vlan_mask = item->mask;
4204 if (vlan_spec && vlan_mask) {
4205 if (vlan_mask->tci ==
4206 rte_cpu_to_be_16(I40E_TCI_MASK)) {
4207 info->region[0].user_priority[0] =
4209 vlan_spec->tci) >> 13) & 0x7;
4210 info->region[0].user_priority_num = 1;
4211 info->queue_region_number = 1;
4217 rte_flow_error_set(error, EINVAL,
4218 RTE_FLOW_ERROR_TYPE_ITEM,
4220 "Not support range");
4229 * This function is used to parse rss queue index, total queue number and
4230 * hash functions, If the purpose of this configuration is for queue region
4231 * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4232 * In queue region configuration, it also need to parse hardware flowtype
4233 * and user_priority from configuration, it will also cheeck the validity
4234 * of these parameters. For example, The queue region sizes should
4235 * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4236 * hw_flowtype or PCTYPE max index should be 63, the user priority
4237 * max index should be 7, and so on. And also, queue index should be
4238 * continuous sequence and queue region index should be part of rss
4239 * queue index for this port.
4242 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4243 const struct rte_flow_action *actions,
4244 struct rte_flow_error *error,
4245 uint8_t action_flag,
4246 struct i40e_queue_regions *conf_info,
4247 union i40e_filter_t *filter)
4249 const struct rte_flow_action *act;
4250 const struct rte_flow_action_rss *rss;
4251 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4252 struct i40e_queue_regions *info = &pf->queue_region;
4253 struct i40e_rte_flow_rss_conf *rss_config =
4255 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4256 uint16_t i, j, n, tmp;
4258 uint64_t hf_bit = 1;
4260 NEXT_ITEM_OF_ACTION(act, actions, index);
4264 * rss only supports forwarding,
4265 * check if the first not void action is RSS.
4267 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4268 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4269 rte_flow_error_set(error, EINVAL,
4270 RTE_FLOW_ERROR_TYPE_ACTION,
4271 act, "Not supported action.");
4276 for (n = 0; n < 64; n++) {
4277 if (rss->types & (hf_bit << n)) {
4278 conf_info->region[0].hw_flowtype[0] = n;
4279 conf_info->region[0].flowtype_num = 1;
4280 conf_info->queue_region_number = 1;
4287 * Do some queue region related parameters check
4288 * in order to keep queue index for queue region to be
4289 * continuous sequence and also to be part of RSS
4290 * queue index for this port.
4292 if (conf_info->queue_region_number) {
4293 for (i = 0; i < rss->queue_num; i++) {
4294 for (j = 0; j < rss_info->conf.queue_num; j++) {
4295 if (rss->queue[i] == rss_info->conf.queue[j])
4298 if (j == rss_info->conf.queue_num) {
4299 rte_flow_error_set(error, EINVAL,
4300 RTE_FLOW_ERROR_TYPE_ACTION,
4307 for (i = 0; i < rss->queue_num - 1; i++) {
4308 if (rss->queue[i + 1] != rss->queue[i] + 1) {
4309 rte_flow_error_set(error, EINVAL,
4310 RTE_FLOW_ERROR_TYPE_ACTION,
4318 /* Parse queue region related parameters from configuration */
4319 for (n = 0; n < conf_info->queue_region_number; n++) {
4320 if (conf_info->region[n].user_priority_num ||
4321 conf_info->region[n].flowtype_num) {
4322 if (!((rte_is_power_of_2(rss->queue_num)) &&
4323 rss->queue_num <= 64)) {
4324 rte_flow_error_set(error, EINVAL,
4325 RTE_FLOW_ERROR_TYPE_ACTION,
4327 "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4328 "total number of queues do not exceed the VSI allocation");
4332 if (conf_info->region[n].user_priority[n] >=
4333 I40E_MAX_USER_PRIORITY) {
4334 rte_flow_error_set(error, EINVAL,
4335 RTE_FLOW_ERROR_TYPE_ACTION,
4337 "the user priority max index is 7");
4341 if (conf_info->region[n].hw_flowtype[n] >=
4342 I40E_FILTER_PCTYPE_MAX) {
4343 rte_flow_error_set(error, EINVAL,
4344 RTE_FLOW_ERROR_TYPE_ACTION,
4346 "the hw_flowtype or PCTYPE max index is 63");
4350 for (i = 0; i < info->queue_region_number; i++) {
4351 if (info->region[i].queue_num ==
4353 info->region[i].queue_start_index ==
4358 if (i == info->queue_region_number) {
4359 if (i > I40E_REGION_MAX_INDEX) {
4360 rte_flow_error_set(error, EINVAL,
4361 RTE_FLOW_ERROR_TYPE_ACTION,
4363 "the queue region max index is 7");
4367 info->region[i].queue_num =
4369 info->region[i].queue_start_index =
4371 info->region[i].region_id =
4372 info->queue_region_number;
4374 j = info->region[i].user_priority_num;
4375 tmp = conf_info->region[n].user_priority[0];
4376 if (conf_info->region[n].user_priority_num) {
4377 info->region[i].user_priority[j] = tmp;
4378 info->region[i].user_priority_num++;
4381 j = info->region[i].flowtype_num;
4382 tmp = conf_info->region[n].hw_flowtype[0];
4383 if (conf_info->region[n].flowtype_num) {
4384 info->region[i].hw_flowtype[j] = tmp;
4385 info->region[i].flowtype_num++;
4387 info->queue_region_number++;
4389 j = info->region[i].user_priority_num;
4390 tmp = conf_info->region[n].user_priority[0];
4391 if (conf_info->region[n].user_priority_num) {
4392 info->region[i].user_priority[j] = tmp;
4393 info->region[i].user_priority_num++;
4396 j = info->region[i].flowtype_num;
4397 tmp = conf_info->region[n].hw_flowtype[0];
4398 if (conf_info->region[n].flowtype_num) {
4399 info->region[i].hw_flowtype[j] = tmp;
4400 info->region[i].flowtype_num++;
4405 rss_config->queue_region_conf = TRUE;
4409 * Return function if this flow is used for queue region configuration
4411 if (rss_config->queue_region_conf)
4414 if (!rss || !rss->queue_num) {
4415 rte_flow_error_set(error, EINVAL,
4416 RTE_FLOW_ERROR_TYPE_ACTION,
4422 for (n = 0; n < rss->queue_num; n++) {
4423 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4424 rte_flow_error_set(error, EINVAL,
4425 RTE_FLOW_ERROR_TYPE_ACTION,
4427 "queue id > max number of queues");
4432 /* Parse RSS related parameters from configuration */
4433 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4434 return rte_flow_error_set
4435 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4436 "non-default RSS hash functions are not supported");
4438 return rte_flow_error_set
4439 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4440 "a nonzero RSS encapsulation level is not supported");
4441 if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4442 return rte_flow_error_set
4443 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4444 "RSS hash key too large");
4445 if (rss->queue_num > RTE_DIM(rss_config->queue))
4446 return rte_flow_error_set
4447 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4448 "too many queues for RSS context");
4449 if (i40e_rss_conf_init(rss_config, rss))
4450 return rte_flow_error_set
4451 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4452 "RSS context initialization failure");
4456 /* check if the next not void action is END */
4457 NEXT_ITEM_OF_ACTION(act, actions, index);
4458 if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4459 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4460 rte_flow_error_set(error, EINVAL,
4461 RTE_FLOW_ERROR_TYPE_ACTION,
4462 act, "Not supported action.");
4465 rss_config->queue_region_conf = FALSE;
4471 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4472 const struct rte_flow_attr *attr,
4473 const struct rte_flow_item pattern[],
4474 const struct rte_flow_action actions[],
4475 union i40e_filter_t *filter,
4476 struct rte_flow_error *error)
4479 struct i40e_queue_regions info;
4480 uint8_t action_flag = 0;
4482 memset(&info, 0, sizeof(struct i40e_queue_regions));
4484 ret = i40e_flow_parse_rss_pattern(dev, pattern,
4485 error, &action_flag, &info);
4489 ret = i40e_flow_parse_rss_action(dev, actions, error,
4490 action_flag, &info, filter);
4494 ret = i40e_flow_parse_attr(attr, error);
4498 cons_filter_type = RTE_ETH_FILTER_HASH;
4504 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4505 struct i40e_rte_flow_rss_conf *conf)
4507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4508 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511 if (conf->queue_region_conf) {
4512 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4513 conf->queue_region_conf = 0;
4515 ret = i40e_config_rss_filter(pf, conf, 1);
4521 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4522 struct i40e_rte_flow_rss_conf *conf)
4524 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4525 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4529 i40e_config_rss_filter(pf, conf, 0);
4534 i40e_flow_validate(struct rte_eth_dev *dev,
4535 const struct rte_flow_attr *attr,
4536 const struct rte_flow_item pattern[],
4537 const struct rte_flow_action actions[],
4538 struct rte_flow_error *error)
4540 struct rte_flow_item *items; /* internal pattern w/o VOID items */
4541 parse_filter_t parse_filter;
4542 uint32_t item_num = 0; /* non-void item number of pattern*/
4545 int ret = I40E_NOT_SUPPORTED;
4548 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4549 NULL, "NULL pattern.");
4554 rte_flow_error_set(error, EINVAL,
4555 RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4556 NULL, "NULL action.");
4561 rte_flow_error_set(error, EINVAL,
4562 RTE_FLOW_ERROR_TYPE_ATTR,
4563 NULL, "NULL attribute.");
4567 memset(&cons_filter, 0, sizeof(cons_filter));
4569 /* Get the non-void item of action */
4570 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4573 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4574 ret = i40e_parse_rss_filter(dev, attr, pattern,
4575 actions, &cons_filter, error);
4580 /* Get the non-void item number of pattern */
4581 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4582 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4588 items = rte_zmalloc("i40e_pattern",
4589 item_num * sizeof(struct rte_flow_item), 0);
4591 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4592 NULL, "No memory for PMD internal items.");
4596 i40e_pattern_skip_void_item(items, pattern);
4600 parse_filter = i40e_find_parse_filter_func(items, &i);
4601 if (!parse_filter && !flag) {
4602 rte_flow_error_set(error, EINVAL,
4603 RTE_FLOW_ERROR_TYPE_ITEM,
4604 pattern, "Unsupported pattern");
4609 ret = parse_filter(dev, attr, items, actions,
4610 error, &cons_filter);
4612 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4619 static struct rte_flow *
4620 i40e_flow_create(struct rte_eth_dev *dev,
4621 const struct rte_flow_attr *attr,
4622 const struct rte_flow_item pattern[],
4623 const struct rte_flow_action actions[],
4624 struct rte_flow_error *error)
4626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4627 struct rte_flow *flow;
4630 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4632 rte_flow_error_set(error, ENOMEM,
4633 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4634 "Failed to allocate memory");
4638 ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4642 switch (cons_filter_type) {
4643 case RTE_ETH_FILTER_ETHERTYPE:
4644 ret = i40e_ethertype_filter_set(pf,
4645 &cons_filter.ethertype_filter, 1);
4648 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4649 i40e_ethertype_filter_list);
4651 case RTE_ETH_FILTER_FDIR:
4652 ret = i40e_flow_add_del_fdir_filter(dev,
4653 &cons_filter.fdir_filter, 1);
4656 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4657 i40e_fdir_filter_list);
4659 case RTE_ETH_FILTER_TUNNEL:
4660 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4661 &cons_filter.consistent_tunnel_filter, 1);
4664 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4665 i40e_tunnel_filter_list);
4667 case RTE_ETH_FILTER_HASH:
4668 ret = i40e_config_rss_filter_set(dev,
4669 &cons_filter.rss_conf);
4672 flow->rule = &pf->rss_info;
4678 flow->filter_type = cons_filter_type;
4679 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4683 rte_flow_error_set(error, -ret,
4684 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4685 "Failed to create flow.");
4691 i40e_flow_destroy(struct rte_eth_dev *dev,
4692 struct rte_flow *flow,
4693 struct rte_flow_error *error)
4695 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4696 enum rte_filter_type filter_type = flow->filter_type;
4699 switch (filter_type) {
4700 case RTE_ETH_FILTER_ETHERTYPE:
4701 ret = i40e_flow_destroy_ethertype_filter(pf,
4702 (struct i40e_ethertype_filter *)flow->rule);
4704 case RTE_ETH_FILTER_TUNNEL:
4705 ret = i40e_flow_destroy_tunnel_filter(pf,
4706 (struct i40e_tunnel_filter *)flow->rule);
4708 case RTE_ETH_FILTER_FDIR:
4709 ret = i40e_flow_add_del_fdir_filter(dev,
4710 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4712 case RTE_ETH_FILTER_HASH:
4713 ret = i40e_config_rss_filter_del(dev,
4714 (struct i40e_rte_flow_rss_conf *)flow->rule);
4717 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4724 TAILQ_REMOVE(&pf->flow_list, flow, node);
4727 rte_flow_error_set(error, -ret,
4728 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4729 "Failed to destroy flow.");
4735 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4736 struct i40e_ethertype_filter *filter)
4738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4739 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4740 struct i40e_ethertype_filter *node;
4741 struct i40e_control_filter_stats stats;
4745 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4746 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4747 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4748 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4749 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4751 memset(&stats, 0, sizeof(stats));
4752 ret = i40e_aq_add_rem_control_packet_filter(hw,
4753 filter->input.mac_addr.addr_bytes,
4754 filter->input.ether_type,
4755 flags, pf->main_vsi->seid,
4756 filter->queue, 0, &stats, NULL);
4760 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4764 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4770 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4771 struct i40e_tunnel_filter *filter)
4773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4774 struct i40e_vsi *vsi;
4775 struct i40e_pf_vf *vf;
4776 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4777 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4778 struct i40e_tunnel_filter *node;
4779 bool big_buffer = 0;
4782 memset(&cld_filter, 0, sizeof(cld_filter));
4783 ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4784 (struct ether_addr *)&cld_filter.element.outer_mac);
4785 ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4786 (struct ether_addr *)&cld_filter.element.inner_mac);
4787 cld_filter.element.inner_vlan = filter->input.inner_vlan;
4788 cld_filter.element.flags = filter->input.flags;
4789 cld_filter.element.tenant_id = filter->input.tenant_id;
4790 cld_filter.element.queue_number = filter->queue;
4791 rte_memcpy(cld_filter.general_fields,
4792 filter->input.general_fields,
4793 sizeof(cld_filter.general_fields));
4795 if (!filter->is_to_vf)
4798 vf = &pf->vfs[filter->vf_id];
4802 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4803 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4804 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4805 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4806 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4807 I40E_AQC_ADD_CLOUD_FILTER_0X10))
4811 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4814 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4815 &cld_filter.element, 1);
4819 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4823 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4829 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4831 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4834 ret = i40e_flow_flush_fdir_filter(pf);
4836 rte_flow_error_set(error, -ret,
4837 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4838 "Failed to flush FDIR flows.");
4842 ret = i40e_flow_flush_ethertype_filter(pf);
4844 rte_flow_error_set(error, -ret,
4845 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4846 "Failed to ethertype flush flows.");
4850 ret = i40e_flow_flush_tunnel_filter(pf);
4852 rte_flow_error_set(error, -ret,
4853 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4854 "Failed to flush tunnel flows.");
4858 ret = i40e_flow_flush_rss_filter(dev);
4860 rte_flow_error_set(error, -ret,
4861 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4862 "Failed to flush rss flows.");
4870 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4872 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4873 struct i40e_fdir_info *fdir_info = &pf->fdir;
4874 struct i40e_fdir_filter *fdir_filter;
4875 enum i40e_filter_pctype pctype;
4876 struct rte_flow *flow;
4880 ret = i40e_fdir_flush(dev);
4882 /* Delete FDIR filters in FDIR list. */
4883 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4884 ret = i40e_sw_fdir_filter_del(pf,
4885 &fdir_filter->fdir.input);
4890 /* Delete FDIR flows in flow list. */
4891 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4892 if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4893 TAILQ_REMOVE(&pf->flow_list, flow, node);
4898 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4899 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4900 pf->fdir.inset_flag[pctype] = 0;
4906 /* Flush all ethertype filters */
4908 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4910 struct i40e_ethertype_filter_list
4911 *ethertype_list = &pf->ethertype.ethertype_list;
4912 struct i40e_ethertype_filter *filter;
4913 struct rte_flow *flow;
4917 while ((filter = TAILQ_FIRST(ethertype_list))) {
4918 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4923 /* Delete ethertype flows in flow list. */
4924 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4925 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4926 TAILQ_REMOVE(&pf->flow_list, flow, node);
4934 /* Flush all tunnel filters */
4936 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4938 struct i40e_tunnel_filter_list
4939 *tunnel_list = &pf->tunnel.tunnel_list;
4940 struct i40e_tunnel_filter *filter;
4941 struct rte_flow *flow;
4945 while ((filter = TAILQ_FIRST(tunnel_list))) {
4946 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4951 /* Delete tunnel flows in flow list. */
4952 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4953 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4954 TAILQ_REMOVE(&pf->flow_list, flow, node);
4962 /* remove the rss filter */
4964 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4967 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969 int32_t ret = -EINVAL;
4971 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4973 if (rss_info->conf.queue_num)
4974 ret = i40e_config_rss_filter(pf, rss_info, FALSE);