1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_string_fns.h>
16 #include <rte_ether.h>
17 #include <ethdev_driver.h>
18 #include <rte_malloc.h>
19 #include <rte_memcpy.h>
21 #include "i40e_logs.h"
22 #include "base/i40e_prototype.h"
23 #include "base/i40e_adminq_cmd.h"
24 #include "base/i40e_type.h"
25 #include "i40e_ethdev.h"
26 #include "i40e_rxtx.h"
28 #include "rte_pmd_i40e.h"
30 #define I40E_CFG_CRCSTRIP_DEFAULT 1
33 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
34 struct virtchnl_queue_select *qsel,
38 * Bind PF queues with VSI and VF.
41 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
44 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
45 uint16_t vsi_id = vf->vsi->vsi_id;
46 uint16_t vf_id = vf->vf_idx;
47 uint16_t nb_qps = vf->vsi->nb_qps;
48 uint16_t qbase = vf->vsi->base_queue;
53 * VF should use scatter range queues. So, it needn't
54 * to set QBASE in this register.
56 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
57 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
59 /* Set to enable VFLAN_QTABLE[] registers valid */
60 I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
61 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
63 /* map PF queues to VF */
64 for (i = 0; i < nb_qps; i++) {
65 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
66 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
69 /* map PF queues to VSI */
70 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
71 if (2 * i > nb_qps - 1)
72 q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
76 if (2 * i + 1 > nb_qps - 1)
77 q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
79 q2 = qbase + 2 * i + 1;
81 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
82 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
91 * Proceed VF reset operation.
94 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
99 uint16_t vf_id, abs_vf_id, vf_msix_num;
101 struct virtchnl_queue_select qsel;
107 hw = I40E_PF_TO_HW(vf->pf);
109 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
111 /* Notify VF that we are in VFR progress */
112 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_INPROGRESS);
115 * If require a SW VF reset, a VFLR interrupt will be generated,
116 * this function will be called again. To avoid it,
117 * disable interrupt first.
120 vf->state = I40E_VF_INRESET;
121 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
122 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
123 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
124 I40E_WRITE_FLUSH(hw);
127 #define VFRESET_MAX_WAIT_CNT 100
128 /* Wait until VF reset is done */
129 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
131 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
132 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
136 if (i >= VFRESET_MAX_WAIT_CNT) {
137 PMD_DRV_LOG(ERR, "VF reset timeout");
140 /* This is not first time to do reset, do cleanup job first */
143 memset(&qsel, 0, sizeof(qsel));
144 for (i = 0; i < vf->vsi->nb_qps; i++)
145 qsel.rx_queues |= 1 << i;
146 qsel.tx_queues = qsel.rx_queues;
147 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
148 if (ret != I40E_SUCCESS) {
149 PMD_DRV_LOG(ERR, "Disable VF queues failed");
153 /* Disable VF interrupt setting */
154 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
155 for (i = 0; i < vf_msix_num; i++) {
157 val = I40E_VFINT_DYN_CTL0(vf_id);
159 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
161 I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
163 I40E_WRITE_FLUSH(hw);
166 ret = i40e_vsi_release(vf->vsi);
167 if (ret != I40E_SUCCESS) {
168 PMD_DRV_LOG(ERR, "Release VSI failed");
173 #define I40E_VF_PCI_ADDR 0xAA
174 #define I40E_VF_PEND_MASK 0x20
175 /* Check the pending transactions of this VF */
176 /* Use absolute VF id, refer to datasheet for details */
177 I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
178 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
179 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
181 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
182 if ((val & I40E_VF_PEND_MASK) == 0)
186 if (i >= VFRESET_MAX_WAIT_CNT) {
187 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
191 /* Reset done, Set COMPLETE flag and clear reset bit */
192 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_COMPLETED);
193 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
194 val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
195 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
197 I40E_WRITE_FLUSH(hw);
199 /* Allocate resource again */
200 if (pf->floating_veb && pf->floating_veb_list[vf_id]) {
201 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
204 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
205 vf->pf->main_vsi, vf->vf_idx);
208 if (vf->vsi == NULL) {
209 PMD_DRV_LOG(ERR, "Add vsi failed");
213 ret = i40e_pf_vf_queues_mapping(vf);
214 if (ret != I40E_SUCCESS) {
215 PMD_DRV_LOG(ERR, "queue mapping error");
216 i40e_vsi_release(vf->vsi);
220 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_VFACTIVE);
226 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
232 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
233 uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
236 ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
239 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
240 hw->aq.asq_last_status);
247 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf, uint8_t *msg,
250 struct virtchnl_version_info info;
252 /* VF and PF drivers need to follow the Virtchnl definition, No matter
253 * it's DPDK or other kernel drivers.
254 * The original DPDK host specific feature
255 * like CFG_VLAN_PVID and CONFIG_VSI_QUEUES_EXT will not available.
258 info.major = VIRTCHNL_VERSION_MAJOR;
259 vf->version = *(struct virtchnl_version_info *)msg;
260 if (VF_IS_V10(&vf->version))
261 info.minor = VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
263 info.minor = VIRTCHNL_VERSION_MINOR;
266 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
271 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
278 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
280 i40e_pf_host_vf_reset(vf, 1);
282 /* No feedback will be sent to VF for VFLR */
287 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf, uint8_t *msg,
290 struct virtchnl_vf_resource *vf_res = NULL;
291 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
293 uint64_t default_hena = I40E_RSS_HENA_ALL;
294 int ret = I40E_SUCCESS;
297 i40e_pf_host_send_msg_to_vf(vf,
298 VIRTCHNL_OP_GET_VF_RESOURCES,
299 I40E_NOT_SUPPORTED, NULL, 0);
303 /* only have 1 VSI by default */
304 len = sizeof(struct virtchnl_vf_resource) +
305 I40E_DEFAULT_VF_VSI_NUM *
306 sizeof(struct virtchnl_vsi_resource);
308 vf_res = rte_zmalloc("i40e_vf_res", len, 0);
309 if (vf_res == NULL) {
310 PMD_DRV_LOG(ERR, "failed to allocate mem");
311 ret = I40E_ERR_NO_MEMORY;
317 if (VF_IS_V10(&vf->version)) /* doesn't support offload negotiate */
318 vf->request_caps = VIRTCHNL_VF_OFFLOAD_L2 |
319 VIRTCHNL_VF_OFFLOAD_VLAN;
321 vf->request_caps = *(uint32_t *)msg;
323 /* enable all RSS by default,
324 * doesn't support hena setting by virtchnnl yet.
326 if (vf->request_caps & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
327 I40E_WRITE_REG(hw, I40E_VFQF_HENA1(0, vf->vf_idx),
328 (uint32_t)default_hena);
329 I40E_WRITE_REG(hw, I40E_VFQF_HENA1(1, vf->vf_idx),
330 (uint32_t)(default_hena >> 32));
331 I40E_WRITE_FLUSH(hw);
334 vf_res->vf_cap_flags = vf->request_caps &
335 I40E_VIRTCHNL_OFFLOAD_CAPS;
337 if (vf->request_caps & VIRTCHNL_VF_OFFLOAD_REQ_QUEUES)
338 vf_res->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_REQ_QUEUES;
340 /* For X722, it supports write back on ITR
341 * without binding queue to interrupt vector.
343 if (hw->mac.type == I40E_MAC_X722)
344 vf_res->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;
345 vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
346 vf_res->num_queue_pairs = vf->vsi->nb_qps;
347 vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
348 vf_res->rss_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 4;
349 vf_res->rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
351 /* Change below setting if PF host can support more VSIs for VF */
352 vf_res->vsi_res[0].vsi_type = VIRTCHNL_VSI_SRIOV;
353 vf_res->vsi_res[0].vsi_id = vf->vsi->vsi_id;
354 vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
355 rte_ether_addr_copy(&vf->mac_addr,
356 (struct rte_ether_addr *)vf_res->vsi_res[0].default_mac_addr);
359 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_VF_RESOURCES,
360 ret, (uint8_t *)vf_res, len);
367 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
368 struct i40e_pf_vf *vf,
369 struct virtchnl_rxq_info *rxq,
372 int err = I40E_SUCCESS;
373 struct i40e_hmc_obj_rxq rx_ctx;
374 uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
376 /* Clear the context structure first */
377 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
378 rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
379 rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
380 rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
381 rx_ctx.qlen = rxq->ring_len;
382 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
386 if (rxq->splithdr_enabled) {
387 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
388 rx_ctx.dtype = i40e_header_split_enabled;
390 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
391 rx_ctx.dtype = i40e_header_split_none;
393 rx_ctx.rxmax = rxq->max_pkt_size;
394 rx_ctx.tphrdesc_ena = 1;
395 rx_ctx.tphwdesc_ena = 1;
396 rx_ctx.tphdata_ena = 1;
397 rx_ctx.tphhead_ena = 1;
398 rx_ctx.lrxqthresh = 2;
399 rx_ctx.crcstrip = crcstrip;
403 err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
404 if (err != I40E_SUCCESS)
406 err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
411 static inline uint8_t
412 i40e_vsi_get_tc_of_queue(struct i40e_vsi *vsi,
415 struct i40e_aqc_vsi_properties_data *info = &vsi->info;
416 uint16_t bsf, qp_idx;
419 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
420 if (vsi->enabled_tc & (1 << i)) {
421 qp_idx = rte_le_to_cpu_16((info->tc_mapping[i] &
422 I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
423 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT);
424 bsf = rte_le_to_cpu_16((info->tc_mapping[i] &
425 I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
426 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
427 if (queue_id >= qp_idx && queue_id < qp_idx + (1 << bsf))
435 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
436 struct i40e_pf_vf *vf,
437 struct virtchnl_txq_info *txq)
439 int err = I40E_SUCCESS;
440 struct i40e_hmc_obj_txq tx_ctx;
441 struct i40e_vsi *vsi = vf->vsi;
443 uint16_t abs_queue_id = vsi->base_queue + txq->queue_id;
446 /* clear the context structure first */
447 memset(&tx_ctx, 0, sizeof(tx_ctx));
448 tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
449 tx_ctx.qlen = txq->ring_len;
450 dcb_tc = i40e_vsi_get_tc_of_queue(vsi, txq->queue_id);
451 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[dcb_tc]);
452 tx_ctx.head_wb_ena = txq->headwb_enabled;
453 tx_ctx.head_wb_addr = txq->dma_headwb_addr;
455 err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
456 if (err != I40E_SUCCESS)
459 err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
460 if (err != I40E_SUCCESS)
463 /* bind queue with VF function, since TX/QX will appear in pair,
464 * so only has QTX_CTL to set.
466 qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
467 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
468 I40E_QTX_CTL_PF_INDX_MASK) |
469 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
470 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
471 I40E_QTX_CTL_VFVM_INDX_MASK);
472 I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
473 I40E_WRITE_FLUSH(hw);
479 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
484 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
485 struct i40e_vsi *vsi = vf->vsi;
486 struct virtchnl_vsi_queue_config_info *vc_vqci =
487 (struct virtchnl_vsi_queue_config_info *)msg;
488 struct virtchnl_queue_pair_info *vc_qpi;
489 int i, ret = I40E_SUCCESS;
492 i40e_pf_host_send_msg_to_vf(vf,
493 VIRTCHNL_OP_CONFIG_VSI_QUEUES,
494 I40E_NOT_SUPPORTED, NULL, 0);
498 if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
499 vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
500 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
501 vc_vqci->num_queue_pairs)) {
502 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong");
503 ret = I40E_ERR_PARAM;
507 vc_qpi = vc_vqci->qpair;
508 for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
509 if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
510 vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
511 ret = I40E_ERR_PARAM;
516 * Apply VF RX queue setting to HMC.
517 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
518 * then the extra information of
519 * 'struct virtchnl_queue_pair_extra_info' is needed,
520 * otherwise set the last parameter to NULL.
522 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
523 I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
524 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
525 ret = I40E_ERR_PARAM;
529 /* Apply VF TX queue setting to HMC */
530 if (i40e_pf_host_hmc_config_txq(hw, vf,
531 &vc_qpi[i].txq) != I40E_SUCCESS) {
532 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
533 ret = I40E_ERR_PARAM;
539 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
546 i40e_pf_config_irq_link_list(struct i40e_pf_vf *vf,
547 struct virtchnl_vector_map *vvm)
549 #define BITS_PER_CHAR 8
550 uint64_t linklistmap = 0, tempmap;
551 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
553 bool b_first_q = true;
554 enum i40e_queue_type qtype;
556 uint32_t reg, reg_idx;
557 uint16_t itr_idx = 0, i;
559 vector_id = vvm->vector_id;
562 reg_idx = I40E_VPINT_LNKLST0(vf->vf_idx);
564 reg_idx = I40E_VPINT_LNKLSTN(
565 ((hw->func_caps.num_msix_vectors_vf - 1) * vf->vf_idx)
568 if (vvm->rxq_map == 0 && vvm->txq_map == 0) {
569 I40E_WRITE_REG(hw, reg_idx,
570 I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
574 /* sort all rx and tx queues */
575 tempmap = vvm->rxq_map;
576 for (i = 0; i < sizeof(vvm->rxq_map) * BITS_PER_CHAR; i++) {
578 linklistmap |= (1 << (2 * i));
582 tempmap = vvm->txq_map;
583 for (i = 0; i < sizeof(vvm->txq_map) * BITS_PER_CHAR; i++) {
585 linklistmap |= (1 << (2 * i + 1));
589 /* Link all rx and tx queues into a chained list */
590 tempmap = linklistmap;
595 qtype = (enum i40e_queue_type)(i % 2);
596 qid = vf->vsi->base_queue + i / 2;
601 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
604 /* element in the link list */
606 (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
607 (qid << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
608 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
609 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
611 I40E_WRITE_REG(hw, reg_idx, reg);
612 /* find next register to program */
614 case I40E_QUEUE_TYPE_RX:
615 reg_idx = I40E_QINT_RQCTL(qid);
616 itr_idx = vvm->rxitr_idx;
618 case I40E_QUEUE_TYPE_TX:
619 reg_idx = I40E_QINT_TQCTL(qid);
620 itr_idx = vvm->txitr_idx;
630 /* Terminate the link list */
632 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
633 (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
634 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
635 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
636 I40E_WRITE_REG(hw, reg_idx, reg);
639 I40E_WRITE_FLUSH(hw);
643 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
644 uint8_t *msg, uint16_t msglen,
647 int ret = I40E_SUCCESS;
648 struct i40e_pf *pf = vf->pf;
649 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
650 struct virtchnl_irq_map_info *irqmap =
651 (struct virtchnl_irq_map_info *)msg;
652 struct virtchnl_vector_map *map;
654 uint16_t vector_id, itr_idx;
655 unsigned long qbit_max;
658 i40e_pf_host_send_msg_to_vf(
660 VIRTCHNL_OP_CONFIG_IRQ_MAP,
661 I40E_NOT_SUPPORTED, NULL, 0);
665 if (msg == NULL || msglen < sizeof(struct virtchnl_irq_map_info)) {
666 PMD_DRV_LOG(ERR, "buffer too short");
667 ret = I40E_ERR_PARAM;
671 /* PF host will support both DPDK VF or Linux VF driver, identify by
672 * number of vectors requested.
675 /* DPDK VF only requires single vector */
676 if (irqmap->num_vectors == 1) {
677 /* This MSIX intr store the intr in VF range */
678 vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
679 vf->vsi->nb_msix = irqmap->num_vectors;
680 vf->vsi->nb_used_qps = vf->vsi->nb_qps;
681 itr_idx = irqmap->vecmap[0].rxitr_idx;
683 /* Don't care how the TX/RX queue mapping with this vector.
684 * Link all VF RX queues together. Only did mapping work.
685 * VF can disable/enable the intr by itself.
687 i40e_vsi_queues_bind_intr(vf->vsi, itr_idx);
691 /* Then, it's Linux VF driver */
692 qbit_max = 1 << pf->vf_nb_qp_max;
693 for (i = 0; i < irqmap->num_vectors; i++) {
694 map = &irqmap->vecmap[i];
696 vector_id = map->vector_id;
697 /* validate msg params */
698 if (vector_id >= hw->func_caps.num_msix_vectors_vf) {
699 ret = I40E_ERR_PARAM;
703 if ((map->rxq_map < qbit_max) && (map->txq_map < qbit_max)) {
704 i40e_pf_config_irq_link_list(vf, map);
706 /* configured queue size excceed limit */
707 ret = I40E_ERR_PARAM;
713 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_IRQ_MAP,
720 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
721 struct virtchnl_queue_select *qsel,
724 int ret = I40E_SUCCESS;
726 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
727 uint16_t baseq = vf->vsi->base_queue;
729 if (qsel->rx_queues + qsel->tx_queues == 0)
730 return I40E_ERR_PARAM;
732 /* always enable RX first and disable last */
733 /* Enable RX if it's enable */
735 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
736 if (qsel->rx_queues & (1 << i)) {
737 ret = i40e_switch_rx_queue(hw, baseq + i, on);
738 if (ret != I40E_SUCCESS)
743 /* Enable/Disable TX */
744 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
745 if (qsel->tx_queues & (1 << i)) {
746 ret = i40e_switch_tx_queue(hw, baseq + i, on);
747 if (ret != I40E_SUCCESS)
751 /* disable RX last if it's disable */
754 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
755 if (qsel->rx_queues & (1 << i)) {
756 ret = i40e_switch_rx_queue(hw, baseq + i, on);
757 if (ret != I40E_SUCCESS)
766 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
770 int ret = I40E_SUCCESS;
771 struct virtchnl_queue_select *q_sel =
772 (struct virtchnl_queue_select *)msg;
774 if (msg == NULL || msglen != sizeof(*q_sel)) {
775 ret = I40E_ERR_PARAM;
778 ret = i40e_pf_host_switch_queues(vf, q_sel, true);
781 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_QUEUES,
788 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
793 int ret = I40E_SUCCESS;
794 struct virtchnl_queue_select *q_sel =
795 (struct virtchnl_queue_select *)msg;
798 i40e_pf_host_send_msg_to_vf(
800 VIRTCHNL_OP_DISABLE_QUEUES,
801 I40E_NOT_SUPPORTED, NULL, 0);
805 if (msg == NULL || msglen != sizeof(*q_sel)) {
806 ret = I40E_ERR_PARAM;
809 ret = i40e_pf_host_switch_queues(vf, q_sel, false);
812 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_QUEUES,
820 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
825 int ret = I40E_SUCCESS;
826 struct virtchnl_ether_addr_list *addr_list =
827 (struct virtchnl_ether_addr_list *)msg;
828 struct i40e_mac_filter_info filter;
830 struct rte_ether_addr *mac;
833 i40e_pf_host_send_msg_to_vf(
835 VIRTCHNL_OP_ADD_ETH_ADDR,
836 I40E_NOT_SUPPORTED, NULL, 0);
840 memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
842 if (msg == NULL || msglen <= sizeof(*addr_list)) {
843 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
844 ret = I40E_ERR_PARAM;
848 for (i = 0; i < addr_list->num_elements; i++) {
849 mac = (struct rte_ether_addr *)(addr_list->list[i].addr);
850 rte_memcpy(&filter.mac_addr, mac, RTE_ETHER_ADDR_LEN);
851 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
852 if (rte_is_zero_ether_addr(mac) ||
853 i40e_vsi_add_mac(vf->vsi, &filter)) {
854 ret = I40E_ERR_INVALID_MAC_ADDR;
860 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_ETH_ADDR,
867 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
872 int ret = I40E_SUCCESS;
873 struct virtchnl_ether_addr_list *addr_list =
874 (struct virtchnl_ether_addr_list *)msg;
876 struct rte_ether_addr *mac;
879 i40e_pf_host_send_msg_to_vf(
881 VIRTCHNL_OP_DEL_ETH_ADDR,
882 I40E_NOT_SUPPORTED, NULL, 0);
886 if (msg == NULL || msglen <= sizeof(*addr_list)) {
887 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
888 ret = I40E_ERR_PARAM;
892 for (i = 0; i < addr_list->num_elements; i++) {
893 mac = (struct rte_ether_addr *)(addr_list->list[i].addr);
894 if (rte_is_zero_ether_addr(mac) ||
895 i40e_vsi_delete_mac(vf->vsi, mac)) {
896 ret = I40E_ERR_INVALID_MAC_ADDR;
902 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_ETH_ADDR,
909 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
910 uint8_t *msg, uint16_t msglen,
913 int ret = I40E_SUCCESS;
914 struct virtchnl_vlan_filter_list *vlan_filter_list =
915 (struct virtchnl_vlan_filter_list *)msg;
920 i40e_pf_host_send_msg_to_vf(
922 VIRTCHNL_OP_ADD_VLAN,
923 I40E_NOT_SUPPORTED, NULL, 0);
927 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
928 PMD_DRV_LOG(ERR, "add_vlan argument too short");
929 ret = I40E_ERR_PARAM;
933 vid = vlan_filter_list->vlan_id;
935 for (i = 0; i < vlan_filter_list->num_elements; i++) {
936 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
937 if(ret != I40E_SUCCESS)
942 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_VLAN,
949 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
954 int ret = I40E_SUCCESS;
955 struct virtchnl_vlan_filter_list *vlan_filter_list =
956 (struct virtchnl_vlan_filter_list *)msg;
961 i40e_pf_host_send_msg_to_vf(
963 VIRTCHNL_OP_DEL_VLAN,
964 I40E_NOT_SUPPORTED, NULL, 0);
968 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
969 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
970 ret = I40E_ERR_PARAM;
974 vid = vlan_filter_list->vlan_id;
975 for (i = 0; i < vlan_filter_list->num_elements; i++) {
976 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
977 if(ret != I40E_SUCCESS)
982 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_VLAN,
989 i40e_pf_host_process_cmd_config_promisc_mode(
990 struct i40e_pf_vf *vf,
995 int ret = I40E_SUCCESS;
996 struct virtchnl_promisc_info *promisc =
997 (struct virtchnl_promisc_info *)msg;
998 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
999 bool unicast = FALSE, multicast = FALSE;
1002 i40e_pf_host_send_msg_to_vf(
1004 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
1005 I40E_NOT_SUPPORTED, NULL, 0);
1009 if (msg == NULL || msglen != sizeof(*promisc)) {
1010 ret = I40E_ERR_PARAM;
1014 if (promisc->flags & FLAG_VF_UNICAST_PROMISC)
1016 ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
1017 vf->vsi->seid, unicast, NULL, true);
1018 if (ret != I40E_SUCCESS)
1021 if (promisc->flags & FLAG_VF_MULTICAST_PROMISC)
1023 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
1027 i40e_pf_host_send_msg_to_vf(vf,
1028 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
1034 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf, bool b_op)
1036 i40e_update_vsi_stats(vf->vsi);
1039 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1041 (uint8_t *)&vf->vsi->eth_stats,
1042 sizeof(vf->vsi->eth_stats));
1044 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1046 (uint8_t *)&vf->vsi->eth_stats,
1047 sizeof(vf->vsi->eth_stats));
1049 return I40E_SUCCESS;
1053 i40e_pf_host_process_cmd_enable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1055 int ret = I40E_SUCCESS;
1058 i40e_pf_host_send_msg_to_vf(
1060 VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1061 I40E_NOT_SUPPORTED, NULL, 0);
1065 ret = i40e_vsi_config_vlan_stripping(vf->vsi, TRUE);
1067 PMD_DRV_LOG(ERR, "Failed to enable vlan stripping");
1069 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1076 i40e_pf_host_process_cmd_disable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1078 int ret = I40E_SUCCESS;
1081 i40e_pf_host_send_msg_to_vf(
1083 VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1084 I40E_NOT_SUPPORTED, NULL, 0);
1088 ret = i40e_vsi_config_vlan_stripping(vf->vsi, FALSE);
1090 PMD_DRV_LOG(ERR, "Failed to disable vlan stripping");
1092 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1099 i40e_pf_host_process_cmd_set_rss_lut(struct i40e_pf_vf *vf,
1104 struct virtchnl_rss_lut *rss_lut = (struct virtchnl_rss_lut *)msg;
1106 int ret = I40E_SUCCESS;
1109 i40e_pf_host_send_msg_to_vf(
1111 VIRTCHNL_OP_CONFIG_RSS_LUT,
1112 I40E_NOT_SUPPORTED, NULL, 0);
1116 if (!msg || msglen <= sizeof(struct virtchnl_rss_lut)) {
1117 PMD_DRV_LOG(ERR, "set_rss_lut argument too short");
1118 ret = I40E_ERR_PARAM;
1121 valid_len = sizeof(struct virtchnl_rss_lut) + rss_lut->lut_entries - 1;
1122 if (msglen < valid_len) {
1123 PMD_DRV_LOG(ERR, "set_rss_lut length mismatch");
1124 ret = I40E_ERR_PARAM;
1128 ret = i40e_set_rss_lut(vf->vsi, rss_lut->lut, rss_lut->lut_entries);
1131 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_LUT,
1138 i40e_pf_host_process_cmd_set_rss_key(struct i40e_pf_vf *vf,
1143 struct virtchnl_rss_key *rss_key = (struct virtchnl_rss_key *)msg;
1145 int ret = I40E_SUCCESS;
1148 i40e_pf_host_send_msg_to_vf(
1150 VIRTCHNL_OP_DEL_VLAN,
1151 VIRTCHNL_OP_CONFIG_RSS_KEY, NULL, 0);
1155 if (!msg || msglen <= sizeof(struct virtchnl_rss_key)) {
1156 PMD_DRV_LOG(ERR, "set_rss_key argument too short");
1157 ret = I40E_ERR_PARAM;
1160 valid_len = sizeof(struct virtchnl_rss_key) + rss_key->key_len - 1;
1161 if (msglen < valid_len) {
1162 PMD_DRV_LOG(ERR, "set_rss_key length mismatch");
1163 ret = I40E_ERR_PARAM;
1167 ret = i40e_set_rss_key(vf->vsi, rss_key->key, rss_key->key_len);
1170 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_KEY,
1177 i40e_notify_vf_link_status(struct rte_eth_dev *dev, struct i40e_pf_vf *vf)
1179 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1180 struct virtchnl_pf_event event;
1181 uint16_t vf_id = vf->vf_idx;
1182 uint32_t tval, rval;
1184 event.event = VIRTCHNL_EVENT_LINK_CHANGE;
1185 event.event_data.link_event.link_status =
1186 dev->data->dev_link.link_status;
1188 /* need to convert the ETH_SPEED_xxx into VIRTCHNL_LINK_SPEED_xxx */
1189 switch (dev->data->dev_link.link_speed) {
1190 case ETH_SPEED_NUM_100M:
1191 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_100MB;
1193 case ETH_SPEED_NUM_1G:
1194 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_1GB;
1196 case ETH_SPEED_NUM_10G:
1197 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_10GB;
1199 case ETH_SPEED_NUM_20G:
1200 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_20GB;
1202 case ETH_SPEED_NUM_25G:
1203 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_25GB;
1205 case ETH_SPEED_NUM_40G:
1206 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_40GB;
1209 event.event_data.link_event.link_speed =
1210 VIRTCHNL_LINK_SPEED_UNKNOWN;
1214 tval = I40E_READ_REG(hw, I40E_VF_ATQLEN(vf_id));
1215 rval = I40E_READ_REG(hw, I40E_VF_ARQLEN(vf_id));
1217 if (tval & I40E_VF_ATQLEN_ATQLEN_MASK ||
1218 tval & I40E_VF_ATQLEN_ATQENABLE_MASK ||
1219 rval & I40E_VF_ARQLEN_ARQLEN_MASK ||
1220 rval & I40E_VF_ARQLEN_ARQENABLE_MASK)
1221 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_EVENT,
1222 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
1226 * i40e_vc_notify_vf_reset
1227 * @vf: pointer to the VF structure
1229 * indicate a pending reset to the given VF
1232 i40e_vc_notify_vf_reset(struct i40e_pf_vf *vf)
1234 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1235 struct virtchnl_pf_event pfe;
1237 uint16_t vf_id = vf->vf_idx;
1239 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
1240 pfe.event = VIRTCHNL_EVENT_RESET_IMPENDING;
1241 pfe.severity = PF_EVENT_SEVERITY_CERTAIN_DOOM;
1242 i40e_aq_send_msg_to_vf(hw, abs_vf_id, VIRTCHNL_OP_EVENT, 0, (u8 *)&pfe,
1243 sizeof(struct virtchnl_pf_event), NULL);
1247 i40e_pf_host_process_cmd_request_queues(struct i40e_pf_vf *vf, uint8_t *msg)
1249 struct virtchnl_vf_res_request *vfres =
1250 (struct virtchnl_vf_res_request *)msg;
1252 uint32_t req_pairs = vfres->num_queue_pairs;
1253 uint32_t cur_pairs = vf->vsi->nb_used_qps;
1257 if (!rte_is_power_of_2(req_pairs))
1258 req_pairs = i40e_align_floor(req_pairs) << 1;
1260 if (req_pairs == 0) {
1261 PMD_DRV_LOG(ERR, "VF %d tried to request 0 queues. Ignoring.\n",
1263 } else if (req_pairs > I40E_MAX_QP_NUM_PER_VF) {
1265 "VF %d tried to request more than %d queues.\n",
1267 I40E_MAX_QP_NUM_PER_VF);
1268 vfres->num_queue_pairs = I40E_MAX_QP_NUM_PER_VF;
1269 } else if (req_pairs > cur_pairs + pf->qp_pool.num_free) {
1270 PMD_DRV_LOG(ERR, "VF %d requested %d queues (rounded to %d) "
1271 "but only %d available\n",
1273 vfres->num_queue_pairs,
1275 cur_pairs + pf->qp_pool.num_free);
1276 vfres->num_queue_pairs = i40e_align_floor(pf->qp_pool.num_free +
1279 i40e_vc_notify_vf_reset(vf);
1280 vf->vsi->nb_qps = req_pairs;
1281 pf->vf_nb_qps = req_pairs;
1282 i40e_pf_host_process_cmd_reset_vf(vf);
1287 return i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_REQUEST_QUEUES, 0,
1288 (u8 *)vfres, sizeof(*vfres));
1292 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
1293 uint16_t abs_vf_id, uint32_t opcode,
1294 __rte_unused uint32_t retval,
1298 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1299 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300 struct i40e_pf_vf *vf;
1301 /* AdminQ will pass absolute VF id, transfer to internal vf id */
1302 uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
1303 struct rte_pmd_i40e_mb_event_param ret_param;
1304 uint64_t first_cycle, cur_cycle;
1308 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1309 PMD_DRV_LOG(ERR, "invalid argument");
1313 vf = &pf->vfs[vf_id];
1315 cur_cycle = rte_get_timer_cycles();
1317 /* if the VF being blocked, ignore the message and return */
1318 if (cur_cycle < vf->ignore_end_cycle)
1322 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
1323 i40e_pf_host_send_msg_to_vf(vf, opcode,
1324 I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
1328 /* perform basic checks on the msg */
1329 ret = virtchnl_vc_validate_vf_msg(&vf->version, opcode, msg, msglen);
1331 /* perform additional checks specific to this driver */
1332 if (opcode == VIRTCHNL_OP_CONFIG_RSS_KEY) {
1333 struct virtchnl_rss_key *vrk = (struct virtchnl_rss_key *)msg;
1335 if (vrk->key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4))
1336 ret = VIRTCHNL_ERR_PARAM;
1337 } else if (opcode == VIRTCHNL_OP_CONFIG_RSS_LUT) {
1338 struct virtchnl_rss_lut *vrl = (struct virtchnl_rss_lut *)msg;
1340 if (vrl->lut_entries != ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4))
1341 ret = VIRTCHNL_ERR_PARAM;
1345 PMD_DRV_LOG(ERR, "Invalid message from VF %u, opcode %u, len %u",
1346 vf_id, opcode, msglen);
1347 i40e_pf_host_send_msg_to_vf(vf, opcode,
1348 I40E_ERR_PARAM, NULL, 0);
1353 * initialise structure to send to user application
1354 * will return response from user in retval field
1356 ret_param.retval = RTE_PMD_I40E_MB_EVENT_PROCEED;
1357 ret_param.vfid = vf_id;
1358 ret_param.msg_type = opcode;
1359 ret_param.msg = (void *)msg;
1360 ret_param.msglen = msglen;
1363 * Ask user application if we're allowed to perform those functions.
1364 * If we get ret_param.retval == RTE_PMD_I40E_MB_EVENT_PROCEED,
1365 * then business as usual.
1366 * If RTE_PMD_I40E_MB_EVENT_NOOP_ACK or RTE_PMD_I40E_MB_EVENT_NOOP_NACK,
1367 * do nothing and send not_supported to VF. As PF must send a response
1368 * to VF and ACK/NACK is not defined.
1370 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &ret_param);
1371 if (ret_param.retval != RTE_PMD_I40E_MB_EVENT_PROCEED) {
1372 PMD_DRV_LOG(WARNING, "VF to PF message(%d) is not permitted!",
1378 case VIRTCHNL_OP_VERSION:
1379 PMD_DRV_LOG(INFO, "OP_VERSION received");
1380 i40e_pf_host_process_cmd_version(vf, msg, b_op);
1382 case VIRTCHNL_OP_RESET_VF:
1383 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
1384 i40e_pf_host_process_cmd_reset_vf(vf);
1386 case VIRTCHNL_OP_GET_VF_RESOURCES:
1387 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
1388 i40e_pf_host_process_cmd_get_vf_resource(vf, msg, b_op);
1390 case VIRTCHNL_OP_CONFIG_VSI_QUEUES:
1391 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
1392 i40e_pf_host_process_cmd_config_vsi_queues(vf, msg,
1395 case VIRTCHNL_OP_CONFIG_IRQ_MAP:
1396 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
1397 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen, b_op);
1399 case VIRTCHNL_OP_ENABLE_QUEUES:
1400 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
1402 i40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);
1403 i40e_notify_vf_link_status(dev, vf);
1405 i40e_pf_host_send_msg_to_vf(
1406 vf, VIRTCHNL_OP_ENABLE_QUEUES,
1407 I40E_NOT_SUPPORTED, NULL, 0);
1410 case VIRTCHNL_OP_DISABLE_QUEUES:
1411 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
1412 i40e_pf_host_process_cmd_disable_queues(vf, msg, msglen, b_op);
1414 case VIRTCHNL_OP_ADD_ETH_ADDR:
1415 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
1416 i40e_pf_host_process_cmd_add_ether_address(vf, msg,
1419 case VIRTCHNL_OP_DEL_ETH_ADDR:
1420 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
1421 i40e_pf_host_process_cmd_del_ether_address(vf, msg,
1424 case VIRTCHNL_OP_ADD_VLAN:
1425 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
1426 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen, b_op);
1428 case VIRTCHNL_OP_DEL_VLAN:
1429 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
1430 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen, b_op);
1432 case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
1433 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
1434 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg,
1437 case VIRTCHNL_OP_GET_STATS:
1438 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
1439 i40e_pf_host_process_cmd_get_stats(vf, b_op);
1441 case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING:
1442 PMD_DRV_LOG(INFO, "OP_ENABLE_VLAN_STRIPPING received");
1443 i40e_pf_host_process_cmd_enable_vlan_strip(vf, b_op);
1445 case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING:
1446 PMD_DRV_LOG(INFO, "OP_DISABLE_VLAN_STRIPPING received");
1447 i40e_pf_host_process_cmd_disable_vlan_strip(vf, b_op);
1449 case VIRTCHNL_OP_CONFIG_RSS_LUT:
1450 PMD_DRV_LOG(INFO, "OP_CONFIG_RSS_LUT received");
1451 i40e_pf_host_process_cmd_set_rss_lut(vf, msg, msglen, b_op);
1453 case VIRTCHNL_OP_CONFIG_RSS_KEY:
1454 PMD_DRV_LOG(INFO, "OP_CONFIG_RSS_KEY received");
1455 i40e_pf_host_process_cmd_set_rss_key(vf, msg, msglen, b_op);
1457 case VIRTCHNL_OP_REQUEST_QUEUES:
1458 PMD_DRV_LOG(INFO, "OP_REQUEST_QUEUES received");
1459 i40e_pf_host_process_cmd_request_queues(vf, msg);
1462 /* Don't add command supported below, which will
1463 * return an error code.
1466 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
1467 i40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,
1473 /* if message validation not enabled */
1474 if (!pf->vf_msg_cfg.max_msg)
1477 /* store current cycle */
1478 vf->msg_timestamps[vf->msg_index++] = cur_cycle;
1479 vf->msg_index %= pf->vf_msg_cfg.max_msg;
1481 /* read the timestamp of earliest message */
1482 first_cycle = vf->msg_timestamps[vf->msg_index];
1485 * If the time span from the arrival time of first message to
1486 * the arrival time of current message smaller than `period`,
1487 * that mean too much message in this statistic period.
1489 if (first_cycle && cur_cycle < first_cycle +
1490 (uint64_t)pf->vf_msg_cfg.period * rte_get_timer_hz()) {
1491 PMD_DRV_LOG(WARNING, "VF %u too much messages(%u in %u"
1492 " seconds),\n\tany new message from which"
1493 " will be ignored during next %u seconds!",
1494 vf_id, pf->vf_msg_cfg.max_msg,
1495 (uint32_t)((cur_cycle - first_cycle +
1496 rte_get_timer_hz() - 1) / rte_get_timer_hz()),
1497 pf->vf_msg_cfg.ignore_second);
1498 vf->ignore_end_cycle = rte_get_timer_cycles() +
1499 pf->vf_msg_cfg.ignore_second *
1505 i40e_pf_host_init(struct rte_eth_dev *dev)
1507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1508 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1513 PMD_INIT_FUNC_TRACE();
1516 * return if SRIOV not enabled, VF number not configured or
1517 * no queue assigned.
1519 if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
1520 return I40E_SUCCESS;
1522 /* Allocate memory to store VF structure */
1523 pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
1527 /* Disable irq0 for VFR event */
1528 i40e_pf_disable_irq0(hw);
1530 /* Disable VF link status interrupt */
1531 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1532 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1533 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1534 I40E_WRITE_FLUSH(hw);
1536 /* calculate the memory size for storing timestamp of messages */
1537 size = pf->vf_msg_cfg.max_msg * sizeof(uint64_t);
1539 for (i = 0; i < pf->vf_num; i++) {
1541 pf->vfs[i].state = I40E_VF_INACTIVE;
1542 pf->vfs[i].vf_idx = i;
1545 /* allocate memory for store timestamp of messages */
1546 pf->vfs[i].msg_timestamps =
1547 rte_zmalloc("i40e_pf_vf", size, 0);
1548 if (pf->vfs[i].msg_timestamps == NULL) {
1554 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
1555 if (ret != I40E_SUCCESS)
1559 RTE_ETH_DEV_SRIOV(dev).active = pf->vf_num;
1561 i40e_pf_enable_irq0(hw);
1563 return I40E_SUCCESS;
1567 rte_free(pf->vfs[i].msg_timestamps);
1569 i40e_pf_enable_irq0(hw);
1575 i40e_pf_host_uninit(struct rte_eth_dev *dev)
1577 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1582 PMD_INIT_FUNC_TRACE();
1585 * return if SRIOV not enabled, VF number not configured or
1586 * no queue assigned.
1588 if ((!hw->func_caps.sr_iov_1_1) ||
1589 (pf->vf_num == 0) ||
1590 (pf->vf_nb_qps == 0))
1591 return I40E_SUCCESS;
1593 /* free memory for store timestamp of messages */
1594 for (i = 0; i < pf->vf_num; i++)
1595 rte_free(pf->vfs[i].msg_timestamps);
1597 /* free memory to store VF structure */
1601 /* Disable irq0 for VFR event */
1602 i40e_pf_disable_irq0(hw);
1604 /* Disable VF link status interrupt */
1605 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1606 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1607 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1608 I40E_WRITE_FLUSH(hw);
1610 return I40E_SUCCESS;