4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
51 #include "i40e_logs.h"
52 #include "base/i40e_prototype.h"
53 #include "base/i40e_adminq_cmd.h"
54 #include "base/i40e_type.h"
55 #include "i40e_ethdev.h"
56 #include "i40e_rxtx.h"
58 #include "rte_pmd_i40e.h"
60 #define I40E_CFG_CRCSTRIP_DEFAULT 1
63 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
64 struct virtchnl_queue_select *qsel,
68 * Bind PF queues with VSI and VF.
71 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
74 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
75 uint16_t vsi_id = vf->vsi->vsi_id;
76 uint16_t vf_id = vf->vf_idx;
77 uint16_t nb_qps = vf->vsi->nb_qps;
78 uint16_t qbase = vf->vsi->base_queue;
83 * VF should use scatter range queues. So, it needn't
84 * to set QBASE in this register.
86 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
87 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
89 /* Set to enable VFLAN_QTABLE[] registers valid */
90 I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
91 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
93 /* map PF queues to VF */
94 for (i = 0; i < nb_qps; i++) {
95 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
96 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
99 /* map PF queues to VSI */
100 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
101 if (2 * i > nb_qps - 1)
102 q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
106 if (2 * i + 1 > nb_qps - 1)
107 q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
109 q2 = qbase + 2 * i + 1;
111 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
112 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
114 I40E_WRITE_FLUSH(hw);
121 * Proceed VF reset operation.
124 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
129 uint16_t vf_id, abs_vf_id, vf_msix_num;
131 struct virtchnl_queue_select qsel;
137 hw = I40E_PF_TO_HW(vf->pf);
139 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
141 /* Notify VF that we are in VFR progress */
142 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_INPROGRESS);
145 * If require a SW VF reset, a VFLR interrupt will be generated,
146 * this function will be called again. To avoid it,
147 * disable interrupt first.
150 vf->state = I40E_VF_INRESET;
151 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
152 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
153 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
154 I40E_WRITE_FLUSH(hw);
157 #define VFRESET_MAX_WAIT_CNT 100
158 /* Wait until VF reset is done */
159 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
161 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
162 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
166 if (i >= VFRESET_MAX_WAIT_CNT) {
167 PMD_DRV_LOG(ERR, "VF reset timeout");
170 /* This is not first time to do reset, do cleanup job first */
173 memset(&qsel, 0, sizeof(qsel));
174 for (i = 0; i < vf->vsi->nb_qps; i++)
175 qsel.rx_queues |= 1 << i;
176 qsel.tx_queues = qsel.rx_queues;
177 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
178 if (ret != I40E_SUCCESS) {
179 PMD_DRV_LOG(ERR, "Disable VF queues failed");
183 /* Disable VF interrupt setting */
184 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
185 for (i = 0; i < vf_msix_num; i++) {
187 val = I40E_VFINT_DYN_CTL0(vf_id);
189 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
191 I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
193 I40E_WRITE_FLUSH(hw);
196 ret = i40e_vsi_release(vf->vsi);
197 if (ret != I40E_SUCCESS) {
198 PMD_DRV_LOG(ERR, "Release VSI failed");
203 #define I40E_VF_PCI_ADDR 0xAA
204 #define I40E_VF_PEND_MASK 0x20
205 /* Check the pending transactions of this VF */
206 /* Use absolute VF id, refer to datasheet for details */
207 I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
208 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
209 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
211 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
212 if ((val & I40E_VF_PEND_MASK) == 0)
216 if (i >= VFRESET_MAX_WAIT_CNT) {
217 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
221 /* Reset done, Set COMPLETE flag and clear reset bit */
222 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_COMPLETED);
223 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
224 val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
225 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
227 I40E_WRITE_FLUSH(hw);
229 /* Allocate resource again */
230 if (pf->floating_veb && pf->floating_veb_list[vf_id]) {
231 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
234 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
235 vf->pf->main_vsi, vf->vf_idx);
238 if (vf->vsi == NULL) {
239 PMD_DRV_LOG(ERR, "Add vsi failed");
243 ret = i40e_pf_vf_queues_mapping(vf);
244 if (ret != I40E_SUCCESS) {
245 PMD_DRV_LOG(ERR, "queue mapping error");
246 i40e_vsi_release(vf->vsi);
250 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_VFACTIVE);
256 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
262 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
263 uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
266 ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
269 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
270 hw->aq.asq_last_status);
277 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf, bool b_op)
279 struct virtchnl_version_info info;
281 /* Respond like a Linux PF host in order to support both DPDK VF and
282 * Linux VF driver. The expense is original DPDK host specific feature
283 * like CFG_VLAN_PVID and CONFIG_VSI_QUEUES_EXT will not available.
285 * DPDK VF also can't identify host driver by version number returned.
286 * It always assume talking with Linux PF.
288 info.major = VIRTCHNL_VERSION_MAJOR;
289 info.minor = VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
292 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
297 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
304 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
306 i40e_pf_host_vf_reset(vf, 1);
308 /* No feedback will be sent to VF for VFLR */
313 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf, bool b_op)
315 struct virtchnl_vf_resource *vf_res = NULL;
316 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
318 int ret = I40E_SUCCESS;
321 i40e_pf_host_send_msg_to_vf(vf,
322 VIRTCHNL_OP_GET_VF_RESOURCES,
323 I40E_NOT_SUPPORTED, NULL, 0);
327 /* only have 1 VSI by default */
328 len = sizeof(struct virtchnl_vf_resource) +
329 I40E_DEFAULT_VF_VSI_NUM *
330 sizeof(struct virtchnl_vsi_resource);
332 vf_res = rte_zmalloc("i40e_vf_res", len, 0);
333 if (vf_res == NULL) {
334 PMD_DRV_LOG(ERR, "failed to allocate mem");
335 ret = I40E_ERR_NO_MEMORY;
341 vf_res->vf_offload_flags = VIRTCHNL_VF_OFFLOAD_L2 |
342 VIRTCHNL_VF_OFFLOAD_VLAN;
343 vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
344 vf_res->num_queue_pairs = vf->vsi->nb_qps;
345 vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
347 /* Change below setting if PF host can support more VSIs for VF */
348 vf_res->vsi_res[0].vsi_type = VIRTCHNL_VSI_SRIOV;
349 vf_res->vsi_res[0].vsi_id = vf->vsi->vsi_id;
350 vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
351 ether_addr_copy(&vf->mac_addr,
352 (struct ether_addr *)vf_res->vsi_res[0].default_mac_addr);
355 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_VF_RESOURCES,
356 ret, (uint8_t *)vf_res, len);
363 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
364 struct i40e_pf_vf *vf,
365 struct virtchnl_rxq_info *rxq,
368 int err = I40E_SUCCESS;
369 struct i40e_hmc_obj_rxq rx_ctx;
370 uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
372 /* Clear the context structure first */
373 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
374 rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
375 rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
376 rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
377 rx_ctx.qlen = rxq->ring_len;
378 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
382 if (rxq->splithdr_enabled) {
383 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
384 rx_ctx.dtype = i40e_header_split_enabled;
386 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
387 rx_ctx.dtype = i40e_header_split_none;
389 rx_ctx.rxmax = rxq->max_pkt_size;
390 rx_ctx.tphrdesc_ena = 1;
391 rx_ctx.tphwdesc_ena = 1;
392 rx_ctx.tphdata_ena = 1;
393 rx_ctx.tphhead_ena = 1;
394 rx_ctx.lrxqthresh = 2;
395 rx_ctx.crcstrip = crcstrip;
399 err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
400 if (err != I40E_SUCCESS)
402 err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
407 static inline uint8_t
408 i40e_vsi_get_tc_of_queue(struct i40e_vsi *vsi,
411 struct i40e_aqc_vsi_properties_data *info = &vsi->info;
412 uint16_t bsf, qp_idx;
415 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
416 if (vsi->enabled_tc & (1 << i)) {
417 qp_idx = rte_le_to_cpu_16((info->tc_mapping[i] &
418 I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
419 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT);
420 bsf = rte_le_to_cpu_16((info->tc_mapping[i] &
421 I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
422 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
423 if (queue_id >= qp_idx && queue_id < qp_idx + (1 << bsf))
431 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
432 struct i40e_pf_vf *vf,
433 struct virtchnl_txq_info *txq)
435 int err = I40E_SUCCESS;
436 struct i40e_hmc_obj_txq tx_ctx;
437 struct i40e_vsi *vsi = vf->vsi;
439 uint16_t abs_queue_id = vsi->base_queue + txq->queue_id;
442 /* clear the context structure first */
443 memset(&tx_ctx, 0, sizeof(tx_ctx));
444 tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
445 tx_ctx.qlen = txq->ring_len;
446 dcb_tc = i40e_vsi_get_tc_of_queue(vsi, txq->queue_id);
447 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[dcb_tc]);
448 tx_ctx.head_wb_ena = txq->headwb_enabled;
449 tx_ctx.head_wb_addr = txq->dma_headwb_addr;
451 err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
452 if (err != I40E_SUCCESS)
455 err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
456 if (err != I40E_SUCCESS)
459 /* bind queue with VF function, since TX/QX will appear in pair,
460 * so only has QTX_CTL to set.
462 qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
463 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
464 I40E_QTX_CTL_PF_INDX_MASK) |
465 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
466 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
467 I40E_QTX_CTL_VFVM_INDX_MASK);
468 I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
469 I40E_WRITE_FLUSH(hw);
475 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
480 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
481 struct i40e_vsi *vsi = vf->vsi;
482 struct virtchnl_vsi_queue_config_info *vc_vqci =
483 (struct virtchnl_vsi_queue_config_info *)msg;
484 struct virtchnl_queue_pair_info *vc_qpi;
485 int i, ret = I40E_SUCCESS;
488 i40e_pf_host_send_msg_to_vf(vf,
489 VIRTCHNL_OP_CONFIG_VSI_QUEUES,
490 I40E_NOT_SUPPORTED, NULL, 0);
494 if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
495 vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
496 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
497 vc_vqci->num_queue_pairs)) {
498 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong");
499 ret = I40E_ERR_PARAM;
503 vc_qpi = vc_vqci->qpair;
504 for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
505 if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
506 vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
507 ret = I40E_ERR_PARAM;
512 * Apply VF RX queue setting to HMC.
513 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
514 * then the extra information of
515 * 'struct virtchnl_queue_pair_extra_info' is needed,
516 * otherwise set the last parameter to NULL.
518 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
519 I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
520 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
521 ret = I40E_ERR_PARAM;
525 /* Apply VF TX queue setting to HMC */
526 if (i40e_pf_host_hmc_config_txq(hw, vf,
527 &vc_qpi[i].txq) != I40E_SUCCESS) {
528 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
529 ret = I40E_ERR_PARAM;
535 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
542 i40e_pf_host_process_cmd_config_vsi_queues_ext(struct i40e_pf_vf *vf,
547 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
548 struct i40e_vsi *vsi = vf->vsi;
549 struct virtchnl_vsi_queue_config_ext_info *vc_vqcei =
550 (struct virtchnl_vsi_queue_config_ext_info *)msg;
551 struct virtchnl_queue_pair_ext_info *vc_qpei;
552 int i, ret = I40E_SUCCESS;
555 i40e_pf_host_send_msg_to_vf(
557 VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
558 I40E_NOT_SUPPORTED, NULL, 0);
562 if (!msg || vc_vqcei->num_queue_pairs > vsi->nb_qps ||
563 vc_vqcei->num_queue_pairs > I40E_MAX_VSI_QP ||
564 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei,
565 vc_vqcei->num_queue_pairs)) {
566 PMD_DRV_LOG(ERR, "vsi_queue_config_ext_info argument wrong");
567 ret = I40E_ERR_PARAM;
571 vc_qpei = vc_vqcei->qpair;
572 for (i = 0; i < vc_vqcei->num_queue_pairs; i++) {
573 if (vc_qpei[i].rxq.queue_id > vsi->nb_qps - 1 ||
574 vc_qpei[i].txq.queue_id > vsi->nb_qps - 1) {
575 ret = I40E_ERR_PARAM;
579 * Apply VF RX queue setting to HMC.
580 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
581 * then the extra information of
582 * 'struct virtchnl_queue_pair_ext_info' is needed,
583 * otherwise set the last parameter to NULL.
585 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpei[i].rxq,
586 vc_qpei[i].rxq_ext.crcstrip) != I40E_SUCCESS) {
587 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
588 ret = I40E_ERR_PARAM;
592 /* Apply VF TX queue setting to HMC */
593 if (i40e_pf_host_hmc_config_txq(hw, vf, &vc_qpei[i].txq) !=
595 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
596 ret = I40E_ERR_PARAM;
602 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
609 i40e_pf_config_irq_link_list(struct i40e_pf_vf *vf,
610 struct virtchnl_vector_map *vvm)
612 #define BITS_PER_CHAR 8
613 uint64_t linklistmap = 0, tempmap;
614 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
616 bool b_first_q = true;
617 enum i40e_queue_type qtype;
619 uint32_t reg, reg_idx;
620 uint16_t itr_idx = 0, i;
622 vector_id = vvm->vector_id;
625 reg_idx = I40E_VPINT_LNKLST0(vf->vf_idx);
627 reg_idx = I40E_VPINT_LNKLSTN(
628 ((hw->func_caps.num_msix_vectors_vf - 1) * vf->vf_idx)
631 if (vvm->rxq_map == 0 && vvm->txq_map == 0) {
632 I40E_WRITE_REG(hw, reg_idx,
633 I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
637 /* sort all rx and tx queues */
638 tempmap = vvm->rxq_map;
639 for (i = 0; i < sizeof(vvm->rxq_map) * BITS_PER_CHAR; i++) {
641 linklistmap |= (1 << (2 * i));
645 tempmap = vvm->txq_map;
646 for (i = 0; i < sizeof(vvm->txq_map) * BITS_PER_CHAR; i++) {
648 linklistmap |= (1 << (2 * i + 1));
652 /* Link all rx and tx queues into a chained list */
653 tempmap = linklistmap;
658 qtype = (enum i40e_queue_type)(i % 2);
659 qid = vf->vsi->base_queue + i / 2;
664 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
667 /* element in the link list */
669 (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
670 (qid << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
671 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
672 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
674 I40E_WRITE_REG(hw, reg_idx, reg);
675 /* find next register to program */
677 case I40E_QUEUE_TYPE_RX:
678 reg_idx = I40E_QINT_RQCTL(qid);
679 itr_idx = vvm->rxitr_idx;
681 case I40E_QUEUE_TYPE_TX:
682 reg_idx = I40E_QINT_TQCTL(qid);
683 itr_idx = vvm->txitr_idx;
693 /* Terminate the link list */
695 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
696 (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
697 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
698 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
699 I40E_WRITE_REG(hw, reg_idx, reg);
702 I40E_WRITE_FLUSH(hw);
706 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
707 uint8_t *msg, uint16_t msglen,
710 int ret = I40E_SUCCESS;
711 struct i40e_pf *pf = vf->pf;
712 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
713 struct virtchnl_irq_map_info *irqmap =
714 (struct virtchnl_irq_map_info *)msg;
715 struct virtchnl_vector_map *map;
718 unsigned long qbit_max;
721 i40e_pf_host_send_msg_to_vf(
723 VIRTCHNL_OP_CONFIG_IRQ_MAP,
724 I40E_NOT_SUPPORTED, NULL, 0);
728 if (msg == NULL || msglen < sizeof(struct virtchnl_irq_map_info)) {
729 PMD_DRV_LOG(ERR, "buffer too short");
730 ret = I40E_ERR_PARAM;
734 /* PF host will support both DPDK VF or Linux VF driver, identify by
735 * number of vectors requested.
738 /* DPDK VF only requires single vector */
739 if (irqmap->num_vectors == 1) {
740 /* This MSIX intr store the intr in VF range */
741 vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
742 vf->vsi->nb_msix = irqmap->num_vectors;
743 vf->vsi->nb_used_qps = vf->vsi->nb_qps;
745 /* Don't care how the TX/RX queue mapping with this vector.
746 * Link all VF RX queues together. Only did mapping work.
747 * VF can disable/enable the intr by itself.
749 i40e_vsi_queues_bind_intr(vf->vsi);
753 /* Then, it's Linux VF driver */
754 qbit_max = 1 << pf->vf_nb_qp_max;
755 for (i = 0; i < irqmap->num_vectors; i++) {
756 map = &irqmap->vecmap[i];
758 vector_id = map->vector_id;
759 /* validate msg params */
760 if (vector_id >= hw->func_caps.num_msix_vectors_vf) {
761 ret = I40E_ERR_PARAM;
765 if ((map->rxq_map < qbit_max) && (map->txq_map < qbit_max)) {
766 i40e_pf_config_irq_link_list(vf, map);
768 /* configured queue size excceed limit */
769 ret = I40E_ERR_PARAM;
775 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_IRQ_MAP,
782 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
783 struct virtchnl_queue_select *qsel,
786 int ret = I40E_SUCCESS;
788 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
789 uint16_t baseq = vf->vsi->base_queue;
791 if (qsel->rx_queues + qsel->tx_queues == 0)
792 return I40E_ERR_PARAM;
794 /* always enable RX first and disable last */
795 /* Enable RX if it's enable */
797 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
798 if (qsel->rx_queues & (1 << i)) {
799 ret = i40e_switch_rx_queue(hw, baseq + i, on);
800 if (ret != I40E_SUCCESS)
805 /* Enable/Disable TX */
806 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
807 if (qsel->tx_queues & (1 << i)) {
808 ret = i40e_switch_tx_queue(hw, baseq + i, on);
809 if (ret != I40E_SUCCESS)
813 /* disable RX last if it's disable */
816 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
817 if (qsel->rx_queues & (1 << i)) {
818 ret = i40e_switch_rx_queue(hw, baseq + i, on);
819 if (ret != I40E_SUCCESS)
828 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
832 int ret = I40E_SUCCESS;
833 struct virtchnl_queue_select *q_sel =
834 (struct virtchnl_queue_select *)msg;
836 if (msg == NULL || msglen != sizeof(*q_sel)) {
837 ret = I40E_ERR_PARAM;
840 ret = i40e_pf_host_switch_queues(vf, q_sel, true);
843 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_QUEUES,
850 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
855 int ret = I40E_SUCCESS;
856 struct virtchnl_queue_select *q_sel =
857 (struct virtchnl_queue_select *)msg;
860 i40e_pf_host_send_msg_to_vf(
862 VIRTCHNL_OP_DISABLE_QUEUES,
863 I40E_NOT_SUPPORTED, NULL, 0);
867 if (msg == NULL || msglen != sizeof(*q_sel)) {
868 ret = I40E_ERR_PARAM;
871 ret = i40e_pf_host_switch_queues(vf, q_sel, false);
874 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_QUEUES,
882 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
887 int ret = I40E_SUCCESS;
888 struct virtchnl_ether_addr_list *addr_list =
889 (struct virtchnl_ether_addr_list *)msg;
890 struct i40e_mac_filter_info filter;
892 struct ether_addr *mac;
895 i40e_pf_host_send_msg_to_vf(
897 VIRTCHNL_OP_ADD_ETH_ADDR,
898 I40E_NOT_SUPPORTED, NULL, 0);
902 memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
904 if (msg == NULL || msglen <= sizeof(*addr_list)) {
905 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
906 ret = I40E_ERR_PARAM;
910 for (i = 0; i < addr_list->num_elements; i++) {
911 mac = (struct ether_addr *)(addr_list->list[i].addr);
912 (void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
913 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
914 if (is_zero_ether_addr(mac) ||
915 i40e_vsi_add_mac(vf->vsi, &filter)) {
916 ret = I40E_ERR_INVALID_MAC_ADDR;
922 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_ETH_ADDR,
929 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
934 int ret = I40E_SUCCESS;
935 struct virtchnl_ether_addr_list *addr_list =
936 (struct virtchnl_ether_addr_list *)msg;
938 struct ether_addr *mac;
941 i40e_pf_host_send_msg_to_vf(
943 VIRTCHNL_OP_DEL_ETH_ADDR,
944 I40E_NOT_SUPPORTED, NULL, 0);
948 if (msg == NULL || msglen <= sizeof(*addr_list)) {
949 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
950 ret = I40E_ERR_PARAM;
954 for (i = 0; i < addr_list->num_elements; i++) {
955 mac = (struct ether_addr *)(addr_list->list[i].addr);
956 if(is_zero_ether_addr(mac) ||
957 i40e_vsi_delete_mac(vf->vsi, mac)) {
958 ret = I40E_ERR_INVALID_MAC_ADDR;
964 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_ETH_ADDR,
971 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
972 uint8_t *msg, uint16_t msglen,
975 int ret = I40E_SUCCESS;
976 struct virtchnl_vlan_filter_list *vlan_filter_list =
977 (struct virtchnl_vlan_filter_list *)msg;
982 i40e_pf_host_send_msg_to_vf(
984 VIRTCHNL_OP_ADD_VLAN,
985 I40E_NOT_SUPPORTED, NULL, 0);
989 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
990 PMD_DRV_LOG(ERR, "add_vlan argument too short");
991 ret = I40E_ERR_PARAM;
995 vid = vlan_filter_list->vlan_id;
997 for (i = 0; i < vlan_filter_list->num_elements; i++) {
998 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
999 if(ret != I40E_SUCCESS)
1004 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_VLAN,
1011 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
1016 int ret = I40E_SUCCESS;
1017 struct virtchnl_vlan_filter_list *vlan_filter_list =
1018 (struct virtchnl_vlan_filter_list *)msg;
1023 i40e_pf_host_send_msg_to_vf(
1025 VIRTCHNL_OP_DEL_VLAN,
1026 I40E_NOT_SUPPORTED, NULL, 0);
1030 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
1031 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
1032 ret = I40E_ERR_PARAM;
1036 vid = vlan_filter_list->vlan_id;
1037 for (i = 0; i < vlan_filter_list->num_elements; i++) {
1038 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
1039 if(ret != I40E_SUCCESS)
1044 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_VLAN,
1051 i40e_pf_host_process_cmd_config_promisc_mode(
1052 struct i40e_pf_vf *vf,
1057 int ret = I40E_SUCCESS;
1058 struct virtchnl_promisc_info *promisc =
1059 (struct virtchnl_promisc_info *)msg;
1060 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1061 bool unicast = FALSE, multicast = FALSE;
1064 i40e_pf_host_send_msg_to_vf(
1066 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
1067 I40E_NOT_SUPPORTED, NULL, 0);
1071 if (msg == NULL || msglen != sizeof(*promisc)) {
1072 ret = I40E_ERR_PARAM;
1076 if (promisc->flags & FLAG_VF_UNICAST_PROMISC)
1078 ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
1079 vf->vsi->seid, unicast, NULL, true);
1080 if (ret != I40E_SUCCESS)
1083 if (promisc->flags & FLAG_VF_MULTICAST_PROMISC)
1085 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
1089 i40e_pf_host_send_msg_to_vf(vf,
1090 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
1096 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf, bool b_op)
1098 i40e_update_vsi_stats(vf->vsi);
1101 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1103 (uint8_t *)&vf->vsi->eth_stats,
1104 sizeof(vf->vsi->eth_stats));
1106 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1108 (uint8_t *)&vf->vsi->eth_stats,
1109 sizeof(vf->vsi->eth_stats));
1111 return I40E_SUCCESS;
1115 i40e_pf_host_process_cmd_enable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1117 int ret = I40E_SUCCESS;
1120 i40e_pf_host_send_msg_to_vf(
1122 VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1123 I40E_NOT_SUPPORTED, NULL, 0);
1127 ret = i40e_vsi_config_vlan_stripping(vf->vsi, TRUE);
1129 PMD_DRV_LOG(ERR, "Failed to enable vlan stripping");
1131 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1138 i40e_pf_host_process_cmd_disable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1140 int ret = I40E_SUCCESS;
1143 i40e_pf_host_send_msg_to_vf(
1145 VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1146 I40E_NOT_SUPPORTED, NULL, 0);
1150 ret = i40e_vsi_config_vlan_stripping(vf->vsi, FALSE);
1152 PMD_DRV_LOG(ERR, "Failed to disable vlan stripping");
1154 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1161 i40e_notify_vf_link_status(struct rte_eth_dev *dev, struct i40e_pf_vf *vf)
1163 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1164 struct virtchnl_pf_event event;
1165 uint16_t vf_id = vf->vf_idx;
1166 uint32_t tval, rval;
1168 event.event = VIRTCHNL_EVENT_LINK_CHANGE;
1169 event.event_data.link_event.link_status =
1170 dev->data->dev_link.link_status;
1172 /* need to convert the ETH_SPEED_xxx into VIRTCHNL_LINK_SPEED_xxx */
1173 switch (dev->data->dev_link.link_speed) {
1174 case ETH_SPEED_NUM_100M:
1175 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_100MB;
1177 case ETH_SPEED_NUM_1G:
1178 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_1GB;
1180 case ETH_SPEED_NUM_10G:
1181 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_10GB;
1183 case ETH_SPEED_NUM_20G:
1184 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_20GB;
1186 case ETH_SPEED_NUM_25G:
1187 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_25GB;
1189 case ETH_SPEED_NUM_40G:
1190 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_40GB;
1193 event.event_data.link_event.link_speed =
1194 VIRTCHNL_LINK_SPEED_UNKNOWN;
1198 tval = I40E_READ_REG(hw, I40E_VF_ATQLEN(vf_id));
1199 rval = I40E_READ_REG(hw, I40E_VF_ARQLEN(vf_id));
1201 if (tval & I40E_VF_ATQLEN_ATQLEN_MASK ||
1202 tval & I40E_VF_ATQLEN_ATQENABLE_MASK ||
1203 rval & I40E_VF_ARQLEN_ARQLEN_MASK ||
1204 rval & I40E_VF_ARQLEN_ARQENABLE_MASK)
1205 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_EVENT,
1206 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
1210 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
1211 uint16_t abs_vf_id, uint32_t opcode,
1212 __rte_unused uint32_t retval,
1216 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1217 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218 struct i40e_pf_vf *vf;
1219 /* AdminQ will pass absolute VF id, transfer to internal vf id */
1220 uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
1221 struct rte_pmd_i40e_mb_event_param ret_param;
1224 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1225 PMD_DRV_LOG(ERR, "invalid argument");
1229 vf = &pf->vfs[vf_id];
1231 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
1232 i40e_pf_host_send_msg_to_vf(vf, opcode,
1233 I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
1238 * initialise structure to send to user application
1239 * will return response from user in retval field
1241 ret_param.retval = RTE_PMD_I40E_MB_EVENT_PROCEED;
1242 ret_param.vfid = vf_id;
1243 ret_param.msg_type = opcode;
1244 ret_param.msg = (void *)msg;
1245 ret_param.msglen = msglen;
1248 * Ask user application if we're allowed to perform those functions.
1249 * If we get ret_param.retval == RTE_PMD_I40E_MB_EVENT_PROCEED,
1250 * then business as usual.
1251 * If RTE_PMD_I40E_MB_EVENT_NOOP_ACK or RTE_PMD_I40E_MB_EVENT_NOOP_NACK,
1252 * do nothing and send not_supported to VF. As PF must send a response
1253 * to VF and ACK/NACK is not defined.
1255 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
1257 if (ret_param.retval != RTE_PMD_I40E_MB_EVENT_PROCEED) {
1258 PMD_DRV_LOG(WARNING, "VF to PF message(%d) is not permitted!",
1264 case VIRTCHNL_OP_VERSION:
1265 PMD_DRV_LOG(INFO, "OP_VERSION received");
1266 i40e_pf_host_process_cmd_version(vf, b_op);
1268 case VIRTCHNL_OP_RESET_VF:
1269 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
1270 i40e_pf_host_process_cmd_reset_vf(vf);
1272 case VIRTCHNL_OP_GET_VF_RESOURCES:
1273 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
1274 i40e_pf_host_process_cmd_get_vf_resource(vf, b_op);
1276 case VIRTCHNL_OP_CONFIG_VSI_QUEUES:
1277 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
1278 i40e_pf_host_process_cmd_config_vsi_queues(vf, msg,
1281 case VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT:
1282 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES_EXT received");
1283 i40e_pf_host_process_cmd_config_vsi_queues_ext(vf, msg,
1286 case VIRTCHNL_OP_CONFIG_IRQ_MAP:
1287 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
1288 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen, b_op);
1290 case VIRTCHNL_OP_ENABLE_QUEUES:
1291 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
1293 i40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);
1294 i40e_notify_vf_link_status(dev, vf);
1296 i40e_pf_host_send_msg_to_vf(
1297 vf, VIRTCHNL_OP_ENABLE_QUEUES,
1298 I40E_NOT_SUPPORTED, NULL, 0);
1301 case VIRTCHNL_OP_DISABLE_QUEUES:
1302 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
1303 i40e_pf_host_process_cmd_disable_queues(vf, msg, msglen, b_op);
1305 case VIRTCHNL_OP_ADD_ETH_ADDR:
1306 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
1307 i40e_pf_host_process_cmd_add_ether_address(vf, msg,
1310 case VIRTCHNL_OP_DEL_ETH_ADDR:
1311 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
1312 i40e_pf_host_process_cmd_del_ether_address(vf, msg,
1315 case VIRTCHNL_OP_ADD_VLAN:
1316 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
1317 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen, b_op);
1319 case VIRTCHNL_OP_DEL_VLAN:
1320 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
1321 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen, b_op);
1323 case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
1324 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
1325 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg,
1328 case VIRTCHNL_OP_GET_STATS:
1329 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
1330 i40e_pf_host_process_cmd_get_stats(vf, b_op);
1332 case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING:
1333 PMD_DRV_LOG(INFO, "OP_ENABLE_VLAN_STRIPPING received");
1334 i40e_pf_host_process_cmd_enable_vlan_strip(vf, b_op);
1336 case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING:
1337 PMD_DRV_LOG(INFO, "OP_DISABLE_VLAN_STRIPPING received");
1338 i40e_pf_host_process_cmd_disable_vlan_strip(vf, b_op);
1340 /* Don't add command supported below, which will
1341 * return an error code.
1344 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
1345 i40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,
1352 i40e_pf_host_init(struct rte_eth_dev *dev)
1354 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1355 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1359 PMD_INIT_FUNC_TRACE();
1362 * return if SRIOV not enabled, VF number not configured or
1363 * no queue assigned.
1365 if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
1366 return I40E_SUCCESS;
1368 /* Allocate memory to store VF structure */
1369 pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
1373 /* Disable irq0 for VFR event */
1374 i40e_pf_disable_irq0(hw);
1376 /* Disable VF link status interrupt */
1377 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1378 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1379 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1380 I40E_WRITE_FLUSH(hw);
1382 for (i = 0; i < pf->vf_num; i++) {
1384 pf->vfs[i].state = I40E_VF_INACTIVE;
1385 pf->vfs[i].vf_idx = i;
1386 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
1387 if (ret != I40E_SUCCESS)
1391 RTE_ETH_DEV_SRIOV(dev).active = pf->vf_num;
1393 i40e_pf_enable_irq0(hw);
1395 return I40E_SUCCESS;
1399 i40e_pf_enable_irq0(hw);
1405 i40e_pf_host_uninit(struct rte_eth_dev *dev)
1407 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1408 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1411 PMD_INIT_FUNC_TRACE();
1414 * return if SRIOV not enabled, VF number not configured or
1415 * no queue assigned.
1417 if ((!hw->func_caps.sr_iov_1_1) ||
1418 (pf->vf_num == 0) ||
1419 (pf->vf_nb_qps == 0))
1420 return I40E_SUCCESS;
1422 /* free memory to store VF structure */
1426 /* Disable irq0 for VFR event */
1427 i40e_pf_disable_irq0(hw);
1429 /* Disable VF link status interrupt */
1430 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1431 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1432 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1433 I40E_WRITE_FLUSH(hw);
1435 return I40E_SUCCESS;