4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
51 #include "i40e_logs.h"
52 #include "base/i40e_prototype.h"
53 #include "base/i40e_adminq_cmd.h"
54 #include "base/i40e_type.h"
55 #include "i40e_ethdev.h"
56 #include "i40e_rxtx.h"
58 #include "rte_pmd_i40e.h"
60 #define I40E_CFG_CRCSTRIP_DEFAULT 1
63 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
64 struct virtchnl_queue_select *qsel,
68 * Bind PF queues with VSI and VF.
71 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
74 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
75 uint16_t vsi_id = vf->vsi->vsi_id;
76 uint16_t vf_id = vf->vf_idx;
77 uint16_t nb_qps = vf->vsi->nb_qps;
78 uint16_t qbase = vf->vsi->base_queue;
83 * VF should use scatter range queues. So, it needn't
84 * to set QBASE in this register.
86 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
87 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
89 /* Set to enable VFLAN_QTABLE[] registers valid */
90 I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
91 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
93 /* map PF queues to VF */
94 for (i = 0; i < nb_qps; i++) {
95 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
96 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
99 /* map PF queues to VSI */
100 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
101 if (2 * i > nb_qps - 1)
102 q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
106 if (2 * i + 1 > nb_qps - 1)
107 q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
109 q2 = qbase + 2 * i + 1;
111 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
112 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
114 I40E_WRITE_FLUSH(hw);
121 * Proceed VF reset operation.
124 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
129 uint16_t vf_id, abs_vf_id, vf_msix_num;
131 struct virtchnl_queue_select qsel;
137 hw = I40E_PF_TO_HW(vf->pf);
139 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
141 /* Notify VF that we are in VFR progress */
142 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_INPROGRESS);
145 * If require a SW VF reset, a VFLR interrupt will be generated,
146 * this function will be called again. To avoid it,
147 * disable interrupt first.
150 vf->state = I40E_VF_INRESET;
151 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
152 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
153 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
154 I40E_WRITE_FLUSH(hw);
157 #define VFRESET_MAX_WAIT_CNT 100
158 /* Wait until VF reset is done */
159 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
161 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
162 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
166 if (i >= VFRESET_MAX_WAIT_CNT) {
167 PMD_DRV_LOG(ERR, "VF reset timeout");
171 /* This is not first time to do reset, do cleanup job first */
174 memset(&qsel, 0, sizeof(qsel));
175 for (i = 0; i < vf->vsi->nb_qps; i++)
176 qsel.rx_queues |= 1 << i;
177 qsel.tx_queues = qsel.rx_queues;
178 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
179 if (ret != I40E_SUCCESS) {
180 PMD_DRV_LOG(ERR, "Disable VF queues failed");
184 /* Disable VF interrupt setting */
185 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
186 for (i = 0; i < vf_msix_num; i++) {
188 val = I40E_VFINT_DYN_CTL0(vf_id);
190 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
192 I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
194 I40E_WRITE_FLUSH(hw);
197 ret = i40e_vsi_release(vf->vsi);
198 if (ret != I40E_SUCCESS) {
199 PMD_DRV_LOG(ERR, "Release VSI failed");
204 #define I40E_VF_PCI_ADDR 0xAA
205 #define I40E_VF_PEND_MASK 0x20
206 /* Check the pending transactions of this VF */
207 /* Use absolute VF id, refer to datasheet for details */
208 I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
209 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
210 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
212 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
213 if ((val & I40E_VF_PEND_MASK) == 0)
217 if (i >= VFRESET_MAX_WAIT_CNT) {
218 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
222 /* Reset done, Set COMPLETE flag and clear reset bit */
223 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_COMPLETED);
224 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
225 val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
226 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
228 I40E_WRITE_FLUSH(hw);
230 /* Allocate resource again */
231 if (pf->floating_veb && pf->floating_veb_list[vf_id]) {
232 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
235 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
236 vf->pf->main_vsi, vf->vf_idx);
239 if (vf->vsi == NULL) {
240 PMD_DRV_LOG(ERR, "Add vsi failed");
244 ret = i40e_pf_vf_queues_mapping(vf);
245 if (ret != I40E_SUCCESS) {
246 PMD_DRV_LOG(ERR, "queue mapping error");
247 i40e_vsi_release(vf->vsi);
251 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_VFACTIVE);
257 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
263 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
264 uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
267 ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
270 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
271 hw->aq.asq_last_status);
278 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf, bool b_op)
280 struct virtchnl_version_info info;
282 /* Respond like a Linux PF host in order to support both DPDK VF and
283 * Linux VF driver. The expense is original DPDK host specific feature
284 * like CFG_VLAN_PVID and CONFIG_VSI_QUEUES_EXT will not available.
286 * DPDK VF also can't identify host driver by version number returned.
287 * It always assume talking with Linux PF.
289 info.major = VIRTCHNL_VERSION_MAJOR;
290 info.minor = VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
293 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
298 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
305 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
307 i40e_pf_host_vf_reset(vf, 1);
309 /* No feedback will be sent to VF for VFLR */
314 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf, bool b_op)
316 struct virtchnl_vf_resource *vf_res = NULL;
317 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
319 int ret = I40E_SUCCESS;
322 i40e_pf_host_send_msg_to_vf(vf,
323 VIRTCHNL_OP_GET_VF_RESOURCES,
324 I40E_NOT_SUPPORTED, NULL, 0);
328 /* only have 1 VSI by default */
329 len = sizeof(struct virtchnl_vf_resource) +
330 I40E_DEFAULT_VF_VSI_NUM *
331 sizeof(struct virtchnl_vsi_resource);
333 vf_res = rte_zmalloc("i40e_vf_res", len, 0);
334 if (vf_res == NULL) {
335 PMD_DRV_LOG(ERR, "failed to allocate mem");
336 ret = I40E_ERR_NO_MEMORY;
342 vf_res->vf_offload_flags = VIRTCHNL_VF_OFFLOAD_L2 |
343 VIRTCHNL_VF_OFFLOAD_VLAN;
344 vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
345 vf_res->num_queue_pairs = vf->vsi->nb_qps;
346 vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
348 /* Change below setting if PF host can support more VSIs for VF */
349 vf_res->vsi_res[0].vsi_type = VIRTCHNL_VSI_SRIOV;
350 vf_res->vsi_res[0].vsi_id = vf->vsi->vsi_id;
351 vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
352 ether_addr_copy(&vf->mac_addr,
353 (struct ether_addr *)vf_res->vsi_res[0].default_mac_addr);
356 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_VF_RESOURCES,
357 ret, (uint8_t *)vf_res, len);
364 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
365 struct i40e_pf_vf *vf,
366 struct virtchnl_rxq_info *rxq,
369 int err = I40E_SUCCESS;
370 struct i40e_hmc_obj_rxq rx_ctx;
371 uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
373 /* Clear the context structure first */
374 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
375 rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
376 rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
377 rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
378 rx_ctx.qlen = rxq->ring_len;
379 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
383 if (rxq->splithdr_enabled) {
384 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
385 rx_ctx.dtype = i40e_header_split_enabled;
387 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
388 rx_ctx.dtype = i40e_header_split_none;
390 rx_ctx.rxmax = rxq->max_pkt_size;
391 rx_ctx.tphrdesc_ena = 1;
392 rx_ctx.tphwdesc_ena = 1;
393 rx_ctx.tphdata_ena = 1;
394 rx_ctx.tphhead_ena = 1;
395 rx_ctx.lrxqthresh = 2;
396 rx_ctx.crcstrip = crcstrip;
400 err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
401 if (err != I40E_SUCCESS)
403 err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
408 static inline uint8_t
409 i40e_vsi_get_tc_of_queue(struct i40e_vsi *vsi,
412 struct i40e_aqc_vsi_properties_data *info = &vsi->info;
413 uint16_t bsf, qp_idx;
416 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
417 if (vsi->enabled_tc & (1 << i)) {
418 qp_idx = rte_le_to_cpu_16((info->tc_mapping[i] &
419 I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
420 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT);
421 bsf = rte_le_to_cpu_16((info->tc_mapping[i] &
422 I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
423 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
424 if (queue_id >= qp_idx && queue_id < qp_idx + (1 << bsf))
432 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
433 struct i40e_pf_vf *vf,
434 struct virtchnl_txq_info *txq)
436 int err = I40E_SUCCESS;
437 struct i40e_hmc_obj_txq tx_ctx;
438 struct i40e_vsi *vsi = vf->vsi;
440 uint16_t abs_queue_id = vsi->base_queue + txq->queue_id;
443 /* clear the context structure first */
444 memset(&tx_ctx, 0, sizeof(tx_ctx));
445 tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
446 tx_ctx.qlen = txq->ring_len;
447 dcb_tc = i40e_vsi_get_tc_of_queue(vsi, txq->queue_id);
448 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[dcb_tc]);
449 tx_ctx.head_wb_ena = txq->headwb_enabled;
450 tx_ctx.head_wb_addr = txq->dma_headwb_addr;
452 err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
453 if (err != I40E_SUCCESS)
456 err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
457 if (err != I40E_SUCCESS)
460 /* bind queue with VF function, since TX/QX will appear in pair,
461 * so only has QTX_CTL to set.
463 qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
464 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
465 I40E_QTX_CTL_PF_INDX_MASK) |
466 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
467 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
468 I40E_QTX_CTL_VFVM_INDX_MASK);
469 I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
470 I40E_WRITE_FLUSH(hw);
476 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
481 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
482 struct i40e_vsi *vsi = vf->vsi;
483 struct virtchnl_vsi_queue_config_info *vc_vqci =
484 (struct virtchnl_vsi_queue_config_info *)msg;
485 struct virtchnl_queue_pair_info *vc_qpi;
486 int i, ret = I40E_SUCCESS;
489 i40e_pf_host_send_msg_to_vf(vf,
490 VIRTCHNL_OP_CONFIG_VSI_QUEUES,
491 I40E_NOT_SUPPORTED, NULL, 0);
495 if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
496 vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
497 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
498 vc_vqci->num_queue_pairs)) {
499 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong");
500 ret = I40E_ERR_PARAM;
504 vc_qpi = vc_vqci->qpair;
505 for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
506 if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
507 vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
508 ret = I40E_ERR_PARAM;
513 * Apply VF RX queue setting to HMC.
514 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
515 * then the extra information of
516 * 'struct virtchnl_queue_pair_extra_info' is needed,
517 * otherwise set the last parameter to NULL.
519 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
520 I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
521 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
522 ret = I40E_ERR_PARAM;
526 /* Apply VF TX queue setting to HMC */
527 if (i40e_pf_host_hmc_config_txq(hw, vf,
528 &vc_qpi[i].txq) != I40E_SUCCESS) {
529 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
530 ret = I40E_ERR_PARAM;
536 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
543 i40e_pf_host_process_cmd_config_vsi_queues_ext(struct i40e_pf_vf *vf,
548 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
549 struct i40e_vsi *vsi = vf->vsi;
550 struct virtchnl_vsi_queue_config_ext_info *vc_vqcei =
551 (struct virtchnl_vsi_queue_config_ext_info *)msg;
552 struct virtchnl_queue_pair_ext_info *vc_qpei;
553 int i, ret = I40E_SUCCESS;
556 i40e_pf_host_send_msg_to_vf(
558 VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
559 I40E_NOT_SUPPORTED, NULL, 0);
563 if (!msg || vc_vqcei->num_queue_pairs > vsi->nb_qps ||
564 vc_vqcei->num_queue_pairs > I40E_MAX_VSI_QP ||
565 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei,
566 vc_vqcei->num_queue_pairs)) {
567 PMD_DRV_LOG(ERR, "vsi_queue_config_ext_info argument wrong");
568 ret = I40E_ERR_PARAM;
572 vc_qpei = vc_vqcei->qpair;
573 for (i = 0; i < vc_vqcei->num_queue_pairs; i++) {
574 if (vc_qpei[i].rxq.queue_id > vsi->nb_qps - 1 ||
575 vc_qpei[i].txq.queue_id > vsi->nb_qps - 1) {
576 ret = I40E_ERR_PARAM;
580 * Apply VF RX queue setting to HMC.
581 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
582 * then the extra information of
583 * 'struct virtchnl_queue_pair_ext_info' is needed,
584 * otherwise set the last parameter to NULL.
586 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpei[i].rxq,
587 vc_qpei[i].rxq_ext.crcstrip) != I40E_SUCCESS) {
588 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
589 ret = I40E_ERR_PARAM;
593 /* Apply VF TX queue setting to HMC */
594 if (i40e_pf_host_hmc_config_txq(hw, vf, &vc_qpei[i].txq) !=
596 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
597 ret = I40E_ERR_PARAM;
603 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
610 i40e_pf_config_irq_link_list(struct i40e_pf_vf *vf,
611 struct virtchnl_vector_map *vvm)
613 #define BITS_PER_CHAR 8
614 uint64_t linklistmap = 0, tempmap;
615 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
617 bool b_first_q = true;
618 enum i40e_queue_type qtype;
620 uint32_t reg, reg_idx;
621 uint16_t itr_idx = 0, i;
623 vector_id = vvm->vector_id;
626 reg_idx = I40E_VPINT_LNKLST0(vf->vf_idx);
628 reg_idx = I40E_VPINT_LNKLSTN(
629 ((hw->func_caps.num_msix_vectors_vf - 1) * vf->vf_idx)
632 if (vvm->rxq_map == 0 && vvm->txq_map == 0) {
633 I40E_WRITE_REG(hw, reg_idx,
634 I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
638 /* sort all rx and tx queues */
639 tempmap = vvm->rxq_map;
640 for (i = 0; i < sizeof(vvm->rxq_map) * BITS_PER_CHAR; i++) {
642 linklistmap |= (1 << (2 * i));
646 tempmap = vvm->txq_map;
647 for (i = 0; i < sizeof(vvm->txq_map) * BITS_PER_CHAR; i++) {
649 linklistmap |= (1 << (2 * i + 1));
653 /* Link all rx and tx queues into a chained list */
654 tempmap = linklistmap;
659 qtype = (enum i40e_queue_type)(i % 2);
660 qid = vf->vsi->base_queue + i / 2;
665 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
668 /* element in the link list */
670 (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
671 (qid << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
672 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
673 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
675 I40E_WRITE_REG(hw, reg_idx, reg);
676 /* find next register to program */
678 case I40E_QUEUE_TYPE_RX:
679 reg_idx = I40E_QINT_RQCTL(qid);
680 itr_idx = vvm->rxitr_idx;
682 case I40E_QUEUE_TYPE_TX:
683 reg_idx = I40E_QINT_TQCTL(qid);
684 itr_idx = vvm->txitr_idx;
694 /* Terminate the link list */
696 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
697 (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
698 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
699 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
700 I40E_WRITE_REG(hw, reg_idx, reg);
703 I40E_WRITE_FLUSH(hw);
707 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
708 uint8_t *msg, uint16_t msglen,
711 int ret = I40E_SUCCESS;
712 struct i40e_pf *pf = vf->pf;
713 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
714 struct virtchnl_irq_map_info *irqmap =
715 (struct virtchnl_irq_map_info *)msg;
716 struct virtchnl_vector_map *map;
719 unsigned long qbit_max;
722 i40e_pf_host_send_msg_to_vf(
724 VIRTCHNL_OP_CONFIG_IRQ_MAP,
725 I40E_NOT_SUPPORTED, NULL, 0);
729 if (msg == NULL || msglen < sizeof(struct virtchnl_irq_map_info)) {
730 PMD_DRV_LOG(ERR, "buffer too short");
731 ret = I40E_ERR_PARAM;
735 /* PF host will support both DPDK VF or Linux VF driver, identify by
736 * number of vectors requested.
739 /* DPDK VF only requires single vector */
740 if (irqmap->num_vectors == 1) {
741 /* This MSIX intr store the intr in VF range */
742 vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
743 vf->vsi->nb_msix = irqmap->num_vectors;
744 vf->vsi->nb_used_qps = vf->vsi->nb_qps;
746 /* Don't care how the TX/RX queue mapping with this vector.
747 * Link all VF RX queues together. Only did mapping work.
748 * VF can disable/enable the intr by itself.
750 i40e_vsi_queues_bind_intr(vf->vsi);
754 /* Then, it's Linux VF driver */
755 qbit_max = 1 << pf->vf_nb_qp_max;
756 for (i = 0; i < irqmap->num_vectors; i++) {
757 map = &irqmap->vecmap[i];
759 vector_id = map->vector_id;
760 /* validate msg params */
761 if (vector_id >= hw->func_caps.num_msix_vectors_vf) {
762 ret = I40E_ERR_PARAM;
766 if ((map->rxq_map < qbit_max) && (map->txq_map < qbit_max)) {
767 i40e_pf_config_irq_link_list(vf, map);
769 /* configured queue size excceed limit */
770 ret = I40E_ERR_PARAM;
776 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_IRQ_MAP,
783 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
784 struct virtchnl_queue_select *qsel,
787 int ret = I40E_SUCCESS;
789 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
790 uint16_t baseq = vf->vsi->base_queue;
792 if (qsel->rx_queues + qsel->tx_queues == 0)
793 return I40E_ERR_PARAM;
795 /* always enable RX first and disable last */
796 /* Enable RX if it's enable */
798 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
799 if (qsel->rx_queues & (1 << i)) {
800 ret = i40e_switch_rx_queue(hw, baseq + i, on);
801 if (ret != I40E_SUCCESS)
806 /* Enable/Disable TX */
807 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
808 if (qsel->tx_queues & (1 << i)) {
809 ret = i40e_switch_tx_queue(hw, baseq + i, on);
810 if (ret != I40E_SUCCESS)
814 /* disable RX last if it's disable */
817 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
818 if (qsel->rx_queues & (1 << i)) {
819 ret = i40e_switch_rx_queue(hw, baseq + i, on);
820 if (ret != I40E_SUCCESS)
829 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
833 int ret = I40E_SUCCESS;
834 struct virtchnl_queue_select *q_sel =
835 (struct virtchnl_queue_select *)msg;
837 if (msg == NULL || msglen != sizeof(*q_sel)) {
838 ret = I40E_ERR_PARAM;
841 ret = i40e_pf_host_switch_queues(vf, q_sel, true);
844 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_QUEUES,
851 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
856 int ret = I40E_SUCCESS;
857 struct virtchnl_queue_select *q_sel =
858 (struct virtchnl_queue_select *)msg;
861 i40e_pf_host_send_msg_to_vf(
863 VIRTCHNL_OP_DISABLE_QUEUES,
864 I40E_NOT_SUPPORTED, NULL, 0);
868 if (msg == NULL || msglen != sizeof(*q_sel)) {
869 ret = I40E_ERR_PARAM;
872 ret = i40e_pf_host_switch_queues(vf, q_sel, false);
875 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_QUEUES,
883 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
888 int ret = I40E_SUCCESS;
889 struct virtchnl_ether_addr_list *addr_list =
890 (struct virtchnl_ether_addr_list *)msg;
891 struct i40e_mac_filter_info filter;
893 struct ether_addr *mac;
896 i40e_pf_host_send_msg_to_vf(
898 VIRTCHNL_OP_ADD_ETH_ADDR,
899 I40E_NOT_SUPPORTED, NULL, 0);
903 memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
905 if (msg == NULL || msglen <= sizeof(*addr_list)) {
906 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
907 ret = I40E_ERR_PARAM;
911 for (i = 0; i < addr_list->num_elements; i++) {
912 mac = (struct ether_addr *)(addr_list->list[i].addr);
913 (void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
914 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
915 if (is_zero_ether_addr(mac) ||
916 i40e_vsi_add_mac(vf->vsi, &filter)) {
917 ret = I40E_ERR_INVALID_MAC_ADDR;
923 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_ETH_ADDR,
930 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
935 int ret = I40E_SUCCESS;
936 struct virtchnl_ether_addr_list *addr_list =
937 (struct virtchnl_ether_addr_list *)msg;
939 struct ether_addr *mac;
942 i40e_pf_host_send_msg_to_vf(
944 VIRTCHNL_OP_DEL_ETH_ADDR,
945 I40E_NOT_SUPPORTED, NULL, 0);
949 if (msg == NULL || msglen <= sizeof(*addr_list)) {
950 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
951 ret = I40E_ERR_PARAM;
955 for (i = 0; i < addr_list->num_elements; i++) {
956 mac = (struct ether_addr *)(addr_list->list[i].addr);
957 if(is_zero_ether_addr(mac) ||
958 i40e_vsi_delete_mac(vf->vsi, mac)) {
959 ret = I40E_ERR_INVALID_MAC_ADDR;
965 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_ETH_ADDR,
972 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
973 uint8_t *msg, uint16_t msglen,
976 int ret = I40E_SUCCESS;
977 struct virtchnl_vlan_filter_list *vlan_filter_list =
978 (struct virtchnl_vlan_filter_list *)msg;
983 i40e_pf_host_send_msg_to_vf(
985 VIRTCHNL_OP_ADD_VLAN,
986 I40E_NOT_SUPPORTED, NULL, 0);
990 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
991 PMD_DRV_LOG(ERR, "add_vlan argument too short");
992 ret = I40E_ERR_PARAM;
996 vid = vlan_filter_list->vlan_id;
998 for (i = 0; i < vlan_filter_list->num_elements; i++) {
999 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
1000 if(ret != I40E_SUCCESS)
1005 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_VLAN,
1012 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
1017 int ret = I40E_SUCCESS;
1018 struct virtchnl_vlan_filter_list *vlan_filter_list =
1019 (struct virtchnl_vlan_filter_list *)msg;
1024 i40e_pf_host_send_msg_to_vf(
1026 VIRTCHNL_OP_DEL_VLAN,
1027 I40E_NOT_SUPPORTED, NULL, 0);
1031 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
1032 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
1033 ret = I40E_ERR_PARAM;
1037 vid = vlan_filter_list->vlan_id;
1038 for (i = 0; i < vlan_filter_list->num_elements; i++) {
1039 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
1040 if(ret != I40E_SUCCESS)
1045 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_VLAN,
1052 i40e_pf_host_process_cmd_config_promisc_mode(
1053 struct i40e_pf_vf *vf,
1058 int ret = I40E_SUCCESS;
1059 struct virtchnl_promisc_info *promisc =
1060 (struct virtchnl_promisc_info *)msg;
1061 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1062 bool unicast = FALSE, multicast = FALSE;
1065 i40e_pf_host_send_msg_to_vf(
1067 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
1068 I40E_NOT_SUPPORTED, NULL, 0);
1072 if (msg == NULL || msglen != sizeof(*promisc)) {
1073 ret = I40E_ERR_PARAM;
1077 if (promisc->flags & FLAG_VF_UNICAST_PROMISC)
1079 ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
1080 vf->vsi->seid, unicast, NULL, true);
1081 if (ret != I40E_SUCCESS)
1084 if (promisc->flags & FLAG_VF_MULTICAST_PROMISC)
1086 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
1090 i40e_pf_host_send_msg_to_vf(vf,
1091 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
1097 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf, bool b_op)
1099 i40e_update_vsi_stats(vf->vsi);
1102 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1104 (uint8_t *)&vf->vsi->eth_stats,
1105 sizeof(vf->vsi->eth_stats));
1107 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1109 (uint8_t *)&vf->vsi->eth_stats,
1110 sizeof(vf->vsi->eth_stats));
1112 return I40E_SUCCESS;
1116 i40e_pf_host_process_cmd_enable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1118 int ret = I40E_SUCCESS;
1121 i40e_pf_host_send_msg_to_vf(
1123 VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1124 I40E_NOT_SUPPORTED, NULL, 0);
1128 ret = i40e_vsi_config_vlan_stripping(vf->vsi, TRUE);
1130 PMD_DRV_LOG(ERR, "Failed to enable vlan stripping");
1132 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1139 i40e_pf_host_process_cmd_disable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1141 int ret = I40E_SUCCESS;
1144 i40e_pf_host_send_msg_to_vf(
1146 VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1147 I40E_NOT_SUPPORTED, NULL, 0);
1151 ret = i40e_vsi_config_vlan_stripping(vf->vsi, FALSE);
1153 PMD_DRV_LOG(ERR, "Failed to disable vlan stripping");
1155 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1162 i40e_pf_host_process_cmd_cfg_pvid(struct i40e_pf_vf *vf,
1167 int ret = I40E_SUCCESS;
1168 struct virtchnl_pvid_info *tpid_info =
1169 (struct virtchnl_pvid_info *)msg;
1172 i40e_pf_host_send_msg_to_vf(
1174 I40E_VIRTCHNL_OP_CFG_VLAN_PVID,
1175 I40E_NOT_SUPPORTED, NULL, 0);
1179 if (msg == NULL || msglen != sizeof(*tpid_info)) {
1180 ret = I40E_ERR_PARAM;
1184 ret = i40e_vsi_vlan_pvid_set(vf->vsi, &tpid_info->info);
1187 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_PVID,
1194 i40e_notify_vf_link_status(struct rte_eth_dev *dev, struct i40e_pf_vf *vf)
1196 struct virtchnl_pf_event event;
1198 event.event = VIRTCHNL_EVENT_LINK_CHANGE;
1199 event.event_data.link_event.link_status =
1200 dev->data->dev_link.link_status;
1202 /* need to convert the ETH_SPEED_xxx into VIRTCHNL_LINK_SPEED_xxx */
1203 switch (dev->data->dev_link.link_speed) {
1204 case ETH_SPEED_NUM_100M:
1205 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_100MB;
1207 case ETH_SPEED_NUM_1G:
1208 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_1GB;
1210 case ETH_SPEED_NUM_10G:
1211 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_10GB;
1213 case ETH_SPEED_NUM_20G:
1214 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_20GB;
1216 case ETH_SPEED_NUM_25G:
1217 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_25GB;
1219 case ETH_SPEED_NUM_40G:
1220 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_40GB;
1223 event.event_data.link_event.link_speed =
1224 VIRTCHNL_LINK_SPEED_UNKNOWN;
1228 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_EVENT,
1229 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
1233 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
1234 uint16_t abs_vf_id, uint32_t opcode,
1235 __rte_unused uint32_t retval,
1239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1241 struct i40e_pf_vf *vf;
1242 /* AdminQ will pass absolute VF id, transfer to internal vf id */
1243 uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
1244 struct rte_pmd_i40e_mb_event_param ret_param;
1247 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1248 PMD_DRV_LOG(ERR, "invalid argument");
1252 vf = &pf->vfs[vf_id];
1254 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
1255 i40e_pf_host_send_msg_to_vf(vf, opcode,
1256 I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
1261 * initialise structure to send to user application
1262 * will return response from user in retval field
1264 ret_param.retval = RTE_PMD_I40E_MB_EVENT_PROCEED;
1265 ret_param.vfid = vf_id;
1266 ret_param.msg_type = opcode;
1267 ret_param.msg = (void *)msg;
1268 ret_param.msglen = msglen;
1271 * Ask user application if we're allowed to perform those functions.
1272 * If we get ret_param.retval == RTE_PMD_I40E_MB_EVENT_PROCEED,
1273 * then business as usual.
1274 * If RTE_PMD_I40E_MB_EVENT_NOOP_ACK or RTE_PMD_I40E_MB_EVENT_NOOP_NACK,
1275 * do nothing and send not_supported to VF. As PF must send a response
1276 * to VF and ACK/NACK is not defined.
1278 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
1280 if (ret_param.retval != RTE_PMD_I40E_MB_EVENT_PROCEED) {
1281 PMD_DRV_LOG(WARNING, "VF to PF message(%d) is not permitted!",
1287 case VIRTCHNL_OP_VERSION:
1288 PMD_DRV_LOG(INFO, "OP_VERSION received");
1289 i40e_pf_host_process_cmd_version(vf, b_op);
1291 case VIRTCHNL_OP_RESET_VF:
1292 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
1293 i40e_pf_host_process_cmd_reset_vf(vf);
1295 case VIRTCHNL_OP_GET_VF_RESOURCES:
1296 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
1297 i40e_pf_host_process_cmd_get_vf_resource(vf, b_op);
1299 case VIRTCHNL_OP_CONFIG_VSI_QUEUES:
1300 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
1301 i40e_pf_host_process_cmd_config_vsi_queues(vf, msg,
1304 case VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT:
1305 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES_EXT received");
1306 i40e_pf_host_process_cmd_config_vsi_queues_ext(vf, msg,
1309 case VIRTCHNL_OP_CONFIG_IRQ_MAP:
1310 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
1311 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen, b_op);
1313 case VIRTCHNL_OP_ENABLE_QUEUES:
1314 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
1316 i40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);
1317 i40e_notify_vf_link_status(dev, vf);
1319 i40e_pf_host_send_msg_to_vf(
1320 vf, VIRTCHNL_OP_ENABLE_QUEUES,
1321 I40E_NOT_SUPPORTED, NULL, 0);
1324 case VIRTCHNL_OP_DISABLE_QUEUES:
1325 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
1326 i40e_pf_host_process_cmd_disable_queues(vf, msg, msglen, b_op);
1328 case VIRTCHNL_OP_ADD_ETH_ADDR:
1329 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
1330 i40e_pf_host_process_cmd_add_ether_address(vf, msg,
1333 case VIRTCHNL_OP_DEL_ETH_ADDR:
1334 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
1335 i40e_pf_host_process_cmd_del_ether_address(vf, msg,
1338 case VIRTCHNL_OP_ADD_VLAN:
1339 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
1340 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen, b_op);
1342 case VIRTCHNL_OP_DEL_VLAN:
1343 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
1344 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen, b_op);
1346 case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
1347 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
1348 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg,
1351 case VIRTCHNL_OP_GET_STATS:
1352 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
1353 i40e_pf_host_process_cmd_get_stats(vf, b_op);
1355 case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING:
1356 PMD_DRV_LOG(INFO, "OP_ENABLE_VLAN_STRIPPING received");
1357 i40e_pf_host_process_cmd_enable_vlan_strip(vf, b_op);
1359 case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING:
1360 PMD_DRV_LOG(INFO, "OP_DISABLE_VLAN_STRIPPING received");
1361 i40e_pf_host_process_cmd_disable_vlan_strip(vf, b_op);
1363 case I40E_VIRTCHNL_OP_CFG_VLAN_PVID:
1364 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_PVID received");
1365 i40e_pf_host_process_cmd_cfg_pvid(vf, msg, msglen, b_op);
1367 /* Don't add command supported below, which will
1368 * return an error code.
1371 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
1372 i40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,
1379 i40e_pf_host_init(struct rte_eth_dev *dev)
1381 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1382 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1386 PMD_INIT_FUNC_TRACE();
1389 * return if SRIOV not enabled, VF number not configured or
1390 * no queue assigned.
1392 if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
1393 return I40E_SUCCESS;
1395 /* Allocate memory to store VF structure */
1396 pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
1400 /* Disable irq0 for VFR event */
1401 i40e_pf_disable_irq0(hw);
1403 /* Disable VF link status interrupt */
1404 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1405 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1406 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1407 I40E_WRITE_FLUSH(hw);
1409 for (i = 0; i < pf->vf_num; i++) {
1411 pf->vfs[i].state = I40E_VF_INACTIVE;
1412 pf->vfs[i].vf_idx = i;
1413 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
1414 if (ret != I40E_SUCCESS)
1418 RTE_ETH_DEV_SRIOV(dev).active = pf->vf_num;
1420 i40e_pf_enable_irq0(hw);
1422 return I40E_SUCCESS;
1426 i40e_pf_enable_irq0(hw);
1432 i40e_pf_host_uninit(struct rte_eth_dev *dev)
1434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1435 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1438 PMD_INIT_FUNC_TRACE();
1441 * return if SRIOV not enabled, VF number not configured or
1442 * no queue assigned.
1444 if ((!hw->func_caps.sr_iov_1_1) ||
1445 (pf->vf_num == 0) ||
1446 (pf->vf_nb_qps == 0))
1447 return I40E_SUCCESS;
1449 /* free memory to store VF structure */
1453 /* Disable irq0 for VFR event */
1454 i40e_pf_disable_irq0(hw);
1456 /* Disable VF link status interrupt */
1457 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1458 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1459 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1460 I40E_WRITE_FLUSH(hw);
1462 return I40E_SUCCESS;