4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
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18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_type.h"
59 #include "i40e_ethdev.h"
60 #include "i40e_rxtx.h"
62 #define DEFAULT_TX_RS_THRESH 32
63 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_TX_MAX_BURST 32
67 #define I40E_DMA_MEM_ALIGN 4096
69 /* Base address of the HW descriptor ring should be 128B aligned. */
70 #define I40E_RING_BASE_ALIGN 128
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #ifdef RTE_LIBRTE_IEEE1588
78 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
80 #define I40E_TX_IEEE1588_TMST 0
83 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
87 PKT_TX_OUTER_IP_CKSUM)
89 #define I40E_TX_OFFLOAD_MASK ( \
92 PKT_TX_OUTER_IP_CKSUM | \
96 PKT_TX_TUNNEL_MASK | \
97 I40E_TX_IEEE1588_TMST)
99 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
100 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
102 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
103 struct rte_mbuf **tx_pkts,
107 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
109 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
110 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
111 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
113 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
114 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
115 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
119 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
120 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
121 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
122 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
123 mb->vlan_tci_outer = mb->vlan_tci;
124 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
125 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
126 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
127 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
129 mb->vlan_tci_outer = 0;
132 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
133 mb->vlan_tci, mb->vlan_tci_outer);
136 /* Translate the rx descriptor status to pkt flags */
137 static inline uint64_t
138 i40e_rxd_status_to_pkt_flags(uint64_t qword)
142 /* Check if RSS_HASH */
143 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
144 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
145 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
147 /* Check if FDIR Match */
148 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
154 static inline uint64_t
155 i40e_rxd_error_to_pkt_flags(uint64_t qword)
158 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
160 #define I40E_RX_ERR_BITS 0x3f
161 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
162 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
166 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
167 flags |= PKT_RX_IP_CKSUM_BAD;
169 flags |= PKT_RX_IP_CKSUM_GOOD;
171 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
172 flags |= PKT_RX_L4_CKSUM_BAD;
174 flags |= PKT_RX_L4_CKSUM_GOOD;
176 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
177 flags |= PKT_RX_EIP_CKSUM_BAD;
182 /* Function to check and set the ieee1588 timesync index and get the
185 #ifdef RTE_LIBRTE_IEEE1588
186 static inline uint64_t
187 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
189 uint64_t pkt_flags = 0;
190 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
191 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
192 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
194 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
195 == RTE_PTYPE_L2_ETHER_TIMESYNC)
196 pkt_flags = PKT_RX_IEEE1588_PTP;
198 pkt_flags |= PKT_RX_IEEE1588_TMST;
199 mb->timesync = tsyn & 0x03;
206 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
207 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
208 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
209 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
210 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
212 static inline uint64_t
213 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
216 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
217 uint16_t flexbh, flexbl;
219 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
220 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
221 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
222 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
223 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
224 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
227 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
229 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
230 flags |= PKT_RX_FDIR_ID;
231 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
233 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
234 flags |= PKT_RX_FDIR_FLX;
236 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
238 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
239 flags |= PKT_RX_FDIR_FLX;
243 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
244 flags |= PKT_RX_FDIR_ID;
250 i40e_parse_tunneling_params(uint64_t ol_flags,
251 union i40e_tx_offload tx_offload,
252 uint32_t *cd_tunneling)
254 /* EIPT: External (outer) IP header type */
255 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
256 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
257 else if (ol_flags & PKT_TX_OUTER_IPV4)
258 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
259 else if (ol_flags & PKT_TX_OUTER_IPV6)
260 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
262 /* EIPLEN: External (outer) IP header length, in DWords */
263 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
264 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
266 /* L4TUNT: L4 Tunneling Type */
267 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
268 case PKT_TX_TUNNEL_IPIP:
269 /* for non UDP / GRE tunneling, set to 00b */
271 case PKT_TX_TUNNEL_VXLAN:
272 case PKT_TX_TUNNEL_GENEVE:
273 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
275 case PKT_TX_TUNNEL_GRE:
276 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
279 PMD_TX_LOG(ERR, "Tunnel type not supported");
283 /* L4TUNLEN: L4 Tunneling Length, in Words
285 * We depend on app to set rte_mbuf.l2_len correctly.
286 * For IP in GRE it should be set to the length of the GRE
288 * for MAC in GRE or MAC in UDP it should be set to the length
289 * of the GRE or UDP headers plus the inner MAC up to including
290 * its last Ethertype.
292 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
293 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
297 i40e_txd_enable_checksum(uint64_t ol_flags,
300 union i40e_tx_offload tx_offload)
303 if (ol_flags & PKT_TX_TUNNEL_MASK)
304 *td_offset |= (tx_offload.outer_l2_len >> 1)
305 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
307 *td_offset |= (tx_offload.l2_len >> 1)
308 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
310 /* Enable L3 checksum offloads */
311 if (ol_flags & PKT_TX_IP_CKSUM) {
312 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
313 *td_offset |= (tx_offload.l3_len >> 2)
314 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
315 } else if (ol_flags & PKT_TX_IPV4) {
316 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
317 *td_offset |= (tx_offload.l3_len >> 2)
318 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
319 } else if (ol_flags & PKT_TX_IPV6) {
320 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
321 *td_offset |= (tx_offload.l3_len >> 2)
322 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
325 if (ol_flags & PKT_TX_TCP_SEG) {
326 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
327 *td_offset |= (tx_offload.l4_len >> 2)
328 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
332 /* Enable L4 checksum offloads */
333 switch (ol_flags & PKT_TX_L4_MASK) {
334 case PKT_TX_TCP_CKSUM:
335 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
336 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
337 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
339 case PKT_TX_SCTP_CKSUM:
340 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
341 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
342 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
344 case PKT_TX_UDP_CKSUM:
345 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
346 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
347 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
354 /* Construct the tx flags */
355 static inline uint64_t
356 i40e_build_ctob(uint32_t td_cmd,
361 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
362 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
363 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
364 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
365 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
369 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
371 struct i40e_tx_entry *sw_ring = txq->sw_ring;
372 volatile struct i40e_tx_desc *txd = txq->tx_ring;
373 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
374 uint16_t nb_tx_desc = txq->nb_tx_desc;
375 uint16_t desc_to_clean_to;
376 uint16_t nb_tx_to_clean;
378 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
379 if (desc_to_clean_to >= nb_tx_desc)
380 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
382 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
383 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
384 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
385 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
386 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
387 "(port=%d queue=%d)", desc_to_clean_to,
388 txq->port_id, txq->queue_id);
392 if (last_desc_cleaned > desc_to_clean_to)
393 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
396 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
399 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
401 txq->last_desc_cleaned = desc_to_clean_to;
402 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
408 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
409 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
411 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
416 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
417 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
418 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
419 "rxq->rx_free_thresh=%d, "
420 "RTE_PMD_I40E_RX_MAX_BURST=%d",
421 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
423 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
424 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
425 "rxq->rx_free_thresh=%d, "
426 "rxq->nb_rx_desc=%d",
427 rxq->rx_free_thresh, rxq->nb_rx_desc);
429 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
430 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
431 "rxq->nb_rx_desc=%d, "
432 "rxq->rx_free_thresh=%d",
433 rxq->nb_rx_desc, rxq->rx_free_thresh);
443 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
444 #define I40E_LOOK_AHEAD 8
445 #if (I40E_LOOK_AHEAD != 8)
446 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
449 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
451 volatile union i40e_rx_desc *rxdp;
452 struct i40e_rx_entry *rxep;
457 int32_t s[I40E_LOOK_AHEAD], nb_dd;
458 int32_t i, j, nb_rx = 0;
460 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
462 rxdp = &rxq->rx_ring[rxq->rx_tail];
463 rxep = &rxq->sw_ring[rxq->rx_tail];
465 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
466 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
467 I40E_RXD_QW1_STATUS_SHIFT;
469 /* Make sure there is at least 1 packet to receive */
470 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
474 * Scan LOOK_AHEAD descriptors at a time to determine which
475 * descriptors reference packets that are ready to be received.
477 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
478 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
479 /* Read desc statuses backwards to avoid race condition */
480 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
481 qword1 = rte_le_to_cpu_64(\
482 rxdp[j].wb.qword1.status_error_len);
483 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
484 I40E_RXD_QW1_STATUS_SHIFT;
489 /* Compute how many status bits were set */
490 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
491 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
495 /* Translate descriptor info to mbuf parameters */
496 for (j = 0; j < nb_dd; j++) {
498 qword1 = rte_le_to_cpu_64(\
499 rxdp[j].wb.qword1.status_error_len);
500 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
501 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
502 mb->data_len = pkt_len;
503 mb->pkt_len = pkt_len;
505 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
506 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
507 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
509 ptype_tbl[(uint8_t)((qword1 &
510 I40E_RXD_QW1_PTYPE_MASK) >>
511 I40E_RXD_QW1_PTYPE_SHIFT)];
512 if (pkt_flags & PKT_RX_RSS_HASH)
513 mb->hash.rss = rte_le_to_cpu_32(\
514 rxdp[j].wb.qword0.hi_dword.rss);
515 if (pkt_flags & PKT_RX_FDIR)
516 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
518 #ifdef RTE_LIBRTE_IEEE1588
519 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
521 mb->ol_flags |= pkt_flags;
525 for (j = 0; j < I40E_LOOK_AHEAD; j++)
526 rxq->rx_stage[i + j] = rxep[j].mbuf;
528 if (nb_dd != I40E_LOOK_AHEAD)
532 /* Clear software ring entries */
533 for (i = 0; i < nb_rx; i++)
534 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
539 static inline uint16_t
540 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
541 struct rte_mbuf **rx_pkts,
545 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
547 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
549 for (i = 0; i < nb_pkts; i++)
550 rx_pkts[i] = stage[i];
552 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
553 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
559 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
561 volatile union i40e_rx_desc *rxdp;
562 struct i40e_rx_entry *rxep;
564 uint16_t alloc_idx, i;
568 /* Allocate buffers in bulk */
569 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
570 (rxq->rx_free_thresh - 1));
571 rxep = &(rxq->sw_ring[alloc_idx]);
572 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
573 rxq->rx_free_thresh);
574 if (unlikely(diag != 0)) {
575 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
579 rxdp = &rxq->rx_ring[alloc_idx];
580 for (i = 0; i < rxq->rx_free_thresh; i++) {
581 if (likely(i < (rxq->rx_free_thresh - 1)))
582 /* Prefetch next mbuf */
583 rte_prefetch0(rxep[i + 1].mbuf);
586 rte_mbuf_refcnt_set(mb, 1);
588 mb->data_off = RTE_PKTMBUF_HEADROOM;
590 mb->port = rxq->port_id;
591 dma_addr = rte_cpu_to_le_64(\
592 rte_mbuf_data_dma_addr_default(mb));
593 rxdp[i].read.hdr_addr = 0;
594 rxdp[i].read.pkt_addr = dma_addr;
597 /* Update rx tail regsiter */
599 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
601 rxq->rx_free_trigger =
602 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
603 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
604 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
609 static inline uint16_t
610 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
612 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
613 struct rte_eth_dev *dev;
619 if (rxq->rx_nb_avail)
620 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
622 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
623 rxq->rx_next_avail = 0;
624 rxq->rx_nb_avail = nb_rx;
625 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
627 if (rxq->rx_tail > rxq->rx_free_trigger) {
628 if (i40e_rx_alloc_bufs(rxq) != 0) {
631 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
632 dev->data->rx_mbuf_alloc_failed +=
635 rxq->rx_nb_avail = 0;
636 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
637 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
638 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
644 if (rxq->rx_tail >= rxq->nb_rx_desc)
647 if (rxq->rx_nb_avail)
648 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
654 i40e_recv_pkts_bulk_alloc(void *rx_queue,
655 struct rte_mbuf **rx_pkts,
658 uint16_t nb_rx = 0, n, count;
660 if (unlikely(nb_pkts == 0))
663 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
664 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
667 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
668 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
669 nb_rx = (uint16_t)(nb_rx + count);
670 nb_pkts = (uint16_t)(nb_pkts - count);
679 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
680 struct rte_mbuf __rte_unused **rx_pkts,
681 uint16_t __rte_unused nb_pkts)
685 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
688 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
690 struct i40e_rx_queue *rxq;
691 volatile union i40e_rx_desc *rx_ring;
692 volatile union i40e_rx_desc *rxdp;
693 union i40e_rx_desc rxd;
694 struct i40e_rx_entry *sw_ring;
695 struct i40e_rx_entry *rxe;
696 struct rte_eth_dev *dev;
697 struct rte_mbuf *rxm;
698 struct rte_mbuf *nmb;
702 uint16_t rx_packet_len;
703 uint16_t rx_id, nb_hold;
711 rx_id = rxq->rx_tail;
712 rx_ring = rxq->rx_ring;
713 sw_ring = rxq->sw_ring;
714 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
716 while (nb_rx < nb_pkts) {
717 rxdp = &rx_ring[rx_id];
718 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
719 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
720 >> I40E_RXD_QW1_STATUS_SHIFT;
722 /* Check the DD bit first */
723 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
726 nmb = rte_mbuf_raw_alloc(rxq->mp);
727 if (unlikely(!nmb)) {
728 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
729 dev->data->rx_mbuf_alloc_failed++;
735 rxe = &sw_ring[rx_id];
737 if (unlikely(rx_id == rxq->nb_rx_desc))
740 /* Prefetch next mbuf */
741 rte_prefetch0(sw_ring[rx_id].mbuf);
744 * When next RX descriptor is on a cache line boundary,
745 * prefetch the next 4 RX descriptors and next 8 pointers
748 if ((rx_id & 0x3) == 0) {
749 rte_prefetch0(&rx_ring[rx_id]);
750 rte_prefetch0(&sw_ring[rx_id]);
755 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
756 rxdp->read.hdr_addr = 0;
757 rxdp->read.pkt_addr = dma_addr;
759 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
760 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
762 rxm->data_off = RTE_PKTMBUF_HEADROOM;
763 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
766 rxm->pkt_len = rx_packet_len;
767 rxm->data_len = rx_packet_len;
768 rxm->port = rxq->port_id;
770 i40e_rxd_to_vlan_tci(rxm, &rxd);
771 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
772 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
774 ptype_tbl[(uint8_t)((qword1 &
775 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
776 if (pkt_flags & PKT_RX_RSS_HASH)
778 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
779 if (pkt_flags & PKT_RX_FDIR)
780 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
782 #ifdef RTE_LIBRTE_IEEE1588
783 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
785 rxm->ol_flags |= pkt_flags;
787 rx_pkts[nb_rx++] = rxm;
789 rxq->rx_tail = rx_id;
792 * If the number of free RX descriptors is greater than the RX free
793 * threshold of the queue, advance the receive tail register of queue.
794 * Update that register with the value of the last processed RX
795 * descriptor minus 1.
797 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
798 if (nb_hold > rxq->rx_free_thresh) {
799 rx_id = (uint16_t) ((rx_id == 0) ?
800 (rxq->nb_rx_desc - 1) : (rx_id - 1));
801 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
804 rxq->nb_rx_hold = nb_hold;
810 i40e_recv_scattered_pkts(void *rx_queue,
811 struct rte_mbuf **rx_pkts,
814 struct i40e_rx_queue *rxq = rx_queue;
815 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
816 volatile union i40e_rx_desc *rxdp;
817 union i40e_rx_desc rxd;
818 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
819 struct i40e_rx_entry *rxe;
820 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
821 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
822 struct rte_mbuf *nmb, *rxm;
823 uint16_t rx_id = rxq->rx_tail;
824 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
825 struct rte_eth_dev *dev;
830 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
832 while (nb_rx < nb_pkts) {
833 rxdp = &rx_ring[rx_id];
834 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
835 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
836 I40E_RXD_QW1_STATUS_SHIFT;
838 /* Check the DD bit */
839 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
842 nmb = rte_mbuf_raw_alloc(rxq->mp);
843 if (unlikely(!nmb)) {
844 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
845 dev->data->rx_mbuf_alloc_failed++;
851 rxe = &sw_ring[rx_id];
853 if (rx_id == rxq->nb_rx_desc)
856 /* Prefetch next mbuf */
857 rte_prefetch0(sw_ring[rx_id].mbuf);
860 * When next RX descriptor is on a cache line boundary,
861 * prefetch the next 4 RX descriptors and next 8 pointers
864 if ((rx_id & 0x3) == 0) {
865 rte_prefetch0(&rx_ring[rx_id]);
866 rte_prefetch0(&sw_ring[rx_id]);
872 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
874 /* Set data buffer address and data length of the mbuf */
875 rxdp->read.hdr_addr = 0;
876 rxdp->read.pkt_addr = dma_addr;
877 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
878 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
879 rxm->data_len = rx_packet_len;
880 rxm->data_off = RTE_PKTMBUF_HEADROOM;
883 * If this is the first buffer of the received packet, set the
884 * pointer to the first mbuf of the packet and initialize its
885 * context. Otherwise, update the total length and the number
886 * of segments of the current scattered packet, and update the
887 * pointer to the last mbuf of the current packet.
891 first_seg->nb_segs = 1;
892 first_seg->pkt_len = rx_packet_len;
895 (uint16_t)(first_seg->pkt_len +
897 first_seg->nb_segs++;
898 last_seg->next = rxm;
902 * If this is not the last buffer of the received packet,
903 * update the pointer to the last mbuf of the current scattered
904 * packet and continue to parse the RX ring.
906 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
912 * This is the last buffer of the received packet. If the CRC
913 * is not stripped by the hardware:
914 * - Subtract the CRC length from the total packet length.
915 * - If the last buffer only contains the whole CRC or a part
916 * of it, free the mbuf associated to the last buffer. If part
917 * of the CRC is also contained in the previous mbuf, subtract
918 * the length of that CRC part from the data length of the
922 if (unlikely(rxq->crc_len > 0)) {
923 first_seg->pkt_len -= ETHER_CRC_LEN;
924 if (rx_packet_len <= ETHER_CRC_LEN) {
925 rte_pktmbuf_free_seg(rxm);
926 first_seg->nb_segs--;
928 (uint16_t)(last_seg->data_len -
929 (ETHER_CRC_LEN - rx_packet_len));
930 last_seg->next = NULL;
932 rxm->data_len = (uint16_t)(rx_packet_len -
936 first_seg->port = rxq->port_id;
937 first_seg->ol_flags = 0;
938 i40e_rxd_to_vlan_tci(first_seg, &rxd);
939 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
940 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
941 first_seg->packet_type =
942 ptype_tbl[(uint8_t)((qword1 &
943 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
944 if (pkt_flags & PKT_RX_RSS_HASH)
945 first_seg->hash.rss =
946 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
947 if (pkt_flags & PKT_RX_FDIR)
948 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
950 #ifdef RTE_LIBRTE_IEEE1588
951 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
953 first_seg->ol_flags |= pkt_flags;
955 /* Prefetch data of first segment, if configured to do so. */
956 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
957 first_seg->data_off));
958 rx_pkts[nb_rx++] = first_seg;
962 /* Record index of the next RX descriptor to probe. */
963 rxq->rx_tail = rx_id;
964 rxq->pkt_first_seg = first_seg;
965 rxq->pkt_last_seg = last_seg;
968 * If the number of free RX descriptors is greater than the RX free
969 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
970 * register. Update the RDT with the value of the last processed RX
971 * descriptor minus 1, to guarantee that the RDT register is never
972 * equal to the RDH register, which creates a "full" ring situtation
973 * from the hardware point of view.
975 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
976 if (nb_hold > rxq->rx_free_thresh) {
977 rx_id = (uint16_t)(rx_id == 0 ?
978 (rxq->nb_rx_desc - 1) : (rx_id - 1));
979 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
982 rxq->nb_rx_hold = nb_hold;
987 /* Check if the context descriptor is needed for TX offloading */
988 static inline uint16_t
989 i40e_calc_context_desc(uint64_t flags)
991 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
996 #ifdef RTE_LIBRTE_IEEE1588
997 mask |= PKT_TX_IEEE1588_TMST;
1000 return (flags & mask) ? 1 : 0;
1003 /* set i40e TSO context descriptor */
1004 static inline uint64_t
1005 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1007 uint64_t ctx_desc = 0;
1008 uint32_t cd_cmd, hdr_len, cd_tso_len;
1010 if (!tx_offload.l4_len) {
1011 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1016 * in case of non tunneling packet, the outer_l2_len and
1017 * outer_l3_len must be 0.
1019 hdr_len = tx_offload.outer_l2_len +
1020 tx_offload.outer_l3_len +
1025 cd_cmd = I40E_TX_CTX_DESC_TSO;
1026 cd_tso_len = mbuf->pkt_len - hdr_len;
1027 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1028 ((uint64_t)cd_tso_len <<
1029 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1030 ((uint64_t)mbuf->tso_segsz <<
1031 I40E_TXD_CTX_QW1_MSS_SHIFT);
1037 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1039 struct i40e_tx_queue *txq;
1040 struct i40e_tx_entry *sw_ring;
1041 struct i40e_tx_entry *txe, *txn;
1042 volatile struct i40e_tx_desc *txd;
1043 volatile struct i40e_tx_desc *txr;
1044 struct rte_mbuf *tx_pkt;
1045 struct rte_mbuf *m_seg;
1046 uint32_t cd_tunneling_params;
1057 uint64_t buf_dma_addr;
1058 union i40e_tx_offload tx_offload = {0};
1061 sw_ring = txq->sw_ring;
1063 tx_id = txq->tx_tail;
1064 txe = &sw_ring[tx_id];
1066 /* Check if the descriptor ring needs to be cleaned. */
1067 if (txq->nb_tx_free < txq->tx_free_thresh)
1068 i40e_xmit_cleanup(txq);
1070 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1075 tx_pkt = *tx_pkts++;
1076 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1078 ol_flags = tx_pkt->ol_flags;
1079 tx_offload.l2_len = tx_pkt->l2_len;
1080 tx_offload.l3_len = tx_pkt->l3_len;
1081 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1082 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1083 tx_offload.l4_len = tx_pkt->l4_len;
1084 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1086 /* Calculate the number of context descriptors needed. */
1087 nb_ctx = i40e_calc_context_desc(ol_flags);
1090 * The number of descriptors that must be allocated for
1091 * a packet equals to the number of the segments of that
1092 * packet plus 1 context descriptor if needed.
1094 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1095 tx_last = (uint16_t)(tx_id + nb_used - 1);
1098 if (tx_last >= txq->nb_tx_desc)
1099 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1101 if (nb_used > txq->nb_tx_free) {
1102 if (i40e_xmit_cleanup(txq) != 0) {
1107 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1108 while (nb_used > txq->nb_tx_free) {
1109 if (i40e_xmit_cleanup(txq) != 0) {
1118 /* Descriptor based VLAN insertion */
1119 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1120 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1121 td_tag = tx_pkt->vlan_tci;
1124 /* Always enable CRC offload insertion */
1125 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1127 /* Fill in tunneling parameters if necessary */
1128 cd_tunneling_params = 0;
1129 if (ol_flags & PKT_TX_TUNNEL_MASK)
1130 i40e_parse_tunneling_params(ol_flags, tx_offload,
1131 &cd_tunneling_params);
1132 /* Enable checksum offloading */
1133 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1134 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1135 &td_offset, tx_offload);
1138 /* Setup TX context descriptor if required */
1139 volatile struct i40e_tx_context_desc *ctx_txd =
1140 (volatile struct i40e_tx_context_desc *)\
1142 uint16_t cd_l2tag2 = 0;
1143 uint64_t cd_type_cmd_tso_mss =
1144 I40E_TX_DESC_DTYPE_CONTEXT;
1146 txn = &sw_ring[txe->next_id];
1147 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1148 if (txe->mbuf != NULL) {
1149 rte_pktmbuf_free_seg(txe->mbuf);
1153 /* TSO enabled means no timestamp */
1154 if (ol_flags & PKT_TX_TCP_SEG)
1155 cd_type_cmd_tso_mss |=
1156 i40e_set_tso_ctx(tx_pkt, tx_offload);
1158 #ifdef RTE_LIBRTE_IEEE1588
1159 if (ol_flags & PKT_TX_IEEE1588_TMST)
1160 cd_type_cmd_tso_mss |=
1161 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1162 I40E_TXD_CTX_QW1_CMD_SHIFT);
1166 ctx_txd->tunneling_params =
1167 rte_cpu_to_le_32(cd_tunneling_params);
1168 if (ol_flags & PKT_TX_QINQ_PKT) {
1169 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1170 cd_type_cmd_tso_mss |=
1171 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1172 I40E_TXD_CTX_QW1_CMD_SHIFT);
1174 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1175 ctx_txd->type_cmd_tso_mss =
1176 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1178 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1179 "tunneling_params: %#x;\n"
1182 "type_cmd_tso_mss: %#"PRIx64";\n",
1184 ctx_txd->tunneling_params,
1187 ctx_txd->type_cmd_tso_mss);
1189 txe->last_id = tx_last;
1190 tx_id = txe->next_id;
1197 txn = &sw_ring[txe->next_id];
1200 rte_pktmbuf_free_seg(txe->mbuf);
1203 /* Setup TX Descriptor */
1204 slen = m_seg->data_len;
1205 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1207 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1208 "buf_dma_addr: %#"PRIx64";\n"
1213 tx_pkt, tx_id, buf_dma_addr,
1214 td_cmd, td_offset, slen, td_tag);
1216 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1217 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1218 td_offset, slen, td_tag);
1219 txe->last_id = tx_last;
1220 tx_id = txe->next_id;
1222 m_seg = m_seg->next;
1223 } while (m_seg != NULL);
1225 /* The last packet data descriptor needs End Of Packet (EOP) */
1226 td_cmd |= I40E_TX_DESC_CMD_EOP;
1227 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1228 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1230 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1231 PMD_TX_FREE_LOG(DEBUG,
1232 "Setting RS bit on TXD id="
1233 "%4u (port=%d queue=%d)",
1234 tx_last, txq->port_id, txq->queue_id);
1236 td_cmd |= I40E_TX_DESC_CMD_RS;
1238 /* Update txq RS bit counters */
1239 txq->nb_tx_used = 0;
1242 txd->cmd_type_offset_bsz |=
1243 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1244 I40E_TXD_QW1_CMD_SHIFT);
1250 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1251 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1252 (unsigned) tx_id, (unsigned) nb_tx);
1254 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1255 txq->tx_tail = tx_id;
1260 static __rte_always_inline int
1261 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1263 struct i40e_tx_entry *txep;
1266 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1267 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1268 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1271 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1273 for (i = 0; i < txq->tx_rs_thresh; i++)
1274 rte_prefetch0((txep + i)->mbuf);
1276 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1277 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1278 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1282 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1283 rte_pktmbuf_free_seg(txep->mbuf);
1288 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1289 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1290 if (txq->tx_next_dd >= txq->nb_tx_desc)
1291 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1293 return txq->tx_rs_thresh;
1296 /* Populate 4 descriptors with data from 4 mbufs */
1298 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1303 for (i = 0; i < 4; i++, txdp++, pkts++) {
1304 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1305 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1306 txdp->cmd_type_offset_bsz =
1307 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1308 (*pkts)->data_len, 0);
1312 /* Populate 1 descriptor with data from 1 mbuf */
1314 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1318 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1319 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1320 txdp->cmd_type_offset_bsz =
1321 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1322 (*pkts)->data_len, 0);
1325 /* Fill hardware descriptor ring with mbuf data */
1327 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1328 struct rte_mbuf **pkts,
1331 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1332 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1333 const int N_PER_LOOP = 4;
1334 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1335 int mainpart, leftover;
1338 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1339 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1340 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1341 for (j = 0; j < N_PER_LOOP; ++j) {
1342 (txep + i + j)->mbuf = *(pkts + i + j);
1344 tx4(txdp + i, pkts + i);
1346 if (unlikely(leftover > 0)) {
1347 for (i = 0; i < leftover; ++i) {
1348 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1349 tx1(txdp + mainpart + i, pkts + mainpart + i);
1354 static inline uint16_t
1355 tx_xmit_pkts(struct i40e_tx_queue *txq,
1356 struct rte_mbuf **tx_pkts,
1359 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1363 * Begin scanning the H/W ring for done descriptors when the number
1364 * of available descriptors drops below tx_free_thresh. For each done
1365 * descriptor, free the associated buffer.
1367 if (txq->nb_tx_free < txq->tx_free_thresh)
1368 i40e_tx_free_bufs(txq);
1370 /* Use available descriptor only */
1371 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1372 if (unlikely(!nb_pkts))
1375 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1376 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1377 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1378 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1379 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1380 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1381 I40E_TXD_QW1_CMD_SHIFT);
1382 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1386 /* Fill hardware descriptor ring with mbuf data */
1387 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1388 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1390 /* Determin if RS bit needs to be set */
1391 if (txq->tx_tail > txq->tx_next_rs) {
1392 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1393 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1394 I40E_TXD_QW1_CMD_SHIFT);
1396 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1397 if (txq->tx_next_rs >= txq->nb_tx_desc)
1398 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1401 if (txq->tx_tail >= txq->nb_tx_desc)
1404 /* Update the tx tail register */
1406 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1412 i40e_xmit_pkts_simple(void *tx_queue,
1413 struct rte_mbuf **tx_pkts,
1418 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1419 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1423 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1426 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1427 &tx_pkts[nb_tx], num);
1428 nb_tx = (uint16_t)(nb_tx + ret);
1429 nb_pkts = (uint16_t)(nb_pkts - ret);
1438 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1442 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1447 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1448 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1459 /*********************************************************************
1463 **********************************************************************/
1465 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1472 for (i = 0; i < nb_pkts; i++) {
1474 ol_flags = m->ol_flags;
1477 * m->nb_segs is uint8_t, so nb_segs is always less than
1479 * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1481 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1482 if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1483 rte_errno = -EINVAL;
1486 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1487 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1488 /* MSS outside the range (256B - 9674B) are considered
1491 rte_errno = -EINVAL;
1495 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1496 rte_errno = -ENOTSUP;
1500 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1501 ret = rte_validate_tx_offload(m);
1507 ret = rte_net_intel_cksum_prepare(m);
1517 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1518 * application used, which assume having sequential ones. But from driver's
1519 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1520 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1521 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1522 * use queue_idx from 0 to 95 to access queues, while real queue would be
1523 * different. This function will do a queue mapping to find VSI the queue
1526 static struct i40e_vsi*
1527 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1529 /* the queue in MAIN VSI range */
1530 if (queue_idx < pf->main_vsi->nb_qps)
1531 return pf->main_vsi;
1533 queue_idx -= pf->main_vsi->nb_qps;
1535 /* queue_idx is greater than VMDQ VSIs range */
1536 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1537 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1541 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1545 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1547 /* the queue in MAIN VSI range */
1548 if (queue_idx < pf->main_vsi->nb_qps)
1551 /* It's VMDQ queues */
1552 queue_idx -= pf->main_vsi->nb_qps;
1554 if (pf->nb_cfg_vmdq_vsi)
1555 return queue_idx % pf->vmdq_nb_qps;
1557 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1558 return (uint16_t)(-1);
1563 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1565 struct i40e_rx_queue *rxq;
1567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569 PMD_INIT_FUNC_TRACE();
1571 if (rx_queue_id < dev->data->nb_rx_queues) {
1572 rxq = dev->data->rx_queues[rx_queue_id];
1574 err = i40e_alloc_rx_queue_mbufs(rxq);
1576 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1582 /* Init the RX tail regieter. */
1583 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1585 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1588 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1591 i40e_rx_queue_release_mbufs(rxq);
1592 i40e_reset_rx_queue(rxq);
1594 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1601 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1603 struct i40e_rx_queue *rxq;
1605 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607 if (rx_queue_id < dev->data->nb_rx_queues) {
1608 rxq = dev->data->rx_queues[rx_queue_id];
1611 * rx_queue_id is queue id aplication refers to, while
1612 * rxq->reg_idx is the real queue index.
1614 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1617 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1621 i40e_rx_queue_release_mbufs(rxq);
1622 i40e_reset_rx_queue(rxq);
1623 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1630 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1633 struct i40e_tx_queue *txq;
1634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636 PMD_INIT_FUNC_TRACE();
1638 if (tx_queue_id < dev->data->nb_tx_queues) {
1639 txq = dev->data->tx_queues[tx_queue_id];
1642 * tx_queue_id is queue id aplication refers to, while
1643 * rxq->reg_idx is the real queue index.
1645 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1647 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1650 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1657 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1659 struct i40e_tx_queue *txq;
1661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 if (tx_queue_id < dev->data->nb_tx_queues) {
1664 txq = dev->data->tx_queues[tx_queue_id];
1667 * tx_queue_id is queue id aplication refers to, while
1668 * txq->reg_idx is the real queue index.
1670 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1673 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1678 i40e_tx_queue_release_mbufs(txq);
1679 i40e_reset_tx_queue(txq);
1680 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1687 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1689 static const uint32_t ptypes[] = {
1690 /* refers to i40e_rxd_pkt_type_mapping() */
1692 RTE_PTYPE_L2_ETHER_TIMESYNC,
1693 RTE_PTYPE_L2_ETHER_LLDP,
1694 RTE_PTYPE_L2_ETHER_ARP,
1695 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1696 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1699 RTE_PTYPE_L4_NONFRAG,
1703 RTE_PTYPE_TUNNEL_GRENAT,
1704 RTE_PTYPE_TUNNEL_IP,
1705 RTE_PTYPE_INNER_L2_ETHER,
1706 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1707 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1708 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1709 RTE_PTYPE_INNER_L4_FRAG,
1710 RTE_PTYPE_INNER_L4_ICMP,
1711 RTE_PTYPE_INNER_L4_NONFRAG,
1712 RTE_PTYPE_INNER_L4_SCTP,
1713 RTE_PTYPE_INNER_L4_TCP,
1714 RTE_PTYPE_INNER_L4_UDP,
1718 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1719 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1720 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1722 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1723 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1724 dev->rx_pkt_burst == i40e_recv_pkts_vec)
1730 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1733 unsigned int socket_id,
1734 const struct rte_eth_rxconf *rx_conf,
1735 struct rte_mempool *mp)
1737 struct i40e_vsi *vsi;
1738 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1740 struct i40e_adapter *ad =
1741 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1742 struct i40e_rx_queue *rxq;
1743 const struct rte_memzone *rz;
1746 uint16_t base, bsf, tc_mapping;
1747 int use_def_burst_func = 1;
1749 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1750 struct i40e_vf *vf =
1751 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1754 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1757 PMD_DRV_LOG(ERR, "VSI not available or queue "
1758 "index exceeds the maximum");
1759 return I40E_ERR_PARAM;
1761 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1762 (nb_desc > I40E_MAX_RING_DESC) ||
1763 (nb_desc < I40E_MIN_RING_DESC)) {
1764 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1765 "invalid", nb_desc);
1766 return I40E_ERR_PARAM;
1769 /* Free memory if needed */
1770 if (dev->data->rx_queues[queue_idx]) {
1771 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1772 dev->data->rx_queues[queue_idx] = NULL;
1775 /* Allocate the rx queue data structure */
1776 rxq = rte_zmalloc_socket("i40e rx queue",
1777 sizeof(struct i40e_rx_queue),
1778 RTE_CACHE_LINE_SIZE,
1781 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1782 "rx queue data structure");
1786 rxq->nb_rx_desc = nb_desc;
1787 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1788 rxq->queue_id = queue_idx;
1789 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1790 rxq->reg_idx = queue_idx;
1791 else /* PF device */
1792 rxq->reg_idx = vsi->base_queue +
1793 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1795 rxq->port_id = dev->data->port_id;
1796 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1798 rxq->drop_en = rx_conf->rx_drop_en;
1800 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1802 /* Allocate the maximun number of RX ring hardware descriptor. */
1803 len = I40E_MAX_RING_DESC;
1806 * Allocating a little more memory because vectorized/bulk_alloc Rx
1807 * functions doesn't check boundaries each time.
1809 len += RTE_PMD_I40E_RX_MAX_BURST;
1811 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1812 I40E_DMA_MEM_ALIGN);
1814 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1815 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1817 i40e_dev_rx_queue_release(rxq);
1818 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1822 /* Zero all the descriptors in the ring. */
1823 memset(rz->addr, 0, ring_size);
1825 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1826 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1828 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1830 /* Allocate the software ring. */
1832 rte_zmalloc_socket("i40e rx sw ring",
1833 sizeof(struct i40e_rx_entry) * len,
1834 RTE_CACHE_LINE_SIZE,
1836 if (!rxq->sw_ring) {
1837 i40e_dev_rx_queue_release(rxq);
1838 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1842 i40e_reset_rx_queue(rxq);
1844 dev->data->rx_queues[queue_idx] = rxq;
1846 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1848 if (!use_def_burst_func) {
1849 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1850 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1851 "satisfied. Rx Burst Bulk Alloc function will be "
1852 "used on port=%d, queue=%d.",
1853 rxq->port_id, rxq->queue_id);
1854 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1856 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1857 "not satisfied, Scattered Rx is requested, "
1858 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1859 "not enabled on port=%d, queue=%d.",
1860 rxq->port_id, rxq->queue_id);
1861 ad->rx_bulk_alloc_allowed = false;
1864 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1865 if (!(vsi->enabled_tc & (1 << i)))
1867 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1868 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1869 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1870 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1871 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1873 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1881 i40e_dev_rx_queue_release(void *rxq)
1883 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1886 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1890 i40e_rx_queue_release_mbufs(q);
1891 rte_free(q->sw_ring);
1896 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1898 #define I40E_RXQ_SCAN_INTERVAL 4
1899 volatile union i40e_rx_desc *rxdp;
1900 struct i40e_rx_queue *rxq;
1903 rxq = dev->data->rx_queues[rx_queue_id];
1904 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1905 while ((desc < rxq->nb_rx_desc) &&
1906 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1907 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1908 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1910 * Check the DD bit of a rx descriptor of each 4 in a group,
1911 * to avoid checking too frequently and downgrading performance
1914 desc += I40E_RXQ_SCAN_INTERVAL;
1915 rxdp += I40E_RXQ_SCAN_INTERVAL;
1916 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1917 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1918 desc - rxq->nb_rx_desc]);
1925 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1927 volatile union i40e_rx_desc *rxdp;
1928 struct i40e_rx_queue *rxq = rx_queue;
1932 if (unlikely(offset >= rxq->nb_rx_desc)) {
1933 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1937 desc = rxq->rx_tail + offset;
1938 if (desc >= rxq->nb_rx_desc)
1939 desc -= rxq->nb_rx_desc;
1941 rxdp = &(rxq->rx_ring[desc]);
1943 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1944 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1945 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1951 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1953 struct i40e_rx_queue *rxq = rx_queue;
1954 volatile uint64_t *status;
1958 if (unlikely(offset >= rxq->nb_rx_desc))
1961 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1962 return RTE_ETH_RX_DESC_UNAVAIL;
1964 desc = rxq->rx_tail + offset;
1965 if (desc >= rxq->nb_rx_desc)
1966 desc -= rxq->nb_rx_desc;
1968 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1969 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1970 << I40E_RXD_QW1_STATUS_SHIFT);
1972 return RTE_ETH_RX_DESC_DONE;
1974 return RTE_ETH_RX_DESC_AVAIL;
1978 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1980 struct i40e_tx_queue *txq = tx_queue;
1981 volatile uint64_t *status;
1982 uint64_t mask, expect;
1985 if (unlikely(offset >= txq->nb_tx_desc))
1988 desc = txq->tx_tail + offset;
1989 /* go to next desc that has the RS bit */
1990 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1992 if (desc >= txq->nb_tx_desc) {
1993 desc -= txq->nb_tx_desc;
1994 if (desc >= txq->nb_tx_desc)
1995 desc -= txq->nb_tx_desc;
1998 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1999 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2000 expect = rte_cpu_to_le_64(
2001 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2002 if ((*status & mask) == expect)
2003 return RTE_ETH_TX_DESC_DONE;
2005 return RTE_ETH_TX_DESC_FULL;
2009 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2012 unsigned int socket_id,
2013 const struct rte_eth_txconf *tx_conf)
2015 struct i40e_vsi *vsi;
2016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2018 struct i40e_tx_queue *txq;
2019 const struct rte_memzone *tz;
2021 uint16_t tx_rs_thresh, tx_free_thresh;
2022 uint16_t i, base, bsf, tc_mapping;
2024 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2025 struct i40e_vf *vf =
2026 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2029 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2032 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2033 "exceeds the maximum", queue_idx);
2034 return I40E_ERR_PARAM;
2037 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2038 (nb_desc > I40E_MAX_RING_DESC) ||
2039 (nb_desc < I40E_MIN_RING_DESC)) {
2040 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2041 "invalid", nb_desc);
2042 return I40E_ERR_PARAM;
2046 * The following two parameters control the setting of the RS bit on
2047 * transmit descriptors. TX descriptors will have their RS bit set
2048 * after txq->tx_rs_thresh descriptors have been used. The TX
2049 * descriptor ring will be cleaned after txq->tx_free_thresh
2050 * descriptors are used or if the number of descriptors required to
2051 * transmit a packet is greater than the number of free TX descriptors.
2053 * The following constraints must be satisfied:
2054 * - tx_rs_thresh must be greater than 0.
2055 * - tx_rs_thresh must be less than the size of the ring minus 2.
2056 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2057 * - tx_rs_thresh must be a divisor of the ring size.
2058 * - tx_free_thresh must be greater than 0.
2059 * - tx_free_thresh must be less than the size of the ring minus 3.
2061 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2062 * race condition, hence the maximum threshold constraints. When set
2063 * to zero use default values.
2065 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2066 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2067 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2068 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2069 if (tx_rs_thresh >= (nb_desc - 2)) {
2070 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2071 "number of TX descriptors minus 2. "
2072 "(tx_rs_thresh=%u port=%d queue=%d)",
2073 (unsigned int)tx_rs_thresh,
2074 (int)dev->data->port_id,
2076 return I40E_ERR_PARAM;
2078 if (tx_free_thresh >= (nb_desc - 3)) {
2079 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2080 "number of TX descriptors minus 3. "
2081 "(tx_free_thresh=%u port=%d queue=%d)",
2082 (unsigned int)tx_free_thresh,
2083 (int)dev->data->port_id,
2085 return I40E_ERR_PARAM;
2087 if (tx_rs_thresh > tx_free_thresh) {
2088 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2089 "equal to tx_free_thresh. (tx_free_thresh=%u"
2090 " tx_rs_thresh=%u port=%d queue=%d)",
2091 (unsigned int)tx_free_thresh,
2092 (unsigned int)tx_rs_thresh,
2093 (int)dev->data->port_id,
2095 return I40E_ERR_PARAM;
2097 if ((nb_desc % tx_rs_thresh) != 0) {
2098 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2099 "number of TX descriptors. (tx_rs_thresh=%u"
2100 " port=%d queue=%d)",
2101 (unsigned int)tx_rs_thresh,
2102 (int)dev->data->port_id,
2104 return I40E_ERR_PARAM;
2106 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2107 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2108 "tx_rs_thresh is greater than 1. "
2109 "(tx_rs_thresh=%u port=%d queue=%d)",
2110 (unsigned int)tx_rs_thresh,
2111 (int)dev->data->port_id,
2113 return I40E_ERR_PARAM;
2116 /* Free memory if needed. */
2117 if (dev->data->tx_queues[queue_idx]) {
2118 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2119 dev->data->tx_queues[queue_idx] = NULL;
2122 /* Allocate the TX queue data structure. */
2123 txq = rte_zmalloc_socket("i40e tx queue",
2124 sizeof(struct i40e_tx_queue),
2125 RTE_CACHE_LINE_SIZE,
2128 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2129 "tx queue structure");
2133 /* Allocate TX hardware ring descriptors. */
2134 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2135 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2136 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2137 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2139 i40e_dev_tx_queue_release(txq);
2140 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2144 txq->nb_tx_desc = nb_desc;
2145 txq->tx_rs_thresh = tx_rs_thresh;
2146 txq->tx_free_thresh = tx_free_thresh;
2147 txq->pthresh = tx_conf->tx_thresh.pthresh;
2148 txq->hthresh = tx_conf->tx_thresh.hthresh;
2149 txq->wthresh = tx_conf->tx_thresh.wthresh;
2150 txq->queue_id = queue_idx;
2151 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2152 txq->reg_idx = queue_idx;
2153 else /* PF device */
2154 txq->reg_idx = vsi->base_queue +
2155 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2157 txq->port_id = dev->data->port_id;
2158 txq->txq_flags = tx_conf->txq_flags;
2160 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2162 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2163 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2165 /* Allocate software ring */
2167 rte_zmalloc_socket("i40e tx sw ring",
2168 sizeof(struct i40e_tx_entry) * nb_desc,
2169 RTE_CACHE_LINE_SIZE,
2171 if (!txq->sw_ring) {
2172 i40e_dev_tx_queue_release(txq);
2173 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2177 i40e_reset_tx_queue(txq);
2179 dev->data->tx_queues[queue_idx] = txq;
2181 /* Use a simple TX queue without offloads or multi segs if possible */
2182 i40e_set_tx_function_flag(dev, txq);
2184 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2185 if (!(vsi->enabled_tc & (1 << i)))
2187 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2188 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2189 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2190 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2191 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2193 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2201 i40e_dev_tx_queue_release(void *txq)
2203 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2206 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2210 i40e_tx_queue_release_mbufs(q);
2211 rte_free(q->sw_ring);
2215 const struct rte_memzone *
2216 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2218 const struct rte_memzone *mz;
2220 mz = rte_memzone_lookup(name);
2224 if (rte_xen_dom0_supported())
2225 mz = rte_memzone_reserve_bounded(name, len,
2226 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2228 mz = rte_memzone_reserve_aligned(name, len,
2229 socket_id, 0, I40E_RING_BASE_ALIGN);
2234 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2238 /* SSE Vector driver has a different way of releasing mbufs. */
2239 if (rxq->rx_using_sse) {
2240 i40e_rx_queue_release_mbufs_vec(rxq);
2244 if (!rxq->sw_ring) {
2245 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2249 for (i = 0; i < rxq->nb_rx_desc; i++) {
2250 if (rxq->sw_ring[i].mbuf) {
2251 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2252 rxq->sw_ring[i].mbuf = NULL;
2255 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2256 if (rxq->rx_nb_avail == 0)
2258 for (i = 0; i < rxq->rx_nb_avail; i++) {
2259 struct rte_mbuf *mbuf;
2261 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2262 rte_pktmbuf_free_seg(mbuf);
2264 rxq->rx_nb_avail = 0;
2265 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2269 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2275 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2279 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2280 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2281 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2283 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2284 len = rxq->nb_rx_desc;
2286 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2287 ((volatile char *)rxq->rx_ring)[i] = 0;
2289 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2290 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2291 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2293 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2294 rxq->rx_nb_avail = 0;
2295 rxq->rx_next_avail = 0;
2296 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2297 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2299 rxq->nb_rx_hold = 0;
2300 rxq->pkt_first_seg = NULL;
2301 rxq->pkt_last_seg = NULL;
2303 rxq->rxrearm_start = 0;
2304 rxq->rxrearm_nb = 0;
2308 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2312 if (!txq || !txq->sw_ring) {
2313 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2317 for (i = 0; i < txq->nb_tx_desc; i++) {
2318 if (txq->sw_ring[i].mbuf) {
2319 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2320 txq->sw_ring[i].mbuf = NULL;
2326 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2328 struct i40e_tx_entry *txe;
2329 uint16_t i, prev, size;
2332 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2337 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2338 for (i = 0; i < size; i++)
2339 ((volatile char *)txq->tx_ring)[i] = 0;
2341 prev = (uint16_t)(txq->nb_tx_desc - 1);
2342 for (i = 0; i < txq->nb_tx_desc; i++) {
2343 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2345 txd->cmd_type_offset_bsz =
2346 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2349 txe[prev].next_id = i;
2353 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2354 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2357 txq->nb_tx_used = 0;
2359 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2360 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2363 /* Init the TX queue in hardware */
2365 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2367 enum i40e_status_code err = I40E_SUCCESS;
2368 struct i40e_vsi *vsi = txq->vsi;
2369 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2370 uint16_t pf_q = txq->reg_idx;
2371 struct i40e_hmc_obj_txq tx_ctx;
2374 /* clear the context structure first */
2375 memset(&tx_ctx, 0, sizeof(tx_ctx));
2376 tx_ctx.new_context = 1;
2377 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2378 tx_ctx.qlen = txq->nb_tx_desc;
2380 #ifdef RTE_LIBRTE_IEEE1588
2381 tx_ctx.timesync_ena = 1;
2383 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2384 if (vsi->type == I40E_VSI_FDIR)
2385 tx_ctx.fd_ena = TRUE;
2387 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2388 if (err != I40E_SUCCESS) {
2389 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2393 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2394 if (err != I40E_SUCCESS) {
2395 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2399 /* Now associate this queue with this PCI function */
2400 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2401 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2402 I40E_QTX_CTL_PF_INDX_MASK);
2403 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2404 I40E_WRITE_FLUSH(hw);
2406 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2412 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2414 struct i40e_rx_entry *rxe = rxq->sw_ring;
2418 for (i = 0; i < rxq->nb_rx_desc; i++) {
2419 volatile union i40e_rx_desc *rxd;
2420 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2422 if (unlikely(!mbuf)) {
2423 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2427 rte_mbuf_refcnt_set(mbuf, 1);
2429 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2431 mbuf->port = rxq->port_id;
2434 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2436 rxd = &rxq->rx_ring[i];
2437 rxd->read.pkt_addr = dma_addr;
2438 rxd->read.hdr_addr = 0;
2439 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2440 rxd->read.rsvd1 = 0;
2441 rxd->read.rsvd2 = 0;
2442 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2451 * Calculate the buffer length, and check the jumbo frame
2452 * and maximum packet length.
2455 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2457 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2458 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2459 struct rte_eth_dev_data *data = pf->dev_data;
2460 uint16_t buf_size, len;
2462 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2463 RTE_PKTMBUF_HEADROOM);
2465 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2466 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2467 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2468 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2469 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2470 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2471 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2472 rxq->hs_mode = i40e_header_split_enabled;
2474 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2476 rxq->rx_hdr_len = 0;
2477 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2478 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2479 rxq->hs_mode = i40e_header_split_none;
2483 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2484 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2485 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2486 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2487 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2488 PMD_DRV_LOG(ERR, "maximum packet length must "
2489 "be larger than %u and smaller than %u,"
2490 "as jumbo frame is enabled",
2491 (uint32_t)ETHER_MAX_LEN,
2492 (uint32_t)I40E_FRAME_SIZE_MAX);
2493 return I40E_ERR_CONFIG;
2496 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2497 rxq->max_pkt_len > ETHER_MAX_LEN) {
2498 PMD_DRV_LOG(ERR, "maximum packet length must be "
2499 "larger than %u and smaller than %u, "
2500 "as jumbo frame is disabled",
2501 (uint32_t)ETHER_MIN_LEN,
2502 (uint32_t)ETHER_MAX_LEN);
2503 return I40E_ERR_CONFIG;
2510 /* Init the RX queue in hardware */
2512 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2514 int err = I40E_SUCCESS;
2515 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2516 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2517 uint16_t pf_q = rxq->reg_idx;
2519 struct i40e_hmc_obj_rxq rx_ctx;
2521 err = i40e_rx_queue_config(rxq);
2523 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2527 /* Clear the context structure first */
2528 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2529 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2530 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2532 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2533 rx_ctx.qlen = rxq->nb_rx_desc;
2534 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2537 rx_ctx.dtype = rxq->hs_mode;
2539 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2541 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2542 rx_ctx.rxmax = rxq->max_pkt_len;
2543 rx_ctx.tphrdesc_ena = 1;
2544 rx_ctx.tphwdesc_ena = 1;
2545 rx_ctx.tphdata_ena = 1;
2546 rx_ctx.tphhead_ena = 1;
2547 rx_ctx.lrxqthresh = 2;
2548 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2550 /* showiv indicates if inner VLAN is stripped inside of tunnel
2551 * packet. When set it to 1, vlan information is stripped from
2552 * the inner header, but the hardware does not put it in the
2553 * descriptor. So set it zero by default.
2558 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2559 if (err != I40E_SUCCESS) {
2560 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2563 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2564 if (err != I40E_SUCCESS) {
2565 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2569 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2571 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2572 RTE_PKTMBUF_HEADROOM);
2574 /* Check if scattered RX needs to be used. */
2575 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2576 dev_data->scattered_rx = 1;
2579 /* Init the RX tail regieter. */
2580 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2586 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2590 PMD_INIT_FUNC_TRACE();
2592 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2593 if (!dev->data->tx_queues[i])
2595 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2596 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2599 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2600 if (!dev->data->rx_queues[i])
2602 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2603 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2608 i40e_dev_free_queues(struct rte_eth_dev *dev)
2612 PMD_INIT_FUNC_TRACE();
2614 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2615 if (!dev->data->rx_queues[i])
2617 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2618 dev->data->rx_queues[i] = NULL;
2620 dev->data->nb_rx_queues = 0;
2622 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2623 if (!dev->data->tx_queues[i])
2625 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2626 dev->data->tx_queues[i] = NULL;
2628 dev->data->nb_tx_queues = 0;
2631 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2632 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2634 enum i40e_status_code
2635 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2637 struct i40e_tx_queue *txq;
2638 const struct rte_memzone *tz = NULL;
2640 struct rte_eth_dev *dev;
2643 PMD_DRV_LOG(ERR, "PF is not available");
2644 return I40E_ERR_BAD_PTR;
2647 dev = pf->adapter->eth_dev;
2649 /* Allocate the TX queue data structure. */
2650 txq = rte_zmalloc_socket("i40e fdir tx queue",
2651 sizeof(struct i40e_tx_queue),
2652 RTE_CACHE_LINE_SIZE,
2655 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2656 "tx queue structure.");
2657 return I40E_ERR_NO_MEMORY;
2660 /* Allocate TX hardware ring descriptors. */
2661 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2662 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2664 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2665 I40E_FDIR_QUEUE_ID, ring_size,
2666 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2668 i40e_dev_tx_queue_release(txq);
2669 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2670 return I40E_ERR_NO_MEMORY;
2673 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2674 txq->queue_id = I40E_FDIR_QUEUE_ID;
2675 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2676 txq->vsi = pf->fdir.fdir_vsi;
2678 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2679 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2681 * don't need to allocate software ring and reset for the fdir
2682 * program queue just set the queue has been configured.
2687 return I40E_SUCCESS;
2690 enum i40e_status_code
2691 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2693 struct i40e_rx_queue *rxq;
2694 const struct rte_memzone *rz = NULL;
2696 struct rte_eth_dev *dev;
2699 PMD_DRV_LOG(ERR, "PF is not available");
2700 return I40E_ERR_BAD_PTR;
2703 dev = pf->adapter->eth_dev;
2705 /* Allocate the RX queue data structure. */
2706 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2707 sizeof(struct i40e_rx_queue),
2708 RTE_CACHE_LINE_SIZE,
2711 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2712 "rx queue structure.");
2713 return I40E_ERR_NO_MEMORY;
2716 /* Allocate RX hardware ring descriptors. */
2717 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2718 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2720 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2721 I40E_FDIR_QUEUE_ID, ring_size,
2722 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2724 i40e_dev_rx_queue_release(rxq);
2725 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2726 return I40E_ERR_NO_MEMORY;
2729 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2730 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2731 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2732 rxq->vsi = pf->fdir.fdir_vsi;
2734 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2735 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2738 * Don't need to allocate software ring and reset for the fdir
2739 * rx queue, just set the queue has been configured.
2744 return I40E_SUCCESS;
2748 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2749 struct rte_eth_rxq_info *qinfo)
2751 struct i40e_rx_queue *rxq;
2753 rxq = dev->data->rx_queues[queue_id];
2755 qinfo->mp = rxq->mp;
2756 qinfo->scattered_rx = dev->data->scattered_rx;
2757 qinfo->nb_desc = rxq->nb_rx_desc;
2759 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2760 qinfo->conf.rx_drop_en = rxq->drop_en;
2761 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2765 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2766 struct rte_eth_txq_info *qinfo)
2768 struct i40e_tx_queue *txq;
2770 txq = dev->data->tx_queues[queue_id];
2772 qinfo->nb_desc = txq->nb_tx_desc;
2774 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2775 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2776 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2778 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2779 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2780 qinfo->conf.txq_flags = txq->txq_flags;
2781 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2784 void __attribute__((cold))
2785 i40e_set_rx_function(struct rte_eth_dev *dev)
2787 struct i40e_adapter *ad =
2788 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2789 uint16_t rx_using_sse, i;
2790 /* In order to allow Vector Rx there are a few configuration
2791 * conditions to be met and Rx Bulk Allocation should be allowed.
2793 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2794 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2795 !ad->rx_bulk_alloc_allowed) {
2796 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2797 " Vector Rx preconditions",
2798 dev->data->port_id);
2800 ad->rx_vec_allowed = false;
2802 if (ad->rx_vec_allowed) {
2803 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2804 struct i40e_rx_queue *rxq =
2805 dev->data->rx_queues[i];
2807 if (rxq && i40e_rxq_vec_setup(rxq)) {
2808 ad->rx_vec_allowed = false;
2815 if (dev->data->scattered_rx) {
2816 /* Set the non-LRO scattered callback: there are Vector and
2817 * single allocation versions.
2819 if (ad->rx_vec_allowed) {
2820 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2821 "callback (port=%d).",
2822 dev->data->port_id);
2824 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2826 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2827 "allocation callback (port=%d).",
2828 dev->data->port_id);
2829 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2831 /* If parameters allow we are going to choose between the following
2835 * - Single buffer allocation (the simplest one)
2837 } else if (ad->rx_vec_allowed) {
2838 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2839 "burst size no less than %d (port=%d).",
2840 RTE_I40E_DESCS_PER_LOOP,
2841 dev->data->port_id);
2843 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2844 } else if (ad->rx_bulk_alloc_allowed) {
2845 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2846 "satisfied. Rx Burst Bulk Alloc function "
2847 "will be used on port=%d.",
2848 dev->data->port_id);
2850 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2852 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2853 "satisfied, or Scattered Rx is requested "
2855 dev->data->port_id);
2857 dev->rx_pkt_burst = i40e_recv_pkts;
2860 /* Propagate information about RX function choice through all queues. */
2861 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2863 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2864 dev->rx_pkt_burst == i40e_recv_pkts_vec);
2866 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2867 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2870 rxq->rx_using_sse = rx_using_sse;
2875 void __attribute__((cold))
2876 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2878 struct i40e_adapter *ad =
2879 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2881 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2882 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2883 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2884 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2885 PMD_INIT_LOG(DEBUG, "Vector tx"
2886 " can be enabled on this txq.");
2889 ad->tx_vec_allowed = false;
2892 ad->tx_simple_allowed = false;
2896 void __attribute__((cold))
2897 i40e_set_tx_function(struct rte_eth_dev *dev)
2899 struct i40e_adapter *ad =
2900 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2903 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2904 if (ad->tx_vec_allowed) {
2905 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2906 struct i40e_tx_queue *txq =
2907 dev->data->tx_queues[i];
2909 if (txq && i40e_txq_vec_setup(txq)) {
2910 ad->tx_vec_allowed = false;
2917 if (ad->tx_simple_allowed) {
2918 if (ad->tx_vec_allowed) {
2919 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2920 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2922 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2923 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2925 dev->tx_pkt_prepare = NULL;
2927 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2928 dev->tx_pkt_burst = i40e_xmit_pkts;
2929 dev->tx_pkt_prepare = i40e_prep_pkts;
2933 void __attribute__((cold))
2934 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
2936 struct i40e_adapter *ad =
2937 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2940 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
2941 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
2944 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2945 int __attribute__((weak))
2946 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2951 uint16_t __attribute__((weak))
2953 void __rte_unused *rx_queue,
2954 struct rte_mbuf __rte_unused **rx_pkts,
2955 uint16_t __rte_unused nb_pkts)
2960 uint16_t __attribute__((weak))
2961 i40e_recv_scattered_pkts_vec(
2962 void __rte_unused *rx_queue,
2963 struct rte_mbuf __rte_unused **rx_pkts,
2964 uint16_t __rte_unused nb_pkts)
2969 int __attribute__((weak))
2970 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2975 int __attribute__((weak))
2976 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2981 void __attribute__((weak))
2982 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2987 uint16_t __attribute__((weak))
2988 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
2989 struct rte_mbuf __rte_unused **tx_pkts,
2990 uint16_t __rte_unused nb_pkts)