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42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define DEFAULT_TX_RS_THRESH 32
61 #define DEFAULT_TX_FREE_THRESH 32
62 #define I40E_MAX_PKT_TYPE 256
64 #define I40E_TX_MAX_BURST 32
66 #define I40E_DMA_MEM_ALIGN 4096
68 /* Base address of the HW descriptor ring should be 128B aligned. */
69 #define I40E_RING_BASE_ALIGN 128
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
79 PKT_TX_OUTER_IP_CKSUM)
81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
82 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
85 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
87 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
88 struct rte_mbuf **tx_pkts,
92 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
94 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
95 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
96 mb->ol_flags |= PKT_RX_VLAN_PKT;
98 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
99 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
100 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
104 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
105 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
106 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
107 mb->ol_flags |= PKT_RX_QINQ_PKT;
108 mb->vlan_tci_outer = mb->vlan_tci;
109 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
110 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
111 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
112 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
114 mb->vlan_tci_outer = 0;
117 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
118 mb->vlan_tci, mb->vlan_tci_outer);
121 /* Translate the rx descriptor status to pkt flags */
122 static inline uint64_t
123 i40e_rxd_status_to_pkt_flags(uint64_t qword)
127 /* Check if RSS_HASH */
128 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
129 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
130 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
132 /* Check if FDIR Match */
133 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
139 static inline uint64_t
140 i40e_rxd_error_to_pkt_flags(uint64_t qword)
143 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
145 #define I40E_RX_ERR_BITS 0x3f
146 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
148 /* If RXE bit set, all other status bits are meaningless */
149 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
150 flags |= PKT_RX_MAC_ERR;
154 /* If RECIPE bit set, all other status indications should be ignored */
155 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
156 flags |= PKT_RX_RECIP_ERR;
159 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
160 flags |= PKT_RX_HBUF_OVERFLOW;
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
162 flags |= PKT_RX_IP_CKSUM_BAD;
163 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
164 flags |= PKT_RX_L4_CKSUM_BAD;
165 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
166 flags |= PKT_RX_EIP_CKSUM_BAD;
167 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
168 flags |= PKT_RX_OVERSIZE;
173 /* Function to check and set the ieee1588 timesync index and get the
176 #ifdef RTE_LIBRTE_IEEE1588
177 static inline uint64_t
178 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
180 uint64_t pkt_flags = 0;
181 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
182 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
183 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
185 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
186 == RTE_PTYPE_L2_ETHER_TIMESYNC)
187 pkt_flags = PKT_RX_IEEE1588_PTP;
189 pkt_flags |= PKT_RX_IEEE1588_TMST;
190 mb->timesync = tsyn & 0x03;
197 /* For each value it means, datasheet of hardware can tell more details */
198 static inline uint32_t
199 i40e_rxd_pkt_type_mapping(uint8_t ptype)
201 static const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {
204 [1] = RTE_PTYPE_L2_ETHER,
205 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
206 /* [3] - [5] reserved */
207 [6] = RTE_PTYPE_L2_ETHER_LLDP,
208 /* [7] - [10] reserved */
209 [11] = RTE_PTYPE_L2_ETHER_ARP,
210 /* [12] - [21] reserved */
212 /* Non tunneled IPv4 */
213 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
215 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
216 RTE_PTYPE_L4_NONFRAG,
217 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
220 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
222 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
228 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
229 RTE_PTYPE_TUNNEL_IP |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_FRAG,
232 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_TUNNEL_IP |
234 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_NONFRAG,
236 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_TUNNEL_IP |
238 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L4_UDP,
241 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_TUNNEL_IP |
243 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L4_TCP,
245 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_TUNNEL_IP |
247 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L4_SCTP,
249 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
250 RTE_PTYPE_TUNNEL_IP |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_ICMP,
255 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_TUNNEL_IP |
257 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_FRAG,
259 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
260 RTE_PTYPE_TUNNEL_IP |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_NONFRAG,
263 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_TUNNEL_IP |
265 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
266 RTE_PTYPE_INNER_L4_UDP,
268 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
269 RTE_PTYPE_TUNNEL_IP |
270 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_TCP,
272 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
273 RTE_PTYPE_TUNNEL_IP |
274 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L4_SCTP,
276 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_TUNNEL_IP |
278 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
279 RTE_PTYPE_INNER_L4_ICMP,
281 /* IPv4 --> GRE/Teredo/VXLAN */
282 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_TUNNEL_GRENAT,
285 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
286 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
287 RTE_PTYPE_TUNNEL_GRENAT |
288 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
289 RTE_PTYPE_INNER_L4_FRAG,
290 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
291 RTE_PTYPE_TUNNEL_GRENAT |
292 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
293 RTE_PTYPE_INNER_L4_NONFRAG,
294 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
295 RTE_PTYPE_TUNNEL_GRENAT |
296 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
297 RTE_PTYPE_INNER_L4_UDP,
299 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
300 RTE_PTYPE_TUNNEL_GRENAT |
301 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
302 RTE_PTYPE_INNER_L4_TCP,
303 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
304 RTE_PTYPE_TUNNEL_GRENAT |
305 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
306 RTE_PTYPE_INNER_L4_SCTP,
307 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
308 RTE_PTYPE_TUNNEL_GRENAT |
309 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
310 RTE_PTYPE_INNER_L4_ICMP,
312 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
313 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_TUNNEL_GRENAT |
315 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
316 RTE_PTYPE_INNER_L4_FRAG,
317 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
318 RTE_PTYPE_TUNNEL_GRENAT |
319 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
320 RTE_PTYPE_INNER_L4_NONFRAG,
321 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
322 RTE_PTYPE_TUNNEL_GRENAT |
323 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
324 RTE_PTYPE_INNER_L4_UDP,
326 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
327 RTE_PTYPE_TUNNEL_GRENAT |
328 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
329 RTE_PTYPE_INNER_L4_TCP,
330 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
331 RTE_PTYPE_TUNNEL_GRENAT |
332 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
333 RTE_PTYPE_INNER_L4_SCTP,
334 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
335 RTE_PTYPE_TUNNEL_GRENAT |
336 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
337 RTE_PTYPE_INNER_L4_ICMP,
339 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
340 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
341 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
343 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
344 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
345 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
346 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
347 RTE_PTYPE_INNER_L4_FRAG,
348 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
349 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
350 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
351 RTE_PTYPE_INNER_L4_NONFRAG,
352 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
353 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
354 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
355 RTE_PTYPE_INNER_L4_UDP,
357 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
358 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
359 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
360 RTE_PTYPE_INNER_L4_TCP,
361 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
362 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
363 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
364 RTE_PTYPE_INNER_L4_SCTP,
365 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
366 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
367 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
368 RTE_PTYPE_INNER_L4_ICMP,
370 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
371 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
372 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
373 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
374 RTE_PTYPE_INNER_L4_FRAG,
375 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
376 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
377 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
378 RTE_PTYPE_INNER_L4_NONFRAG,
379 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
380 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
381 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
382 RTE_PTYPE_INNER_L4_UDP,
384 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
385 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
386 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
387 RTE_PTYPE_INNER_L4_TCP,
388 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
389 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
390 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
391 RTE_PTYPE_INNER_L4_SCTP,
392 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
393 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
394 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
395 RTE_PTYPE_INNER_L4_ICMP,
397 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
398 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
399 RTE_PTYPE_TUNNEL_GRENAT |
400 RTE_PTYPE_INNER_L2_ETHER_VLAN,
402 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
403 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
404 RTE_PTYPE_TUNNEL_GRENAT |
405 RTE_PTYPE_INNER_L2_ETHER_VLAN |
406 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
407 RTE_PTYPE_INNER_L4_FRAG,
408 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
409 RTE_PTYPE_TUNNEL_GRENAT |
410 RTE_PTYPE_INNER_L2_ETHER_VLAN |
411 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
412 RTE_PTYPE_INNER_L4_NONFRAG,
413 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
414 RTE_PTYPE_TUNNEL_GRENAT |
415 RTE_PTYPE_INNER_L2_ETHER_VLAN |
416 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
417 RTE_PTYPE_INNER_L4_UDP,
419 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
420 RTE_PTYPE_TUNNEL_GRENAT |
421 RTE_PTYPE_INNER_L2_ETHER_VLAN |
422 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
423 RTE_PTYPE_INNER_L4_TCP,
424 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
425 RTE_PTYPE_TUNNEL_GRENAT |
426 RTE_PTYPE_INNER_L2_ETHER_VLAN |
427 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
428 RTE_PTYPE_INNER_L4_SCTP,
429 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
430 RTE_PTYPE_TUNNEL_GRENAT |
431 RTE_PTYPE_INNER_L2_ETHER_VLAN |
432 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
433 RTE_PTYPE_INNER_L4_ICMP,
435 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
436 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
437 RTE_PTYPE_TUNNEL_GRENAT |
438 RTE_PTYPE_INNER_L2_ETHER_VLAN |
439 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
440 RTE_PTYPE_INNER_L4_FRAG,
441 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
442 RTE_PTYPE_TUNNEL_GRENAT |
443 RTE_PTYPE_INNER_L2_ETHER_VLAN |
444 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
445 RTE_PTYPE_INNER_L4_NONFRAG,
446 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
447 RTE_PTYPE_TUNNEL_GRENAT |
448 RTE_PTYPE_INNER_L2_ETHER_VLAN |
449 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
450 RTE_PTYPE_INNER_L4_UDP,
452 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
453 RTE_PTYPE_TUNNEL_GRENAT |
454 RTE_PTYPE_INNER_L2_ETHER_VLAN |
455 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
456 RTE_PTYPE_INNER_L4_TCP,
457 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
458 RTE_PTYPE_TUNNEL_GRENAT |
459 RTE_PTYPE_INNER_L2_ETHER_VLAN |
460 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
461 RTE_PTYPE_INNER_L4_SCTP,
462 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
463 RTE_PTYPE_TUNNEL_GRENAT |
464 RTE_PTYPE_INNER_L2_ETHER_VLAN |
465 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
466 RTE_PTYPE_INNER_L4_ICMP,
468 /* Non tunneled IPv6 */
469 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
471 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
472 RTE_PTYPE_L4_NONFRAG,
473 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
476 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
478 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
480 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
484 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
485 RTE_PTYPE_TUNNEL_IP |
486 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
487 RTE_PTYPE_INNER_L4_FRAG,
488 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
489 RTE_PTYPE_TUNNEL_IP |
490 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
491 RTE_PTYPE_INNER_L4_NONFRAG,
492 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
493 RTE_PTYPE_TUNNEL_IP |
494 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
495 RTE_PTYPE_INNER_L4_UDP,
497 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
498 RTE_PTYPE_TUNNEL_IP |
499 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
500 RTE_PTYPE_INNER_L4_TCP,
501 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
502 RTE_PTYPE_TUNNEL_IP |
503 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
504 RTE_PTYPE_INNER_L4_SCTP,
505 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
506 RTE_PTYPE_TUNNEL_IP |
507 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
508 RTE_PTYPE_INNER_L4_ICMP,
511 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
512 RTE_PTYPE_TUNNEL_IP |
513 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
514 RTE_PTYPE_INNER_L4_FRAG,
515 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
516 RTE_PTYPE_TUNNEL_IP |
517 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
518 RTE_PTYPE_INNER_L4_NONFRAG,
519 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
520 RTE_PTYPE_TUNNEL_IP |
521 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
522 RTE_PTYPE_INNER_L4_UDP,
524 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
525 RTE_PTYPE_TUNNEL_IP |
526 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
527 RTE_PTYPE_INNER_L4_TCP,
528 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
529 RTE_PTYPE_TUNNEL_IP |
530 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
531 RTE_PTYPE_INNER_L4_SCTP,
532 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
533 RTE_PTYPE_TUNNEL_IP |
534 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
535 RTE_PTYPE_INNER_L4_ICMP,
537 /* IPv6 --> GRE/Teredo/VXLAN */
538 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
539 RTE_PTYPE_TUNNEL_GRENAT,
541 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
542 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
543 RTE_PTYPE_TUNNEL_GRENAT |
544 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
545 RTE_PTYPE_INNER_L4_FRAG,
546 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
547 RTE_PTYPE_TUNNEL_GRENAT |
548 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
549 RTE_PTYPE_INNER_L4_NONFRAG,
550 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
551 RTE_PTYPE_TUNNEL_GRENAT |
552 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
553 RTE_PTYPE_INNER_L4_UDP,
555 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
556 RTE_PTYPE_TUNNEL_GRENAT |
557 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
558 RTE_PTYPE_INNER_L4_TCP,
559 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
560 RTE_PTYPE_TUNNEL_GRENAT |
561 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
562 RTE_PTYPE_INNER_L4_SCTP,
563 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
564 RTE_PTYPE_TUNNEL_GRENAT |
565 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
566 RTE_PTYPE_INNER_L4_ICMP,
568 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
569 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
570 RTE_PTYPE_TUNNEL_GRENAT |
571 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
572 RTE_PTYPE_INNER_L4_FRAG,
573 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
574 RTE_PTYPE_TUNNEL_GRENAT |
575 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
576 RTE_PTYPE_INNER_L4_NONFRAG,
577 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
578 RTE_PTYPE_TUNNEL_GRENAT |
579 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
580 RTE_PTYPE_INNER_L4_UDP,
582 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
583 RTE_PTYPE_TUNNEL_GRENAT |
584 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
585 RTE_PTYPE_INNER_L4_TCP,
586 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
587 RTE_PTYPE_TUNNEL_GRENAT |
588 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
589 RTE_PTYPE_INNER_L4_SCTP,
590 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
591 RTE_PTYPE_TUNNEL_GRENAT |
592 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
593 RTE_PTYPE_INNER_L4_ICMP,
595 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
596 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
597 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
599 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
600 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
601 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
602 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
603 RTE_PTYPE_INNER_L4_FRAG,
604 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
605 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
606 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
607 RTE_PTYPE_INNER_L4_NONFRAG,
608 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
609 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
610 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
611 RTE_PTYPE_INNER_L4_UDP,
613 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
614 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
615 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
616 RTE_PTYPE_INNER_L4_TCP,
617 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
618 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
619 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
620 RTE_PTYPE_INNER_L4_SCTP,
621 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
622 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
623 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
624 RTE_PTYPE_INNER_L4_ICMP,
626 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
627 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
628 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
629 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
630 RTE_PTYPE_INNER_L4_FRAG,
631 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
632 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
633 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
634 RTE_PTYPE_INNER_L4_NONFRAG,
635 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
636 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
637 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
638 RTE_PTYPE_INNER_L4_UDP,
640 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
641 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
642 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
643 RTE_PTYPE_INNER_L4_TCP,
644 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
645 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
646 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
647 RTE_PTYPE_INNER_L4_SCTP,
648 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
649 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
650 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
651 RTE_PTYPE_INNER_L4_ICMP,
653 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
654 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
655 RTE_PTYPE_TUNNEL_GRENAT |
656 RTE_PTYPE_INNER_L2_ETHER_VLAN,
658 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
659 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
660 RTE_PTYPE_TUNNEL_GRENAT |
661 RTE_PTYPE_INNER_L2_ETHER_VLAN |
662 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
663 RTE_PTYPE_INNER_L4_FRAG,
664 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
665 RTE_PTYPE_TUNNEL_GRENAT |
666 RTE_PTYPE_INNER_L2_ETHER_VLAN |
667 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
668 RTE_PTYPE_INNER_L4_NONFRAG,
669 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
670 RTE_PTYPE_TUNNEL_GRENAT |
671 RTE_PTYPE_INNER_L2_ETHER_VLAN |
672 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
673 RTE_PTYPE_INNER_L4_UDP,
675 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
676 RTE_PTYPE_TUNNEL_GRENAT |
677 RTE_PTYPE_INNER_L2_ETHER_VLAN |
678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
679 RTE_PTYPE_INNER_L4_TCP,
680 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
681 RTE_PTYPE_TUNNEL_GRENAT |
682 RTE_PTYPE_INNER_L2_ETHER_VLAN |
683 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
684 RTE_PTYPE_INNER_L4_SCTP,
685 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
686 RTE_PTYPE_TUNNEL_GRENAT |
687 RTE_PTYPE_INNER_L2_ETHER_VLAN |
688 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
689 RTE_PTYPE_INNER_L4_ICMP,
691 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
692 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
693 RTE_PTYPE_TUNNEL_GRENAT |
694 RTE_PTYPE_INNER_L2_ETHER_VLAN |
695 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
696 RTE_PTYPE_INNER_L4_FRAG,
697 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
698 RTE_PTYPE_TUNNEL_GRENAT |
699 RTE_PTYPE_INNER_L2_ETHER_VLAN |
700 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
701 RTE_PTYPE_INNER_L4_NONFRAG,
702 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
703 RTE_PTYPE_TUNNEL_GRENAT |
704 RTE_PTYPE_INNER_L2_ETHER_VLAN |
705 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
706 RTE_PTYPE_INNER_L4_UDP,
708 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
709 RTE_PTYPE_TUNNEL_GRENAT |
710 RTE_PTYPE_INNER_L2_ETHER_VLAN |
711 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
712 RTE_PTYPE_INNER_L4_TCP,
713 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
714 RTE_PTYPE_TUNNEL_GRENAT |
715 RTE_PTYPE_INNER_L2_ETHER_VLAN |
716 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
717 RTE_PTYPE_INNER_L4_SCTP,
718 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
719 RTE_PTYPE_TUNNEL_GRENAT |
720 RTE_PTYPE_INNER_L2_ETHER_VLAN |
721 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
722 RTE_PTYPE_INNER_L4_ICMP,
724 /* All others reserved */
727 return ptype_table[ptype];
730 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
731 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
732 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
733 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
734 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
736 static inline uint64_t
737 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
740 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
741 uint16_t flexbh, flexbl;
743 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
744 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
745 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
746 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
747 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
748 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
751 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
753 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
754 flags |= PKT_RX_FDIR_ID;
755 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
757 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
758 flags |= PKT_RX_FDIR_FLX;
760 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
762 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
763 flags |= PKT_RX_FDIR_FLX;
767 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
768 flags |= PKT_RX_FDIR_ID;
773 i40e_txd_enable_checksum(uint64_t ol_flags,
776 union i40e_tx_offload tx_offload,
777 uint32_t *cd_tunneling)
779 /* UDP tunneling packet TX checksum offload */
780 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
782 *td_offset |= (tx_offload.outer_l2_len >> 1)
783 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
785 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
786 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
787 else if (ol_flags & PKT_TX_OUTER_IPV4)
788 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
789 else if (ol_flags & PKT_TX_OUTER_IPV6)
790 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
792 /* Now set the ctx descriptor fields */
793 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
794 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
795 (tx_offload.l2_len >> 1) <<
796 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
799 *td_offset |= (tx_offload.l2_len >> 1)
800 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
802 /* Enable L3 checksum offloads */
803 if (ol_flags & PKT_TX_IP_CKSUM) {
804 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
805 *td_offset |= (tx_offload.l3_len >> 2)
806 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
807 } else if (ol_flags & PKT_TX_IPV4) {
808 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
809 *td_offset |= (tx_offload.l3_len >> 2)
810 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
811 } else if (ol_flags & PKT_TX_IPV6) {
812 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
813 *td_offset |= (tx_offload.l3_len >> 2)
814 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
817 if (ol_flags & PKT_TX_TCP_SEG) {
818 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
819 *td_offset |= (tx_offload.l4_len >> 2)
820 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
824 /* Enable L4 checksum offloads */
825 switch (ol_flags & PKT_TX_L4_MASK) {
826 case PKT_TX_TCP_CKSUM:
827 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
828 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
829 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
831 case PKT_TX_SCTP_CKSUM:
832 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
833 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
834 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
836 case PKT_TX_UDP_CKSUM:
837 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
838 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
839 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
846 static inline struct rte_mbuf *
847 rte_rxmbuf_alloc(struct rte_mempool *mp)
851 m = __rte_mbuf_raw_alloc(mp);
852 __rte_mbuf_sanity_check_raw(m, 0);
857 /* Construct the tx flags */
858 static inline uint64_t
859 i40e_build_ctob(uint32_t td_cmd,
864 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
865 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
866 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
867 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
868 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
872 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
874 struct i40e_tx_entry *sw_ring = txq->sw_ring;
875 volatile struct i40e_tx_desc *txd = txq->tx_ring;
876 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
877 uint16_t nb_tx_desc = txq->nb_tx_desc;
878 uint16_t desc_to_clean_to;
879 uint16_t nb_tx_to_clean;
881 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
882 if (desc_to_clean_to >= nb_tx_desc)
883 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
885 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
886 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
887 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
888 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
889 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
890 "(port=%d queue=%d)", desc_to_clean_to,
891 txq->port_id, txq->queue_id);
895 if (last_desc_cleaned > desc_to_clean_to)
896 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
899 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
902 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
904 txq->last_desc_cleaned = desc_to_clean_to;
905 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
911 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
912 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
914 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
919 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
920 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
921 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
922 "rxq->rx_free_thresh=%d, "
923 "RTE_PMD_I40E_RX_MAX_BURST=%d",
924 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
926 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
927 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
928 "rxq->rx_free_thresh=%d, "
929 "rxq->nb_rx_desc=%d",
930 rxq->rx_free_thresh, rxq->nb_rx_desc);
932 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
933 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
934 "rxq->nb_rx_desc=%d, "
935 "rxq->rx_free_thresh=%d",
936 rxq->nb_rx_desc, rxq->rx_free_thresh);
938 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
939 RTE_PMD_I40E_RX_MAX_BURST))) {
940 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
941 "rxq->nb_rx_desc=%d, "
942 "I40E_MAX_RING_DESC=%d, "
943 "RTE_PMD_I40E_RX_MAX_BURST=%d",
944 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
945 RTE_PMD_I40E_RX_MAX_BURST);
955 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
956 #define I40E_LOOK_AHEAD 8
957 #if (I40E_LOOK_AHEAD != 8)
958 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
961 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
963 volatile union i40e_rx_desc *rxdp;
964 struct i40e_rx_entry *rxep;
969 int32_t s[I40E_LOOK_AHEAD], nb_dd;
970 int32_t i, j, nb_rx = 0;
973 rxdp = &rxq->rx_ring[rxq->rx_tail];
974 rxep = &rxq->sw_ring[rxq->rx_tail];
976 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
977 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
978 I40E_RXD_QW1_STATUS_SHIFT;
980 /* Make sure there is at least 1 packet to receive */
981 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
985 * Scan LOOK_AHEAD descriptors at a time to determine which
986 * descriptors reference packets that are ready to be received.
988 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
989 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
990 /* Read desc statuses backwards to avoid race condition */
991 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
992 qword1 = rte_le_to_cpu_64(\
993 rxdp[j].wb.qword1.status_error_len);
994 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
995 I40E_RXD_QW1_STATUS_SHIFT;
998 /* Compute how many status bits were set */
999 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1000 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1004 /* Translate descriptor info to mbuf parameters */
1005 for (j = 0; j < nb_dd; j++) {
1007 qword1 = rte_le_to_cpu_64(\
1008 rxdp[j].wb.qword1.status_error_len);
1009 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1010 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1011 mb->data_len = pkt_len;
1012 mb->pkt_len = pkt_len;
1014 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1015 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1016 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1018 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1019 I40E_RXD_QW1_PTYPE_MASK) >>
1020 I40E_RXD_QW1_PTYPE_SHIFT));
1021 if (pkt_flags & PKT_RX_RSS_HASH)
1022 mb->hash.rss = rte_le_to_cpu_32(\
1023 rxdp[j].wb.qword0.hi_dword.rss);
1024 if (pkt_flags & PKT_RX_FDIR)
1025 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1027 #ifdef RTE_LIBRTE_IEEE1588
1028 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1030 mb->ol_flags |= pkt_flags;
1034 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1035 rxq->rx_stage[i + j] = rxep[j].mbuf;
1037 if (nb_dd != I40E_LOOK_AHEAD)
1041 /* Clear software ring entries */
1042 for (i = 0; i < nb_rx; i++)
1043 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1048 static inline uint16_t
1049 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1050 struct rte_mbuf **rx_pkts,
1054 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1056 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1058 for (i = 0; i < nb_pkts; i++)
1059 rx_pkts[i] = stage[i];
1061 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1062 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1068 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1070 volatile union i40e_rx_desc *rxdp;
1071 struct i40e_rx_entry *rxep;
1072 struct rte_mbuf *mb;
1073 uint16_t alloc_idx, i;
1077 /* Allocate buffers in bulk */
1078 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1079 (rxq->rx_free_thresh - 1));
1080 rxep = &(rxq->sw_ring[alloc_idx]);
1081 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1082 rxq->rx_free_thresh);
1083 if (unlikely(diag != 0)) {
1084 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1088 rxdp = &rxq->rx_ring[alloc_idx];
1089 for (i = 0; i < rxq->rx_free_thresh; i++) {
1090 if (likely(i < (rxq->rx_free_thresh - 1)))
1091 /* Prefetch next mbuf */
1092 rte_prefetch0(rxep[i + 1].mbuf);
1095 rte_mbuf_refcnt_set(mb, 1);
1097 mb->data_off = RTE_PKTMBUF_HEADROOM;
1099 mb->port = rxq->port_id;
1100 dma_addr = rte_cpu_to_le_64(\
1101 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1102 rxdp[i].read.hdr_addr = 0;
1103 rxdp[i].read.pkt_addr = dma_addr;
1106 /* Update rx tail regsiter */
1108 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1110 rxq->rx_free_trigger =
1111 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1112 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1113 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1118 static inline uint16_t
1119 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1121 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1127 if (rxq->rx_nb_avail)
1128 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1130 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1131 rxq->rx_next_avail = 0;
1132 rxq->rx_nb_avail = nb_rx;
1133 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1135 if (rxq->rx_tail > rxq->rx_free_trigger) {
1136 if (i40e_rx_alloc_bufs(rxq) != 0) {
1139 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1140 "port_id=%u, queue_id=%u",
1141 rxq->port_id, rxq->queue_id);
1142 rxq->rx_nb_avail = 0;
1143 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1144 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1145 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1151 if (rxq->rx_tail >= rxq->nb_rx_desc)
1154 if (rxq->rx_nb_avail)
1155 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1161 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1162 struct rte_mbuf **rx_pkts,
1165 uint16_t nb_rx = 0, n, count;
1167 if (unlikely(nb_pkts == 0))
1170 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1171 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1174 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1175 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1176 nb_rx = (uint16_t)(nb_rx + count);
1177 nb_pkts = (uint16_t)(nb_pkts - count);
1184 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1187 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1189 struct i40e_rx_queue *rxq;
1190 volatile union i40e_rx_desc *rx_ring;
1191 volatile union i40e_rx_desc *rxdp;
1192 union i40e_rx_desc rxd;
1193 struct i40e_rx_entry *sw_ring;
1194 struct i40e_rx_entry *rxe;
1195 struct rte_mbuf *rxm;
1196 struct rte_mbuf *nmb;
1200 uint16_t rx_packet_len;
1201 uint16_t rx_id, nb_hold;
1208 rx_id = rxq->rx_tail;
1209 rx_ring = rxq->rx_ring;
1210 sw_ring = rxq->sw_ring;
1212 while (nb_rx < nb_pkts) {
1213 rxdp = &rx_ring[rx_id];
1214 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1215 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1216 >> I40E_RXD_QW1_STATUS_SHIFT;
1218 /* Check the DD bit first */
1219 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1222 nmb = rte_rxmbuf_alloc(rxq->mp);
1228 rxe = &sw_ring[rx_id];
1230 if (unlikely(rx_id == rxq->nb_rx_desc))
1233 /* Prefetch next mbuf */
1234 rte_prefetch0(sw_ring[rx_id].mbuf);
1237 * When next RX descriptor is on a cache line boundary,
1238 * prefetch the next 4 RX descriptors and next 8 pointers
1241 if ((rx_id & 0x3) == 0) {
1242 rte_prefetch0(&rx_ring[rx_id]);
1243 rte_prefetch0(&sw_ring[rx_id]);
1248 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1249 rxdp->read.hdr_addr = 0;
1250 rxdp->read.pkt_addr = dma_addr;
1252 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1253 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1255 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1256 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1259 rxm->pkt_len = rx_packet_len;
1260 rxm->data_len = rx_packet_len;
1261 rxm->port = rxq->port_id;
1263 i40e_rxd_to_vlan_tci(rxm, &rxd);
1264 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1265 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1267 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1268 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1269 if (pkt_flags & PKT_RX_RSS_HASH)
1271 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1272 if (pkt_flags & PKT_RX_FDIR)
1273 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1275 #ifdef RTE_LIBRTE_IEEE1588
1276 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1278 rxm->ol_flags |= pkt_flags;
1280 rx_pkts[nb_rx++] = rxm;
1282 rxq->rx_tail = rx_id;
1285 * If the number of free RX descriptors is greater than the RX free
1286 * threshold of the queue, advance the receive tail register of queue.
1287 * Update that register with the value of the last processed RX
1288 * descriptor minus 1.
1290 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1291 if (nb_hold > rxq->rx_free_thresh) {
1292 rx_id = (uint16_t) ((rx_id == 0) ?
1293 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1294 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1297 rxq->nb_rx_hold = nb_hold;
1303 i40e_recv_scattered_pkts(void *rx_queue,
1304 struct rte_mbuf **rx_pkts,
1307 struct i40e_rx_queue *rxq = rx_queue;
1308 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1309 volatile union i40e_rx_desc *rxdp;
1310 union i40e_rx_desc rxd;
1311 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1312 struct i40e_rx_entry *rxe;
1313 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1314 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1315 struct rte_mbuf *nmb, *rxm;
1316 uint16_t rx_id = rxq->rx_tail;
1317 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1323 while (nb_rx < nb_pkts) {
1324 rxdp = &rx_ring[rx_id];
1325 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1326 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1327 I40E_RXD_QW1_STATUS_SHIFT;
1329 /* Check the DD bit */
1330 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1333 nmb = rte_rxmbuf_alloc(rxq->mp);
1338 rxe = &sw_ring[rx_id];
1340 if (rx_id == rxq->nb_rx_desc)
1343 /* Prefetch next mbuf */
1344 rte_prefetch0(sw_ring[rx_id].mbuf);
1347 * When next RX descriptor is on a cache line boundary,
1348 * prefetch the next 4 RX descriptors and next 8 pointers
1351 if ((rx_id & 0x3) == 0) {
1352 rte_prefetch0(&rx_ring[rx_id]);
1353 rte_prefetch0(&sw_ring[rx_id]);
1359 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1361 /* Set data buffer address and data length of the mbuf */
1362 rxdp->read.hdr_addr = 0;
1363 rxdp->read.pkt_addr = dma_addr;
1364 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1365 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1366 rxm->data_len = rx_packet_len;
1367 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1370 * If this is the first buffer of the received packet, set the
1371 * pointer to the first mbuf of the packet and initialize its
1372 * context. Otherwise, update the total length and the number
1373 * of segments of the current scattered packet, and update the
1374 * pointer to the last mbuf of the current packet.
1378 first_seg->nb_segs = 1;
1379 first_seg->pkt_len = rx_packet_len;
1381 first_seg->pkt_len =
1382 (uint16_t)(first_seg->pkt_len +
1384 first_seg->nb_segs++;
1385 last_seg->next = rxm;
1389 * If this is not the last buffer of the received packet,
1390 * update the pointer to the last mbuf of the current scattered
1391 * packet and continue to parse the RX ring.
1393 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1399 * This is the last buffer of the received packet. If the CRC
1400 * is not stripped by the hardware:
1401 * - Subtract the CRC length from the total packet length.
1402 * - If the last buffer only contains the whole CRC or a part
1403 * of it, free the mbuf associated to the last buffer. If part
1404 * of the CRC is also contained in the previous mbuf, subtract
1405 * the length of that CRC part from the data length of the
1409 if (unlikely(rxq->crc_len > 0)) {
1410 first_seg->pkt_len -= ETHER_CRC_LEN;
1411 if (rx_packet_len <= ETHER_CRC_LEN) {
1412 rte_pktmbuf_free_seg(rxm);
1413 first_seg->nb_segs--;
1414 last_seg->data_len =
1415 (uint16_t)(last_seg->data_len -
1416 (ETHER_CRC_LEN - rx_packet_len));
1417 last_seg->next = NULL;
1419 rxm->data_len = (uint16_t)(rx_packet_len -
1423 first_seg->port = rxq->port_id;
1424 first_seg->ol_flags = 0;
1425 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1426 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1427 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1428 first_seg->packet_type =
1429 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1430 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1431 if (pkt_flags & PKT_RX_RSS_HASH)
1433 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1434 if (pkt_flags & PKT_RX_FDIR)
1435 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1437 #ifdef RTE_LIBRTE_IEEE1588
1438 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1440 first_seg->ol_flags |= pkt_flags;
1442 /* Prefetch data of first segment, if configured to do so. */
1443 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1444 first_seg->data_off));
1445 rx_pkts[nb_rx++] = first_seg;
1449 /* Record index of the next RX descriptor to probe. */
1450 rxq->rx_tail = rx_id;
1451 rxq->pkt_first_seg = first_seg;
1452 rxq->pkt_last_seg = last_seg;
1455 * If the number of free RX descriptors is greater than the RX free
1456 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1457 * register. Update the RDT with the value of the last processed RX
1458 * descriptor minus 1, to guarantee that the RDT register is never
1459 * equal to the RDH register, which creates a "full" ring situtation
1460 * from the hardware point of view.
1462 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1463 if (nb_hold > rxq->rx_free_thresh) {
1464 rx_id = (uint16_t)(rx_id == 0 ?
1465 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1466 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1469 rxq->nb_rx_hold = nb_hold;
1474 /* Check if the context descriptor is needed for TX offloading */
1475 static inline uint16_t
1476 i40e_calc_context_desc(uint64_t flags)
1478 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1482 #ifdef RTE_LIBRTE_IEEE1588
1483 mask |= PKT_TX_IEEE1588_TMST;
1486 return ((flags & mask) ? 1 : 0);
1489 /* set i40e TSO context descriptor */
1490 static inline uint64_t
1491 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1493 uint64_t ctx_desc = 0;
1494 uint32_t cd_cmd, hdr_len, cd_tso_len;
1496 if (!tx_offload.l4_len) {
1497 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1502 * in case of tunneling packet, the outer_l2_len and
1503 * outer_l3_len must be 0.
1505 hdr_len = tx_offload.outer_l2_len +
1506 tx_offload.outer_l3_len +
1511 cd_cmd = I40E_TX_CTX_DESC_TSO;
1512 cd_tso_len = mbuf->pkt_len - hdr_len;
1513 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1514 ((uint64_t)cd_tso_len <<
1515 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1516 ((uint64_t)mbuf->tso_segsz <<
1517 I40E_TXD_CTX_QW1_MSS_SHIFT);
1523 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1525 struct i40e_tx_queue *txq;
1526 struct i40e_tx_entry *sw_ring;
1527 struct i40e_tx_entry *txe, *txn;
1528 volatile struct i40e_tx_desc *txd;
1529 volatile struct i40e_tx_desc *txr;
1530 struct rte_mbuf *tx_pkt;
1531 struct rte_mbuf *m_seg;
1532 uint32_t cd_tunneling_params;
1544 uint64_t buf_dma_addr;
1545 union i40e_tx_offload tx_offload = {0};
1548 sw_ring = txq->sw_ring;
1550 tx_id = txq->tx_tail;
1551 txe = &sw_ring[tx_id];
1553 /* Check if the descriptor ring needs to be cleaned. */
1554 if (txq->nb_tx_free < txq->tx_free_thresh)
1555 i40e_xmit_cleanup(txq);
1557 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1563 tx_pkt = *tx_pkts++;
1564 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1566 ol_flags = tx_pkt->ol_flags;
1567 tx_offload.l2_len = tx_pkt->l2_len;
1568 tx_offload.l3_len = tx_pkt->l3_len;
1569 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1570 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1571 tx_offload.l4_len = tx_pkt->l4_len;
1572 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1574 /* Calculate the number of context descriptors needed. */
1575 nb_ctx = i40e_calc_context_desc(ol_flags);
1578 * The number of descriptors that must be allocated for
1579 * a packet equals to the number of the segments of that
1580 * packet plus 1 context descriptor if needed.
1582 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1583 tx_last = (uint16_t)(tx_id + nb_used - 1);
1586 if (tx_last >= txq->nb_tx_desc)
1587 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1589 if (nb_used > txq->nb_tx_free) {
1590 if (i40e_xmit_cleanup(txq) != 0) {
1595 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1596 while (nb_used > txq->nb_tx_free) {
1597 if (i40e_xmit_cleanup(txq) != 0) {
1606 /* Descriptor based VLAN insertion */
1607 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1608 tx_flags |= tx_pkt->vlan_tci <<
1609 I40E_TX_FLAG_L2TAG1_SHIFT;
1610 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1611 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1612 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1613 I40E_TX_FLAG_L2TAG1_SHIFT;
1616 /* Always enable CRC offload insertion */
1617 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1619 /* Enable checksum offloading */
1620 cd_tunneling_params = 0;
1621 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1622 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1623 tx_offload, &cd_tunneling_params);
1627 /* Setup TX context descriptor if required */
1628 volatile struct i40e_tx_context_desc *ctx_txd =
1629 (volatile struct i40e_tx_context_desc *)\
1631 uint16_t cd_l2tag2 = 0;
1632 uint64_t cd_type_cmd_tso_mss =
1633 I40E_TX_DESC_DTYPE_CONTEXT;
1635 txn = &sw_ring[txe->next_id];
1636 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1637 if (txe->mbuf != NULL) {
1638 rte_pktmbuf_free_seg(txe->mbuf);
1642 /* TSO enabled means no timestamp */
1643 if (ol_flags & PKT_TX_TCP_SEG)
1644 cd_type_cmd_tso_mss |=
1645 i40e_set_tso_ctx(tx_pkt, tx_offload);
1647 #ifdef RTE_LIBRTE_IEEE1588
1648 if (ol_flags & PKT_TX_IEEE1588_TMST)
1649 cd_type_cmd_tso_mss |=
1650 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1651 I40E_TXD_CTX_QW1_CMD_SHIFT);
1655 ctx_txd->tunneling_params =
1656 rte_cpu_to_le_32(cd_tunneling_params);
1657 if (ol_flags & PKT_TX_QINQ_PKT) {
1658 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1659 cd_type_cmd_tso_mss |=
1660 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1661 I40E_TXD_CTX_QW1_CMD_SHIFT);
1663 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1664 ctx_txd->type_cmd_tso_mss =
1665 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1667 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1668 "tunneling_params: %#x;\n"
1671 "type_cmd_tso_mss: %#"PRIx64";\n",
1673 ctx_txd->tunneling_params,
1676 ctx_txd->type_cmd_tso_mss);
1678 txe->last_id = tx_last;
1679 tx_id = txe->next_id;
1686 txn = &sw_ring[txe->next_id];
1689 rte_pktmbuf_free_seg(txe->mbuf);
1692 /* Setup TX Descriptor */
1693 slen = m_seg->data_len;
1694 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1696 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1697 "buf_dma_addr: %#"PRIx64";\n"
1702 tx_pkt, tx_id, buf_dma_addr,
1703 td_cmd, td_offset, slen, td_tag);
1705 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1706 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1707 td_offset, slen, td_tag);
1708 txe->last_id = tx_last;
1709 tx_id = txe->next_id;
1711 m_seg = m_seg->next;
1712 } while (m_seg != NULL);
1714 /* The last packet data descriptor needs End Of Packet (EOP) */
1715 td_cmd |= I40E_TX_DESC_CMD_EOP;
1716 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1717 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1719 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1720 PMD_TX_FREE_LOG(DEBUG,
1721 "Setting RS bit on TXD id="
1722 "%4u (port=%d queue=%d)",
1723 tx_last, txq->port_id, txq->queue_id);
1725 td_cmd |= I40E_TX_DESC_CMD_RS;
1727 /* Update txq RS bit counters */
1728 txq->nb_tx_used = 0;
1731 txd->cmd_type_offset_bsz |=
1732 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1733 I40E_TXD_QW1_CMD_SHIFT);
1739 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1740 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1741 (unsigned) tx_id, (unsigned) nb_tx);
1743 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1744 txq->tx_tail = tx_id;
1749 static inline int __attribute__((always_inline))
1750 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1752 struct i40e_tx_entry *txep;
1755 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1756 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1757 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1760 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1762 for (i = 0; i < txq->tx_rs_thresh; i++)
1763 rte_prefetch0((txep + i)->mbuf);
1765 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1766 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1767 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1771 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1772 rte_pktmbuf_free_seg(txep->mbuf);
1777 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1778 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1779 if (txq->tx_next_dd >= txq->nb_tx_desc)
1780 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1782 return txq->tx_rs_thresh;
1785 /* Populate 4 descriptors with data from 4 mbufs */
1787 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1792 for (i = 0; i < 4; i++, txdp++, pkts++) {
1793 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1794 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1795 txdp->cmd_type_offset_bsz =
1796 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1797 (*pkts)->data_len, 0);
1801 /* Populate 1 descriptor with data from 1 mbuf */
1803 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1807 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1808 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1809 txdp->cmd_type_offset_bsz =
1810 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1811 (*pkts)->data_len, 0);
1814 /* Fill hardware descriptor ring with mbuf data */
1816 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1817 struct rte_mbuf **pkts,
1820 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1821 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1822 const int N_PER_LOOP = 4;
1823 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1824 int mainpart, leftover;
1827 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1828 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1829 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1830 for (j = 0; j < N_PER_LOOP; ++j) {
1831 (txep + i + j)->mbuf = *(pkts + i + j);
1833 tx4(txdp + i, pkts + i);
1835 if (unlikely(leftover > 0)) {
1836 for (i = 0; i < leftover; ++i) {
1837 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1838 tx1(txdp + mainpart + i, pkts + mainpart + i);
1843 static inline uint16_t
1844 tx_xmit_pkts(struct i40e_tx_queue *txq,
1845 struct rte_mbuf **tx_pkts,
1848 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1852 * Begin scanning the H/W ring for done descriptors when the number
1853 * of available descriptors drops below tx_free_thresh. For each done
1854 * descriptor, free the associated buffer.
1856 if (txq->nb_tx_free < txq->tx_free_thresh)
1857 i40e_tx_free_bufs(txq);
1859 /* Use available descriptor only */
1860 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1861 if (unlikely(!nb_pkts))
1864 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1865 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1866 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1867 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1868 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1869 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1870 I40E_TXD_QW1_CMD_SHIFT);
1871 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1875 /* Fill hardware descriptor ring with mbuf data */
1876 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1877 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1879 /* Determin if RS bit needs to be set */
1880 if (txq->tx_tail > txq->tx_next_rs) {
1881 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1882 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1883 I40E_TXD_QW1_CMD_SHIFT);
1885 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1886 if (txq->tx_next_rs >= txq->nb_tx_desc)
1887 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1890 if (txq->tx_tail >= txq->nb_tx_desc)
1893 /* Update the tx tail register */
1895 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1901 i40e_xmit_pkts_simple(void *tx_queue,
1902 struct rte_mbuf **tx_pkts,
1907 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1908 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1912 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1915 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1916 &tx_pkts[nb_tx], num);
1917 nb_tx = (uint16_t)(nb_tx + ret);
1918 nb_pkts = (uint16_t)(nb_pkts - ret);
1927 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1928 * application used, which assume having sequential ones. But from driver's
1929 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1930 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1931 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1932 * use queue_idx from 0 to 95 to access queues, while real queue would be
1933 * different. This function will do a queue mapping to find VSI the queue
1936 static struct i40e_vsi*
1937 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1939 /* the queue in MAIN VSI range */
1940 if (queue_idx < pf->main_vsi->nb_qps)
1941 return pf->main_vsi;
1943 queue_idx -= pf->main_vsi->nb_qps;
1945 /* queue_idx is greater than VMDQ VSIs range */
1946 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1947 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1951 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1955 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1957 /* the queue in MAIN VSI range */
1958 if (queue_idx < pf->main_vsi->nb_qps)
1961 /* It's VMDQ queues */
1962 queue_idx -= pf->main_vsi->nb_qps;
1964 if (pf->nb_cfg_vmdq_vsi)
1965 return queue_idx % pf->vmdq_nb_qps;
1967 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1968 return (uint16_t)(-1);
1973 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1975 struct i40e_rx_queue *rxq;
1977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 PMD_INIT_FUNC_TRACE();
1981 if (rx_queue_id < dev->data->nb_rx_queues) {
1982 rxq = dev->data->rx_queues[rx_queue_id];
1984 err = i40e_alloc_rx_queue_mbufs(rxq);
1986 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1992 /* Init the RX tail regieter. */
1993 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1995 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1998 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2001 i40e_rx_queue_release_mbufs(rxq);
2002 i40e_reset_rx_queue(rxq);
2004 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2011 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2013 struct i40e_rx_queue *rxq;
2015 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017 if (rx_queue_id < dev->data->nb_rx_queues) {
2018 rxq = dev->data->rx_queues[rx_queue_id];
2021 * rx_queue_id is queue id aplication refers to, while
2022 * rxq->reg_idx is the real queue index.
2024 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2027 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2031 i40e_rx_queue_release_mbufs(rxq);
2032 i40e_reset_rx_queue(rxq);
2033 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2040 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2043 struct i40e_tx_queue *txq;
2044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046 PMD_INIT_FUNC_TRACE();
2048 if (tx_queue_id < dev->data->nb_tx_queues) {
2049 txq = dev->data->tx_queues[tx_queue_id];
2052 * tx_queue_id is queue id aplication refers to, while
2053 * rxq->reg_idx is the real queue index.
2055 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2057 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2060 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2067 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2069 struct i40e_tx_queue *txq;
2071 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073 if (tx_queue_id < dev->data->nb_tx_queues) {
2074 txq = dev->data->tx_queues[tx_queue_id];
2077 * tx_queue_id is queue id aplication refers to, while
2078 * txq->reg_idx is the real queue index.
2080 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2083 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2088 i40e_tx_queue_release_mbufs(txq);
2089 i40e_reset_tx_queue(txq);
2090 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2097 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2100 unsigned int socket_id,
2101 const struct rte_eth_rxconf *rx_conf,
2102 struct rte_mempool *mp)
2104 struct i40e_vsi *vsi;
2105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2107 struct i40e_adapter *ad =
2108 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2109 struct i40e_rx_queue *rxq;
2110 const struct rte_memzone *rz;
2113 uint16_t base, bsf, tc_mapping;
2114 int use_def_burst_func = 1;
2116 if (hw->mac.type == I40E_MAC_VF) {
2117 struct i40e_vf *vf =
2118 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2121 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2124 PMD_DRV_LOG(ERR, "VSI not available or queue "
2125 "index exceeds the maximum");
2126 return I40E_ERR_PARAM;
2128 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2129 (nb_desc > I40E_MAX_RING_DESC) ||
2130 (nb_desc < I40E_MIN_RING_DESC)) {
2131 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2132 "invalid", nb_desc);
2133 return I40E_ERR_PARAM;
2136 /* Free memory if needed */
2137 if (dev->data->rx_queues[queue_idx]) {
2138 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2139 dev->data->rx_queues[queue_idx] = NULL;
2142 /* Allocate the rx queue data structure */
2143 rxq = rte_zmalloc_socket("i40e rx queue",
2144 sizeof(struct i40e_rx_queue),
2145 RTE_CACHE_LINE_SIZE,
2148 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2149 "rx queue data structure");
2153 rxq->nb_rx_desc = nb_desc;
2154 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2155 rxq->queue_id = queue_idx;
2156 if (hw->mac.type == I40E_MAC_VF)
2157 rxq->reg_idx = queue_idx;
2158 else /* PF device */
2159 rxq->reg_idx = vsi->base_queue +
2160 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2162 rxq->port_id = dev->data->port_id;
2163 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2165 rxq->drop_en = rx_conf->rx_drop_en;
2167 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2169 /* Allocate the maximun number of RX ring hardware descriptor. */
2170 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2171 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2172 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2173 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2175 i40e_dev_rx_queue_release(rxq);
2176 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2180 /* Zero all the descriptors in the ring. */
2181 memset(rz->addr, 0, ring_size);
2183 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2184 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2186 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2187 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2192 /* Allocate the software ring. */
2194 rte_zmalloc_socket("i40e rx sw ring",
2195 sizeof(struct i40e_rx_entry) * len,
2196 RTE_CACHE_LINE_SIZE,
2198 if (!rxq->sw_ring) {
2199 i40e_dev_rx_queue_release(rxq);
2200 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2204 i40e_reset_rx_queue(rxq);
2206 dev->data->rx_queues[queue_idx] = rxq;
2208 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2210 if (!use_def_burst_func) {
2211 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2212 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2213 "satisfied. Rx Burst Bulk Alloc function will be "
2214 "used on port=%d, queue=%d.",
2215 rxq->port_id, rxq->queue_id);
2216 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2218 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2219 "not satisfied, Scattered Rx is requested, "
2220 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2221 "not enabled on port=%d, queue=%d.",
2222 rxq->port_id, rxq->queue_id);
2223 ad->rx_bulk_alloc_allowed = false;
2226 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2227 if (!(vsi->enabled_tc & (1 << i)))
2229 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2230 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2231 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2232 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2233 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2235 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2243 i40e_dev_rx_queue_release(void *rxq)
2245 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2248 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2252 i40e_rx_queue_release_mbufs(q);
2253 rte_free(q->sw_ring);
2258 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2260 #define I40E_RXQ_SCAN_INTERVAL 4
2261 volatile union i40e_rx_desc *rxdp;
2262 struct i40e_rx_queue *rxq;
2265 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2266 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2270 rxq = dev->data->rx_queues[rx_queue_id];
2271 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2272 while ((desc < rxq->nb_rx_desc) &&
2273 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2274 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2275 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2277 * Check the DD bit of a rx descriptor of each 4 in a group,
2278 * to avoid checking too frequently and downgrading performance
2281 desc += I40E_RXQ_SCAN_INTERVAL;
2282 rxdp += I40E_RXQ_SCAN_INTERVAL;
2283 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2284 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2285 desc - rxq->nb_rx_desc]);
2292 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2294 volatile union i40e_rx_desc *rxdp;
2295 struct i40e_rx_queue *rxq = rx_queue;
2299 if (unlikely(offset >= rxq->nb_rx_desc)) {
2300 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2304 desc = rxq->rx_tail + offset;
2305 if (desc >= rxq->nb_rx_desc)
2306 desc -= rxq->nb_rx_desc;
2308 rxdp = &(rxq->rx_ring[desc]);
2310 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2311 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2312 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2318 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2321 unsigned int socket_id,
2322 const struct rte_eth_txconf *tx_conf)
2324 struct i40e_vsi *vsi;
2325 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2327 struct i40e_tx_queue *txq;
2328 const struct rte_memzone *tz;
2330 uint16_t tx_rs_thresh, tx_free_thresh;
2331 uint16_t i, base, bsf, tc_mapping;
2333 if (hw->mac.type == I40E_MAC_VF) {
2334 struct i40e_vf *vf =
2335 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2338 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2341 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2342 "exceeds the maximum", queue_idx);
2343 return I40E_ERR_PARAM;
2346 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2347 (nb_desc > I40E_MAX_RING_DESC) ||
2348 (nb_desc < I40E_MIN_RING_DESC)) {
2349 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2350 "invalid", nb_desc);
2351 return I40E_ERR_PARAM;
2355 * The following two parameters control the setting of the RS bit on
2356 * transmit descriptors. TX descriptors will have their RS bit set
2357 * after txq->tx_rs_thresh descriptors have been used. The TX
2358 * descriptor ring will be cleaned after txq->tx_free_thresh
2359 * descriptors are used or if the number of descriptors required to
2360 * transmit a packet is greater than the number of free TX descriptors.
2362 * The following constraints must be satisfied:
2363 * - tx_rs_thresh must be greater than 0.
2364 * - tx_rs_thresh must be less than the size of the ring minus 2.
2365 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2366 * - tx_rs_thresh must be a divisor of the ring size.
2367 * - tx_free_thresh must be greater than 0.
2368 * - tx_free_thresh must be less than the size of the ring minus 3.
2370 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2371 * race condition, hence the maximum threshold constraints. When set
2372 * to zero use default values.
2374 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2375 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2376 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2377 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2378 if (tx_rs_thresh >= (nb_desc - 2)) {
2379 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2380 "number of TX descriptors minus 2. "
2381 "(tx_rs_thresh=%u port=%d queue=%d)",
2382 (unsigned int)tx_rs_thresh,
2383 (int)dev->data->port_id,
2385 return I40E_ERR_PARAM;
2387 if (tx_free_thresh >= (nb_desc - 3)) {
2388 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2389 "tx_free_thresh must be less than the "
2390 "number of TX descriptors minus 3. "
2391 "(tx_free_thresh=%u port=%d queue=%d)",
2392 (unsigned int)tx_free_thresh,
2393 (int)dev->data->port_id,
2395 return I40E_ERR_PARAM;
2397 if (tx_rs_thresh > tx_free_thresh) {
2398 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2399 "equal to tx_free_thresh. (tx_free_thresh=%u"
2400 " tx_rs_thresh=%u port=%d queue=%d)",
2401 (unsigned int)tx_free_thresh,
2402 (unsigned int)tx_rs_thresh,
2403 (int)dev->data->port_id,
2405 return I40E_ERR_PARAM;
2407 if ((nb_desc % tx_rs_thresh) != 0) {
2408 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2409 "number of TX descriptors. (tx_rs_thresh=%u"
2410 " port=%d queue=%d)",
2411 (unsigned int)tx_rs_thresh,
2412 (int)dev->data->port_id,
2414 return I40E_ERR_PARAM;
2416 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2417 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2418 "tx_rs_thresh is greater than 1. "
2419 "(tx_rs_thresh=%u port=%d queue=%d)",
2420 (unsigned int)tx_rs_thresh,
2421 (int)dev->data->port_id,
2423 return I40E_ERR_PARAM;
2426 /* Free memory if needed. */
2427 if (dev->data->tx_queues[queue_idx]) {
2428 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2429 dev->data->tx_queues[queue_idx] = NULL;
2432 /* Allocate the TX queue data structure. */
2433 txq = rte_zmalloc_socket("i40e tx queue",
2434 sizeof(struct i40e_tx_queue),
2435 RTE_CACHE_LINE_SIZE,
2438 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2439 "tx queue structure");
2443 /* Allocate TX hardware ring descriptors. */
2444 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2445 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2446 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2447 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2449 i40e_dev_tx_queue_release(txq);
2450 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2454 txq->nb_tx_desc = nb_desc;
2455 txq->tx_rs_thresh = tx_rs_thresh;
2456 txq->tx_free_thresh = tx_free_thresh;
2457 txq->pthresh = tx_conf->tx_thresh.pthresh;
2458 txq->hthresh = tx_conf->tx_thresh.hthresh;
2459 txq->wthresh = tx_conf->tx_thresh.wthresh;
2460 txq->queue_id = queue_idx;
2461 if (hw->mac.type == I40E_MAC_VF)
2462 txq->reg_idx = queue_idx;
2463 else /* PF device */
2464 txq->reg_idx = vsi->base_queue +
2465 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2467 txq->port_id = dev->data->port_id;
2468 txq->txq_flags = tx_conf->txq_flags;
2470 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2472 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2473 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2475 /* Allocate software ring */
2477 rte_zmalloc_socket("i40e tx sw ring",
2478 sizeof(struct i40e_tx_entry) * nb_desc,
2479 RTE_CACHE_LINE_SIZE,
2481 if (!txq->sw_ring) {
2482 i40e_dev_tx_queue_release(txq);
2483 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2487 i40e_reset_tx_queue(txq);
2489 dev->data->tx_queues[queue_idx] = txq;
2491 /* Use a simple TX queue without offloads or multi segs if possible */
2492 i40e_set_tx_function_flag(dev, txq);
2494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2495 if (!(vsi->enabled_tc & (1 << i)))
2497 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2498 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2499 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2500 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2501 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2503 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2511 i40e_dev_tx_queue_release(void *txq)
2513 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2516 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2520 i40e_tx_queue_release_mbufs(q);
2521 rte_free(q->sw_ring);
2525 const struct rte_memzone *
2526 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2528 const struct rte_memzone *mz;
2530 mz = rte_memzone_lookup(name);
2534 if (is_xen_dom0_supported())
2535 mz = rte_memzone_reserve_bounded(name, len,
2536 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2538 mz = rte_memzone_reserve_aligned(name, len,
2539 socket_id, 0, I40E_RING_BASE_ALIGN);
2544 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2548 /* SSE Vector driver has a different way of releasing mbufs. */
2549 if (rxq->rx_using_sse) {
2550 i40e_rx_queue_release_mbufs_vec(rxq);
2554 if (!rxq || !rxq->sw_ring) {
2555 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2559 for (i = 0; i < rxq->nb_rx_desc; i++) {
2560 if (rxq->sw_ring[i].mbuf) {
2561 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2562 rxq->sw_ring[i].mbuf = NULL;
2565 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2566 if (rxq->rx_nb_avail == 0)
2568 for (i = 0; i < rxq->rx_nb_avail; i++) {
2569 struct rte_mbuf *mbuf;
2571 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2572 rte_pktmbuf_free_seg(mbuf);
2574 rxq->rx_nb_avail = 0;
2575 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2579 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2585 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2589 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2590 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2591 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2593 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2594 len = rxq->nb_rx_desc;
2596 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2597 ((volatile char *)rxq->rx_ring)[i] = 0;
2599 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2600 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2601 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2602 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2604 rxq->rx_nb_avail = 0;
2605 rxq->rx_next_avail = 0;
2606 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2607 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2609 rxq->nb_rx_hold = 0;
2610 rxq->pkt_first_seg = NULL;
2611 rxq->pkt_last_seg = NULL;
2613 rxq->rxrearm_start = 0;
2614 rxq->rxrearm_nb = 0;
2618 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2622 if (!txq || !txq->sw_ring) {
2623 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2627 for (i = 0; i < txq->nb_tx_desc; i++) {
2628 if (txq->sw_ring[i].mbuf) {
2629 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2630 txq->sw_ring[i].mbuf = NULL;
2636 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2638 struct i40e_tx_entry *txe;
2639 uint16_t i, prev, size;
2642 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2647 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2648 for (i = 0; i < size; i++)
2649 ((volatile char *)txq->tx_ring)[i] = 0;
2651 prev = (uint16_t)(txq->nb_tx_desc - 1);
2652 for (i = 0; i < txq->nb_tx_desc; i++) {
2653 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2655 txd->cmd_type_offset_bsz =
2656 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2659 txe[prev].next_id = i;
2663 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2664 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2667 txq->nb_tx_used = 0;
2669 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2670 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2673 /* Init the TX queue in hardware */
2675 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2677 enum i40e_status_code err = I40E_SUCCESS;
2678 struct i40e_vsi *vsi = txq->vsi;
2679 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2680 uint16_t pf_q = txq->reg_idx;
2681 struct i40e_hmc_obj_txq tx_ctx;
2684 /* clear the context structure first */
2685 memset(&tx_ctx, 0, sizeof(tx_ctx));
2686 tx_ctx.new_context = 1;
2687 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2688 tx_ctx.qlen = txq->nb_tx_desc;
2690 #ifdef RTE_LIBRTE_IEEE1588
2691 tx_ctx.timesync_ena = 1;
2693 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2694 if (vsi->type == I40E_VSI_FDIR)
2695 tx_ctx.fd_ena = TRUE;
2697 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2698 if (err != I40E_SUCCESS) {
2699 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2703 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2704 if (err != I40E_SUCCESS) {
2705 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2709 /* Now associate this queue with this PCI function */
2710 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2711 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2712 I40E_QTX_CTL_PF_INDX_MASK);
2713 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2714 I40E_WRITE_FLUSH(hw);
2716 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2722 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2724 struct i40e_rx_entry *rxe = rxq->sw_ring;
2728 for (i = 0; i < rxq->nb_rx_desc; i++) {
2729 volatile union i40e_rx_desc *rxd;
2730 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2732 if (unlikely(!mbuf)) {
2733 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2737 rte_mbuf_refcnt_set(mbuf, 1);
2739 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2741 mbuf->port = rxq->port_id;
2744 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2746 rxd = &rxq->rx_ring[i];
2747 rxd->read.pkt_addr = dma_addr;
2748 rxd->read.hdr_addr = 0;
2749 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2750 rxd->read.rsvd1 = 0;
2751 rxd->read.rsvd2 = 0;
2752 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2761 * Calculate the buffer length, and check the jumbo frame
2762 * and maximum packet length.
2765 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2767 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2768 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2769 struct rte_eth_dev_data *data = pf->dev_data;
2770 uint16_t buf_size, len;
2772 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2773 RTE_PKTMBUF_HEADROOM);
2775 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2776 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2777 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2778 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2779 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2780 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2781 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2782 rxq->hs_mode = i40e_header_split_enabled;
2784 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2786 rxq->rx_hdr_len = 0;
2787 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2788 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2789 rxq->hs_mode = i40e_header_split_none;
2793 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2794 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2795 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2796 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2797 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2798 PMD_DRV_LOG(ERR, "maximum packet length must "
2799 "be larger than %u and smaller than %u,"
2800 "as jumbo frame is enabled",
2801 (uint32_t)ETHER_MAX_LEN,
2802 (uint32_t)I40E_FRAME_SIZE_MAX);
2803 return I40E_ERR_CONFIG;
2806 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2807 rxq->max_pkt_len > ETHER_MAX_LEN) {
2808 PMD_DRV_LOG(ERR, "maximum packet length must be "
2809 "larger than %u and smaller than %u, "
2810 "as jumbo frame is disabled",
2811 (uint32_t)ETHER_MIN_LEN,
2812 (uint32_t)ETHER_MAX_LEN);
2813 return I40E_ERR_CONFIG;
2820 /* Init the RX queue in hardware */
2822 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2824 int err = I40E_SUCCESS;
2825 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2826 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2827 uint16_t pf_q = rxq->reg_idx;
2829 struct i40e_hmc_obj_rxq rx_ctx;
2831 err = i40e_rx_queue_config(rxq);
2833 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2837 /* Clear the context structure first */
2838 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2839 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2840 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2842 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2843 rx_ctx.qlen = rxq->nb_rx_desc;
2844 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2847 rx_ctx.dtype = rxq->hs_mode;
2849 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2851 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2852 rx_ctx.rxmax = rxq->max_pkt_len;
2853 rx_ctx.tphrdesc_ena = 1;
2854 rx_ctx.tphwdesc_ena = 1;
2855 rx_ctx.tphdata_ena = 1;
2856 rx_ctx.tphhead_ena = 1;
2857 rx_ctx.lrxqthresh = 2;
2858 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2863 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2864 if (err != I40E_SUCCESS) {
2865 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2868 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2869 if (err != I40E_SUCCESS) {
2870 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2874 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2876 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2877 RTE_PKTMBUF_HEADROOM);
2879 /* Check if scattered RX needs to be used. */
2880 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2881 dev_data->scattered_rx = 1;
2884 /* Init the RX tail regieter. */
2885 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2891 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2895 PMD_INIT_FUNC_TRACE();
2897 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2898 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2899 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2902 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2903 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2904 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2909 i40e_dev_free_queues(struct rte_eth_dev *dev)
2913 PMD_INIT_FUNC_TRACE();
2915 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2916 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2917 dev->data->rx_queues[i] = NULL;
2919 dev->data->nb_rx_queues = 0;
2921 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2922 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2923 dev->data->tx_queues[i] = NULL;
2925 dev->data->nb_tx_queues = 0;
2928 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2929 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2931 enum i40e_status_code
2932 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2934 struct i40e_tx_queue *txq;
2935 const struct rte_memzone *tz = NULL;
2937 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2940 PMD_DRV_LOG(ERR, "PF is not available");
2941 return I40E_ERR_BAD_PTR;
2944 /* Allocate the TX queue data structure. */
2945 txq = rte_zmalloc_socket("i40e fdir tx queue",
2946 sizeof(struct i40e_tx_queue),
2947 RTE_CACHE_LINE_SIZE,
2950 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2951 "tx queue structure.");
2952 return I40E_ERR_NO_MEMORY;
2955 /* Allocate TX hardware ring descriptors. */
2956 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2957 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2959 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2960 I40E_FDIR_QUEUE_ID, ring_size,
2961 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2963 i40e_dev_tx_queue_release(txq);
2964 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2965 return I40E_ERR_NO_MEMORY;
2968 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2969 txq->queue_id = I40E_FDIR_QUEUE_ID;
2970 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2971 txq->vsi = pf->fdir.fdir_vsi;
2973 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2974 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2976 * don't need to allocate software ring and reset for the fdir
2977 * program queue just set the queue has been configured.
2982 return I40E_SUCCESS;
2985 enum i40e_status_code
2986 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2988 struct i40e_rx_queue *rxq;
2989 const struct rte_memzone *rz = NULL;
2991 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2994 PMD_DRV_LOG(ERR, "PF is not available");
2995 return I40E_ERR_BAD_PTR;
2998 /* Allocate the RX queue data structure. */
2999 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3000 sizeof(struct i40e_rx_queue),
3001 RTE_CACHE_LINE_SIZE,
3004 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3005 "rx queue structure.");
3006 return I40E_ERR_NO_MEMORY;
3009 /* Allocate RX hardware ring descriptors. */
3010 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3011 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3013 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3014 I40E_FDIR_QUEUE_ID, ring_size,
3015 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3017 i40e_dev_rx_queue_release(rxq);
3018 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3019 return I40E_ERR_NO_MEMORY;
3022 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3023 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3024 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3025 rxq->vsi = pf->fdir.fdir_vsi;
3027 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3028 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3031 * Don't need to allocate software ring and reset for the fdir
3032 * rx queue, just set the queue has been configured.
3037 return I40E_SUCCESS;
3041 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3042 struct rte_eth_rxq_info *qinfo)
3044 struct i40e_rx_queue *rxq;
3046 rxq = dev->data->rx_queues[queue_id];
3048 qinfo->mp = rxq->mp;
3049 qinfo->scattered_rx = dev->data->scattered_rx;
3050 qinfo->nb_desc = rxq->nb_rx_desc;
3052 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3053 qinfo->conf.rx_drop_en = rxq->drop_en;
3054 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3058 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3059 struct rte_eth_txq_info *qinfo)
3061 struct i40e_tx_queue *txq;
3063 txq = dev->data->tx_queues[queue_id];
3065 qinfo->nb_desc = txq->nb_tx_desc;
3067 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3068 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3069 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3071 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3072 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3073 qinfo->conf.txq_flags = txq->txq_flags;
3074 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3077 void __attribute__((cold))
3078 i40e_set_rx_function(struct rte_eth_dev *dev)
3080 struct i40e_adapter *ad =
3081 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3082 uint16_t rx_using_sse, i;
3083 /* In order to allow Vector Rx there are a few configuration
3084 * conditions to be met and Rx Bulk Allocation should be allowed.
3086 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3087 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3088 !ad->rx_bulk_alloc_allowed) {
3089 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3090 " Vector Rx preconditions",
3091 dev->data->port_id);
3093 ad->rx_vec_allowed = false;
3095 if (ad->rx_vec_allowed) {
3096 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3097 struct i40e_rx_queue *rxq =
3098 dev->data->rx_queues[i];
3100 if (i40e_rxq_vec_setup(rxq)) {
3101 ad->rx_vec_allowed = false;
3108 if (dev->data->scattered_rx) {
3109 /* Set the non-LRO scattered callback: there are Vector and
3110 * single allocation versions.
3112 if (ad->rx_vec_allowed) {
3113 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3114 "callback (port=%d).",
3115 dev->data->port_id);
3117 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3119 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3120 "allocation callback (port=%d).",
3121 dev->data->port_id);
3122 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3124 /* If parameters allow we are going to choose between the following
3128 * - Single buffer allocation (the simplest one)
3130 } else if (ad->rx_vec_allowed) {
3131 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3132 "burst size no less than %d (port=%d).",
3133 RTE_I40E_DESCS_PER_LOOP,
3134 dev->data->port_id);
3136 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3137 } else if (ad->rx_bulk_alloc_allowed) {
3138 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3139 "satisfied. Rx Burst Bulk Alloc function "
3140 "will be used on port=%d.",
3141 dev->data->port_id);
3143 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3145 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3146 "satisfied, or Scattered Rx is requested "
3148 dev->data->port_id);
3150 dev->rx_pkt_burst = i40e_recv_pkts;
3153 /* Propagate information about RX function choice through all queues. */
3154 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3156 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3157 dev->rx_pkt_burst == i40e_recv_pkts_vec);
3159 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3160 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3162 rxq->rx_using_sse = rx_using_sse;
3167 void __attribute__((cold))
3168 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3170 struct i40e_adapter *ad =
3171 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3173 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3174 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3175 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3176 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3177 PMD_INIT_LOG(DEBUG, "Vector tx"
3178 " can be enabled on this txq.");
3181 ad->tx_vec_allowed = false;
3184 ad->tx_simple_allowed = false;
3188 void __attribute__((cold))
3189 i40e_set_tx_function(struct rte_eth_dev *dev)
3191 struct i40e_adapter *ad =
3192 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3195 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3196 if (ad->tx_vec_allowed) {
3197 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3198 struct i40e_tx_queue *txq =
3199 dev->data->tx_queues[i];
3201 if (i40e_txq_vec_setup(txq)) {
3202 ad->tx_vec_allowed = false;
3209 if (ad->tx_simple_allowed) {
3210 if (ad->tx_vec_allowed) {
3211 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3212 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3214 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3215 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3218 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3219 dev->tx_pkt_burst = i40e_xmit_pkts;
3223 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3224 int __attribute__((weak))
3225 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3230 uint16_t __attribute__((weak))
3232 void __rte_unused *rx_queue,
3233 struct rte_mbuf __rte_unused **rx_pkts,
3234 uint16_t __rte_unused nb_pkts)
3239 uint16_t __attribute__((weak))
3240 i40e_recv_scattered_pkts_vec(
3241 void __rte_unused *rx_queue,
3242 struct rte_mbuf __rte_unused **rx_pkts,
3243 uint16_t __rte_unused nb_pkts)
3248 int __attribute__((weak))
3249 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3254 int __attribute__((weak))
3255 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3260 void __attribute__((weak))
3261 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3266 uint16_t __attribute__((weak))
3267 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3268 struct rte_mbuf __rte_unused **tx_pkts,
3269 uint16_t __rte_unused nb_pkts)