1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
28 #include "i40e_logs.h"
29 #include "base/i40e_prototype.h"
30 #include "base/i40e_type.h"
31 #include "i40e_ethdev.h"
32 #include "i40e_rxtx.h"
34 #define DEFAULT_TX_RS_THRESH 32
35 #define DEFAULT_TX_FREE_THRESH 32
37 #define I40E_TX_MAX_BURST 32
39 #define I40E_DMA_MEM_ALIGN 4096
41 /* Base address of the HW descriptor ring should be 128B aligned. */
42 #define I40E_RING_BASE_ALIGN 128
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define I40E_TX_IEEE1588_TMST RTE_MBUF_F_TX_IEEE1588_TMST
49 #define I40E_TX_IEEE1588_TMST 0
52 #define I40E_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM | \
53 RTE_MBUF_F_TX_L4_MASK | \
54 RTE_MBUF_F_TX_TCP_SEG | \
55 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
57 #define I40E_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_IPV4 | \
58 RTE_MBUF_F_TX_OUTER_IPV6 | \
59 RTE_MBUF_F_TX_IPV4 | \
60 RTE_MBUF_F_TX_IPV6 | \
61 RTE_MBUF_F_TX_IP_CKSUM | \
62 RTE_MBUF_F_TX_L4_MASK | \
63 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \
64 RTE_MBUF_F_TX_TCP_SEG | \
65 RTE_MBUF_F_TX_QINQ | \
66 RTE_MBUF_F_TX_VLAN | \
67 RTE_MBUF_F_TX_TUNNEL_MASK | \
68 RTE_MBUF_F_TX_OUTER_UDP_CKSUM | \
69 I40E_TX_IEEE1588_TMST)
71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
72 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
74 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK (RTE_MBUF_F_TX_IPV4 | \
75 RTE_MBUF_F_TX_IPV6 | \
76 RTE_MBUF_F_TX_OUTER_IPV4 | \
77 RTE_MBUF_F_TX_OUTER_IPV6)
79 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
80 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
83 i40e_monitor_callback(const uint64_t value,
84 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
86 const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
88 * we expect the DD bit to be set to 1 if this descriptor was already
91 return (value & m) == m ? -1 : 0;
95 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
97 struct i40e_rx_queue *rxq = rx_queue;
98 volatile union i40e_rx_desc *rxdp;
102 rxdp = &rxq->rx_ring[desc];
103 /* watch for changes in status bit */
104 pmc->addr = &rxdp->wb.qword1.status_error_len;
106 /* comparison callback */
107 pmc->fn = i40e_monitor_callback;
109 /* registers are 64-bit */
110 pmc->size = sizeof(uint64_t);
116 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
118 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
119 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
120 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
122 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
123 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
124 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
128 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
129 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
130 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
131 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
132 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
133 mb->vlan_tci_outer = mb->vlan_tci;
134 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
135 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
136 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
137 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
139 mb->vlan_tci_outer = 0;
142 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
143 mb->vlan_tci, mb->vlan_tci_outer);
146 /* Translate the rx descriptor status to pkt flags */
147 static inline uint64_t
148 i40e_rxd_status_to_pkt_flags(uint64_t qword)
152 /* Check if RSS_HASH */
153 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
154 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
155 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
157 /* Check if FDIR Match */
158 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
159 RTE_MBUF_F_RX_FDIR : 0);
164 static inline uint64_t
165 i40e_rxd_error_to_pkt_flags(uint64_t qword)
168 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
170 #define I40E_RX_ERR_BITS 0x3f
171 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
172 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
176 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
177 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
179 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
181 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
182 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
184 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
186 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
187 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
192 /* Function to check and set the ieee1588 timesync index and get the
195 #ifdef RTE_LIBRTE_IEEE1588
196 static inline uint64_t
197 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
199 uint64_t pkt_flags = 0;
200 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
201 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
202 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
204 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
205 == RTE_PTYPE_L2_ETHER_TIMESYNC)
206 pkt_flags = RTE_MBUF_F_RX_IEEE1588_PTP;
208 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
209 mb->timesync = tsyn & 0x03;
216 static inline uint64_t
217 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
220 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
221 uint16_t flexbh, flexbl;
223 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
224 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
225 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
226 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
227 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
228 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
231 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
233 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
234 flags |= RTE_MBUF_F_RX_FDIR_ID;
235 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
237 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
238 flags |= RTE_MBUF_F_RX_FDIR_FLX;
240 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
242 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
243 flags |= RTE_MBUF_F_RX_FDIR_FLX;
247 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
248 flags |= RTE_MBUF_F_RX_FDIR_ID;
254 i40e_parse_tunneling_params(uint64_t ol_flags,
255 union i40e_tx_offload tx_offload,
256 uint32_t *cd_tunneling)
258 /* EIPT: External (outer) IP header type */
259 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
260 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
261 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
262 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
263 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
264 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
266 /* EIPLEN: External (outer) IP header length, in DWords */
267 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
268 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
270 /* L4TUNT: L4 Tunneling Type */
271 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
272 case RTE_MBUF_F_TX_TUNNEL_IPIP:
273 /* for non UDP / GRE tunneling, set to 00b */
275 case RTE_MBUF_F_TX_TUNNEL_VXLAN:
276 case RTE_MBUF_F_TX_TUNNEL_GENEVE:
277 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
279 case RTE_MBUF_F_TX_TUNNEL_GRE:
280 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
283 PMD_TX_LOG(ERR, "Tunnel type not supported");
287 /* L4TUNLEN: L4 Tunneling Length, in Words
289 * We depend on app to set rte_mbuf.l2_len correctly.
290 * For IP in GRE it should be set to the length of the GRE
292 * for MAC in GRE or MAC in UDP it should be set to the length
293 * of the GRE or UDP headers plus the inner MAC up to including
294 * its last Ethertype.
296 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
297 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
301 i40e_txd_enable_checksum(uint64_t ol_flags,
304 union i40e_tx_offload tx_offload)
307 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
308 *td_offset |= (tx_offload.outer_l2_len >> 1)
309 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
311 *td_offset |= (tx_offload.l2_len >> 1)
312 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
314 /* Enable L3 checksum offloads */
315 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
316 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
317 *td_offset |= (tx_offload.l3_len >> 2)
318 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
319 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
320 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
321 *td_offset |= (tx_offload.l3_len >> 2)
322 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
323 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
324 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
325 *td_offset |= (tx_offload.l3_len >> 2)
326 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
329 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
330 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
331 *td_offset |= (tx_offload.l4_len >> 2)
332 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
336 /* Enable L4 checksum offloads */
337 switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
338 case RTE_MBUF_F_TX_TCP_CKSUM:
339 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
340 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
341 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
343 case RTE_MBUF_F_TX_SCTP_CKSUM:
344 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
345 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
346 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
348 case RTE_MBUF_F_TX_UDP_CKSUM:
349 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
350 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
351 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
358 /* Construct the tx flags */
359 static inline uint64_t
360 i40e_build_ctob(uint32_t td_cmd,
365 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
366 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
367 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
368 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
369 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
373 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
375 struct i40e_tx_entry *sw_ring = txq->sw_ring;
376 volatile struct i40e_tx_desc *txd = txq->tx_ring;
377 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
378 uint16_t nb_tx_desc = txq->nb_tx_desc;
379 uint16_t desc_to_clean_to;
380 uint16_t nb_tx_to_clean;
382 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
383 if (desc_to_clean_to >= nb_tx_desc)
384 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
386 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
387 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
388 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
389 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
390 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
391 "(port=%d queue=%d)", desc_to_clean_to,
392 txq->port_id, txq->queue_id);
396 if (last_desc_cleaned > desc_to_clean_to)
397 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
400 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
403 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
405 txq->last_desc_cleaned = desc_to_clean_to;
406 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
413 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
415 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
420 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
421 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
422 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
423 "rxq->rx_free_thresh=%d, "
424 "RTE_PMD_I40E_RX_MAX_BURST=%d",
425 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
427 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
428 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
429 "rxq->rx_free_thresh=%d, "
430 "rxq->nb_rx_desc=%d",
431 rxq->rx_free_thresh, rxq->nb_rx_desc);
433 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
434 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
435 "rxq->nb_rx_desc=%d, "
436 "rxq->rx_free_thresh=%d",
437 rxq->nb_rx_desc, rxq->rx_free_thresh);
447 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
448 #define I40E_LOOK_AHEAD 8
449 #if (I40E_LOOK_AHEAD != 8)
450 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
453 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
455 volatile union i40e_rx_desc *rxdp;
456 struct i40e_rx_entry *rxep;
461 int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
462 int32_t i, j, nb_rx = 0;
464 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
466 rxdp = &rxq->rx_ring[rxq->rx_tail];
467 rxep = &rxq->sw_ring[rxq->rx_tail];
469 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
470 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
471 I40E_RXD_QW1_STATUS_SHIFT;
473 /* Make sure there is at least 1 packet to receive */
474 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
478 * Scan LOOK_AHEAD descriptors at a time to determine which
479 * descriptors reference packets that are ready to be received.
481 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
482 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
483 /* Read desc statuses backwards to avoid race condition */
484 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
485 qword1 = rte_le_to_cpu_64(\
486 rxdp[j].wb.qword1.status_error_len);
487 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
488 I40E_RXD_QW1_STATUS_SHIFT;
491 /* This barrier is to order loads of different words in the descriptor */
492 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
494 /* Compute how many status bits were set */
495 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
496 var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
498 /* For Arm platforms, only compute continuous status bits */
510 /* Translate descriptor info to mbuf parameters */
511 for (j = 0; j < nb_dd; j++) {
513 qword1 = rte_le_to_cpu_64(\
514 rxdp[j].wb.qword1.status_error_len);
515 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
516 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
517 mb->data_len = pkt_len;
518 mb->pkt_len = pkt_len;
520 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
521 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
522 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
524 ptype_tbl[(uint8_t)((qword1 &
525 I40E_RXD_QW1_PTYPE_MASK) >>
526 I40E_RXD_QW1_PTYPE_SHIFT)];
527 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
528 mb->hash.rss = rte_le_to_cpu_32(\
529 rxdp[j].wb.qword0.hi_dword.rss);
530 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
531 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
533 #ifdef RTE_LIBRTE_IEEE1588
534 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
536 mb->ol_flags |= pkt_flags;
540 for (j = 0; j < I40E_LOOK_AHEAD; j++)
541 rxq->rx_stage[i + j] = rxep[j].mbuf;
543 if (nb_dd != I40E_LOOK_AHEAD)
547 /* Clear software ring entries */
548 for (i = 0; i < nb_rx; i++)
549 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
554 static inline uint16_t
555 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
556 struct rte_mbuf **rx_pkts,
560 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
562 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
564 for (i = 0; i < nb_pkts; i++)
565 rx_pkts[i] = stage[i];
567 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
568 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
574 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
576 volatile union i40e_rx_desc *rxdp;
577 struct i40e_rx_entry *rxep;
579 uint16_t alloc_idx, i;
583 /* Allocate buffers in bulk */
584 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
585 (rxq->rx_free_thresh - 1));
586 rxep = &(rxq->sw_ring[alloc_idx]);
587 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
588 rxq->rx_free_thresh);
589 if (unlikely(diag != 0)) {
590 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
594 rxdp = &rxq->rx_ring[alloc_idx];
595 for (i = 0; i < rxq->rx_free_thresh; i++) {
596 if (likely(i < (rxq->rx_free_thresh - 1)))
597 /* Prefetch next mbuf */
598 rte_prefetch0(rxep[i + 1].mbuf);
601 rte_mbuf_refcnt_set(mb, 1);
603 mb->data_off = RTE_PKTMBUF_HEADROOM;
605 mb->port = rxq->port_id;
606 dma_addr = rte_cpu_to_le_64(\
607 rte_mbuf_data_iova_default(mb));
608 rxdp[i].read.hdr_addr = 0;
609 rxdp[i].read.pkt_addr = dma_addr;
612 /* Update rx tail register */
613 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
615 rxq->rx_free_trigger =
616 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
617 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
618 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
623 static inline uint16_t
624 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
626 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
627 struct rte_eth_dev *dev;
633 if (rxq->rx_nb_avail)
634 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
636 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
637 rxq->rx_next_avail = 0;
638 rxq->rx_nb_avail = nb_rx;
639 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
641 if (rxq->rx_tail > rxq->rx_free_trigger) {
642 if (i40e_rx_alloc_bufs(rxq) != 0) {
645 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
646 dev->data->rx_mbuf_alloc_failed +=
649 rxq->rx_nb_avail = 0;
650 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
651 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
652 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
658 if (rxq->rx_tail >= rxq->nb_rx_desc)
661 if (rxq->rx_nb_avail)
662 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
668 i40e_recv_pkts_bulk_alloc(void *rx_queue,
669 struct rte_mbuf **rx_pkts,
672 uint16_t nb_rx = 0, n, count;
674 if (unlikely(nb_pkts == 0))
677 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
678 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
681 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
682 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
683 nb_rx = (uint16_t)(nb_rx + count);
684 nb_pkts = (uint16_t)(nb_pkts - count);
693 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
694 struct rte_mbuf __rte_unused **rx_pkts,
695 uint16_t __rte_unused nb_pkts)
699 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
702 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
704 struct i40e_rx_queue *rxq;
705 volatile union i40e_rx_desc *rx_ring;
706 volatile union i40e_rx_desc *rxdp;
707 union i40e_rx_desc rxd;
708 struct i40e_rx_entry *sw_ring;
709 struct i40e_rx_entry *rxe;
710 struct rte_eth_dev *dev;
711 struct rte_mbuf *rxm;
712 struct rte_mbuf *nmb;
716 uint16_t rx_packet_len;
717 uint16_t rx_id, nb_hold;
725 rx_id = rxq->rx_tail;
726 rx_ring = rxq->rx_ring;
727 sw_ring = rxq->sw_ring;
728 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
730 while (nb_rx < nb_pkts) {
731 rxdp = &rx_ring[rx_id];
732 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
733 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
734 >> I40E_RXD_QW1_STATUS_SHIFT;
736 /* Check the DD bit first */
737 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
740 nmb = rte_mbuf_raw_alloc(rxq->mp);
741 if (unlikely(!nmb)) {
742 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
743 dev->data->rx_mbuf_alloc_failed++;
748 * Use acquire fence to ensure that qword1 which includes DD
749 * bit is loaded before loading of other descriptor words.
751 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
755 rxe = &sw_ring[rx_id];
757 if (unlikely(rx_id == rxq->nb_rx_desc))
760 /* Prefetch next mbuf */
761 rte_prefetch0(sw_ring[rx_id].mbuf);
764 * When next RX descriptor is on a cache line boundary,
765 * prefetch the next 4 RX descriptors and next 8 pointers
768 if ((rx_id & 0x3) == 0) {
769 rte_prefetch0(&rx_ring[rx_id]);
770 rte_prefetch0(&sw_ring[rx_id]);
775 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
776 rxdp->read.hdr_addr = 0;
777 rxdp->read.pkt_addr = dma_addr;
779 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
780 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
782 rxm->data_off = RTE_PKTMBUF_HEADROOM;
783 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
786 rxm->pkt_len = rx_packet_len;
787 rxm->data_len = rx_packet_len;
788 rxm->port = rxq->port_id;
790 i40e_rxd_to_vlan_tci(rxm, &rxd);
791 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
792 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
794 ptype_tbl[(uint8_t)((qword1 &
795 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
796 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
798 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
799 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
800 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
802 #ifdef RTE_LIBRTE_IEEE1588
803 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
805 rxm->ol_flags |= pkt_flags;
807 rx_pkts[nb_rx++] = rxm;
809 rxq->rx_tail = rx_id;
812 * If the number of free RX descriptors is greater than the RX free
813 * threshold of the queue, advance the receive tail register of queue.
814 * Update that register with the value of the last processed RX
815 * descriptor minus 1.
817 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
818 if (nb_hold > rxq->rx_free_thresh) {
819 rx_id = (uint16_t) ((rx_id == 0) ?
820 (rxq->nb_rx_desc - 1) : (rx_id - 1));
821 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
824 rxq->nb_rx_hold = nb_hold;
830 i40e_recv_scattered_pkts(void *rx_queue,
831 struct rte_mbuf **rx_pkts,
834 struct i40e_rx_queue *rxq = rx_queue;
835 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
836 volatile union i40e_rx_desc *rxdp;
837 union i40e_rx_desc rxd;
838 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
839 struct i40e_rx_entry *rxe;
840 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
841 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
842 struct rte_mbuf *nmb, *rxm;
843 uint16_t rx_id = rxq->rx_tail;
844 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
845 struct rte_eth_dev *dev;
850 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
852 while (nb_rx < nb_pkts) {
853 rxdp = &rx_ring[rx_id];
854 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
855 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
856 I40E_RXD_QW1_STATUS_SHIFT;
858 /* Check the DD bit */
859 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
862 nmb = rte_mbuf_raw_alloc(rxq->mp);
863 if (unlikely(!nmb)) {
864 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
865 dev->data->rx_mbuf_alloc_failed++;
870 * Use acquire fence to ensure that qword1 which includes DD
871 * bit is loaded before loading of other descriptor words.
873 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
877 rxe = &sw_ring[rx_id];
879 if (rx_id == rxq->nb_rx_desc)
882 /* Prefetch next mbuf */
883 rte_prefetch0(sw_ring[rx_id].mbuf);
886 * When next RX descriptor is on a cache line boundary,
887 * prefetch the next 4 RX descriptors and next 8 pointers
890 if ((rx_id & 0x3) == 0) {
891 rte_prefetch0(&rx_ring[rx_id]);
892 rte_prefetch0(&sw_ring[rx_id]);
898 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
900 /* Set data buffer address and data length of the mbuf */
901 rxdp->read.hdr_addr = 0;
902 rxdp->read.pkt_addr = dma_addr;
903 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
904 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
905 rxm->data_len = rx_packet_len;
906 rxm->data_off = RTE_PKTMBUF_HEADROOM;
909 * If this is the first buffer of the received packet, set the
910 * pointer to the first mbuf of the packet and initialize its
911 * context. Otherwise, update the total length and the number
912 * of segments of the current scattered packet, and update the
913 * pointer to the last mbuf of the current packet.
917 first_seg->nb_segs = 1;
918 first_seg->pkt_len = rx_packet_len;
921 (uint16_t)(first_seg->pkt_len +
923 first_seg->nb_segs++;
924 last_seg->next = rxm;
928 * If this is not the last buffer of the received packet,
929 * update the pointer to the last mbuf of the current scattered
930 * packet and continue to parse the RX ring.
932 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
938 * This is the last buffer of the received packet. If the CRC
939 * is not stripped by the hardware:
940 * - Subtract the CRC length from the total packet length.
941 * - If the last buffer only contains the whole CRC or a part
942 * of it, free the mbuf associated to the last buffer. If part
943 * of the CRC is also contained in the previous mbuf, subtract
944 * the length of that CRC part from the data length of the
948 if (unlikely(rxq->crc_len > 0)) {
949 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
950 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
951 rte_pktmbuf_free_seg(rxm);
952 first_seg->nb_segs--;
954 (uint16_t)(last_seg->data_len -
955 (RTE_ETHER_CRC_LEN - rx_packet_len));
956 last_seg->next = NULL;
958 rxm->data_len = (uint16_t)(rx_packet_len -
962 first_seg->port = rxq->port_id;
963 first_seg->ol_flags = 0;
964 i40e_rxd_to_vlan_tci(first_seg, &rxd);
965 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
966 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
967 first_seg->packet_type =
968 ptype_tbl[(uint8_t)((qword1 &
969 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
970 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
971 first_seg->hash.rss =
972 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
973 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
974 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
976 #ifdef RTE_LIBRTE_IEEE1588
977 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
979 first_seg->ol_flags |= pkt_flags;
981 /* Prefetch data of first segment, if configured to do so. */
982 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
983 first_seg->data_off));
984 rx_pkts[nb_rx++] = first_seg;
988 /* Record index of the next RX descriptor to probe. */
989 rxq->rx_tail = rx_id;
990 rxq->pkt_first_seg = first_seg;
991 rxq->pkt_last_seg = last_seg;
994 * If the number of free RX descriptors is greater than the RX free
995 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
996 * register. Update the RDT with the value of the last processed RX
997 * descriptor minus 1, to guarantee that the RDT register is never
998 * equal to the RDH register, which creates a "full" ring situation
999 * from the hardware point of view.
1001 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1002 if (nb_hold > rxq->rx_free_thresh) {
1003 rx_id = (uint16_t)(rx_id == 0 ?
1004 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1005 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1008 rxq->nb_rx_hold = nb_hold;
1013 /* Check if the context descriptor is needed for TX offloading */
1014 static inline uint16_t
1015 i40e_calc_context_desc(uint64_t flags)
1017 static uint64_t mask = RTE_MBUF_F_TX_OUTER_IP_CKSUM |
1018 RTE_MBUF_F_TX_TCP_SEG |
1019 RTE_MBUF_F_TX_QINQ |
1020 RTE_MBUF_F_TX_TUNNEL_MASK;
1022 #ifdef RTE_LIBRTE_IEEE1588
1023 mask |= RTE_MBUF_F_TX_IEEE1588_TMST;
1026 return (flags & mask) ? 1 : 0;
1029 /* set i40e TSO context descriptor */
1030 static inline uint64_t
1031 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1033 uint64_t ctx_desc = 0;
1034 uint32_t cd_cmd, hdr_len, cd_tso_len;
1036 if (!tx_offload.l4_len) {
1037 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1041 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1042 hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
1043 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1045 cd_cmd = I40E_TX_CTX_DESC_TSO;
1046 cd_tso_len = mbuf->pkt_len - hdr_len;
1047 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1048 ((uint64_t)cd_tso_len <<
1049 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1050 ((uint64_t)mbuf->tso_segsz <<
1051 I40E_TXD_CTX_QW1_MSS_SHIFT);
1056 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1057 #define I40E_MAX_DATA_PER_TXD \
1058 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1059 /* Calculate the number of TX descriptors needed for each pkt */
1060 static inline uint16_t
1061 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1063 struct rte_mbuf *txd = tx_pkt;
1066 while (txd != NULL) {
1067 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1075 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1077 struct i40e_tx_queue *txq;
1078 struct i40e_tx_entry *sw_ring;
1079 struct i40e_tx_entry *txe, *txn;
1080 volatile struct i40e_tx_desc *txd;
1081 volatile struct i40e_tx_desc *txr;
1082 struct rte_mbuf *tx_pkt;
1083 struct rte_mbuf *m_seg;
1084 uint32_t cd_tunneling_params;
1095 uint64_t buf_dma_addr;
1096 union i40e_tx_offload tx_offload = {0};
1099 sw_ring = txq->sw_ring;
1101 tx_id = txq->tx_tail;
1102 txe = &sw_ring[tx_id];
1104 /* Check if the descriptor ring needs to be cleaned. */
1105 if (txq->nb_tx_free < txq->tx_free_thresh)
1106 (void)i40e_xmit_cleanup(txq);
1108 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1113 tx_pkt = *tx_pkts++;
1114 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1116 ol_flags = tx_pkt->ol_flags;
1117 tx_offload.l2_len = tx_pkt->l2_len;
1118 tx_offload.l3_len = tx_pkt->l3_len;
1119 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1120 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1121 tx_offload.l4_len = tx_pkt->l4_len;
1122 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1124 /* Calculate the number of context descriptors needed. */
1125 nb_ctx = i40e_calc_context_desc(ol_flags);
1128 * The number of descriptors that must be allocated for
1129 * a packet equals to the number of the segments of that
1130 * packet plus 1 context descriptor if needed.
1131 * Recalculate the needed tx descs when TSO enabled in case
1132 * the mbuf data size exceeds max data size that hw allows
1135 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1136 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1139 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1140 tx_last = (uint16_t)(tx_id + nb_used - 1);
1143 if (tx_last >= txq->nb_tx_desc)
1144 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1146 if (nb_used > txq->nb_tx_free) {
1147 if (i40e_xmit_cleanup(txq) != 0) {
1152 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1153 while (nb_used > txq->nb_tx_free) {
1154 if (i40e_xmit_cleanup(txq) != 0) {
1163 /* Descriptor based VLAN insertion */
1164 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
1165 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1166 td_tag = tx_pkt->vlan_tci;
1169 /* Always enable CRC offload insertion */
1170 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1172 /* Fill in tunneling parameters if necessary */
1173 cd_tunneling_params = 0;
1174 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
1175 i40e_parse_tunneling_params(ol_flags, tx_offload,
1176 &cd_tunneling_params);
1177 /* Enable checksum offloading */
1178 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1179 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1180 &td_offset, tx_offload);
1183 /* Setup TX context descriptor if required */
1184 volatile struct i40e_tx_context_desc *ctx_txd =
1185 (volatile struct i40e_tx_context_desc *)\
1187 uint16_t cd_l2tag2 = 0;
1188 uint64_t cd_type_cmd_tso_mss =
1189 I40E_TX_DESC_DTYPE_CONTEXT;
1191 txn = &sw_ring[txe->next_id];
1192 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1193 if (txe->mbuf != NULL) {
1194 rte_pktmbuf_free_seg(txe->mbuf);
1198 /* TSO enabled means no timestamp */
1199 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1200 cd_type_cmd_tso_mss |=
1201 i40e_set_tso_ctx(tx_pkt, tx_offload);
1203 #ifdef RTE_LIBRTE_IEEE1588
1204 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
1205 cd_type_cmd_tso_mss |=
1206 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1207 I40E_TXD_CTX_QW1_CMD_SHIFT);
1211 ctx_txd->tunneling_params =
1212 rte_cpu_to_le_32(cd_tunneling_params);
1213 if (ol_flags & RTE_MBUF_F_TX_QINQ) {
1214 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1215 cd_type_cmd_tso_mss |=
1216 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1217 I40E_TXD_CTX_QW1_CMD_SHIFT);
1219 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1220 ctx_txd->type_cmd_tso_mss =
1221 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1223 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1224 "tunneling_params: %#x;\n"
1227 "type_cmd_tso_mss: %#"PRIx64";\n",
1229 ctx_txd->tunneling_params,
1232 ctx_txd->type_cmd_tso_mss);
1234 txe->last_id = tx_last;
1235 tx_id = txe->next_id;
1242 txn = &sw_ring[txe->next_id];
1245 rte_pktmbuf_free_seg(txe->mbuf);
1248 /* Setup TX Descriptor */
1249 slen = m_seg->data_len;
1250 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1252 while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
1253 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1255 rte_cpu_to_le_64(buf_dma_addr);
1256 txd->cmd_type_offset_bsz =
1257 i40e_build_ctob(td_cmd,
1258 td_offset, I40E_MAX_DATA_PER_TXD,
1261 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1262 slen -= I40E_MAX_DATA_PER_TXD;
1264 txe->last_id = tx_last;
1265 tx_id = txe->next_id;
1268 txn = &sw_ring[txe->next_id];
1270 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1271 "buf_dma_addr: %#"PRIx64";\n"
1276 tx_pkt, tx_id, buf_dma_addr,
1277 td_cmd, td_offset, slen, td_tag);
1279 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1280 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1281 td_offset, slen, td_tag);
1282 txe->last_id = tx_last;
1283 tx_id = txe->next_id;
1285 m_seg = m_seg->next;
1286 } while (m_seg != NULL);
1288 /* The last packet data descriptor needs End Of Packet (EOP) */
1289 td_cmd |= I40E_TX_DESC_CMD_EOP;
1290 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1291 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1293 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1295 "Setting RS bit on TXD id="
1296 "%4u (port=%d queue=%d)",
1297 tx_last, txq->port_id, txq->queue_id);
1299 td_cmd |= I40E_TX_DESC_CMD_RS;
1301 /* Update txq RS bit counters */
1302 txq->nb_tx_used = 0;
1305 txd->cmd_type_offset_bsz |=
1306 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1307 I40E_TXD_QW1_CMD_SHIFT);
1311 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1312 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1313 (unsigned) tx_id, (unsigned) nb_tx);
1316 I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1317 txq->tx_tail = tx_id;
1322 static __rte_always_inline int
1323 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1325 struct i40e_tx_entry *txep;
1326 uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1327 uint16_t i = 0, j = 0;
1328 struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1329 const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1330 const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1332 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1333 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1334 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1337 txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1339 for (i = 0; i < tx_rs_thresh; i++)
1340 rte_prefetch0((txep + i)->mbuf);
1342 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
1344 for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1345 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1346 free[i] = txep->mbuf;
1349 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1350 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1355 for (i = 0; i < m; ++i, ++txep) {
1356 free[i] = txep->mbuf;
1359 rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1362 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1363 rte_pktmbuf_free_seg(txep->mbuf);
1368 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1369 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1370 if (txq->tx_next_dd >= txq->nb_tx_desc)
1371 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1373 return txq->tx_rs_thresh;
1376 /* Populate 4 descriptors with data from 4 mbufs */
1378 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1383 for (i = 0; i < 4; i++, txdp++, pkts++) {
1384 dma_addr = rte_mbuf_data_iova(*pkts);
1385 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1386 txdp->cmd_type_offset_bsz =
1387 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1388 (*pkts)->data_len, 0);
1392 /* Populate 1 descriptor with data from 1 mbuf */
1394 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1398 dma_addr = rte_mbuf_data_iova(*pkts);
1399 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1400 txdp->cmd_type_offset_bsz =
1401 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1402 (*pkts)->data_len, 0);
1405 /* Fill hardware descriptor ring with mbuf data */
1407 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1408 struct rte_mbuf **pkts,
1411 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1412 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1413 const int N_PER_LOOP = 4;
1414 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1415 int mainpart, leftover;
1418 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1419 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1420 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1421 for (j = 0; j < N_PER_LOOP; ++j) {
1422 (txep + i + j)->mbuf = *(pkts + i + j);
1424 tx4(txdp + i, pkts + i);
1426 if (unlikely(leftover > 0)) {
1427 for (i = 0; i < leftover; ++i) {
1428 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1429 tx1(txdp + mainpart + i, pkts + mainpart + i);
1434 static inline uint16_t
1435 tx_xmit_pkts(struct i40e_tx_queue *txq,
1436 struct rte_mbuf **tx_pkts,
1439 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1443 * Begin scanning the H/W ring for done descriptors when the number
1444 * of available descriptors drops below tx_free_thresh. For each done
1445 * descriptor, free the associated buffer.
1447 if (txq->nb_tx_free < txq->tx_free_thresh)
1448 i40e_tx_free_bufs(txq);
1450 /* Use available descriptor only */
1451 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1452 if (unlikely(!nb_pkts))
1455 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1456 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1457 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1458 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1459 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1460 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1461 I40E_TXD_QW1_CMD_SHIFT);
1462 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1466 /* Fill hardware descriptor ring with mbuf data */
1467 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1468 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1470 /* Determine if RS bit needs to be set */
1471 if (txq->tx_tail > txq->tx_next_rs) {
1472 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1473 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1474 I40E_TXD_QW1_CMD_SHIFT);
1476 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1477 if (txq->tx_next_rs >= txq->nb_tx_desc)
1478 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1481 if (txq->tx_tail >= txq->nb_tx_desc)
1484 /* Update the tx tail register */
1485 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1491 i40e_xmit_pkts_simple(void *tx_queue,
1492 struct rte_mbuf **tx_pkts,
1497 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1498 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1502 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1505 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1506 &tx_pkts[nb_tx], num);
1507 nb_tx = (uint16_t)(nb_tx + ret);
1508 nb_pkts = (uint16_t)(nb_pkts - ret);
1517 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1521 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1526 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1527 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1538 /*********************************************************************
1540 * TX simple prep functions
1542 **********************************************************************/
1544 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1551 for (i = 0; i < nb_pkts; i++) {
1553 ol_flags = m->ol_flags;
1555 if (m->nb_segs != 1) {
1560 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1561 rte_errno = ENOTSUP;
1565 /* check the size of packet */
1566 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1567 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1575 /*********************************************************************
1579 **********************************************************************/
1581 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1588 for (i = 0; i < nb_pkts; i++) {
1590 ol_flags = m->ol_flags;
1592 /* Check for m->nb_segs to not exceed the limits. */
1593 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
1594 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1595 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1599 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1600 m->tso_segsz < I40E_MIN_TSO_MSS ||
1601 m->tso_segsz > I40E_MAX_TSO_MSS ||
1602 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1603 /* MSS outside the range (256B - 9674B) are considered
1610 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1611 rte_errno = ENOTSUP;
1615 /* check the size of packet */
1616 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1621 #ifdef RTE_ETHDEV_DEBUG_TX
1622 ret = rte_validate_tx_offload(m);
1628 ret = rte_net_intel_cksum_prepare(m);
1638 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1639 * application used, which assume having sequential ones. But from driver's
1640 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1641 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1642 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1643 * use queue_idx from 0 to 95 to access queues, while real queue would be
1644 * different. This function will do a queue mapping to find VSI the queue
1647 static struct i40e_vsi*
1648 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1650 /* the queue in MAIN VSI range */
1651 if (queue_idx < pf->main_vsi->nb_qps)
1652 return pf->main_vsi;
1654 queue_idx -= pf->main_vsi->nb_qps;
1656 /* queue_idx is greater than VMDQ VSIs range */
1657 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1658 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1662 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1666 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1668 /* the queue in MAIN VSI range */
1669 if (queue_idx < pf->main_vsi->nb_qps)
1672 /* It's VMDQ queues */
1673 queue_idx -= pf->main_vsi->nb_qps;
1675 if (pf->nb_cfg_vmdq_vsi)
1676 return queue_idx % pf->vmdq_nb_qps;
1678 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1679 return (uint16_t)(-1);
1684 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1686 struct i40e_rx_queue *rxq;
1688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690 PMD_INIT_FUNC_TRACE();
1692 rxq = dev->data->rx_queues[rx_queue_id];
1693 if (!rxq || !rxq->q_set) {
1694 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1699 if (rxq->rx_deferred_start)
1700 PMD_DRV_LOG(WARNING, "RX queue %u is deferred start",
1703 err = i40e_alloc_rx_queue_mbufs(rxq);
1705 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1709 /* Init the RX tail register. */
1710 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1712 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1714 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1717 i40e_rx_queue_release_mbufs(rxq);
1718 i40e_reset_rx_queue(rxq);
1721 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1727 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1729 struct i40e_rx_queue *rxq;
1731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733 rxq = dev->data->rx_queues[rx_queue_id];
1734 if (!rxq || !rxq->q_set) {
1735 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1741 * rx_queue_id is queue id application refers to, while
1742 * rxq->reg_idx is the real queue index.
1744 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1746 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1750 i40e_rx_queue_release_mbufs(rxq);
1751 i40e_reset_rx_queue(rxq);
1752 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1758 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1761 struct i40e_tx_queue *txq;
1762 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764 PMD_INIT_FUNC_TRACE();
1766 txq = dev->data->tx_queues[tx_queue_id];
1767 if (!txq || !txq->q_set) {
1768 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1773 if (txq->tx_deferred_start)
1774 PMD_DRV_LOG(WARNING, "TX queue %u is deferred start",
1778 * tx_queue_id is queue id application refers to, while
1779 * rxq->reg_idx is the real queue index.
1781 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1783 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1787 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1793 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1795 struct i40e_tx_queue *txq;
1797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799 txq = dev->data->tx_queues[tx_queue_id];
1800 if (!txq || !txq->q_set) {
1801 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1807 * tx_queue_id is queue id application refers to, while
1808 * txq->reg_idx is the real queue index.
1810 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1812 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1817 i40e_tx_queue_release_mbufs(txq);
1818 i40e_reset_tx_queue(txq);
1819 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1825 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1827 static const uint32_t ptypes[] = {
1828 /* refers to i40e_rxd_pkt_type_mapping() */
1830 RTE_PTYPE_L2_ETHER_TIMESYNC,
1831 RTE_PTYPE_L2_ETHER_LLDP,
1832 RTE_PTYPE_L2_ETHER_ARP,
1833 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1834 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1837 RTE_PTYPE_L4_NONFRAG,
1841 RTE_PTYPE_TUNNEL_GRENAT,
1842 RTE_PTYPE_TUNNEL_IP,
1843 RTE_PTYPE_INNER_L2_ETHER,
1844 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1845 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1846 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1847 RTE_PTYPE_INNER_L4_FRAG,
1848 RTE_PTYPE_INNER_L4_ICMP,
1849 RTE_PTYPE_INNER_L4_NONFRAG,
1850 RTE_PTYPE_INNER_L4_SCTP,
1851 RTE_PTYPE_INNER_L4_TCP,
1852 RTE_PTYPE_INNER_L4_UDP,
1856 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1857 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1858 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1860 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1861 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1862 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1863 #ifdef CC_AVX512_SUPPORT
1864 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1865 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1867 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1868 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1874 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1878 for (i = 0; i < num; i++) {
1879 if (i != idx && queues[i])
1887 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1888 struct i40e_rx_queue *rxq)
1890 struct i40e_adapter *ad =
1891 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1892 int use_def_burst_func =
1893 check_rx_burst_bulk_alloc_preconditions(rxq);
1895 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1896 RTE_PKTMBUF_HEADROOM);
1897 int use_scattered_rx =
1898 (rxq->max_pkt_len > buf_size);
1900 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1902 "Failed to do RX queue initialization");
1906 if (i40e_dev_first_queue(rxq->queue_id,
1907 dev->data->rx_queues,
1908 dev->data->nb_rx_queues)) {
1910 * If it is the first queue to setup,
1911 * set all flags to default and call
1912 * i40e_set_rx_function.
1914 ad->rx_bulk_alloc_allowed = true;
1915 ad->rx_vec_allowed = true;
1916 dev->data->scattered_rx = use_scattered_rx;
1917 if (use_def_burst_func)
1918 ad->rx_bulk_alloc_allowed = false;
1919 i40e_set_rx_function(dev);
1921 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1922 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1923 " number %d of queue %d isn't power of 2",
1924 rxq->nb_rx_desc, rxq->queue_id);
1928 /* check bulk alloc conflict */
1929 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1930 PMD_DRV_LOG(ERR, "Can't use default burst.");
1933 /* check scattered conflict */
1934 if (!dev->data->scattered_rx && use_scattered_rx) {
1935 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1938 /* check vector conflict */
1939 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1940 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1948 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1951 unsigned int socket_id,
1952 const struct rte_eth_rxconf *rx_conf,
1953 struct rte_mempool *mp)
1955 struct i40e_adapter *ad =
1956 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1957 struct i40e_vsi *vsi;
1958 struct i40e_pf *pf = NULL;
1959 struct i40e_rx_queue *rxq;
1960 const struct rte_memzone *rz;
1963 uint16_t reg_idx, base, bsf, tc_mapping;
1964 int q_offset, use_def_burst_func = 1;
1967 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1969 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1970 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1973 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1976 reg_idx = vsi->base_queue + q_offset;
1978 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1979 (nb_desc > I40E_MAX_RING_DESC) ||
1980 (nb_desc < I40E_MIN_RING_DESC)) {
1981 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1982 "invalid", nb_desc);
1986 /* Free memory if needed */
1987 if (dev->data->rx_queues[queue_idx]) {
1988 i40e_rx_queue_release(dev->data->rx_queues[queue_idx]);
1989 dev->data->rx_queues[queue_idx] = NULL;
1992 /* Allocate the rx queue data structure */
1993 rxq = rte_zmalloc_socket("i40e rx queue",
1994 sizeof(struct i40e_rx_queue),
1995 RTE_CACHE_LINE_SIZE,
1998 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1999 "rx queue data structure");
2003 rxq->nb_rx_desc = nb_desc;
2004 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2005 rxq->queue_id = queue_idx;
2006 rxq->reg_idx = reg_idx;
2007 rxq->port_id = dev->data->port_id;
2008 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2009 rxq->crc_len = RTE_ETHER_CRC_LEN;
2012 rxq->drop_en = rx_conf->rx_drop_en;
2014 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2015 rxq->offloads = offloads;
2017 /* Allocate the maximum number of RX ring hardware descriptor. */
2018 len = I40E_MAX_RING_DESC;
2021 * Allocating a little more memory because vectorized/bulk_alloc Rx
2022 * functions doesn't check boundaries each time.
2024 len += RTE_PMD_I40E_RX_MAX_BURST;
2026 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2027 I40E_DMA_MEM_ALIGN);
2029 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2030 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2032 i40e_rx_queue_release(rxq);
2033 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2038 /* Zero all the descriptors in the ring. */
2039 memset(rz->addr, 0, ring_size);
2041 rxq->rx_ring_phys_addr = rz->iova;
2042 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2044 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2046 /* Allocate the software ring. */
2048 rte_zmalloc_socket("i40e rx sw ring",
2049 sizeof(struct i40e_rx_entry) * len,
2050 RTE_CACHE_LINE_SIZE,
2052 if (!rxq->sw_ring) {
2053 i40e_rx_queue_release(rxq);
2054 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2058 i40e_reset_rx_queue(rxq);
2061 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2062 if (!(vsi->enabled_tc & (1 << i)))
2064 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2065 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2066 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2067 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2068 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2070 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2074 if (dev->data->dev_started) {
2075 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2076 i40e_rx_queue_release(rxq);
2080 use_def_burst_func =
2081 check_rx_burst_bulk_alloc_preconditions(rxq);
2082 if (!use_def_burst_func) {
2083 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2085 "Rx Burst Bulk Alloc Preconditions are "
2086 "satisfied. Rx Burst Bulk Alloc function will be "
2087 "used on port=%d, queue=%d.",
2088 rxq->port_id, rxq->queue_id);
2089 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2092 "Rx Burst Bulk Alloc Preconditions are "
2093 "not satisfied, Scattered Rx is requested, "
2094 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2095 "not enabled on port=%d, queue=%d.",
2096 rxq->port_id, rxq->queue_id);
2097 ad->rx_bulk_alloc_allowed = false;
2101 dev->data->rx_queues[queue_idx] = rxq;
2106 i40e_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2108 i40e_rx_queue_release(dev->data->rx_queues[qid]);
2112 i40e_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2114 i40e_tx_queue_release(dev->data->tx_queues[qid]);
2118 i40e_rx_queue_release(void *rxq)
2120 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2123 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2127 i40e_rx_queue_release_mbufs(q);
2128 rte_free(q->sw_ring);
2129 rte_memzone_free(q->mz);
2134 i40e_dev_rx_queue_count(void *rx_queue)
2136 #define I40E_RXQ_SCAN_INTERVAL 4
2137 volatile union i40e_rx_desc *rxdp;
2138 struct i40e_rx_queue *rxq;
2142 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2143 while ((desc < rxq->nb_rx_desc) &&
2144 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2145 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2146 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2148 * Check the DD bit of a rx descriptor of each 4 in a group,
2149 * to avoid checking too frequently and downgrading performance
2152 desc += I40E_RXQ_SCAN_INTERVAL;
2153 rxdp += I40E_RXQ_SCAN_INTERVAL;
2154 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2155 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2156 desc - rxq->nb_rx_desc]);
2163 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2165 struct i40e_rx_queue *rxq = rx_queue;
2166 volatile uint64_t *status;
2170 if (unlikely(offset >= rxq->nb_rx_desc))
2173 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2174 return RTE_ETH_RX_DESC_UNAVAIL;
2176 desc = rxq->rx_tail + offset;
2177 if (desc >= rxq->nb_rx_desc)
2178 desc -= rxq->nb_rx_desc;
2180 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2181 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2182 << I40E_RXD_QW1_STATUS_SHIFT);
2184 return RTE_ETH_RX_DESC_DONE;
2186 return RTE_ETH_RX_DESC_AVAIL;
2190 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2192 struct i40e_tx_queue *txq = tx_queue;
2193 volatile uint64_t *status;
2194 uint64_t mask, expect;
2197 if (unlikely(offset >= txq->nb_tx_desc))
2200 desc = txq->tx_tail + offset;
2201 /* go to next desc that has the RS bit */
2202 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2204 if (desc >= txq->nb_tx_desc) {
2205 desc -= txq->nb_tx_desc;
2206 if (desc >= txq->nb_tx_desc)
2207 desc -= txq->nb_tx_desc;
2210 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2211 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2212 expect = rte_cpu_to_le_64(
2213 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2214 if ((*status & mask) == expect)
2215 return RTE_ETH_TX_DESC_DONE;
2217 return RTE_ETH_TX_DESC_FULL;
2221 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2222 struct i40e_tx_queue *txq)
2224 struct i40e_adapter *ad =
2225 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2227 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2229 "Failed to do TX queue initialization");
2233 if (i40e_dev_first_queue(txq->queue_id,
2234 dev->data->tx_queues,
2235 dev->data->nb_tx_queues)) {
2237 * If it is the first queue to setup,
2238 * set all flags and call
2239 * i40e_set_tx_function.
2241 i40e_set_tx_function_flag(dev, txq);
2242 i40e_set_tx_function(dev);
2246 /* check vector conflict */
2247 if (ad->tx_vec_allowed) {
2248 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2249 i40e_txq_vec_setup(txq)) {
2250 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2254 /* check simple tx conflict */
2255 if (ad->tx_simple_allowed) {
2256 if ((txq->offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2257 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2258 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2267 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2270 unsigned int socket_id,
2271 const struct rte_eth_txconf *tx_conf)
2273 struct i40e_vsi *vsi;
2274 struct i40e_pf *pf = NULL;
2275 struct i40e_tx_queue *txq;
2276 const struct rte_memzone *tz;
2278 uint16_t tx_rs_thresh, tx_free_thresh;
2279 uint16_t reg_idx, i, base, bsf, tc_mapping;
2283 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2285 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2289 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2292 reg_idx = vsi->base_queue + q_offset;
2294 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2295 (nb_desc > I40E_MAX_RING_DESC) ||
2296 (nb_desc < I40E_MIN_RING_DESC)) {
2297 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2298 "invalid", nb_desc);
2303 * The following two parameters control the setting of the RS bit on
2304 * transmit descriptors. TX descriptors will have their RS bit set
2305 * after txq->tx_rs_thresh descriptors have been used. The TX
2306 * descriptor ring will be cleaned after txq->tx_free_thresh
2307 * descriptors are used or if the number of descriptors required to
2308 * transmit a packet is greater than the number of free TX descriptors.
2310 * The following constraints must be satisfied:
2311 * - tx_rs_thresh must be greater than 0.
2312 * - tx_rs_thresh must be less than the size of the ring minus 2.
2313 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2314 * - tx_rs_thresh must be a divisor of the ring size.
2315 * - tx_free_thresh must be greater than 0.
2316 * - tx_free_thresh must be less than the size of the ring minus 3.
2317 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2319 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2320 * race condition, hence the maximum threshold constraints. When set
2321 * to zero use default values.
2323 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2324 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2325 /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
2326 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2327 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2328 if (tx_conf->tx_rs_thresh > 0)
2329 tx_rs_thresh = tx_conf->tx_rs_thresh;
2330 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2331 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2332 "exceed nb_desc. (tx_rs_thresh=%u "
2333 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2334 (unsigned int)tx_rs_thresh,
2335 (unsigned int)tx_free_thresh,
2336 (unsigned int)nb_desc,
2337 (int)dev->data->port_id,
2339 return I40E_ERR_PARAM;
2341 if (tx_rs_thresh >= (nb_desc - 2)) {
2342 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2343 "number of TX descriptors minus 2. "
2344 "(tx_rs_thresh=%u port=%d queue=%d)",
2345 (unsigned int)tx_rs_thresh,
2346 (int)dev->data->port_id,
2348 return I40E_ERR_PARAM;
2350 if (tx_free_thresh >= (nb_desc - 3)) {
2351 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2352 "number of TX descriptors minus 3. "
2353 "(tx_free_thresh=%u port=%d queue=%d)",
2354 (unsigned int)tx_free_thresh,
2355 (int)dev->data->port_id,
2357 return I40E_ERR_PARAM;
2359 if (tx_rs_thresh > tx_free_thresh) {
2360 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2361 "equal to tx_free_thresh. (tx_free_thresh=%u"
2362 " tx_rs_thresh=%u port=%d queue=%d)",
2363 (unsigned int)tx_free_thresh,
2364 (unsigned int)tx_rs_thresh,
2365 (int)dev->data->port_id,
2367 return I40E_ERR_PARAM;
2369 if ((nb_desc % tx_rs_thresh) != 0) {
2370 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2371 "number of TX descriptors. (tx_rs_thresh=%u"
2372 " port=%d queue=%d)",
2373 (unsigned int)tx_rs_thresh,
2374 (int)dev->data->port_id,
2376 return I40E_ERR_PARAM;
2378 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2379 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2380 "tx_rs_thresh is greater than 1. "
2381 "(tx_rs_thresh=%u port=%d queue=%d)",
2382 (unsigned int)tx_rs_thresh,
2383 (int)dev->data->port_id,
2385 return I40E_ERR_PARAM;
2388 /* Free memory if needed. */
2389 if (dev->data->tx_queues[queue_idx]) {
2390 i40e_tx_queue_release(dev->data->tx_queues[queue_idx]);
2391 dev->data->tx_queues[queue_idx] = NULL;
2394 /* Allocate the TX queue data structure. */
2395 txq = rte_zmalloc_socket("i40e tx queue",
2396 sizeof(struct i40e_tx_queue),
2397 RTE_CACHE_LINE_SIZE,
2400 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2401 "tx queue structure");
2405 /* Allocate TX hardware ring descriptors. */
2406 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2407 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2408 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2409 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2411 i40e_tx_queue_release(txq);
2412 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2417 txq->nb_tx_desc = nb_desc;
2418 txq->tx_rs_thresh = tx_rs_thresh;
2419 txq->tx_free_thresh = tx_free_thresh;
2420 txq->pthresh = tx_conf->tx_thresh.pthresh;
2421 txq->hthresh = tx_conf->tx_thresh.hthresh;
2422 txq->wthresh = tx_conf->tx_thresh.wthresh;
2423 txq->queue_id = queue_idx;
2424 txq->reg_idx = reg_idx;
2425 txq->port_id = dev->data->port_id;
2426 txq->offloads = offloads;
2428 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2430 txq->tx_ring_phys_addr = tz->iova;
2431 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2433 /* Allocate software ring */
2435 rte_zmalloc_socket("i40e tx sw ring",
2436 sizeof(struct i40e_tx_entry) * nb_desc,
2437 RTE_CACHE_LINE_SIZE,
2439 if (!txq->sw_ring) {
2440 i40e_tx_queue_release(txq);
2441 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2445 i40e_reset_tx_queue(txq);
2448 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2449 if (!(vsi->enabled_tc & (1 << i)))
2451 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2452 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2453 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2454 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2455 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2457 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2461 if (dev->data->dev_started) {
2462 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2463 i40e_tx_queue_release(txq);
2468 * Use a simple TX queue without offloads or
2469 * multi segs if possible
2471 i40e_set_tx_function_flag(dev, txq);
2473 dev->data->tx_queues[queue_idx] = txq;
2479 i40e_tx_queue_release(void *txq)
2481 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2484 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2488 i40e_tx_queue_release_mbufs(q);
2489 rte_free(q->sw_ring);
2490 rte_memzone_free(q->mz);
2494 const struct rte_memzone *
2495 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2497 const struct rte_memzone *mz;
2499 mz = rte_memzone_lookup(name);
2503 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2504 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2509 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2513 /* SSE Vector driver has a different way of releasing mbufs. */
2514 if (rxq->rx_using_sse) {
2515 i40e_rx_queue_release_mbufs_vec(rxq);
2519 if (!rxq->sw_ring) {
2520 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2524 for (i = 0; i < rxq->nb_rx_desc; i++) {
2525 if (rxq->sw_ring[i].mbuf) {
2526 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2527 rxq->sw_ring[i].mbuf = NULL;
2530 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2531 if (rxq->rx_nb_avail == 0)
2533 for (i = 0; i < rxq->rx_nb_avail; i++) {
2534 struct rte_mbuf *mbuf;
2536 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2537 rte_pktmbuf_free_seg(mbuf);
2539 rxq->rx_nb_avail = 0;
2540 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2544 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2550 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2554 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2555 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2556 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2558 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2559 len = rxq->nb_rx_desc;
2561 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2562 ((volatile char *)rxq->rx_ring)[i] = 0;
2564 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2565 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2566 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2568 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2569 rxq->rx_nb_avail = 0;
2570 rxq->rx_next_avail = 0;
2571 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2572 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2574 rxq->nb_rx_hold = 0;
2576 rte_pktmbuf_free(rxq->pkt_first_seg);
2578 rxq->pkt_first_seg = NULL;
2579 rxq->pkt_last_seg = NULL;
2581 rxq->rxrearm_start = 0;
2582 rxq->rxrearm_nb = 0;
2586 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2588 struct rte_eth_dev *dev;
2591 if (!txq || !txq->sw_ring) {
2592 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2596 dev = &rte_eth_devices[txq->port_id];
2599 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2600 * so need to free remains more carefully.
2602 #ifdef CC_AVX512_SUPPORT
2603 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2604 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2606 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2607 if (txq->tx_tail < i) {
2608 for (; i < txq->nb_tx_desc; i++) {
2609 rte_pktmbuf_free_seg(swr[i].mbuf);
2614 for (; i < txq->tx_tail; i++) {
2615 rte_pktmbuf_free_seg(swr[i].mbuf);
2621 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2622 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2623 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2624 if (txq->tx_tail < i) {
2625 for (; i < txq->nb_tx_desc; i++) {
2626 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2627 txq->sw_ring[i].mbuf = NULL;
2631 for (; i < txq->tx_tail; i++) {
2632 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2633 txq->sw_ring[i].mbuf = NULL;
2636 for (i = 0; i < txq->nb_tx_desc; i++) {
2637 if (txq->sw_ring[i].mbuf) {
2638 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2639 txq->sw_ring[i].mbuf = NULL;
2646 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2649 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2650 uint16_t i, tx_last, tx_id;
2651 uint16_t nb_tx_free_last;
2652 uint16_t nb_tx_to_clean;
2655 /* Start free mbuf from the next of tx_tail */
2656 tx_last = txq->tx_tail;
2657 tx_id = swr_ring[tx_last].next_id;
2659 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2662 nb_tx_to_clean = txq->nb_tx_free;
2663 nb_tx_free_last = txq->nb_tx_free;
2665 free_cnt = txq->nb_tx_desc;
2667 /* Loop through swr_ring to count the amount of
2668 * freeable mubfs and packets.
2670 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2671 for (i = 0; i < nb_tx_to_clean &&
2672 pkt_cnt < free_cnt &&
2673 tx_id != tx_last; i++) {
2674 if (swr_ring[tx_id].mbuf != NULL) {
2675 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2676 swr_ring[tx_id].mbuf = NULL;
2679 * last segment in the packet,
2680 * increment packet count
2682 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2685 tx_id = swr_ring[tx_id].next_id;
2688 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2689 txq->nb_tx_free || tx_id == tx_last)
2692 if (pkt_cnt < free_cnt) {
2693 if (i40e_xmit_cleanup(txq))
2696 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2697 nb_tx_free_last = txq->nb_tx_free;
2701 return (int)pkt_cnt;
2705 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2710 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2711 free_cnt = txq->nb_tx_desc;
2713 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2715 for (i = 0; i < cnt; i += n) {
2716 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2719 n = i40e_tx_free_bufs(txq);
2729 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2730 uint32_t free_cnt __rte_unused)
2735 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2737 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2738 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2739 struct i40e_adapter *ad =
2740 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2742 if (ad->tx_simple_allowed) {
2743 if (ad->tx_vec_allowed)
2744 return i40e_tx_done_cleanup_vec(q, free_cnt);
2746 return i40e_tx_done_cleanup_simple(q, free_cnt);
2748 return i40e_tx_done_cleanup_full(q, free_cnt);
2753 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2755 struct i40e_tx_entry *txe;
2756 uint16_t i, prev, size;
2759 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2764 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2765 for (i = 0; i < size; i++)
2766 ((volatile char *)txq->tx_ring)[i] = 0;
2768 prev = (uint16_t)(txq->nb_tx_desc - 1);
2769 for (i = 0; i < txq->nb_tx_desc; i++) {
2770 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2772 txd->cmd_type_offset_bsz =
2773 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2776 txe[prev].next_id = i;
2780 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2781 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2784 txq->nb_tx_used = 0;
2786 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2787 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2790 /* Init the TX queue in hardware */
2792 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2794 enum i40e_status_code err = I40E_SUCCESS;
2795 struct i40e_vsi *vsi = txq->vsi;
2796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2797 uint16_t pf_q = txq->reg_idx;
2798 struct i40e_hmc_obj_txq tx_ctx;
2801 /* clear the context structure first */
2802 memset(&tx_ctx, 0, sizeof(tx_ctx));
2803 tx_ctx.new_context = 1;
2804 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2805 tx_ctx.qlen = txq->nb_tx_desc;
2807 #ifdef RTE_LIBRTE_IEEE1588
2808 tx_ctx.timesync_ena = 1;
2810 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2811 if (vsi->type == I40E_VSI_FDIR)
2812 tx_ctx.fd_ena = TRUE;
2814 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2815 if (err != I40E_SUCCESS) {
2816 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2820 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2821 if (err != I40E_SUCCESS) {
2822 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2826 /* Now associate this queue with this PCI function */
2827 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2828 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2829 I40E_QTX_CTL_PF_INDX_MASK);
2830 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2831 I40E_WRITE_FLUSH(hw);
2833 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2839 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2841 struct i40e_rx_entry *rxe = rxq->sw_ring;
2845 for (i = 0; i < rxq->nb_rx_desc; i++) {
2846 volatile union i40e_rx_desc *rxd;
2847 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2849 if (unlikely(!mbuf)) {
2850 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2854 rte_mbuf_refcnt_set(mbuf, 1);
2856 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2858 mbuf->port = rxq->port_id;
2861 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2863 rxd = &rxq->rx_ring[i];
2864 rxd->read.pkt_addr = dma_addr;
2865 rxd->read.hdr_addr = 0;
2866 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2867 rxd->read.rsvd1 = 0;
2868 rxd->read.rsvd2 = 0;
2869 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2878 * Calculate the buffer length, and check the jumbo frame
2879 * and maximum packet length.
2882 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2884 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2885 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2886 struct rte_eth_dev_data *data = pf->dev_data;
2889 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2890 RTE_PKTMBUF_HEADROOM);
2892 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2893 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2894 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2895 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2896 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2897 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2898 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2899 rxq->hs_mode = i40e_header_split_enabled;
2901 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2903 rxq->rx_hdr_len = 0;
2904 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2905 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2906 rxq->hs_mode = i40e_header_split_none;
2911 RTE_MIN(hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len,
2912 data->mtu + I40E_ETH_OVERHEAD);
2913 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2914 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2915 PMD_DRV_LOG(ERR, "maximum packet length must be "
2916 "larger than %u and smaller than %u",
2917 (uint32_t)RTE_ETHER_MIN_LEN,
2918 (uint32_t)I40E_FRAME_SIZE_MAX);
2919 return I40E_ERR_CONFIG;
2925 /* Init the RX queue in hardware */
2927 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2929 int err = I40E_SUCCESS;
2930 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2931 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2932 uint16_t pf_q = rxq->reg_idx;
2934 struct i40e_hmc_obj_rxq rx_ctx;
2936 err = i40e_rx_queue_config(rxq);
2938 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2942 /* Clear the context structure first */
2943 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2944 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2945 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2947 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2948 rx_ctx.qlen = rxq->nb_rx_desc;
2949 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2952 rx_ctx.dtype = rxq->hs_mode;
2954 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2956 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2957 rx_ctx.rxmax = rxq->max_pkt_len;
2958 rx_ctx.tphrdesc_ena = 1;
2959 rx_ctx.tphwdesc_ena = 1;
2960 rx_ctx.tphdata_ena = 1;
2961 rx_ctx.tphhead_ena = 1;
2962 rx_ctx.lrxqthresh = 2;
2963 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2965 /* showiv indicates if inner VLAN is stripped inside of tunnel
2966 * packet. When set it to 1, vlan information is stripped from
2967 * the inner header, but the hardware does not put it in the
2968 * descriptor. So set it zero by default.
2973 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2974 if (err != I40E_SUCCESS) {
2975 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2978 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2979 if (err != I40E_SUCCESS) {
2980 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2984 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2986 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2987 RTE_PKTMBUF_HEADROOM);
2989 /* Check if scattered RX needs to be used. */
2990 if (rxq->max_pkt_len > buf_size)
2991 dev_data->scattered_rx = 1;
2993 /* Init the RX tail register. */
2994 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3000 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3004 PMD_INIT_FUNC_TRACE();
3006 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3007 if (!dev->data->tx_queues[i])
3009 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3010 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3013 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3014 if (!dev->data->rx_queues[i])
3016 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3017 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3022 i40e_dev_free_queues(struct rte_eth_dev *dev)
3026 PMD_INIT_FUNC_TRACE();
3028 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3029 if (!dev->data->rx_queues[i])
3031 i40e_rx_queue_release(dev->data->rx_queues[i]);
3032 dev->data->rx_queues[i] = NULL;
3035 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3036 if (!dev->data->tx_queues[i])
3038 i40e_tx_queue_release(dev->data->tx_queues[i]);
3039 dev->data->tx_queues[i] = NULL;
3043 enum i40e_status_code
3044 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3046 struct i40e_tx_queue *txq;
3047 const struct rte_memzone *tz = NULL;
3048 struct rte_eth_dev *dev;
3052 PMD_DRV_LOG(ERR, "PF is not available");
3053 return I40E_ERR_BAD_PTR;
3056 dev = &rte_eth_devices[pf->dev_data->port_id];
3058 /* Allocate the TX queue data structure. */
3059 txq = rte_zmalloc_socket("i40e fdir tx queue",
3060 sizeof(struct i40e_tx_queue),
3061 RTE_CACHE_LINE_SIZE,
3064 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3065 "tx queue structure.");
3066 return I40E_ERR_NO_MEMORY;
3069 /* Allocate TX hardware ring descriptors. */
3070 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3071 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3073 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3074 I40E_FDIR_QUEUE_ID, ring_size,
3075 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3077 i40e_tx_queue_release(txq);
3078 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3079 return I40E_ERR_NO_MEMORY;
3083 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3084 txq->queue_id = I40E_FDIR_QUEUE_ID;
3085 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3086 txq->vsi = pf->fdir.fdir_vsi;
3088 txq->tx_ring_phys_addr = tz->iova;
3089 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3092 * don't need to allocate software ring and reset for the fdir
3093 * program queue just set the queue has been configured.
3097 pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3099 return I40E_SUCCESS;
3102 enum i40e_status_code
3103 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3105 struct i40e_rx_queue *rxq;
3106 const struct rte_memzone *rz = NULL;
3108 struct rte_eth_dev *dev;
3111 PMD_DRV_LOG(ERR, "PF is not available");
3112 return I40E_ERR_BAD_PTR;
3115 dev = &rte_eth_devices[pf->dev_data->port_id];
3117 /* Allocate the RX queue data structure. */
3118 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3119 sizeof(struct i40e_rx_queue),
3120 RTE_CACHE_LINE_SIZE,
3123 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3124 "rx queue structure.");
3125 return I40E_ERR_NO_MEMORY;
3128 /* Allocate RX hardware ring descriptors. */
3129 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3130 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3132 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3133 I40E_FDIR_QUEUE_ID, ring_size,
3134 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3136 i40e_rx_queue_release(rxq);
3137 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3138 return I40E_ERR_NO_MEMORY;
3142 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3143 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3144 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3145 rxq->vsi = pf->fdir.fdir_vsi;
3147 rxq->rx_ring_phys_addr = rz->iova;
3148 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3149 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3152 * Don't need to allocate software ring and reset for the fdir
3153 * rx queue, just set the queue has been configured.
3158 return I40E_SUCCESS;
3162 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3163 struct rte_eth_rxq_info *qinfo)
3165 struct i40e_rx_queue *rxq;
3167 rxq = dev->data->rx_queues[queue_id];
3169 qinfo->mp = rxq->mp;
3170 qinfo->scattered_rx = dev->data->scattered_rx;
3171 qinfo->nb_desc = rxq->nb_rx_desc;
3173 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3174 qinfo->conf.rx_drop_en = rxq->drop_en;
3175 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3176 qinfo->conf.offloads = rxq->offloads;
3180 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3181 struct rte_eth_txq_info *qinfo)
3183 struct i40e_tx_queue *txq;
3185 txq = dev->data->tx_queues[queue_id];
3187 qinfo->nb_desc = txq->nb_tx_desc;
3189 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3190 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3191 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3193 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3194 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3195 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3196 qinfo->conf.offloads = txq->offloads;
3201 get_avx_supported(bool request_avx512)
3203 if (request_avx512) {
3204 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3205 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3206 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3207 #ifdef CC_AVX512_SUPPORT
3211 "AVX512 is not supported in build env");
3215 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3216 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3217 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3218 #ifdef CC_AVX2_SUPPORT
3222 "AVX2 is not supported in build env");
3229 #endif /* RTE_ARCH_X86 */
3233 i40e_set_rx_function(struct rte_eth_dev *dev)
3235 struct i40e_adapter *ad =
3236 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3237 uint16_t rx_using_sse, i;
3238 /* In order to allow Vector Rx there are a few configuration
3239 * conditions to be met and Rx Bulk Allocation should be allowed.
3241 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3243 ad->rx_use_avx512 = false;
3244 ad->rx_use_avx2 = false;
3246 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3247 !ad->rx_bulk_alloc_allowed) {
3248 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3249 " Vector Rx preconditions",
3250 dev->data->port_id);
3252 ad->rx_vec_allowed = false;
3254 if (ad->rx_vec_allowed) {
3255 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3256 struct i40e_rx_queue *rxq =
3257 dev->data->rx_queues[i];
3259 if (rxq && i40e_rxq_vec_setup(rxq)) {
3260 ad->rx_vec_allowed = false;
3265 ad->rx_use_avx512 = get_avx_supported(1);
3267 if (!ad->rx_use_avx512)
3268 ad->rx_use_avx2 = get_avx_supported(0);
3273 if (ad->rx_vec_allowed &&
3274 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3276 if (dev->data->scattered_rx) {
3277 if (ad->rx_use_avx512) {
3278 #ifdef CC_AVX512_SUPPORT
3280 "Using AVX512 Vector Scattered Rx (port %d).",
3281 dev->data->port_id);
3283 i40e_recv_scattered_pkts_vec_avx512;
3287 "Using %sVector Scattered Rx (port %d).",
3288 ad->rx_use_avx2 ? "avx2 " : "",
3289 dev->data->port_id);
3290 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3291 i40e_recv_scattered_pkts_vec_avx2 :
3292 i40e_recv_scattered_pkts_vec;
3295 if (ad->rx_use_avx512) {
3296 #ifdef CC_AVX512_SUPPORT
3298 "Using AVX512 Vector Rx (port %d).",
3299 dev->data->port_id);
3301 i40e_recv_pkts_vec_avx512;
3305 "Using %sVector Rx (port %d).",
3306 ad->rx_use_avx2 ? "avx2 " : "",
3307 dev->data->port_id);
3308 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3309 i40e_recv_pkts_vec_avx2 :
3313 #else /* RTE_ARCH_X86 */
3314 if (dev->data->scattered_rx) {
3316 "Using Vector Scattered Rx (port %d).",
3317 dev->data->port_id);
3318 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3320 PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3321 dev->data->port_id);
3322 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3324 #endif /* RTE_ARCH_X86 */
3325 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3326 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3327 "satisfied. Rx Burst Bulk Alloc function "
3328 "will be used on port=%d.",
3329 dev->data->port_id);
3331 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3333 /* Simple Rx Path. */
3334 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3335 dev->data->port_id);
3336 dev->rx_pkt_burst = dev->data->scattered_rx ?
3337 i40e_recv_scattered_pkts :
3341 /* Propagate information about RX function choice through all queues. */
3342 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3344 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3345 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3346 #ifdef CC_AVX512_SUPPORT
3347 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3348 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3350 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3351 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3353 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3354 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3357 rxq->rx_using_sse = rx_using_sse;
3362 static const struct {
3363 eth_rx_burst_t pkt_burst;
3365 } i40e_rx_burst_infos[] = {
3366 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3367 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3368 { i40e_recv_pkts, "Scalar" },
3370 #ifdef CC_AVX512_SUPPORT
3371 { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3372 { i40e_recv_pkts_vec_avx512, "Vector AVX512" },
3374 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3375 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3376 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3377 { i40e_recv_pkts_vec, "Vector SSE" },
3378 #elif defined(RTE_ARCH_ARM64)
3379 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3380 { i40e_recv_pkts_vec, "Vector Neon" },
3381 #elif defined(RTE_ARCH_PPC_64)
3382 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3383 { i40e_recv_pkts_vec, "Vector AltiVec" },
3388 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3389 struct rte_eth_burst_mode *mode)
3391 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3395 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3396 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3397 snprintf(mode->info, sizeof(mode->info), "%s",
3398 i40e_rx_burst_infos[i].info);
3408 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3410 struct i40e_adapter *ad =
3411 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3413 /* Use a simple Tx queue if possible (only fast free is allowed) */
3414 ad->tx_simple_allowed =
3416 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3417 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3418 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3419 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3421 if (ad->tx_vec_allowed)
3422 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3424 else if (ad->tx_simple_allowed)
3425 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3429 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3434 i40e_set_tx_function(struct rte_eth_dev *dev)
3436 struct i40e_adapter *ad =
3437 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3440 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3442 ad->tx_use_avx2 = false;
3443 ad->tx_use_avx512 = false;
3445 if (ad->tx_vec_allowed) {
3446 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3447 struct i40e_tx_queue *txq =
3448 dev->data->tx_queues[i];
3450 if (txq && i40e_txq_vec_setup(txq)) {
3451 ad->tx_vec_allowed = false;
3456 ad->tx_use_avx512 = get_avx_supported(1);
3458 if (!ad->tx_use_avx512)
3459 ad->tx_use_avx2 = get_avx_supported(0);
3464 if (ad->tx_simple_allowed) {
3465 if (ad->tx_vec_allowed &&
3466 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3468 if (ad->tx_use_avx512) {
3469 #ifdef CC_AVX512_SUPPORT
3470 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3471 dev->data->port_id);
3472 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3475 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3476 ad->tx_use_avx2 ? "avx2 " : "",
3477 dev->data->port_id);
3478 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3479 i40e_xmit_pkts_vec_avx2 :
3482 #else /* RTE_ARCH_X86 */
3483 PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3484 dev->data->port_id);
3485 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3486 #endif /* RTE_ARCH_X86 */
3488 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3489 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3491 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3493 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3494 dev->tx_pkt_burst = i40e_xmit_pkts;
3495 dev->tx_pkt_prepare = i40e_prep_pkts;
3499 static const struct {
3500 eth_tx_burst_t pkt_burst;
3502 } i40e_tx_burst_infos[] = {
3503 { i40e_xmit_pkts_simple, "Scalar Simple" },
3504 { i40e_xmit_pkts, "Scalar" },
3506 #ifdef CC_AVX512_SUPPORT
3507 { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3509 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3510 { i40e_xmit_pkts_vec, "Vector SSE" },
3511 #elif defined(RTE_ARCH_ARM64)
3512 { i40e_xmit_pkts_vec, "Vector Neon" },
3513 #elif defined(RTE_ARCH_PPC_64)
3514 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3519 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3520 struct rte_eth_burst_mode *mode)
3522 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3526 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3527 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3528 snprintf(mode->info, sizeof(mode->info), "%s",
3529 i40e_tx_burst_infos[i].info);
3539 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3541 struct i40e_adapter *ad =
3542 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3545 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3546 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3550 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3552 struct i40e_adapter *ad =
3553 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3558 ad->pctypes_tbl[i] = 0ULL;
3559 ad->flow_types_mask = 0ULL;
3560 ad->pctypes_mask = 0ULL;
3562 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3563 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3564 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3565 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3566 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3567 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3568 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3569 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3570 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3571 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3572 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3573 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3574 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3575 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3576 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3577 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3578 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3579 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3580 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3581 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3582 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3583 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3585 if (hw->mac.type == I40E_MAC_X722 ||
3586 hw->mac.type == I40E_MAC_X722_VF) {
3587 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3588 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3589 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3590 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3591 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3592 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3593 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3594 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3595 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3596 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3597 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3598 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3601 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3602 if (ad->pctypes_tbl[i])
3603 ad->flow_types_mask |= (1ULL << i);
3604 ad->pctypes_mask |= ad->pctypes_tbl[i];
3608 #ifndef CC_AVX2_SUPPORT
3610 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3611 struct rte_mbuf __rte_unused **rx_pkts,
3612 uint16_t __rte_unused nb_pkts)
3618 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3619 struct rte_mbuf __rte_unused **rx_pkts,
3620 uint16_t __rte_unused nb_pkts)
3626 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3627 struct rte_mbuf __rte_unused **tx_pkts,
3628 uint16_t __rte_unused nb_pkts)
3632 #endif /* ifndef CC_AVX2_SUPPORT */