drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_TCP_SEG |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  83                                       struct rte_mbuf **tx_pkts,
  84                                       uint16_t nb_pkts);
  85
  86 static inline void
  87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  88 {
  89         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  90                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  91                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
  92                 mb->vlan_tci =
  93                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  96         } else {
  97                 mb->vlan_tci = 0;
  98         }
  99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 100         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 101                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 103                 mb->vlan_tci_outer = mb->vlan_tci;
 104                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 107                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 108         } else {
 109                 mb->vlan_tci_outer = 0;
 110         }
 111 #endif
 112         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 113                    mb->vlan_tci, mb->vlan_tci_outer);
 114 }
 115
 116 /* Translate the rx descriptor status to pkt flags */
 117 static inline uint64_t
 118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 119 {
 120         uint64_t flags;
 121
 122         /* Check if RSS_HASH */
 123         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 124                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 125                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 126
 127         /* Check if FDIR Match */
 128         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 129                                                         PKT_RX_FDIR : 0);
 130
 131         return flags;
 132 }
 133
 134 static inline uint64_t
 135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 136 {
 137         uint64_t flags = 0;
 138         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 139
 140 #define I40E_RX_ERR_BITS 0x3f
 141         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 142                 return flags;
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 144                 flags |= PKT_RX_IP_CKSUM_BAD;
 145         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 146                 flags |= PKT_RX_L4_CKSUM_BAD;
 147         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 148                 flags |= PKT_RX_EIP_CKSUM_BAD;
 149
 150         return flags;
 151 }
 152
 153 /* Function to check and set the ieee1588 timesync index and get the
 154  * appropriate flags.
 155  */
 156 #ifdef RTE_LIBRTE_IEEE1588
 157 static inline uint64_t
 158 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 159 {
 160         uint64_t pkt_flags = 0;
 161         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 162                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 163                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 164
 165         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 166                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 167                 pkt_flags = PKT_RX_IEEE1588_PTP;
 168         if (tsyn & 0x04) {
 169                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 170                 mb->timesync = tsyn & 0x03;
 171         }
 172
 173         return pkt_flags;
 174 }
 175 #endif
 176
 177 /* For each value it means, datasheet of hardware can tell more details
 178  *
 179  * @note: fix i40e_dev_supported_ptypes_get() if any change here.
 180  */
 181 static inline uint32_t
 182 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 183 {
 184         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 185                 /* L2 types */
 186                 /* [0] reserved */
 187                 [1] = RTE_PTYPE_L2_ETHER,
 188                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 189                 /* [3] - [5] reserved */
 190                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 191                 /* [7] - [10] reserved */
 192                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 193                 /* [12] - [21] reserved */
 194
 195                 /* Non tunneled IPv4 */
 196                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 197                         RTE_PTYPE_L4_FRAG,
 198                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 199                         RTE_PTYPE_L4_NONFRAG,
 200                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 201                         RTE_PTYPE_L4_UDP,
 202                 /* [25] reserved */
 203                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                         RTE_PTYPE_L4_TCP,
 205                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 206                         RTE_PTYPE_L4_SCTP,
 207                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                         RTE_PTYPE_L4_ICMP,
 209
 210                 /* IPv4 --> IPv4 */
 211                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 212                         RTE_PTYPE_TUNNEL_IP |
 213                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 214                         RTE_PTYPE_INNER_L4_FRAG,
 215                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 216                         RTE_PTYPE_TUNNEL_IP |
 217                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 218                         RTE_PTYPE_INNER_L4_NONFRAG,
 219                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 220                         RTE_PTYPE_TUNNEL_IP |
 221                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 222                         RTE_PTYPE_INNER_L4_UDP,
 223                 /* [32] reserved */
 224                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                         RTE_PTYPE_TUNNEL_IP |
 226                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_INNER_L4_TCP,
 228                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_TUNNEL_IP |
 230                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_INNER_L4_SCTP,
 232                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_TUNNEL_IP |
 234                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_INNER_L4_ICMP,
 236
 237                 /* IPv4 --> IPv6 */
 238                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 239                         RTE_PTYPE_TUNNEL_IP |
 240                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 241                         RTE_PTYPE_INNER_L4_FRAG,
 242                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 243                         RTE_PTYPE_TUNNEL_IP |
 244                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 245                         RTE_PTYPE_INNER_L4_NONFRAG,
 246                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 247                         RTE_PTYPE_TUNNEL_IP |
 248                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 249                         RTE_PTYPE_INNER_L4_UDP,
 250                 /* [39] reserved */
 251                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                         RTE_PTYPE_TUNNEL_IP |
 253                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 254                         RTE_PTYPE_INNER_L4_TCP,
 255                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 256                         RTE_PTYPE_TUNNEL_IP |
 257                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 258                         RTE_PTYPE_INNER_L4_SCTP,
 259                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 260                         RTE_PTYPE_TUNNEL_IP |
 261                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 262                         RTE_PTYPE_INNER_L4_ICMP,
 263
 264                 /* IPv4 --> GRE/Teredo/VXLAN */
 265                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 266                         RTE_PTYPE_TUNNEL_GRENAT,
 267
 268                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 269                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 270                         RTE_PTYPE_TUNNEL_GRENAT |
 271                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 272                         RTE_PTYPE_INNER_L4_FRAG,
 273                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 274                         RTE_PTYPE_TUNNEL_GRENAT |
 275                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 276                         RTE_PTYPE_INNER_L4_NONFRAG,
 277                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 278                         RTE_PTYPE_TUNNEL_GRENAT |
 279                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 280                         RTE_PTYPE_INNER_L4_UDP,
 281                 /* [47] reserved */
 282                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 283                         RTE_PTYPE_TUNNEL_GRENAT |
 284                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 285                         RTE_PTYPE_INNER_L4_TCP,
 286                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_TUNNEL_GRENAT |
 288                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_INNER_L4_SCTP,
 290                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_TUNNEL_GRENAT |
 292                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_INNER_L4_ICMP,
 294
 295                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 296                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 297                         RTE_PTYPE_TUNNEL_GRENAT |
 298                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 299                         RTE_PTYPE_INNER_L4_FRAG,
 300                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 301                         RTE_PTYPE_TUNNEL_GRENAT |
 302                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 303                         RTE_PTYPE_INNER_L4_NONFRAG,
 304                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 305                         RTE_PTYPE_TUNNEL_GRENAT |
 306                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 307                         RTE_PTYPE_INNER_L4_UDP,
 308                 /* [54] reserved */
 309                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 310                         RTE_PTYPE_TUNNEL_GRENAT |
 311                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 312                         RTE_PTYPE_INNER_L4_TCP,
 313                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 314                         RTE_PTYPE_TUNNEL_GRENAT |
 315                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 316                         RTE_PTYPE_INNER_L4_SCTP,
 317                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 318                         RTE_PTYPE_TUNNEL_GRENAT |
 319                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 320                         RTE_PTYPE_INNER_L4_ICMP,
 321
 322                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 323                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 324                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 325
 326                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 327                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 328                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 329                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 330                         RTE_PTYPE_INNER_L4_FRAG,
 331                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 332                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 333                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 334                         RTE_PTYPE_INNER_L4_NONFRAG,
 335                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 336                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 337                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 338                         RTE_PTYPE_INNER_L4_UDP,
 339                 /* [62] reserved */
 340                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 341                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 342                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 343                         RTE_PTYPE_INNER_L4_TCP,
 344                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 346                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_INNER_L4_SCTP,
 348                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 350                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_INNER_L4_ICMP,
 352
 353                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 354                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 355                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 356                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 357                         RTE_PTYPE_INNER_L4_FRAG,
 358                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 359                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 360                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 361                         RTE_PTYPE_INNER_L4_NONFRAG,
 362                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 363                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 364                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 365                         RTE_PTYPE_INNER_L4_UDP,
 366                 /* [69] reserved */
 367                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 368                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 369                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 370                         RTE_PTYPE_INNER_L4_TCP,
 371                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 372                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 373                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 374                         RTE_PTYPE_INNER_L4_SCTP,
 375                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 376                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 377                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 378                         RTE_PTYPE_INNER_L4_ICMP,
 379
 380                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 381                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 382                         RTE_PTYPE_TUNNEL_GRENAT |
 383                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 384
 385                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 386                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 387                         RTE_PTYPE_TUNNEL_GRENAT |
 388                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 389                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 390                         RTE_PTYPE_INNER_L4_FRAG,
 391                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 392                         RTE_PTYPE_TUNNEL_GRENAT |
 393                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 394                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 395                         RTE_PTYPE_INNER_L4_NONFRAG,
 396                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 397                         RTE_PTYPE_TUNNEL_GRENAT |
 398                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 399                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 400                         RTE_PTYPE_INNER_L4_UDP,
 401                 /* [77] reserved */
 402                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 403                         RTE_PTYPE_TUNNEL_GRENAT |
 404                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 405                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 406                         RTE_PTYPE_INNER_L4_TCP,
 407                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 408                         RTE_PTYPE_TUNNEL_GRENAT |
 409                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 410                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 411                         RTE_PTYPE_INNER_L4_SCTP,
 412                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 413                         RTE_PTYPE_TUNNEL_GRENAT |
 414                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 415                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 416                         RTE_PTYPE_INNER_L4_ICMP,
 417
 418                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 419                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 420                         RTE_PTYPE_TUNNEL_GRENAT |
 421                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 422                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 423                         RTE_PTYPE_INNER_L4_FRAG,
 424                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 425                         RTE_PTYPE_TUNNEL_GRENAT |
 426                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 427                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 428                         RTE_PTYPE_INNER_L4_NONFRAG,
 429                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 430                         RTE_PTYPE_TUNNEL_GRENAT |
 431                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 432                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 433                         RTE_PTYPE_INNER_L4_UDP,
 434                 /* [84] reserved */
 435                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 436                         RTE_PTYPE_TUNNEL_GRENAT |
 437                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 438                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 439                         RTE_PTYPE_INNER_L4_TCP,
 440                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 441                         RTE_PTYPE_TUNNEL_GRENAT |
 442                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 443                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 444                         RTE_PTYPE_INNER_L4_SCTP,
 445                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 446                         RTE_PTYPE_TUNNEL_GRENAT |
 447                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 448                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 449                         RTE_PTYPE_INNER_L4_ICMP,
 450
 451                 /* Non tunneled IPv6 */
 452                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 453                         RTE_PTYPE_L4_FRAG,
 454                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 455                         RTE_PTYPE_L4_NONFRAG,
 456                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 457                         RTE_PTYPE_L4_UDP,
 458                 /* [91] reserved */
 459                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 460                         RTE_PTYPE_L4_TCP,
 461                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 462                         RTE_PTYPE_L4_SCTP,
 463                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 464                         RTE_PTYPE_L4_ICMP,
 465
 466                 /* IPv6 --> IPv4 */
 467                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 468                         RTE_PTYPE_TUNNEL_IP |
 469                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 470                         RTE_PTYPE_INNER_L4_FRAG,
 471                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_TUNNEL_IP |
 473                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 474                         RTE_PTYPE_INNER_L4_NONFRAG,
 475                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 476                         RTE_PTYPE_TUNNEL_IP |
 477                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 478                         RTE_PTYPE_INNER_L4_UDP,
 479                 /* [98] reserved */
 480                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 481                         RTE_PTYPE_TUNNEL_IP |
 482                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 483                         RTE_PTYPE_INNER_L4_TCP,
 484                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 485                         RTE_PTYPE_TUNNEL_IP |
 486                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 487                         RTE_PTYPE_INNER_L4_SCTP,
 488                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 489                         RTE_PTYPE_TUNNEL_IP |
 490                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 491                         RTE_PTYPE_INNER_L4_ICMP,
 492
 493                 /* IPv6 --> IPv6 */
 494                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 495                         RTE_PTYPE_TUNNEL_IP |
 496                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 497                         RTE_PTYPE_INNER_L4_FRAG,
 498                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 499                         RTE_PTYPE_TUNNEL_IP |
 500                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 501                         RTE_PTYPE_INNER_L4_NONFRAG,
 502                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 503                         RTE_PTYPE_TUNNEL_IP |
 504                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 505                         RTE_PTYPE_INNER_L4_UDP,
 506                 /* [105] reserved */
 507                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 508                         RTE_PTYPE_TUNNEL_IP |
 509                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 510                         RTE_PTYPE_INNER_L4_TCP,
 511                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_TUNNEL_IP |
 513                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_INNER_L4_SCTP,
 515                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_TUNNEL_IP |
 517                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_INNER_L4_ICMP,
 519
 520                 /* IPv6 --> GRE/Teredo/VXLAN */
 521                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 522                         RTE_PTYPE_TUNNEL_GRENAT,
 523
 524                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 525                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 526                         RTE_PTYPE_TUNNEL_GRENAT |
 527                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 528                         RTE_PTYPE_INNER_L4_FRAG,
 529                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 530                         RTE_PTYPE_TUNNEL_GRENAT |
 531                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 532                         RTE_PTYPE_INNER_L4_NONFRAG,
 533                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 534                         RTE_PTYPE_TUNNEL_GRENAT |
 535                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 536                         RTE_PTYPE_INNER_L4_UDP,
 537                 /* [113] reserved */
 538                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 539                         RTE_PTYPE_TUNNEL_GRENAT |
 540                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 541                         RTE_PTYPE_INNER_L4_TCP,
 542                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 543                         RTE_PTYPE_TUNNEL_GRENAT |
 544                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 545                         RTE_PTYPE_INNER_L4_SCTP,
 546                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 547                         RTE_PTYPE_TUNNEL_GRENAT |
 548                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 549                         RTE_PTYPE_INNER_L4_ICMP,
 550
 551                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 552                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 553                         RTE_PTYPE_TUNNEL_GRENAT |
 554                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 555                         RTE_PTYPE_INNER_L4_FRAG,
 556                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 557                         RTE_PTYPE_TUNNEL_GRENAT |
 558                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 559                         RTE_PTYPE_INNER_L4_NONFRAG,
 560                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 561                         RTE_PTYPE_TUNNEL_GRENAT |
 562                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 563                         RTE_PTYPE_INNER_L4_UDP,
 564                 /* [120] reserved */
 565                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 566                         RTE_PTYPE_TUNNEL_GRENAT |
 567                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 568                         RTE_PTYPE_INNER_L4_TCP,
 569                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_TUNNEL_GRENAT |
 571                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_INNER_L4_SCTP,
 573                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_TUNNEL_GRENAT |
 575                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_INNER_L4_ICMP,
 577
 578                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 579                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 580                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 581
 582                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 583                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 584                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 585                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 586                         RTE_PTYPE_INNER_L4_FRAG,
 587                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 588                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 589                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 590                         RTE_PTYPE_INNER_L4_NONFRAG,
 591                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 592                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 593                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 594                         RTE_PTYPE_INNER_L4_UDP,
 595                 /* [128] reserved */
 596                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 597                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 598                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 599                         RTE_PTYPE_INNER_L4_TCP,
 600                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 601                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 602                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 603                         RTE_PTYPE_INNER_L4_SCTP,
 604                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 605                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 606                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 607                         RTE_PTYPE_INNER_L4_ICMP,
 608
 609                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 610                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 611                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 612                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 613                         RTE_PTYPE_INNER_L4_FRAG,
 614                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 615                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 616                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 617                         RTE_PTYPE_INNER_L4_NONFRAG,
 618                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 619                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 620                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 621                         RTE_PTYPE_INNER_L4_UDP,
 622                 /* [135] reserved */
 623                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 624                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 625                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 626                         RTE_PTYPE_INNER_L4_TCP,
 627                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 629                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_INNER_L4_SCTP,
 631                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 633                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_INNER_L4_ICMP,
 635
 636                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 637                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 638                         RTE_PTYPE_TUNNEL_GRENAT |
 639                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 640
 641                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 642                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_TUNNEL_GRENAT |
 644                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 645                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 646                         RTE_PTYPE_INNER_L4_FRAG,
 647                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 648                         RTE_PTYPE_TUNNEL_GRENAT |
 649                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 650                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 651                         RTE_PTYPE_INNER_L4_NONFRAG,
 652                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 653                         RTE_PTYPE_TUNNEL_GRENAT |
 654                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 655                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 656                         RTE_PTYPE_INNER_L4_UDP,
 657                 /* [143] reserved */
 658                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 659                         RTE_PTYPE_TUNNEL_GRENAT |
 660                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 661                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 662                         RTE_PTYPE_INNER_L4_TCP,
 663                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 664                         RTE_PTYPE_TUNNEL_GRENAT |
 665                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 666                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 667                         RTE_PTYPE_INNER_L4_SCTP,
 668                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 669                         RTE_PTYPE_TUNNEL_GRENAT |
 670                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 671                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 672                         RTE_PTYPE_INNER_L4_ICMP,
 673
 674                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 675                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 676                         RTE_PTYPE_TUNNEL_GRENAT |
 677                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 678                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 679                         RTE_PTYPE_INNER_L4_FRAG,
 680                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 681                         RTE_PTYPE_TUNNEL_GRENAT |
 682                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 683                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 684                         RTE_PTYPE_INNER_L4_NONFRAG,
 685                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 686                         RTE_PTYPE_TUNNEL_GRENAT |
 687                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 688                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 689                         RTE_PTYPE_INNER_L4_UDP,
 690                 /* [150] reserved */
 691                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 692                         RTE_PTYPE_TUNNEL_GRENAT |
 693                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 695                         RTE_PTYPE_INNER_L4_TCP,
 696                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 697                         RTE_PTYPE_TUNNEL_GRENAT |
 698                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 699                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 700                         RTE_PTYPE_INNER_L4_SCTP,
 701                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 702                         RTE_PTYPE_TUNNEL_GRENAT |
 703                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 704                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 705                         RTE_PTYPE_INNER_L4_ICMP,
 706
 707                 /* L2 NSH packet type */
 708                 [154] = RTE_PTYPE_L2_ETHER_NSH,
 709                 [155] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 710                         RTE_PTYPE_L4_FRAG,
 711                 [156] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 712                         RTE_PTYPE_L4_NONFRAG,
 713                 [157] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 714                         RTE_PTYPE_L4_UDP,
 715                 [158] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 716                         RTE_PTYPE_L4_TCP,
 717                 [159] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 718                         RTE_PTYPE_L4_SCTP,
 719                 [160] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 720                         RTE_PTYPE_L4_ICMP,
 721                 [161] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 722                         RTE_PTYPE_L4_FRAG,
 723                 [162] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 724                         RTE_PTYPE_L4_NONFRAG,
 725                 [163] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 726                         RTE_PTYPE_L4_UDP,
 727                 [164] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 728                         RTE_PTYPE_L4_TCP,
 729                 [165] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 730                         RTE_PTYPE_L4_SCTP,
 731                 [166] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 732                         RTE_PTYPE_L4_ICMP,
 733
 734                 /* All others reserved */
 735         };
 736
 737         return type_table[ptype];
 738 }
 739
 740 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 741 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 742 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 743 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 744 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 745
 746 static inline uint64_t
 747 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 748 {
 749         uint64_t flags = 0;
 750 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 751         uint16_t flexbh, flexbl;
 752
 753         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 754                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 755                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 756         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 757                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 758                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 759
 760
 761         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 762                 mb->hash.fdir.hi =
 763                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 764                 flags |= PKT_RX_FDIR_ID;
 765         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 766                 mb->hash.fdir.hi =
 767                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 768                 flags |= PKT_RX_FDIR_FLX;
 769         }
 770         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 771                 mb->hash.fdir.lo =
 772                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 773                 flags |= PKT_RX_FDIR_FLX;
 774         }
 775 #else
 776         mb->hash.fdir.hi =
 777                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 778         flags |= PKT_RX_FDIR_ID;
 779 #endif
 780         return flags;
 781 }
 782
 783 static inline void
 784 i40e_parse_tunneling_params(uint64_t ol_flags,
 785                             union i40e_tx_offload tx_offload,
 786                             uint32_t *cd_tunneling)
 787 {
 788         /* EIPT: External (outer) IP header type */
 789         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 790                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 791         else if (ol_flags & PKT_TX_OUTER_IPV4)
 792                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 793         else if (ol_flags & PKT_TX_OUTER_IPV6)
 794                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 795
 796         /* EIPLEN: External (outer) IP header length, in DWords */
 797         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 798                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 799
 800         /* L4TUNT: L4 Tunneling Type */
 801         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 802         case PKT_TX_TUNNEL_IPIP:
 803                 /* for non UDP / GRE tunneling, set to 00b */
 804                 break;
 805         case PKT_TX_TUNNEL_VXLAN:
 806         case PKT_TX_TUNNEL_GENEVE:
 807                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 808                 break;
 809         case PKT_TX_TUNNEL_GRE:
 810                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 811                 break;
 812         default:
 813                 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
 814                 return;
 815         }
 816
 817         /* L4TUNLEN: L4 Tunneling Length, in Words
 818          *
 819          * We depend on app to set rte_mbuf.l2_len correctly.
 820          * For IP in GRE it should be set to the length of the GRE
 821          * header;
 822          * for MAC in GRE or MAC in UDP it should be set to the length
 823          * of the GRE or UDP headers plus the inner MAC up to including
 824          * its last Ethertype.
 825          */
 826         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 827                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 828 }
 829
 830 static inline void
 831 i40e_txd_enable_checksum(uint64_t ol_flags,
 832                         uint32_t *td_cmd,
 833                         uint32_t *td_offset,
 834                         union i40e_tx_offload tx_offload)
 835 {
 836         /* Set MACLEN */
 837         if (ol_flags & PKT_TX_TUNNEL_MASK)
 838                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 839                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 840         else
 841                 *td_offset |= (tx_offload.l2_len >> 1)
 842                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 843
 844         /* Enable L3 checksum offloads */
 845         if (ol_flags & PKT_TX_IP_CKSUM) {
 846                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 847                 *td_offset |= (tx_offload.l3_len >> 2)
 848                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 849         } else if (ol_flags & PKT_TX_IPV4) {
 850                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 851                 *td_offset |= (tx_offload.l3_len >> 2)
 852                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 853         } else if (ol_flags & PKT_TX_IPV6) {
 854                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 855                 *td_offset |= (tx_offload.l3_len >> 2)
 856                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 857         }
 858
 859         if (ol_flags & PKT_TX_TCP_SEG) {
 860                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 861                 *td_offset |= (tx_offload.l4_len >> 2)
 862                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 863                 return;
 864         }
 865
 866         /* Enable L4 checksum offloads */
 867         switch (ol_flags & PKT_TX_L4_MASK) {
 868         case PKT_TX_TCP_CKSUM:
 869                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 870                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 871                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 872                 break;
 873         case PKT_TX_SCTP_CKSUM:
 874                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 875                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 876                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 877                 break;
 878         case PKT_TX_UDP_CKSUM:
 879                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 880                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 881                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 882                 break;
 883         default:
 884                 break;
 885         }
 886 }
 887
 888 /* Construct the tx flags */
 889 static inline uint64_t
 890 i40e_build_ctob(uint32_t td_cmd,
 891                 uint32_t td_offset,
 892                 unsigned int size,
 893                 uint32_t td_tag)
 894 {
 895         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 896                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 897                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 898                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 899                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 900 }
 901
 902 static inline int
 903 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 904 {
 905         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 906         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 907         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 908         uint16_t nb_tx_desc = txq->nb_tx_desc;
 909         uint16_t desc_to_clean_to;
 910         uint16_t nb_tx_to_clean;
 911
 912         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 913         if (desc_to_clean_to >= nb_tx_desc)
 914                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 915
 916         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 917         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 918                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 919                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 920                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 921                         "(port=%d queue=%d)", desc_to_clean_to,
 922                                 txq->port_id, txq->queue_id);
 923                 return -1;
 924         }
 925
 926         if (last_desc_cleaned > desc_to_clean_to)
 927                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 928                                                         desc_to_clean_to);
 929         else
 930                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 931                                         last_desc_cleaned);
 932
 933         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 934
 935         txq->last_desc_cleaned = desc_to_clean_to;
 936         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 937
 938         return 0;
 939 }
 940
 941 static inline int
 942 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 943 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 944 #else
 945 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 946 #endif
 947 {
 948         int ret = 0;
 949
 950 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 951         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 952                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 953                              "rxq->rx_free_thresh=%d, "
 954                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 955                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 956                 ret = -EINVAL;
 957         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 958                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 959                              "rxq->rx_free_thresh=%d, "
 960                              "rxq->nb_rx_desc=%d",
 961                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 962                 ret = -EINVAL;
 963         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 964                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 965                              "rxq->nb_rx_desc=%d, "
 966                              "rxq->rx_free_thresh=%d",
 967                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 968                 ret = -EINVAL;
 969         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 970                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 971                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 972                              "rxq->nb_rx_desc=%d, "
 973                              "I40E_MAX_RING_DESC=%d, "
 974                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 975                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 976                              RTE_PMD_I40E_RX_MAX_BURST);
 977                 ret = -EINVAL;
 978         }
 979 #else
 980         ret = -EINVAL;
 981 #endif
 982
 983         return ret;
 984 }
 985
 986 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 987 #define I40E_LOOK_AHEAD 8
 988 #if (I40E_LOOK_AHEAD != 8)
 989 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 990 #endif
 991 static inline int
 992 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 993 {
 994         volatile union i40e_rx_desc *rxdp;
 995         struct i40e_rx_entry *rxep;
 996         struct rte_mbuf *mb;
 997         uint16_t pkt_len;
 998         uint64_t qword1;
 999         uint32_t rx_status;
1000         int32_t s[I40E_LOOK_AHEAD], nb_dd;
1001         int32_t i, j, nb_rx = 0;
1002         uint64_t pkt_flags;
1003
1004         rxdp = &rxq->rx_ring[rxq->rx_tail];
1005         rxep = &rxq->sw_ring[rxq->rx_tail];
1006
1007         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1008         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1009                                 I40E_RXD_QW1_STATUS_SHIFT;
1010
1011         /* Make sure there is at least 1 packet to receive */
1012         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1013                 return 0;
1014
1015         /**
1016          * Scan LOOK_AHEAD descriptors at a time to determine which
1017          * descriptors reference packets that are ready to be received.
1018          */
1019         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
1020                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
1021                 /* Read desc statuses backwards to avoid race condition */
1022                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
1023                         qword1 = rte_le_to_cpu_64(\
1024                                 rxdp[j].wb.qword1.status_error_len);
1025                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1026                                         I40E_RXD_QW1_STATUS_SHIFT;
1027                 }
1028
1029                 rte_smp_rmb();
1030
1031                 /* Compute how many status bits were set */
1032                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1033                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1034
1035                 nb_rx += nb_dd;
1036
1037                 /* Translate descriptor info to mbuf parameters */
1038                 for (j = 0; j < nb_dd; j++) {
1039                         mb = rxep[j].mbuf;
1040                         qword1 = rte_le_to_cpu_64(\
1041                                 rxdp[j].wb.qword1.status_error_len);
1042                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1043                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1044                         mb->data_len = pkt_len;
1045                         mb->pkt_len = pkt_len;
1046                         mb->ol_flags = 0;
1047                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1048                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1049                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1050                         mb->packet_type =
1051                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1052                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1053                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1054                         if (pkt_flags & PKT_RX_RSS_HASH)
1055                                 mb->hash.rss = rte_le_to_cpu_32(\
1056                                         rxdp[j].wb.qword0.hi_dword.rss);
1057                         if (pkt_flags & PKT_RX_FDIR)
1058                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1059
1060 #ifdef RTE_LIBRTE_IEEE1588
1061                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1062 #endif
1063                         mb->ol_flags |= pkt_flags;
1064
1065                 }
1066
1067                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1068                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1069
1070                 if (nb_dd != I40E_LOOK_AHEAD)
1071                         break;
1072         }
1073
1074         /* Clear software ring entries */
1075         for (i = 0; i < nb_rx; i++)
1076                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1077
1078         return nb_rx;
1079 }
1080
1081 static inline uint16_t
1082 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1083                         struct rte_mbuf **rx_pkts,
1084                         uint16_t nb_pkts)
1085 {
1086         uint16_t i;
1087         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1088
1089         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1090
1091         for (i = 0; i < nb_pkts; i++)
1092                 rx_pkts[i] = stage[i];
1093
1094         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1095         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1096
1097         return nb_pkts;
1098 }
1099
1100 static inline int
1101 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1102 {
1103         volatile union i40e_rx_desc *rxdp;
1104         struct i40e_rx_entry *rxep;
1105         struct rte_mbuf *mb;
1106         uint16_t alloc_idx, i;
1107         uint64_t dma_addr;
1108         int diag;
1109
1110         /* Allocate buffers in bulk */
1111         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1112                                 (rxq->rx_free_thresh - 1));
1113         rxep = &(rxq->sw_ring[alloc_idx]);
1114         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1115                                         rxq->rx_free_thresh);
1116         if (unlikely(diag != 0)) {
1117                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1118                 return -ENOMEM;
1119         }
1120
1121         rxdp = &rxq->rx_ring[alloc_idx];
1122         for (i = 0; i < rxq->rx_free_thresh; i++) {
1123                 if (likely(i < (rxq->rx_free_thresh - 1)))
1124                         /* Prefetch next mbuf */
1125                         rte_prefetch0(rxep[i + 1].mbuf);
1126
1127                 mb = rxep[i].mbuf;
1128                 rte_mbuf_refcnt_set(mb, 1);
1129                 mb->next = NULL;
1130                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1131                 mb->nb_segs = 1;
1132                 mb->port = rxq->port_id;
1133                 dma_addr = rte_cpu_to_le_64(\
1134                         rte_mbuf_data_dma_addr_default(mb));
1135                 rxdp[i].read.hdr_addr = 0;
1136                 rxdp[i].read.pkt_addr = dma_addr;
1137         }
1138
1139         /* Update rx tail regsiter */
1140         rte_wmb();
1141         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1142
1143         rxq->rx_free_trigger =
1144                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1145         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1146                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1147
1148         return 0;
1149 }
1150
1151 static inline uint16_t
1152 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1153 {
1154         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1155         uint16_t nb_rx = 0;
1156
1157         if (!nb_pkts)
1158                 return 0;
1159
1160         if (rxq->rx_nb_avail)
1161                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1162
1163         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1164         rxq->rx_next_avail = 0;
1165         rxq->rx_nb_avail = nb_rx;
1166         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1167
1168         if (rxq->rx_tail > rxq->rx_free_trigger) {
1169                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1170                         uint16_t i, j;
1171
1172                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1173                                    "port_id=%u, queue_id=%u",
1174                                    rxq->port_id, rxq->queue_id);
1175                         rxq->rx_nb_avail = 0;
1176                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1177                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1178                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1179
1180                         return 0;
1181                 }
1182         }
1183
1184         if (rxq->rx_tail >= rxq->nb_rx_desc)
1185                 rxq->rx_tail = 0;
1186
1187         if (rxq->rx_nb_avail)
1188                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1189
1190         return 0;
1191 }
1192
1193 static uint16_t
1194 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1195                           struct rte_mbuf **rx_pkts,
1196                           uint16_t nb_pkts)
1197 {
1198         uint16_t nb_rx = 0, n, count;
1199
1200         if (unlikely(nb_pkts == 0))
1201                 return 0;
1202
1203         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1204                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1205
1206         while (nb_pkts) {
1207                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1208                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1209                 nb_rx = (uint16_t)(nb_rx + count);
1210                 nb_pkts = (uint16_t)(nb_pkts - count);
1211                 if (count < n)
1212                         break;
1213         }
1214
1215         return nb_rx;
1216 }
1217 #else
1218 static uint16_t
1219 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1220                           struct rte_mbuf __rte_unused **rx_pkts,
1221                           uint16_t __rte_unused nb_pkts)
1222 {
1223         return 0;
1224 }
1225 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1226
1227 uint16_t
1228 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1229 {
1230         struct i40e_rx_queue *rxq;
1231         volatile union i40e_rx_desc *rx_ring;
1232         volatile union i40e_rx_desc *rxdp;
1233         union i40e_rx_desc rxd;
1234         struct i40e_rx_entry *sw_ring;
1235         struct i40e_rx_entry *rxe;
1236         struct rte_mbuf *rxm;
1237         struct rte_mbuf *nmb;
1238         uint16_t nb_rx;
1239         uint32_t rx_status;
1240         uint64_t qword1;
1241         uint16_t rx_packet_len;
1242         uint16_t rx_id, nb_hold;
1243         uint64_t dma_addr;
1244         uint64_t pkt_flags;
1245
1246         nb_rx = 0;
1247         nb_hold = 0;
1248         rxq = rx_queue;
1249         rx_id = rxq->rx_tail;
1250         rx_ring = rxq->rx_ring;
1251         sw_ring = rxq->sw_ring;
1252
1253         while (nb_rx < nb_pkts) {
1254                 rxdp = &rx_ring[rx_id];
1255                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1256                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1257                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1258
1259                 /* Check the DD bit first */
1260                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1261                         break;
1262
1263                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1264                 if (unlikely(!nmb))
1265                         break;
1266                 rxd = *rxdp;
1267
1268                 nb_hold++;
1269                 rxe = &sw_ring[rx_id];
1270                 rx_id++;
1271                 if (unlikely(rx_id == rxq->nb_rx_desc))
1272                         rx_id = 0;
1273
1274                 /* Prefetch next mbuf */
1275                 rte_prefetch0(sw_ring[rx_id].mbuf);
1276
1277                 /**
1278                  * When next RX descriptor is on a cache line boundary,
1279                  * prefetch the next 4 RX descriptors and next 8 pointers
1280                  * to mbufs.
1281                  */
1282                 if ((rx_id & 0x3) == 0) {
1283                         rte_prefetch0(&rx_ring[rx_id]);
1284                         rte_prefetch0(&sw_ring[rx_id]);
1285                 }
1286                 rxm = rxe->mbuf;
1287                 rxe->mbuf = nmb;
1288                 dma_addr =
1289                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1290                 rxdp->read.hdr_addr = 0;
1291                 rxdp->read.pkt_addr = dma_addr;
1292
1293                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1294                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1295
1296                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1297                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1298                 rxm->nb_segs = 1;
1299                 rxm->next = NULL;
1300                 rxm->pkt_len = rx_packet_len;
1301                 rxm->data_len = rx_packet_len;
1302                 rxm->port = rxq->port_id;
1303                 rxm->ol_flags = 0;
1304                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1305                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1306                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1307                 rxm->packet_type =
1308                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1309                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1310                 if (pkt_flags & PKT_RX_RSS_HASH)
1311                         rxm->hash.rss =
1312                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1313                 if (pkt_flags & PKT_RX_FDIR)
1314                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1315
1316 #ifdef RTE_LIBRTE_IEEE1588
1317                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1318 #endif
1319                 rxm->ol_flags |= pkt_flags;
1320
1321                 rx_pkts[nb_rx++] = rxm;
1322         }
1323         rxq->rx_tail = rx_id;
1324
1325         /**
1326          * If the number of free RX descriptors is greater than the RX free
1327          * threshold of the queue, advance the receive tail register of queue.
1328          * Update that register with the value of the last processed RX
1329          * descriptor minus 1.
1330          */
1331         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1332         if (nb_hold > rxq->rx_free_thresh) {
1333                 rx_id = (uint16_t) ((rx_id == 0) ?
1334                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1335                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1336                 nb_hold = 0;
1337         }
1338         rxq->nb_rx_hold = nb_hold;
1339
1340         return nb_rx;
1341 }
1342
1343 uint16_t
1344 i40e_recv_scattered_pkts(void *rx_queue,
1345                          struct rte_mbuf **rx_pkts,
1346                          uint16_t nb_pkts)
1347 {
1348         struct i40e_rx_queue *rxq = rx_queue;
1349         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1350         volatile union i40e_rx_desc *rxdp;
1351         union i40e_rx_desc rxd;
1352         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1353         struct i40e_rx_entry *rxe;
1354         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1355         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1356         struct rte_mbuf *nmb, *rxm;
1357         uint16_t rx_id = rxq->rx_tail;
1358         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1359         uint32_t rx_status;
1360         uint64_t qword1;
1361         uint64_t dma_addr;
1362         uint64_t pkt_flags;
1363
1364         while (nb_rx < nb_pkts) {
1365                 rxdp = &rx_ring[rx_id];
1366                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1367                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1368                                         I40E_RXD_QW1_STATUS_SHIFT;
1369
1370                 /* Check the DD bit */
1371                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1372                         break;
1373
1374                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1375                 if (unlikely(!nmb))
1376                         break;
1377                 rxd = *rxdp;
1378                 nb_hold++;
1379                 rxe = &sw_ring[rx_id];
1380                 rx_id++;
1381                 if (rx_id == rxq->nb_rx_desc)
1382                         rx_id = 0;
1383
1384                 /* Prefetch next mbuf */
1385                 rte_prefetch0(sw_ring[rx_id].mbuf);
1386
1387                 /**
1388                  * When next RX descriptor is on a cache line boundary,
1389                  * prefetch the next 4 RX descriptors and next 8 pointers
1390                  * to mbufs.
1391                  */
1392                 if ((rx_id & 0x3) == 0) {
1393                         rte_prefetch0(&rx_ring[rx_id]);
1394                         rte_prefetch0(&sw_ring[rx_id]);
1395                 }
1396
1397                 rxm = rxe->mbuf;
1398                 rxe->mbuf = nmb;
1399                 dma_addr =
1400                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1401
1402                 /* Set data buffer address and data length of the mbuf */
1403                 rxdp->read.hdr_addr = 0;
1404                 rxdp->read.pkt_addr = dma_addr;
1405                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1406                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1407                 rxm->data_len = rx_packet_len;
1408                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1409
1410                 /**
1411                  * If this is the first buffer of the received packet, set the
1412                  * pointer to the first mbuf of the packet and initialize its
1413                  * context. Otherwise, update the total length and the number
1414                  * of segments of the current scattered packet, and update the
1415                  * pointer to the last mbuf of the current packet.
1416                  */
1417                 if (!first_seg) {
1418                         first_seg = rxm;
1419                         first_seg->nb_segs = 1;
1420                         first_seg->pkt_len = rx_packet_len;
1421                 } else {
1422                         first_seg->pkt_len =
1423                                 (uint16_t)(first_seg->pkt_len +
1424                                                 rx_packet_len);
1425                         first_seg->nb_segs++;
1426                         last_seg->next = rxm;
1427                 }
1428
1429                 /**
1430                  * If this is not the last buffer of the received packet,
1431                  * update the pointer to the last mbuf of the current scattered
1432                  * packet and continue to parse the RX ring.
1433                  */
1434                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1435                         last_seg = rxm;
1436                         continue;
1437                 }
1438
1439                 /**
1440                  * This is the last buffer of the received packet. If the CRC
1441                  * is not stripped by the hardware:
1442                  *  - Subtract the CRC length from the total packet length.
1443                  *  - If the last buffer only contains the whole CRC or a part
1444                  *  of it, free the mbuf associated to the last buffer. If part
1445                  *  of the CRC is also contained in the previous mbuf, subtract
1446                  *  the length of that CRC part from the data length of the
1447                  *  previous mbuf.
1448                  */
1449                 rxm->next = NULL;
1450                 if (unlikely(rxq->crc_len > 0)) {
1451                         first_seg->pkt_len -= ETHER_CRC_LEN;
1452                         if (rx_packet_len <= ETHER_CRC_LEN) {
1453                                 rte_pktmbuf_free_seg(rxm);
1454                                 first_seg->nb_segs--;
1455                                 last_seg->data_len =
1456                                         (uint16_t)(last_seg->data_len -
1457                                         (ETHER_CRC_LEN - rx_packet_len));
1458                                 last_seg->next = NULL;
1459                         } else
1460                                 rxm->data_len = (uint16_t)(rx_packet_len -
1461                                                                 ETHER_CRC_LEN);
1462                 }
1463
1464                 first_seg->port = rxq->port_id;
1465                 first_seg->ol_flags = 0;
1466                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1467                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1468                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1469                 first_seg->packet_type =
1470                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1471                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1472                 if (pkt_flags & PKT_RX_RSS_HASH)
1473                         first_seg->hash.rss =
1474                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1475                 if (pkt_flags & PKT_RX_FDIR)
1476                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
1477
1478 #ifdef RTE_LIBRTE_IEEE1588
1479                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1480 #endif
1481                 first_seg->ol_flags |= pkt_flags;
1482
1483                 /* Prefetch data of first segment, if configured to do so. */
1484                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1485                         first_seg->data_off));
1486                 rx_pkts[nb_rx++] = first_seg;
1487                 first_seg = NULL;
1488         }
1489
1490         /* Record index of the next RX descriptor to probe. */
1491         rxq->rx_tail = rx_id;
1492         rxq->pkt_first_seg = first_seg;
1493         rxq->pkt_last_seg = last_seg;
1494
1495         /**
1496          * If the number of free RX descriptors is greater than the RX free
1497          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1498          * register. Update the RDT with the value of the last processed RX
1499          * descriptor minus 1, to guarantee that the RDT register is never
1500          * equal to the RDH register, which creates a "full" ring situtation
1501          * from the hardware point of view.
1502          */
1503         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1504         if (nb_hold > rxq->rx_free_thresh) {
1505                 rx_id = (uint16_t)(rx_id == 0 ?
1506                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1507                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1508                 nb_hold = 0;
1509         }
1510         rxq->nb_rx_hold = nb_hold;
1511
1512         return nb_rx;
1513 }
1514
1515 /* Check if the context descriptor is needed for TX offloading */
1516 static inline uint16_t
1517 i40e_calc_context_desc(uint64_t flags)
1518 {
1519         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1520                 PKT_TX_TCP_SEG |
1521                 PKT_TX_QINQ_PKT |
1522                 PKT_TX_TUNNEL_MASK;
1523
1524 #ifdef RTE_LIBRTE_IEEE1588
1525         mask |= PKT_TX_IEEE1588_TMST;
1526 #endif
1527
1528         return (flags & mask) ? 1 : 0;
1529 }
1530
1531 /* set i40e TSO context descriptor */
1532 static inline uint64_t
1533 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1534 {
1535         uint64_t ctx_desc = 0;
1536         uint32_t cd_cmd, hdr_len, cd_tso_len;
1537
1538         if (!tx_offload.l4_len) {
1539                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1540                 return ctx_desc;
1541         }
1542
1543         /**
1544          * in case of non tunneling packet, the outer_l2_len and
1545          * outer_l3_len must be 0.
1546          */
1547         hdr_len = tx_offload.outer_l2_len +
1548                 tx_offload.outer_l3_len +
1549                 tx_offload.l2_len +
1550                 tx_offload.l3_len +
1551                 tx_offload.l4_len;
1552
1553         cd_cmd = I40E_TX_CTX_DESC_TSO;
1554         cd_tso_len = mbuf->pkt_len - hdr_len;
1555         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1556                 ((uint64_t)cd_tso_len <<
1557                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1558                 ((uint64_t)mbuf->tso_segsz <<
1559                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1560
1561         return ctx_desc;
1562 }
1563
1564 uint16_t
1565 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1566 {
1567         struct i40e_tx_queue *txq;
1568         struct i40e_tx_entry *sw_ring;
1569         struct i40e_tx_entry *txe, *txn;
1570         volatile struct i40e_tx_desc *txd;
1571         volatile struct i40e_tx_desc *txr;
1572         struct rte_mbuf *tx_pkt;
1573         struct rte_mbuf *m_seg;
1574         uint32_t cd_tunneling_params;
1575         uint16_t tx_id;
1576         uint16_t nb_tx;
1577         uint32_t td_cmd;
1578         uint32_t td_offset;
1579         uint32_t tx_flags;
1580         uint32_t td_tag;
1581         uint64_t ol_flags;
1582         uint16_t nb_used;
1583         uint16_t nb_ctx;
1584         uint16_t tx_last;
1585         uint16_t slen;
1586         uint64_t buf_dma_addr;
1587         union i40e_tx_offload tx_offload = {0};
1588
1589         txq = tx_queue;
1590         sw_ring = txq->sw_ring;
1591         txr = txq->tx_ring;
1592         tx_id = txq->tx_tail;
1593         txe = &sw_ring[tx_id];
1594
1595         /* Check if the descriptor ring needs to be cleaned. */
1596         if (txq->nb_tx_free < txq->tx_free_thresh)
1597                 i40e_xmit_cleanup(txq);
1598
1599         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1600                 td_cmd = 0;
1601                 td_tag = 0;
1602                 td_offset = 0;
1603                 tx_flags = 0;
1604
1605                 tx_pkt = *tx_pkts++;
1606                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1607
1608                 ol_flags = tx_pkt->ol_flags;
1609                 tx_offload.l2_len = tx_pkt->l2_len;
1610                 tx_offload.l3_len = tx_pkt->l3_len;
1611                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1612                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1613                 tx_offload.l4_len = tx_pkt->l4_len;
1614                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1615
1616                 /* Calculate the number of context descriptors needed. */
1617                 nb_ctx = i40e_calc_context_desc(ol_flags);
1618
1619                 /**
1620                  * The number of descriptors that must be allocated for
1621                  * a packet equals to the number of the segments of that
1622                  * packet plus 1 context descriptor if needed.
1623                  */
1624                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1625                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1626
1627                 /* Circular ring */
1628                 if (tx_last >= txq->nb_tx_desc)
1629                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1630
1631                 if (nb_used > txq->nb_tx_free) {
1632                         if (i40e_xmit_cleanup(txq) != 0) {
1633                                 if (nb_tx == 0)
1634                                         return 0;
1635                                 goto end_of_tx;
1636                         }
1637                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1638                                 while (nb_used > txq->nb_tx_free) {
1639                                         if (i40e_xmit_cleanup(txq) != 0) {
1640                                                 if (nb_tx == 0)
1641                                                         return 0;
1642                                                 goto end_of_tx;
1643                                         }
1644                                 }
1645                         }
1646                 }
1647
1648                 /* Descriptor based VLAN insertion */
1649                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1650                         tx_flags |= tx_pkt->vlan_tci <<
1651                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1652                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1653                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1654                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1655                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1656                 }
1657
1658                 /* Always enable CRC offload insertion */
1659                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1660
1661                 /* Fill in tunneling parameters if necessary */
1662                 cd_tunneling_params = 0;
1663                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1664                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1665                                                     &cd_tunneling_params);
1666                 /* Enable checksum offloading */
1667                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1668                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1669                                                  &td_offset, tx_offload);
1670
1671                 if (nb_ctx) {
1672                         /* Setup TX context descriptor if required */
1673                         volatile struct i40e_tx_context_desc *ctx_txd =
1674                                 (volatile struct i40e_tx_context_desc *)\
1675                                                         &txr[tx_id];
1676                         uint16_t cd_l2tag2 = 0;
1677                         uint64_t cd_type_cmd_tso_mss =
1678                                 I40E_TX_DESC_DTYPE_CONTEXT;
1679
1680                         txn = &sw_ring[txe->next_id];
1681                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1682                         if (txe->mbuf != NULL) {
1683                                 rte_pktmbuf_free_seg(txe->mbuf);
1684                                 txe->mbuf = NULL;
1685                         }
1686
1687                         /* TSO enabled means no timestamp */
1688                         if (ol_flags & PKT_TX_TCP_SEG)
1689                                 cd_type_cmd_tso_mss |=
1690                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1691                         else {
1692 #ifdef RTE_LIBRTE_IEEE1588
1693                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1694                                         cd_type_cmd_tso_mss |=
1695                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1696                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1697 #endif
1698                         }
1699
1700                         ctx_txd->tunneling_params =
1701                                 rte_cpu_to_le_32(cd_tunneling_params);
1702                         if (ol_flags & PKT_TX_QINQ_PKT) {
1703                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1704                                 cd_type_cmd_tso_mss |=
1705                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1706                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1707                         }
1708                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1709                         ctx_txd->type_cmd_tso_mss =
1710                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1711
1712                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1713                                 "tunneling_params: %#x;\n"
1714                                 "l2tag2: %#hx;\n"
1715                                 "rsvd: %#hx;\n"
1716                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1717                                 tx_pkt, tx_id,
1718                                 ctx_txd->tunneling_params,
1719                                 ctx_txd->l2tag2,
1720                                 ctx_txd->rsvd,
1721                                 ctx_txd->type_cmd_tso_mss);
1722
1723                         txe->last_id = tx_last;
1724                         tx_id = txe->next_id;
1725                         txe = txn;
1726                 }
1727
1728                 m_seg = tx_pkt;
1729                 do {
1730                         txd = &txr[tx_id];
1731                         txn = &sw_ring[txe->next_id];
1732
1733                         if (txe->mbuf)
1734                                 rte_pktmbuf_free_seg(txe->mbuf);
1735                         txe->mbuf = m_seg;
1736
1737                         /* Setup TX Descriptor */
1738                         slen = m_seg->data_len;
1739                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1740
1741                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1742                                 "buf_dma_addr: %#"PRIx64";\n"
1743                                 "td_cmd: %#x;\n"
1744                                 "td_offset: %#x;\n"
1745                                 "td_len: %u;\n"
1746                                 "td_tag: %#x;\n",
1747                                 tx_pkt, tx_id, buf_dma_addr,
1748                                 td_cmd, td_offset, slen, td_tag);
1749
1750                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1751                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1752                                                 td_offset, slen, td_tag);
1753                         txe->last_id = tx_last;
1754                         tx_id = txe->next_id;
1755                         txe = txn;
1756                         m_seg = m_seg->next;
1757                 } while (m_seg != NULL);
1758
1759                 /* The last packet data descriptor needs End Of Packet (EOP) */
1760                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1761                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1762                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1763
1764                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1765                         PMD_TX_FREE_LOG(DEBUG,
1766                                         "Setting RS bit on TXD id="
1767                                         "%4u (port=%d queue=%d)",
1768                                         tx_last, txq->port_id, txq->queue_id);
1769
1770                         td_cmd |= I40E_TX_DESC_CMD_RS;
1771
1772                         /* Update txq RS bit counters */
1773                         txq->nb_tx_used = 0;
1774                 }
1775
1776                 txd->cmd_type_offset_bsz |=
1777                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1778                                         I40E_TXD_QW1_CMD_SHIFT);
1779         }
1780
1781 end_of_tx:
1782         rte_wmb();
1783
1784         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1785                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1786                    (unsigned) tx_id, (unsigned) nb_tx);
1787
1788         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1789         txq->tx_tail = tx_id;
1790
1791         return nb_tx;
1792 }
1793
1794 static inline int __attribute__((always_inline))
1795 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1796 {
1797         struct i40e_tx_entry *txep;
1798         uint16_t i;
1799
1800         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1801                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1802                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1803                 return 0;
1804
1805         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1806
1807         for (i = 0; i < txq->tx_rs_thresh; i++)
1808                 rte_prefetch0((txep + i)->mbuf);
1809
1810         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1811                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1812                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1813                         txep->mbuf = NULL;
1814                 }
1815         } else {
1816                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1817                         rte_pktmbuf_free_seg(txep->mbuf);
1818                         txep->mbuf = NULL;
1819                 }
1820         }
1821
1822         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1823         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1824         if (txq->tx_next_dd >= txq->nb_tx_desc)
1825                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1826
1827         return txq->tx_rs_thresh;
1828 }
1829
1830 /* Populate 4 descriptors with data from 4 mbufs */
1831 static inline void
1832 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1833 {
1834         uint64_t dma_addr;
1835         uint32_t i;
1836
1837         for (i = 0; i < 4; i++, txdp++, pkts++) {
1838                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1839                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1840                 txdp->cmd_type_offset_bsz =
1841                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1842                                         (*pkts)->data_len, 0);
1843         }
1844 }
1845
1846 /* Populate 1 descriptor with data from 1 mbuf */
1847 static inline void
1848 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1849 {
1850         uint64_t dma_addr;
1851
1852         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1853         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1854         txdp->cmd_type_offset_bsz =
1855                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1856                                 (*pkts)->data_len, 0);
1857 }
1858
1859 /* Fill hardware descriptor ring with mbuf data */
1860 static inline void
1861 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1862                      struct rte_mbuf **pkts,
1863                      uint16_t nb_pkts)
1864 {
1865         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1866         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1867         const int N_PER_LOOP = 4;
1868         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1869         int mainpart, leftover;
1870         int i, j;
1871
1872         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1873         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1874         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1875                 for (j = 0; j < N_PER_LOOP; ++j) {
1876                         (txep + i + j)->mbuf = *(pkts + i + j);
1877                 }
1878                 tx4(txdp + i, pkts + i);
1879         }
1880         if (unlikely(leftover > 0)) {
1881                 for (i = 0; i < leftover; ++i) {
1882                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1883                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1884                 }
1885         }
1886 }
1887
1888 static inline uint16_t
1889 tx_xmit_pkts(struct i40e_tx_queue *txq,
1890              struct rte_mbuf **tx_pkts,
1891              uint16_t nb_pkts)
1892 {
1893         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1894         uint16_t n = 0;
1895
1896         /**
1897          * Begin scanning the H/W ring for done descriptors when the number
1898          * of available descriptors drops below tx_free_thresh. For each done
1899          * descriptor, free the associated buffer.
1900          */
1901         if (txq->nb_tx_free < txq->tx_free_thresh)
1902                 i40e_tx_free_bufs(txq);
1903
1904         /* Use available descriptor only */
1905         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1906         if (unlikely(!nb_pkts))
1907                 return 0;
1908
1909         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1910         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1911                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1912                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1913                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1914                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1915                                                 I40E_TXD_QW1_CMD_SHIFT);
1916                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1917                 txq->tx_tail = 0;
1918         }
1919
1920         /* Fill hardware descriptor ring with mbuf data */
1921         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1922         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1923
1924         /* Determin if RS bit needs to be set */
1925         if (txq->tx_tail > txq->tx_next_rs) {
1926                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1927                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1928                                                 I40E_TXD_QW1_CMD_SHIFT);
1929                 txq->tx_next_rs =
1930                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1931                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1932                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1933         }
1934
1935         if (txq->tx_tail >= txq->nb_tx_desc)
1936                 txq->tx_tail = 0;
1937
1938         /* Update the tx tail register */
1939         rte_wmb();
1940         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1941
1942         return nb_pkts;
1943 }
1944
1945 static uint16_t
1946 i40e_xmit_pkts_simple(void *tx_queue,
1947                       struct rte_mbuf **tx_pkts,
1948                       uint16_t nb_pkts)
1949 {
1950         uint16_t nb_tx = 0;
1951
1952         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1953                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1954                                                 tx_pkts, nb_pkts);
1955
1956         while (nb_pkts) {
1957                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1958                                                 I40E_TX_MAX_BURST);
1959
1960                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1961                                                 &tx_pkts[nb_tx], num);
1962                 nb_tx = (uint16_t)(nb_tx + ret);
1963                 nb_pkts = (uint16_t)(nb_pkts - ret);
1964                 if (ret < num)
1965                         break;
1966         }
1967
1968         return nb_tx;
1969 }
1970
1971 /*
1972  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1973  * application used, which assume having sequential ones. But from driver's
1974  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1975  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1976  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1977  * use queue_idx from 0 to 95 to access queues, while real queue would be
1978  * different. This function will do a queue mapping to find VSI the queue
1979  * belongs to.
1980  */
1981 static struct i40e_vsi*
1982 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1983 {
1984         /* the queue in MAIN VSI range */
1985         if (queue_idx < pf->main_vsi->nb_qps)
1986                 return pf->main_vsi;
1987
1988         queue_idx -= pf->main_vsi->nb_qps;
1989
1990         /* queue_idx is greater than VMDQ VSIs range */
1991         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1992                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1993                 return NULL;
1994         }
1995
1996         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1997 }
1998
1999 static uint16_t
2000 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
2001 {
2002         /* the queue in MAIN VSI range */
2003         if (queue_idx < pf->main_vsi->nb_qps)
2004                 return queue_idx;
2005
2006         /* It's VMDQ queues */
2007         queue_idx -= pf->main_vsi->nb_qps;
2008
2009         if (pf->nb_cfg_vmdq_vsi)
2010                 return queue_idx % pf->vmdq_nb_qps;
2011         else {
2012                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
2013                 return (uint16_t)(-1);
2014         }
2015 }
2016
2017 int
2018 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2019 {
2020         struct i40e_rx_queue *rxq;
2021         int err = -1;
2022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (rx_queue_id < dev->data->nb_rx_queues) {
2027                 rxq = dev->data->rx_queues[rx_queue_id];
2028
2029                 err = i40e_alloc_rx_queue_mbufs(rxq);
2030                 if (err) {
2031                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
2032                         return err;
2033                 }
2034
2035                 rte_wmb();
2036
2037                 /* Init the RX tail regieter. */
2038                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2039
2040                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2041
2042                 if (err) {
2043                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2044                                     rx_queue_id);
2045
2046                         i40e_rx_queue_release_mbufs(rxq);
2047                         i40e_reset_rx_queue(rxq);
2048                 } else
2049                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2050         }
2051
2052         return err;
2053 }
2054
2055 int
2056 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2057 {
2058         struct i40e_rx_queue *rxq;
2059         int err;
2060         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061
2062         if (rx_queue_id < dev->data->nb_rx_queues) {
2063                 rxq = dev->data->rx_queues[rx_queue_id];
2064
2065                 /*
2066                 * rx_queue_id is queue id aplication refers to, while
2067                 * rxq->reg_idx is the real queue index.
2068                 */
2069                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2070
2071                 if (err) {
2072                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2073                                     rx_queue_id);
2074                         return err;
2075                 }
2076                 i40e_rx_queue_release_mbufs(rxq);
2077                 i40e_reset_rx_queue(rxq);
2078                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2079         }
2080
2081         return 0;
2082 }
2083
2084 int
2085 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2086 {
2087         int err = -1;
2088         struct i40e_tx_queue *txq;
2089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         if (tx_queue_id < dev->data->nb_tx_queues) {
2094                 txq = dev->data->tx_queues[tx_queue_id];
2095
2096                 /*
2097                 * tx_queue_id is queue id aplication refers to, while
2098                 * rxq->reg_idx is the real queue index.
2099                 */
2100                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2101                 if (err)
2102                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2103                                     tx_queue_id);
2104                 else
2105                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2106         }
2107
2108         return err;
2109 }
2110
2111 int
2112 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2113 {
2114         struct i40e_tx_queue *txq;
2115         int err;
2116         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117
2118         if (tx_queue_id < dev->data->nb_tx_queues) {
2119                 txq = dev->data->tx_queues[tx_queue_id];
2120
2121                 /*
2122                 * tx_queue_id is queue id aplication refers to, while
2123                 * txq->reg_idx is the real queue index.
2124                 */
2125                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2126
2127                 if (err) {
2128                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2129                                     tx_queue_id);
2130                         return err;
2131                 }
2132
2133                 i40e_tx_queue_release_mbufs(txq);
2134                 i40e_reset_tx_queue(txq);
2135                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2136         }
2137
2138         return 0;
2139 }
2140
2141 const uint32_t *
2142 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2143 {
2144         static const uint32_t ptypes[] = {
2145                 /* refers to i40e_rxd_pkt_type_mapping() */
2146                 RTE_PTYPE_L2_ETHER,
2147                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2148                 RTE_PTYPE_L2_ETHER_LLDP,
2149                 RTE_PTYPE_L2_ETHER_ARP,
2150                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2151                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2152                 RTE_PTYPE_L4_FRAG,
2153                 RTE_PTYPE_L4_ICMP,
2154                 RTE_PTYPE_L4_NONFRAG,
2155                 RTE_PTYPE_L4_SCTP,
2156                 RTE_PTYPE_L4_TCP,
2157                 RTE_PTYPE_L4_UDP,
2158                 RTE_PTYPE_TUNNEL_GRENAT,
2159                 RTE_PTYPE_TUNNEL_IP,
2160                 RTE_PTYPE_INNER_L2_ETHER,
2161                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2162                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2163                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2164                 RTE_PTYPE_INNER_L4_FRAG,
2165                 RTE_PTYPE_INNER_L4_ICMP,
2166                 RTE_PTYPE_INNER_L4_NONFRAG,
2167                 RTE_PTYPE_INNER_L4_SCTP,
2168                 RTE_PTYPE_INNER_L4_TCP,
2169                 RTE_PTYPE_INNER_L4_UDP,
2170                 RTE_PTYPE_UNKNOWN
2171         };
2172
2173         if (dev->rx_pkt_burst == i40e_recv_pkts ||
2174 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2175             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2176 #endif
2177             dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2178                 return ptypes;
2179         return NULL;
2180 }
2181
2182 int
2183 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2184                         uint16_t queue_idx,
2185                         uint16_t nb_desc,
2186                         unsigned int socket_id,
2187                         const struct rte_eth_rxconf *rx_conf,
2188                         struct rte_mempool *mp)
2189 {
2190         struct i40e_vsi *vsi;
2191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct i40e_adapter *ad =
2194                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2195         struct i40e_rx_queue *rxq;
2196         const struct rte_memzone *rz;
2197         uint32_t ring_size;
2198         uint16_t len, i;
2199         uint16_t base, bsf, tc_mapping;
2200         int use_def_burst_func = 1;
2201
2202         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2203                 struct i40e_vf *vf =
2204                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2205                 vsi = &vf->vsi;
2206         } else
2207                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2208
2209         if (vsi == NULL) {
2210                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2211                             "index exceeds the maximum");
2212                 return I40E_ERR_PARAM;
2213         }
2214         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2215                         (nb_desc > I40E_MAX_RING_DESC) ||
2216                         (nb_desc < I40E_MIN_RING_DESC)) {
2217                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2218                             "invalid", nb_desc);
2219                 return I40E_ERR_PARAM;
2220         }
2221
2222         /* Free memory if needed */
2223         if (dev->data->rx_queues[queue_idx]) {
2224                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2225                 dev->data->rx_queues[queue_idx] = NULL;
2226         }
2227
2228         /* Allocate the rx queue data structure */
2229         rxq = rte_zmalloc_socket("i40e rx queue",
2230                                  sizeof(struct i40e_rx_queue),
2231                                  RTE_CACHE_LINE_SIZE,
2232                                  socket_id);
2233         if (!rxq) {
2234                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2235                             "rx queue data structure");
2236                 return -ENOMEM;
2237         }
2238         rxq->mp = mp;
2239         rxq->nb_rx_desc = nb_desc;
2240         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2241         rxq->queue_id = queue_idx;
2242         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2243                 rxq->reg_idx = queue_idx;
2244         else /* PF device */
2245                 rxq->reg_idx = vsi->base_queue +
2246                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2247
2248         rxq->port_id = dev->data->port_id;
2249         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2250                                                         0 : ETHER_CRC_LEN);
2251         rxq->drop_en = rx_conf->rx_drop_en;
2252         rxq->vsi = vsi;
2253         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2254
2255         /* Allocate the maximun number of RX ring hardware descriptor. */
2256         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2257         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2258         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2259                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2260         if (!rz) {
2261                 i40e_dev_rx_queue_release(rxq);
2262                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2263                 return -ENOMEM;
2264         }
2265
2266         /* Zero all the descriptors in the ring. */
2267         memset(rz->addr, 0, ring_size);
2268
2269         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2270         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2271
2272 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2273         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2274 #else
2275         len = nb_desc;
2276 #endif
2277
2278         /* Allocate the software ring. */
2279         rxq->sw_ring =
2280                 rte_zmalloc_socket("i40e rx sw ring",
2281                                    sizeof(struct i40e_rx_entry) * len,
2282                                    RTE_CACHE_LINE_SIZE,
2283                                    socket_id);
2284         if (!rxq->sw_ring) {
2285                 i40e_dev_rx_queue_release(rxq);
2286                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2287                 return -ENOMEM;
2288         }
2289
2290         i40e_reset_rx_queue(rxq);
2291         rxq->q_set = TRUE;
2292         dev->data->rx_queues[queue_idx] = rxq;
2293
2294         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2295
2296         if (!use_def_burst_func) {
2297 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2298                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2299                              "satisfied. Rx Burst Bulk Alloc function will be "
2300                              "used on port=%d, queue=%d.",
2301                              rxq->port_id, rxq->queue_id);
2302 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2303         } else {
2304                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2305                              "not satisfied, Scattered Rx is requested, "
2306                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2307                              "not enabled on port=%d, queue=%d.",
2308                              rxq->port_id, rxq->queue_id);
2309                 ad->rx_bulk_alloc_allowed = false;
2310         }
2311
2312         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2313                 if (!(vsi->enabled_tc & (1 << i)))
2314                         continue;
2315                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2316                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2317                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2318                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2319                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2320
2321                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2322                         rxq->dcb_tc = i;
2323         }
2324
2325         return 0;
2326 }
2327
2328 void
2329 i40e_dev_rx_queue_release(void *rxq)
2330 {
2331         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2332
2333         if (!q) {
2334                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2335                 return;
2336         }
2337
2338         i40e_rx_queue_release_mbufs(q);
2339         rte_free(q->sw_ring);
2340         rte_free(q);
2341 }
2342
2343 uint32_t
2344 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2345 {
2346 #define I40E_RXQ_SCAN_INTERVAL 4
2347         volatile union i40e_rx_desc *rxdp;
2348         struct i40e_rx_queue *rxq;
2349         uint16_t desc = 0;
2350
2351         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2352                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2353                 return 0;
2354         }
2355
2356         rxq = dev->data->rx_queues[rx_queue_id];
2357         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2358         while ((desc < rxq->nb_rx_desc) &&
2359                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2360                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2361                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2362                 /**
2363                  * Check the DD bit of a rx descriptor of each 4 in a group,
2364                  * to avoid checking too frequently and downgrading performance
2365                  * too much.
2366                  */
2367                 desc += I40E_RXQ_SCAN_INTERVAL;
2368                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2369                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2370                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2371                                         desc - rxq->nb_rx_desc]);
2372         }
2373
2374         return desc;
2375 }
2376
2377 int
2378 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2379 {
2380         volatile union i40e_rx_desc *rxdp;
2381         struct i40e_rx_queue *rxq = rx_queue;
2382         uint16_t desc;
2383         int ret;
2384
2385         if (unlikely(offset >= rxq->nb_rx_desc)) {
2386                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2387                 return 0;
2388         }
2389
2390         desc = rxq->rx_tail + offset;
2391         if (desc >= rxq->nb_rx_desc)
2392                 desc -= rxq->nb_rx_desc;
2393
2394         rxdp = &(rxq->rx_ring[desc]);
2395
2396         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2397                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2398                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2399
2400         return ret;
2401 }
2402
2403 int
2404 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2405                         uint16_t queue_idx,
2406                         uint16_t nb_desc,
2407                         unsigned int socket_id,
2408                         const struct rte_eth_txconf *tx_conf)
2409 {
2410         struct i40e_vsi *vsi;
2411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413         struct i40e_tx_queue *txq;
2414         const struct rte_memzone *tz;
2415         uint32_t ring_size;
2416         uint16_t tx_rs_thresh, tx_free_thresh;
2417         uint16_t i, base, bsf, tc_mapping;
2418
2419         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2420                 struct i40e_vf *vf =
2421                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2422                 vsi = &vf->vsi;
2423         } else
2424                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2425
2426         if (vsi == NULL) {
2427                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2428                             "exceeds the maximum", queue_idx);
2429                 return I40E_ERR_PARAM;
2430         }
2431
2432         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2433                         (nb_desc > I40E_MAX_RING_DESC) ||
2434                         (nb_desc < I40E_MIN_RING_DESC)) {
2435                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2436                             "invalid", nb_desc);
2437                 return I40E_ERR_PARAM;
2438         }
2439
2440         /**
2441          * The following two parameters control the setting of the RS bit on
2442          * transmit descriptors. TX descriptors will have their RS bit set
2443          * after txq->tx_rs_thresh descriptors have been used. The TX
2444          * descriptor ring will be cleaned after txq->tx_free_thresh
2445          * descriptors are used or if the number of descriptors required to
2446          * transmit a packet is greater than the number of free TX descriptors.
2447          *
2448          * The following constraints must be satisfied:
2449          *  - tx_rs_thresh must be greater than 0.
2450          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2451          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2452          *  - tx_rs_thresh must be a divisor of the ring size.
2453          *  - tx_free_thresh must be greater than 0.
2454          *  - tx_free_thresh must be less than the size of the ring minus 3.
2455          *
2456          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2457          * race condition, hence the maximum threshold constraints. When set
2458          * to zero use default values.
2459          */
2460         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2461                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2462         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2463                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2464         if (tx_rs_thresh >= (nb_desc - 2)) {
2465                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2466                              "number of TX descriptors minus 2. "
2467                              "(tx_rs_thresh=%u port=%d queue=%d)",
2468                              (unsigned int)tx_rs_thresh,
2469                              (int)dev->data->port_id,
2470                              (int)queue_idx);
2471                 return I40E_ERR_PARAM;
2472         }
2473         if (tx_free_thresh >= (nb_desc - 3)) {
2474                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2475                              "tx_free_thresh must be less than the "
2476                              "number of TX descriptors minus 3. "
2477                              "(tx_free_thresh=%u port=%d queue=%d)",
2478                              (unsigned int)tx_free_thresh,
2479                              (int)dev->data->port_id,
2480                              (int)queue_idx);
2481                 return I40E_ERR_PARAM;
2482         }
2483         if (tx_rs_thresh > tx_free_thresh) {
2484                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2485                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2486                              " tx_rs_thresh=%u port=%d queue=%d)",
2487                              (unsigned int)tx_free_thresh,
2488                              (unsigned int)tx_rs_thresh,
2489                              (int)dev->data->port_id,
2490                              (int)queue_idx);
2491                 return I40E_ERR_PARAM;
2492         }
2493         if ((nb_desc % tx_rs_thresh) != 0) {
2494                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2495                              "number of TX descriptors. (tx_rs_thresh=%u"
2496                              " port=%d queue=%d)",
2497                              (unsigned int)tx_rs_thresh,
2498                              (int)dev->data->port_id,
2499                              (int)queue_idx);
2500                 return I40E_ERR_PARAM;
2501         }
2502         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2503                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2504                              "tx_rs_thresh is greater than 1. "
2505                              "(tx_rs_thresh=%u port=%d queue=%d)",
2506                              (unsigned int)tx_rs_thresh,
2507                              (int)dev->data->port_id,
2508                              (int)queue_idx);
2509                 return I40E_ERR_PARAM;
2510         }
2511
2512         /* Free memory if needed. */
2513         if (dev->data->tx_queues[queue_idx]) {
2514                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2515                 dev->data->tx_queues[queue_idx] = NULL;
2516         }
2517
2518         /* Allocate the TX queue data structure. */
2519         txq = rte_zmalloc_socket("i40e tx queue",
2520                                   sizeof(struct i40e_tx_queue),
2521                                   RTE_CACHE_LINE_SIZE,
2522                                   socket_id);
2523         if (!txq) {
2524                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2525                             "tx queue structure");
2526                 return -ENOMEM;
2527         }
2528
2529         /* Allocate TX hardware ring descriptors. */
2530         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2531         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2532         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2533                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2534         if (!tz) {
2535                 i40e_dev_tx_queue_release(txq);
2536                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2537                 return -ENOMEM;
2538         }
2539
2540         txq->nb_tx_desc = nb_desc;
2541         txq->tx_rs_thresh = tx_rs_thresh;
2542         txq->tx_free_thresh = tx_free_thresh;
2543         txq->pthresh = tx_conf->tx_thresh.pthresh;
2544         txq->hthresh = tx_conf->tx_thresh.hthresh;
2545         txq->wthresh = tx_conf->tx_thresh.wthresh;
2546         txq->queue_id = queue_idx;
2547         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2548                 txq->reg_idx = queue_idx;
2549         else /* PF device */
2550                 txq->reg_idx = vsi->base_queue +
2551                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2552
2553         txq->port_id = dev->data->port_id;
2554         txq->txq_flags = tx_conf->txq_flags;
2555         txq->vsi = vsi;
2556         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2557
2558         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2559         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2560
2561         /* Allocate software ring */
2562         txq->sw_ring =
2563                 rte_zmalloc_socket("i40e tx sw ring",
2564                                    sizeof(struct i40e_tx_entry) * nb_desc,
2565                                    RTE_CACHE_LINE_SIZE,
2566                                    socket_id);
2567         if (!txq->sw_ring) {
2568                 i40e_dev_tx_queue_release(txq);
2569                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2570                 return -ENOMEM;
2571         }
2572
2573         i40e_reset_tx_queue(txq);
2574         txq->q_set = TRUE;
2575         dev->data->tx_queues[queue_idx] = txq;
2576
2577         /* Use a simple TX queue without offloads or multi segs if possible */
2578         i40e_set_tx_function_flag(dev, txq);
2579
2580         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2581                 if (!(vsi->enabled_tc & (1 << i)))
2582                         continue;
2583                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2584                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2585                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2586                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2587                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2588
2589                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2590                         txq->dcb_tc = i;
2591         }
2592
2593         return 0;
2594 }
2595
2596 void
2597 i40e_dev_tx_queue_release(void *txq)
2598 {
2599         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2600
2601         if (!q) {
2602                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2603                 return;
2604         }
2605
2606         i40e_tx_queue_release_mbufs(q);
2607         rte_free(q->sw_ring);
2608         rte_free(q);
2609 }
2610
2611 const struct rte_memzone *
2612 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2613 {
2614         const struct rte_memzone *mz;
2615
2616         mz = rte_memzone_lookup(name);
2617         if (mz)
2618                 return mz;
2619
2620         if (rte_xen_dom0_supported())
2621                 mz = rte_memzone_reserve_bounded(name, len,
2622                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2623         else
2624                 mz = rte_memzone_reserve_aligned(name, len,
2625                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2626         return mz;
2627 }
2628
2629 void
2630 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2631 {
2632         uint16_t i;
2633
2634         /* SSE Vector driver has a different way of releasing mbufs. */
2635         if (rxq->rx_using_sse) {
2636                 i40e_rx_queue_release_mbufs_vec(rxq);
2637                 return;
2638         }
2639
2640         if (!rxq->sw_ring) {
2641                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2642                 return;
2643         }
2644
2645         for (i = 0; i < rxq->nb_rx_desc; i++) {
2646                 if (rxq->sw_ring[i].mbuf) {
2647                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2648                         rxq->sw_ring[i].mbuf = NULL;
2649                 }
2650         }
2651 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2652         if (rxq->rx_nb_avail == 0)
2653                 return;
2654         for (i = 0; i < rxq->rx_nb_avail; i++) {
2655                 struct rte_mbuf *mbuf;
2656
2657                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2658                 rte_pktmbuf_free_seg(mbuf);
2659         }
2660         rxq->rx_nb_avail = 0;
2661 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2662 }
2663
2664 void
2665 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2666 {
2667         unsigned i;
2668         uint16_t len;
2669
2670         if (!rxq) {
2671                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2672                 return;
2673         }
2674
2675 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2676         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2677                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2678         else
2679 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2680                 len = rxq->nb_rx_desc;
2681
2682         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2683                 ((volatile char *)rxq->rx_ring)[i] = 0;
2684
2685 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2686         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2687         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2688                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2689
2690         rxq->rx_nb_avail = 0;
2691         rxq->rx_next_avail = 0;
2692         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2693 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2694         rxq->rx_tail = 0;
2695         rxq->nb_rx_hold = 0;
2696         rxq->pkt_first_seg = NULL;
2697         rxq->pkt_last_seg = NULL;
2698
2699         rxq->rxrearm_start = 0;
2700         rxq->rxrearm_nb = 0;
2701 }
2702
2703 void
2704 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2705 {
2706         uint16_t i;
2707
2708         if (!txq || !txq->sw_ring) {
2709                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2710                 return;
2711         }
2712
2713         for (i = 0; i < txq->nb_tx_desc; i++) {
2714                 if (txq->sw_ring[i].mbuf) {
2715                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2716                         txq->sw_ring[i].mbuf = NULL;
2717                 }
2718         }
2719 }
2720
2721 void
2722 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2723 {
2724         struct i40e_tx_entry *txe;
2725         uint16_t i, prev, size;
2726
2727         if (!txq) {
2728                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2729                 return;
2730         }
2731
2732         txe = txq->sw_ring;
2733         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2734         for (i = 0; i < size; i++)
2735                 ((volatile char *)txq->tx_ring)[i] = 0;
2736
2737         prev = (uint16_t)(txq->nb_tx_desc - 1);
2738         for (i = 0; i < txq->nb_tx_desc; i++) {
2739                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2740
2741                 txd->cmd_type_offset_bsz =
2742                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2743                 txe[i].mbuf =  NULL;
2744                 txe[i].last_id = i;
2745                 txe[prev].next_id = i;
2746                 prev = i;
2747         }
2748
2749         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2750         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2751
2752         txq->tx_tail = 0;
2753         txq->nb_tx_used = 0;
2754
2755         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2756         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2757 }
2758
2759 /* Init the TX queue in hardware */
2760 int
2761 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2762 {
2763         enum i40e_status_code err = I40E_SUCCESS;
2764         struct i40e_vsi *vsi = txq->vsi;
2765         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2766         uint16_t pf_q = txq->reg_idx;
2767         struct i40e_hmc_obj_txq tx_ctx;
2768         uint32_t qtx_ctl;
2769
2770         /* clear the context structure first */
2771         memset(&tx_ctx, 0, sizeof(tx_ctx));
2772         tx_ctx.new_context = 1;
2773         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2774         tx_ctx.qlen = txq->nb_tx_desc;
2775
2776 #ifdef RTE_LIBRTE_IEEE1588
2777         tx_ctx.timesync_ena = 1;
2778 #endif
2779         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2780         if (vsi->type == I40E_VSI_FDIR)
2781                 tx_ctx.fd_ena = TRUE;
2782
2783         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2784         if (err != I40E_SUCCESS) {
2785                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2786                 return err;
2787         }
2788
2789         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2790         if (err != I40E_SUCCESS) {
2791                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2792                 return err;
2793         }
2794
2795         /* Now associate this queue with this PCI function */
2796         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2797         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2798                                         I40E_QTX_CTL_PF_INDX_MASK);
2799         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2800         I40E_WRITE_FLUSH(hw);
2801
2802         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2803
2804         return err;
2805 }
2806
2807 int
2808 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2809 {
2810         struct i40e_rx_entry *rxe = rxq->sw_ring;
2811         uint64_t dma_addr;
2812         uint16_t i;
2813
2814         for (i = 0; i < rxq->nb_rx_desc; i++) {
2815                 volatile union i40e_rx_desc *rxd;
2816                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2817
2818                 if (unlikely(!mbuf)) {
2819                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2820                         return -ENOMEM;
2821                 }
2822
2823                 rte_mbuf_refcnt_set(mbuf, 1);
2824                 mbuf->next = NULL;
2825                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2826                 mbuf->nb_segs = 1;
2827                 mbuf->port = rxq->port_id;
2828
2829                 dma_addr =
2830                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2831
2832                 rxd = &rxq->rx_ring[i];
2833                 rxd->read.pkt_addr = dma_addr;
2834                 rxd->read.hdr_addr = 0;
2835 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2836                 rxd->read.rsvd1 = 0;
2837                 rxd->read.rsvd2 = 0;
2838 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2839
2840                 rxe[i].mbuf = mbuf;
2841         }
2842
2843         return 0;
2844 }
2845
2846 /*
2847  * Calculate the buffer length, and check the jumbo frame
2848  * and maximum packet length.
2849  */
2850 static int
2851 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2852 {
2853         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2854         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2855         struct rte_eth_dev_data *data = pf->dev_data;
2856         uint16_t buf_size, len;
2857
2858         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2859                 RTE_PKTMBUF_HEADROOM);
2860
2861         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2862                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2863         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2864                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2865                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2866                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2867                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2868                 rxq->hs_mode = i40e_header_split_enabled;
2869                 break;
2870         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2871         default:
2872                 rxq->rx_hdr_len = 0;
2873                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2874                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2875                 rxq->hs_mode = i40e_header_split_none;
2876                 break;
2877         }
2878
2879         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2880         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2881         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2882                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2883                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2884                         PMD_DRV_LOG(ERR, "maximum packet length must "
2885                                     "be larger than %u and smaller than %u,"
2886                                     "as jumbo frame is enabled",
2887                                     (uint32_t)ETHER_MAX_LEN,
2888                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2889                         return I40E_ERR_CONFIG;
2890                 }
2891         } else {
2892                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2893                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2894                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2895                                     "larger than %u and smaller than %u, "
2896                                     "as jumbo frame is disabled",
2897                                     (uint32_t)ETHER_MIN_LEN,
2898                                     (uint32_t)ETHER_MAX_LEN);
2899                         return I40E_ERR_CONFIG;
2900                 }
2901         }
2902
2903         return 0;
2904 }
2905
2906 /* Init the RX queue in hardware */
2907 int
2908 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2909 {
2910         int err = I40E_SUCCESS;
2911         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2912         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2913         uint16_t pf_q = rxq->reg_idx;
2914         uint16_t buf_size;
2915         struct i40e_hmc_obj_rxq rx_ctx;
2916
2917         err = i40e_rx_queue_config(rxq);
2918         if (err < 0) {
2919                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2920                 return err;
2921         }
2922
2923         /* Clear the context structure first */
2924         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2925         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2926         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2927
2928         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2929         rx_ctx.qlen = rxq->nb_rx_desc;
2930 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2931         rx_ctx.dsize = 1;
2932 #endif
2933         rx_ctx.dtype = rxq->hs_mode;
2934         if (rxq->hs_mode)
2935                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2936         else
2937                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2938         rx_ctx.rxmax = rxq->max_pkt_len;
2939         rx_ctx.tphrdesc_ena = 1;
2940         rx_ctx.tphwdesc_ena = 1;
2941         rx_ctx.tphdata_ena = 1;
2942         rx_ctx.tphhead_ena = 1;
2943         rx_ctx.lrxqthresh = 2;
2944         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2945         rx_ctx.l2tsel = 1;
2946         /* showiv indicates if inner VLAN is stripped inside of tunnel
2947          * packet. When set it to 1, vlan information is stripped from
2948          * the inner header, but the hardware does not put it in the
2949          * descriptor. So set it zero by default.
2950          */
2951         rx_ctx.showiv = 0;
2952         rx_ctx.prefena = 1;
2953
2954         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2955         if (err != I40E_SUCCESS) {
2956                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2957                 return err;
2958         }
2959         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2960         if (err != I40E_SUCCESS) {
2961                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2962                 return err;
2963         }
2964
2965         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2966
2967         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2968                 RTE_PKTMBUF_HEADROOM);
2969
2970         /* Check if scattered RX needs to be used. */
2971         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2972                 dev_data->scattered_rx = 1;
2973         }
2974
2975         /* Init the RX tail regieter. */
2976         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2977
2978         return 0;
2979 }
2980
2981 void
2982 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2983 {
2984         uint16_t i;
2985
2986         PMD_INIT_FUNC_TRACE();
2987
2988         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2989                 if (!dev->data->tx_queues[i])
2990                         continue;
2991                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2992                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2993         }
2994
2995         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2996                 if (!dev->data->rx_queues[i])
2997                         continue;
2998                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2999                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3000         }
3001 }
3002
3003 void
3004 i40e_dev_free_queues(struct rte_eth_dev *dev)
3005 {
3006         uint16_t i;
3007
3008         PMD_INIT_FUNC_TRACE();
3009
3010         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3011                 if (!dev->data->rx_queues[i])
3012                         continue;
3013                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3014                 dev->data->rx_queues[i] = NULL;
3015         }
3016         dev->data->nb_rx_queues = 0;
3017
3018         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3019                 if (!dev->data->tx_queues[i])
3020                         continue;
3021                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3022                 dev->data->tx_queues[i] = NULL;
3023         }
3024         dev->data->nb_tx_queues = 0;
3025 }
3026
3027 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
3028 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
3029
3030 enum i40e_status_code
3031 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3032 {
3033         struct i40e_tx_queue *txq;
3034         const struct rte_memzone *tz = NULL;
3035         uint32_t ring_size;
3036         struct rte_eth_dev *dev;
3037
3038         if (!pf) {
3039                 PMD_DRV_LOG(ERR, "PF is not available");
3040                 return I40E_ERR_BAD_PTR;
3041         }
3042
3043         dev = pf->adapter->eth_dev;
3044
3045         /* Allocate the TX queue data structure. */
3046         txq = rte_zmalloc_socket("i40e fdir tx queue",
3047                                   sizeof(struct i40e_tx_queue),
3048                                   RTE_CACHE_LINE_SIZE,
3049                                   SOCKET_ID_ANY);
3050         if (!txq) {
3051                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3052                                         "tx queue structure.");
3053                 return I40E_ERR_NO_MEMORY;
3054         }
3055
3056         /* Allocate TX hardware ring descriptors. */
3057         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3058         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3059
3060         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3061                                       I40E_FDIR_QUEUE_ID, ring_size,
3062                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3063         if (!tz) {
3064                 i40e_dev_tx_queue_release(txq);
3065                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3066                 return I40E_ERR_NO_MEMORY;
3067         }
3068
3069         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3070         txq->queue_id = I40E_FDIR_QUEUE_ID;
3071         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3072         txq->vsi = pf->fdir.fdir_vsi;
3073
3074         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3075         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3076         /*
3077          * don't need to allocate software ring and reset for the fdir
3078          * program queue just set the queue has been configured.
3079          */
3080         txq->q_set = TRUE;
3081         pf->fdir.txq = txq;
3082
3083         return I40E_SUCCESS;
3084 }
3085
3086 enum i40e_status_code
3087 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3088 {
3089         struct i40e_rx_queue *rxq;
3090         const struct rte_memzone *rz = NULL;
3091         uint32_t ring_size;
3092         struct rte_eth_dev *dev;
3093
3094         if (!pf) {
3095                 PMD_DRV_LOG(ERR, "PF is not available");
3096                 return I40E_ERR_BAD_PTR;
3097         }
3098
3099         dev = pf->adapter->eth_dev;
3100
3101         /* Allocate the RX queue data structure. */
3102         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3103                                   sizeof(struct i40e_rx_queue),
3104                                   RTE_CACHE_LINE_SIZE,
3105                                   SOCKET_ID_ANY);
3106         if (!rxq) {
3107                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3108                                         "rx queue structure.");
3109                 return I40E_ERR_NO_MEMORY;
3110         }
3111
3112         /* Allocate RX hardware ring descriptors. */
3113         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3114         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3115
3116         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3117                                       I40E_FDIR_QUEUE_ID, ring_size,
3118                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3119         if (!rz) {
3120                 i40e_dev_rx_queue_release(rxq);
3121                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3122                 return I40E_ERR_NO_MEMORY;
3123         }
3124
3125         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3126         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3127         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3128         rxq->vsi = pf->fdir.fdir_vsi;
3129
3130         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3131         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3132
3133         /*
3134          * Don't need to allocate software ring and reset for the fdir
3135          * rx queue, just set the queue has been configured.
3136          */
3137         rxq->q_set = TRUE;
3138         pf->fdir.rxq = rxq;
3139
3140         return I40E_SUCCESS;
3141 }
3142
3143 void
3144 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3145         struct rte_eth_rxq_info *qinfo)
3146 {
3147         struct i40e_rx_queue *rxq;
3148
3149         rxq = dev->data->rx_queues[queue_id];
3150
3151         qinfo->mp = rxq->mp;
3152         qinfo->scattered_rx = dev->data->scattered_rx;
3153         qinfo->nb_desc = rxq->nb_rx_desc;
3154
3155         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3156         qinfo->conf.rx_drop_en = rxq->drop_en;
3157         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3158 }
3159
3160 void
3161 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3162         struct rte_eth_txq_info *qinfo)
3163 {
3164         struct i40e_tx_queue *txq;
3165
3166         txq = dev->data->tx_queues[queue_id];
3167
3168         qinfo->nb_desc = txq->nb_tx_desc;
3169
3170         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3171         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3172         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3173
3174         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3175         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3176         qinfo->conf.txq_flags = txq->txq_flags;
3177         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3178 }
3179
3180 void __attribute__((cold))
3181 i40e_set_rx_function(struct rte_eth_dev *dev)
3182 {
3183         struct i40e_adapter *ad =
3184                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3185         uint16_t rx_using_sse, i;
3186         /* In order to allow Vector Rx there are a few configuration
3187          * conditions to be met and Rx Bulk Allocation should be allowed.
3188          */
3189         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3190                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3191                     !ad->rx_bulk_alloc_allowed) {
3192                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3193                                      " Vector Rx preconditions",
3194                                      dev->data->port_id);
3195
3196                         ad->rx_vec_allowed = false;
3197                 }
3198                 if (ad->rx_vec_allowed) {
3199                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3200                                 struct i40e_rx_queue *rxq =
3201                                         dev->data->rx_queues[i];
3202
3203                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3204                                         ad->rx_vec_allowed = false;
3205                                         break;
3206                                 }
3207                         }
3208                 }
3209         }
3210
3211         if (dev->data->scattered_rx) {
3212                 /* Set the non-LRO scattered callback: there are Vector and
3213                  * single allocation versions.
3214                  */
3215                 if (ad->rx_vec_allowed) {
3216                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3217                                             "callback (port=%d).",
3218                                      dev->data->port_id);
3219
3220                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3221                 } else {
3222                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3223                                            "allocation callback (port=%d).",
3224                                      dev->data->port_id);
3225                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3226                 }
3227         /* If parameters allow we are going to choose between the following
3228          * callbacks:
3229          *    - Vector
3230          *    - Bulk Allocation
3231          *    - Single buffer allocation (the simplest one)
3232          */
3233         } else if (ad->rx_vec_allowed) {
3234                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3235                                     "burst size no less than %d (port=%d).",
3236                              RTE_I40E_DESCS_PER_LOOP,
3237                              dev->data->port_id);
3238
3239                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3240         } else if (ad->rx_bulk_alloc_allowed) {
3241                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3242                                     "satisfied. Rx Burst Bulk Alloc function "
3243                                     "will be used on port=%d.",
3244                              dev->data->port_id);
3245
3246                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3247         } else {
3248                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3249                                     "satisfied, or Scattered Rx is requested "
3250                                     "(port=%d).",
3251                              dev->data->port_id);
3252
3253                 dev->rx_pkt_burst = i40e_recv_pkts;
3254         }
3255
3256         /* Propagate information about RX function choice through all queues. */
3257         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3258                 rx_using_sse =
3259                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3260                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3261
3262                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3263                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3264
3265                         if (rxq)
3266                                 rxq->rx_using_sse = rx_using_sse;
3267                 }
3268         }
3269 }
3270
3271 void __attribute__((cold))
3272 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3273 {
3274         struct i40e_adapter *ad =
3275                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3276
3277         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3278         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3279                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3280                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3281                         PMD_INIT_LOG(DEBUG, "Vector tx"
3282                                      " can be enabled on this txq.");
3283
3284                 } else {
3285                         ad->tx_vec_allowed = false;
3286                 }
3287         } else {
3288                 ad->tx_simple_allowed = false;
3289         }
3290 }
3291
3292 void __attribute__((cold))
3293 i40e_set_tx_function(struct rte_eth_dev *dev)
3294 {
3295         struct i40e_adapter *ad =
3296                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3297         int i;
3298
3299         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3300                 if (ad->tx_vec_allowed) {
3301                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3302                                 struct i40e_tx_queue *txq =
3303                                         dev->data->tx_queues[i];
3304
3305                                 if (txq && i40e_txq_vec_setup(txq)) {
3306                                         ad->tx_vec_allowed = false;
3307                                         break;
3308                                 }
3309                         }
3310                 }
3311         }
3312
3313         if (ad->tx_simple_allowed) {
3314                 if (ad->tx_vec_allowed) {
3315                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3316                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3317                 } else {
3318                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3319                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3320                 }
3321         } else {
3322                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3323                 dev->tx_pkt_burst = i40e_xmit_pkts;
3324         }
3325 }
3326
3327 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3328 int __attribute__((weak))
3329 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3330 {
3331         return -1;
3332 }
3333
3334 uint16_t __attribute__((weak))
3335 i40e_recv_pkts_vec(
3336         void __rte_unused *rx_queue,
3337         struct rte_mbuf __rte_unused **rx_pkts,
3338         uint16_t __rte_unused nb_pkts)
3339 {
3340         return 0;
3341 }
3342
3343 uint16_t __attribute__((weak))
3344 i40e_recv_scattered_pkts_vec(
3345         void __rte_unused *rx_queue,
3346         struct rte_mbuf __rte_unused **rx_pkts,
3347         uint16_t __rte_unused nb_pkts)
3348 {
3349         return 0;
3350 }
3351
3352 int __attribute__((weak))
3353 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3354 {
3355         return -1;
3356 }
3357
3358 int __attribute__((weak))
3359 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3360 {
3361         return -1;
3362 }
3363
3364 void __attribute__((weak))
3365 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3366 {
3367         return;
3368 }
3369
3370 uint16_t __attribute__((weak))
3371 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3372                    struct rte_mbuf __rte_unused **tx_pkts,
3373                    uint16_t __rte_unused nb_pkts)
3374 {
3375         return 0;
3376 }