drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "i40e_logs.h"
  29 #include "base/i40e_prototype.h"
  30 #include "base/i40e_type.h"
  31 #include "i40e_ethdev.h"
  32 #include "i40e_rxtx.h"
  33
  34 #define DEFAULT_TX_RS_THRESH   32
  35 #define DEFAULT_TX_FREE_THRESH 32
  36
  37 #define I40E_TX_MAX_BURST  32
  38
  39 #define I40E_DMA_MEM_ALIGN 4096
  40
  41 /* Base address of the HW descriptor ring should be 128B aligned. */
  42 #define I40E_RING_BASE_ALIGN    128
  43
  44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  45
  46 #ifdef RTE_LIBRTE_IEEE1588
  47 #define I40E_TX_IEEE1588_TMST RTE_MBUF_F_TX_IEEE1588_TMST
  48 #else
  49 #define I40E_TX_IEEE1588_TMST 0
  50 #endif
  51
  52 #define I40E_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |             \
  53                 RTE_MBUF_F_TX_L4_MASK |          \
  54                 RTE_MBUF_F_TX_TCP_SEG |          \
  55                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_IPV4 |        \
  58                 RTE_MBUF_F_TX_OUTER_IPV6 |      \
  59                 RTE_MBUF_F_TX_IPV4 |            \
  60                 RTE_MBUF_F_TX_IPV6 |            \
  61                 RTE_MBUF_F_TX_IP_CKSUM |       \
  62                 RTE_MBUF_F_TX_L4_MASK |        \
  63                 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \
  64                 RTE_MBUF_F_TX_TCP_SEG |        \
  65                 RTE_MBUF_F_TX_QINQ |       \
  66                 RTE_MBUF_F_TX_VLAN |    \
  67                 RTE_MBUF_F_TX_TUNNEL_MASK |     \
  68                 I40E_TX_IEEE1588_TMST)
  69
  70 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  71                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  72
  73 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK (RTE_MBUF_F_TX_IPV4 | \
  74                 RTE_MBUF_F_TX_IPV6 | \
  75                 RTE_MBUF_F_TX_OUTER_IPV4 | \
  76                 RTE_MBUF_F_TX_OUTER_IPV6)
  77
  78 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
  79                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
  80
  81 static int
  82 i40e_monitor_callback(const uint64_t value,
  83                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  84 {
  85         const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
  86         /*
  87          * we expect the DD bit to be set to 1 if this descriptor was already
  88          * written to.
  89          */
  90         return (value & m) == m ? -1 : 0;
  91 }
  92
  93 int
  94 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  95 {
  96         struct i40e_rx_queue *rxq = rx_queue;
  97         volatile union i40e_rx_desc *rxdp;
  98         uint16_t desc;
  99
 100         desc = rxq->rx_tail;
 101         rxdp = &rxq->rx_ring[desc];
 102         /* watch for changes in status bit */
 103         pmc->addr = &rxdp->wb.qword1.status_error_len;
 104
 105         /* comparison callback */
 106         pmc->fn = i40e_monitor_callback;
 107
 108         /* registers are 64-bit */
 109         pmc->size = sizeof(uint64_t);
 110
 111         return 0;
 112 }
 113
 114 static inline void
 115 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 116 {
 117         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 118                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 119                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
 120                 mb->vlan_tci =
 121                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 122                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 123                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 124         } else {
 125                 mb->vlan_tci = 0;
 126         }
 127 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 128         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 129                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 130                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
 131                         RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
 132                 mb->vlan_tci_outer = mb->vlan_tci;
 133                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 134                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 135                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 136                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 137         } else {
 138                 mb->vlan_tci_outer = 0;
 139         }
 140 #endif
 141         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 142                    mb->vlan_tci, mb->vlan_tci_outer);
 143 }
 144
 145 /* Translate the rx descriptor status to pkt flags */
 146 static inline uint64_t
 147 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 148 {
 149         uint64_t flags;
 150
 151         /* Check if RSS_HASH */
 152         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 153                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 154                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
 155
 156         /* Check if FDIR Match */
 157         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 158                                                         RTE_MBUF_F_RX_FDIR : 0);
 159
 160         return flags;
 161 }
 162
 163 static inline uint64_t
 164 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 165 {
 166         uint64_t flags = 0;
 167         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 168
 169 #define I40E_RX_ERR_BITS 0x3f
 170         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 171                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
 172                 return flags;
 173         }
 174
 175         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 176                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 177         else
 178                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 179
 180         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 181                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 182         else
 183                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 184
 185         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 186                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
 187
 188         return flags;
 189 }
 190
 191 /* Function to check and set the ieee1588 timesync index and get the
 192  * appropriate flags.
 193  */
 194 #ifdef RTE_LIBRTE_IEEE1588
 195 static inline uint64_t
 196 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 197 {
 198         uint64_t pkt_flags = 0;
 199         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 200                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 201                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 202
 203         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 204                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 205                 pkt_flags = RTE_MBUF_F_RX_IEEE1588_PTP;
 206         if (tsyn & 0x04) {
 207                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
 208                 mb->timesync = tsyn & 0x03;
 209         }
 210
 211         return pkt_flags;
 212 }
 213 #endif
 214
 215 static inline uint64_t
 216 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 217 {
 218         uint64_t flags = 0;
 219 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 220         uint16_t flexbh, flexbl;
 221
 222         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 223                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 225         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 226                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 227                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 228
 229
 230         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 231                 mb->hash.fdir.hi =
 232                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 233                 flags |= RTE_MBUF_F_RX_FDIR_ID;
 234         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 235                 mb->hash.fdir.hi =
 236                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 237                 flags |= RTE_MBUF_F_RX_FDIR_FLX;
 238         }
 239         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 240                 mb->hash.fdir.lo =
 241                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 242                 flags |= RTE_MBUF_F_RX_FDIR_FLX;
 243         }
 244 #else
 245         mb->hash.fdir.hi =
 246                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 247         flags |= RTE_MBUF_F_RX_FDIR_ID;
 248 #endif
 249         return flags;
 250 }
 251
 252 static inline void
 253 i40e_parse_tunneling_params(uint64_t ol_flags,
 254                             union i40e_tx_offload tx_offload,
 255                             uint32_t *cd_tunneling)
 256 {
 257         /* EIPT: External (outer) IP header type */
 258         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
 259                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 260         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
 261                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 262         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
 263                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 264
 265         /* EIPLEN: External (outer) IP header length, in DWords */
 266         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 267                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 268
 269         /* L4TUNT: L4 Tunneling Type */
 270         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
 271         case RTE_MBUF_F_TX_TUNNEL_IPIP:
 272                 /* for non UDP / GRE tunneling, set to 00b */
 273                 break;
 274         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
 275         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
 276                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 277                 break;
 278         case RTE_MBUF_F_TX_TUNNEL_GRE:
 279                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 280                 break;
 281         default:
 282                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 283                 return;
 284         }
 285
 286         /* L4TUNLEN: L4 Tunneling Length, in Words
 287          *
 288          * We depend on app to set rte_mbuf.l2_len correctly.
 289          * For IP in GRE it should be set to the length of the GRE
 290          * header;
 291          * for MAC in GRE or MAC in UDP it should be set to the length
 292          * of the GRE or UDP headers plus the inner MAC up to including
 293          * its last Ethertype.
 294          */
 295         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 296                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 297 }
 298
 299 static inline void
 300 i40e_txd_enable_checksum(uint64_t ol_flags,
 301                         uint32_t *td_cmd,
 302                         uint32_t *td_offset,
 303                         union i40e_tx_offload tx_offload)
 304 {
 305         /* Set MACLEN */
 306         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
 307                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 308                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 309         else
 310                 *td_offset |= (tx_offload.l2_len >> 1)
 311                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 312
 313         /* Enable L3 checksum offloads */
 314         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
 315                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 316                 *td_offset |= (tx_offload.l3_len >> 2)
 317                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 318         } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
 319                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 320                 *td_offset |= (tx_offload.l3_len >> 2)
 321                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 322         } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
 323                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 324                 *td_offset |= (tx_offload.l3_len >> 2)
 325                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 326         }
 327
 328         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
 329                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 330                 *td_offset |= (tx_offload.l4_len >> 2)
 331                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 332                 return;
 333         }
 334
 335         /* Enable L4 checksum offloads */
 336         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
 337         case RTE_MBUF_F_TX_TCP_CKSUM:
 338                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 339                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 340                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 341                 break;
 342         case RTE_MBUF_F_TX_SCTP_CKSUM:
 343                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 344                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 345                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 346                 break;
 347         case RTE_MBUF_F_TX_UDP_CKSUM:
 348                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 349                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 350                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 351                 break;
 352         default:
 353                 break;
 354         }
 355 }
 356
 357 /* Construct the tx flags */
 358 static inline uint64_t
 359 i40e_build_ctob(uint32_t td_cmd,
 360                 uint32_t td_offset,
 361                 unsigned int size,
 362                 uint32_t td_tag)
 363 {
 364         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 365                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 366                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 367                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 368                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 369 }
 370
 371 static inline int
 372 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 373 {
 374         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 375         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 376         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 377         uint16_t nb_tx_desc = txq->nb_tx_desc;
 378         uint16_t desc_to_clean_to;
 379         uint16_t nb_tx_to_clean;
 380
 381         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 382         if (desc_to_clean_to >= nb_tx_desc)
 383                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 384
 385         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 386         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 387                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 388                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 389                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
 390                            "(port=%d queue=%d)", desc_to_clean_to,
 391                            txq->port_id, txq->queue_id);
 392                 return -1;
 393         }
 394
 395         if (last_desc_cleaned > desc_to_clean_to)
 396                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 397                                                         desc_to_clean_to);
 398         else
 399                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 400                                         last_desc_cleaned);
 401
 402         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 403
 404         txq->last_desc_cleaned = desc_to_clean_to;
 405         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 406
 407         return 0;
 408 }
 409
 410 static inline int
 411 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 412 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 413 #else
 414 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 415 #endif
 416 {
 417         int ret = 0;
 418
 419 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 420         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 421                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 422                              "rxq->rx_free_thresh=%d, "
 423                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 424                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 425                 ret = -EINVAL;
 426         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 427                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 428                              "rxq->rx_free_thresh=%d, "
 429                              "rxq->nb_rx_desc=%d",
 430                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 431                 ret = -EINVAL;
 432         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 433                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 434                              "rxq->nb_rx_desc=%d, "
 435                              "rxq->rx_free_thresh=%d",
 436                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 437                 ret = -EINVAL;
 438         }
 439 #else
 440         ret = -EINVAL;
 441 #endif
 442
 443         return ret;
 444 }
 445
 446 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 447 #define I40E_LOOK_AHEAD 8
 448 #if (I40E_LOOK_AHEAD != 8)
 449 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 450 #endif
 451 static inline int
 452 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 453 {
 454         volatile union i40e_rx_desc *rxdp;
 455         struct i40e_rx_entry *rxep;
 456         struct rte_mbuf *mb;
 457         uint16_t pkt_len;
 458         uint64_t qword1;
 459         uint32_t rx_status;
 460         int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
 461         int32_t i, j, nb_rx = 0;
 462         uint64_t pkt_flags;
 463         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 464
 465         rxdp = &rxq->rx_ring[rxq->rx_tail];
 466         rxep = &rxq->sw_ring[rxq->rx_tail];
 467
 468         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 469         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 470                                 I40E_RXD_QW1_STATUS_SHIFT;
 471
 472         /* Make sure there is at least 1 packet to receive */
 473         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 474                 return 0;
 475
 476         /**
 477          * Scan LOOK_AHEAD descriptors at a time to determine which
 478          * descriptors reference packets that are ready to be received.
 479          */
 480         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 481                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 482                 /* Read desc statuses backwards to avoid race condition */
 483                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 484                         qword1 = rte_le_to_cpu_64(\
 485                                 rxdp[j].wb.qword1.status_error_len);
 486                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 487                                         I40E_RXD_QW1_STATUS_SHIFT;
 488                 }
 489
 490                 /* This barrier is to order loads of different words in the descriptor */
 491                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 492
 493                 /* Compute how many status bits were set */
 494                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
 495                         var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 496 #ifdef RTE_ARCH_ARM
 497                         /* For Arm platforms, only compute continuous status bits */
 498                         if (var)
 499                                 nb_dd += 1;
 500                         else
 501                                 break;
 502 #else
 503                         nb_dd += var;
 504 #endif
 505                 }
 506
 507                 nb_rx += nb_dd;
 508
 509                 /* Translate descriptor info to mbuf parameters */
 510                 for (j = 0; j < nb_dd; j++) {
 511                         mb = rxep[j].mbuf;
 512                         qword1 = rte_le_to_cpu_64(\
 513                                 rxdp[j].wb.qword1.status_error_len);
 514                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 515                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 516                         mb->data_len = pkt_len;
 517                         mb->pkt_len = pkt_len;
 518                         mb->ol_flags = 0;
 519                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 520                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 521                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 522                         mb->packet_type =
 523                                 ptype_tbl[(uint8_t)((qword1 &
 524                                 I40E_RXD_QW1_PTYPE_MASK) >>
 525                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 526                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 527                                 mb->hash.rss = rte_le_to_cpu_32(\
 528                                         rxdp[j].wb.qword0.hi_dword.rss);
 529                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 530                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 531
 532 #ifdef RTE_LIBRTE_IEEE1588
 533                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 534 #endif
 535                         mb->ol_flags |= pkt_flags;
 536
 537                 }
 538
 539                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 540                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 541
 542                 if (nb_dd != I40E_LOOK_AHEAD)
 543                         break;
 544         }
 545
 546         /* Clear software ring entries */
 547         for (i = 0; i < nb_rx; i++)
 548                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 549
 550         return nb_rx;
 551 }
 552
 553 static inline uint16_t
 554 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 555                         struct rte_mbuf **rx_pkts,
 556                         uint16_t nb_pkts)
 557 {
 558         uint16_t i;
 559         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 560
 561         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 562
 563         for (i = 0; i < nb_pkts; i++)
 564                 rx_pkts[i] = stage[i];
 565
 566         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 567         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 568
 569         return nb_pkts;
 570 }
 571
 572 static inline int
 573 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 574 {
 575         volatile union i40e_rx_desc *rxdp;
 576         struct i40e_rx_entry *rxep;
 577         struct rte_mbuf *mb;
 578         uint16_t alloc_idx, i;
 579         uint64_t dma_addr;
 580         int diag;
 581
 582         /* Allocate buffers in bulk */
 583         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 584                                 (rxq->rx_free_thresh - 1));
 585         rxep = &(rxq->sw_ring[alloc_idx]);
 586         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 587                                         rxq->rx_free_thresh);
 588         if (unlikely(diag != 0)) {
 589                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 590                 return -ENOMEM;
 591         }
 592
 593         rxdp = &rxq->rx_ring[alloc_idx];
 594         for (i = 0; i < rxq->rx_free_thresh; i++) {
 595                 if (likely(i < (rxq->rx_free_thresh - 1)))
 596                         /* Prefetch next mbuf */
 597                         rte_prefetch0(rxep[i + 1].mbuf);
 598
 599                 mb = rxep[i].mbuf;
 600                 rte_mbuf_refcnt_set(mb, 1);
 601                 mb->next = NULL;
 602                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 603                 mb->nb_segs = 1;
 604                 mb->port = rxq->port_id;
 605                 dma_addr = rte_cpu_to_le_64(\
 606                         rte_mbuf_data_iova_default(mb));
 607                 rxdp[i].read.hdr_addr = 0;
 608                 rxdp[i].read.pkt_addr = dma_addr;
 609         }
 610
 611         /* Update rx tail regsiter */
 612         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 613
 614         rxq->rx_free_trigger =
 615                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 616         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 617                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 618
 619         return 0;
 620 }
 621
 622 static inline uint16_t
 623 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 624 {
 625         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 626         struct rte_eth_dev *dev;
 627         uint16_t nb_rx = 0;
 628
 629         if (!nb_pkts)
 630                 return 0;
 631
 632         if (rxq->rx_nb_avail)
 633                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 634
 635         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 636         rxq->rx_next_avail = 0;
 637         rxq->rx_nb_avail = nb_rx;
 638         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 639
 640         if (rxq->rx_tail > rxq->rx_free_trigger) {
 641                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 642                         uint16_t i, j;
 643
 644                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 645                         dev->data->rx_mbuf_alloc_failed +=
 646                                 rxq->rx_free_thresh;
 647
 648                         rxq->rx_nb_avail = 0;
 649                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 650                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 651                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 652
 653                         return 0;
 654                 }
 655         }
 656
 657         if (rxq->rx_tail >= rxq->nb_rx_desc)
 658                 rxq->rx_tail = 0;
 659
 660         if (rxq->rx_nb_avail)
 661                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 662
 663         return 0;
 664 }
 665
 666 static uint16_t
 667 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 668                           struct rte_mbuf **rx_pkts,
 669                           uint16_t nb_pkts)
 670 {
 671         uint16_t nb_rx = 0, n, count;
 672
 673         if (unlikely(nb_pkts == 0))
 674                 return 0;
 675
 676         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 677                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 678
 679         while (nb_pkts) {
 680                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 681                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 682                 nb_rx = (uint16_t)(nb_rx + count);
 683                 nb_pkts = (uint16_t)(nb_pkts - count);
 684                 if (count < n)
 685                         break;
 686         }
 687
 688         return nb_rx;
 689 }
 690 #else
 691 static uint16_t
 692 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 693                           struct rte_mbuf __rte_unused **rx_pkts,
 694                           uint16_t __rte_unused nb_pkts)
 695 {
 696         return 0;
 697 }
 698 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 699
 700 uint16_t
 701 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 702 {
 703         struct i40e_rx_queue *rxq;
 704         volatile union i40e_rx_desc *rx_ring;
 705         volatile union i40e_rx_desc *rxdp;
 706         union i40e_rx_desc rxd;
 707         struct i40e_rx_entry *sw_ring;
 708         struct i40e_rx_entry *rxe;
 709         struct rte_eth_dev *dev;
 710         struct rte_mbuf *rxm;
 711         struct rte_mbuf *nmb;
 712         uint16_t nb_rx;
 713         uint32_t rx_status;
 714         uint64_t qword1;
 715         uint16_t rx_packet_len;
 716         uint16_t rx_id, nb_hold;
 717         uint64_t dma_addr;
 718         uint64_t pkt_flags;
 719         uint32_t *ptype_tbl;
 720
 721         nb_rx = 0;
 722         nb_hold = 0;
 723         rxq = rx_queue;
 724         rx_id = rxq->rx_tail;
 725         rx_ring = rxq->rx_ring;
 726         sw_ring = rxq->sw_ring;
 727         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 728
 729         while (nb_rx < nb_pkts) {
 730                 rxdp = &rx_ring[rx_id];
 731                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 732                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 733                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 734
 735                 /* Check the DD bit first */
 736                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 737                         break;
 738
 739                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 740                 if (unlikely(!nmb)) {
 741                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 742                         dev->data->rx_mbuf_alloc_failed++;
 743                         break;
 744                 }
 745
 746                 rxd = *rxdp;
 747                 nb_hold++;
 748                 rxe = &sw_ring[rx_id];
 749                 rx_id++;
 750                 if (unlikely(rx_id == rxq->nb_rx_desc))
 751                         rx_id = 0;
 752
 753                 /* Prefetch next mbuf */
 754                 rte_prefetch0(sw_ring[rx_id].mbuf);
 755
 756                 /**
 757                  * When next RX descriptor is on a cache line boundary,
 758                  * prefetch the next 4 RX descriptors and next 8 pointers
 759                  * to mbufs.
 760                  */
 761                 if ((rx_id & 0x3) == 0) {
 762                         rte_prefetch0(&rx_ring[rx_id]);
 763                         rte_prefetch0(&sw_ring[rx_id]);
 764                 }
 765                 rxm = rxe->mbuf;
 766                 rxe->mbuf = nmb;
 767                 dma_addr =
 768                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 769                 rxdp->read.hdr_addr = 0;
 770                 rxdp->read.pkt_addr = dma_addr;
 771
 772                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 773                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 774
 775                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 776                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 777                 rxm->nb_segs = 1;
 778                 rxm->next = NULL;
 779                 rxm->pkt_len = rx_packet_len;
 780                 rxm->data_len = rx_packet_len;
 781                 rxm->port = rxq->port_id;
 782                 rxm->ol_flags = 0;
 783                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 784                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 785                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 786                 rxm->packet_type =
 787                         ptype_tbl[(uint8_t)((qword1 &
 788                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 789                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 790                         rxm->hash.rss =
 791                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 792                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 793                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 794
 795 #ifdef RTE_LIBRTE_IEEE1588
 796                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 797 #endif
 798                 rxm->ol_flags |= pkt_flags;
 799
 800                 rx_pkts[nb_rx++] = rxm;
 801         }
 802         rxq->rx_tail = rx_id;
 803
 804         /**
 805          * If the number of free RX descriptors is greater than the RX free
 806          * threshold of the queue, advance the receive tail register of queue.
 807          * Update that register with the value of the last processed RX
 808          * descriptor minus 1.
 809          */
 810         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 811         if (nb_hold > rxq->rx_free_thresh) {
 812                 rx_id = (uint16_t) ((rx_id == 0) ?
 813                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 814                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 815                 nb_hold = 0;
 816         }
 817         rxq->nb_rx_hold = nb_hold;
 818
 819         return nb_rx;
 820 }
 821
 822 uint16_t
 823 i40e_recv_scattered_pkts(void *rx_queue,
 824                          struct rte_mbuf **rx_pkts,
 825                          uint16_t nb_pkts)
 826 {
 827         struct i40e_rx_queue *rxq = rx_queue;
 828         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 829         volatile union i40e_rx_desc *rxdp;
 830         union i40e_rx_desc rxd;
 831         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 832         struct i40e_rx_entry *rxe;
 833         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 834         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 835         struct rte_mbuf *nmb, *rxm;
 836         uint16_t rx_id = rxq->rx_tail;
 837         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 838         struct rte_eth_dev *dev;
 839         uint32_t rx_status;
 840         uint64_t qword1;
 841         uint64_t dma_addr;
 842         uint64_t pkt_flags;
 843         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 844
 845         while (nb_rx < nb_pkts) {
 846                 rxdp = &rx_ring[rx_id];
 847                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 848                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 849                                         I40E_RXD_QW1_STATUS_SHIFT;
 850
 851                 /* Check the DD bit */
 852                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 853                         break;
 854
 855                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 856                 if (unlikely(!nmb)) {
 857                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 858                         dev->data->rx_mbuf_alloc_failed++;
 859                         break;
 860                 }
 861
 862                 rxd = *rxdp;
 863                 nb_hold++;
 864                 rxe = &sw_ring[rx_id];
 865                 rx_id++;
 866                 if (rx_id == rxq->nb_rx_desc)
 867                         rx_id = 0;
 868
 869                 /* Prefetch next mbuf */
 870                 rte_prefetch0(sw_ring[rx_id].mbuf);
 871
 872                 /**
 873                  * When next RX descriptor is on a cache line boundary,
 874                  * prefetch the next 4 RX descriptors and next 8 pointers
 875                  * to mbufs.
 876                  */
 877                 if ((rx_id & 0x3) == 0) {
 878                         rte_prefetch0(&rx_ring[rx_id]);
 879                         rte_prefetch0(&sw_ring[rx_id]);
 880                 }
 881
 882                 rxm = rxe->mbuf;
 883                 rxe->mbuf = nmb;
 884                 dma_addr =
 885                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 886
 887                 /* Set data buffer address and data length of the mbuf */
 888                 rxdp->read.hdr_addr = 0;
 889                 rxdp->read.pkt_addr = dma_addr;
 890                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 891                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 892                 rxm->data_len = rx_packet_len;
 893                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 894
 895                 /**
 896                  * If this is the first buffer of the received packet, set the
 897                  * pointer to the first mbuf of the packet and initialize its
 898                  * context. Otherwise, update the total length and the number
 899                  * of segments of the current scattered packet, and update the
 900                  * pointer to the last mbuf of the current packet.
 901                  */
 902                 if (!first_seg) {
 903                         first_seg = rxm;
 904                         first_seg->nb_segs = 1;
 905                         first_seg->pkt_len = rx_packet_len;
 906                 } else {
 907                         first_seg->pkt_len =
 908                                 (uint16_t)(first_seg->pkt_len +
 909                                                 rx_packet_len);
 910                         first_seg->nb_segs++;
 911                         last_seg->next = rxm;
 912                 }
 913
 914                 /**
 915                  * If this is not the last buffer of the received packet,
 916                  * update the pointer to the last mbuf of the current scattered
 917                  * packet and continue to parse the RX ring.
 918                  */
 919                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 920                         last_seg = rxm;
 921                         continue;
 922                 }
 923
 924                 /**
 925                  * This is the last buffer of the received packet. If the CRC
 926                  * is not stripped by the hardware:
 927                  *  - Subtract the CRC length from the total packet length.
 928                  *  - If the last buffer only contains the whole CRC or a part
 929                  *  of it, free the mbuf associated to the last buffer. If part
 930                  *  of the CRC is also contained in the previous mbuf, subtract
 931                  *  the length of that CRC part from the data length of the
 932                  *  previous mbuf.
 933                  */
 934                 rxm->next = NULL;
 935                 if (unlikely(rxq->crc_len > 0)) {
 936                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 937                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 938                                 rte_pktmbuf_free_seg(rxm);
 939                                 first_seg->nb_segs--;
 940                                 last_seg->data_len =
 941                                         (uint16_t)(last_seg->data_len -
 942                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 943                                 last_seg->next = NULL;
 944                         } else
 945                                 rxm->data_len = (uint16_t)(rx_packet_len -
 946                                                         RTE_ETHER_CRC_LEN);
 947                 }
 948
 949                 first_seg->port = rxq->port_id;
 950                 first_seg->ol_flags = 0;
 951                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 952                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 953                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 954                 first_seg->packet_type =
 955                         ptype_tbl[(uint8_t)((qword1 &
 956                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 957                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 958                         first_seg->hash.rss =
 959                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 960                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 961                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 962
 963 #ifdef RTE_LIBRTE_IEEE1588
 964                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 965 #endif
 966                 first_seg->ol_flags |= pkt_flags;
 967
 968                 /* Prefetch data of first segment, if configured to do so. */
 969                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 970                         first_seg->data_off));
 971                 rx_pkts[nb_rx++] = first_seg;
 972                 first_seg = NULL;
 973         }
 974
 975         /* Record index of the next RX descriptor to probe. */
 976         rxq->rx_tail = rx_id;
 977         rxq->pkt_first_seg = first_seg;
 978         rxq->pkt_last_seg = last_seg;
 979
 980         /**
 981          * If the number of free RX descriptors is greater than the RX free
 982          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 983          * register. Update the RDT with the value of the last processed RX
 984          * descriptor minus 1, to guarantee that the RDT register is never
 985          * equal to the RDH register, which creates a "full" ring situtation
 986          * from the hardware point of view.
 987          */
 988         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 989         if (nb_hold > rxq->rx_free_thresh) {
 990                 rx_id = (uint16_t)(rx_id == 0 ?
 991                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 992                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 993                 nb_hold = 0;
 994         }
 995         rxq->nb_rx_hold = nb_hold;
 996
 997         return nb_rx;
 998 }
 999
1000 /* Check if the context descriptor is needed for TX offloading */
1001 static inline uint16_t
1002 i40e_calc_context_desc(uint64_t flags)
1003 {
1004         static uint64_t mask = RTE_MBUF_F_TX_OUTER_IP_CKSUM |
1005                 RTE_MBUF_F_TX_TCP_SEG |
1006                 RTE_MBUF_F_TX_QINQ |
1007                 RTE_MBUF_F_TX_TUNNEL_MASK;
1008
1009 #ifdef RTE_LIBRTE_IEEE1588
1010         mask |= RTE_MBUF_F_TX_IEEE1588_TMST;
1011 #endif
1012
1013         return (flags & mask) ? 1 : 0;
1014 }
1015
1016 /* set i40e TSO context descriptor */
1017 static inline uint64_t
1018 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1019 {
1020         uint64_t ctx_desc = 0;
1021         uint32_t cd_cmd, hdr_len, cd_tso_len;
1022
1023         if (!tx_offload.l4_len) {
1024                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1025                 return ctx_desc;
1026         }
1027
1028         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1029         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
1030                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1031
1032         cd_cmd = I40E_TX_CTX_DESC_TSO;
1033         cd_tso_len = mbuf->pkt_len - hdr_len;
1034         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1035                 ((uint64_t)cd_tso_len <<
1036                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1037                 ((uint64_t)mbuf->tso_segsz <<
1038                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1039
1040         return ctx_desc;
1041 }
1042
1043 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1044 #define I40E_MAX_DATA_PER_TXD \
1045         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1046 /* Calculate the number of TX descriptors needed for each pkt */
1047 static inline uint16_t
1048 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1049 {
1050         struct rte_mbuf *txd = tx_pkt;
1051         uint16_t count = 0;
1052
1053         while (txd != NULL) {
1054                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1055                 txd = txd->next;
1056         }
1057
1058         return count;
1059 }
1060
1061 uint16_t
1062 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1063 {
1064         struct i40e_tx_queue *txq;
1065         struct i40e_tx_entry *sw_ring;
1066         struct i40e_tx_entry *txe, *txn;
1067         volatile struct i40e_tx_desc *txd;
1068         volatile struct i40e_tx_desc *txr;
1069         struct rte_mbuf *tx_pkt;
1070         struct rte_mbuf *m_seg;
1071         uint32_t cd_tunneling_params;
1072         uint16_t tx_id;
1073         uint16_t nb_tx;
1074         uint32_t td_cmd;
1075         uint32_t td_offset;
1076         uint32_t td_tag;
1077         uint64_t ol_flags;
1078         uint16_t nb_used;
1079         uint16_t nb_ctx;
1080         uint16_t tx_last;
1081         uint16_t slen;
1082         uint64_t buf_dma_addr;
1083         union i40e_tx_offload tx_offload = {0};
1084
1085         txq = tx_queue;
1086         sw_ring = txq->sw_ring;
1087         txr = txq->tx_ring;
1088         tx_id = txq->tx_tail;
1089         txe = &sw_ring[tx_id];
1090
1091         /* Check if the descriptor ring needs to be cleaned. */
1092         if (txq->nb_tx_free < txq->tx_free_thresh)
1093                 (void)i40e_xmit_cleanup(txq);
1094
1095         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1096                 td_cmd = 0;
1097                 td_tag = 0;
1098                 td_offset = 0;
1099
1100                 tx_pkt = *tx_pkts++;
1101                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1102
1103                 ol_flags = tx_pkt->ol_flags;
1104                 tx_offload.l2_len = tx_pkt->l2_len;
1105                 tx_offload.l3_len = tx_pkt->l3_len;
1106                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1107                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1108                 tx_offload.l4_len = tx_pkt->l4_len;
1109                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1110
1111                 /* Calculate the number of context descriptors needed. */
1112                 nb_ctx = i40e_calc_context_desc(ol_flags);
1113
1114                 /**
1115                  * The number of descriptors that must be allocated for
1116                  * a packet equals to the number of the segments of that
1117                  * packet plus 1 context descriptor if needed.
1118                  * Recalculate the needed tx descs when TSO enabled in case
1119                  * the mbuf data size exceeds max data size that hw allows
1120                  * per tx desc.
1121                  */
1122                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1123                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1124                                              nb_ctx);
1125                 else
1126                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1127                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1128
1129                 /* Circular ring */
1130                 if (tx_last >= txq->nb_tx_desc)
1131                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1132
1133                 if (nb_used > txq->nb_tx_free) {
1134                         if (i40e_xmit_cleanup(txq) != 0) {
1135                                 if (nb_tx == 0)
1136                                         return 0;
1137                                 goto end_of_tx;
1138                         }
1139                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1140                                 while (nb_used > txq->nb_tx_free) {
1141                                         if (i40e_xmit_cleanup(txq) != 0) {
1142                                                 if (nb_tx == 0)
1143                                                         return 0;
1144                                                 goto end_of_tx;
1145                                         }
1146                                 }
1147                         }
1148                 }
1149
1150                 /* Descriptor based VLAN insertion */
1151                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
1152                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1153                         td_tag = tx_pkt->vlan_tci;
1154                 }
1155
1156                 /* Always enable CRC offload insertion */
1157                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1158
1159                 /* Fill in tunneling parameters if necessary */
1160                 cd_tunneling_params = 0;
1161                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
1162                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1163                                                     &cd_tunneling_params);
1164                 /* Enable checksum offloading */
1165                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1166                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1167                                                  &td_offset, tx_offload);
1168
1169                 if (nb_ctx) {
1170                         /* Setup TX context descriptor if required */
1171                         volatile struct i40e_tx_context_desc *ctx_txd =
1172                                 (volatile struct i40e_tx_context_desc *)\
1173                                                         &txr[tx_id];
1174                         uint16_t cd_l2tag2 = 0;
1175                         uint64_t cd_type_cmd_tso_mss =
1176                                 I40E_TX_DESC_DTYPE_CONTEXT;
1177
1178                         txn = &sw_ring[txe->next_id];
1179                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1180                         if (txe->mbuf != NULL) {
1181                                 rte_pktmbuf_free_seg(txe->mbuf);
1182                                 txe->mbuf = NULL;
1183                         }
1184
1185                         /* TSO enabled means no timestamp */
1186                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1187                                 cd_type_cmd_tso_mss |=
1188                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1189                         else {
1190 #ifdef RTE_LIBRTE_IEEE1588
1191                                 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
1192                                         cd_type_cmd_tso_mss |=
1193                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1194                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1195 #endif
1196                         }
1197
1198                         ctx_txd->tunneling_params =
1199                                 rte_cpu_to_le_32(cd_tunneling_params);
1200                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
1201                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1202                                 cd_type_cmd_tso_mss |=
1203                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1204                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1205                         }
1206                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1207                         ctx_txd->type_cmd_tso_mss =
1208                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1209
1210                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1211                                 "tunneling_params: %#x;\n"
1212                                 "l2tag2: %#hx;\n"
1213                                 "rsvd: %#hx;\n"
1214                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1215                                 tx_pkt, tx_id,
1216                                 ctx_txd->tunneling_params,
1217                                 ctx_txd->l2tag2,
1218                                 ctx_txd->rsvd,
1219                                 ctx_txd->type_cmd_tso_mss);
1220
1221                         txe->last_id = tx_last;
1222                         tx_id = txe->next_id;
1223                         txe = txn;
1224                 }
1225
1226                 m_seg = tx_pkt;
1227                 do {
1228                         txd = &txr[tx_id];
1229                         txn = &sw_ring[txe->next_id];
1230
1231                         if (txe->mbuf)
1232                                 rte_pktmbuf_free_seg(txe->mbuf);
1233                         txe->mbuf = m_seg;
1234
1235                         /* Setup TX Descriptor */
1236                         slen = m_seg->data_len;
1237                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1238
1239                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
1240                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1241                                 txd->buffer_addr =
1242                                         rte_cpu_to_le_64(buf_dma_addr);
1243                                 txd->cmd_type_offset_bsz =
1244                                         i40e_build_ctob(td_cmd,
1245                                         td_offset, I40E_MAX_DATA_PER_TXD,
1246                                         td_tag);
1247
1248                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1249                                 slen -= I40E_MAX_DATA_PER_TXD;
1250
1251                                 txe->last_id = tx_last;
1252                                 tx_id = txe->next_id;
1253                                 txe = txn;
1254                                 txd = &txr[tx_id];
1255                                 txn = &sw_ring[txe->next_id];
1256                         }
1257                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1258                                 "buf_dma_addr: %#"PRIx64";\n"
1259                                 "td_cmd: %#x;\n"
1260                                 "td_offset: %#x;\n"
1261                                 "td_len: %u;\n"
1262                                 "td_tag: %#x;\n",
1263                                 tx_pkt, tx_id, buf_dma_addr,
1264                                 td_cmd, td_offset, slen, td_tag);
1265
1266                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1267                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1268                                                 td_offset, slen, td_tag);
1269                         txe->last_id = tx_last;
1270                         tx_id = txe->next_id;
1271                         txe = txn;
1272                         m_seg = m_seg->next;
1273                 } while (m_seg != NULL);
1274
1275                 /* The last packet data descriptor needs End Of Packet (EOP) */
1276                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1277                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1278                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1279
1280                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1281                         PMD_TX_LOG(DEBUG,
1282                                    "Setting RS bit on TXD id="
1283                                    "%4u (port=%d queue=%d)",
1284                                    tx_last, txq->port_id, txq->queue_id);
1285
1286                         td_cmd |= I40E_TX_DESC_CMD_RS;
1287
1288                         /* Update txq RS bit counters */
1289                         txq->nb_tx_used = 0;
1290                 }
1291
1292                 txd->cmd_type_offset_bsz |=
1293                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1294                                         I40E_TXD_QW1_CMD_SHIFT);
1295         }
1296
1297 end_of_tx:
1298         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1299                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1300                    (unsigned) tx_id, (unsigned) nb_tx);
1301
1302         rte_io_wmb();
1303         I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1304         txq->tx_tail = tx_id;
1305
1306         return nb_tx;
1307 }
1308
1309 static __rte_always_inline int
1310 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1311 {
1312         struct i40e_tx_entry *txep;
1313         uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1314         uint16_t i = 0, j = 0;
1315         struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1316         const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1317         const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1318
1319         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1320                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1321                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1322                 return 0;
1323
1324         txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1325
1326         for (i = 0; i < tx_rs_thresh; i++)
1327                 rte_prefetch0((txep + i)->mbuf);
1328
1329         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
1330                 if (k) {
1331                         for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1332                                 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1333                                         free[i] = txep->mbuf;
1334                                         txep->mbuf = NULL;
1335                                 }
1336                                 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1337                                                 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1338                         }
1339                 }
1340
1341                 if (m) {
1342                         for (i = 0; i < m; ++i, ++txep) {
1343                                 free[i] = txep->mbuf;
1344                                 txep->mbuf = NULL;
1345                         }
1346                         rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1347                 }
1348         } else {
1349                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1350                         rte_pktmbuf_free_seg(txep->mbuf);
1351                         txep->mbuf = NULL;
1352                 }
1353         }
1354
1355         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1356         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1357         if (txq->tx_next_dd >= txq->nb_tx_desc)
1358                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1359
1360         return txq->tx_rs_thresh;
1361 }
1362
1363 /* Populate 4 descriptors with data from 4 mbufs */
1364 static inline void
1365 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1366 {
1367         uint64_t dma_addr;
1368         uint32_t i;
1369
1370         for (i = 0; i < 4; i++, txdp++, pkts++) {
1371                 dma_addr = rte_mbuf_data_iova(*pkts);
1372                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1373                 txdp->cmd_type_offset_bsz =
1374                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1375                                         (*pkts)->data_len, 0);
1376         }
1377 }
1378
1379 /* Populate 1 descriptor with data from 1 mbuf */
1380 static inline void
1381 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1382 {
1383         uint64_t dma_addr;
1384
1385         dma_addr = rte_mbuf_data_iova(*pkts);
1386         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1387         txdp->cmd_type_offset_bsz =
1388                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1389                                 (*pkts)->data_len, 0);
1390 }
1391
1392 /* Fill hardware descriptor ring with mbuf data */
1393 static inline void
1394 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1395                      struct rte_mbuf **pkts,
1396                      uint16_t nb_pkts)
1397 {
1398         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1399         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1400         const int N_PER_LOOP = 4;
1401         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1402         int mainpart, leftover;
1403         int i, j;
1404
1405         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1406         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1407         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1408                 for (j = 0; j < N_PER_LOOP; ++j) {
1409                         (txep + i + j)->mbuf = *(pkts + i + j);
1410                 }
1411                 tx4(txdp + i, pkts + i);
1412         }
1413         if (unlikely(leftover > 0)) {
1414                 for (i = 0; i < leftover; ++i) {
1415                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1416                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1417                 }
1418         }
1419 }
1420
1421 static inline uint16_t
1422 tx_xmit_pkts(struct i40e_tx_queue *txq,
1423              struct rte_mbuf **tx_pkts,
1424              uint16_t nb_pkts)
1425 {
1426         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1427         uint16_t n = 0;
1428
1429         /**
1430          * Begin scanning the H/W ring for done descriptors when the number
1431          * of available descriptors drops below tx_free_thresh. For each done
1432          * descriptor, free the associated buffer.
1433          */
1434         if (txq->nb_tx_free < txq->tx_free_thresh)
1435                 i40e_tx_free_bufs(txq);
1436
1437         /* Use available descriptor only */
1438         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1439         if (unlikely(!nb_pkts))
1440                 return 0;
1441
1442         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1443         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1444                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1445                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1446                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1447                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1448                                                 I40E_TXD_QW1_CMD_SHIFT);
1449                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1450                 txq->tx_tail = 0;
1451         }
1452
1453         /* Fill hardware descriptor ring with mbuf data */
1454         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1455         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1456
1457         /* Determin if RS bit needs to be set */
1458         if (txq->tx_tail > txq->tx_next_rs) {
1459                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1460                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1461                                                 I40E_TXD_QW1_CMD_SHIFT);
1462                 txq->tx_next_rs =
1463                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1464                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1465                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1466         }
1467
1468         if (txq->tx_tail >= txq->nb_tx_desc)
1469                 txq->tx_tail = 0;
1470
1471         /* Update the tx tail register */
1472         I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1473
1474         return nb_pkts;
1475 }
1476
1477 static uint16_t
1478 i40e_xmit_pkts_simple(void *tx_queue,
1479                       struct rte_mbuf **tx_pkts,
1480                       uint16_t nb_pkts)
1481 {
1482         uint16_t nb_tx = 0;
1483
1484         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1485                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1486                                                 tx_pkts, nb_pkts);
1487
1488         while (nb_pkts) {
1489                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1490                                                 I40E_TX_MAX_BURST);
1491
1492                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1493                                                 &tx_pkts[nb_tx], num);
1494                 nb_tx = (uint16_t)(nb_tx + ret);
1495                 nb_pkts = (uint16_t)(nb_pkts - ret);
1496                 if (ret < num)
1497                         break;
1498         }
1499
1500         return nb_tx;
1501 }
1502
1503 static uint16_t
1504 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1505                    uint16_t nb_pkts)
1506 {
1507         uint16_t nb_tx = 0;
1508         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1509
1510         while (nb_pkts) {
1511                 uint16_t ret, num;
1512
1513                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1514                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1515                                                 num);
1516                 nb_tx += ret;
1517                 nb_pkts -= ret;
1518                 if (ret < num)
1519                         break;
1520         }
1521
1522         return nb_tx;
1523 }
1524
1525 /*********************************************************************
1526  *
1527  *  TX simple prep functions
1528  *
1529  **********************************************************************/
1530 uint16_t
1531 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1532                       uint16_t nb_pkts)
1533 {
1534         int i;
1535         uint64_t ol_flags;
1536         struct rte_mbuf *m;
1537
1538         for (i = 0; i < nb_pkts; i++) {
1539                 m = tx_pkts[i];
1540                 ol_flags = m->ol_flags;
1541
1542                 if (m->nb_segs != 1) {
1543                         rte_errno = EINVAL;
1544                         return i;
1545                 }
1546
1547                 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1548                         rte_errno = ENOTSUP;
1549                         return i;
1550                 }
1551
1552                 /* check the size of packet */
1553                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1554                     m->pkt_len > I40E_FRAME_SIZE_MAX) {
1555                         rte_errno = EINVAL;
1556                         return i;
1557                 }
1558         }
1559         return i;
1560 }
1561
1562 /*********************************************************************
1563  *
1564  *  TX prep functions
1565  *
1566  **********************************************************************/
1567 uint16_t
1568 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1569                 uint16_t nb_pkts)
1570 {
1571         int i, ret;
1572         uint64_t ol_flags;
1573         struct rte_mbuf *m;
1574
1575         for (i = 0; i < nb_pkts; i++) {
1576                 m = tx_pkts[i];
1577                 ol_flags = m->ol_flags;
1578
1579                 /* Check for m->nb_segs to not exceed the limits. */
1580                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
1581                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1582                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1583                                 rte_errno = EINVAL;
1584                                 return i;
1585                         }
1586                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1587                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1588                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1589                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1590                         /* MSS outside the range (256B - 9674B) are considered
1591                          * malicious
1592                          */
1593                         rte_errno = EINVAL;
1594                         return i;
1595                 }
1596
1597                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1598                         rte_errno = ENOTSUP;
1599                         return i;
1600                 }
1601
1602                 /* check the size of packet */
1603                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1604                         rte_errno = EINVAL;
1605                         return i;
1606                 }
1607
1608 #ifdef RTE_ETHDEV_DEBUG_TX
1609                 ret = rte_validate_tx_offload(m);
1610                 if (ret != 0) {
1611                         rte_errno = -ret;
1612                         return i;
1613                 }
1614 #endif
1615                 ret = rte_net_intel_cksum_prepare(m);
1616                 if (ret != 0) {
1617                         rte_errno = -ret;
1618                         return i;
1619                 }
1620         }
1621         return i;
1622 }
1623
1624 /*
1625  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1626  * application used, which assume having sequential ones. But from driver's
1627  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1628  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1629  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1630  * use queue_idx from 0 to 95 to access queues, while real queue would be
1631  * different. This function will do a queue mapping to find VSI the queue
1632  * belongs to.
1633  */
1634 static struct i40e_vsi*
1635 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1636 {
1637         /* the queue in MAIN VSI range */
1638         if (queue_idx < pf->main_vsi->nb_qps)
1639                 return pf->main_vsi;
1640
1641         queue_idx -= pf->main_vsi->nb_qps;
1642
1643         /* queue_idx is greater than VMDQ VSIs range */
1644         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1645                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1646                 return NULL;
1647         }
1648
1649         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1650 }
1651
1652 static uint16_t
1653 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1654 {
1655         /* the queue in MAIN VSI range */
1656         if (queue_idx < pf->main_vsi->nb_qps)
1657                 return queue_idx;
1658
1659         /* It's VMDQ queues */
1660         queue_idx -= pf->main_vsi->nb_qps;
1661
1662         if (pf->nb_cfg_vmdq_vsi)
1663                 return queue_idx % pf->vmdq_nb_qps;
1664         else {
1665                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1666                 return (uint16_t)(-1);
1667         }
1668 }
1669
1670 int
1671 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1672 {
1673         struct i40e_rx_queue *rxq;
1674         int err;
1675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676
1677         PMD_INIT_FUNC_TRACE();
1678
1679         rxq = dev->data->rx_queues[rx_queue_id];
1680         if (!rxq || !rxq->q_set) {
1681                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1682                             rx_queue_id);
1683                 return -EINVAL;
1684         }
1685
1686         if (rxq->rx_deferred_start)
1687                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1688                             rx_queue_id);
1689
1690         err = i40e_alloc_rx_queue_mbufs(rxq);
1691         if (err) {
1692                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1693                 return err;
1694         }
1695
1696         /* Init the RX tail regieter. */
1697         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1698
1699         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1700         if (err) {
1701                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1702                             rx_queue_id);
1703
1704                 i40e_rx_queue_release_mbufs(rxq);
1705                 i40e_reset_rx_queue(rxq);
1706                 return err;
1707         }
1708         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1709
1710         return 0;
1711 }
1712
1713 int
1714 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1715 {
1716         struct i40e_rx_queue *rxq;
1717         int err;
1718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719
1720         rxq = dev->data->rx_queues[rx_queue_id];
1721         if (!rxq || !rxq->q_set) {
1722                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1723                                 rx_queue_id);
1724                 return -EINVAL;
1725         }
1726
1727         /*
1728          * rx_queue_id is queue id application refers to, while
1729          * rxq->reg_idx is the real queue index.
1730          */
1731         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1732         if (err) {
1733                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1734                             rx_queue_id);
1735                 return err;
1736         }
1737         i40e_rx_queue_release_mbufs(rxq);
1738         i40e_reset_rx_queue(rxq);
1739         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1740
1741         return 0;
1742 }
1743
1744 int
1745 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1746 {
1747         int err;
1748         struct i40e_tx_queue *txq;
1749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750
1751         PMD_INIT_FUNC_TRACE();
1752
1753         txq = dev->data->tx_queues[tx_queue_id];
1754         if (!txq || !txq->q_set) {
1755                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1756                             tx_queue_id);
1757                 return -EINVAL;
1758         }
1759
1760         if (txq->tx_deferred_start)
1761                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1762                             tx_queue_id);
1763
1764         /*
1765          * tx_queue_id is queue id application refers to, while
1766          * rxq->reg_idx is the real queue index.
1767          */
1768         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1769         if (err) {
1770                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1771                             tx_queue_id);
1772                 return err;
1773         }
1774         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1775
1776         return 0;
1777 }
1778
1779 int
1780 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1781 {
1782         struct i40e_tx_queue *txq;
1783         int err;
1784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1785
1786         txq = dev->data->tx_queues[tx_queue_id];
1787         if (!txq || !txq->q_set) {
1788                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1789                         tx_queue_id);
1790                 return -EINVAL;
1791         }
1792
1793         /*
1794          * tx_queue_id is queue id application refers to, while
1795          * txq->reg_idx is the real queue index.
1796          */
1797         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1798         if (err) {
1799                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1800                             tx_queue_id);
1801                 return err;
1802         }
1803
1804         i40e_tx_queue_release_mbufs(txq);
1805         i40e_reset_tx_queue(txq);
1806         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1807
1808         return 0;
1809 }
1810
1811 const uint32_t *
1812 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1813 {
1814         static const uint32_t ptypes[] = {
1815                 /* refers to i40e_rxd_pkt_type_mapping() */
1816                 RTE_PTYPE_L2_ETHER,
1817                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1818                 RTE_PTYPE_L2_ETHER_LLDP,
1819                 RTE_PTYPE_L2_ETHER_ARP,
1820                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1821                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1822                 RTE_PTYPE_L4_FRAG,
1823                 RTE_PTYPE_L4_ICMP,
1824                 RTE_PTYPE_L4_NONFRAG,
1825                 RTE_PTYPE_L4_SCTP,
1826                 RTE_PTYPE_L4_TCP,
1827                 RTE_PTYPE_L4_UDP,
1828                 RTE_PTYPE_TUNNEL_GRENAT,
1829                 RTE_PTYPE_TUNNEL_IP,
1830                 RTE_PTYPE_INNER_L2_ETHER,
1831                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1832                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1833                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1834                 RTE_PTYPE_INNER_L4_FRAG,
1835                 RTE_PTYPE_INNER_L4_ICMP,
1836                 RTE_PTYPE_INNER_L4_NONFRAG,
1837                 RTE_PTYPE_INNER_L4_SCTP,
1838                 RTE_PTYPE_INNER_L4_TCP,
1839                 RTE_PTYPE_INNER_L4_UDP,
1840                 RTE_PTYPE_UNKNOWN
1841         };
1842
1843         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1844 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1845             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1846 #endif
1847             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1848             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1849             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1850 #ifdef CC_AVX512_SUPPORT
1851             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1852             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1853 #endif
1854             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1855             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1856                 return ptypes;
1857         return NULL;
1858 }
1859
1860 static int
1861 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1862 {
1863         uint16_t i;
1864
1865         for (i = 0; i < num; i++) {
1866                 if (i != idx && queues[i])
1867                         return 0;
1868         }
1869
1870         return 1;
1871 }
1872
1873 static int
1874 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1875                                 struct i40e_rx_queue *rxq)
1876 {
1877         struct i40e_adapter *ad =
1878                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1879         int use_def_burst_func =
1880                 check_rx_burst_bulk_alloc_preconditions(rxq);
1881         uint16_t buf_size =
1882                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1883                            RTE_PKTMBUF_HEADROOM);
1884         int use_scattered_rx =
1885                 (rxq->max_pkt_len > buf_size);
1886
1887         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1888                 PMD_DRV_LOG(ERR,
1889                             "Failed to do RX queue initialization");
1890                 return -EINVAL;
1891         }
1892
1893         if (i40e_dev_first_queue(rxq->queue_id,
1894                                  dev->data->rx_queues,
1895                                  dev->data->nb_rx_queues)) {
1896                 /**
1897                  * If it is the first queue to setup,
1898                  * set all flags to default and call
1899                  * i40e_set_rx_function.
1900                  */
1901                 ad->rx_bulk_alloc_allowed = true;
1902                 ad->rx_vec_allowed = true;
1903                 dev->data->scattered_rx = use_scattered_rx;
1904                 if (use_def_burst_func)
1905                         ad->rx_bulk_alloc_allowed = false;
1906                 i40e_set_rx_function(dev);
1907                 return 0;
1908         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1909                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1910                             " number %d of queue %d isn't power of 2",
1911                             rxq->nb_rx_desc, rxq->queue_id);
1912                 return -EINVAL;
1913         }
1914
1915         /* check bulk alloc conflict */
1916         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1917                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1918                 return -EINVAL;
1919         }
1920         /* check scatterred conflict */
1921         if (!dev->data->scattered_rx && use_scattered_rx) {
1922                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1923                 return -EINVAL;
1924         }
1925         /* check vector conflict */
1926         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1927                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1928                 return -EINVAL;
1929         }
1930
1931         return 0;
1932 }
1933
1934 int
1935 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1936                         uint16_t queue_idx,
1937                         uint16_t nb_desc,
1938                         unsigned int socket_id,
1939                         const struct rte_eth_rxconf *rx_conf,
1940                         struct rte_mempool *mp)
1941 {
1942         struct i40e_adapter *ad =
1943                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1944         struct i40e_vsi *vsi;
1945         struct i40e_pf *pf = NULL;
1946         struct i40e_rx_queue *rxq;
1947         const struct rte_memzone *rz;
1948         uint32_t ring_size;
1949         uint16_t len, i;
1950         uint16_t reg_idx, base, bsf, tc_mapping;
1951         int q_offset, use_def_burst_func = 1;
1952         uint64_t offloads;
1953
1954         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1955
1956         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1957         vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1958         if (!vsi)
1959                 return -EINVAL;
1960         q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1961         if (q_offset < 0)
1962                 return -EINVAL;
1963         reg_idx = vsi->base_queue + q_offset;
1964
1965         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1966             (nb_desc > I40E_MAX_RING_DESC) ||
1967             (nb_desc < I40E_MIN_RING_DESC)) {
1968                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1969                             "invalid", nb_desc);
1970                 return -EINVAL;
1971         }
1972
1973         /* Free memory if needed */
1974         if (dev->data->rx_queues[queue_idx]) {
1975                 i40e_rx_queue_release(dev->data->rx_queues[queue_idx]);
1976                 dev->data->rx_queues[queue_idx] = NULL;
1977         }
1978
1979         /* Allocate the rx queue data structure */
1980         rxq = rte_zmalloc_socket("i40e rx queue",
1981                                  sizeof(struct i40e_rx_queue),
1982                                  RTE_CACHE_LINE_SIZE,
1983                                  socket_id);
1984         if (!rxq) {
1985                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1986                             "rx queue data structure");
1987                 return -ENOMEM;
1988         }
1989         rxq->mp = mp;
1990         rxq->nb_rx_desc = nb_desc;
1991         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1992         rxq->queue_id = queue_idx;
1993         rxq->reg_idx = reg_idx;
1994         rxq->port_id = dev->data->port_id;
1995         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1996                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1997         else
1998                 rxq->crc_len = 0;
1999         rxq->drop_en = rx_conf->rx_drop_en;
2000         rxq->vsi = vsi;
2001         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2002         rxq->offloads = offloads;
2003
2004         /* Allocate the maximun number of RX ring hardware descriptor. */
2005         len = I40E_MAX_RING_DESC;
2006
2007         /**
2008          * Allocating a little more memory because vectorized/bulk_alloc Rx
2009          * functions doesn't check boundaries each time.
2010          */
2011         len += RTE_PMD_I40E_RX_MAX_BURST;
2012
2013         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2014                               I40E_DMA_MEM_ALIGN);
2015
2016         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2017                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2018         if (!rz) {
2019                 i40e_rx_queue_release(rxq);
2020                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2021                 return -ENOMEM;
2022         }
2023
2024         rxq->mz = rz;
2025         /* Zero all the descriptors in the ring. */
2026         memset(rz->addr, 0, ring_size);
2027
2028         rxq->rx_ring_phys_addr = rz->iova;
2029         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2030
2031         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2032
2033         /* Allocate the software ring. */
2034         rxq->sw_ring =
2035                 rte_zmalloc_socket("i40e rx sw ring",
2036                                    sizeof(struct i40e_rx_entry) * len,
2037                                    RTE_CACHE_LINE_SIZE,
2038                                    socket_id);
2039         if (!rxq->sw_ring) {
2040                 i40e_rx_queue_release(rxq);
2041                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2042                 return -ENOMEM;
2043         }
2044
2045         i40e_reset_rx_queue(rxq);
2046         rxq->q_set = TRUE;
2047
2048         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2049                 if (!(vsi->enabled_tc & (1 << i)))
2050                         continue;
2051                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2052                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2053                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2054                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2055                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2056
2057                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2058                         rxq->dcb_tc = i;
2059         }
2060
2061         if (dev->data->dev_started) {
2062                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2063                         i40e_rx_queue_release(rxq);
2064                         return -EINVAL;
2065                 }
2066         } else {
2067                 use_def_burst_func =
2068                         check_rx_burst_bulk_alloc_preconditions(rxq);
2069                 if (!use_def_burst_func) {
2070 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2071                         PMD_INIT_LOG(DEBUG,
2072                           "Rx Burst Bulk Alloc Preconditions are "
2073                           "satisfied. Rx Burst Bulk Alloc function will be "
2074                           "used on port=%d, queue=%d.",
2075                           rxq->port_id, rxq->queue_id);
2076 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2077                 } else {
2078                         PMD_INIT_LOG(DEBUG,
2079                           "Rx Burst Bulk Alloc Preconditions are "
2080                           "not satisfied, Scattered Rx is requested, "
2081                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2082                           "not enabled on port=%d, queue=%d.",
2083                           rxq->port_id, rxq->queue_id);
2084                         ad->rx_bulk_alloc_allowed = false;
2085                 }
2086         }
2087
2088         dev->data->rx_queues[queue_idx] = rxq;
2089         return 0;
2090 }
2091
2092 void
2093 i40e_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2094 {
2095         i40e_rx_queue_release(dev->data->rx_queues[qid]);
2096 }
2097
2098 void
2099 i40e_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2100 {
2101         i40e_tx_queue_release(dev->data->tx_queues[qid]);
2102 }
2103
2104 void
2105 i40e_rx_queue_release(void *rxq)
2106 {
2107         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2108
2109         if (!q) {
2110                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2111                 return;
2112         }
2113
2114         i40e_rx_queue_release_mbufs(q);
2115         rte_free(q->sw_ring);
2116         rte_memzone_free(q->mz);
2117         rte_free(q);
2118 }
2119
2120 uint32_t
2121 i40e_dev_rx_queue_count(void *rx_queue)
2122 {
2123 #define I40E_RXQ_SCAN_INTERVAL 4
2124         volatile union i40e_rx_desc *rxdp;
2125         struct i40e_rx_queue *rxq;
2126         uint16_t desc = 0;
2127
2128         rxq = rx_queue;
2129         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2130         while ((desc < rxq->nb_rx_desc) &&
2131                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2132                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2133                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2134                 /**
2135                  * Check the DD bit of a rx descriptor of each 4 in a group,
2136                  * to avoid checking too frequently and downgrading performance
2137                  * too much.
2138                  */
2139                 desc += I40E_RXQ_SCAN_INTERVAL;
2140                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2141                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2142                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2143                                         desc - rxq->nb_rx_desc]);
2144         }
2145
2146         return desc;
2147 }
2148
2149 int
2150 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2151 {
2152         struct i40e_rx_queue *rxq = rx_queue;
2153         volatile uint64_t *status;
2154         uint64_t mask;
2155         uint32_t desc;
2156
2157         if (unlikely(offset >= rxq->nb_rx_desc))
2158                 return -EINVAL;
2159
2160         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2161                 return RTE_ETH_RX_DESC_UNAVAIL;
2162
2163         desc = rxq->rx_tail + offset;
2164         if (desc >= rxq->nb_rx_desc)
2165                 desc -= rxq->nb_rx_desc;
2166
2167         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2168         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2169                 << I40E_RXD_QW1_STATUS_SHIFT);
2170         if (*status & mask)
2171                 return RTE_ETH_RX_DESC_DONE;
2172
2173         return RTE_ETH_RX_DESC_AVAIL;
2174 }
2175
2176 int
2177 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2178 {
2179         struct i40e_tx_queue *txq = tx_queue;
2180         volatile uint64_t *status;
2181         uint64_t mask, expect;
2182         uint32_t desc;
2183
2184         if (unlikely(offset >= txq->nb_tx_desc))
2185                 return -EINVAL;
2186
2187         desc = txq->tx_tail + offset;
2188         /* go to next desc that has the RS bit */
2189         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2190                 txq->tx_rs_thresh;
2191         if (desc >= txq->nb_tx_desc) {
2192                 desc -= txq->nb_tx_desc;
2193                 if (desc >= txq->nb_tx_desc)
2194                         desc -= txq->nb_tx_desc;
2195         }
2196
2197         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2198         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2199         expect = rte_cpu_to_le_64(
2200                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2201         if ((*status & mask) == expect)
2202                 return RTE_ETH_TX_DESC_DONE;
2203
2204         return RTE_ETH_TX_DESC_FULL;
2205 }
2206
2207 static int
2208 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2209                                 struct i40e_tx_queue *txq)
2210 {
2211         struct i40e_adapter *ad =
2212                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2213
2214         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2215                 PMD_DRV_LOG(ERR,
2216                             "Failed to do TX queue initialization");
2217                 return -EINVAL;
2218         }
2219
2220         if (i40e_dev_first_queue(txq->queue_id,
2221                                  dev->data->tx_queues,
2222                                  dev->data->nb_tx_queues)) {
2223                 /**
2224                  * If it is the first queue to setup,
2225                  * set all flags and call
2226                  * i40e_set_tx_function.
2227                  */
2228                 i40e_set_tx_function_flag(dev, txq);
2229                 i40e_set_tx_function(dev);
2230                 return 0;
2231         }
2232
2233         /* check vector conflict */
2234         if (ad->tx_vec_allowed) {
2235                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2236                     i40e_txq_vec_setup(txq)) {
2237                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2238                         return -EINVAL;
2239                 }
2240         }
2241         /* check simple tx conflict */
2242         if (ad->tx_simple_allowed) {
2243                 if ((txq->offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2244                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2245                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2246                         return -EINVAL;
2247                 }
2248         }
2249
2250         return 0;
2251 }
2252
2253 int
2254 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2255                         uint16_t queue_idx,
2256                         uint16_t nb_desc,
2257                         unsigned int socket_id,
2258                         const struct rte_eth_txconf *tx_conf)
2259 {
2260         struct i40e_vsi *vsi;
2261         struct i40e_pf *pf = NULL;
2262         struct i40e_tx_queue *txq;
2263         const struct rte_memzone *tz;
2264         uint32_t ring_size;
2265         uint16_t tx_rs_thresh, tx_free_thresh;
2266         uint16_t reg_idx, i, base, bsf, tc_mapping;
2267         int q_offset;
2268         uint64_t offloads;
2269
2270         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2271
2272         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2273         vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2274         if (!vsi)
2275                 return -EINVAL;
2276         q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2277         if (q_offset < 0)
2278                 return -EINVAL;
2279         reg_idx = vsi->base_queue + q_offset;
2280
2281         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2282             (nb_desc > I40E_MAX_RING_DESC) ||
2283             (nb_desc < I40E_MIN_RING_DESC)) {
2284                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2285                             "invalid", nb_desc);
2286                 return -EINVAL;
2287         }
2288
2289         /**
2290          * The following two parameters control the setting of the RS bit on
2291          * transmit descriptors. TX descriptors will have their RS bit set
2292          * after txq->tx_rs_thresh descriptors have been used. The TX
2293          * descriptor ring will be cleaned after txq->tx_free_thresh
2294          * descriptors are used or if the number of descriptors required to
2295          * transmit a packet is greater than the number of free TX descriptors.
2296          *
2297          * The following constraints must be satisfied:
2298          *  - tx_rs_thresh must be greater than 0.
2299          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2300          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2301          *  - tx_rs_thresh must be a divisor of the ring size.
2302          *  - tx_free_thresh must be greater than 0.
2303          *  - tx_free_thresh must be less than the size of the ring minus 3.
2304          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2305          *
2306          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2307          * race condition, hence the maximum threshold constraints. When set
2308          * to zero use default values.
2309          */
2310         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2311                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2312         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2313         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2314                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2315         if (tx_conf->tx_rs_thresh > 0)
2316                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2317         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2318                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2319                                 "exceed nb_desc. (tx_rs_thresh=%u "
2320                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2321                                 (unsigned int)tx_rs_thresh,
2322                                 (unsigned int)tx_free_thresh,
2323                                 (unsigned int)nb_desc,
2324                                 (int)dev->data->port_id,
2325                                 (int)queue_idx);
2326                 return I40E_ERR_PARAM;
2327         }
2328         if (tx_rs_thresh >= (nb_desc - 2)) {
2329                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2330                              "number of TX descriptors minus 2. "
2331                              "(tx_rs_thresh=%u port=%d queue=%d)",
2332                              (unsigned int)tx_rs_thresh,
2333                              (int)dev->data->port_id,
2334                              (int)queue_idx);
2335                 return I40E_ERR_PARAM;
2336         }
2337         if (tx_free_thresh >= (nb_desc - 3)) {
2338                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2339                              "number of TX descriptors minus 3. "
2340                              "(tx_free_thresh=%u port=%d queue=%d)",
2341                              (unsigned int)tx_free_thresh,
2342                              (int)dev->data->port_id,
2343                              (int)queue_idx);
2344                 return I40E_ERR_PARAM;
2345         }
2346         if (tx_rs_thresh > tx_free_thresh) {
2347                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2348                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2349                              " tx_rs_thresh=%u port=%d queue=%d)",
2350                              (unsigned int)tx_free_thresh,
2351                              (unsigned int)tx_rs_thresh,
2352                              (int)dev->data->port_id,
2353                              (int)queue_idx);
2354                 return I40E_ERR_PARAM;
2355         }
2356         if ((nb_desc % tx_rs_thresh) != 0) {
2357                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2358                              "number of TX descriptors. (tx_rs_thresh=%u"
2359                              " port=%d queue=%d)",
2360                              (unsigned int)tx_rs_thresh,
2361                              (int)dev->data->port_id,
2362                              (int)queue_idx);
2363                 return I40E_ERR_PARAM;
2364         }
2365         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2366                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2367                              "tx_rs_thresh is greater than 1. "
2368                              "(tx_rs_thresh=%u port=%d queue=%d)",
2369                              (unsigned int)tx_rs_thresh,
2370                              (int)dev->data->port_id,
2371                              (int)queue_idx);
2372                 return I40E_ERR_PARAM;
2373         }
2374
2375         /* Free memory if needed. */
2376         if (dev->data->tx_queues[queue_idx]) {
2377                 i40e_tx_queue_release(dev->data->tx_queues[queue_idx]);
2378                 dev->data->tx_queues[queue_idx] = NULL;
2379         }
2380
2381         /* Allocate the TX queue data structure. */
2382         txq = rte_zmalloc_socket("i40e tx queue",
2383                                   sizeof(struct i40e_tx_queue),
2384                                   RTE_CACHE_LINE_SIZE,
2385                                   socket_id);
2386         if (!txq) {
2387                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2388                             "tx queue structure");
2389                 return -ENOMEM;
2390         }
2391
2392         /* Allocate TX hardware ring descriptors. */
2393         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2394         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2395         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2396                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2397         if (!tz) {
2398                 i40e_tx_queue_release(txq);
2399                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2400                 return -ENOMEM;
2401         }
2402
2403         txq->mz = tz;
2404         txq->nb_tx_desc = nb_desc;
2405         txq->tx_rs_thresh = tx_rs_thresh;
2406         txq->tx_free_thresh = tx_free_thresh;
2407         txq->pthresh = tx_conf->tx_thresh.pthresh;
2408         txq->hthresh = tx_conf->tx_thresh.hthresh;
2409         txq->wthresh = tx_conf->tx_thresh.wthresh;
2410         txq->queue_id = queue_idx;
2411         txq->reg_idx = reg_idx;
2412         txq->port_id = dev->data->port_id;
2413         txq->offloads = offloads;
2414         txq->vsi = vsi;
2415         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2416
2417         txq->tx_ring_phys_addr = tz->iova;
2418         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2419
2420         /* Allocate software ring */
2421         txq->sw_ring =
2422                 rte_zmalloc_socket("i40e tx sw ring",
2423                                    sizeof(struct i40e_tx_entry) * nb_desc,
2424                                    RTE_CACHE_LINE_SIZE,
2425                                    socket_id);
2426         if (!txq->sw_ring) {
2427                 i40e_tx_queue_release(txq);
2428                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2429                 return -ENOMEM;
2430         }
2431
2432         i40e_reset_tx_queue(txq);
2433         txq->q_set = TRUE;
2434
2435         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2436                 if (!(vsi->enabled_tc & (1 << i)))
2437                         continue;
2438                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2439                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2440                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2441                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2442                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2443
2444                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2445                         txq->dcb_tc = i;
2446         }
2447
2448         if (dev->data->dev_started) {
2449                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2450                         i40e_tx_queue_release(txq);
2451                         return -EINVAL;
2452                 }
2453         } else {
2454                 /**
2455                  * Use a simple TX queue without offloads or
2456                  * multi segs if possible
2457                  */
2458                 i40e_set_tx_function_flag(dev, txq);
2459         }
2460         dev->data->tx_queues[queue_idx] = txq;
2461
2462         return 0;
2463 }
2464
2465 void
2466 i40e_tx_queue_release(void *txq)
2467 {
2468         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2469
2470         if (!q) {
2471                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2472                 return;
2473         }
2474
2475         i40e_tx_queue_release_mbufs(q);
2476         rte_free(q->sw_ring);
2477         rte_memzone_free(q->mz);
2478         rte_free(q);
2479 }
2480
2481 const struct rte_memzone *
2482 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2483 {
2484         const struct rte_memzone *mz;
2485
2486         mz = rte_memzone_lookup(name);
2487         if (mz)
2488                 return mz;
2489
2490         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2491                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2492         return mz;
2493 }
2494
2495 void
2496 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2497 {
2498         uint16_t i;
2499
2500         /* SSE Vector driver has a different way of releasing mbufs. */
2501         if (rxq->rx_using_sse) {
2502                 i40e_rx_queue_release_mbufs_vec(rxq);
2503                 return;
2504         }
2505
2506         if (!rxq->sw_ring) {
2507                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2508                 return;
2509         }
2510
2511         for (i = 0; i < rxq->nb_rx_desc; i++) {
2512                 if (rxq->sw_ring[i].mbuf) {
2513                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2514                         rxq->sw_ring[i].mbuf = NULL;
2515                 }
2516         }
2517 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2518         if (rxq->rx_nb_avail == 0)
2519                 return;
2520         for (i = 0; i < rxq->rx_nb_avail; i++) {
2521                 struct rte_mbuf *mbuf;
2522
2523                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2524                 rte_pktmbuf_free_seg(mbuf);
2525         }
2526         rxq->rx_nb_avail = 0;
2527 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2528 }
2529
2530 void
2531 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2532 {
2533         unsigned i;
2534         uint16_t len;
2535
2536         if (!rxq) {
2537                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2538                 return;
2539         }
2540
2541 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2542         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2543                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2544         else
2545 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2546                 len = rxq->nb_rx_desc;
2547
2548         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2549                 ((volatile char *)rxq->rx_ring)[i] = 0;
2550
2551         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2552         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2553                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2554
2555 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2556         rxq->rx_nb_avail = 0;
2557         rxq->rx_next_avail = 0;
2558         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2559 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2560         rxq->rx_tail = 0;
2561         rxq->nb_rx_hold = 0;
2562
2563         if (rxq->pkt_first_seg != NULL)
2564                 rte_pktmbuf_free(rxq->pkt_first_seg);
2565
2566         rxq->pkt_first_seg = NULL;
2567         rxq->pkt_last_seg = NULL;
2568
2569         rxq->rxrearm_start = 0;
2570         rxq->rxrearm_nb = 0;
2571 }
2572
2573 void
2574 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2575 {
2576         struct rte_eth_dev *dev;
2577         uint16_t i;
2578
2579         if (!txq || !txq->sw_ring) {
2580                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2581                 return;
2582         }
2583
2584         dev = &rte_eth_devices[txq->port_id];
2585
2586         /**
2587          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2588          *  so need to free remains more carefully.
2589          */
2590 #ifdef CC_AVX512_SUPPORT
2591         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2592                 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2593
2594                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2595                 if (txq->tx_tail < i) {
2596                         for (; i < txq->nb_tx_desc; i++) {
2597                                 rte_pktmbuf_free_seg(swr[i].mbuf);
2598                                 swr[i].mbuf = NULL;
2599                         }
2600                         i = 0;
2601                 }
2602                 for (; i < txq->tx_tail; i++) {
2603                         rte_pktmbuf_free_seg(swr[i].mbuf);
2604                         swr[i].mbuf = NULL;
2605                 }
2606                 return;
2607         }
2608 #endif
2609         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2610                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2611                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2612                 if (txq->tx_tail < i) {
2613                         for (; i < txq->nb_tx_desc; i++) {
2614                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2615                                 txq->sw_ring[i].mbuf = NULL;
2616                         }
2617                         i = 0;
2618                 }
2619                 for (; i < txq->tx_tail; i++) {
2620                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2621                         txq->sw_ring[i].mbuf = NULL;
2622                 }
2623         } else {
2624                 for (i = 0; i < txq->nb_tx_desc; i++) {
2625                         if (txq->sw_ring[i].mbuf) {
2626                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2627                                 txq->sw_ring[i].mbuf = NULL;
2628                         }
2629                 }
2630         }
2631 }
2632
2633 static int
2634 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2635                         uint32_t free_cnt)
2636 {
2637         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2638         uint16_t i, tx_last, tx_id;
2639         uint16_t nb_tx_free_last;
2640         uint16_t nb_tx_to_clean;
2641         uint32_t pkt_cnt;
2642
2643         /* Start free mbuf from the next of tx_tail */
2644         tx_last = txq->tx_tail;
2645         tx_id  = swr_ring[tx_last].next_id;
2646
2647         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2648                 return 0;
2649
2650         nb_tx_to_clean = txq->nb_tx_free;
2651         nb_tx_free_last = txq->nb_tx_free;
2652         if (!free_cnt)
2653                 free_cnt = txq->nb_tx_desc;
2654
2655         /* Loop through swr_ring to count the amount of
2656          * freeable mubfs and packets.
2657          */
2658         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2659                 for (i = 0; i < nb_tx_to_clean &&
2660                         pkt_cnt < free_cnt &&
2661                         tx_id != tx_last; i++) {
2662                         if (swr_ring[tx_id].mbuf != NULL) {
2663                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2664                                 swr_ring[tx_id].mbuf = NULL;
2665
2666                                 /*
2667                                  * last segment in the packet,
2668                                  * increment packet count
2669                                  */
2670                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2671                         }
2672
2673                         tx_id = swr_ring[tx_id].next_id;
2674                 }
2675
2676                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2677                         txq->nb_tx_free || tx_id == tx_last)
2678                         break;
2679
2680                 if (pkt_cnt < free_cnt) {
2681                         if (i40e_xmit_cleanup(txq))
2682                                 break;
2683
2684                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2685                         nb_tx_free_last = txq->nb_tx_free;
2686                 }
2687         }
2688
2689         return (int)pkt_cnt;
2690 }
2691
2692 static int
2693 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2694                         uint32_t free_cnt)
2695 {
2696         int i, n, cnt;
2697
2698         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2699                 free_cnt = txq->nb_tx_desc;
2700
2701         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2702
2703         for (i = 0; i < cnt; i += n) {
2704                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2705                         break;
2706
2707                 n = i40e_tx_free_bufs(txq);
2708
2709                 if (n == 0)
2710                         break;
2711         }
2712
2713         return i;
2714 }
2715
2716 static int
2717 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2718                         uint32_t free_cnt __rte_unused)
2719 {
2720         return -ENOTSUP;
2721 }
2722 int
2723 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2724 {
2725         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2726         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2727         struct i40e_adapter *ad =
2728                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2729
2730         if (ad->tx_simple_allowed) {
2731                 if (ad->tx_vec_allowed)
2732                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2733                 else
2734                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2735         } else {
2736                 return i40e_tx_done_cleanup_full(q, free_cnt);
2737         }
2738 }
2739
2740 void
2741 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2742 {
2743         struct i40e_tx_entry *txe;
2744         uint16_t i, prev, size;
2745
2746         if (!txq) {
2747                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2748                 return;
2749         }
2750
2751         txe = txq->sw_ring;
2752         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2753         for (i = 0; i < size; i++)
2754                 ((volatile char *)txq->tx_ring)[i] = 0;
2755
2756         prev = (uint16_t)(txq->nb_tx_desc - 1);
2757         for (i = 0; i < txq->nb_tx_desc; i++) {
2758                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2759
2760                 txd->cmd_type_offset_bsz =
2761                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2762                 txe[i].mbuf =  NULL;
2763                 txe[i].last_id = i;
2764                 txe[prev].next_id = i;
2765                 prev = i;
2766         }
2767
2768         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2769         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2770
2771         txq->tx_tail = 0;
2772         txq->nb_tx_used = 0;
2773
2774         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2775         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2776 }
2777
2778 /* Init the TX queue in hardware */
2779 int
2780 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2781 {
2782         enum i40e_status_code err = I40E_SUCCESS;
2783         struct i40e_vsi *vsi = txq->vsi;
2784         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2785         uint16_t pf_q = txq->reg_idx;
2786         struct i40e_hmc_obj_txq tx_ctx;
2787         uint32_t qtx_ctl;
2788
2789         /* clear the context structure first */
2790         memset(&tx_ctx, 0, sizeof(tx_ctx));
2791         tx_ctx.new_context = 1;
2792         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2793         tx_ctx.qlen = txq->nb_tx_desc;
2794
2795 #ifdef RTE_LIBRTE_IEEE1588
2796         tx_ctx.timesync_ena = 1;
2797 #endif
2798         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2799         if (vsi->type == I40E_VSI_FDIR)
2800                 tx_ctx.fd_ena = TRUE;
2801
2802         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2803         if (err != I40E_SUCCESS) {
2804                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2805                 return err;
2806         }
2807
2808         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2809         if (err != I40E_SUCCESS) {
2810                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2811                 return err;
2812         }
2813
2814         /* Now associate this queue with this PCI function */
2815         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2816         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2817                                         I40E_QTX_CTL_PF_INDX_MASK);
2818         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2819         I40E_WRITE_FLUSH(hw);
2820
2821         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2822
2823         return err;
2824 }
2825
2826 int
2827 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2828 {
2829         struct i40e_rx_entry *rxe = rxq->sw_ring;
2830         uint64_t dma_addr;
2831         uint16_t i;
2832
2833         for (i = 0; i < rxq->nb_rx_desc; i++) {
2834                 volatile union i40e_rx_desc *rxd;
2835                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2836
2837                 if (unlikely(!mbuf)) {
2838                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2839                         return -ENOMEM;
2840                 }
2841
2842                 rte_mbuf_refcnt_set(mbuf, 1);
2843                 mbuf->next = NULL;
2844                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2845                 mbuf->nb_segs = 1;
2846                 mbuf->port = rxq->port_id;
2847
2848                 dma_addr =
2849                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2850
2851                 rxd = &rxq->rx_ring[i];
2852                 rxd->read.pkt_addr = dma_addr;
2853                 rxd->read.hdr_addr = 0;
2854 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2855                 rxd->read.rsvd1 = 0;
2856                 rxd->read.rsvd2 = 0;
2857 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2858
2859                 rxe[i].mbuf = mbuf;
2860         }
2861
2862         return 0;
2863 }
2864
2865 /*
2866  * Calculate the buffer length, and check the jumbo frame
2867  * and maximum packet length.
2868  */
2869 static int
2870 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2871 {
2872         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2873         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2874         struct rte_eth_dev_data *data = pf->dev_data;
2875         uint16_t buf_size;
2876
2877         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2878                 RTE_PKTMBUF_HEADROOM);
2879
2880         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2881                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2882         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2883                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2884                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2885                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2886                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2887                 rxq->hs_mode = i40e_header_split_enabled;
2888                 break;
2889         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2890         default:
2891                 rxq->rx_hdr_len = 0;
2892                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2893                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2894                 rxq->hs_mode = i40e_header_split_none;
2895                 break;
2896         }
2897
2898         rxq->max_pkt_len =
2899                 RTE_MIN(hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len,
2900                                 data->mtu + I40E_ETH_OVERHEAD);
2901         if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2902                 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2903                 PMD_DRV_LOG(ERR, "maximum packet length must be "
2904                             "larger than %u and smaller than %u",
2905                             (uint32_t)RTE_ETHER_MIN_LEN,
2906                             (uint32_t)I40E_FRAME_SIZE_MAX);
2907                 return I40E_ERR_CONFIG;
2908         }
2909
2910         return 0;
2911 }
2912
2913 /* Init the RX queue in hardware */
2914 int
2915 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2916 {
2917         int err = I40E_SUCCESS;
2918         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2919         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2920         uint16_t pf_q = rxq->reg_idx;
2921         uint16_t buf_size;
2922         struct i40e_hmc_obj_rxq rx_ctx;
2923
2924         err = i40e_rx_queue_config(rxq);
2925         if (err < 0) {
2926                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2927                 return err;
2928         }
2929
2930         /* Clear the context structure first */
2931         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2932         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2933         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2934
2935         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2936         rx_ctx.qlen = rxq->nb_rx_desc;
2937 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2938         rx_ctx.dsize = 1;
2939 #endif
2940         rx_ctx.dtype = rxq->hs_mode;
2941         if (rxq->hs_mode)
2942                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2943         else
2944                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2945         rx_ctx.rxmax = rxq->max_pkt_len;
2946         rx_ctx.tphrdesc_ena = 1;
2947         rx_ctx.tphwdesc_ena = 1;
2948         rx_ctx.tphdata_ena = 1;
2949         rx_ctx.tphhead_ena = 1;
2950         rx_ctx.lrxqthresh = 2;
2951         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2952         rx_ctx.l2tsel = 1;
2953         /* showiv indicates if inner VLAN is stripped inside of tunnel
2954          * packet. When set it to 1, vlan information is stripped from
2955          * the inner header, but the hardware does not put it in the
2956          * descriptor. So set it zero by default.
2957          */
2958         rx_ctx.showiv = 0;
2959         rx_ctx.prefena = 1;
2960
2961         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2962         if (err != I40E_SUCCESS) {
2963                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2964                 return err;
2965         }
2966         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2967         if (err != I40E_SUCCESS) {
2968                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2969                 return err;
2970         }
2971
2972         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2973
2974         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2975                 RTE_PKTMBUF_HEADROOM);
2976
2977         /* Check if scattered RX needs to be used. */
2978         if (rxq->max_pkt_len > buf_size)
2979                 dev_data->scattered_rx = 1;
2980
2981         /* Init the RX tail regieter. */
2982         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2983
2984         return 0;
2985 }
2986
2987 void
2988 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2989 {
2990         uint16_t i;
2991
2992         PMD_INIT_FUNC_TRACE();
2993
2994         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2995                 if (!dev->data->tx_queues[i])
2996                         continue;
2997                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2998                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2999         }
3000
3001         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3002                 if (!dev->data->rx_queues[i])
3003                         continue;
3004                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3005                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3006         }
3007 }
3008
3009 void
3010 i40e_dev_free_queues(struct rte_eth_dev *dev)
3011 {
3012         uint16_t i;
3013
3014         PMD_INIT_FUNC_TRACE();
3015
3016         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3017                 if (!dev->data->rx_queues[i])
3018                         continue;
3019                 i40e_rx_queue_release(dev->data->rx_queues[i]);
3020                 dev->data->rx_queues[i] = NULL;
3021         }
3022
3023         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3024                 if (!dev->data->tx_queues[i])
3025                         continue;
3026                 i40e_tx_queue_release(dev->data->tx_queues[i]);
3027                 dev->data->tx_queues[i] = NULL;
3028         }
3029 }
3030
3031 enum i40e_status_code
3032 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3033 {
3034         struct i40e_tx_queue *txq;
3035         const struct rte_memzone *tz = NULL;
3036         struct rte_eth_dev *dev;
3037         uint32_t ring_size;
3038
3039         if (!pf) {
3040                 PMD_DRV_LOG(ERR, "PF is not available");
3041                 return I40E_ERR_BAD_PTR;
3042         }
3043
3044         dev = &rte_eth_devices[pf->dev_data->port_id];
3045
3046         /* Allocate the TX queue data structure. */
3047         txq = rte_zmalloc_socket("i40e fdir tx queue",
3048                                   sizeof(struct i40e_tx_queue),
3049                                   RTE_CACHE_LINE_SIZE,
3050                                   SOCKET_ID_ANY);
3051         if (!txq) {
3052                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3053                                         "tx queue structure.");
3054                 return I40E_ERR_NO_MEMORY;
3055         }
3056
3057         /* Allocate TX hardware ring descriptors. */
3058         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3059         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3060
3061         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3062                                       I40E_FDIR_QUEUE_ID, ring_size,
3063                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3064         if (!tz) {
3065                 i40e_tx_queue_release(txq);
3066                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3067                 return I40E_ERR_NO_MEMORY;
3068         }
3069
3070         txq->mz = tz;
3071         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3072         txq->queue_id = I40E_FDIR_QUEUE_ID;
3073         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3074         txq->vsi = pf->fdir.fdir_vsi;
3075
3076         txq->tx_ring_phys_addr = tz->iova;
3077         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3078
3079         /*
3080          * don't need to allocate software ring and reset for the fdir
3081          * program queue just set the queue has been configured.
3082          */
3083         txq->q_set = TRUE;
3084         pf->fdir.txq = txq;
3085         pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3086
3087         return I40E_SUCCESS;
3088 }
3089
3090 enum i40e_status_code
3091 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3092 {
3093         struct i40e_rx_queue *rxq;
3094         const struct rte_memzone *rz = NULL;
3095         uint32_t ring_size;
3096         struct rte_eth_dev *dev;
3097
3098         if (!pf) {
3099                 PMD_DRV_LOG(ERR, "PF is not available");
3100                 return I40E_ERR_BAD_PTR;
3101         }
3102
3103         dev = &rte_eth_devices[pf->dev_data->port_id];
3104
3105         /* Allocate the RX queue data structure. */
3106         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3107                                   sizeof(struct i40e_rx_queue),
3108                                   RTE_CACHE_LINE_SIZE,
3109                                   SOCKET_ID_ANY);
3110         if (!rxq) {
3111                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3112                                         "rx queue structure.");
3113                 return I40E_ERR_NO_MEMORY;
3114         }
3115
3116         /* Allocate RX hardware ring descriptors. */
3117         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3118         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3119
3120         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3121                                       I40E_FDIR_QUEUE_ID, ring_size,
3122                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3123         if (!rz) {
3124                 i40e_rx_queue_release(rxq);
3125                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3126                 return I40E_ERR_NO_MEMORY;
3127         }
3128
3129         rxq->mz = rz;
3130         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3131         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3132         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3133         rxq->vsi = pf->fdir.fdir_vsi;
3134
3135         rxq->rx_ring_phys_addr = rz->iova;
3136         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3137         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3138
3139         /*
3140          * Don't need to allocate software ring and reset for the fdir
3141          * rx queue, just set the queue has been configured.
3142          */
3143         rxq->q_set = TRUE;
3144         pf->fdir.rxq = rxq;
3145
3146         return I40E_SUCCESS;
3147 }
3148
3149 void
3150 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3151         struct rte_eth_rxq_info *qinfo)
3152 {
3153         struct i40e_rx_queue *rxq;
3154
3155         rxq = dev->data->rx_queues[queue_id];
3156
3157         qinfo->mp = rxq->mp;
3158         qinfo->scattered_rx = dev->data->scattered_rx;
3159         qinfo->nb_desc = rxq->nb_rx_desc;
3160
3161         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3162         qinfo->conf.rx_drop_en = rxq->drop_en;
3163         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3164         qinfo->conf.offloads = rxq->offloads;
3165 }
3166
3167 void
3168 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3169         struct rte_eth_txq_info *qinfo)
3170 {
3171         struct i40e_tx_queue *txq;
3172
3173         txq = dev->data->tx_queues[queue_id];
3174
3175         qinfo->nb_desc = txq->nb_tx_desc;
3176
3177         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3178         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3179         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3180
3181         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3182         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3183         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3184         qinfo->conf.offloads = txq->offloads;
3185 }
3186
3187 #ifdef RTE_ARCH_X86
3188 static inline bool
3189 get_avx_supported(bool request_avx512)
3190 {
3191         if (request_avx512) {
3192                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3193                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3194                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3195 #ifdef CC_AVX512_SUPPORT
3196                         return true;
3197 #else
3198                 PMD_DRV_LOG(NOTICE,
3199                         "AVX512 is not supported in build env");
3200                 return false;
3201 #endif
3202         } else {
3203                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3204                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3205                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3206 #ifdef CC_AVX2_SUPPORT
3207                         return true;
3208 #else
3209                 PMD_DRV_LOG(NOTICE,
3210                         "AVX2 is not supported in build env");
3211                 return false;
3212 #endif
3213         }
3214
3215         return false;
3216 }
3217 #endif /* RTE_ARCH_X86 */
3218
3219
3220 void __rte_cold
3221 i40e_set_rx_function(struct rte_eth_dev *dev)
3222 {
3223         struct i40e_adapter *ad =
3224                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3225         uint16_t rx_using_sse, i;
3226         /* In order to allow Vector Rx there are a few configuration
3227          * conditions to be met and Rx Bulk Allocation should be allowed.
3228          */
3229         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3230 #ifdef RTE_ARCH_X86
3231                 ad->rx_use_avx512 = false;
3232                 ad->rx_use_avx2 = false;
3233 #endif
3234                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3235                     !ad->rx_bulk_alloc_allowed) {
3236                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3237                                      " Vector Rx preconditions",
3238                                      dev->data->port_id);
3239
3240                         ad->rx_vec_allowed = false;
3241                 }
3242                 if (ad->rx_vec_allowed) {
3243                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3244                                 struct i40e_rx_queue *rxq =
3245                                         dev->data->rx_queues[i];
3246
3247                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3248                                         ad->rx_vec_allowed = false;
3249                                         break;
3250                                 }
3251                         }
3252 #ifdef RTE_ARCH_X86
3253                         ad->rx_use_avx512 = get_avx_supported(1);
3254
3255                         if (!ad->rx_use_avx512)
3256                                 ad->rx_use_avx2 = get_avx_supported(0);
3257 #endif
3258                 }
3259         }
3260
3261         if (ad->rx_vec_allowed  &&
3262             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3263 #ifdef RTE_ARCH_X86
3264                 if (dev->data->scattered_rx) {
3265                         if (ad->rx_use_avx512) {
3266 #ifdef CC_AVX512_SUPPORT
3267                                 PMD_DRV_LOG(NOTICE,
3268                                         "Using AVX512 Vector Scattered Rx (port %d).",
3269                                         dev->data->port_id);
3270                                 dev->rx_pkt_burst =
3271                                         i40e_recv_scattered_pkts_vec_avx512;
3272 #endif
3273                         } else {
3274                                 PMD_INIT_LOG(DEBUG,
3275                                         "Using %sVector Scattered Rx (port %d).",
3276                                         ad->rx_use_avx2 ? "avx2 " : "",
3277                                         dev->data->port_id);
3278                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3279                                         i40e_recv_scattered_pkts_vec_avx2 :
3280                                         i40e_recv_scattered_pkts_vec;
3281                         }
3282                 } else {
3283                         if (ad->rx_use_avx512) {
3284 #ifdef CC_AVX512_SUPPORT
3285                                 PMD_DRV_LOG(NOTICE,
3286                                         "Using AVX512 Vector Rx (port %d).",
3287                                         dev->data->port_id);
3288                                 dev->rx_pkt_burst =
3289                                         i40e_recv_pkts_vec_avx512;
3290 #endif
3291                         } else {
3292                                 PMD_INIT_LOG(DEBUG,
3293                                         "Using %sVector Rx (port %d).",
3294                                         ad->rx_use_avx2 ? "avx2 " : "",
3295                                         dev->data->port_id);
3296                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3297                                         i40e_recv_pkts_vec_avx2 :
3298                                         i40e_recv_pkts_vec;
3299                         }
3300                 }
3301 #else /* RTE_ARCH_X86 */
3302                 if (dev->data->scattered_rx) {
3303                         PMD_INIT_LOG(DEBUG,
3304                                      "Using Vector Scattered Rx (port %d).",
3305                                      dev->data->port_id);
3306                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3307                 } else {
3308                         PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3309                                      dev->data->port_id);
3310                         dev->rx_pkt_burst = i40e_recv_pkts_vec;
3311                 }
3312 #endif /* RTE_ARCH_X86 */
3313         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3314                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3315                                     "satisfied. Rx Burst Bulk Alloc function "
3316                                     "will be used on port=%d.",
3317                              dev->data->port_id);
3318
3319                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3320         } else {
3321                 /* Simple Rx Path. */
3322                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3323                              dev->data->port_id);
3324                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3325                                         i40e_recv_scattered_pkts :
3326                                         i40e_recv_pkts;
3327         }
3328
3329         /* Propagate information about RX function choice through all queues. */
3330         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3331                 rx_using_sse =
3332                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3333                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3334 #ifdef CC_AVX512_SUPPORT
3335                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3336                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3337 #endif
3338                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3339                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3340
3341                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3342                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3343
3344                         if (rxq)
3345                                 rxq->rx_using_sse = rx_using_sse;
3346                 }
3347         }
3348 }
3349
3350 static const struct {
3351         eth_rx_burst_t pkt_burst;
3352         const char *info;
3353 } i40e_rx_burst_infos[] = {
3354         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3355         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3356         { i40e_recv_pkts,                    "Scalar" },
3357 #ifdef RTE_ARCH_X86
3358 #ifdef CC_AVX512_SUPPORT
3359         { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3360         { i40e_recv_pkts_vec_avx512,           "Vector AVX512" },
3361 #endif
3362         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3363         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3364         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3365         { i40e_recv_pkts_vec,                "Vector SSE" },
3366 #elif defined(RTE_ARCH_ARM64)
3367         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3368         { i40e_recv_pkts_vec,                "Vector Neon" },
3369 #elif defined(RTE_ARCH_PPC_64)
3370         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3371         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3372 #endif
3373 };
3374
3375 int
3376 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3377                        struct rte_eth_burst_mode *mode)
3378 {
3379         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3380         int ret = -EINVAL;
3381         unsigned int i;
3382
3383         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3384                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3385                         snprintf(mode->info, sizeof(mode->info), "%s",
3386                                  i40e_rx_burst_infos[i].info);
3387                         ret = 0;
3388                         break;
3389                 }
3390         }
3391
3392         return ret;
3393 }
3394
3395 void __rte_cold
3396 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3397 {
3398         struct i40e_adapter *ad =
3399                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3400
3401         /* Use a simple Tx queue if possible (only fast free is allowed) */
3402         ad->tx_simple_allowed =
3403                 (txq->offloads ==
3404                  (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3405                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3406         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3407                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3408
3409         if (ad->tx_vec_allowed)
3410                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3411                                 txq->queue_id);
3412         else if (ad->tx_simple_allowed)
3413                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3414                                 txq->queue_id);
3415         else
3416                 PMD_INIT_LOG(DEBUG,
3417                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3418                                 txq->queue_id);
3419 }
3420
3421 void __rte_cold
3422 i40e_set_tx_function(struct rte_eth_dev *dev)
3423 {
3424         struct i40e_adapter *ad =
3425                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3426         int i;
3427
3428         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3429 #ifdef RTE_ARCH_X86
3430                 ad->tx_use_avx2 = false;
3431                 ad->tx_use_avx512 = false;
3432 #endif
3433                 if (ad->tx_vec_allowed) {
3434                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3435                                 struct i40e_tx_queue *txq =
3436                                         dev->data->tx_queues[i];
3437
3438                                 if (txq && i40e_txq_vec_setup(txq)) {
3439                                         ad->tx_vec_allowed = false;
3440                                         break;
3441                                 }
3442                         }
3443 #ifdef RTE_ARCH_X86
3444                         ad->tx_use_avx512 = get_avx_supported(1);
3445
3446                         if (!ad->tx_use_avx512)
3447                                 ad->tx_use_avx2 = get_avx_supported(0);
3448 #endif
3449                 }
3450         }
3451
3452         if (ad->tx_simple_allowed) {
3453                 if (ad->tx_vec_allowed &&
3454                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3455 #ifdef RTE_ARCH_X86
3456                         if (ad->tx_use_avx512) {
3457 #ifdef CC_AVX512_SUPPORT
3458                                 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3459                                             dev->data->port_id);
3460                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3461 #endif
3462                         } else {
3463                                 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3464                                              ad->tx_use_avx2 ? "avx2 " : "",
3465                                              dev->data->port_id);
3466                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3467                                                     i40e_xmit_pkts_vec_avx2 :
3468                                                     i40e_xmit_pkts_vec;
3469                         }
3470 #else /* RTE_ARCH_X86 */
3471                         PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3472                                      dev->data->port_id);
3473                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3474 #endif /* RTE_ARCH_X86 */
3475                 } else {
3476                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3477                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3478                 }
3479                 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3480         } else {
3481                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3482                 dev->tx_pkt_burst = i40e_xmit_pkts;
3483                 dev->tx_pkt_prepare = i40e_prep_pkts;
3484         }
3485 }
3486
3487 static const struct {
3488         eth_tx_burst_t pkt_burst;
3489         const char *info;
3490 } i40e_tx_burst_infos[] = {
3491         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3492         { i40e_xmit_pkts,          "Scalar" },
3493 #ifdef RTE_ARCH_X86
3494 #ifdef CC_AVX512_SUPPORT
3495         { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3496 #endif
3497         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3498         { i40e_xmit_pkts_vec,      "Vector SSE" },
3499 #elif defined(RTE_ARCH_ARM64)
3500         { i40e_xmit_pkts_vec,      "Vector Neon" },
3501 #elif defined(RTE_ARCH_PPC_64)
3502         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3503 #endif
3504 };
3505
3506 int
3507 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3508                        struct rte_eth_burst_mode *mode)
3509 {
3510         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3511         int ret = -EINVAL;
3512         unsigned int i;
3513
3514         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3515                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3516                         snprintf(mode->info, sizeof(mode->info), "%s",
3517                                  i40e_tx_burst_infos[i].info);
3518                         ret = 0;
3519                         break;
3520                 }
3521         }
3522
3523         return ret;
3524 }
3525
3526 void __rte_cold
3527 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3528 {
3529         struct i40e_adapter *ad =
3530                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3531         int i;
3532
3533         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3534                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3535 }
3536
3537 void __rte_cold
3538 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3539 {
3540         struct i40e_adapter *ad =
3541                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3542         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543         int i;
3544
3545         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3546                 ad->pctypes_tbl[i] = 0ULL;
3547         ad->flow_types_mask = 0ULL;
3548         ad->pctypes_mask = 0ULL;
3549
3550         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3551                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3552         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3553                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3554         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3555                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3556         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3557                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3558         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3559                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3560         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3561                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3562         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3563                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3564         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3565                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3566         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3567                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3568         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3569                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3570         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3571                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3572
3573         if (hw->mac.type == I40E_MAC_X722 ||
3574                 hw->mac.type == I40E_MAC_X722_VF) {
3575                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3576                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3577                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3578                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3579                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3580                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3581                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3582                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3583                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3584                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3585                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3586                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3587         }
3588
3589         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3590                 if (ad->pctypes_tbl[i])
3591                         ad->flow_types_mask |= (1ULL << i);
3592                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3593         }
3594 }
3595
3596 #ifndef CC_AVX2_SUPPORT
3597 uint16_t
3598 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3599                         struct rte_mbuf __rte_unused **rx_pkts,
3600                         uint16_t __rte_unused nb_pkts)
3601 {
3602         return 0;
3603 }
3604
3605 uint16_t
3606 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3607                         struct rte_mbuf __rte_unused **rx_pkts,
3608                         uint16_t __rte_unused nb_pkts)
3609 {
3610         return 0;
3611 }
3612
3613 uint16_t
3614 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3615                           struct rte_mbuf __rte_unused **tx_pkts,
3616                           uint16_t __rte_unused nb_pkts)
3617 {
3618         return 0;
3619 }
3620 #endif /* ifndef CC_AVX2_SUPPORT */