4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_TX_MAX_BURST 32
69 #define I40E_DMA_MEM_ALIGN 4096
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
79 PKT_TX_OUTER_IP_CKSUM)
81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
82 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
85 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
87 static const struct rte_memzone *
88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
89 const char *ring_name,
93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
94 struct rte_mbuf **tx_pkts,
98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
100 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
101 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
102 mb->ol_flags |= PKT_RX_VLAN_PKT;
104 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
105 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
106 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
111 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
112 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
113 mb->ol_flags |= PKT_RX_QINQ_PKT;
114 mb->vlan_tci_outer = mb->vlan_tci;
115 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
116 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
117 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
118 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
120 mb->vlan_tci_outer = 0;
123 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
124 mb->vlan_tci, mb->vlan_tci_outer);
127 /* Translate the rx descriptor status to pkt flags */
128 static inline uint64_t
129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
133 /* Check if RSS_HASH */
134 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
135 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
136 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
138 /* Check if FDIR Match */
139 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
145 static inline uint64_t
146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
149 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
151 #define I40E_RX_ERR_BITS 0x3f
152 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
154 /* If RXE bit set, all other status bits are meaningless */
155 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
156 flags |= PKT_RX_MAC_ERR;
160 /* If RECIPE bit set, all other status indications should be ignored */
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
162 flags |= PKT_RX_RECIP_ERR;
165 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
166 flags |= PKT_RX_HBUF_OVERFLOW;
167 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
168 flags |= PKT_RX_IP_CKSUM_BAD;
169 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
170 flags |= PKT_RX_L4_CKSUM_BAD;
171 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
172 flags |= PKT_RX_EIP_CKSUM_BAD;
173 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
174 flags |= PKT_RX_OVERSIZE;
179 /* Translate pkt types to pkt flags */
180 static inline uint64_t
181 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
183 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
184 I40E_RXD_QW1_PTYPE_SHIFT);
185 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
188 PKT_RX_IEEE1588_PTP, /* PTYPE 2 */
208 PKT_RX_IPV4_HDR, /* PTYPE 22 */
209 PKT_RX_IPV4_HDR, /* PTYPE 23 */
210 PKT_RX_IPV4_HDR, /* PTYPE 24 */
212 PKT_RX_IPV4_HDR, /* PTYPE 26 */
213 PKT_RX_IPV4_HDR, /* PTYPE 27 */
214 PKT_RX_IPV4_HDR, /* PTYPE 28 */
215 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
220 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
221 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
222 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
223 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
224 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
226 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
227 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
228 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
229 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
230 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
231 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
232 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
234 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
235 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
236 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
237 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
238 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
239 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
241 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
242 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
243 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
244 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
245 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
246 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
247 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
249 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
250 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
251 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
252 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
253 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
254 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
256 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
257 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
258 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
259 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
260 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
261 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
262 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
264 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
265 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
266 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
267 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
268 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
269 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
271 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
272 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
273 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
274 PKT_RX_IPV6_HDR, /* PTYPE 88 */
275 PKT_RX_IPV6_HDR, /* PTYPE 89 */
276 PKT_RX_IPV6_HDR, /* PTYPE 90 */
278 PKT_RX_IPV6_HDR, /* PTYPE 92 */
279 PKT_RX_IPV6_HDR, /* PTYPE 93 */
280 PKT_RX_IPV6_HDR, /* PTYPE 94 */
281 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
286 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
287 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
288 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
289 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
290 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
292 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
293 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
294 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
295 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
296 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
297 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
298 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
300 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
301 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
302 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
303 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
304 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
305 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
307 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
308 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
309 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
310 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
311 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
312 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
313 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
315 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
316 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
317 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
318 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
319 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
320 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
322 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
323 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
324 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
325 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
326 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
327 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
328 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
330 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
331 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
332 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
333 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
334 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
335 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
337 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
338 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
339 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
444 return ip_ptype_map[ptype];
447 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
448 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
449 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
450 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
451 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
453 static inline uint64_t
454 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
457 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
458 uint16_t flexbh, flexbl;
460 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
461 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
462 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
463 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
464 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
465 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
468 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
470 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
471 flags |= PKT_RX_FDIR_ID;
472 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
474 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
475 flags |= PKT_RX_FDIR_FLX;
477 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
479 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
480 flags |= PKT_RX_FDIR_FLX;
484 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
485 flags |= PKT_RX_FDIR_ID;
490 i40e_txd_enable_checksum(uint64_t ol_flags,
493 union i40e_tx_offload tx_offload,
494 uint32_t *cd_tunneling)
496 /* UDP tunneling packet TX checksum offload */
497 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
499 *td_offset |= (tx_offload.outer_l2_len >> 1)
500 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
502 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
503 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
504 else if (ol_flags & PKT_TX_OUTER_IPV4)
505 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
506 else if (ol_flags & PKT_TX_OUTER_IPV6)
507 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
509 /* Now set the ctx descriptor fields */
510 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
511 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
512 (tx_offload.l2_len >> 1) <<
513 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
516 *td_offset |= (tx_offload.l2_len >> 1)
517 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
519 /* Enable L3 checksum offloads */
520 if (ol_flags & PKT_TX_IP_CKSUM) {
521 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
522 *td_offset |= (tx_offload.l3_len >> 2)
523 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
524 } else if (ol_flags & PKT_TX_IPV4) {
525 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
526 *td_offset |= (tx_offload.l3_len >> 2)
527 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
528 } else if (ol_flags & PKT_TX_IPV6) {
529 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
530 *td_offset |= (tx_offload.l3_len >> 2)
531 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
534 if (ol_flags & PKT_TX_TCP_SEG) {
535 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
536 *td_offset |= (tx_offload.l4_len >> 2)
537 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
541 /* Enable L4 checksum offloads */
542 switch (ol_flags & PKT_TX_L4_MASK) {
543 case PKT_TX_TCP_CKSUM:
544 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
545 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
546 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
548 case PKT_TX_SCTP_CKSUM:
549 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
550 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
551 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
553 case PKT_TX_UDP_CKSUM:
554 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
555 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
556 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
563 static inline struct rte_mbuf *
564 rte_rxmbuf_alloc(struct rte_mempool *mp)
568 m = __rte_mbuf_raw_alloc(mp);
569 __rte_mbuf_sanity_check_raw(m, 0);
574 /* Construct the tx flags */
575 static inline uint64_t
576 i40e_build_ctob(uint32_t td_cmd,
581 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
582 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
583 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
584 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
585 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
589 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
591 struct i40e_tx_entry *sw_ring = txq->sw_ring;
592 volatile struct i40e_tx_desc *txd = txq->tx_ring;
593 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
594 uint16_t nb_tx_desc = txq->nb_tx_desc;
595 uint16_t desc_to_clean_to;
596 uint16_t nb_tx_to_clean;
598 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
599 if (desc_to_clean_to >= nb_tx_desc)
600 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
602 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
603 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
604 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
605 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
606 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
607 "(port=%d queue=%d)", desc_to_clean_to,
608 txq->port_id, txq->queue_id);
612 if (last_desc_cleaned > desc_to_clean_to)
613 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
616 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
619 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
621 txq->last_desc_cleaned = desc_to_clean_to;
622 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
628 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
629 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
631 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
636 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
637 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
638 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
639 "rxq->rx_free_thresh=%d, "
640 "RTE_PMD_I40E_RX_MAX_BURST=%d",
641 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
643 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
644 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
645 "rxq->rx_free_thresh=%d, "
646 "rxq->nb_rx_desc=%d",
647 rxq->rx_free_thresh, rxq->nb_rx_desc);
649 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
650 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
651 "rxq->nb_rx_desc=%d, "
652 "rxq->rx_free_thresh=%d",
653 rxq->nb_rx_desc, rxq->rx_free_thresh);
655 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
656 RTE_PMD_I40E_RX_MAX_BURST))) {
657 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
658 "rxq->nb_rx_desc=%d, "
659 "I40E_MAX_RING_DESC=%d, "
660 "RTE_PMD_I40E_RX_MAX_BURST=%d",
661 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
662 RTE_PMD_I40E_RX_MAX_BURST);
672 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
673 #define I40E_LOOK_AHEAD 8
674 #if (I40E_LOOK_AHEAD != 8)
675 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
678 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
680 volatile union i40e_rx_desc *rxdp;
681 struct i40e_rx_entry *rxep;
686 int32_t s[I40E_LOOK_AHEAD], nb_dd;
687 int32_t i, j, nb_rx = 0;
690 rxdp = &rxq->rx_ring[rxq->rx_tail];
691 rxep = &rxq->sw_ring[rxq->rx_tail];
693 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
694 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
695 I40E_RXD_QW1_STATUS_SHIFT;
697 /* Make sure there is at least 1 packet to receive */
698 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
702 * Scan LOOK_AHEAD descriptors at a time to determine which
703 * descriptors reference packets that are ready to be received.
705 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
706 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
707 /* Read desc statuses backwards to avoid race condition */
708 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
709 qword1 = rte_le_to_cpu_64(\
710 rxdp[j].wb.qword1.status_error_len);
711 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
712 I40E_RXD_QW1_STATUS_SHIFT;
715 /* Compute how many status bits were set */
716 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
717 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
721 /* Translate descriptor info to mbuf parameters */
722 for (j = 0; j < nb_dd; j++) {
724 qword1 = rte_le_to_cpu_64(\
725 rxdp[j].wb.qword1.status_error_len);
726 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
727 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
728 mb->data_len = pkt_len;
729 mb->pkt_len = pkt_len;
731 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
732 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
733 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
734 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
736 mb->packet_type = (uint16_t)((qword1 &
737 I40E_RXD_QW1_PTYPE_MASK) >>
738 I40E_RXD_QW1_PTYPE_SHIFT);
739 if (pkt_flags & PKT_RX_RSS_HASH)
740 mb->hash.rss = rte_le_to_cpu_32(\
741 rxdp[j].wb.qword0.hi_dword.rss);
742 if (pkt_flags & PKT_RX_FDIR)
743 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
745 #ifdef RTE_LIBRTE_IEEE1588
746 uint16_t tsyn = (qword1
747 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
748 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
749 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
752 pkt_flags |= PKT_RX_IEEE1588_TMST;
754 mb->timesync = tsyn & 0x03;
756 mb->ol_flags |= pkt_flags;
760 for (j = 0; j < I40E_LOOK_AHEAD; j++)
761 rxq->rx_stage[i + j] = rxep[j].mbuf;
763 if (nb_dd != I40E_LOOK_AHEAD)
767 /* Clear software ring entries */
768 for (i = 0; i < nb_rx; i++)
769 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
774 static inline uint16_t
775 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
776 struct rte_mbuf **rx_pkts,
780 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
782 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
784 for (i = 0; i < nb_pkts; i++)
785 rx_pkts[i] = stage[i];
787 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
788 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
794 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
796 volatile union i40e_rx_desc *rxdp;
797 struct i40e_rx_entry *rxep;
799 uint16_t alloc_idx, i;
803 /* Allocate buffers in bulk */
804 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
805 (rxq->rx_free_thresh - 1));
806 rxep = &(rxq->sw_ring[alloc_idx]);
807 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
808 rxq->rx_free_thresh);
809 if (unlikely(diag != 0)) {
810 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
814 rxdp = &rxq->rx_ring[alloc_idx];
815 for (i = 0; i < rxq->rx_free_thresh; i++) {
817 rte_mbuf_refcnt_set(mb, 1);
819 mb->data_off = RTE_PKTMBUF_HEADROOM;
821 mb->port = rxq->port_id;
822 dma_addr = rte_cpu_to_le_64(\
823 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
824 rxdp[i].read.hdr_addr = dma_addr;
825 rxdp[i].read.pkt_addr = dma_addr;
828 /* Update rx tail regsiter */
830 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
832 rxq->rx_free_trigger =
833 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
834 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
835 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
840 static inline uint16_t
841 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
843 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
849 if (rxq->rx_nb_avail)
850 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
852 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
853 rxq->rx_next_avail = 0;
854 rxq->rx_nb_avail = nb_rx;
855 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
857 if (rxq->rx_tail > rxq->rx_free_trigger) {
858 if (i40e_rx_alloc_bufs(rxq) != 0) {
861 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
862 "port_id=%u, queue_id=%u",
863 rxq->port_id, rxq->queue_id);
864 rxq->rx_nb_avail = 0;
865 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
866 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
867 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
873 if (rxq->rx_tail >= rxq->nb_rx_desc)
876 if (rxq->rx_nb_avail)
877 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
883 i40e_recv_pkts_bulk_alloc(void *rx_queue,
884 struct rte_mbuf **rx_pkts,
887 uint16_t nb_rx = 0, n, count;
889 if (unlikely(nb_pkts == 0))
892 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
893 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
896 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
897 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
898 nb_rx = (uint16_t)(nb_rx + count);
899 nb_pkts = (uint16_t)(nb_pkts - count);
906 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
909 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
911 struct i40e_rx_queue *rxq;
912 volatile union i40e_rx_desc *rx_ring;
913 volatile union i40e_rx_desc *rxdp;
914 union i40e_rx_desc rxd;
915 struct i40e_rx_entry *sw_ring;
916 struct i40e_rx_entry *rxe;
917 struct rte_mbuf *rxm;
918 struct rte_mbuf *nmb;
922 uint16_t rx_packet_len;
923 uint16_t rx_id, nb_hold;
930 rx_id = rxq->rx_tail;
931 rx_ring = rxq->rx_ring;
932 sw_ring = rxq->sw_ring;
934 while (nb_rx < nb_pkts) {
935 rxdp = &rx_ring[rx_id];
936 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
937 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
938 >> I40E_RXD_QW1_STATUS_SHIFT;
940 /* Check the DD bit first */
941 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
944 nmb = rte_rxmbuf_alloc(rxq->mp);
950 rxe = &sw_ring[rx_id];
952 if (unlikely(rx_id == rxq->nb_rx_desc))
955 /* Prefetch next mbuf */
956 rte_prefetch0(sw_ring[rx_id].mbuf);
959 * When next RX descriptor is on a cache line boundary,
960 * prefetch the next 4 RX descriptors and next 8 pointers
963 if ((rx_id & 0x3) == 0) {
964 rte_prefetch0(&rx_ring[rx_id]);
965 rte_prefetch0(&sw_ring[rx_id]);
970 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
971 rxdp->read.hdr_addr = dma_addr;
972 rxdp->read.pkt_addr = dma_addr;
974 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
975 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
977 rxm->data_off = RTE_PKTMBUF_HEADROOM;
978 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
981 rxm->pkt_len = rx_packet_len;
982 rxm->data_len = rx_packet_len;
983 rxm->port = rxq->port_id;
985 i40e_rxd_to_vlan_tci(rxm, &rxd);
986 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
987 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
988 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
989 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
990 I40E_RXD_QW1_PTYPE_SHIFT);
991 if (pkt_flags & PKT_RX_RSS_HASH)
993 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
994 if (pkt_flags & PKT_RX_FDIR)
995 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
997 #ifdef RTE_LIBRTE_IEEE1588
998 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
999 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1000 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1003 pkt_flags |= PKT_RX_IEEE1588_TMST;
1005 rxm->timesync = tsyn & 0x03;
1007 rxm->ol_flags |= pkt_flags;
1009 rx_pkts[nb_rx++] = rxm;
1011 rxq->rx_tail = rx_id;
1014 * If the number of free RX descriptors is greater than the RX free
1015 * threshold of the queue, advance the receive tail register of queue.
1016 * Update that register with the value of the last processed RX
1017 * descriptor minus 1.
1019 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1020 if (nb_hold > rxq->rx_free_thresh) {
1021 rx_id = (uint16_t) ((rx_id == 0) ?
1022 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1023 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1026 rxq->nb_rx_hold = nb_hold;
1032 i40e_recv_scattered_pkts(void *rx_queue,
1033 struct rte_mbuf **rx_pkts,
1036 struct i40e_rx_queue *rxq = rx_queue;
1037 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1038 volatile union i40e_rx_desc *rxdp;
1039 union i40e_rx_desc rxd;
1040 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1041 struct i40e_rx_entry *rxe;
1042 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1043 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1044 struct rte_mbuf *nmb, *rxm;
1045 uint16_t rx_id = rxq->rx_tail;
1046 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1052 while (nb_rx < nb_pkts) {
1053 rxdp = &rx_ring[rx_id];
1054 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1055 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1056 I40E_RXD_QW1_STATUS_SHIFT;
1058 /* Check the DD bit */
1059 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1062 nmb = rte_rxmbuf_alloc(rxq->mp);
1067 rxe = &sw_ring[rx_id];
1069 if (rx_id == rxq->nb_rx_desc)
1072 /* Prefetch next mbuf */
1073 rte_prefetch0(sw_ring[rx_id].mbuf);
1076 * When next RX descriptor is on a cache line boundary,
1077 * prefetch the next 4 RX descriptors and next 8 pointers
1080 if ((rx_id & 0x3) == 0) {
1081 rte_prefetch0(&rx_ring[rx_id]);
1082 rte_prefetch0(&sw_ring[rx_id]);
1088 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1090 /* Set data buffer address and data length of the mbuf */
1091 rxdp->read.hdr_addr = dma_addr;
1092 rxdp->read.pkt_addr = dma_addr;
1093 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1094 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1095 rxm->data_len = rx_packet_len;
1096 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1099 * If this is the first buffer of the received packet, set the
1100 * pointer to the first mbuf of the packet and initialize its
1101 * context. Otherwise, update the total length and the number
1102 * of segments of the current scattered packet, and update the
1103 * pointer to the last mbuf of the current packet.
1107 first_seg->nb_segs = 1;
1108 first_seg->pkt_len = rx_packet_len;
1110 first_seg->pkt_len =
1111 (uint16_t)(first_seg->pkt_len +
1113 first_seg->nb_segs++;
1114 last_seg->next = rxm;
1118 * If this is not the last buffer of the received packet,
1119 * update the pointer to the last mbuf of the current scattered
1120 * packet and continue to parse the RX ring.
1122 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1128 * This is the last buffer of the received packet. If the CRC
1129 * is not stripped by the hardware:
1130 * - Subtract the CRC length from the total packet length.
1131 * - If the last buffer only contains the whole CRC or a part
1132 * of it, free the mbuf associated to the last buffer. If part
1133 * of the CRC is also contained in the previous mbuf, subtract
1134 * the length of that CRC part from the data length of the
1138 if (unlikely(rxq->crc_len > 0)) {
1139 first_seg->pkt_len -= ETHER_CRC_LEN;
1140 if (rx_packet_len <= ETHER_CRC_LEN) {
1141 rte_pktmbuf_free_seg(rxm);
1142 first_seg->nb_segs--;
1143 last_seg->data_len =
1144 (uint16_t)(last_seg->data_len -
1145 (ETHER_CRC_LEN - rx_packet_len));
1146 last_seg->next = NULL;
1148 rxm->data_len = (uint16_t)(rx_packet_len -
1152 first_seg->port = rxq->port_id;
1153 first_seg->ol_flags = 0;
1154 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1155 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1156 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1157 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1158 first_seg->packet_type = (uint16_t)((qword1 &
1159 I40E_RXD_QW1_PTYPE_MASK) >>
1160 I40E_RXD_QW1_PTYPE_SHIFT);
1161 if (pkt_flags & PKT_RX_RSS_HASH)
1163 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1164 if (pkt_flags & PKT_RX_FDIR)
1165 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1167 #ifdef RTE_LIBRTE_IEEE1588
1168 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1169 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1170 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1173 pkt_flags |= PKT_RX_IEEE1588_TMST;
1175 first_seg->timesync = tsyn & 0x03;
1177 first_seg->ol_flags |= pkt_flags;
1179 /* Prefetch data of first segment, if configured to do so. */
1180 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1181 first_seg->data_off));
1182 rx_pkts[nb_rx++] = first_seg;
1186 /* Record index of the next RX descriptor to probe. */
1187 rxq->rx_tail = rx_id;
1188 rxq->pkt_first_seg = first_seg;
1189 rxq->pkt_last_seg = last_seg;
1192 * If the number of free RX descriptors is greater than the RX free
1193 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1194 * register. Update the RDT with the value of the last processed RX
1195 * descriptor minus 1, to guarantee that the RDT register is never
1196 * equal to the RDH register, which creates a "full" ring situtation
1197 * from the hardware point of view.
1199 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1200 if (nb_hold > rxq->rx_free_thresh) {
1201 rx_id = (uint16_t)(rx_id == 0 ?
1202 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1203 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1206 rxq->nb_rx_hold = nb_hold;
1211 /* Check if the context descriptor is needed for TX offloading */
1212 static inline uint16_t
1213 i40e_calc_context_desc(uint64_t flags)
1215 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1219 #ifdef RTE_LIBRTE_IEEE1588
1220 mask |= PKT_TX_IEEE1588_TMST;
1223 return ((flags & mask) ? 1 : 0);
1226 /* set i40e TSO context descriptor */
1227 static inline uint64_t
1228 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1230 uint64_t ctx_desc = 0;
1231 uint32_t cd_cmd, hdr_len, cd_tso_len;
1233 if (!tx_offload.l4_len) {
1234 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1239 * in case of tunneling packet, the outer_l2_len and
1240 * outer_l3_len must be 0.
1242 hdr_len = tx_offload.outer_l2_len +
1243 tx_offload.outer_l3_len +
1248 cd_cmd = I40E_TX_CTX_DESC_TSO;
1249 cd_tso_len = mbuf->pkt_len - hdr_len;
1250 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1251 ((uint64_t)cd_tso_len <<
1252 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1253 ((uint64_t)mbuf->tso_segsz <<
1254 I40E_TXD_CTX_QW1_MSS_SHIFT);
1260 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1262 struct i40e_tx_queue *txq;
1263 struct i40e_tx_entry *sw_ring;
1264 struct i40e_tx_entry *txe, *txn;
1265 volatile struct i40e_tx_desc *txd;
1266 volatile struct i40e_tx_desc *txr;
1267 struct rte_mbuf *tx_pkt;
1268 struct rte_mbuf *m_seg;
1269 uint32_t cd_tunneling_params;
1281 uint64_t buf_dma_addr;
1282 union i40e_tx_offload tx_offload = {0};
1285 sw_ring = txq->sw_ring;
1287 tx_id = txq->tx_tail;
1288 txe = &sw_ring[tx_id];
1290 /* Check if the descriptor ring needs to be cleaned. */
1291 if (txq->nb_tx_free < txq->tx_free_thresh)
1292 i40e_xmit_cleanup(txq);
1294 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1300 tx_pkt = *tx_pkts++;
1301 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1303 ol_flags = tx_pkt->ol_flags;
1304 tx_offload.l2_len = tx_pkt->l2_len;
1305 tx_offload.l3_len = tx_pkt->l3_len;
1306 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1307 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1308 tx_offload.l4_len = tx_pkt->l4_len;
1309 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1311 /* Calculate the number of context descriptors needed. */
1312 nb_ctx = i40e_calc_context_desc(ol_flags);
1315 * The number of descriptors that must be allocated for
1316 * a packet equals to the number of the segments of that
1317 * packet plus 1 context descriptor if needed.
1319 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1320 tx_last = (uint16_t)(tx_id + nb_used - 1);
1323 if (tx_last >= txq->nb_tx_desc)
1324 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1326 if (nb_used > txq->nb_tx_free) {
1327 if (i40e_xmit_cleanup(txq) != 0) {
1332 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1333 while (nb_used > txq->nb_tx_free) {
1334 if (i40e_xmit_cleanup(txq) != 0) {
1343 /* Descriptor based VLAN insertion */
1344 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1345 tx_flags |= tx_pkt->vlan_tci <<
1346 I40E_TX_FLAG_L2TAG1_SHIFT;
1347 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1348 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1349 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1350 I40E_TX_FLAG_L2TAG1_SHIFT;
1353 /* Always enable CRC offload insertion */
1354 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1356 /* Enable checksum offloading */
1357 cd_tunneling_params = 0;
1358 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1359 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1360 tx_offload, &cd_tunneling_params);
1363 if (unlikely(nb_ctx)) {
1364 /* Setup TX context descriptor if required */
1365 volatile struct i40e_tx_context_desc *ctx_txd =
1366 (volatile struct i40e_tx_context_desc *)\
1368 uint16_t cd_l2tag2 = 0;
1369 uint64_t cd_type_cmd_tso_mss =
1370 I40E_TX_DESC_DTYPE_CONTEXT;
1372 txn = &sw_ring[txe->next_id];
1373 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1374 if (txe->mbuf != NULL) {
1375 rte_pktmbuf_free_seg(txe->mbuf);
1379 /* TSO enabled means no timestamp */
1380 if (ol_flags & PKT_TX_TCP_SEG)
1381 cd_type_cmd_tso_mss |=
1382 i40e_set_tso_ctx(tx_pkt, tx_offload);
1384 #ifdef RTE_LIBRTE_IEEE1588
1385 if (ol_flags & PKT_TX_IEEE1588_TMST)
1386 cd_type_cmd_tso_mss |=
1387 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1388 I40E_TXD_CTX_QW1_CMD_SHIFT);
1392 ctx_txd->tunneling_params =
1393 rte_cpu_to_le_32(cd_tunneling_params);
1394 if (ol_flags & PKT_TX_QINQ_PKT) {
1395 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1396 cd_type_cmd_tso_mss |=
1397 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1398 I40E_TXD_CTX_QW1_CMD_SHIFT);
1400 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1401 ctx_txd->type_cmd_tso_mss =
1402 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1404 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1405 "tunneling_params: %#x;\n"
1408 "type_cmd_tso_mss: %#"PRIx64";\n",
1410 ctx_txd->tunneling_params,
1413 ctx_txd->type_cmd_tso_mss);
1415 txe->last_id = tx_last;
1416 tx_id = txe->next_id;
1423 txn = &sw_ring[txe->next_id];
1426 rte_pktmbuf_free_seg(txe->mbuf);
1429 /* Setup TX Descriptor */
1430 slen = m_seg->data_len;
1431 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1433 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1434 "buf_dma_addr: %#"PRIx64";\n"
1439 tx_pkt, tx_id, buf_dma_addr,
1440 td_cmd, td_offset, slen, td_tag);
1442 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1443 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1444 td_offset, slen, td_tag);
1445 txe->last_id = tx_last;
1446 tx_id = txe->next_id;
1448 m_seg = m_seg->next;
1449 } while (m_seg != NULL);
1451 /* The last packet data descriptor needs End Of Packet (EOP) */
1452 td_cmd |= I40E_TX_DESC_CMD_EOP;
1453 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1454 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1456 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1457 PMD_TX_FREE_LOG(DEBUG,
1458 "Setting RS bit on TXD id="
1459 "%4u (port=%d queue=%d)",
1460 tx_last, txq->port_id, txq->queue_id);
1462 td_cmd |= I40E_TX_DESC_CMD_RS;
1464 /* Update txq RS bit counters */
1465 txq->nb_tx_used = 0;
1468 txd->cmd_type_offset_bsz |=
1469 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1470 I40E_TXD_QW1_CMD_SHIFT);
1476 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1477 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1478 (unsigned) tx_id, (unsigned) nb_tx);
1480 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1481 txq->tx_tail = tx_id;
1486 static inline int __attribute__((always_inline))
1487 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1489 struct i40e_tx_entry *txep;
1492 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1493 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1494 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1497 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1499 for (i = 0; i < txq->tx_rs_thresh; i++)
1500 rte_prefetch0((txep + i)->mbuf);
1502 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1503 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1504 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1508 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1509 rte_pktmbuf_free_seg(txep->mbuf);
1514 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1515 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1516 if (txq->tx_next_dd >= txq->nb_tx_desc)
1517 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1519 return txq->tx_rs_thresh;
1522 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1523 I40E_TX_DESC_CMD_EOP)
1525 /* Populate 4 descriptors with data from 4 mbufs */
1527 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1532 for (i = 0; i < 4; i++, txdp++, pkts++) {
1533 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1534 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1535 txdp->cmd_type_offset_bsz =
1536 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1537 (*pkts)->data_len, 0);
1541 /* Populate 1 descriptor with data from 1 mbuf */
1543 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1547 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1548 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1549 txdp->cmd_type_offset_bsz =
1550 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1551 (*pkts)->data_len, 0);
1554 /* Fill hardware descriptor ring with mbuf data */
1556 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1557 struct rte_mbuf **pkts,
1560 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1561 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1562 const int N_PER_LOOP = 4;
1563 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1564 int mainpart, leftover;
1567 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1568 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1569 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1570 for (j = 0; j < N_PER_LOOP; ++j) {
1571 (txep + i + j)->mbuf = *(pkts + i + j);
1573 tx4(txdp + i, pkts + i);
1575 if (unlikely(leftover > 0)) {
1576 for (i = 0; i < leftover; ++i) {
1577 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1578 tx1(txdp + mainpart + i, pkts + mainpart + i);
1583 static inline uint16_t
1584 tx_xmit_pkts(struct i40e_tx_queue *txq,
1585 struct rte_mbuf **tx_pkts,
1588 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1592 * Begin scanning the H/W ring for done descriptors when the number
1593 * of available descriptors drops below tx_free_thresh. For each done
1594 * descriptor, free the associated buffer.
1596 if (txq->nb_tx_free < txq->tx_free_thresh)
1597 i40e_tx_free_bufs(txq);
1599 /* Use available descriptor only */
1600 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1601 if (unlikely(!nb_pkts))
1604 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1605 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1606 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1607 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1608 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1609 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1610 I40E_TXD_QW1_CMD_SHIFT);
1611 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1615 /* Fill hardware descriptor ring with mbuf data */
1616 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1617 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1619 /* Determin if RS bit needs to be set */
1620 if (txq->tx_tail > txq->tx_next_rs) {
1621 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1622 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1623 I40E_TXD_QW1_CMD_SHIFT);
1625 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1626 if (txq->tx_next_rs >= txq->nb_tx_desc)
1627 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1630 if (txq->tx_tail >= txq->nb_tx_desc)
1633 /* Update the tx tail register */
1635 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1641 i40e_xmit_pkts_simple(void *tx_queue,
1642 struct rte_mbuf **tx_pkts,
1647 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1648 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1652 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1655 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1656 &tx_pkts[nb_tx], num);
1657 nb_tx = (uint16_t)(nb_tx + ret);
1658 nb_pkts = (uint16_t)(nb_pkts - ret);
1667 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1668 * application used, which assume having sequential ones. But from driver's
1669 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1670 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1671 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1672 * use queue_idx from 0 to 95 to access queues, while real queue would be
1673 * different. This function will do a queue mapping to find VSI the queue
1676 static struct i40e_vsi*
1677 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1679 /* the queue in MAIN VSI range */
1680 if (queue_idx < pf->main_vsi->nb_qps)
1681 return pf->main_vsi;
1683 queue_idx -= pf->main_vsi->nb_qps;
1685 /* queue_idx is greater than VMDQ VSIs range */
1686 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1687 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1691 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1695 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1697 /* the queue in MAIN VSI range */
1698 if (queue_idx < pf->main_vsi->nb_qps)
1701 /* It's VMDQ queues */
1702 queue_idx -= pf->main_vsi->nb_qps;
1704 if (pf->nb_cfg_vmdq_vsi)
1705 return queue_idx % pf->vmdq_nb_qps;
1707 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1708 return (uint16_t)(-1);
1713 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1715 struct i40e_rx_queue *rxq;
1717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719 PMD_INIT_FUNC_TRACE();
1721 if (rx_queue_id < dev->data->nb_rx_queues) {
1722 rxq = dev->data->rx_queues[rx_queue_id];
1724 err = i40e_alloc_rx_queue_mbufs(rxq);
1726 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1732 /* Init the RX tail regieter. */
1733 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1735 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1738 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1741 i40e_rx_queue_release_mbufs(rxq);
1742 i40e_reset_rx_queue(rxq);
1750 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1752 struct i40e_rx_queue *rxq;
1754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756 if (rx_queue_id < dev->data->nb_rx_queues) {
1757 rxq = dev->data->rx_queues[rx_queue_id];
1760 * rx_queue_id is queue id aplication refers to, while
1761 * rxq->reg_idx is the real queue index.
1763 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1766 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1770 i40e_rx_queue_release_mbufs(rxq);
1771 i40e_reset_rx_queue(rxq);
1778 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1781 struct i40e_tx_queue *txq;
1782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784 PMD_INIT_FUNC_TRACE();
1786 if (tx_queue_id < dev->data->nb_tx_queues) {
1787 txq = dev->data->tx_queues[tx_queue_id];
1790 * tx_queue_id is queue id aplication refers to, while
1791 * rxq->reg_idx is the real queue index.
1793 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1795 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1803 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1805 struct i40e_tx_queue *txq;
1807 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1809 if (tx_queue_id < dev->data->nb_tx_queues) {
1810 txq = dev->data->tx_queues[tx_queue_id];
1813 * tx_queue_id is queue id aplication refers to, while
1814 * txq->reg_idx is the real queue index.
1816 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1819 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1824 i40e_tx_queue_release_mbufs(txq);
1825 i40e_reset_tx_queue(txq);
1832 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1835 unsigned int socket_id,
1836 const struct rte_eth_rxconf *rx_conf,
1837 struct rte_mempool *mp)
1839 struct i40e_vsi *vsi;
1840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1842 struct i40e_rx_queue *rxq;
1843 const struct rte_memzone *rz;
1846 int use_def_burst_func = 1;
1848 if (hw->mac.type == I40E_MAC_VF) {
1849 struct i40e_vf *vf =
1850 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1853 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1856 PMD_DRV_LOG(ERR, "VSI not available or queue "
1857 "index exceeds the maximum");
1858 return I40E_ERR_PARAM;
1860 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1861 (nb_desc > I40E_MAX_RING_DESC) ||
1862 (nb_desc < I40E_MIN_RING_DESC)) {
1863 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1864 "invalid", nb_desc);
1865 return I40E_ERR_PARAM;
1868 /* Free memory if needed */
1869 if (dev->data->rx_queues[queue_idx]) {
1870 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1871 dev->data->rx_queues[queue_idx] = NULL;
1874 /* Allocate the rx queue data structure */
1875 rxq = rte_zmalloc_socket("i40e rx queue",
1876 sizeof(struct i40e_rx_queue),
1877 RTE_CACHE_LINE_SIZE,
1880 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1881 "rx queue data structure");
1885 rxq->nb_rx_desc = nb_desc;
1886 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1887 rxq->queue_id = queue_idx;
1888 if (hw->mac.type == I40E_MAC_VF)
1889 rxq->reg_idx = queue_idx;
1890 else /* PF device */
1891 rxq->reg_idx = vsi->base_queue +
1892 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1894 rxq->port_id = dev->data->port_id;
1895 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1897 rxq->drop_en = rx_conf->rx_drop_en;
1899 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1901 /* Allocate the maximun number of RX ring hardware descriptor. */
1902 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1903 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1904 rz = i40e_ring_dma_zone_reserve(dev,
1910 i40e_dev_rx_queue_release(rxq);
1911 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1915 /* Zero all the descriptors in the ring. */
1916 memset(rz->addr, 0, ring_size);
1918 #ifdef RTE_LIBRTE_XEN_DOM0
1919 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1921 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1924 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1926 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1927 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1932 /* Allocate the software ring. */
1934 rte_zmalloc_socket("i40e rx sw ring",
1935 sizeof(struct i40e_rx_entry) * len,
1936 RTE_CACHE_LINE_SIZE,
1938 if (!rxq->sw_ring) {
1939 i40e_dev_rx_queue_release(rxq);
1940 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1944 i40e_reset_rx_queue(rxq);
1946 dev->data->rx_queues[queue_idx] = rxq;
1948 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1950 if (!use_def_burst_func && !dev->data->scattered_rx) {
1951 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1952 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1953 "satisfied. Rx Burst Bulk Alloc function will be "
1954 "used on port=%d, queue=%d.",
1955 rxq->port_id, rxq->queue_id);
1956 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1957 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1959 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1960 "not satisfied, Scattered Rx is requested, "
1961 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1962 "not enabled on port=%d, queue=%d.",
1963 rxq->port_id, rxq->queue_id);
1970 i40e_dev_rx_queue_release(void *rxq)
1972 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1975 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1979 i40e_rx_queue_release_mbufs(q);
1980 rte_free(q->sw_ring);
1985 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1987 #define I40E_RXQ_SCAN_INTERVAL 4
1988 volatile union i40e_rx_desc *rxdp;
1989 struct i40e_rx_queue *rxq;
1992 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1993 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1997 rxq = dev->data->rx_queues[rx_queue_id];
1998 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1999 while ((desc < rxq->nb_rx_desc) &&
2000 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2001 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2002 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2004 * Check the DD bit of a rx descriptor of each 4 in a group,
2005 * to avoid checking too frequently and downgrading performance
2008 desc += I40E_RXQ_SCAN_INTERVAL;
2009 rxdp += I40E_RXQ_SCAN_INTERVAL;
2010 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2011 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2012 desc - rxq->nb_rx_desc]);
2019 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2021 volatile union i40e_rx_desc *rxdp;
2022 struct i40e_rx_queue *rxq = rx_queue;
2026 if (unlikely(offset >= rxq->nb_rx_desc)) {
2027 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2031 desc = rxq->rx_tail + offset;
2032 if (desc >= rxq->nb_rx_desc)
2033 desc -= rxq->nb_rx_desc;
2035 rxdp = &(rxq->rx_ring[desc]);
2037 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2038 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2039 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2045 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2048 unsigned int socket_id,
2049 const struct rte_eth_txconf *tx_conf)
2051 struct i40e_vsi *vsi;
2052 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054 struct i40e_tx_queue *txq;
2055 const struct rte_memzone *tz;
2057 uint16_t tx_rs_thresh, tx_free_thresh;
2059 if (hw->mac.type == I40E_MAC_VF) {
2060 struct i40e_vf *vf =
2061 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2064 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2067 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2068 "exceeds the maximum", queue_idx);
2069 return I40E_ERR_PARAM;
2072 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2073 (nb_desc > I40E_MAX_RING_DESC) ||
2074 (nb_desc < I40E_MIN_RING_DESC)) {
2075 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2076 "invalid", nb_desc);
2077 return I40E_ERR_PARAM;
2081 * The following two parameters control the setting of the RS bit on
2082 * transmit descriptors. TX descriptors will have their RS bit set
2083 * after txq->tx_rs_thresh descriptors have been used. The TX
2084 * descriptor ring will be cleaned after txq->tx_free_thresh
2085 * descriptors are used or if the number of descriptors required to
2086 * transmit a packet is greater than the number of free TX descriptors.
2088 * The following constraints must be satisfied:
2089 * - tx_rs_thresh must be greater than 0.
2090 * - tx_rs_thresh must be less than the size of the ring minus 2.
2091 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2092 * - tx_rs_thresh must be a divisor of the ring size.
2093 * - tx_free_thresh must be greater than 0.
2094 * - tx_free_thresh must be less than the size of the ring minus 3.
2096 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2097 * race condition, hence the maximum threshold constraints. When set
2098 * to zero use default values.
2100 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2101 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2102 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2103 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2104 if (tx_rs_thresh >= (nb_desc - 2)) {
2105 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2106 "number of TX descriptors minus 2. "
2107 "(tx_rs_thresh=%u port=%d queue=%d)",
2108 (unsigned int)tx_rs_thresh,
2109 (int)dev->data->port_id,
2111 return I40E_ERR_PARAM;
2113 if (tx_free_thresh >= (nb_desc - 3)) {
2114 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2115 "tx_free_thresh must be less than the "
2116 "number of TX descriptors minus 3. "
2117 "(tx_free_thresh=%u port=%d queue=%d)",
2118 (unsigned int)tx_free_thresh,
2119 (int)dev->data->port_id,
2121 return I40E_ERR_PARAM;
2123 if (tx_rs_thresh > tx_free_thresh) {
2124 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2125 "equal to tx_free_thresh. (tx_free_thresh=%u"
2126 " tx_rs_thresh=%u port=%d queue=%d)",
2127 (unsigned int)tx_free_thresh,
2128 (unsigned int)tx_rs_thresh,
2129 (int)dev->data->port_id,
2131 return I40E_ERR_PARAM;
2133 if ((nb_desc % tx_rs_thresh) != 0) {
2134 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2135 "number of TX descriptors. (tx_rs_thresh=%u"
2136 " port=%d queue=%d)",
2137 (unsigned int)tx_rs_thresh,
2138 (int)dev->data->port_id,
2140 return I40E_ERR_PARAM;
2142 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2143 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2144 "tx_rs_thresh is greater than 1. "
2145 "(tx_rs_thresh=%u port=%d queue=%d)",
2146 (unsigned int)tx_rs_thresh,
2147 (int)dev->data->port_id,
2149 return I40E_ERR_PARAM;
2152 /* Free memory if needed. */
2153 if (dev->data->tx_queues[queue_idx]) {
2154 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2155 dev->data->tx_queues[queue_idx] = NULL;
2158 /* Allocate the TX queue data structure. */
2159 txq = rte_zmalloc_socket("i40e tx queue",
2160 sizeof(struct i40e_tx_queue),
2161 RTE_CACHE_LINE_SIZE,
2164 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2165 "tx queue structure");
2169 /* Allocate TX hardware ring descriptors. */
2170 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2171 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2172 tz = i40e_ring_dma_zone_reserve(dev,
2178 i40e_dev_tx_queue_release(txq);
2179 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2183 txq->nb_tx_desc = nb_desc;
2184 txq->tx_rs_thresh = tx_rs_thresh;
2185 txq->tx_free_thresh = tx_free_thresh;
2186 txq->pthresh = tx_conf->tx_thresh.pthresh;
2187 txq->hthresh = tx_conf->tx_thresh.hthresh;
2188 txq->wthresh = tx_conf->tx_thresh.wthresh;
2189 txq->queue_id = queue_idx;
2190 if (hw->mac.type == I40E_MAC_VF)
2191 txq->reg_idx = queue_idx;
2192 else /* PF device */
2193 txq->reg_idx = vsi->base_queue +
2194 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2196 txq->port_id = dev->data->port_id;
2197 txq->txq_flags = tx_conf->txq_flags;
2199 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2201 #ifdef RTE_LIBRTE_XEN_DOM0
2202 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2204 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2206 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2208 /* Allocate software ring */
2210 rte_zmalloc_socket("i40e tx sw ring",
2211 sizeof(struct i40e_tx_entry) * nb_desc,
2212 RTE_CACHE_LINE_SIZE,
2214 if (!txq->sw_ring) {
2215 i40e_dev_tx_queue_release(txq);
2216 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2220 i40e_reset_tx_queue(txq);
2222 dev->data->tx_queues[queue_idx] = txq;
2224 /* Use a simple TX queue without offloads or multi segs if possible */
2225 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2226 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2227 PMD_INIT_LOG(INFO, "Using simple tx path");
2228 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2230 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2231 dev->tx_pkt_burst = i40e_xmit_pkts;
2238 i40e_dev_tx_queue_release(void *txq)
2240 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2243 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2247 i40e_tx_queue_release_mbufs(q);
2248 rte_free(q->sw_ring);
2252 static const struct rte_memzone *
2253 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2254 const char *ring_name,
2259 char z_name[RTE_MEMZONE_NAMESIZE];
2260 const struct rte_memzone *mz;
2262 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2263 dev->driver->pci_drv.name, ring_name,
2264 dev->data->port_id, queue_id);
2265 mz = rte_memzone_lookup(z_name);
2269 #ifdef RTE_LIBRTE_XEN_DOM0
2270 return rte_memzone_reserve_bounded(z_name, ring_size,
2271 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2273 return rte_memzone_reserve_aligned(z_name, ring_size,
2274 socket_id, 0, I40E_ALIGN);
2278 const struct rte_memzone *
2279 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2281 const struct rte_memzone *mz = NULL;
2283 mz = rte_memzone_lookup(name);
2286 #ifdef RTE_LIBRTE_XEN_DOM0
2287 mz = rte_memzone_reserve_bounded(name, len,
2288 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2290 mz = rte_memzone_reserve_aligned(name, len,
2291 socket_id, 0, I40E_ALIGN);
2297 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2301 if (!rxq || !rxq->sw_ring) {
2302 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2306 for (i = 0; i < rxq->nb_rx_desc; i++) {
2307 if (rxq->sw_ring[i].mbuf) {
2308 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2309 rxq->sw_ring[i].mbuf = NULL;
2312 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2313 if (rxq->rx_nb_avail == 0)
2315 for (i = 0; i < rxq->rx_nb_avail; i++) {
2316 struct rte_mbuf *mbuf;
2318 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2319 rte_pktmbuf_free_seg(mbuf);
2321 rxq->rx_nb_avail = 0;
2322 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2326 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2331 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2332 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2333 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2335 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2336 len = rxq->nb_rx_desc;
2338 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2339 ((volatile char *)rxq->rx_ring)[i] = 0;
2341 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2342 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2343 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2344 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2346 rxq->rx_nb_avail = 0;
2347 rxq->rx_next_avail = 0;
2348 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2349 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2351 rxq->nb_rx_hold = 0;
2352 rxq->pkt_first_seg = NULL;
2353 rxq->pkt_last_seg = NULL;
2357 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2361 if (!txq || !txq->sw_ring) {
2362 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2366 for (i = 0; i < txq->nb_tx_desc; i++) {
2367 if (txq->sw_ring[i].mbuf) {
2368 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2369 txq->sw_ring[i].mbuf = NULL;
2375 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2377 struct i40e_tx_entry *txe;
2378 uint16_t i, prev, size;
2381 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2386 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2387 for (i = 0; i < size; i++)
2388 ((volatile char *)txq->tx_ring)[i] = 0;
2390 prev = (uint16_t)(txq->nb_tx_desc - 1);
2391 for (i = 0; i < txq->nb_tx_desc; i++) {
2392 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2394 txd->cmd_type_offset_bsz =
2395 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2398 txe[prev].next_id = i;
2402 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2403 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2406 txq->nb_tx_used = 0;
2408 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2409 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2412 /* Init the TX queue in hardware */
2414 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2416 enum i40e_status_code err = I40E_SUCCESS;
2417 struct i40e_vsi *vsi = txq->vsi;
2418 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2419 uint16_t pf_q = txq->reg_idx;
2420 struct i40e_hmc_obj_txq tx_ctx;
2423 /* clear the context structure first */
2424 memset(&tx_ctx, 0, sizeof(tx_ctx));
2425 tx_ctx.new_context = 1;
2426 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2427 tx_ctx.qlen = txq->nb_tx_desc;
2429 #ifdef RTE_LIBRTE_IEEE1588
2430 tx_ctx.timesync_ena = 1;
2432 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2433 if (vsi->type == I40E_VSI_FDIR)
2434 tx_ctx.fd_ena = TRUE;
2436 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2437 if (err != I40E_SUCCESS) {
2438 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2442 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2443 if (err != I40E_SUCCESS) {
2444 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2448 /* Now associate this queue with this PCI function */
2449 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2450 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2451 I40E_QTX_CTL_PF_INDX_MASK);
2452 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2453 I40E_WRITE_FLUSH(hw);
2455 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2461 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2463 struct i40e_rx_entry *rxe = rxq->sw_ring;
2467 for (i = 0; i < rxq->nb_rx_desc; i++) {
2468 volatile union i40e_rx_desc *rxd;
2469 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2471 if (unlikely(!mbuf)) {
2472 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2476 rte_mbuf_refcnt_set(mbuf, 1);
2478 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2480 mbuf->port = rxq->port_id;
2483 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2485 rxd = &rxq->rx_ring[i];
2486 rxd->read.pkt_addr = dma_addr;
2487 rxd->read.hdr_addr = dma_addr;
2488 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2489 rxd->read.rsvd1 = 0;
2490 rxd->read.rsvd2 = 0;
2491 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2500 * Calculate the buffer length, and check the jumbo frame
2501 * and maximum packet length.
2504 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2506 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2507 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2508 struct rte_eth_dev_data *data = pf->dev_data;
2509 uint16_t buf_size, len;
2511 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2512 RTE_PKTMBUF_HEADROOM);
2514 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2515 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2516 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2517 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2518 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2519 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2520 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2521 rxq->hs_mode = i40e_header_split_enabled;
2523 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2525 rxq->rx_hdr_len = 0;
2526 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2527 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2528 rxq->hs_mode = i40e_header_split_none;
2532 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2533 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2534 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2535 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2536 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2537 PMD_DRV_LOG(ERR, "maximum packet length must "
2538 "be larger than %u and smaller than %u,"
2539 "as jumbo frame is enabled",
2540 (uint32_t)ETHER_MAX_LEN,
2541 (uint32_t)I40E_FRAME_SIZE_MAX);
2542 return I40E_ERR_CONFIG;
2545 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2546 rxq->max_pkt_len > ETHER_MAX_LEN) {
2547 PMD_DRV_LOG(ERR, "maximum packet length must be "
2548 "larger than %u and smaller than %u, "
2549 "as jumbo frame is disabled",
2550 (uint32_t)ETHER_MIN_LEN,
2551 (uint32_t)ETHER_MAX_LEN);
2552 return I40E_ERR_CONFIG;
2559 /* Init the RX queue in hardware */
2561 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2563 int err = I40E_SUCCESS;
2564 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2565 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2566 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2567 uint16_t pf_q = rxq->reg_idx;
2569 struct i40e_hmc_obj_rxq rx_ctx;
2571 err = i40e_rx_queue_config(rxq);
2573 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2577 /* Clear the context structure first */
2578 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2579 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2580 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2582 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2583 rx_ctx.qlen = rxq->nb_rx_desc;
2584 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2587 rx_ctx.dtype = rxq->hs_mode;
2589 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2591 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2592 rx_ctx.rxmax = rxq->max_pkt_len;
2593 rx_ctx.tphrdesc_ena = 1;
2594 rx_ctx.tphwdesc_ena = 1;
2595 rx_ctx.tphdata_ena = 1;
2596 rx_ctx.tphhead_ena = 1;
2597 rx_ctx.lrxqthresh = 2;
2598 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2603 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2604 if (err != I40E_SUCCESS) {
2605 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2608 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2609 if (err != I40E_SUCCESS) {
2610 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2614 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2616 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2617 RTE_PKTMBUF_HEADROOM);
2619 /* Check if scattered RX needs to be used. */
2620 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2621 dev_data->scattered_rx = 1;
2622 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2625 /* Init the RX tail regieter. */
2626 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2632 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2636 PMD_INIT_FUNC_TRACE();
2638 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2639 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2640 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2643 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2644 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2645 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2649 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2650 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2652 enum i40e_status_code
2653 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2655 struct i40e_tx_queue *txq;
2656 const struct rte_memzone *tz = NULL;
2658 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2661 PMD_DRV_LOG(ERR, "PF is not available");
2662 return I40E_ERR_BAD_PTR;
2665 /* Allocate the TX queue data structure. */
2666 txq = rte_zmalloc_socket("i40e fdir tx queue",
2667 sizeof(struct i40e_tx_queue),
2668 RTE_CACHE_LINE_SIZE,
2671 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2672 "tx queue structure.");
2673 return I40E_ERR_NO_MEMORY;
2676 /* Allocate TX hardware ring descriptors. */
2677 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2678 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2680 tz = i40e_ring_dma_zone_reserve(dev,
2686 i40e_dev_tx_queue_release(txq);
2687 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2688 return I40E_ERR_NO_MEMORY;
2691 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2692 txq->queue_id = I40E_FDIR_QUEUE_ID;
2693 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2694 txq->vsi = pf->fdir.fdir_vsi;
2696 #ifdef RTE_LIBRTE_XEN_DOM0
2697 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2699 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2701 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2703 * don't need to allocate software ring and reset for the fdir
2704 * program queue just set the queue has been configured.
2709 return I40E_SUCCESS;
2712 enum i40e_status_code
2713 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2715 struct i40e_rx_queue *rxq;
2716 const struct rte_memzone *rz = NULL;
2718 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2721 PMD_DRV_LOG(ERR, "PF is not available");
2722 return I40E_ERR_BAD_PTR;
2725 /* Allocate the RX queue data structure. */
2726 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2727 sizeof(struct i40e_rx_queue),
2728 RTE_CACHE_LINE_SIZE,
2731 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2732 "rx queue structure.");
2733 return I40E_ERR_NO_MEMORY;
2736 /* Allocate RX hardware ring descriptors. */
2737 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2738 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2740 rz = i40e_ring_dma_zone_reserve(dev,
2746 i40e_dev_rx_queue_release(rxq);
2747 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2748 return I40E_ERR_NO_MEMORY;
2751 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2752 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2753 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2754 rxq->vsi = pf->fdir.fdir_vsi;
2756 #ifdef RTE_LIBRTE_XEN_DOM0
2757 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2759 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2761 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2764 * Don't need to allocate software ring and reset for the fdir
2765 * rx queue, just set the queue has been configured.
2770 return I40E_SUCCESS;