4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_type.h"
59 #include "i40e_ethdev.h"
60 #include "i40e_rxtx.h"
62 #define DEFAULT_TX_RS_THRESH 32
63 #define DEFAULT_TX_FREE_THRESH 32
64 #define I40E_MAX_PKT_TYPE 256
66 #define I40E_TX_MAX_BURST 32
68 #define I40E_DMA_MEM_ALIGN 4096
70 /* Base address of the HW descriptor ring should be 128B aligned. */
71 #define I40E_RING_BASE_ALIGN 128
73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
74 ETH_TXQ_FLAGS_NOOFFLOADS)
76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
78 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
82 PKT_TX_OUTER_IP_CKSUM)
84 #define I40E_TX_OFFLOAD_MASK ( \
87 PKT_TX_OUTER_IP_CKSUM | \
92 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
93 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
95 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
96 struct rte_mbuf **tx_pkts,
100 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
102 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
103 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
104 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
106 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
107 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
108 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
112 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
113 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
114 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
115 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
116 mb->vlan_tci_outer = mb->vlan_tci;
117 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
118 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
119 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
120 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
122 mb->vlan_tci_outer = 0;
125 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
126 mb->vlan_tci, mb->vlan_tci_outer);
129 /* Translate the rx descriptor status to pkt flags */
130 static inline uint64_t
131 i40e_rxd_status_to_pkt_flags(uint64_t qword)
135 /* Check if RSS_HASH */
136 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
137 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
138 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
140 /* Check if FDIR Match */
141 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
147 static inline uint64_t
148 i40e_rxd_error_to_pkt_flags(uint64_t qword)
151 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
153 #define I40E_RX_ERR_BITS 0x3f
154 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
156 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
157 flags |= PKT_RX_IP_CKSUM_BAD;
159 flags |= PKT_RX_IP_CKSUM_GOOD;
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
162 flags |= PKT_RX_L4_CKSUM_BAD;
164 flags |= PKT_RX_L4_CKSUM_GOOD;
166 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
167 flags |= PKT_RX_EIP_CKSUM_BAD;
172 /* Function to check and set the ieee1588 timesync index and get the
175 #ifdef RTE_LIBRTE_IEEE1588
176 static inline uint64_t
177 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
179 uint64_t pkt_flags = 0;
180 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
181 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
182 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
184 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
185 == RTE_PTYPE_L2_ETHER_TIMESYNC)
186 pkt_flags = PKT_RX_IEEE1588_PTP;
188 pkt_flags |= PKT_RX_IEEE1588_TMST;
189 mb->timesync = tsyn & 0x03;
196 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
197 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
198 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
199 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
200 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
202 static inline uint64_t
203 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
206 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
207 uint16_t flexbh, flexbl;
209 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
210 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
211 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
212 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
213 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
214 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
217 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
219 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
220 flags |= PKT_RX_FDIR_ID;
221 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
223 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
224 flags |= PKT_RX_FDIR_FLX;
226 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
228 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
229 flags |= PKT_RX_FDIR_FLX;
233 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
234 flags |= PKT_RX_FDIR_ID;
240 i40e_parse_tunneling_params(uint64_t ol_flags,
241 union i40e_tx_offload tx_offload,
242 uint32_t *cd_tunneling)
244 /* EIPT: External (outer) IP header type */
245 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
246 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
247 else if (ol_flags & PKT_TX_OUTER_IPV4)
248 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
249 else if (ol_flags & PKT_TX_OUTER_IPV6)
250 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
252 /* EIPLEN: External (outer) IP header length, in DWords */
253 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
254 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
256 /* L4TUNT: L4 Tunneling Type */
257 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
258 case PKT_TX_TUNNEL_IPIP:
259 /* for non UDP / GRE tunneling, set to 00b */
261 case PKT_TX_TUNNEL_VXLAN:
262 case PKT_TX_TUNNEL_GENEVE:
263 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
265 case PKT_TX_TUNNEL_GRE:
266 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
269 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
273 /* L4TUNLEN: L4 Tunneling Length, in Words
275 * We depend on app to set rte_mbuf.l2_len correctly.
276 * For IP in GRE it should be set to the length of the GRE
278 * for MAC in GRE or MAC in UDP it should be set to the length
279 * of the GRE or UDP headers plus the inner MAC up to including
280 * its last Ethertype.
282 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
283 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
287 i40e_txd_enable_checksum(uint64_t ol_flags,
290 union i40e_tx_offload tx_offload)
293 if (ol_flags & PKT_TX_TUNNEL_MASK)
294 *td_offset |= (tx_offload.outer_l2_len >> 1)
295 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
297 *td_offset |= (tx_offload.l2_len >> 1)
298 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
300 /* Enable L3 checksum offloads */
301 if (ol_flags & PKT_TX_IP_CKSUM) {
302 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
303 *td_offset |= (tx_offload.l3_len >> 2)
304 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
305 } else if (ol_flags & PKT_TX_IPV4) {
306 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
307 *td_offset |= (tx_offload.l3_len >> 2)
308 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
309 } else if (ol_flags & PKT_TX_IPV6) {
310 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
311 *td_offset |= (tx_offload.l3_len >> 2)
312 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
315 if (ol_flags & PKT_TX_TCP_SEG) {
316 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
317 *td_offset |= (tx_offload.l4_len >> 2)
318 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
322 /* Enable L4 checksum offloads */
323 switch (ol_flags & PKT_TX_L4_MASK) {
324 case PKT_TX_TCP_CKSUM:
325 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
326 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
327 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
329 case PKT_TX_SCTP_CKSUM:
330 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
331 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
332 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
334 case PKT_TX_UDP_CKSUM:
335 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
336 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
337 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
344 /* Construct the tx flags */
345 static inline uint64_t
346 i40e_build_ctob(uint32_t td_cmd,
351 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
352 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
353 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
354 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
355 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
359 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
361 struct i40e_tx_entry *sw_ring = txq->sw_ring;
362 volatile struct i40e_tx_desc *txd = txq->tx_ring;
363 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
364 uint16_t nb_tx_desc = txq->nb_tx_desc;
365 uint16_t desc_to_clean_to;
366 uint16_t nb_tx_to_clean;
368 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
369 if (desc_to_clean_to >= nb_tx_desc)
370 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
372 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
373 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
374 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
375 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
376 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
377 "(port=%d queue=%d)", desc_to_clean_to,
378 txq->port_id, txq->queue_id);
382 if (last_desc_cleaned > desc_to_clean_to)
383 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
386 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
389 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
391 txq->last_desc_cleaned = desc_to_clean_to;
392 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
398 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
399 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
401 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
407 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
408 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
409 "rxq->rx_free_thresh=%d, "
410 "RTE_PMD_I40E_RX_MAX_BURST=%d",
411 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
413 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
414 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
415 "rxq->rx_free_thresh=%d, "
416 "rxq->nb_rx_desc=%d",
417 rxq->rx_free_thresh, rxq->nb_rx_desc);
419 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
420 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
421 "rxq->nb_rx_desc=%d, "
422 "rxq->rx_free_thresh=%d",
423 rxq->nb_rx_desc, rxq->rx_free_thresh);
425 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
426 RTE_PMD_I40E_RX_MAX_BURST))) {
427 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
428 "rxq->nb_rx_desc=%d, "
429 "I40E_MAX_RING_DESC=%d, "
430 "RTE_PMD_I40E_RX_MAX_BURST=%d",
431 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
432 RTE_PMD_I40E_RX_MAX_BURST);
442 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
443 #define I40E_LOOK_AHEAD 8
444 #if (I40E_LOOK_AHEAD != 8)
445 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
448 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
450 volatile union i40e_rx_desc *rxdp;
451 struct i40e_rx_entry *rxep;
456 int32_t s[I40E_LOOK_AHEAD], nb_dd;
457 int32_t i, j, nb_rx = 0;
460 rxdp = &rxq->rx_ring[rxq->rx_tail];
461 rxep = &rxq->sw_ring[rxq->rx_tail];
463 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
464 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
465 I40E_RXD_QW1_STATUS_SHIFT;
467 /* Make sure there is at least 1 packet to receive */
468 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
472 * Scan LOOK_AHEAD descriptors at a time to determine which
473 * descriptors reference packets that are ready to be received.
475 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
476 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
477 /* Read desc statuses backwards to avoid race condition */
478 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
479 qword1 = rte_le_to_cpu_64(\
480 rxdp[j].wb.qword1.status_error_len);
481 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
482 I40E_RXD_QW1_STATUS_SHIFT;
487 /* Compute how many status bits were set */
488 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
489 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
493 /* Translate descriptor info to mbuf parameters */
494 for (j = 0; j < nb_dd; j++) {
496 qword1 = rte_le_to_cpu_64(\
497 rxdp[j].wb.qword1.status_error_len);
498 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
499 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
500 mb->data_len = pkt_len;
501 mb->pkt_len = pkt_len;
503 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
504 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
505 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
507 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
508 I40E_RXD_QW1_PTYPE_MASK) >>
509 I40E_RXD_QW1_PTYPE_SHIFT));
510 if (pkt_flags & PKT_RX_RSS_HASH)
511 mb->hash.rss = rte_le_to_cpu_32(\
512 rxdp[j].wb.qword0.hi_dword.rss);
513 if (pkt_flags & PKT_RX_FDIR)
514 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
516 #ifdef RTE_LIBRTE_IEEE1588
517 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
519 mb->ol_flags |= pkt_flags;
523 for (j = 0; j < I40E_LOOK_AHEAD; j++)
524 rxq->rx_stage[i + j] = rxep[j].mbuf;
526 if (nb_dd != I40E_LOOK_AHEAD)
530 /* Clear software ring entries */
531 for (i = 0; i < nb_rx; i++)
532 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
537 static inline uint16_t
538 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
539 struct rte_mbuf **rx_pkts,
543 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
545 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
547 for (i = 0; i < nb_pkts; i++)
548 rx_pkts[i] = stage[i];
550 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
551 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
557 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
559 volatile union i40e_rx_desc *rxdp;
560 struct i40e_rx_entry *rxep;
562 uint16_t alloc_idx, i;
566 /* Allocate buffers in bulk */
567 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
568 (rxq->rx_free_thresh - 1));
569 rxep = &(rxq->sw_ring[alloc_idx]);
570 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
571 rxq->rx_free_thresh);
572 if (unlikely(diag != 0)) {
573 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
577 rxdp = &rxq->rx_ring[alloc_idx];
578 for (i = 0; i < rxq->rx_free_thresh; i++) {
579 if (likely(i < (rxq->rx_free_thresh - 1)))
580 /* Prefetch next mbuf */
581 rte_prefetch0(rxep[i + 1].mbuf);
584 rte_mbuf_refcnt_set(mb, 1);
586 mb->data_off = RTE_PKTMBUF_HEADROOM;
588 mb->port = rxq->port_id;
589 dma_addr = rte_cpu_to_le_64(\
590 rte_mbuf_data_dma_addr_default(mb));
591 rxdp[i].read.hdr_addr = 0;
592 rxdp[i].read.pkt_addr = dma_addr;
595 /* Update rx tail regsiter */
597 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
599 rxq->rx_free_trigger =
600 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
601 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
602 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
607 static inline uint16_t
608 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
610 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
616 if (rxq->rx_nb_avail)
617 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
619 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
620 rxq->rx_next_avail = 0;
621 rxq->rx_nb_avail = nb_rx;
622 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
624 if (rxq->rx_tail > rxq->rx_free_trigger) {
625 if (i40e_rx_alloc_bufs(rxq) != 0) {
628 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
629 "port_id=%u, queue_id=%u",
630 rxq->port_id, rxq->queue_id);
631 rxq->rx_nb_avail = 0;
632 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
633 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
634 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
640 if (rxq->rx_tail >= rxq->nb_rx_desc)
643 if (rxq->rx_nb_avail)
644 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
650 i40e_recv_pkts_bulk_alloc(void *rx_queue,
651 struct rte_mbuf **rx_pkts,
654 uint16_t nb_rx = 0, n, count;
656 if (unlikely(nb_pkts == 0))
659 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
660 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
663 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
664 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
665 nb_rx = (uint16_t)(nb_rx + count);
666 nb_pkts = (uint16_t)(nb_pkts - count);
675 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
676 struct rte_mbuf __rte_unused **rx_pkts,
677 uint16_t __rte_unused nb_pkts)
681 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
684 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
686 struct i40e_rx_queue *rxq;
687 volatile union i40e_rx_desc *rx_ring;
688 volatile union i40e_rx_desc *rxdp;
689 union i40e_rx_desc rxd;
690 struct i40e_rx_entry *sw_ring;
691 struct i40e_rx_entry *rxe;
692 struct rte_mbuf *rxm;
693 struct rte_mbuf *nmb;
697 uint16_t rx_packet_len;
698 uint16_t rx_id, nb_hold;
705 rx_id = rxq->rx_tail;
706 rx_ring = rxq->rx_ring;
707 sw_ring = rxq->sw_ring;
709 while (nb_rx < nb_pkts) {
710 rxdp = &rx_ring[rx_id];
711 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
712 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
713 >> I40E_RXD_QW1_STATUS_SHIFT;
715 /* Check the DD bit first */
716 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
719 nmb = rte_mbuf_raw_alloc(rxq->mp);
725 rxe = &sw_ring[rx_id];
727 if (unlikely(rx_id == rxq->nb_rx_desc))
730 /* Prefetch next mbuf */
731 rte_prefetch0(sw_ring[rx_id].mbuf);
734 * When next RX descriptor is on a cache line boundary,
735 * prefetch the next 4 RX descriptors and next 8 pointers
738 if ((rx_id & 0x3) == 0) {
739 rte_prefetch0(&rx_ring[rx_id]);
740 rte_prefetch0(&sw_ring[rx_id]);
745 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
746 rxdp->read.hdr_addr = 0;
747 rxdp->read.pkt_addr = dma_addr;
749 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
750 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
752 rxm->data_off = RTE_PKTMBUF_HEADROOM;
753 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
756 rxm->pkt_len = rx_packet_len;
757 rxm->data_len = rx_packet_len;
758 rxm->port = rxq->port_id;
760 i40e_rxd_to_vlan_tci(rxm, &rxd);
761 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
762 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
764 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
765 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
766 if (pkt_flags & PKT_RX_RSS_HASH)
768 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
769 if (pkt_flags & PKT_RX_FDIR)
770 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
772 #ifdef RTE_LIBRTE_IEEE1588
773 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
775 rxm->ol_flags |= pkt_flags;
777 rx_pkts[nb_rx++] = rxm;
779 rxq->rx_tail = rx_id;
782 * If the number of free RX descriptors is greater than the RX free
783 * threshold of the queue, advance the receive tail register of queue.
784 * Update that register with the value of the last processed RX
785 * descriptor minus 1.
787 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
788 if (nb_hold > rxq->rx_free_thresh) {
789 rx_id = (uint16_t) ((rx_id == 0) ?
790 (rxq->nb_rx_desc - 1) : (rx_id - 1));
791 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
794 rxq->nb_rx_hold = nb_hold;
800 i40e_recv_scattered_pkts(void *rx_queue,
801 struct rte_mbuf **rx_pkts,
804 struct i40e_rx_queue *rxq = rx_queue;
805 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
806 volatile union i40e_rx_desc *rxdp;
807 union i40e_rx_desc rxd;
808 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
809 struct i40e_rx_entry *rxe;
810 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
811 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
812 struct rte_mbuf *nmb, *rxm;
813 uint16_t rx_id = rxq->rx_tail;
814 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
820 while (nb_rx < nb_pkts) {
821 rxdp = &rx_ring[rx_id];
822 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
823 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
824 I40E_RXD_QW1_STATUS_SHIFT;
826 /* Check the DD bit */
827 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
830 nmb = rte_mbuf_raw_alloc(rxq->mp);
835 rxe = &sw_ring[rx_id];
837 if (rx_id == rxq->nb_rx_desc)
840 /* Prefetch next mbuf */
841 rte_prefetch0(sw_ring[rx_id].mbuf);
844 * When next RX descriptor is on a cache line boundary,
845 * prefetch the next 4 RX descriptors and next 8 pointers
848 if ((rx_id & 0x3) == 0) {
849 rte_prefetch0(&rx_ring[rx_id]);
850 rte_prefetch0(&sw_ring[rx_id]);
856 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
858 /* Set data buffer address and data length of the mbuf */
859 rxdp->read.hdr_addr = 0;
860 rxdp->read.pkt_addr = dma_addr;
861 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
862 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
863 rxm->data_len = rx_packet_len;
864 rxm->data_off = RTE_PKTMBUF_HEADROOM;
867 * If this is the first buffer of the received packet, set the
868 * pointer to the first mbuf of the packet and initialize its
869 * context. Otherwise, update the total length and the number
870 * of segments of the current scattered packet, and update the
871 * pointer to the last mbuf of the current packet.
875 first_seg->nb_segs = 1;
876 first_seg->pkt_len = rx_packet_len;
879 (uint16_t)(first_seg->pkt_len +
881 first_seg->nb_segs++;
882 last_seg->next = rxm;
886 * If this is not the last buffer of the received packet,
887 * update the pointer to the last mbuf of the current scattered
888 * packet and continue to parse the RX ring.
890 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
896 * This is the last buffer of the received packet. If the CRC
897 * is not stripped by the hardware:
898 * - Subtract the CRC length from the total packet length.
899 * - If the last buffer only contains the whole CRC or a part
900 * of it, free the mbuf associated to the last buffer. If part
901 * of the CRC is also contained in the previous mbuf, subtract
902 * the length of that CRC part from the data length of the
906 if (unlikely(rxq->crc_len > 0)) {
907 first_seg->pkt_len -= ETHER_CRC_LEN;
908 if (rx_packet_len <= ETHER_CRC_LEN) {
909 rte_pktmbuf_free_seg(rxm);
910 first_seg->nb_segs--;
912 (uint16_t)(last_seg->data_len -
913 (ETHER_CRC_LEN - rx_packet_len));
914 last_seg->next = NULL;
916 rxm->data_len = (uint16_t)(rx_packet_len -
920 first_seg->port = rxq->port_id;
921 first_seg->ol_flags = 0;
922 i40e_rxd_to_vlan_tci(first_seg, &rxd);
923 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
924 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
925 first_seg->packet_type =
926 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
927 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
928 if (pkt_flags & PKT_RX_RSS_HASH)
929 first_seg->hash.rss =
930 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
931 if (pkt_flags & PKT_RX_FDIR)
932 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
934 #ifdef RTE_LIBRTE_IEEE1588
935 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
937 first_seg->ol_flags |= pkt_flags;
939 /* Prefetch data of first segment, if configured to do so. */
940 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
941 first_seg->data_off));
942 rx_pkts[nb_rx++] = first_seg;
946 /* Record index of the next RX descriptor to probe. */
947 rxq->rx_tail = rx_id;
948 rxq->pkt_first_seg = first_seg;
949 rxq->pkt_last_seg = last_seg;
952 * If the number of free RX descriptors is greater than the RX free
953 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
954 * register. Update the RDT with the value of the last processed RX
955 * descriptor minus 1, to guarantee that the RDT register is never
956 * equal to the RDH register, which creates a "full" ring situtation
957 * from the hardware point of view.
959 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
960 if (nb_hold > rxq->rx_free_thresh) {
961 rx_id = (uint16_t)(rx_id == 0 ?
962 (rxq->nb_rx_desc - 1) : (rx_id - 1));
963 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
966 rxq->nb_rx_hold = nb_hold;
971 /* Check if the context descriptor is needed for TX offloading */
972 static inline uint16_t
973 i40e_calc_context_desc(uint64_t flags)
975 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
980 #ifdef RTE_LIBRTE_IEEE1588
981 mask |= PKT_TX_IEEE1588_TMST;
984 return (flags & mask) ? 1 : 0;
987 /* set i40e TSO context descriptor */
988 static inline uint64_t
989 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
991 uint64_t ctx_desc = 0;
992 uint32_t cd_cmd, hdr_len, cd_tso_len;
994 if (!tx_offload.l4_len) {
995 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1000 * in case of non tunneling packet, the outer_l2_len and
1001 * outer_l3_len must be 0.
1003 hdr_len = tx_offload.outer_l2_len +
1004 tx_offload.outer_l3_len +
1009 cd_cmd = I40E_TX_CTX_DESC_TSO;
1010 cd_tso_len = mbuf->pkt_len - hdr_len;
1011 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1012 ((uint64_t)cd_tso_len <<
1013 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1014 ((uint64_t)mbuf->tso_segsz <<
1015 I40E_TXD_CTX_QW1_MSS_SHIFT);
1021 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1023 struct i40e_tx_queue *txq;
1024 struct i40e_tx_entry *sw_ring;
1025 struct i40e_tx_entry *txe, *txn;
1026 volatile struct i40e_tx_desc *txd;
1027 volatile struct i40e_tx_desc *txr;
1028 struct rte_mbuf *tx_pkt;
1029 struct rte_mbuf *m_seg;
1030 uint32_t cd_tunneling_params;
1042 uint64_t buf_dma_addr;
1043 union i40e_tx_offload tx_offload = {0};
1046 sw_ring = txq->sw_ring;
1048 tx_id = txq->tx_tail;
1049 txe = &sw_ring[tx_id];
1051 /* Check if the descriptor ring needs to be cleaned. */
1052 if (txq->nb_tx_free < txq->tx_free_thresh)
1053 i40e_xmit_cleanup(txq);
1055 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1061 tx_pkt = *tx_pkts++;
1062 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1064 ol_flags = tx_pkt->ol_flags;
1065 tx_offload.l2_len = tx_pkt->l2_len;
1066 tx_offload.l3_len = tx_pkt->l3_len;
1067 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1068 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1069 tx_offload.l4_len = tx_pkt->l4_len;
1070 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1072 /* Calculate the number of context descriptors needed. */
1073 nb_ctx = i40e_calc_context_desc(ol_flags);
1076 * The number of descriptors that must be allocated for
1077 * a packet equals to the number of the segments of that
1078 * packet plus 1 context descriptor if needed.
1080 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1081 tx_last = (uint16_t)(tx_id + nb_used - 1);
1084 if (tx_last >= txq->nb_tx_desc)
1085 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1087 if (nb_used > txq->nb_tx_free) {
1088 if (i40e_xmit_cleanup(txq) != 0) {
1093 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1094 while (nb_used > txq->nb_tx_free) {
1095 if (i40e_xmit_cleanup(txq) != 0) {
1104 /* Descriptor based VLAN insertion */
1105 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1106 tx_flags |= tx_pkt->vlan_tci <<
1107 I40E_TX_FLAG_L2TAG1_SHIFT;
1108 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1109 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1110 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1111 I40E_TX_FLAG_L2TAG1_SHIFT;
1114 /* Always enable CRC offload insertion */
1115 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1117 /* Fill in tunneling parameters if necessary */
1118 cd_tunneling_params = 0;
1119 if (ol_flags & PKT_TX_TUNNEL_MASK)
1120 i40e_parse_tunneling_params(ol_flags, tx_offload,
1121 &cd_tunneling_params);
1122 /* Enable checksum offloading */
1123 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1124 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1125 &td_offset, tx_offload);
1128 /* Setup TX context descriptor if required */
1129 volatile struct i40e_tx_context_desc *ctx_txd =
1130 (volatile struct i40e_tx_context_desc *)\
1132 uint16_t cd_l2tag2 = 0;
1133 uint64_t cd_type_cmd_tso_mss =
1134 I40E_TX_DESC_DTYPE_CONTEXT;
1136 txn = &sw_ring[txe->next_id];
1137 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1138 if (txe->mbuf != NULL) {
1139 rte_pktmbuf_free_seg(txe->mbuf);
1143 /* TSO enabled means no timestamp */
1144 if (ol_flags & PKT_TX_TCP_SEG)
1145 cd_type_cmd_tso_mss |=
1146 i40e_set_tso_ctx(tx_pkt, tx_offload);
1148 #ifdef RTE_LIBRTE_IEEE1588
1149 if (ol_flags & PKT_TX_IEEE1588_TMST)
1150 cd_type_cmd_tso_mss |=
1151 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1152 I40E_TXD_CTX_QW1_CMD_SHIFT);
1156 ctx_txd->tunneling_params =
1157 rte_cpu_to_le_32(cd_tunneling_params);
1158 if (ol_flags & PKT_TX_QINQ_PKT) {
1159 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1160 cd_type_cmd_tso_mss |=
1161 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1162 I40E_TXD_CTX_QW1_CMD_SHIFT);
1164 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1165 ctx_txd->type_cmd_tso_mss =
1166 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1168 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1169 "tunneling_params: %#x;\n"
1172 "type_cmd_tso_mss: %#"PRIx64";\n",
1174 ctx_txd->tunneling_params,
1177 ctx_txd->type_cmd_tso_mss);
1179 txe->last_id = tx_last;
1180 tx_id = txe->next_id;
1187 txn = &sw_ring[txe->next_id];
1190 rte_pktmbuf_free_seg(txe->mbuf);
1193 /* Setup TX Descriptor */
1194 slen = m_seg->data_len;
1195 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1197 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1198 "buf_dma_addr: %#"PRIx64";\n"
1203 tx_pkt, tx_id, buf_dma_addr,
1204 td_cmd, td_offset, slen, td_tag);
1206 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1207 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1208 td_offset, slen, td_tag);
1209 txe->last_id = tx_last;
1210 tx_id = txe->next_id;
1212 m_seg = m_seg->next;
1213 } while (m_seg != NULL);
1215 /* The last packet data descriptor needs End Of Packet (EOP) */
1216 td_cmd |= I40E_TX_DESC_CMD_EOP;
1217 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1218 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1220 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1221 PMD_TX_FREE_LOG(DEBUG,
1222 "Setting RS bit on TXD id="
1223 "%4u (port=%d queue=%d)",
1224 tx_last, txq->port_id, txq->queue_id);
1226 td_cmd |= I40E_TX_DESC_CMD_RS;
1228 /* Update txq RS bit counters */
1229 txq->nb_tx_used = 0;
1232 txd->cmd_type_offset_bsz |=
1233 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1234 I40E_TXD_QW1_CMD_SHIFT);
1240 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1241 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1242 (unsigned) tx_id, (unsigned) nb_tx);
1244 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1245 txq->tx_tail = tx_id;
1250 static inline int __attribute__((always_inline))
1251 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1253 struct i40e_tx_entry *txep;
1256 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1257 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1258 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1261 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1263 for (i = 0; i < txq->tx_rs_thresh; i++)
1264 rte_prefetch0((txep + i)->mbuf);
1266 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1267 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1268 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1272 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1273 rte_pktmbuf_free_seg(txep->mbuf);
1278 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1279 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1280 if (txq->tx_next_dd >= txq->nb_tx_desc)
1281 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1283 return txq->tx_rs_thresh;
1286 /* Populate 4 descriptors with data from 4 mbufs */
1288 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1293 for (i = 0; i < 4; i++, txdp++, pkts++) {
1294 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1295 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1296 txdp->cmd_type_offset_bsz =
1297 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1298 (*pkts)->data_len, 0);
1302 /* Populate 1 descriptor with data from 1 mbuf */
1304 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1308 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1309 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1310 txdp->cmd_type_offset_bsz =
1311 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1312 (*pkts)->data_len, 0);
1315 /* Fill hardware descriptor ring with mbuf data */
1317 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1318 struct rte_mbuf **pkts,
1321 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1322 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1323 const int N_PER_LOOP = 4;
1324 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1325 int mainpart, leftover;
1328 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1329 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1330 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1331 for (j = 0; j < N_PER_LOOP; ++j) {
1332 (txep + i + j)->mbuf = *(pkts + i + j);
1334 tx4(txdp + i, pkts + i);
1336 if (unlikely(leftover > 0)) {
1337 for (i = 0; i < leftover; ++i) {
1338 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1339 tx1(txdp + mainpart + i, pkts + mainpart + i);
1344 static inline uint16_t
1345 tx_xmit_pkts(struct i40e_tx_queue *txq,
1346 struct rte_mbuf **tx_pkts,
1349 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1353 * Begin scanning the H/W ring for done descriptors when the number
1354 * of available descriptors drops below tx_free_thresh. For each done
1355 * descriptor, free the associated buffer.
1357 if (txq->nb_tx_free < txq->tx_free_thresh)
1358 i40e_tx_free_bufs(txq);
1360 /* Use available descriptor only */
1361 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1362 if (unlikely(!nb_pkts))
1365 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1366 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1367 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1368 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1369 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1370 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1371 I40E_TXD_QW1_CMD_SHIFT);
1372 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1376 /* Fill hardware descriptor ring with mbuf data */
1377 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1378 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1380 /* Determin if RS bit needs to be set */
1381 if (txq->tx_tail > txq->tx_next_rs) {
1382 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1383 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1384 I40E_TXD_QW1_CMD_SHIFT);
1386 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1387 if (txq->tx_next_rs >= txq->nb_tx_desc)
1388 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1391 if (txq->tx_tail >= txq->nb_tx_desc)
1394 /* Update the tx tail register */
1396 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1402 i40e_xmit_pkts_simple(void *tx_queue,
1403 struct rte_mbuf **tx_pkts,
1408 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1409 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1413 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1416 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1417 &tx_pkts[nb_tx], num);
1418 nb_tx = (uint16_t)(nb_tx + ret);
1419 nb_pkts = (uint16_t)(nb_pkts - ret);
1427 /*********************************************************************
1431 **********************************************************************/
1433 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1440 for (i = 0; i < nb_pkts; i++) {
1442 ol_flags = m->ol_flags;
1445 * m->nb_segs is uint8_t, so nb_segs is always less than
1447 * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1449 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1450 if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1451 rte_errno = -EINVAL;
1454 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1455 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1456 /* MSS outside the range (256B - 9674B) are considered
1459 rte_errno = -EINVAL;
1463 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1464 rte_errno = -ENOTSUP;
1468 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1469 ret = rte_validate_tx_offload(m);
1475 ret = rte_net_intel_cksum_prepare(m);
1485 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1486 * application used, which assume having sequential ones. But from driver's
1487 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1488 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1489 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1490 * use queue_idx from 0 to 95 to access queues, while real queue would be
1491 * different. This function will do a queue mapping to find VSI the queue
1494 static struct i40e_vsi*
1495 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1497 /* the queue in MAIN VSI range */
1498 if (queue_idx < pf->main_vsi->nb_qps)
1499 return pf->main_vsi;
1501 queue_idx -= pf->main_vsi->nb_qps;
1503 /* queue_idx is greater than VMDQ VSIs range */
1504 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1505 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1509 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1513 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1515 /* the queue in MAIN VSI range */
1516 if (queue_idx < pf->main_vsi->nb_qps)
1519 /* It's VMDQ queues */
1520 queue_idx -= pf->main_vsi->nb_qps;
1522 if (pf->nb_cfg_vmdq_vsi)
1523 return queue_idx % pf->vmdq_nb_qps;
1525 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1526 return (uint16_t)(-1);
1531 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1533 struct i40e_rx_queue *rxq;
1535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537 PMD_INIT_FUNC_TRACE();
1539 if (rx_queue_id < dev->data->nb_rx_queues) {
1540 rxq = dev->data->rx_queues[rx_queue_id];
1542 err = i40e_alloc_rx_queue_mbufs(rxq);
1544 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1550 /* Init the RX tail regieter. */
1551 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1553 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1556 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1559 i40e_rx_queue_release_mbufs(rxq);
1560 i40e_reset_rx_queue(rxq);
1562 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1569 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1571 struct i40e_rx_queue *rxq;
1573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575 if (rx_queue_id < dev->data->nb_rx_queues) {
1576 rxq = dev->data->rx_queues[rx_queue_id];
1579 * rx_queue_id is queue id aplication refers to, while
1580 * rxq->reg_idx is the real queue index.
1582 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1585 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1589 i40e_rx_queue_release_mbufs(rxq);
1590 i40e_reset_rx_queue(rxq);
1591 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1598 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1601 struct i40e_tx_queue *txq;
1602 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604 PMD_INIT_FUNC_TRACE();
1606 if (tx_queue_id < dev->data->nb_tx_queues) {
1607 txq = dev->data->tx_queues[tx_queue_id];
1610 * tx_queue_id is queue id aplication refers to, while
1611 * rxq->reg_idx is the real queue index.
1613 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1615 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1618 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1625 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1627 struct i40e_tx_queue *txq;
1629 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 if (tx_queue_id < dev->data->nb_tx_queues) {
1632 txq = dev->data->tx_queues[tx_queue_id];
1635 * tx_queue_id is queue id aplication refers to, while
1636 * txq->reg_idx is the real queue index.
1638 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1641 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1646 i40e_tx_queue_release_mbufs(txq);
1647 i40e_reset_tx_queue(txq);
1648 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1655 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1657 static const uint32_t ptypes[] = {
1658 /* refers to i40e_rxd_pkt_type_mapping() */
1660 RTE_PTYPE_L2_ETHER_TIMESYNC,
1661 RTE_PTYPE_L2_ETHER_LLDP,
1662 RTE_PTYPE_L2_ETHER_ARP,
1663 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1664 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1667 RTE_PTYPE_L4_NONFRAG,
1671 RTE_PTYPE_TUNNEL_GRENAT,
1672 RTE_PTYPE_TUNNEL_IP,
1673 RTE_PTYPE_INNER_L2_ETHER,
1674 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1675 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1676 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1677 RTE_PTYPE_INNER_L4_FRAG,
1678 RTE_PTYPE_INNER_L4_ICMP,
1679 RTE_PTYPE_INNER_L4_NONFRAG,
1680 RTE_PTYPE_INNER_L4_SCTP,
1681 RTE_PTYPE_INNER_L4_TCP,
1682 RTE_PTYPE_INNER_L4_UDP,
1686 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1687 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1688 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1690 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1691 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1692 dev->rx_pkt_burst == i40e_recv_pkts_vec)
1698 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1701 unsigned int socket_id,
1702 const struct rte_eth_rxconf *rx_conf,
1703 struct rte_mempool *mp)
1705 struct i40e_vsi *vsi;
1706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 struct i40e_adapter *ad =
1709 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1710 struct i40e_rx_queue *rxq;
1711 const struct rte_memzone *rz;
1714 uint16_t base, bsf, tc_mapping;
1715 int use_def_burst_func = 1;
1717 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1718 struct i40e_vf *vf =
1719 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1722 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1725 PMD_DRV_LOG(ERR, "VSI not available or queue "
1726 "index exceeds the maximum");
1727 return I40E_ERR_PARAM;
1729 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1730 (nb_desc > I40E_MAX_RING_DESC) ||
1731 (nb_desc < I40E_MIN_RING_DESC)) {
1732 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1733 "invalid", nb_desc);
1734 return I40E_ERR_PARAM;
1737 /* Free memory if needed */
1738 if (dev->data->rx_queues[queue_idx]) {
1739 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1740 dev->data->rx_queues[queue_idx] = NULL;
1743 /* Allocate the rx queue data structure */
1744 rxq = rte_zmalloc_socket("i40e rx queue",
1745 sizeof(struct i40e_rx_queue),
1746 RTE_CACHE_LINE_SIZE,
1749 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1750 "rx queue data structure");
1754 rxq->nb_rx_desc = nb_desc;
1755 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1756 rxq->queue_id = queue_idx;
1757 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1758 rxq->reg_idx = queue_idx;
1759 else /* PF device */
1760 rxq->reg_idx = vsi->base_queue +
1761 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1763 rxq->port_id = dev->data->port_id;
1764 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1766 rxq->drop_en = rx_conf->rx_drop_en;
1768 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1770 /* Allocate the maximun number of RX ring hardware descriptor. */
1771 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1772 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1773 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1774 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1776 i40e_dev_rx_queue_release(rxq);
1777 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1781 /* Zero all the descriptors in the ring. */
1782 memset(rz->addr, 0, ring_size);
1784 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1785 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1787 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1788 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1793 /* Allocate the software ring. */
1795 rte_zmalloc_socket("i40e rx sw ring",
1796 sizeof(struct i40e_rx_entry) * len,
1797 RTE_CACHE_LINE_SIZE,
1799 if (!rxq->sw_ring) {
1800 i40e_dev_rx_queue_release(rxq);
1801 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1805 i40e_reset_rx_queue(rxq);
1807 dev->data->rx_queues[queue_idx] = rxq;
1809 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1811 if (!use_def_burst_func) {
1812 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1813 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1814 "satisfied. Rx Burst Bulk Alloc function will be "
1815 "used on port=%d, queue=%d.",
1816 rxq->port_id, rxq->queue_id);
1817 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1819 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1820 "not satisfied, Scattered Rx is requested, "
1821 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1822 "not enabled on port=%d, queue=%d.",
1823 rxq->port_id, rxq->queue_id);
1824 ad->rx_bulk_alloc_allowed = false;
1827 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1828 if (!(vsi->enabled_tc & (1 << i)))
1830 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1831 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1832 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1833 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1834 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1836 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1844 i40e_dev_rx_queue_release(void *rxq)
1846 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1849 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1853 i40e_rx_queue_release_mbufs(q);
1854 rte_free(q->sw_ring);
1859 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1861 #define I40E_RXQ_SCAN_INTERVAL 4
1862 volatile union i40e_rx_desc *rxdp;
1863 struct i40e_rx_queue *rxq;
1866 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1867 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1871 rxq = dev->data->rx_queues[rx_queue_id];
1872 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1873 while ((desc < rxq->nb_rx_desc) &&
1874 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1875 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1876 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1878 * Check the DD bit of a rx descriptor of each 4 in a group,
1879 * to avoid checking too frequently and downgrading performance
1882 desc += I40E_RXQ_SCAN_INTERVAL;
1883 rxdp += I40E_RXQ_SCAN_INTERVAL;
1884 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1885 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1886 desc - rxq->nb_rx_desc]);
1893 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1895 volatile union i40e_rx_desc *rxdp;
1896 struct i40e_rx_queue *rxq = rx_queue;
1900 if (unlikely(offset >= rxq->nb_rx_desc)) {
1901 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1905 desc = rxq->rx_tail + offset;
1906 if (desc >= rxq->nb_rx_desc)
1907 desc -= rxq->nb_rx_desc;
1909 rxdp = &(rxq->rx_ring[desc]);
1911 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1912 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1913 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1919 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1922 unsigned int socket_id,
1923 const struct rte_eth_txconf *tx_conf)
1925 struct i40e_vsi *vsi;
1926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928 struct i40e_tx_queue *txq;
1929 const struct rte_memzone *tz;
1931 uint16_t tx_rs_thresh, tx_free_thresh;
1932 uint16_t i, base, bsf, tc_mapping;
1934 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1935 struct i40e_vf *vf =
1936 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1939 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1942 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1943 "exceeds the maximum", queue_idx);
1944 return I40E_ERR_PARAM;
1947 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1948 (nb_desc > I40E_MAX_RING_DESC) ||
1949 (nb_desc < I40E_MIN_RING_DESC)) {
1950 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1951 "invalid", nb_desc);
1952 return I40E_ERR_PARAM;
1956 * The following two parameters control the setting of the RS bit on
1957 * transmit descriptors. TX descriptors will have their RS bit set
1958 * after txq->tx_rs_thresh descriptors have been used. The TX
1959 * descriptor ring will be cleaned after txq->tx_free_thresh
1960 * descriptors are used or if the number of descriptors required to
1961 * transmit a packet is greater than the number of free TX descriptors.
1963 * The following constraints must be satisfied:
1964 * - tx_rs_thresh must be greater than 0.
1965 * - tx_rs_thresh must be less than the size of the ring minus 2.
1966 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1967 * - tx_rs_thresh must be a divisor of the ring size.
1968 * - tx_free_thresh must be greater than 0.
1969 * - tx_free_thresh must be less than the size of the ring minus 3.
1971 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1972 * race condition, hence the maximum threshold constraints. When set
1973 * to zero use default values.
1975 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1976 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1977 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1978 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1979 if (tx_rs_thresh >= (nb_desc - 2)) {
1980 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1981 "number of TX descriptors minus 2. "
1982 "(tx_rs_thresh=%u port=%d queue=%d)",
1983 (unsigned int)tx_rs_thresh,
1984 (int)dev->data->port_id,
1986 return I40E_ERR_PARAM;
1988 if (tx_free_thresh >= (nb_desc - 3)) {
1989 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1990 "number of TX descriptors minus 3. "
1991 "(tx_free_thresh=%u port=%d queue=%d)",
1992 (unsigned int)tx_free_thresh,
1993 (int)dev->data->port_id,
1995 return I40E_ERR_PARAM;
1997 if (tx_rs_thresh > tx_free_thresh) {
1998 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1999 "equal to tx_free_thresh. (tx_free_thresh=%u"
2000 " tx_rs_thresh=%u port=%d queue=%d)",
2001 (unsigned int)tx_free_thresh,
2002 (unsigned int)tx_rs_thresh,
2003 (int)dev->data->port_id,
2005 return I40E_ERR_PARAM;
2007 if ((nb_desc % tx_rs_thresh) != 0) {
2008 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2009 "number of TX descriptors. (tx_rs_thresh=%u"
2010 " port=%d queue=%d)",
2011 (unsigned int)tx_rs_thresh,
2012 (int)dev->data->port_id,
2014 return I40E_ERR_PARAM;
2016 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2017 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2018 "tx_rs_thresh is greater than 1. "
2019 "(tx_rs_thresh=%u port=%d queue=%d)",
2020 (unsigned int)tx_rs_thresh,
2021 (int)dev->data->port_id,
2023 return I40E_ERR_PARAM;
2026 /* Free memory if needed. */
2027 if (dev->data->tx_queues[queue_idx]) {
2028 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2029 dev->data->tx_queues[queue_idx] = NULL;
2032 /* Allocate the TX queue data structure. */
2033 txq = rte_zmalloc_socket("i40e tx queue",
2034 sizeof(struct i40e_tx_queue),
2035 RTE_CACHE_LINE_SIZE,
2038 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2039 "tx queue structure");
2043 /* Allocate TX hardware ring descriptors. */
2044 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2045 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2046 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2047 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2049 i40e_dev_tx_queue_release(txq);
2050 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2054 txq->nb_tx_desc = nb_desc;
2055 txq->tx_rs_thresh = tx_rs_thresh;
2056 txq->tx_free_thresh = tx_free_thresh;
2057 txq->pthresh = tx_conf->tx_thresh.pthresh;
2058 txq->hthresh = tx_conf->tx_thresh.hthresh;
2059 txq->wthresh = tx_conf->tx_thresh.wthresh;
2060 txq->queue_id = queue_idx;
2061 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2062 txq->reg_idx = queue_idx;
2063 else /* PF device */
2064 txq->reg_idx = vsi->base_queue +
2065 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2067 txq->port_id = dev->data->port_id;
2068 txq->txq_flags = tx_conf->txq_flags;
2070 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2072 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2073 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2075 /* Allocate software ring */
2077 rte_zmalloc_socket("i40e tx sw ring",
2078 sizeof(struct i40e_tx_entry) * nb_desc,
2079 RTE_CACHE_LINE_SIZE,
2081 if (!txq->sw_ring) {
2082 i40e_dev_tx_queue_release(txq);
2083 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2087 i40e_reset_tx_queue(txq);
2089 dev->data->tx_queues[queue_idx] = txq;
2091 /* Use a simple TX queue without offloads or multi segs if possible */
2092 i40e_set_tx_function_flag(dev, txq);
2094 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2095 if (!(vsi->enabled_tc & (1 << i)))
2097 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2098 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2099 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2100 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2101 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2103 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2111 i40e_dev_tx_queue_release(void *txq)
2113 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2116 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2120 i40e_tx_queue_release_mbufs(q);
2121 rte_free(q->sw_ring);
2125 const struct rte_memzone *
2126 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2128 const struct rte_memzone *mz;
2130 mz = rte_memzone_lookup(name);
2134 if (rte_xen_dom0_supported())
2135 mz = rte_memzone_reserve_bounded(name, len,
2136 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2138 mz = rte_memzone_reserve_aligned(name, len,
2139 socket_id, 0, I40E_RING_BASE_ALIGN);
2144 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2148 /* SSE Vector driver has a different way of releasing mbufs. */
2149 if (rxq->rx_using_sse) {
2150 i40e_rx_queue_release_mbufs_vec(rxq);
2154 if (!rxq->sw_ring) {
2155 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2159 for (i = 0; i < rxq->nb_rx_desc; i++) {
2160 if (rxq->sw_ring[i].mbuf) {
2161 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2162 rxq->sw_ring[i].mbuf = NULL;
2165 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2166 if (rxq->rx_nb_avail == 0)
2168 for (i = 0; i < rxq->rx_nb_avail; i++) {
2169 struct rte_mbuf *mbuf;
2171 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2172 rte_pktmbuf_free_seg(mbuf);
2174 rxq->rx_nb_avail = 0;
2175 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2179 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2185 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2189 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2190 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2191 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2193 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2194 len = rxq->nb_rx_desc;
2196 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2197 ((volatile char *)rxq->rx_ring)[i] = 0;
2199 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2200 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2201 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2202 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2204 rxq->rx_nb_avail = 0;
2205 rxq->rx_next_avail = 0;
2206 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2207 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2209 rxq->nb_rx_hold = 0;
2210 rxq->pkt_first_seg = NULL;
2211 rxq->pkt_last_seg = NULL;
2213 rxq->rxrearm_start = 0;
2214 rxq->rxrearm_nb = 0;
2218 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2222 if (!txq || !txq->sw_ring) {
2223 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2227 for (i = 0; i < txq->nb_tx_desc; i++) {
2228 if (txq->sw_ring[i].mbuf) {
2229 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2230 txq->sw_ring[i].mbuf = NULL;
2236 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2238 struct i40e_tx_entry *txe;
2239 uint16_t i, prev, size;
2242 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2247 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2248 for (i = 0; i < size; i++)
2249 ((volatile char *)txq->tx_ring)[i] = 0;
2251 prev = (uint16_t)(txq->nb_tx_desc - 1);
2252 for (i = 0; i < txq->nb_tx_desc; i++) {
2253 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2255 txd->cmd_type_offset_bsz =
2256 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2259 txe[prev].next_id = i;
2263 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2264 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2267 txq->nb_tx_used = 0;
2269 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2270 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2273 /* Init the TX queue in hardware */
2275 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2277 enum i40e_status_code err = I40E_SUCCESS;
2278 struct i40e_vsi *vsi = txq->vsi;
2279 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2280 uint16_t pf_q = txq->reg_idx;
2281 struct i40e_hmc_obj_txq tx_ctx;
2284 /* clear the context structure first */
2285 memset(&tx_ctx, 0, sizeof(tx_ctx));
2286 tx_ctx.new_context = 1;
2287 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2288 tx_ctx.qlen = txq->nb_tx_desc;
2290 #ifdef RTE_LIBRTE_IEEE1588
2291 tx_ctx.timesync_ena = 1;
2293 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2294 if (vsi->type == I40E_VSI_FDIR)
2295 tx_ctx.fd_ena = TRUE;
2297 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2298 if (err != I40E_SUCCESS) {
2299 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2303 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2304 if (err != I40E_SUCCESS) {
2305 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2309 /* Now associate this queue with this PCI function */
2310 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2311 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2312 I40E_QTX_CTL_PF_INDX_MASK);
2313 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2314 I40E_WRITE_FLUSH(hw);
2316 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2322 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2324 struct i40e_rx_entry *rxe = rxq->sw_ring;
2328 for (i = 0; i < rxq->nb_rx_desc; i++) {
2329 volatile union i40e_rx_desc *rxd;
2330 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2332 if (unlikely(!mbuf)) {
2333 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2337 rte_mbuf_refcnt_set(mbuf, 1);
2339 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2341 mbuf->port = rxq->port_id;
2344 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2346 rxd = &rxq->rx_ring[i];
2347 rxd->read.pkt_addr = dma_addr;
2348 rxd->read.hdr_addr = 0;
2349 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2350 rxd->read.rsvd1 = 0;
2351 rxd->read.rsvd2 = 0;
2352 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2361 * Calculate the buffer length, and check the jumbo frame
2362 * and maximum packet length.
2365 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2367 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2368 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2369 struct rte_eth_dev_data *data = pf->dev_data;
2370 uint16_t buf_size, len;
2372 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2373 RTE_PKTMBUF_HEADROOM);
2375 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2376 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2377 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2378 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2379 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2380 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2381 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2382 rxq->hs_mode = i40e_header_split_enabled;
2384 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2386 rxq->rx_hdr_len = 0;
2387 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2388 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2389 rxq->hs_mode = i40e_header_split_none;
2393 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2394 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2395 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2396 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2397 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2398 PMD_DRV_LOG(ERR, "maximum packet length must "
2399 "be larger than %u and smaller than %u,"
2400 "as jumbo frame is enabled",
2401 (uint32_t)ETHER_MAX_LEN,
2402 (uint32_t)I40E_FRAME_SIZE_MAX);
2403 return I40E_ERR_CONFIG;
2406 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2407 rxq->max_pkt_len > ETHER_MAX_LEN) {
2408 PMD_DRV_LOG(ERR, "maximum packet length must be "
2409 "larger than %u and smaller than %u, "
2410 "as jumbo frame is disabled",
2411 (uint32_t)ETHER_MIN_LEN,
2412 (uint32_t)ETHER_MAX_LEN);
2413 return I40E_ERR_CONFIG;
2420 /* Init the RX queue in hardware */
2422 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2424 int err = I40E_SUCCESS;
2425 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2426 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2427 uint16_t pf_q = rxq->reg_idx;
2429 struct i40e_hmc_obj_rxq rx_ctx;
2431 err = i40e_rx_queue_config(rxq);
2433 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2437 /* Clear the context structure first */
2438 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2439 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2440 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2442 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2443 rx_ctx.qlen = rxq->nb_rx_desc;
2444 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2447 rx_ctx.dtype = rxq->hs_mode;
2449 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2451 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2452 rx_ctx.rxmax = rxq->max_pkt_len;
2453 rx_ctx.tphrdesc_ena = 1;
2454 rx_ctx.tphwdesc_ena = 1;
2455 rx_ctx.tphdata_ena = 1;
2456 rx_ctx.tphhead_ena = 1;
2457 rx_ctx.lrxqthresh = 2;
2458 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2460 /* showiv indicates if inner VLAN is stripped inside of tunnel
2461 * packet. When set it to 1, vlan information is stripped from
2462 * the inner header, but the hardware does not put it in the
2463 * descriptor. So set it zero by default.
2468 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2469 if (err != I40E_SUCCESS) {
2470 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2473 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2474 if (err != I40E_SUCCESS) {
2475 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2479 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2481 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2482 RTE_PKTMBUF_HEADROOM);
2484 /* Check if scattered RX needs to be used. */
2485 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2486 dev_data->scattered_rx = 1;
2489 /* Init the RX tail regieter. */
2490 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2496 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2500 PMD_INIT_FUNC_TRACE();
2502 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2503 if (!dev->data->tx_queues[i])
2505 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2506 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2509 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2510 if (!dev->data->rx_queues[i])
2512 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2513 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2518 i40e_dev_free_queues(struct rte_eth_dev *dev)
2522 PMD_INIT_FUNC_TRACE();
2524 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2525 if (!dev->data->rx_queues[i])
2527 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2528 dev->data->rx_queues[i] = NULL;
2530 dev->data->nb_rx_queues = 0;
2532 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2533 if (!dev->data->tx_queues[i])
2535 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2536 dev->data->tx_queues[i] = NULL;
2538 dev->data->nb_tx_queues = 0;
2541 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2542 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2544 enum i40e_status_code
2545 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2547 struct i40e_tx_queue *txq;
2548 const struct rte_memzone *tz = NULL;
2550 struct rte_eth_dev *dev;
2553 PMD_DRV_LOG(ERR, "PF is not available");
2554 return I40E_ERR_BAD_PTR;
2557 dev = pf->adapter->eth_dev;
2559 /* Allocate the TX queue data structure. */
2560 txq = rte_zmalloc_socket("i40e fdir tx queue",
2561 sizeof(struct i40e_tx_queue),
2562 RTE_CACHE_LINE_SIZE,
2565 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2566 "tx queue structure.");
2567 return I40E_ERR_NO_MEMORY;
2570 /* Allocate TX hardware ring descriptors. */
2571 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2572 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2574 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2575 I40E_FDIR_QUEUE_ID, ring_size,
2576 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2578 i40e_dev_tx_queue_release(txq);
2579 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2580 return I40E_ERR_NO_MEMORY;
2583 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2584 txq->queue_id = I40E_FDIR_QUEUE_ID;
2585 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2586 txq->vsi = pf->fdir.fdir_vsi;
2588 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2589 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2591 * don't need to allocate software ring and reset for the fdir
2592 * program queue just set the queue has been configured.
2597 return I40E_SUCCESS;
2600 enum i40e_status_code
2601 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2603 struct i40e_rx_queue *rxq;
2604 const struct rte_memzone *rz = NULL;
2606 struct rte_eth_dev *dev;
2609 PMD_DRV_LOG(ERR, "PF is not available");
2610 return I40E_ERR_BAD_PTR;
2613 dev = pf->adapter->eth_dev;
2615 /* Allocate the RX queue data structure. */
2616 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2617 sizeof(struct i40e_rx_queue),
2618 RTE_CACHE_LINE_SIZE,
2621 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2622 "rx queue structure.");
2623 return I40E_ERR_NO_MEMORY;
2626 /* Allocate RX hardware ring descriptors. */
2627 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2628 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2630 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2631 I40E_FDIR_QUEUE_ID, ring_size,
2632 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2634 i40e_dev_rx_queue_release(rxq);
2635 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2636 return I40E_ERR_NO_MEMORY;
2639 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2640 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2641 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2642 rxq->vsi = pf->fdir.fdir_vsi;
2644 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2645 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2648 * Don't need to allocate software ring and reset for the fdir
2649 * rx queue, just set the queue has been configured.
2654 return I40E_SUCCESS;
2658 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2659 struct rte_eth_rxq_info *qinfo)
2661 struct i40e_rx_queue *rxq;
2663 rxq = dev->data->rx_queues[queue_id];
2665 qinfo->mp = rxq->mp;
2666 qinfo->scattered_rx = dev->data->scattered_rx;
2667 qinfo->nb_desc = rxq->nb_rx_desc;
2669 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2670 qinfo->conf.rx_drop_en = rxq->drop_en;
2671 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2675 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2676 struct rte_eth_txq_info *qinfo)
2678 struct i40e_tx_queue *txq;
2680 txq = dev->data->tx_queues[queue_id];
2682 qinfo->nb_desc = txq->nb_tx_desc;
2684 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2685 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2686 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2688 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2689 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2690 qinfo->conf.txq_flags = txq->txq_flags;
2691 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2694 void __attribute__((cold))
2695 i40e_set_rx_function(struct rte_eth_dev *dev)
2697 struct i40e_adapter *ad =
2698 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2699 uint16_t rx_using_sse, i;
2700 /* In order to allow Vector Rx there are a few configuration
2701 * conditions to be met and Rx Bulk Allocation should be allowed.
2703 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2704 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2705 !ad->rx_bulk_alloc_allowed) {
2706 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2707 " Vector Rx preconditions",
2708 dev->data->port_id);
2710 ad->rx_vec_allowed = false;
2712 if (ad->rx_vec_allowed) {
2713 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2714 struct i40e_rx_queue *rxq =
2715 dev->data->rx_queues[i];
2717 if (rxq && i40e_rxq_vec_setup(rxq)) {
2718 ad->rx_vec_allowed = false;
2725 if (dev->data->scattered_rx) {
2726 /* Set the non-LRO scattered callback: there are Vector and
2727 * single allocation versions.
2729 if (ad->rx_vec_allowed) {
2730 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2731 "callback (port=%d).",
2732 dev->data->port_id);
2734 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2736 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2737 "allocation callback (port=%d).",
2738 dev->data->port_id);
2739 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2741 /* If parameters allow we are going to choose between the following
2745 * - Single buffer allocation (the simplest one)
2747 } else if (ad->rx_vec_allowed) {
2748 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2749 "burst size no less than %d (port=%d).",
2750 RTE_I40E_DESCS_PER_LOOP,
2751 dev->data->port_id);
2753 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2754 } else if (ad->rx_bulk_alloc_allowed) {
2755 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2756 "satisfied. Rx Burst Bulk Alloc function "
2757 "will be used on port=%d.",
2758 dev->data->port_id);
2760 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2762 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2763 "satisfied, or Scattered Rx is requested "
2765 dev->data->port_id);
2767 dev->rx_pkt_burst = i40e_recv_pkts;
2770 /* Propagate information about RX function choice through all queues. */
2771 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2773 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2774 dev->rx_pkt_burst == i40e_recv_pkts_vec);
2776 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2777 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2780 rxq->rx_using_sse = rx_using_sse;
2785 void __attribute__((cold))
2786 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2788 struct i40e_adapter *ad =
2789 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2791 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2792 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2793 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2794 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2795 PMD_INIT_LOG(DEBUG, "Vector tx"
2796 " can be enabled on this txq.");
2799 ad->tx_vec_allowed = false;
2802 ad->tx_simple_allowed = false;
2806 void __attribute__((cold))
2807 i40e_set_tx_function(struct rte_eth_dev *dev)
2809 struct i40e_adapter *ad =
2810 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2813 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2814 if (ad->tx_vec_allowed) {
2815 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2816 struct i40e_tx_queue *txq =
2817 dev->data->tx_queues[i];
2819 if (txq && i40e_txq_vec_setup(txq)) {
2820 ad->tx_vec_allowed = false;
2827 if (ad->tx_simple_allowed) {
2828 if (ad->tx_vec_allowed) {
2829 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2830 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2832 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2833 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2835 dev->tx_pkt_prepare = NULL;
2837 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2838 dev->tx_pkt_burst = i40e_xmit_pkts;
2839 dev->tx_pkt_prepare = i40e_prep_pkts;
2843 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2844 int __attribute__((weak))
2845 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2850 uint16_t __attribute__((weak))
2852 void __rte_unused *rx_queue,
2853 struct rte_mbuf __rte_unused **rx_pkts,
2854 uint16_t __rte_unused nb_pkts)
2859 uint16_t __attribute__((weak))
2860 i40e_recv_scattered_pkts_vec(
2861 void __rte_unused *rx_queue,
2862 struct rte_mbuf __rte_unused **rx_pkts,
2863 uint16_t __rte_unused nb_pkts)
2868 int __attribute__((weak))
2869 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2874 int __attribute__((weak))
2875 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2880 void __attribute__((weak))
2881 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2886 uint16_t __attribute__((weak))
2887 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2888 struct rte_mbuf __rte_unused **tx_pkts,
2889 uint16_t __rte_unused nb_pkts)