drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "i40e_logs.h"
  29 #include "base/i40e_prototype.h"
  30 #include "base/i40e_type.h"
  31 #include "i40e_ethdev.h"
  32 #include "i40e_rxtx.h"
  33
  34 #define DEFAULT_TX_RS_THRESH   32
  35 #define DEFAULT_TX_FREE_THRESH 32
  36
  37 #define I40E_TX_MAX_BURST  32
  38
  39 #define I40E_DMA_MEM_ALIGN 4096
  40
  41 /* Base address of the HW descriptor ring should be 128B aligned. */
  42 #define I40E_RING_BASE_ALIGN    128
  43
  44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  45
  46 #ifdef RTE_LIBRTE_IEEE1588
  47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  48 #else
  49 #define I40E_TX_IEEE1588_TMST 0
  50 #endif
  51
  52 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG |                 \
  56                 PKT_TX_OUTER_IP_CKSUM)
  57
  58 #define I40E_TX_OFFLOAD_MASK (  \
  59                 PKT_TX_OUTER_IPV4 |     \
  60                 PKT_TX_OUTER_IPV6 |     \
  61                 PKT_TX_IPV4 |           \
  62                 PKT_TX_IPV6 |           \
  63                 PKT_TX_IP_CKSUM |       \
  64                 PKT_TX_L4_MASK |        \
  65                 PKT_TX_OUTER_IP_CKSUM | \
  66                 PKT_TX_TCP_SEG |        \
  67                 PKT_TX_QINQ_PKT |       \
  68                 PKT_TX_VLAN_PKT |       \
  69                 PKT_TX_TUNNEL_MASK |    \
  70                 I40E_TX_IEEE1588_TMST)
  71
  72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  73                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  74
  75 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK ( \
  76                 PKT_TX_IPV4 | \
  77                 PKT_TX_IPV6 | \
  78                 PKT_TX_OUTER_IPV4 | \
  79                 PKT_TX_OUTER_IPV6)
  80
  81 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
  82                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
  83
  84 int
  85 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  86 {
  87         struct i40e_rx_queue *rxq = rx_queue;
  88         volatile union i40e_rx_desc *rxdp;
  89         uint16_t desc;
  90
  91         desc = rxq->rx_tail;
  92         rxdp = &rxq->rx_ring[desc];
  93         /* watch for changes in status bit */
  94         pmc->addr = &rxdp->wb.qword1.status_error_len;
  95
  96         /*
  97          * we expect the DD bit to be set to 1 if this descriptor was already
  98          * written to.
  99          */
 100         pmc->val = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 101         pmc->mask = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 102
 103         /* registers are 64-bit */
 104         pmc->size = sizeof(uint64_t);
 105
 106         return 0;
 107 }
 108
 109 static inline void
 110 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 111 {
 112         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 113                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 114                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 115                 mb->vlan_tci =
 116                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 117                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 118                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 119         } else {
 120                 mb->vlan_tci = 0;
 121         }
 122 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 123         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 124                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 125                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
 126                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
 127                 mb->vlan_tci_outer = mb->vlan_tci;
 128                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 129                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 130                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 131                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 132         } else {
 133                 mb->vlan_tci_outer = 0;
 134         }
 135 #endif
 136         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 137                    mb->vlan_tci, mb->vlan_tci_outer);
 138 }
 139
 140 /* Translate the rx descriptor status to pkt flags */
 141 static inline uint64_t
 142 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 143 {
 144         uint64_t flags;
 145
 146         /* Check if RSS_HASH */
 147         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 148                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 149                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 150
 151         /* Check if FDIR Match */
 152         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 153                                                         PKT_RX_FDIR : 0);
 154
 155         return flags;
 156 }
 157
 158 static inline uint64_t
 159 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 160 {
 161         uint64_t flags = 0;
 162         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 163
 164 #define I40E_RX_ERR_BITS 0x3f
 165         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 166                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 167                 return flags;
 168         }
 169
 170         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 171                 flags |= PKT_RX_IP_CKSUM_BAD;
 172         else
 173                 flags |= PKT_RX_IP_CKSUM_GOOD;
 174
 175         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 176                 flags |= PKT_RX_L4_CKSUM_BAD;
 177         else
 178                 flags |= PKT_RX_L4_CKSUM_GOOD;
 179
 180         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 181                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
 182
 183         return flags;
 184 }
 185
 186 /* Function to check and set the ieee1588 timesync index and get the
 187  * appropriate flags.
 188  */
 189 #ifdef RTE_LIBRTE_IEEE1588
 190 static inline uint64_t
 191 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 192 {
 193         uint64_t pkt_flags = 0;
 194         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 195                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 196                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 197
 198         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 199                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 200                 pkt_flags = PKT_RX_IEEE1588_PTP;
 201         if (tsyn & 0x04) {
 202                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 203                 mb->timesync = tsyn & 0x03;
 204         }
 205
 206         return pkt_flags;
 207 }
 208 #endif
 209
 210 static inline uint64_t
 211 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 212 {
 213         uint64_t flags = 0;
 214 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 215         uint16_t flexbh, flexbl;
 216
 217         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 218                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 219                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 220         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 221                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 222                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 223
 224
 225         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 226                 mb->hash.fdir.hi =
 227                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 228                 flags |= PKT_RX_FDIR_ID;
 229         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 230                 mb->hash.fdir.hi =
 231                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 232                 flags |= PKT_RX_FDIR_FLX;
 233         }
 234         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 235                 mb->hash.fdir.lo =
 236                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 237                 flags |= PKT_RX_FDIR_FLX;
 238         }
 239 #else
 240         mb->hash.fdir.hi =
 241                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 242         flags |= PKT_RX_FDIR_ID;
 243 #endif
 244         return flags;
 245 }
 246
 247 static inline void
 248 i40e_parse_tunneling_params(uint64_t ol_flags,
 249                             union i40e_tx_offload tx_offload,
 250                             uint32_t *cd_tunneling)
 251 {
 252         /* EIPT: External (outer) IP header type */
 253         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 254                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 255         else if (ol_flags & PKT_TX_OUTER_IPV4)
 256                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 257         else if (ol_flags & PKT_TX_OUTER_IPV6)
 258                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 259
 260         /* EIPLEN: External (outer) IP header length, in DWords */
 261         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 262                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 263
 264         /* L4TUNT: L4 Tunneling Type */
 265         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 266         case PKT_TX_TUNNEL_IPIP:
 267                 /* for non UDP / GRE tunneling, set to 00b */
 268                 break;
 269         case PKT_TX_TUNNEL_VXLAN:
 270         case PKT_TX_TUNNEL_GENEVE:
 271                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 272                 break;
 273         case PKT_TX_TUNNEL_GRE:
 274                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 275                 break;
 276         default:
 277                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 278                 return;
 279         }
 280
 281         /* L4TUNLEN: L4 Tunneling Length, in Words
 282          *
 283          * We depend on app to set rte_mbuf.l2_len correctly.
 284          * For IP in GRE it should be set to the length of the GRE
 285          * header;
 286          * for MAC in GRE or MAC in UDP it should be set to the length
 287          * of the GRE or UDP headers plus the inner MAC up to including
 288          * its last Ethertype.
 289          */
 290         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 291                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 292 }
 293
 294 static inline void
 295 i40e_txd_enable_checksum(uint64_t ol_flags,
 296                         uint32_t *td_cmd,
 297                         uint32_t *td_offset,
 298                         union i40e_tx_offload tx_offload)
 299 {
 300         /* Set MACLEN */
 301         if (ol_flags & PKT_TX_TUNNEL_MASK)
 302                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 303                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 304         else
 305                 *td_offset |= (tx_offload.l2_len >> 1)
 306                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 307
 308         /* Enable L3 checksum offloads */
 309         if (ol_flags & PKT_TX_IP_CKSUM) {
 310                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 311                 *td_offset |= (tx_offload.l3_len >> 2)
 312                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 313         } else if (ol_flags & PKT_TX_IPV4) {
 314                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 315                 *td_offset |= (tx_offload.l3_len >> 2)
 316                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 317         } else if (ol_flags & PKT_TX_IPV6) {
 318                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 319                 *td_offset |= (tx_offload.l3_len >> 2)
 320                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 321         }
 322
 323         if (ol_flags & PKT_TX_TCP_SEG) {
 324                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 325                 *td_offset |= (tx_offload.l4_len >> 2)
 326                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 327                 return;
 328         }
 329
 330         /* Enable L4 checksum offloads */
 331         switch (ol_flags & PKT_TX_L4_MASK) {
 332         case PKT_TX_TCP_CKSUM:
 333                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 334                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 335                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 336                 break;
 337         case PKT_TX_SCTP_CKSUM:
 338                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 339                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 340                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 341                 break;
 342         case PKT_TX_UDP_CKSUM:
 343                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 344                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 345                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 346                 break;
 347         default:
 348                 break;
 349         }
 350 }
 351
 352 /* Construct the tx flags */
 353 static inline uint64_t
 354 i40e_build_ctob(uint32_t td_cmd,
 355                 uint32_t td_offset,
 356                 unsigned int size,
 357                 uint32_t td_tag)
 358 {
 359         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 360                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 361                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 362                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 363                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 364 }
 365
 366 static inline int
 367 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 368 {
 369         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 370         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 371         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 372         uint16_t nb_tx_desc = txq->nb_tx_desc;
 373         uint16_t desc_to_clean_to;
 374         uint16_t nb_tx_to_clean;
 375
 376         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 377         if (desc_to_clean_to >= nb_tx_desc)
 378                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 379
 380         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 381         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 382                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 383                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 384                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
 385                            "(port=%d queue=%d)", desc_to_clean_to,
 386                            txq->port_id, txq->queue_id);
 387                 return -1;
 388         }
 389
 390         if (last_desc_cleaned > desc_to_clean_to)
 391                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 392                                                         desc_to_clean_to);
 393         else
 394                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 395                                         last_desc_cleaned);
 396
 397         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 398
 399         txq->last_desc_cleaned = desc_to_clean_to;
 400         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 401
 402         return 0;
 403 }
 404
 405 static inline int
 406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 407 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 408 #else
 409 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 410 #endif
 411 {
 412         int ret = 0;
 413
 414 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 415         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 416                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 417                              "rxq->rx_free_thresh=%d, "
 418                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 419                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 420                 ret = -EINVAL;
 421         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 422                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 423                              "rxq->rx_free_thresh=%d, "
 424                              "rxq->nb_rx_desc=%d",
 425                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 426                 ret = -EINVAL;
 427         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 428                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 429                              "rxq->nb_rx_desc=%d, "
 430                              "rxq->rx_free_thresh=%d",
 431                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 432                 ret = -EINVAL;
 433         }
 434 #else
 435         ret = -EINVAL;
 436 #endif
 437
 438         return ret;
 439 }
 440
 441 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 442 #define I40E_LOOK_AHEAD 8
 443 #if (I40E_LOOK_AHEAD != 8)
 444 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 445 #endif
 446 static inline int
 447 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 448 {
 449         volatile union i40e_rx_desc *rxdp;
 450         struct i40e_rx_entry *rxep;
 451         struct rte_mbuf *mb;
 452         uint16_t pkt_len;
 453         uint64_t qword1;
 454         uint32_t rx_status;
 455         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 456         int32_t i, j, nb_rx = 0;
 457         uint64_t pkt_flags;
 458         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 459
 460         rxdp = &rxq->rx_ring[rxq->rx_tail];
 461         rxep = &rxq->sw_ring[rxq->rx_tail];
 462
 463         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 464         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 465                                 I40E_RXD_QW1_STATUS_SHIFT;
 466
 467         /* Make sure there is at least 1 packet to receive */
 468         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 469                 return 0;
 470
 471         /**
 472          * Scan LOOK_AHEAD descriptors at a time to determine which
 473          * descriptors reference packets that are ready to be received.
 474          */
 475         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 476                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 477                 /* Read desc statuses backwards to avoid race condition */
 478                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 479                         qword1 = rte_le_to_cpu_64(\
 480                                 rxdp[j].wb.qword1.status_error_len);
 481                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 482                                         I40E_RXD_QW1_STATUS_SHIFT;
 483                 }
 484
 485                 rte_smp_rmb();
 486
 487                 /* Compute how many status bits were set */
 488                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 489                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 490
 491                 nb_rx += nb_dd;
 492
 493                 /* Translate descriptor info to mbuf parameters */
 494                 for (j = 0; j < nb_dd; j++) {
 495                         mb = rxep[j].mbuf;
 496                         qword1 = rte_le_to_cpu_64(\
 497                                 rxdp[j].wb.qword1.status_error_len);
 498                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 499                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 500                         mb->data_len = pkt_len;
 501                         mb->pkt_len = pkt_len;
 502                         mb->ol_flags = 0;
 503                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 504                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 505                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 506                         mb->packet_type =
 507                                 ptype_tbl[(uint8_t)((qword1 &
 508                                 I40E_RXD_QW1_PTYPE_MASK) >>
 509                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 510                         if (pkt_flags & PKT_RX_RSS_HASH)
 511                                 mb->hash.rss = rte_le_to_cpu_32(\
 512                                         rxdp[j].wb.qword0.hi_dword.rss);
 513                         if (pkt_flags & PKT_RX_FDIR)
 514                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 515
 516 #ifdef RTE_LIBRTE_IEEE1588
 517                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 518 #endif
 519                         mb->ol_flags |= pkt_flags;
 520
 521                 }
 522
 523                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 524                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 525
 526                 if (nb_dd != I40E_LOOK_AHEAD)
 527                         break;
 528         }
 529
 530         /* Clear software ring entries */
 531         for (i = 0; i < nb_rx; i++)
 532                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 533
 534         return nb_rx;
 535 }
 536
 537 static inline uint16_t
 538 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 539                         struct rte_mbuf **rx_pkts,
 540                         uint16_t nb_pkts)
 541 {
 542         uint16_t i;
 543         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 544
 545         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 546
 547         for (i = 0; i < nb_pkts; i++)
 548                 rx_pkts[i] = stage[i];
 549
 550         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 551         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 552
 553         return nb_pkts;
 554 }
 555
 556 static inline int
 557 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 558 {
 559         volatile union i40e_rx_desc *rxdp;
 560         struct i40e_rx_entry *rxep;
 561         struct rte_mbuf *mb;
 562         uint16_t alloc_idx, i;
 563         uint64_t dma_addr;
 564         int diag;
 565
 566         /* Allocate buffers in bulk */
 567         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 568                                 (rxq->rx_free_thresh - 1));
 569         rxep = &(rxq->sw_ring[alloc_idx]);
 570         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 571                                         rxq->rx_free_thresh);
 572         if (unlikely(diag != 0)) {
 573                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 574                 return -ENOMEM;
 575         }
 576
 577         rxdp = &rxq->rx_ring[alloc_idx];
 578         for (i = 0; i < rxq->rx_free_thresh; i++) {
 579                 if (likely(i < (rxq->rx_free_thresh - 1)))
 580                         /* Prefetch next mbuf */
 581                         rte_prefetch0(rxep[i + 1].mbuf);
 582
 583                 mb = rxep[i].mbuf;
 584                 rte_mbuf_refcnt_set(mb, 1);
 585                 mb->next = NULL;
 586                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 587                 mb->nb_segs = 1;
 588                 mb->port = rxq->port_id;
 589                 dma_addr = rte_cpu_to_le_64(\
 590                         rte_mbuf_data_iova_default(mb));
 591                 rxdp[i].read.hdr_addr = 0;
 592                 rxdp[i].read.pkt_addr = dma_addr;
 593         }
 594
 595         /* Update rx tail regsiter */
 596         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 597
 598         rxq->rx_free_trigger =
 599                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 600         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 601                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 602
 603         return 0;
 604 }
 605
 606 static inline uint16_t
 607 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 608 {
 609         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 610         struct rte_eth_dev *dev;
 611         uint16_t nb_rx = 0;
 612
 613         if (!nb_pkts)
 614                 return 0;
 615
 616         if (rxq->rx_nb_avail)
 617                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 618
 619         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 620         rxq->rx_next_avail = 0;
 621         rxq->rx_nb_avail = nb_rx;
 622         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 623
 624         if (rxq->rx_tail > rxq->rx_free_trigger) {
 625                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 626                         uint16_t i, j;
 627
 628                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 629                         dev->data->rx_mbuf_alloc_failed +=
 630                                 rxq->rx_free_thresh;
 631
 632                         rxq->rx_nb_avail = 0;
 633                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 634                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 635                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 636
 637                         return 0;
 638                 }
 639         }
 640
 641         if (rxq->rx_tail >= rxq->nb_rx_desc)
 642                 rxq->rx_tail = 0;
 643
 644         if (rxq->rx_nb_avail)
 645                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 646
 647         return 0;
 648 }
 649
 650 static uint16_t
 651 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 652                           struct rte_mbuf **rx_pkts,
 653                           uint16_t nb_pkts)
 654 {
 655         uint16_t nb_rx = 0, n, count;
 656
 657         if (unlikely(nb_pkts == 0))
 658                 return 0;
 659
 660         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 661                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 662
 663         while (nb_pkts) {
 664                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 665                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 666                 nb_rx = (uint16_t)(nb_rx + count);
 667                 nb_pkts = (uint16_t)(nb_pkts - count);
 668                 if (count < n)
 669                         break;
 670         }
 671
 672         return nb_rx;
 673 }
 674 #else
 675 static uint16_t
 676 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 677                           struct rte_mbuf __rte_unused **rx_pkts,
 678                           uint16_t __rte_unused nb_pkts)
 679 {
 680         return 0;
 681 }
 682 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 683
 684 uint16_t
 685 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 686 {
 687         struct i40e_rx_queue *rxq;
 688         volatile union i40e_rx_desc *rx_ring;
 689         volatile union i40e_rx_desc *rxdp;
 690         union i40e_rx_desc rxd;
 691         struct i40e_rx_entry *sw_ring;
 692         struct i40e_rx_entry *rxe;
 693         struct rte_eth_dev *dev;
 694         struct rte_mbuf *rxm;
 695         struct rte_mbuf *nmb;
 696         uint16_t nb_rx;
 697         uint32_t rx_status;
 698         uint64_t qword1;
 699         uint16_t rx_packet_len;
 700         uint16_t rx_id, nb_hold;
 701         uint64_t dma_addr;
 702         uint64_t pkt_flags;
 703         uint32_t *ptype_tbl;
 704
 705         nb_rx = 0;
 706         nb_hold = 0;
 707         rxq = rx_queue;
 708         rx_id = rxq->rx_tail;
 709         rx_ring = rxq->rx_ring;
 710         sw_ring = rxq->sw_ring;
 711         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 712
 713         while (nb_rx < nb_pkts) {
 714                 rxdp = &rx_ring[rx_id];
 715                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 716                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 717                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 718
 719                 /* Check the DD bit first */
 720                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 721                         break;
 722
 723                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 724                 if (unlikely(!nmb)) {
 725                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 726                         dev->data->rx_mbuf_alloc_failed++;
 727                         break;
 728                 }
 729
 730                 rxd = *rxdp;
 731                 nb_hold++;
 732                 rxe = &sw_ring[rx_id];
 733                 rx_id++;
 734                 if (unlikely(rx_id == rxq->nb_rx_desc))
 735                         rx_id = 0;
 736
 737                 /* Prefetch next mbuf */
 738                 rte_prefetch0(sw_ring[rx_id].mbuf);
 739
 740                 /**
 741                  * When next RX descriptor is on a cache line boundary,
 742                  * prefetch the next 4 RX descriptors and next 8 pointers
 743                  * to mbufs.
 744                  */
 745                 if ((rx_id & 0x3) == 0) {
 746                         rte_prefetch0(&rx_ring[rx_id]);
 747                         rte_prefetch0(&sw_ring[rx_id]);
 748                 }
 749                 rxm = rxe->mbuf;
 750                 rxe->mbuf = nmb;
 751                 dma_addr =
 752                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 753                 rxdp->read.hdr_addr = 0;
 754                 rxdp->read.pkt_addr = dma_addr;
 755
 756                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 757                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 758
 759                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 760                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 761                 rxm->nb_segs = 1;
 762                 rxm->next = NULL;
 763                 rxm->pkt_len = rx_packet_len;
 764                 rxm->data_len = rx_packet_len;
 765                 rxm->port = rxq->port_id;
 766                 rxm->ol_flags = 0;
 767                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 768                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 769                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 770                 rxm->packet_type =
 771                         ptype_tbl[(uint8_t)((qword1 &
 772                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 773                 if (pkt_flags & PKT_RX_RSS_HASH)
 774                         rxm->hash.rss =
 775                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 776                 if (pkt_flags & PKT_RX_FDIR)
 777                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 778
 779 #ifdef RTE_LIBRTE_IEEE1588
 780                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 781 #endif
 782                 rxm->ol_flags |= pkt_flags;
 783
 784                 rx_pkts[nb_rx++] = rxm;
 785         }
 786         rxq->rx_tail = rx_id;
 787
 788         /**
 789          * If the number of free RX descriptors is greater than the RX free
 790          * threshold of the queue, advance the receive tail register of queue.
 791          * Update that register with the value of the last processed RX
 792          * descriptor minus 1.
 793          */
 794         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 795         if (nb_hold > rxq->rx_free_thresh) {
 796                 rx_id = (uint16_t) ((rx_id == 0) ?
 797                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 798                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 799                 nb_hold = 0;
 800         }
 801         rxq->nb_rx_hold = nb_hold;
 802
 803         return nb_rx;
 804 }
 805
 806 uint16_t
 807 i40e_recv_scattered_pkts(void *rx_queue,
 808                          struct rte_mbuf **rx_pkts,
 809                          uint16_t nb_pkts)
 810 {
 811         struct i40e_rx_queue *rxq = rx_queue;
 812         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 813         volatile union i40e_rx_desc *rxdp;
 814         union i40e_rx_desc rxd;
 815         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 816         struct i40e_rx_entry *rxe;
 817         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 818         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 819         struct rte_mbuf *nmb, *rxm;
 820         uint16_t rx_id = rxq->rx_tail;
 821         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 822         struct rte_eth_dev *dev;
 823         uint32_t rx_status;
 824         uint64_t qword1;
 825         uint64_t dma_addr;
 826         uint64_t pkt_flags;
 827         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 828
 829         while (nb_rx < nb_pkts) {
 830                 rxdp = &rx_ring[rx_id];
 831                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 832                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 833                                         I40E_RXD_QW1_STATUS_SHIFT;
 834
 835                 /* Check the DD bit */
 836                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 837                         break;
 838
 839                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 840                 if (unlikely(!nmb)) {
 841                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 842                         dev->data->rx_mbuf_alloc_failed++;
 843                         break;
 844                 }
 845
 846                 rxd = *rxdp;
 847                 nb_hold++;
 848                 rxe = &sw_ring[rx_id];
 849                 rx_id++;
 850                 if (rx_id == rxq->nb_rx_desc)
 851                         rx_id = 0;
 852
 853                 /* Prefetch next mbuf */
 854                 rte_prefetch0(sw_ring[rx_id].mbuf);
 855
 856                 /**
 857                  * When next RX descriptor is on a cache line boundary,
 858                  * prefetch the next 4 RX descriptors and next 8 pointers
 859                  * to mbufs.
 860                  */
 861                 if ((rx_id & 0x3) == 0) {
 862                         rte_prefetch0(&rx_ring[rx_id]);
 863                         rte_prefetch0(&sw_ring[rx_id]);
 864                 }
 865
 866                 rxm = rxe->mbuf;
 867                 rxe->mbuf = nmb;
 868                 dma_addr =
 869                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 870
 871                 /* Set data buffer address and data length of the mbuf */
 872                 rxdp->read.hdr_addr = 0;
 873                 rxdp->read.pkt_addr = dma_addr;
 874                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 875                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 876                 rxm->data_len = rx_packet_len;
 877                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 878
 879                 /**
 880                  * If this is the first buffer of the received packet, set the
 881                  * pointer to the first mbuf of the packet and initialize its
 882                  * context. Otherwise, update the total length and the number
 883                  * of segments of the current scattered packet, and update the
 884                  * pointer to the last mbuf of the current packet.
 885                  */
 886                 if (!first_seg) {
 887                         first_seg = rxm;
 888                         first_seg->nb_segs = 1;
 889                         first_seg->pkt_len = rx_packet_len;
 890                 } else {
 891                         first_seg->pkt_len =
 892                                 (uint16_t)(first_seg->pkt_len +
 893                                                 rx_packet_len);
 894                         first_seg->nb_segs++;
 895                         last_seg->next = rxm;
 896                 }
 897
 898                 /**
 899                  * If this is not the last buffer of the received packet,
 900                  * update the pointer to the last mbuf of the current scattered
 901                  * packet and continue to parse the RX ring.
 902                  */
 903                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 904                         last_seg = rxm;
 905                         continue;
 906                 }
 907
 908                 /**
 909                  * This is the last buffer of the received packet. If the CRC
 910                  * is not stripped by the hardware:
 911                  *  - Subtract the CRC length from the total packet length.
 912                  *  - If the last buffer only contains the whole CRC or a part
 913                  *  of it, free the mbuf associated to the last buffer. If part
 914                  *  of the CRC is also contained in the previous mbuf, subtract
 915                  *  the length of that CRC part from the data length of the
 916                  *  previous mbuf.
 917                  */
 918                 rxm->next = NULL;
 919                 if (unlikely(rxq->crc_len > 0)) {
 920                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 921                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 922                                 rte_pktmbuf_free_seg(rxm);
 923                                 first_seg->nb_segs--;
 924                                 last_seg->data_len =
 925                                         (uint16_t)(last_seg->data_len -
 926                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 927                                 last_seg->next = NULL;
 928                         } else
 929                                 rxm->data_len = (uint16_t)(rx_packet_len -
 930                                                         RTE_ETHER_CRC_LEN);
 931                 }
 932
 933                 first_seg->port = rxq->port_id;
 934                 first_seg->ol_flags = 0;
 935                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 936                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 937                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 938                 first_seg->packet_type =
 939                         ptype_tbl[(uint8_t)((qword1 &
 940                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 941                 if (pkt_flags & PKT_RX_RSS_HASH)
 942                         first_seg->hash.rss =
 943                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 944                 if (pkt_flags & PKT_RX_FDIR)
 945                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 946
 947 #ifdef RTE_LIBRTE_IEEE1588
 948                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 949 #endif
 950                 first_seg->ol_flags |= pkt_flags;
 951
 952                 /* Prefetch data of first segment, if configured to do so. */
 953                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 954                         first_seg->data_off));
 955                 rx_pkts[nb_rx++] = first_seg;
 956                 first_seg = NULL;
 957         }
 958
 959         /* Record index of the next RX descriptor to probe. */
 960         rxq->rx_tail = rx_id;
 961         rxq->pkt_first_seg = first_seg;
 962         rxq->pkt_last_seg = last_seg;
 963
 964         /**
 965          * If the number of free RX descriptors is greater than the RX free
 966          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 967          * register. Update the RDT with the value of the last processed RX
 968          * descriptor minus 1, to guarantee that the RDT register is never
 969          * equal to the RDH register, which creates a "full" ring situtation
 970          * from the hardware point of view.
 971          */
 972         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 973         if (nb_hold > rxq->rx_free_thresh) {
 974                 rx_id = (uint16_t)(rx_id == 0 ?
 975                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 976                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 977                 nb_hold = 0;
 978         }
 979         rxq->nb_rx_hold = nb_hold;
 980
 981         return nb_rx;
 982 }
 983
 984 /* Check if the context descriptor is needed for TX offloading */
 985 static inline uint16_t
 986 i40e_calc_context_desc(uint64_t flags)
 987 {
 988         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 989                 PKT_TX_TCP_SEG |
 990                 PKT_TX_QINQ_PKT |
 991                 PKT_TX_TUNNEL_MASK;
 992
 993 #ifdef RTE_LIBRTE_IEEE1588
 994         mask |= PKT_TX_IEEE1588_TMST;
 995 #endif
 996
 997         return (flags & mask) ? 1 : 0;
 998 }
 999
1000 /* set i40e TSO context descriptor */
1001 static inline uint64_t
1002 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1003 {
1004         uint64_t ctx_desc = 0;
1005         uint32_t cd_cmd, hdr_len, cd_tso_len;
1006
1007         if (!tx_offload.l4_len) {
1008                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1009                 return ctx_desc;
1010         }
1011
1012         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1013         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1014                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1015
1016         cd_cmd = I40E_TX_CTX_DESC_TSO;
1017         cd_tso_len = mbuf->pkt_len - hdr_len;
1018         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1019                 ((uint64_t)cd_tso_len <<
1020                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1021                 ((uint64_t)mbuf->tso_segsz <<
1022                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1023
1024         return ctx_desc;
1025 }
1026
1027 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1028 #define I40E_MAX_DATA_PER_TXD \
1029         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1030 /* Calculate the number of TX descriptors needed for each pkt */
1031 static inline uint16_t
1032 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1033 {
1034         struct rte_mbuf *txd = tx_pkt;
1035         uint16_t count = 0;
1036
1037         while (txd != NULL) {
1038                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1039                 txd = txd->next;
1040         }
1041
1042         return count;
1043 }
1044
1045 uint16_t
1046 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1047 {
1048         struct i40e_tx_queue *txq;
1049         struct i40e_tx_entry *sw_ring;
1050         struct i40e_tx_entry *txe, *txn;
1051         volatile struct i40e_tx_desc *txd;
1052         volatile struct i40e_tx_desc *txr;
1053         struct rte_mbuf *tx_pkt;
1054         struct rte_mbuf *m_seg;
1055         uint32_t cd_tunneling_params;
1056         uint16_t tx_id;
1057         uint16_t nb_tx;
1058         uint32_t td_cmd;
1059         uint32_t td_offset;
1060         uint32_t td_tag;
1061         uint64_t ol_flags;
1062         uint16_t nb_used;
1063         uint16_t nb_ctx;
1064         uint16_t tx_last;
1065         uint16_t slen;
1066         uint64_t buf_dma_addr;
1067         union i40e_tx_offload tx_offload = {0};
1068
1069         txq = tx_queue;
1070         sw_ring = txq->sw_ring;
1071         txr = txq->tx_ring;
1072         tx_id = txq->tx_tail;
1073         txe = &sw_ring[tx_id];
1074
1075         /* Check if the descriptor ring needs to be cleaned. */
1076         if (txq->nb_tx_free < txq->tx_free_thresh)
1077                 (void)i40e_xmit_cleanup(txq);
1078
1079         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1080                 td_cmd = 0;
1081                 td_tag = 0;
1082                 td_offset = 0;
1083
1084                 tx_pkt = *tx_pkts++;
1085                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1086
1087                 ol_flags = tx_pkt->ol_flags;
1088                 tx_offload.l2_len = tx_pkt->l2_len;
1089                 tx_offload.l3_len = tx_pkt->l3_len;
1090                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1091                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1092                 tx_offload.l4_len = tx_pkt->l4_len;
1093                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1094
1095                 /* Calculate the number of context descriptors needed. */
1096                 nb_ctx = i40e_calc_context_desc(ol_flags);
1097
1098                 /**
1099                  * The number of descriptors that must be allocated for
1100                  * a packet equals to the number of the segments of that
1101                  * packet plus 1 context descriptor if needed.
1102                  * Recalculate the needed tx descs when TSO enabled in case
1103                  * the mbuf data size exceeds max data size that hw allows
1104                  * per tx desc.
1105                  */
1106                 if (ol_flags & PKT_TX_TCP_SEG)
1107                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1108                                              nb_ctx);
1109                 else
1110                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1111                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1112
1113                 /* Circular ring */
1114                 if (tx_last >= txq->nb_tx_desc)
1115                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1116
1117                 if (nb_used > txq->nb_tx_free) {
1118                         if (i40e_xmit_cleanup(txq) != 0) {
1119                                 if (nb_tx == 0)
1120                                         return 0;
1121                                 goto end_of_tx;
1122                         }
1123                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1124                                 while (nb_used > txq->nb_tx_free) {
1125                                         if (i40e_xmit_cleanup(txq) != 0) {
1126                                                 if (nb_tx == 0)
1127                                                         return 0;
1128                                                 goto end_of_tx;
1129                                         }
1130                                 }
1131                         }
1132                 }
1133
1134                 /* Descriptor based VLAN insertion */
1135                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1136                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1137                         td_tag = tx_pkt->vlan_tci;
1138                 }
1139
1140                 /* Always enable CRC offload insertion */
1141                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1142
1143                 /* Fill in tunneling parameters if necessary */
1144                 cd_tunneling_params = 0;
1145                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1146                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1147                                                     &cd_tunneling_params);
1148                 /* Enable checksum offloading */
1149                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1150                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1151                                                  &td_offset, tx_offload);
1152
1153                 if (nb_ctx) {
1154                         /* Setup TX context descriptor if required */
1155                         volatile struct i40e_tx_context_desc *ctx_txd =
1156                                 (volatile struct i40e_tx_context_desc *)\
1157                                                         &txr[tx_id];
1158                         uint16_t cd_l2tag2 = 0;
1159                         uint64_t cd_type_cmd_tso_mss =
1160                                 I40E_TX_DESC_DTYPE_CONTEXT;
1161
1162                         txn = &sw_ring[txe->next_id];
1163                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1164                         if (txe->mbuf != NULL) {
1165                                 rte_pktmbuf_free_seg(txe->mbuf);
1166                                 txe->mbuf = NULL;
1167                         }
1168
1169                         /* TSO enabled means no timestamp */
1170                         if (ol_flags & PKT_TX_TCP_SEG)
1171                                 cd_type_cmd_tso_mss |=
1172                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1173                         else {
1174 #ifdef RTE_LIBRTE_IEEE1588
1175                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1176                                         cd_type_cmd_tso_mss |=
1177                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1178                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1179 #endif
1180                         }
1181
1182                         ctx_txd->tunneling_params =
1183                                 rte_cpu_to_le_32(cd_tunneling_params);
1184                         if (ol_flags & PKT_TX_QINQ_PKT) {
1185                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1186                                 cd_type_cmd_tso_mss |=
1187                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1188                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1189                         }
1190                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1191                         ctx_txd->type_cmd_tso_mss =
1192                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1193
1194                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1195                                 "tunneling_params: %#x;\n"
1196                                 "l2tag2: %#hx;\n"
1197                                 "rsvd: %#hx;\n"
1198                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1199                                 tx_pkt, tx_id,
1200                                 ctx_txd->tunneling_params,
1201                                 ctx_txd->l2tag2,
1202                                 ctx_txd->rsvd,
1203                                 ctx_txd->type_cmd_tso_mss);
1204
1205                         txe->last_id = tx_last;
1206                         tx_id = txe->next_id;
1207                         txe = txn;
1208                 }
1209
1210                 m_seg = tx_pkt;
1211                 do {
1212                         txd = &txr[tx_id];
1213                         txn = &sw_ring[txe->next_id];
1214
1215                         if (txe->mbuf)
1216                                 rte_pktmbuf_free_seg(txe->mbuf);
1217                         txe->mbuf = m_seg;
1218
1219                         /* Setup TX Descriptor */
1220                         slen = m_seg->data_len;
1221                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1222
1223                         while ((ol_flags & PKT_TX_TCP_SEG) &&
1224                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1225                                 txd->buffer_addr =
1226                                         rte_cpu_to_le_64(buf_dma_addr);
1227                                 txd->cmd_type_offset_bsz =
1228                                         i40e_build_ctob(td_cmd,
1229                                         td_offset, I40E_MAX_DATA_PER_TXD,
1230                                         td_tag);
1231
1232                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1233                                 slen -= I40E_MAX_DATA_PER_TXD;
1234
1235                                 txe->last_id = tx_last;
1236                                 tx_id = txe->next_id;
1237                                 txe = txn;
1238                                 txd = &txr[tx_id];
1239                                 txn = &sw_ring[txe->next_id];
1240                         }
1241                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1242                                 "buf_dma_addr: %#"PRIx64";\n"
1243                                 "td_cmd: %#x;\n"
1244                                 "td_offset: %#x;\n"
1245                                 "td_len: %u;\n"
1246                                 "td_tag: %#x;\n",
1247                                 tx_pkt, tx_id, buf_dma_addr,
1248                                 td_cmd, td_offset, slen, td_tag);
1249
1250                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1251                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1252                                                 td_offset, slen, td_tag);
1253                         txe->last_id = tx_last;
1254                         tx_id = txe->next_id;
1255                         txe = txn;
1256                         m_seg = m_seg->next;
1257                 } while (m_seg != NULL);
1258
1259                 /* The last packet data descriptor needs End Of Packet (EOP) */
1260                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1261                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1262                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1263
1264                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1265                         PMD_TX_LOG(DEBUG,
1266                                    "Setting RS bit on TXD id="
1267                                    "%4u (port=%d queue=%d)",
1268                                    tx_last, txq->port_id, txq->queue_id);
1269
1270                         td_cmd |= I40E_TX_DESC_CMD_RS;
1271
1272                         /* Update txq RS bit counters */
1273                         txq->nb_tx_used = 0;
1274                 }
1275
1276                 txd->cmd_type_offset_bsz |=
1277                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1278                                         I40E_TXD_QW1_CMD_SHIFT);
1279         }
1280
1281 end_of_tx:
1282         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1283                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1284                    (unsigned) tx_id, (unsigned) nb_tx);
1285
1286         rte_io_wmb();
1287         I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1288         txq->tx_tail = tx_id;
1289
1290         return nb_tx;
1291 }
1292
1293 static __rte_always_inline int
1294 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1295 {
1296         struct i40e_tx_entry *txep;
1297         uint16_t i;
1298
1299         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1300                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1301                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1302                 return 0;
1303
1304         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1305
1306         for (i = 0; i < txq->tx_rs_thresh; i++)
1307                 rte_prefetch0((txep + i)->mbuf);
1308
1309         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1310                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1311                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1312                         txep->mbuf = NULL;
1313                 }
1314         } else {
1315                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1316                         rte_pktmbuf_free_seg(txep->mbuf);
1317                         txep->mbuf = NULL;
1318                 }
1319         }
1320
1321         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1322         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1323         if (txq->tx_next_dd >= txq->nb_tx_desc)
1324                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1325
1326         return txq->tx_rs_thresh;
1327 }
1328
1329 /* Populate 4 descriptors with data from 4 mbufs */
1330 static inline void
1331 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1332 {
1333         uint64_t dma_addr;
1334         uint32_t i;
1335
1336         for (i = 0; i < 4; i++, txdp++, pkts++) {
1337                 dma_addr = rte_mbuf_data_iova(*pkts);
1338                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1339                 txdp->cmd_type_offset_bsz =
1340                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1341                                         (*pkts)->data_len, 0);
1342         }
1343 }
1344
1345 /* Populate 1 descriptor with data from 1 mbuf */
1346 static inline void
1347 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1348 {
1349         uint64_t dma_addr;
1350
1351         dma_addr = rte_mbuf_data_iova(*pkts);
1352         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1353         txdp->cmd_type_offset_bsz =
1354                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1355                                 (*pkts)->data_len, 0);
1356 }
1357
1358 /* Fill hardware descriptor ring with mbuf data */
1359 static inline void
1360 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1361                      struct rte_mbuf **pkts,
1362                      uint16_t nb_pkts)
1363 {
1364         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1365         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1366         const int N_PER_LOOP = 4;
1367         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1368         int mainpart, leftover;
1369         int i, j;
1370
1371         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1372         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1373         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1374                 for (j = 0; j < N_PER_LOOP; ++j) {
1375                         (txep + i + j)->mbuf = *(pkts + i + j);
1376                 }
1377                 tx4(txdp + i, pkts + i);
1378         }
1379         if (unlikely(leftover > 0)) {
1380                 for (i = 0; i < leftover; ++i) {
1381                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1382                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1383                 }
1384         }
1385 }
1386
1387 static inline uint16_t
1388 tx_xmit_pkts(struct i40e_tx_queue *txq,
1389              struct rte_mbuf **tx_pkts,
1390              uint16_t nb_pkts)
1391 {
1392         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1393         uint16_t n = 0;
1394
1395         /**
1396          * Begin scanning the H/W ring for done descriptors when the number
1397          * of available descriptors drops below tx_free_thresh. For each done
1398          * descriptor, free the associated buffer.
1399          */
1400         if (txq->nb_tx_free < txq->tx_free_thresh)
1401                 i40e_tx_free_bufs(txq);
1402
1403         /* Use available descriptor only */
1404         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1405         if (unlikely(!nb_pkts))
1406                 return 0;
1407
1408         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1409         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1410                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1411                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1412                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1413                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1414                                                 I40E_TXD_QW1_CMD_SHIFT);
1415                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1416                 txq->tx_tail = 0;
1417         }
1418
1419         /* Fill hardware descriptor ring with mbuf data */
1420         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1421         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1422
1423         /* Determin if RS bit needs to be set */
1424         if (txq->tx_tail > txq->tx_next_rs) {
1425                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1426                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1427                                                 I40E_TXD_QW1_CMD_SHIFT);
1428                 txq->tx_next_rs =
1429                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1430                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1431                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1432         }
1433
1434         if (txq->tx_tail >= txq->nb_tx_desc)
1435                 txq->tx_tail = 0;
1436
1437         /* Update the tx tail register */
1438         I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1439
1440         return nb_pkts;
1441 }
1442
1443 static uint16_t
1444 i40e_xmit_pkts_simple(void *tx_queue,
1445                       struct rte_mbuf **tx_pkts,
1446                       uint16_t nb_pkts)
1447 {
1448         uint16_t nb_tx = 0;
1449
1450         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1451                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1452                                                 tx_pkts, nb_pkts);
1453
1454         while (nb_pkts) {
1455                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1456                                                 I40E_TX_MAX_BURST);
1457
1458                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1459                                                 &tx_pkts[nb_tx], num);
1460                 nb_tx = (uint16_t)(nb_tx + ret);
1461                 nb_pkts = (uint16_t)(nb_pkts - ret);
1462                 if (ret < num)
1463                         break;
1464         }
1465
1466         return nb_tx;
1467 }
1468
1469 static uint16_t
1470 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1471                    uint16_t nb_pkts)
1472 {
1473         uint16_t nb_tx = 0;
1474         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1475
1476         while (nb_pkts) {
1477                 uint16_t ret, num;
1478
1479                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1480                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1481                                                 num);
1482                 nb_tx += ret;
1483                 nb_pkts -= ret;
1484                 if (ret < num)
1485                         break;
1486         }
1487
1488         return nb_tx;
1489 }
1490
1491 /*********************************************************************
1492  *
1493  *  TX simple prep functions
1494  *
1495  **********************************************************************/
1496 uint16_t
1497 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1498                       uint16_t nb_pkts)
1499 {
1500         int i;
1501         uint64_t ol_flags;
1502         struct rte_mbuf *m;
1503
1504         for (i = 0; i < nb_pkts; i++) {
1505                 m = tx_pkts[i];
1506                 ol_flags = m->ol_flags;
1507
1508                 if (m->nb_segs != 1) {
1509                         rte_errno = EINVAL;
1510                         return i;
1511                 }
1512
1513                 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1514                         rte_errno = ENOTSUP;
1515                         return i;
1516                 }
1517
1518                 /* check the size of packet */
1519                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1520                     m->pkt_len > I40E_FRAME_SIZE_MAX) {
1521                         rte_errno = EINVAL;
1522                         return i;
1523                 }
1524         }
1525         return i;
1526 }
1527
1528 /*********************************************************************
1529  *
1530  *  TX prep functions
1531  *
1532  **********************************************************************/
1533 uint16_t
1534 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1535                 uint16_t nb_pkts)
1536 {
1537         int i, ret;
1538         uint64_t ol_flags;
1539         struct rte_mbuf *m;
1540
1541         for (i = 0; i < nb_pkts; i++) {
1542                 m = tx_pkts[i];
1543                 ol_flags = m->ol_flags;
1544
1545                 /* Check for m->nb_segs to not exceed the limits. */
1546                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1547                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1548                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1549                                 rte_errno = EINVAL;
1550                                 return i;
1551                         }
1552                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1553                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1554                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1555                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1556                         /* MSS outside the range (256B - 9674B) are considered
1557                          * malicious
1558                          */
1559                         rte_errno = EINVAL;
1560                         return i;
1561                 }
1562
1563                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1564                         rte_errno = ENOTSUP;
1565                         return i;
1566                 }
1567
1568                 /* check the size of packet */
1569                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1570                         rte_errno = EINVAL;
1571                         return i;
1572                 }
1573
1574 #ifdef RTE_ETHDEV_DEBUG_TX
1575                 ret = rte_validate_tx_offload(m);
1576                 if (ret != 0) {
1577                         rte_errno = -ret;
1578                         return i;
1579                 }
1580 #endif
1581                 ret = rte_net_intel_cksum_prepare(m);
1582                 if (ret != 0) {
1583                         rte_errno = -ret;
1584                         return i;
1585                 }
1586         }
1587         return i;
1588 }
1589
1590 /*
1591  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1592  * application used, which assume having sequential ones. But from driver's
1593  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1594  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1595  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1596  * use queue_idx from 0 to 95 to access queues, while real queue would be
1597  * different. This function will do a queue mapping to find VSI the queue
1598  * belongs to.
1599  */
1600 static struct i40e_vsi*
1601 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1602 {
1603         /* the queue in MAIN VSI range */
1604         if (queue_idx < pf->main_vsi->nb_qps)
1605                 return pf->main_vsi;
1606
1607         queue_idx -= pf->main_vsi->nb_qps;
1608
1609         /* queue_idx is greater than VMDQ VSIs range */
1610         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1611                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1612                 return NULL;
1613         }
1614
1615         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1616 }
1617
1618 static uint16_t
1619 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1620 {
1621         /* the queue in MAIN VSI range */
1622         if (queue_idx < pf->main_vsi->nb_qps)
1623                 return queue_idx;
1624
1625         /* It's VMDQ queues */
1626         queue_idx -= pf->main_vsi->nb_qps;
1627
1628         if (pf->nb_cfg_vmdq_vsi)
1629                 return queue_idx % pf->vmdq_nb_qps;
1630         else {
1631                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1632                 return (uint16_t)(-1);
1633         }
1634 }
1635
1636 int
1637 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1638 {
1639         struct i40e_rx_queue *rxq;
1640         int err;
1641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642
1643         PMD_INIT_FUNC_TRACE();
1644
1645         rxq = dev->data->rx_queues[rx_queue_id];
1646         if (!rxq || !rxq->q_set) {
1647                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1648                             rx_queue_id);
1649                 return -EINVAL;
1650         }
1651
1652         if (rxq->rx_deferred_start)
1653                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1654                             rx_queue_id);
1655
1656         err = i40e_alloc_rx_queue_mbufs(rxq);
1657         if (err) {
1658                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1659                 return err;
1660         }
1661
1662         /* Init the RX tail regieter. */
1663         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1664
1665         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1666         if (err) {
1667                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1668                             rx_queue_id);
1669
1670                 i40e_rx_queue_release_mbufs(rxq);
1671                 i40e_reset_rx_queue(rxq);
1672                 return err;
1673         }
1674         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1675
1676         return 0;
1677 }
1678
1679 int
1680 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1681 {
1682         struct i40e_rx_queue *rxq;
1683         int err;
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685
1686         rxq = dev->data->rx_queues[rx_queue_id];
1687         if (!rxq || !rxq->q_set) {
1688                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1689                                 rx_queue_id);
1690                 return -EINVAL;
1691         }
1692
1693         /*
1694          * rx_queue_id is queue id application refers to, while
1695          * rxq->reg_idx is the real queue index.
1696          */
1697         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1698         if (err) {
1699                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1700                             rx_queue_id);
1701                 return err;
1702         }
1703         i40e_rx_queue_release_mbufs(rxq);
1704         i40e_reset_rx_queue(rxq);
1705         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1706
1707         return 0;
1708 }
1709
1710 int
1711 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1712 {
1713         int err;
1714         struct i40e_tx_queue *txq;
1715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716
1717         PMD_INIT_FUNC_TRACE();
1718
1719         txq = dev->data->tx_queues[tx_queue_id];
1720         if (!txq || !txq->q_set) {
1721                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1722                             tx_queue_id);
1723                 return -EINVAL;
1724         }
1725
1726         if (txq->tx_deferred_start)
1727                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1728                             tx_queue_id);
1729
1730         /*
1731          * tx_queue_id is queue id application refers to, while
1732          * rxq->reg_idx is the real queue index.
1733          */
1734         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1735         if (err) {
1736                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1737                             tx_queue_id);
1738                 return err;
1739         }
1740         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1741
1742         return 0;
1743 }
1744
1745 int
1746 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1747 {
1748         struct i40e_tx_queue *txq;
1749         int err;
1750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751
1752         txq = dev->data->tx_queues[tx_queue_id];
1753         if (!txq || !txq->q_set) {
1754                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1755                         tx_queue_id);
1756                 return -EINVAL;
1757         }
1758
1759         /*
1760          * tx_queue_id is queue id application refers to, while
1761          * txq->reg_idx is the real queue index.
1762          */
1763         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1764         if (err) {
1765                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1766                             tx_queue_id);
1767                 return err;
1768         }
1769
1770         i40e_tx_queue_release_mbufs(txq);
1771         i40e_reset_tx_queue(txq);
1772         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1773
1774         return 0;
1775 }
1776
1777 const uint32_t *
1778 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1779 {
1780         static const uint32_t ptypes[] = {
1781                 /* refers to i40e_rxd_pkt_type_mapping() */
1782                 RTE_PTYPE_L2_ETHER,
1783                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1784                 RTE_PTYPE_L2_ETHER_LLDP,
1785                 RTE_PTYPE_L2_ETHER_ARP,
1786                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1787                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1788                 RTE_PTYPE_L4_FRAG,
1789                 RTE_PTYPE_L4_ICMP,
1790                 RTE_PTYPE_L4_NONFRAG,
1791                 RTE_PTYPE_L4_SCTP,
1792                 RTE_PTYPE_L4_TCP,
1793                 RTE_PTYPE_L4_UDP,
1794                 RTE_PTYPE_TUNNEL_GRENAT,
1795                 RTE_PTYPE_TUNNEL_IP,
1796                 RTE_PTYPE_INNER_L2_ETHER,
1797                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1798                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1799                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1800                 RTE_PTYPE_INNER_L4_FRAG,
1801                 RTE_PTYPE_INNER_L4_ICMP,
1802                 RTE_PTYPE_INNER_L4_NONFRAG,
1803                 RTE_PTYPE_INNER_L4_SCTP,
1804                 RTE_PTYPE_INNER_L4_TCP,
1805                 RTE_PTYPE_INNER_L4_UDP,
1806                 RTE_PTYPE_UNKNOWN
1807         };
1808
1809         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1810 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1811             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1812 #endif
1813             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1814             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1815             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1816 #ifdef CC_AVX512_SUPPORT
1817             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1818             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1819 #endif
1820             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1821             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1822                 return ptypes;
1823         return NULL;
1824 }
1825
1826 static int
1827 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1828 {
1829         uint16_t i;
1830
1831         for (i = 0; i < num; i++) {
1832                 if (i != idx && queues[i])
1833                         return 0;
1834         }
1835
1836         return 1;
1837 }
1838
1839 static int
1840 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1841                                 struct i40e_rx_queue *rxq)
1842 {
1843         struct i40e_adapter *ad =
1844                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1845         int use_def_burst_func =
1846                 check_rx_burst_bulk_alloc_preconditions(rxq);
1847         uint16_t buf_size =
1848                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1849                            RTE_PKTMBUF_HEADROOM);
1850         int use_scattered_rx =
1851                 (rxq->max_pkt_len > buf_size);
1852
1853         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1854                 PMD_DRV_LOG(ERR,
1855                             "Failed to do RX queue initialization");
1856                 return -EINVAL;
1857         }
1858
1859         if (i40e_dev_first_queue(rxq->queue_id,
1860                                  dev->data->rx_queues,
1861                                  dev->data->nb_rx_queues)) {
1862                 /**
1863                  * If it is the first queue to setup,
1864                  * set all flags to default and call
1865                  * i40e_set_rx_function.
1866                  */
1867                 ad->rx_bulk_alloc_allowed = true;
1868                 ad->rx_vec_allowed = true;
1869                 dev->data->scattered_rx = use_scattered_rx;
1870                 if (use_def_burst_func)
1871                         ad->rx_bulk_alloc_allowed = false;
1872                 i40e_set_rx_function(dev);
1873                 return 0;
1874         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1875                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1876                             " number %d of queue %d isn't power of 2",
1877                             rxq->nb_rx_desc, rxq->queue_id);
1878                 return -EINVAL;
1879         }
1880
1881         /* check bulk alloc conflict */
1882         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1883                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1884                 return -EINVAL;
1885         }
1886         /* check scatterred conflict */
1887         if (!dev->data->scattered_rx && use_scattered_rx) {
1888                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1889                 return -EINVAL;
1890         }
1891         /* check vector conflict */
1892         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1893                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1894                 return -EINVAL;
1895         }
1896
1897         return 0;
1898 }
1899
1900 int
1901 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1902                         uint16_t queue_idx,
1903                         uint16_t nb_desc,
1904                         unsigned int socket_id,
1905                         const struct rte_eth_rxconf *rx_conf,
1906                         struct rte_mempool *mp)
1907 {
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_adapter *ad =
1910                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1911         struct i40e_vsi *vsi;
1912         struct i40e_pf *pf = NULL;
1913         struct i40e_vf *vf = NULL;
1914         struct i40e_rx_queue *rxq;
1915         const struct rte_memzone *rz;
1916         uint32_t ring_size;
1917         uint16_t len, i;
1918         uint16_t reg_idx, base, bsf, tc_mapping;
1919         int q_offset, use_def_burst_func = 1;
1920         uint64_t offloads;
1921
1922         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1923
1924         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1925                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1926                 vsi = &vf->vsi;
1927                 if (!vsi)
1928                         return -EINVAL;
1929                 reg_idx = queue_idx;
1930         } else {
1931                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1932                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1933                 if (!vsi)
1934                         return -EINVAL;
1935                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1936                 if (q_offset < 0)
1937                         return -EINVAL;
1938                 reg_idx = vsi->base_queue + q_offset;
1939         }
1940
1941         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1942             (nb_desc > I40E_MAX_RING_DESC) ||
1943             (nb_desc < I40E_MIN_RING_DESC)) {
1944                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1945                             "invalid", nb_desc);
1946                 return -EINVAL;
1947         }
1948
1949         /* Free memory if needed */
1950         if (dev->data->rx_queues[queue_idx]) {
1951                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1952                 dev->data->rx_queues[queue_idx] = NULL;
1953         }
1954
1955         /* Allocate the rx queue data structure */
1956         rxq = rte_zmalloc_socket("i40e rx queue",
1957                                  sizeof(struct i40e_rx_queue),
1958                                  RTE_CACHE_LINE_SIZE,
1959                                  socket_id);
1960         if (!rxq) {
1961                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1962                             "rx queue data structure");
1963                 return -ENOMEM;
1964         }
1965         rxq->mp = mp;
1966         rxq->nb_rx_desc = nb_desc;
1967         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1968         rxq->queue_id = queue_idx;
1969         rxq->reg_idx = reg_idx;
1970         rxq->port_id = dev->data->port_id;
1971         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1972                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1973         else
1974                 rxq->crc_len = 0;
1975         rxq->drop_en = rx_conf->rx_drop_en;
1976         rxq->vsi = vsi;
1977         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1978         rxq->offloads = offloads;
1979
1980         /* Allocate the maximun number of RX ring hardware descriptor. */
1981         len = I40E_MAX_RING_DESC;
1982
1983         /**
1984          * Allocating a little more memory because vectorized/bulk_alloc Rx
1985          * functions doesn't check boundaries each time.
1986          */
1987         len += RTE_PMD_I40E_RX_MAX_BURST;
1988
1989         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1990                               I40E_DMA_MEM_ALIGN);
1991
1992         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1993                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1994         if (!rz) {
1995                 i40e_dev_rx_queue_release(rxq);
1996                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1997                 return -ENOMEM;
1998         }
1999
2000         /* Zero all the descriptors in the ring. */
2001         memset(rz->addr, 0, ring_size);
2002
2003         rxq->rx_ring_phys_addr = rz->iova;
2004         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2005
2006         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2007
2008         /* Allocate the software ring. */
2009         rxq->sw_ring =
2010                 rte_zmalloc_socket("i40e rx sw ring",
2011                                    sizeof(struct i40e_rx_entry) * len,
2012                                    RTE_CACHE_LINE_SIZE,
2013                                    socket_id);
2014         if (!rxq->sw_ring) {
2015                 i40e_dev_rx_queue_release(rxq);
2016                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2017                 return -ENOMEM;
2018         }
2019
2020         i40e_reset_rx_queue(rxq);
2021         rxq->q_set = TRUE;
2022
2023         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2024                 if (!(vsi->enabled_tc & (1 << i)))
2025                         continue;
2026                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2027                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2028                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2029                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2030                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2031
2032                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2033                         rxq->dcb_tc = i;
2034         }
2035
2036         if (dev->data->dev_started) {
2037                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2038                         i40e_dev_rx_queue_release(rxq);
2039                         return -EINVAL;
2040                 }
2041         } else {
2042                 use_def_burst_func =
2043                         check_rx_burst_bulk_alloc_preconditions(rxq);
2044                 if (!use_def_burst_func) {
2045 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2046                         PMD_INIT_LOG(DEBUG,
2047                           "Rx Burst Bulk Alloc Preconditions are "
2048                           "satisfied. Rx Burst Bulk Alloc function will be "
2049                           "used on port=%d, queue=%d.",
2050                           rxq->port_id, rxq->queue_id);
2051 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2052                 } else {
2053                         PMD_INIT_LOG(DEBUG,
2054                           "Rx Burst Bulk Alloc Preconditions are "
2055                           "not satisfied, Scattered Rx is requested, "
2056                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2057                           "not enabled on port=%d, queue=%d.",
2058                           rxq->port_id, rxq->queue_id);
2059                         ad->rx_bulk_alloc_allowed = false;
2060                 }
2061         }
2062
2063         dev->data->rx_queues[queue_idx] = rxq;
2064         return 0;
2065 }
2066
2067 void
2068 i40e_dev_rx_queue_release(void *rxq)
2069 {
2070         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2071
2072         if (!q) {
2073                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2074                 return;
2075         }
2076
2077         i40e_rx_queue_release_mbufs(q);
2078         rte_free(q->sw_ring);
2079         rte_free(q);
2080 }
2081
2082 uint32_t
2083 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2084 {
2085 #define I40E_RXQ_SCAN_INTERVAL 4
2086         volatile union i40e_rx_desc *rxdp;
2087         struct i40e_rx_queue *rxq;
2088         uint16_t desc = 0;
2089
2090         rxq = dev->data->rx_queues[rx_queue_id];
2091         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2092         while ((desc < rxq->nb_rx_desc) &&
2093                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2094                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2095                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2096                 /**
2097                  * Check the DD bit of a rx descriptor of each 4 in a group,
2098                  * to avoid checking too frequently and downgrading performance
2099                  * too much.
2100                  */
2101                 desc += I40E_RXQ_SCAN_INTERVAL;
2102                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2103                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2104                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2105                                         desc - rxq->nb_rx_desc]);
2106         }
2107
2108         return desc;
2109 }
2110
2111 int
2112 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2113 {
2114         volatile union i40e_rx_desc *rxdp;
2115         struct i40e_rx_queue *rxq = rx_queue;
2116         uint16_t desc;
2117         int ret;
2118
2119         if (unlikely(offset >= rxq->nb_rx_desc)) {
2120                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2121                 return 0;
2122         }
2123
2124         desc = rxq->rx_tail + offset;
2125         if (desc >= rxq->nb_rx_desc)
2126                 desc -= rxq->nb_rx_desc;
2127
2128         rxdp = &(rxq->rx_ring[desc]);
2129
2130         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2131                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2132                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2133
2134         return ret;
2135 }
2136
2137 int
2138 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2139 {
2140         struct i40e_rx_queue *rxq = rx_queue;
2141         volatile uint64_t *status;
2142         uint64_t mask;
2143         uint32_t desc;
2144
2145         if (unlikely(offset >= rxq->nb_rx_desc))
2146                 return -EINVAL;
2147
2148         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2149                 return RTE_ETH_RX_DESC_UNAVAIL;
2150
2151         desc = rxq->rx_tail + offset;
2152         if (desc >= rxq->nb_rx_desc)
2153                 desc -= rxq->nb_rx_desc;
2154
2155         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2156         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2157                 << I40E_RXD_QW1_STATUS_SHIFT);
2158         if (*status & mask)
2159                 return RTE_ETH_RX_DESC_DONE;
2160
2161         return RTE_ETH_RX_DESC_AVAIL;
2162 }
2163
2164 int
2165 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2166 {
2167         struct i40e_tx_queue *txq = tx_queue;
2168         volatile uint64_t *status;
2169         uint64_t mask, expect;
2170         uint32_t desc;
2171
2172         if (unlikely(offset >= txq->nb_tx_desc))
2173                 return -EINVAL;
2174
2175         desc = txq->tx_tail + offset;
2176         /* go to next desc that has the RS bit */
2177         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2178                 txq->tx_rs_thresh;
2179         if (desc >= txq->nb_tx_desc) {
2180                 desc -= txq->nb_tx_desc;
2181                 if (desc >= txq->nb_tx_desc)
2182                         desc -= txq->nb_tx_desc;
2183         }
2184
2185         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2186         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2187         expect = rte_cpu_to_le_64(
2188                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2189         if ((*status & mask) == expect)
2190                 return RTE_ETH_TX_DESC_DONE;
2191
2192         return RTE_ETH_TX_DESC_FULL;
2193 }
2194
2195 static int
2196 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2197                                 struct i40e_tx_queue *txq)
2198 {
2199         struct i40e_adapter *ad =
2200                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2201
2202         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2203                 PMD_DRV_LOG(ERR,
2204                             "Failed to do TX queue initialization");
2205                 return -EINVAL;
2206         }
2207
2208         if (i40e_dev_first_queue(txq->queue_id,
2209                                  dev->data->tx_queues,
2210                                  dev->data->nb_tx_queues)) {
2211                 /**
2212                  * If it is the first queue to setup,
2213                  * set all flags and call
2214                  * i40e_set_tx_function.
2215                  */
2216                 i40e_set_tx_function_flag(dev, txq);
2217                 i40e_set_tx_function(dev);
2218                 return 0;
2219         }
2220
2221         /* check vector conflict */
2222         if (ad->tx_vec_allowed) {
2223                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2224                     i40e_txq_vec_setup(txq)) {
2225                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2226                         return -EINVAL;
2227                 }
2228         }
2229         /* check simple tx conflict */
2230         if (ad->tx_simple_allowed) {
2231                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2232                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2233                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2234                         return -EINVAL;
2235                 }
2236         }
2237
2238         return 0;
2239 }
2240
2241 int
2242 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2243                         uint16_t queue_idx,
2244                         uint16_t nb_desc,
2245                         unsigned int socket_id,
2246                         const struct rte_eth_txconf *tx_conf)
2247 {
2248         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2249         struct i40e_vsi *vsi;
2250         struct i40e_pf *pf = NULL;
2251         struct i40e_vf *vf = NULL;
2252         struct i40e_tx_queue *txq;
2253         const struct rte_memzone *tz;
2254         uint32_t ring_size;
2255         uint16_t tx_rs_thresh, tx_free_thresh;
2256         uint16_t reg_idx, i, base, bsf, tc_mapping;
2257         int q_offset;
2258         uint64_t offloads;
2259
2260         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2261
2262         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2263                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2264                 vsi = &vf->vsi;
2265                 reg_idx = queue_idx;
2266         } else {
2267                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2268                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2269                 if (!vsi)
2270                         return -EINVAL;
2271                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2272                 if (q_offset < 0)
2273                         return -EINVAL;
2274                 reg_idx = vsi->base_queue + q_offset;
2275         }
2276
2277         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2278             (nb_desc > I40E_MAX_RING_DESC) ||
2279             (nb_desc < I40E_MIN_RING_DESC)) {
2280                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2281                             "invalid", nb_desc);
2282                 return -EINVAL;
2283         }
2284
2285         /**
2286          * The following two parameters control the setting of the RS bit on
2287          * transmit descriptors. TX descriptors will have their RS bit set
2288          * after txq->tx_rs_thresh descriptors have been used. The TX
2289          * descriptor ring will be cleaned after txq->tx_free_thresh
2290          * descriptors are used or if the number of descriptors required to
2291          * transmit a packet is greater than the number of free TX descriptors.
2292          *
2293          * The following constraints must be satisfied:
2294          *  - tx_rs_thresh must be greater than 0.
2295          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2296          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2297          *  - tx_rs_thresh must be a divisor of the ring size.
2298          *  - tx_free_thresh must be greater than 0.
2299          *  - tx_free_thresh must be less than the size of the ring minus 3.
2300          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2301          *
2302          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2303          * race condition, hence the maximum threshold constraints. When set
2304          * to zero use default values.
2305          */
2306         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2307                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2308         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2309         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2310                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2311         if (tx_conf->tx_rs_thresh > 0)
2312                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2313         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2314                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2315                                 "exceed nb_desc. (tx_rs_thresh=%u "
2316                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2317                                 (unsigned int)tx_rs_thresh,
2318                                 (unsigned int)tx_free_thresh,
2319                                 (unsigned int)nb_desc,
2320                                 (int)dev->data->port_id,
2321                                 (int)queue_idx);
2322                 return I40E_ERR_PARAM;
2323         }
2324         if (tx_rs_thresh >= (nb_desc - 2)) {
2325                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2326                              "number of TX descriptors minus 2. "
2327                              "(tx_rs_thresh=%u port=%d queue=%d)",
2328                              (unsigned int)tx_rs_thresh,
2329                              (int)dev->data->port_id,
2330                              (int)queue_idx);
2331                 return I40E_ERR_PARAM;
2332         }
2333         if (tx_free_thresh >= (nb_desc - 3)) {
2334                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2335                              "number of TX descriptors minus 3. "
2336                              "(tx_free_thresh=%u port=%d queue=%d)",
2337                              (unsigned int)tx_free_thresh,
2338                              (int)dev->data->port_id,
2339                              (int)queue_idx);
2340                 return I40E_ERR_PARAM;
2341         }
2342         if (tx_rs_thresh > tx_free_thresh) {
2343                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2344                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2345                              " tx_rs_thresh=%u port=%d queue=%d)",
2346                              (unsigned int)tx_free_thresh,
2347                              (unsigned int)tx_rs_thresh,
2348                              (int)dev->data->port_id,
2349                              (int)queue_idx);
2350                 return I40E_ERR_PARAM;
2351         }
2352         if ((nb_desc % tx_rs_thresh) != 0) {
2353                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2354                              "number of TX descriptors. (tx_rs_thresh=%u"
2355                              " port=%d queue=%d)",
2356                              (unsigned int)tx_rs_thresh,
2357                              (int)dev->data->port_id,
2358                              (int)queue_idx);
2359                 return I40E_ERR_PARAM;
2360         }
2361         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2362                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2363                              "tx_rs_thresh is greater than 1. "
2364                              "(tx_rs_thresh=%u port=%d queue=%d)",
2365                              (unsigned int)tx_rs_thresh,
2366                              (int)dev->data->port_id,
2367                              (int)queue_idx);
2368                 return I40E_ERR_PARAM;
2369         }
2370
2371         /* Free memory if needed. */
2372         if (dev->data->tx_queues[queue_idx]) {
2373                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2374                 dev->data->tx_queues[queue_idx] = NULL;
2375         }
2376
2377         /* Allocate the TX queue data structure. */
2378         txq = rte_zmalloc_socket("i40e tx queue",
2379                                   sizeof(struct i40e_tx_queue),
2380                                   RTE_CACHE_LINE_SIZE,
2381                                   socket_id);
2382         if (!txq) {
2383                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2384                             "tx queue structure");
2385                 return -ENOMEM;
2386         }
2387
2388         /* Allocate TX hardware ring descriptors. */
2389         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2390         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2391         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2392                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2393         if (!tz) {
2394                 i40e_dev_tx_queue_release(txq);
2395                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2396                 return -ENOMEM;
2397         }
2398
2399         txq->nb_tx_desc = nb_desc;
2400         txq->tx_rs_thresh = tx_rs_thresh;
2401         txq->tx_free_thresh = tx_free_thresh;
2402         txq->pthresh = tx_conf->tx_thresh.pthresh;
2403         txq->hthresh = tx_conf->tx_thresh.hthresh;
2404         txq->wthresh = tx_conf->tx_thresh.wthresh;
2405         txq->queue_id = queue_idx;
2406         txq->reg_idx = reg_idx;
2407         txq->port_id = dev->data->port_id;
2408         txq->offloads = offloads;
2409         txq->vsi = vsi;
2410         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2411
2412         txq->tx_ring_phys_addr = tz->iova;
2413         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2414
2415         /* Allocate software ring */
2416         txq->sw_ring =
2417                 rte_zmalloc_socket("i40e tx sw ring",
2418                                    sizeof(struct i40e_tx_entry) * nb_desc,
2419                                    RTE_CACHE_LINE_SIZE,
2420                                    socket_id);
2421         if (!txq->sw_ring) {
2422                 i40e_dev_tx_queue_release(txq);
2423                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2424                 return -ENOMEM;
2425         }
2426
2427         i40e_reset_tx_queue(txq);
2428         txq->q_set = TRUE;
2429
2430         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2431                 if (!(vsi->enabled_tc & (1 << i)))
2432                         continue;
2433                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2434                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2435                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2436                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2437                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2438
2439                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2440                         txq->dcb_tc = i;
2441         }
2442
2443         if (dev->data->dev_started) {
2444                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2445                         i40e_dev_tx_queue_release(txq);
2446                         return -EINVAL;
2447                 }
2448         } else {
2449                 /**
2450                  * Use a simple TX queue without offloads or
2451                  * multi segs if possible
2452                  */
2453                 i40e_set_tx_function_flag(dev, txq);
2454         }
2455         dev->data->tx_queues[queue_idx] = txq;
2456
2457         return 0;
2458 }
2459
2460 void
2461 i40e_dev_tx_queue_release(void *txq)
2462 {
2463         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2464
2465         if (!q) {
2466                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2467                 return;
2468         }
2469
2470         i40e_tx_queue_release_mbufs(q);
2471         rte_free(q->sw_ring);
2472         rte_free(q);
2473 }
2474
2475 const struct rte_memzone *
2476 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2477 {
2478         const struct rte_memzone *mz;
2479
2480         mz = rte_memzone_lookup(name);
2481         if (mz)
2482                 return mz;
2483
2484         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2485                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2486         return mz;
2487 }
2488
2489 void
2490 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2491 {
2492         uint16_t i;
2493
2494         /* SSE Vector driver has a different way of releasing mbufs. */
2495         if (rxq->rx_using_sse) {
2496                 i40e_rx_queue_release_mbufs_vec(rxq);
2497                 return;
2498         }
2499
2500         if (!rxq->sw_ring) {
2501                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2502                 return;
2503         }
2504
2505         for (i = 0; i < rxq->nb_rx_desc; i++) {
2506                 if (rxq->sw_ring[i].mbuf) {
2507                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2508                         rxq->sw_ring[i].mbuf = NULL;
2509                 }
2510         }
2511 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2512         if (rxq->rx_nb_avail == 0)
2513                 return;
2514         for (i = 0; i < rxq->rx_nb_avail; i++) {
2515                 struct rte_mbuf *mbuf;
2516
2517                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2518                 rte_pktmbuf_free_seg(mbuf);
2519         }
2520         rxq->rx_nb_avail = 0;
2521 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2522 }
2523
2524 void
2525 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2526 {
2527         unsigned i;
2528         uint16_t len;
2529
2530         if (!rxq) {
2531                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2532                 return;
2533         }
2534
2535 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2536         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2537                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2538         else
2539 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2540                 len = rxq->nb_rx_desc;
2541
2542         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2543                 ((volatile char *)rxq->rx_ring)[i] = 0;
2544
2545         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2546         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2547                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2548
2549 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2550         rxq->rx_nb_avail = 0;
2551         rxq->rx_next_avail = 0;
2552         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2553 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2554         rxq->rx_tail = 0;
2555         rxq->nb_rx_hold = 0;
2556         rxq->pkt_first_seg = NULL;
2557         rxq->pkt_last_seg = NULL;
2558
2559         rxq->rxrearm_start = 0;
2560         rxq->rxrearm_nb = 0;
2561 }
2562
2563 void
2564 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2565 {
2566         struct rte_eth_dev *dev;
2567         uint16_t i;
2568
2569         if (!txq || !txq->sw_ring) {
2570                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2571                 return;
2572         }
2573
2574         dev = &rte_eth_devices[txq->port_id];
2575
2576         /**
2577          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2578          *  so need to free remains more carefully.
2579          */
2580 #ifdef CC_AVX512_SUPPORT
2581         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2582                 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2583
2584                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2585                 if (txq->tx_tail < i) {
2586                         for (; i < txq->nb_tx_desc; i++) {
2587                                 rte_pktmbuf_free_seg(swr[i].mbuf);
2588                                 swr[i].mbuf = NULL;
2589                         }
2590                         i = 0;
2591                 }
2592                 for (; i < txq->tx_tail; i++) {
2593                         rte_pktmbuf_free_seg(swr[i].mbuf);
2594                         swr[i].mbuf = NULL;
2595                 }
2596                 return;
2597         }
2598 #endif
2599         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2600                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2601                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2602                 if (txq->tx_tail < i) {
2603                         for (; i < txq->nb_tx_desc; i++) {
2604                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2605                                 txq->sw_ring[i].mbuf = NULL;
2606                         }
2607                         i = 0;
2608                 }
2609                 for (; i < txq->tx_tail; i++) {
2610                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2611                         txq->sw_ring[i].mbuf = NULL;
2612                 }
2613         } else {
2614                 for (i = 0; i < txq->nb_tx_desc; i++) {
2615                         if (txq->sw_ring[i].mbuf) {
2616                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2617                                 txq->sw_ring[i].mbuf = NULL;
2618                         }
2619                 }
2620         }
2621 }
2622
2623 static int
2624 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2625                         uint32_t free_cnt)
2626 {
2627         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2628         uint16_t i, tx_last, tx_id;
2629         uint16_t nb_tx_free_last;
2630         uint16_t nb_tx_to_clean;
2631         uint32_t pkt_cnt;
2632
2633         /* Start free mbuf from the next of tx_tail */
2634         tx_last = txq->tx_tail;
2635         tx_id  = swr_ring[tx_last].next_id;
2636
2637         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2638                 return 0;
2639
2640         nb_tx_to_clean = txq->nb_tx_free;
2641         nb_tx_free_last = txq->nb_tx_free;
2642         if (!free_cnt)
2643                 free_cnt = txq->nb_tx_desc;
2644
2645         /* Loop through swr_ring to count the amount of
2646          * freeable mubfs and packets.
2647          */
2648         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2649                 for (i = 0; i < nb_tx_to_clean &&
2650                         pkt_cnt < free_cnt &&
2651                         tx_id != tx_last; i++) {
2652                         if (swr_ring[tx_id].mbuf != NULL) {
2653                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2654                                 swr_ring[tx_id].mbuf = NULL;
2655
2656                                 /*
2657                                  * last segment in the packet,
2658                                  * increment packet count
2659                                  */
2660                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2661                         }
2662
2663                         tx_id = swr_ring[tx_id].next_id;
2664                 }
2665
2666                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2667                         txq->nb_tx_free || tx_id == tx_last)
2668                         break;
2669
2670                 if (pkt_cnt < free_cnt) {
2671                         if (i40e_xmit_cleanup(txq))
2672                                 break;
2673
2674                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2675                         nb_tx_free_last = txq->nb_tx_free;
2676                 }
2677         }
2678
2679         return (int)pkt_cnt;
2680 }
2681
2682 static int
2683 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2684                         uint32_t free_cnt)
2685 {
2686         int i, n, cnt;
2687
2688         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2689                 free_cnt = txq->nb_tx_desc;
2690
2691         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2692
2693         for (i = 0; i < cnt; i += n) {
2694                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2695                         break;
2696
2697                 n = i40e_tx_free_bufs(txq);
2698
2699                 if (n == 0)
2700                         break;
2701         }
2702
2703         return i;
2704 }
2705
2706 static int
2707 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2708                         uint32_t free_cnt __rte_unused)
2709 {
2710         return -ENOTSUP;
2711 }
2712 int
2713 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2714 {
2715         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2716         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2717         struct i40e_adapter *ad =
2718                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2719
2720         if (ad->tx_simple_allowed) {
2721                 if (ad->tx_vec_allowed)
2722                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2723                 else
2724                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2725         } else {
2726                 return i40e_tx_done_cleanup_full(q, free_cnt);
2727         }
2728 }
2729
2730 void
2731 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2732 {
2733         struct i40e_tx_entry *txe;
2734         uint16_t i, prev, size;
2735
2736         if (!txq) {
2737                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2738                 return;
2739         }
2740
2741         txe = txq->sw_ring;
2742         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2743         for (i = 0; i < size; i++)
2744                 ((volatile char *)txq->tx_ring)[i] = 0;
2745
2746         prev = (uint16_t)(txq->nb_tx_desc - 1);
2747         for (i = 0; i < txq->nb_tx_desc; i++) {
2748                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2749
2750                 txd->cmd_type_offset_bsz =
2751                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2752                 txe[i].mbuf =  NULL;
2753                 txe[i].last_id = i;
2754                 txe[prev].next_id = i;
2755                 prev = i;
2756         }
2757
2758         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2759         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2760
2761         txq->tx_tail = 0;
2762         txq->nb_tx_used = 0;
2763
2764         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2765         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2766 }
2767
2768 /* Init the TX queue in hardware */
2769 int
2770 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2771 {
2772         enum i40e_status_code err = I40E_SUCCESS;
2773         struct i40e_vsi *vsi = txq->vsi;
2774         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2775         uint16_t pf_q = txq->reg_idx;
2776         struct i40e_hmc_obj_txq tx_ctx;
2777         uint32_t qtx_ctl;
2778
2779         /* clear the context structure first */
2780         memset(&tx_ctx, 0, sizeof(tx_ctx));
2781         tx_ctx.new_context = 1;
2782         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2783         tx_ctx.qlen = txq->nb_tx_desc;
2784
2785 #ifdef RTE_LIBRTE_IEEE1588
2786         tx_ctx.timesync_ena = 1;
2787 #endif
2788         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2789         if (vsi->type == I40E_VSI_FDIR)
2790                 tx_ctx.fd_ena = TRUE;
2791
2792         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2793         if (err != I40E_SUCCESS) {
2794                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2795                 return err;
2796         }
2797
2798         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2799         if (err != I40E_SUCCESS) {
2800                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2801                 return err;
2802         }
2803
2804         /* Now associate this queue with this PCI function */
2805         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2806         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2807                                         I40E_QTX_CTL_PF_INDX_MASK);
2808         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2809         I40E_WRITE_FLUSH(hw);
2810
2811         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2812
2813         return err;
2814 }
2815
2816 int
2817 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2818 {
2819         struct i40e_rx_entry *rxe = rxq->sw_ring;
2820         uint64_t dma_addr;
2821         uint16_t i;
2822
2823         for (i = 0; i < rxq->nb_rx_desc; i++) {
2824                 volatile union i40e_rx_desc *rxd;
2825                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2826
2827                 if (unlikely(!mbuf)) {
2828                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2829                         return -ENOMEM;
2830                 }
2831
2832                 rte_mbuf_refcnt_set(mbuf, 1);
2833                 mbuf->next = NULL;
2834                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2835                 mbuf->nb_segs = 1;
2836                 mbuf->port = rxq->port_id;
2837
2838                 dma_addr =
2839                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2840
2841                 rxd = &rxq->rx_ring[i];
2842                 rxd->read.pkt_addr = dma_addr;
2843                 rxd->read.hdr_addr = 0;
2844 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2845                 rxd->read.rsvd1 = 0;
2846                 rxd->read.rsvd2 = 0;
2847 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2848
2849                 rxe[i].mbuf = mbuf;
2850         }
2851
2852         return 0;
2853 }
2854
2855 /*
2856  * Calculate the buffer length, and check the jumbo frame
2857  * and maximum packet length.
2858  */
2859 static int
2860 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2861 {
2862         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2863         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2864         struct rte_eth_dev_data *data = pf->dev_data;
2865         uint16_t buf_size;
2866
2867         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2868                 RTE_PKTMBUF_HEADROOM);
2869
2870         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2871                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2872         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2873                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2874                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2875                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2876                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2877                 rxq->hs_mode = i40e_header_split_enabled;
2878                 break;
2879         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2880         default:
2881                 rxq->rx_hdr_len = 0;
2882                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2883                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2884                 rxq->hs_mode = i40e_header_split_none;
2885                 break;
2886         }
2887
2888         rxq->max_pkt_len =
2889                 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2890                         rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2891         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2892                 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
2893                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2894                         PMD_DRV_LOG(ERR, "maximum packet length must "
2895                                     "be larger than %u and smaller than %u,"
2896                                     "as jumbo frame is enabled",
2897                                     (uint32_t)I40E_ETH_MAX_LEN,
2898                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2899                         return I40E_ERR_CONFIG;
2900                 }
2901         } else {
2902                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2903                         rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
2904                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2905                                     "larger than %u and smaller than %u, "
2906                                     "as jumbo frame is disabled",
2907                                     (uint32_t)RTE_ETHER_MIN_LEN,
2908                                     (uint32_t)I40E_ETH_MAX_LEN);
2909                         return I40E_ERR_CONFIG;
2910                 }
2911         }
2912
2913         return 0;
2914 }
2915
2916 /* Init the RX queue in hardware */
2917 int
2918 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2919 {
2920         int err = I40E_SUCCESS;
2921         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2922         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2923         uint16_t pf_q = rxq->reg_idx;
2924         uint16_t buf_size;
2925         struct i40e_hmc_obj_rxq rx_ctx;
2926
2927         err = i40e_rx_queue_config(rxq);
2928         if (err < 0) {
2929                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2930                 return err;
2931         }
2932
2933         /* Clear the context structure first */
2934         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2935         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2936         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2937
2938         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2939         rx_ctx.qlen = rxq->nb_rx_desc;
2940 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2941         rx_ctx.dsize = 1;
2942 #endif
2943         rx_ctx.dtype = rxq->hs_mode;
2944         if (rxq->hs_mode)
2945                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2946         else
2947                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2948         rx_ctx.rxmax = rxq->max_pkt_len;
2949         rx_ctx.tphrdesc_ena = 1;
2950         rx_ctx.tphwdesc_ena = 1;
2951         rx_ctx.tphdata_ena = 1;
2952         rx_ctx.tphhead_ena = 1;
2953         rx_ctx.lrxqthresh = 2;
2954         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2955         rx_ctx.l2tsel = 1;
2956         /* showiv indicates if inner VLAN is stripped inside of tunnel
2957          * packet. When set it to 1, vlan information is stripped from
2958          * the inner header, but the hardware does not put it in the
2959          * descriptor. So set it zero by default.
2960          */
2961         rx_ctx.showiv = 0;
2962         rx_ctx.prefena = 1;
2963
2964         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2965         if (err != I40E_SUCCESS) {
2966                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2967                 return err;
2968         }
2969         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2970         if (err != I40E_SUCCESS) {
2971                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2972                 return err;
2973         }
2974
2975         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2976
2977         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2978                 RTE_PKTMBUF_HEADROOM);
2979
2980         /* Check if scattered RX needs to be used. */
2981         if (rxq->max_pkt_len > buf_size)
2982                 dev_data->scattered_rx = 1;
2983
2984         /* Init the RX tail regieter. */
2985         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2986
2987         return 0;
2988 }
2989
2990 void
2991 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2992 {
2993         uint16_t i;
2994
2995         PMD_INIT_FUNC_TRACE();
2996
2997         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2998                 if (!dev->data->tx_queues[i])
2999                         continue;
3000                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3001                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3002         }
3003
3004         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3005                 if (!dev->data->rx_queues[i])
3006                         continue;
3007                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3008                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3009         }
3010 }
3011
3012 void
3013 i40e_dev_free_queues(struct rte_eth_dev *dev)
3014 {
3015         uint16_t i;
3016
3017         PMD_INIT_FUNC_TRACE();
3018
3019         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3020                 if (!dev->data->rx_queues[i])
3021                         continue;
3022                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3023                 dev->data->rx_queues[i] = NULL;
3024                 rte_eth_dma_zone_free(dev, "rx_ring", i);
3025         }
3026
3027         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3028                 if (!dev->data->tx_queues[i])
3029                         continue;
3030                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3031                 dev->data->tx_queues[i] = NULL;
3032                 rte_eth_dma_zone_free(dev, "tx_ring", i);
3033         }
3034 }
3035
3036 enum i40e_status_code
3037 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3038 {
3039         struct i40e_tx_queue *txq;
3040         const struct rte_memzone *tz = NULL;
3041         struct rte_eth_dev *dev;
3042         uint32_t ring_size;
3043
3044         if (!pf) {
3045                 PMD_DRV_LOG(ERR, "PF is not available");
3046                 return I40E_ERR_BAD_PTR;
3047         }
3048
3049         dev = pf->adapter->eth_dev;
3050
3051         /* Allocate the TX queue data structure. */
3052         txq = rte_zmalloc_socket("i40e fdir tx queue",
3053                                   sizeof(struct i40e_tx_queue),
3054                                   RTE_CACHE_LINE_SIZE,
3055                                   SOCKET_ID_ANY);
3056         if (!txq) {
3057                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3058                                         "tx queue structure.");
3059                 return I40E_ERR_NO_MEMORY;
3060         }
3061
3062         /* Allocate TX hardware ring descriptors. */
3063         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3064         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3065
3066         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3067                                       I40E_FDIR_QUEUE_ID, ring_size,
3068                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3069         if (!tz) {
3070                 i40e_dev_tx_queue_release(txq);
3071                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3072                 return I40E_ERR_NO_MEMORY;
3073         }
3074
3075         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3076         txq->queue_id = I40E_FDIR_QUEUE_ID;
3077         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3078         txq->vsi = pf->fdir.fdir_vsi;
3079
3080         txq->tx_ring_phys_addr = tz->iova;
3081         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3082
3083         /*
3084          * don't need to allocate software ring and reset for the fdir
3085          * program queue just set the queue has been configured.
3086          */
3087         txq->q_set = TRUE;
3088         pf->fdir.txq = txq;
3089         pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3090
3091         return I40E_SUCCESS;
3092 }
3093
3094 enum i40e_status_code
3095 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3096 {
3097         struct i40e_rx_queue *rxq;
3098         const struct rte_memzone *rz = NULL;
3099         uint32_t ring_size;
3100         struct rte_eth_dev *dev;
3101
3102         if (!pf) {
3103                 PMD_DRV_LOG(ERR, "PF is not available");
3104                 return I40E_ERR_BAD_PTR;
3105         }
3106
3107         dev = pf->adapter->eth_dev;
3108
3109         /* Allocate the RX queue data structure. */
3110         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3111                                   sizeof(struct i40e_rx_queue),
3112                                   RTE_CACHE_LINE_SIZE,
3113                                   SOCKET_ID_ANY);
3114         if (!rxq) {
3115                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3116                                         "rx queue structure.");
3117                 return I40E_ERR_NO_MEMORY;
3118         }
3119
3120         /* Allocate RX hardware ring descriptors. */
3121         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3122         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3123
3124         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3125                                       I40E_FDIR_QUEUE_ID, ring_size,
3126                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3127         if (!rz) {
3128                 i40e_dev_rx_queue_release(rxq);
3129                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3130                 return I40E_ERR_NO_MEMORY;
3131         }
3132
3133         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3134         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3135         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3136         rxq->vsi = pf->fdir.fdir_vsi;
3137
3138         rxq->rx_ring_phys_addr = rz->iova;
3139         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3140         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3141
3142         /*
3143          * Don't need to allocate software ring and reset for the fdir
3144          * rx queue, just set the queue has been configured.
3145          */
3146         rxq->q_set = TRUE;
3147         pf->fdir.rxq = rxq;
3148
3149         return I40E_SUCCESS;
3150 }
3151
3152 void
3153 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3154         struct rte_eth_rxq_info *qinfo)
3155 {
3156         struct i40e_rx_queue *rxq;
3157
3158         rxq = dev->data->rx_queues[queue_id];
3159
3160         qinfo->mp = rxq->mp;
3161         qinfo->scattered_rx = dev->data->scattered_rx;
3162         qinfo->nb_desc = rxq->nb_rx_desc;
3163
3164         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3165         qinfo->conf.rx_drop_en = rxq->drop_en;
3166         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3167         qinfo->conf.offloads = rxq->offloads;
3168 }
3169
3170 void
3171 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3172         struct rte_eth_txq_info *qinfo)
3173 {
3174         struct i40e_tx_queue *txq;
3175
3176         txq = dev->data->tx_queues[queue_id];
3177
3178         qinfo->nb_desc = txq->nb_tx_desc;
3179
3180         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3181         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3182         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3183
3184         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3185         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3186         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3187         qinfo->conf.offloads = txq->offloads;
3188 }
3189
3190 static inline bool
3191 get_avx_supported(bool request_avx512)
3192 {
3193 #ifdef RTE_ARCH_X86
3194         if (request_avx512) {
3195                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3196                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3197                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3198 #ifdef CC_AVX512_SUPPORT
3199                         return true;
3200 #else
3201                 PMD_DRV_LOG(NOTICE,
3202                         "AVX512 is not supported in build env");
3203                 return false;
3204 #endif
3205         } else {
3206                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3207                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3208                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3209 #ifdef CC_AVX2_SUPPORT
3210                         return true;
3211 #else
3212                 PMD_DRV_LOG(NOTICE,
3213                         "AVX2 is not supported in build env");
3214                 return false;
3215 #endif
3216         }
3217 #else
3218         RTE_SET_USED(request_avx512);
3219 #endif /* RTE_ARCH_X86 */
3220
3221         return false;
3222 }
3223
3224
3225 void __rte_cold
3226 i40e_set_rx_function(struct rte_eth_dev *dev)
3227 {
3228         struct i40e_adapter *ad =
3229                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3230         uint16_t rx_using_sse, i;
3231         /* In order to allow Vector Rx there are a few configuration
3232          * conditions to be met and Rx Bulk Allocation should be allowed.
3233          */
3234         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3235 #ifdef RTE_ARCH_X86
3236                 ad->rx_use_avx512 = false;
3237                 ad->rx_use_avx2 = false;
3238 #endif
3239                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3240                     !ad->rx_bulk_alloc_allowed) {
3241                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3242                                      " Vector Rx preconditions",
3243                                      dev->data->port_id);
3244
3245                         ad->rx_vec_allowed = false;
3246                 }
3247                 if (ad->rx_vec_allowed) {
3248                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3249                                 struct i40e_rx_queue *rxq =
3250                                         dev->data->rx_queues[i];
3251
3252                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3253                                         ad->rx_vec_allowed = false;
3254                                         break;
3255                                 }
3256                         }
3257 #ifdef RTE_ARCH_X86
3258                         ad->rx_use_avx512 = get_avx_supported(1);
3259
3260                         if (!ad->rx_use_avx512)
3261                                 ad->rx_use_avx2 = get_avx_supported(0);
3262 #endif
3263                 }
3264         }
3265
3266         if (ad->rx_vec_allowed  &&
3267             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3268 #ifdef RTE_ARCH_X86
3269                 if (dev->data->scattered_rx) {
3270                         if (ad->rx_use_avx512) {
3271 #ifdef CC_AVX512_SUPPORT
3272                                 PMD_DRV_LOG(NOTICE,
3273                                         "Using AVX512 Vector Scattered Rx (port %d).",
3274                                         dev->data->port_id);
3275                                 dev->rx_pkt_burst =
3276                                         i40e_recv_scattered_pkts_vec_avx512;
3277 #endif
3278                         } else {
3279                                 PMD_INIT_LOG(DEBUG,
3280                                         "Using %sVector Scattered Rx (port %d).",
3281                                         ad->rx_use_avx2 ? "avx2 " : "",
3282                                         dev->data->port_id);
3283                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3284                                         i40e_recv_scattered_pkts_vec_avx2 :
3285                                         i40e_recv_scattered_pkts_vec;
3286                         }
3287                 } else {
3288                         if (ad->rx_use_avx512) {
3289 #ifdef CC_AVX512_SUPPORT
3290                                 PMD_DRV_LOG(NOTICE,
3291                                         "Using AVX512 Vector Rx (port %d).",
3292                                         dev->data->port_id);
3293                                 dev->rx_pkt_burst =
3294                                         i40e_recv_pkts_vec_avx512;
3295 #endif
3296                         } else {
3297                                 PMD_INIT_LOG(DEBUG,
3298                                         "Using %sVector Rx (port %d).",
3299                                         ad->rx_use_avx2 ? "avx2 " : "",
3300                                         dev->data->port_id);
3301                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3302                                         i40e_recv_pkts_vec_avx2 :
3303                                         i40e_recv_pkts_vec;
3304                         }
3305                 }
3306 #else /* RTE_ARCH_X86 */
3307                 if (dev->data->scattered_rx) {
3308                         PMD_INIT_LOG(DEBUG,
3309                                      "Using Vector Scattered Rx (port %d).",
3310                                      dev->data->port_id);
3311                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3312                 } else {
3313                         PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3314                                      dev->data->port_id);
3315                         dev->rx_pkt_burst = i40e_recv_pkts_vec;
3316                 }
3317 #endif /* RTE_ARCH_X86 */
3318         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3319                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3320                                     "satisfied. Rx Burst Bulk Alloc function "
3321                                     "will be used on port=%d.",
3322                              dev->data->port_id);
3323
3324                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3325         } else {
3326                 /* Simple Rx Path. */
3327                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3328                              dev->data->port_id);
3329                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3330                                         i40e_recv_scattered_pkts :
3331                                         i40e_recv_pkts;
3332         }
3333
3334         /* Propagate information about RX function choice through all queues. */
3335         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3336                 rx_using_sse =
3337                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3338                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3339 #ifdef CC_AVX512_SUPPORT
3340                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3341                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3342 #endif
3343                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3344                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3345
3346                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3347                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3348
3349                         if (rxq)
3350                                 rxq->rx_using_sse = rx_using_sse;
3351                 }
3352         }
3353 }
3354
3355 static const struct {
3356         eth_rx_burst_t pkt_burst;
3357         const char *info;
3358 } i40e_rx_burst_infos[] = {
3359         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3360         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3361         { i40e_recv_pkts,                    "Scalar" },
3362 #ifdef RTE_ARCH_X86
3363 #ifdef CC_AVX512_SUPPORT
3364         { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3365         { i40e_recv_pkts_vec_avx512,           "Vector AVX512" },
3366 #endif
3367         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3368         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3369         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3370         { i40e_recv_pkts_vec,                "Vector SSE" },
3371 #elif defined(RTE_ARCH_ARM64)
3372         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3373         { i40e_recv_pkts_vec,                "Vector Neon" },
3374 #elif defined(RTE_ARCH_PPC_64)
3375         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3376         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3377 #endif
3378 };
3379
3380 int
3381 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3382                        struct rte_eth_burst_mode *mode)
3383 {
3384         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3385         int ret = -EINVAL;
3386         unsigned int i;
3387
3388         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3389                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3390                         snprintf(mode->info, sizeof(mode->info), "%s",
3391                                  i40e_rx_burst_infos[i].info);
3392                         ret = 0;
3393                         break;
3394                 }
3395         }
3396
3397         return ret;
3398 }
3399
3400 void __rte_cold
3401 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3402 {
3403         struct i40e_adapter *ad =
3404                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3405
3406         /* Use a simple Tx queue if possible (only fast free is allowed) */
3407         ad->tx_simple_allowed =
3408                 (txq->offloads ==
3409                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3410                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3411         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3412                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3413
3414         if (ad->tx_vec_allowed)
3415                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3416                                 txq->queue_id);
3417         else if (ad->tx_simple_allowed)
3418                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3419                                 txq->queue_id);
3420         else
3421                 PMD_INIT_LOG(DEBUG,
3422                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3423                                 txq->queue_id);
3424 }
3425
3426 void __rte_cold
3427 i40e_set_tx_function(struct rte_eth_dev *dev)
3428 {
3429         struct i40e_adapter *ad =
3430                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3431         int i;
3432
3433         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3434 #ifdef RTE_ARCH_X86
3435                 ad->tx_use_avx2 = false;
3436                 ad->tx_use_avx512 = false;
3437 #endif
3438                 if (ad->tx_vec_allowed) {
3439                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3440                                 struct i40e_tx_queue *txq =
3441                                         dev->data->tx_queues[i];
3442
3443                                 if (txq && i40e_txq_vec_setup(txq)) {
3444                                         ad->tx_vec_allowed = false;
3445                                         break;
3446                                 }
3447                         }
3448 #ifdef RTE_ARCH_X86
3449                         ad->tx_use_avx512 = get_avx_supported(1);
3450
3451                         if (!ad->tx_use_avx512)
3452                                 ad->tx_use_avx2 = get_avx_supported(0);
3453 #endif
3454                 }
3455         }
3456
3457         if (ad->tx_simple_allowed) {
3458                 if (ad->tx_vec_allowed &&
3459                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3460 #ifdef RTE_ARCH_X86
3461                         if (ad->tx_use_avx512) {
3462 #ifdef CC_AVX512_SUPPORT
3463                                 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3464                                             dev->data->port_id);
3465                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3466 #endif
3467                         } else {
3468                                 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3469                                              ad->tx_use_avx2 ? "avx2 " : "",
3470                                              dev->data->port_id);
3471                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3472                                                     i40e_xmit_pkts_vec_avx2 :
3473                                                     i40e_xmit_pkts_vec;
3474                         }
3475 #else /* RTE_ARCH_X86 */
3476                         PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3477                                      dev->data->port_id);
3478                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3479 #endif /* RTE_ARCH_X86 */
3480                 } else {
3481                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3482                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3483                 }
3484                 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3485         } else {
3486                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3487                 dev->tx_pkt_burst = i40e_xmit_pkts;
3488                 dev->tx_pkt_prepare = i40e_prep_pkts;
3489         }
3490 }
3491
3492 static const struct {
3493         eth_tx_burst_t pkt_burst;
3494         const char *info;
3495 } i40e_tx_burst_infos[] = {
3496         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3497         { i40e_xmit_pkts,          "Scalar" },
3498 #ifdef RTE_ARCH_X86
3499 #ifdef CC_AVX512_SUPPORT
3500         { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3501 #endif
3502         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3503         { i40e_xmit_pkts_vec,      "Vector SSE" },
3504 #elif defined(RTE_ARCH_ARM64)
3505         { i40e_xmit_pkts_vec,      "Vector Neon" },
3506 #elif defined(RTE_ARCH_PPC_64)
3507         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3508 #endif
3509 };
3510
3511 int
3512 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3513                        struct rte_eth_burst_mode *mode)
3514 {
3515         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3516         int ret = -EINVAL;
3517         unsigned int i;
3518
3519         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3520                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3521                         snprintf(mode->info, sizeof(mode->info), "%s",
3522                                  i40e_tx_burst_infos[i].info);
3523                         ret = 0;
3524                         break;
3525                 }
3526         }
3527
3528         return ret;
3529 }
3530
3531 void __rte_cold
3532 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3533 {
3534         struct i40e_adapter *ad =
3535                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3536         int i;
3537
3538         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3539                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3540 }
3541
3542 void __rte_cold
3543 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3544 {
3545         struct i40e_adapter *ad =
3546                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3547         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548         int i;
3549
3550         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3551                 ad->pctypes_tbl[i] = 0ULL;
3552         ad->flow_types_mask = 0ULL;
3553         ad->pctypes_mask = 0ULL;
3554
3555         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3556                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3557         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3558                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3559         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3560                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3561         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3562                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3563         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3564                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3565         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3566                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3567         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3568                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3569         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3570                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3571         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3572                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3573         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3574                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3575         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3576                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3577
3578         if (hw->mac.type == I40E_MAC_X722 ||
3579                 hw->mac.type == I40E_MAC_X722_VF) {
3580                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3581                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3582                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3583                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3584                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3585                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3586                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3587                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3588                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3589                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3590                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3591                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3592         }
3593
3594         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3595                 if (ad->pctypes_tbl[i])
3596                         ad->flow_types_mask |= (1ULL << i);
3597                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3598         }
3599 }
3600
3601 #ifndef CC_AVX2_SUPPORT
3602 uint16_t
3603 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3604                         struct rte_mbuf __rte_unused **rx_pkts,
3605                         uint16_t __rte_unused nb_pkts)
3606 {
3607         return 0;
3608 }
3609
3610 uint16_t
3611 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3612                         struct rte_mbuf __rte_unused **rx_pkts,
3613                         uint16_t __rte_unused nb_pkts)
3614 {
3615         return 0;
3616 }
3617
3618 uint16_t
3619 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3620                           struct rte_mbuf __rte_unused **tx_pkts,
3621                           uint16_t __rte_unused nb_pkts)
3622 {
3623         return 0;
3624 }
3625 #endif /* ifndef CC_AVX2_SUPPORT */