drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 #ifdef RTE_LIBRTE_IEEE1588
  46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  47 #else
  48 #define I40E_TX_IEEE1588_TMST 0
  49 #endif
  50
  51 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  52                 PKT_TX_IP_CKSUM |                \
  53                 PKT_TX_L4_MASK |                 \
  54                 PKT_TX_TCP_SEG |                 \
  55                 PKT_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (  \
  58                 PKT_TX_OUTER_IPV4 |     \
  59                 PKT_TX_OUTER_IPV6 |     \
  60                 PKT_TX_IPV4 |           \
  61                 PKT_TX_IPV6 |           \
  62                 PKT_TX_IP_CKSUM |       \
  63                 PKT_TX_L4_MASK |        \
  64                 PKT_TX_OUTER_IP_CKSUM | \
  65                 PKT_TX_TCP_SEG |        \
  66                 PKT_TX_QINQ_PKT |       \
  67                 PKT_TX_VLAN_PKT |       \
  68                 PKT_TX_TUNNEL_MASK |    \
  69                 I40E_TX_IEEE1588_TMST)
  70
  71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  72                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  73
  74 static inline void
  75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  76 {
  77         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  78                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  79                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  80                 mb->vlan_tci =
  81                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  82                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  83                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  84         } else {
  85                 mb->vlan_tci = 0;
  86         }
  87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  88         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  89                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
  91                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
  92                 mb->vlan_tci_outer = mb->vlan_tci;
  93                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  96                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  97         } else {
  98                 mb->vlan_tci_outer = 0;
  99         }
 100 #endif
 101         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 102                    mb->vlan_tci, mb->vlan_tci_outer);
 103 }
 104
 105 /* Translate the rx descriptor status to pkt flags */
 106 static inline uint64_t
 107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 108 {
 109         uint64_t flags;
 110
 111         /* Check if RSS_HASH */
 112         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 113                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 114                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 115
 116         /* Check if FDIR Match */
 117         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 118                                                         PKT_RX_FDIR : 0);
 119
 120         return flags;
 121 }
 122
 123 static inline uint64_t
 124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 125 {
 126         uint64_t flags = 0;
 127         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 128
 129 #define I40E_RX_ERR_BITS 0x3f
 130         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 131                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 132                 return flags;
 133         }
 134
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 136                 flags |= PKT_RX_IP_CKSUM_BAD;
 137         else
 138                 flags |= PKT_RX_IP_CKSUM_GOOD;
 139
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 141                 flags |= PKT_RX_L4_CKSUM_BAD;
 142         else
 143                 flags |= PKT_RX_L4_CKSUM_GOOD;
 144
 145         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 146                 flags |= PKT_RX_EIP_CKSUM_BAD;
 147
 148         return flags;
 149 }
 150
 151 /* Function to check and set the ieee1588 timesync index and get the
 152  * appropriate flags.
 153  */
 154 #ifdef RTE_LIBRTE_IEEE1588
 155 static inline uint64_t
 156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 157 {
 158         uint64_t pkt_flags = 0;
 159         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 160                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 161                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 162
 163         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 164                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 165                 pkt_flags = PKT_RX_IEEE1588_PTP;
 166         if (tsyn & 0x04) {
 167                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 168                 mb->timesync = tsyn & 0x03;
 169         }
 170
 171         return pkt_flags;
 172 }
 173 #endif
 174
 175 static inline uint64_t
 176 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 177 {
 178         uint64_t flags = 0;
 179 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 180         uint16_t flexbh, flexbl;
 181
 182         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 183                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 184                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 185         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 186                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 187                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 188
 189
 190         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 191                 mb->hash.fdir.hi =
 192                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 193                 flags |= PKT_RX_FDIR_ID;
 194         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 195                 mb->hash.fdir.hi =
 196                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 197                 flags |= PKT_RX_FDIR_FLX;
 198         }
 199         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 200                 mb->hash.fdir.lo =
 201                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 202                 flags |= PKT_RX_FDIR_FLX;
 203         }
 204 #else
 205         mb->hash.fdir.hi =
 206                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 207         flags |= PKT_RX_FDIR_ID;
 208 #endif
 209         return flags;
 210 }
 211
 212 static inline void
 213 i40e_parse_tunneling_params(uint64_t ol_flags,
 214                             union i40e_tx_offload tx_offload,
 215                             uint32_t *cd_tunneling)
 216 {
 217         /* EIPT: External (outer) IP header type */
 218         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 219                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 220         else if (ol_flags & PKT_TX_OUTER_IPV4)
 221                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 222         else if (ol_flags & PKT_TX_OUTER_IPV6)
 223                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 224
 225         /* EIPLEN: External (outer) IP header length, in DWords */
 226         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 227                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 228
 229         /* L4TUNT: L4 Tunneling Type */
 230         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 231         case PKT_TX_TUNNEL_IPIP:
 232                 /* for non UDP / GRE tunneling, set to 00b */
 233                 break;
 234         case PKT_TX_TUNNEL_VXLAN:
 235         case PKT_TX_TUNNEL_GENEVE:
 236                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 237                 break;
 238         case PKT_TX_TUNNEL_GRE:
 239                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 240                 break;
 241         default:
 242                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 243                 return;
 244         }
 245
 246         /* L4TUNLEN: L4 Tunneling Length, in Words
 247          *
 248          * We depend on app to set rte_mbuf.l2_len correctly.
 249          * For IP in GRE it should be set to the length of the GRE
 250          * header;
 251          * for MAC in GRE or MAC in UDP it should be set to the length
 252          * of the GRE or UDP headers plus the inner MAC up to including
 253          * its last Ethertype.
 254          */
 255         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 256                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 257 }
 258
 259 static inline void
 260 i40e_txd_enable_checksum(uint64_t ol_flags,
 261                         uint32_t *td_cmd,
 262                         uint32_t *td_offset,
 263                         union i40e_tx_offload tx_offload)
 264 {
 265         /* Set MACLEN */
 266         if (ol_flags & PKT_TX_TUNNEL_MASK)
 267                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 268                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 269         else
 270                 *td_offset |= (tx_offload.l2_len >> 1)
 271                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 272
 273         /* Enable L3 checksum offloads */
 274         if (ol_flags & PKT_TX_IP_CKSUM) {
 275                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 276                 *td_offset |= (tx_offload.l3_len >> 2)
 277                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 278         } else if (ol_flags & PKT_TX_IPV4) {
 279                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 280                 *td_offset |= (tx_offload.l3_len >> 2)
 281                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 282         } else if (ol_flags & PKT_TX_IPV6) {
 283                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 284                 *td_offset |= (tx_offload.l3_len >> 2)
 285                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 286         }
 287
 288         if (ol_flags & PKT_TX_TCP_SEG) {
 289                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 290                 *td_offset |= (tx_offload.l4_len >> 2)
 291                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 292                 return;
 293         }
 294
 295         /* Enable L4 checksum offloads */
 296         switch (ol_flags & PKT_TX_L4_MASK) {
 297         case PKT_TX_TCP_CKSUM:
 298                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 299                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 300                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 301                 break;
 302         case PKT_TX_SCTP_CKSUM:
 303                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 304                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 305                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 306                 break;
 307         case PKT_TX_UDP_CKSUM:
 308                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 309                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 310                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 311                 break;
 312         default:
 313                 break;
 314         }
 315 }
 316
 317 /* Construct the tx flags */
 318 static inline uint64_t
 319 i40e_build_ctob(uint32_t td_cmd,
 320                 uint32_t td_offset,
 321                 unsigned int size,
 322                 uint32_t td_tag)
 323 {
 324         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 325                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 326                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 327                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 328                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 329 }
 330
 331 static inline int
 332 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 333 {
 334         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 335         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 336         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 337         uint16_t nb_tx_desc = txq->nb_tx_desc;
 338         uint16_t desc_to_clean_to;
 339         uint16_t nb_tx_to_clean;
 340
 341         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 342         if (desc_to_clean_to >= nb_tx_desc)
 343                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 344
 345         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 346         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 347                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 348                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 349                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 350                         "(port=%d queue=%d)", desc_to_clean_to,
 351                                 txq->port_id, txq->queue_id);
 352                 return -1;
 353         }
 354
 355         if (last_desc_cleaned > desc_to_clean_to)
 356                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 357                                                         desc_to_clean_to);
 358         else
 359                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 360                                         last_desc_cleaned);
 361
 362         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 363
 364         txq->last_desc_cleaned = desc_to_clean_to;
 365         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 366
 367         return 0;
 368 }
 369
 370 static inline int
 371 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 372 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 373 #else
 374 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 375 #endif
 376 {
 377         int ret = 0;
 378
 379 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 380         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 381                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 382                              "rxq->rx_free_thresh=%d, "
 383                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 384                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 385                 ret = -EINVAL;
 386         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 387                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 388                              "rxq->rx_free_thresh=%d, "
 389                              "rxq->nb_rx_desc=%d",
 390                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 391                 ret = -EINVAL;
 392         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 393                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 394                              "rxq->nb_rx_desc=%d, "
 395                              "rxq->rx_free_thresh=%d",
 396                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 397                 ret = -EINVAL;
 398         }
 399 #else
 400         ret = -EINVAL;
 401 #endif
 402
 403         return ret;
 404 }
 405
 406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 407 #define I40E_LOOK_AHEAD 8
 408 #if (I40E_LOOK_AHEAD != 8)
 409 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 410 #endif
 411 static inline int
 412 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 413 {
 414         volatile union i40e_rx_desc *rxdp;
 415         struct i40e_rx_entry *rxep;
 416         struct rte_mbuf *mb;
 417         uint16_t pkt_len;
 418         uint64_t qword1;
 419         uint32_t rx_status;
 420         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 421         int32_t i, j, nb_rx = 0;
 422         uint64_t pkt_flags;
 423         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 424
 425         rxdp = &rxq->rx_ring[rxq->rx_tail];
 426         rxep = &rxq->sw_ring[rxq->rx_tail];
 427
 428         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 429         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 430                                 I40E_RXD_QW1_STATUS_SHIFT;
 431
 432         /* Make sure there is at least 1 packet to receive */
 433         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 434                 return 0;
 435
 436         /**
 437          * Scan LOOK_AHEAD descriptors at a time to determine which
 438          * descriptors reference packets that are ready to be received.
 439          */
 440         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 441                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 442                 /* Read desc statuses backwards to avoid race condition */
 443                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 444                         qword1 = rte_le_to_cpu_64(\
 445                                 rxdp[j].wb.qword1.status_error_len);
 446                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 447                                         I40E_RXD_QW1_STATUS_SHIFT;
 448                 }
 449
 450                 rte_smp_rmb();
 451
 452                 /* Compute how many status bits were set */
 453                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 454                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 455
 456                 nb_rx += nb_dd;
 457
 458                 /* Translate descriptor info to mbuf parameters */
 459                 for (j = 0; j < nb_dd; j++) {
 460                         mb = rxep[j].mbuf;
 461                         qword1 = rte_le_to_cpu_64(\
 462                                 rxdp[j].wb.qword1.status_error_len);
 463                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 464                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 465                         mb->data_len = pkt_len;
 466                         mb->pkt_len = pkt_len;
 467                         mb->ol_flags = 0;
 468                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 469                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 470                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 471                         mb->packet_type =
 472                                 ptype_tbl[(uint8_t)((qword1 &
 473                                 I40E_RXD_QW1_PTYPE_MASK) >>
 474                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 475                         if (pkt_flags & PKT_RX_RSS_HASH)
 476                                 mb->hash.rss = rte_le_to_cpu_32(\
 477                                         rxdp[j].wb.qword0.hi_dword.rss);
 478                         if (pkt_flags & PKT_RX_FDIR)
 479                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 480
 481 #ifdef RTE_LIBRTE_IEEE1588
 482                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 483 #endif
 484                         mb->ol_flags |= pkt_flags;
 485
 486                 }
 487
 488                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 489                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 490
 491                 if (nb_dd != I40E_LOOK_AHEAD)
 492                         break;
 493         }
 494
 495         /* Clear software ring entries */
 496         for (i = 0; i < nb_rx; i++)
 497                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 498
 499         return nb_rx;
 500 }
 501
 502 static inline uint16_t
 503 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 504                         struct rte_mbuf **rx_pkts,
 505                         uint16_t nb_pkts)
 506 {
 507         uint16_t i;
 508         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 509
 510         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 511
 512         for (i = 0; i < nb_pkts; i++)
 513                 rx_pkts[i] = stage[i];
 514
 515         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 516         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 517
 518         return nb_pkts;
 519 }
 520
 521 static inline int
 522 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 523 {
 524         volatile union i40e_rx_desc *rxdp;
 525         struct i40e_rx_entry *rxep;
 526         struct rte_mbuf *mb;
 527         uint16_t alloc_idx, i;
 528         uint64_t dma_addr;
 529         int diag;
 530
 531         /* Allocate buffers in bulk */
 532         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 533                                 (rxq->rx_free_thresh - 1));
 534         rxep = &(rxq->sw_ring[alloc_idx]);
 535         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 536                                         rxq->rx_free_thresh);
 537         if (unlikely(diag != 0)) {
 538                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 539                 return -ENOMEM;
 540         }
 541
 542         rxdp = &rxq->rx_ring[alloc_idx];
 543         for (i = 0; i < rxq->rx_free_thresh; i++) {
 544                 if (likely(i < (rxq->rx_free_thresh - 1)))
 545                         /* Prefetch next mbuf */
 546                         rte_prefetch0(rxep[i + 1].mbuf);
 547
 548                 mb = rxep[i].mbuf;
 549                 rte_mbuf_refcnt_set(mb, 1);
 550                 mb->next = NULL;
 551                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 552                 mb->nb_segs = 1;
 553                 mb->port = rxq->port_id;
 554                 dma_addr = rte_cpu_to_le_64(\
 555                         rte_mbuf_data_iova_default(mb));
 556                 rxdp[i].read.hdr_addr = 0;
 557                 rxdp[i].read.pkt_addr = dma_addr;
 558         }
 559
 560         /* Update rx tail regsiter */
 561         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 562
 563         rxq->rx_free_trigger =
 564                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 565         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 566                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 567
 568         return 0;
 569 }
 570
 571 static inline uint16_t
 572 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 573 {
 574         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 575         struct rte_eth_dev *dev;
 576         uint16_t nb_rx = 0;
 577
 578         if (!nb_pkts)
 579                 return 0;
 580
 581         if (rxq->rx_nb_avail)
 582                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 583
 584         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 585         rxq->rx_next_avail = 0;
 586         rxq->rx_nb_avail = nb_rx;
 587         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 588
 589         if (rxq->rx_tail > rxq->rx_free_trigger) {
 590                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 591                         uint16_t i, j;
 592
 593                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 594                         dev->data->rx_mbuf_alloc_failed +=
 595                                 rxq->rx_free_thresh;
 596
 597                         rxq->rx_nb_avail = 0;
 598                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 599                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 600                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 601
 602                         return 0;
 603                 }
 604         }
 605
 606         if (rxq->rx_tail >= rxq->nb_rx_desc)
 607                 rxq->rx_tail = 0;
 608
 609         if (rxq->rx_nb_avail)
 610                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 611
 612         return 0;
 613 }
 614
 615 static uint16_t
 616 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 617                           struct rte_mbuf **rx_pkts,
 618                           uint16_t nb_pkts)
 619 {
 620         uint16_t nb_rx = 0, n, count;
 621
 622         if (unlikely(nb_pkts == 0))
 623                 return 0;
 624
 625         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 626                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 627
 628         while (nb_pkts) {
 629                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 630                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 631                 nb_rx = (uint16_t)(nb_rx + count);
 632                 nb_pkts = (uint16_t)(nb_pkts - count);
 633                 if (count < n)
 634                         break;
 635         }
 636
 637         return nb_rx;
 638 }
 639 #else
 640 static uint16_t
 641 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 642                           struct rte_mbuf __rte_unused **rx_pkts,
 643                           uint16_t __rte_unused nb_pkts)
 644 {
 645         return 0;
 646 }
 647 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 648
 649 uint16_t
 650 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 651 {
 652         struct i40e_rx_queue *rxq;
 653         volatile union i40e_rx_desc *rx_ring;
 654         volatile union i40e_rx_desc *rxdp;
 655         union i40e_rx_desc rxd;
 656         struct i40e_rx_entry *sw_ring;
 657         struct i40e_rx_entry *rxe;
 658         struct rte_eth_dev *dev;
 659         struct rte_mbuf *rxm;
 660         struct rte_mbuf *nmb;
 661         uint16_t nb_rx;
 662         uint32_t rx_status;
 663         uint64_t qword1;
 664         uint16_t rx_packet_len;
 665         uint16_t rx_id, nb_hold;
 666         uint64_t dma_addr;
 667         uint64_t pkt_flags;
 668         uint32_t *ptype_tbl;
 669
 670         nb_rx = 0;
 671         nb_hold = 0;
 672         rxq = rx_queue;
 673         rx_id = rxq->rx_tail;
 674         rx_ring = rxq->rx_ring;
 675         sw_ring = rxq->sw_ring;
 676         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 677
 678         while (nb_rx < nb_pkts) {
 679                 rxdp = &rx_ring[rx_id];
 680                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 681                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 682                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 683
 684                 /* Check the DD bit first */
 685                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 686                         break;
 687
 688                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 689                 if (unlikely(!nmb)) {
 690                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 691                         dev->data->rx_mbuf_alloc_failed++;
 692                         break;
 693                 }
 694
 695                 rxd = *rxdp;
 696                 nb_hold++;
 697                 rxe = &sw_ring[rx_id];
 698                 rx_id++;
 699                 if (unlikely(rx_id == rxq->nb_rx_desc))
 700                         rx_id = 0;
 701
 702                 /* Prefetch next mbuf */
 703                 rte_prefetch0(sw_ring[rx_id].mbuf);
 704
 705                 /**
 706                  * When next RX descriptor is on a cache line boundary,
 707                  * prefetch the next 4 RX descriptors and next 8 pointers
 708                  * to mbufs.
 709                  */
 710                 if ((rx_id & 0x3) == 0) {
 711                         rte_prefetch0(&rx_ring[rx_id]);
 712                         rte_prefetch0(&sw_ring[rx_id]);
 713                 }
 714                 rxm = rxe->mbuf;
 715                 rxe->mbuf = nmb;
 716                 dma_addr =
 717                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 718                 rxdp->read.hdr_addr = 0;
 719                 rxdp->read.pkt_addr = dma_addr;
 720
 721                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 722                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 723
 724                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 725                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 726                 rxm->nb_segs = 1;
 727                 rxm->next = NULL;
 728                 rxm->pkt_len = rx_packet_len;
 729                 rxm->data_len = rx_packet_len;
 730                 rxm->port = rxq->port_id;
 731                 rxm->ol_flags = 0;
 732                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 733                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 734                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 735                 rxm->packet_type =
 736                         ptype_tbl[(uint8_t)((qword1 &
 737                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 738                 if (pkt_flags & PKT_RX_RSS_HASH)
 739                         rxm->hash.rss =
 740                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 741                 if (pkt_flags & PKT_RX_FDIR)
 742                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 743
 744 #ifdef RTE_LIBRTE_IEEE1588
 745                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 746 #endif
 747                 rxm->ol_flags |= pkt_flags;
 748
 749                 rx_pkts[nb_rx++] = rxm;
 750         }
 751         rxq->rx_tail = rx_id;
 752
 753         /**
 754          * If the number of free RX descriptors is greater than the RX free
 755          * threshold of the queue, advance the receive tail register of queue.
 756          * Update that register with the value of the last processed RX
 757          * descriptor minus 1.
 758          */
 759         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 760         if (nb_hold > rxq->rx_free_thresh) {
 761                 rx_id = (uint16_t) ((rx_id == 0) ?
 762                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 763                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 764                 nb_hold = 0;
 765         }
 766         rxq->nb_rx_hold = nb_hold;
 767
 768         return nb_rx;
 769 }
 770
 771 uint16_t
 772 i40e_recv_scattered_pkts(void *rx_queue,
 773                          struct rte_mbuf **rx_pkts,
 774                          uint16_t nb_pkts)
 775 {
 776         struct i40e_rx_queue *rxq = rx_queue;
 777         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 778         volatile union i40e_rx_desc *rxdp;
 779         union i40e_rx_desc rxd;
 780         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 781         struct i40e_rx_entry *rxe;
 782         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 783         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 784         struct rte_mbuf *nmb, *rxm;
 785         uint16_t rx_id = rxq->rx_tail;
 786         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 787         struct rte_eth_dev *dev;
 788         uint32_t rx_status;
 789         uint64_t qword1;
 790         uint64_t dma_addr;
 791         uint64_t pkt_flags;
 792         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 793
 794         while (nb_rx < nb_pkts) {
 795                 rxdp = &rx_ring[rx_id];
 796                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 797                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 798                                         I40E_RXD_QW1_STATUS_SHIFT;
 799
 800                 /* Check the DD bit */
 801                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 802                         break;
 803
 804                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 805                 if (unlikely(!nmb)) {
 806                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 807                         dev->data->rx_mbuf_alloc_failed++;
 808                         break;
 809                 }
 810
 811                 rxd = *rxdp;
 812                 nb_hold++;
 813                 rxe = &sw_ring[rx_id];
 814                 rx_id++;
 815                 if (rx_id == rxq->nb_rx_desc)
 816                         rx_id = 0;
 817
 818                 /* Prefetch next mbuf */
 819                 rte_prefetch0(sw_ring[rx_id].mbuf);
 820
 821                 /**
 822                  * When next RX descriptor is on a cache line boundary,
 823                  * prefetch the next 4 RX descriptors and next 8 pointers
 824                  * to mbufs.
 825                  */
 826                 if ((rx_id & 0x3) == 0) {
 827                         rte_prefetch0(&rx_ring[rx_id]);
 828                         rte_prefetch0(&sw_ring[rx_id]);
 829                 }
 830
 831                 rxm = rxe->mbuf;
 832                 rxe->mbuf = nmb;
 833                 dma_addr =
 834                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 835
 836                 /* Set data buffer address and data length of the mbuf */
 837                 rxdp->read.hdr_addr = 0;
 838                 rxdp->read.pkt_addr = dma_addr;
 839                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 840                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 841                 rxm->data_len = rx_packet_len;
 842                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 843
 844                 /**
 845                  * If this is the first buffer of the received packet, set the
 846                  * pointer to the first mbuf of the packet and initialize its
 847                  * context. Otherwise, update the total length and the number
 848                  * of segments of the current scattered packet, and update the
 849                  * pointer to the last mbuf of the current packet.
 850                  */
 851                 if (!first_seg) {
 852                         first_seg = rxm;
 853                         first_seg->nb_segs = 1;
 854                         first_seg->pkt_len = rx_packet_len;
 855                 } else {
 856                         first_seg->pkt_len =
 857                                 (uint16_t)(first_seg->pkt_len +
 858                                                 rx_packet_len);
 859                         first_seg->nb_segs++;
 860                         last_seg->next = rxm;
 861                 }
 862
 863                 /**
 864                  * If this is not the last buffer of the received packet,
 865                  * update the pointer to the last mbuf of the current scattered
 866                  * packet and continue to parse the RX ring.
 867                  */
 868                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 869                         last_seg = rxm;
 870                         continue;
 871                 }
 872
 873                 /**
 874                  * This is the last buffer of the received packet. If the CRC
 875                  * is not stripped by the hardware:
 876                  *  - Subtract the CRC length from the total packet length.
 877                  *  - If the last buffer only contains the whole CRC or a part
 878                  *  of it, free the mbuf associated to the last buffer. If part
 879                  *  of the CRC is also contained in the previous mbuf, subtract
 880                  *  the length of that CRC part from the data length of the
 881                  *  previous mbuf.
 882                  */
 883                 rxm->next = NULL;
 884                 if (unlikely(rxq->crc_len > 0)) {
 885                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 886                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 887                                 rte_pktmbuf_free_seg(rxm);
 888                                 first_seg->nb_segs--;
 889                                 last_seg->data_len =
 890                                         (uint16_t)(last_seg->data_len -
 891                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 892                                 last_seg->next = NULL;
 893                         } else
 894                                 rxm->data_len = (uint16_t)(rx_packet_len -
 895                                                         RTE_ETHER_CRC_LEN);
 896                 }
 897
 898                 first_seg->port = rxq->port_id;
 899                 first_seg->ol_flags = 0;
 900                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 901                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 902                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 903                 first_seg->packet_type =
 904                         ptype_tbl[(uint8_t)((qword1 &
 905                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 906                 if (pkt_flags & PKT_RX_RSS_HASH)
 907                         first_seg->hash.rss =
 908                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 909                 if (pkt_flags & PKT_RX_FDIR)
 910                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 911
 912 #ifdef RTE_LIBRTE_IEEE1588
 913                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 914 #endif
 915                 first_seg->ol_flags |= pkt_flags;
 916
 917                 /* Prefetch data of first segment, if configured to do so. */
 918                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 919                         first_seg->data_off));
 920                 rx_pkts[nb_rx++] = first_seg;
 921                 first_seg = NULL;
 922         }
 923
 924         /* Record index of the next RX descriptor to probe. */
 925         rxq->rx_tail = rx_id;
 926         rxq->pkt_first_seg = first_seg;
 927         rxq->pkt_last_seg = last_seg;
 928
 929         /**
 930          * If the number of free RX descriptors is greater than the RX free
 931          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 932          * register. Update the RDT with the value of the last processed RX
 933          * descriptor minus 1, to guarantee that the RDT register is never
 934          * equal to the RDH register, which creates a "full" ring situtation
 935          * from the hardware point of view.
 936          */
 937         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 938         if (nb_hold > rxq->rx_free_thresh) {
 939                 rx_id = (uint16_t)(rx_id == 0 ?
 940                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 941                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 942                 nb_hold = 0;
 943         }
 944         rxq->nb_rx_hold = nb_hold;
 945
 946         return nb_rx;
 947 }
 948
 949 /* Check if the context descriptor is needed for TX offloading */
 950 static inline uint16_t
 951 i40e_calc_context_desc(uint64_t flags)
 952 {
 953         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 954                 PKT_TX_TCP_SEG |
 955                 PKT_TX_QINQ_PKT |
 956                 PKT_TX_TUNNEL_MASK;
 957
 958 #ifdef RTE_LIBRTE_IEEE1588
 959         mask |= PKT_TX_IEEE1588_TMST;
 960 #endif
 961
 962         return (flags & mask) ? 1 : 0;
 963 }
 964
 965 /* set i40e TSO context descriptor */
 966 static inline uint64_t
 967 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 968 {
 969         uint64_t ctx_desc = 0;
 970         uint32_t cd_cmd, hdr_len, cd_tso_len;
 971
 972         if (!tx_offload.l4_len) {
 973                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 974                 return ctx_desc;
 975         }
 976
 977         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
 978         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
 979                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
 980
 981         cd_cmd = I40E_TX_CTX_DESC_TSO;
 982         cd_tso_len = mbuf->pkt_len - hdr_len;
 983         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 984                 ((uint64_t)cd_tso_len <<
 985                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 986                 ((uint64_t)mbuf->tso_segsz <<
 987                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 988
 989         return ctx_desc;
 990 }
 991
 992 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
 993 #define I40E_MAX_DATA_PER_TXD \
 994         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 995 /* Calculate the number of TX descriptors needed for each pkt */
 996 static inline uint16_t
 997 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
 998 {
 999         struct rte_mbuf *txd = tx_pkt;
1000         uint16_t count = 0;
1001
1002         while (txd != NULL) {
1003                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1004                 txd = txd->next;
1005         }
1006
1007         return count;
1008 }
1009
1010 uint16_t
1011 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1012 {
1013         struct i40e_tx_queue *txq;
1014         struct i40e_tx_entry *sw_ring;
1015         struct i40e_tx_entry *txe, *txn;
1016         volatile struct i40e_tx_desc *txd;
1017         volatile struct i40e_tx_desc *txr;
1018         struct rte_mbuf *tx_pkt;
1019         struct rte_mbuf *m_seg;
1020         uint32_t cd_tunneling_params;
1021         uint16_t tx_id;
1022         uint16_t nb_tx;
1023         uint32_t td_cmd;
1024         uint32_t td_offset;
1025         uint32_t td_tag;
1026         uint64_t ol_flags;
1027         uint16_t nb_used;
1028         uint16_t nb_ctx;
1029         uint16_t tx_last;
1030         uint16_t slen;
1031         uint64_t buf_dma_addr;
1032         union i40e_tx_offload tx_offload = {0};
1033
1034         txq = tx_queue;
1035         sw_ring = txq->sw_ring;
1036         txr = txq->tx_ring;
1037         tx_id = txq->tx_tail;
1038         txe = &sw_ring[tx_id];
1039
1040         /* Check if the descriptor ring needs to be cleaned. */
1041         if (txq->nb_tx_free < txq->tx_free_thresh)
1042                 (void)i40e_xmit_cleanup(txq);
1043
1044         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1045                 td_cmd = 0;
1046                 td_tag = 0;
1047                 td_offset = 0;
1048
1049                 tx_pkt = *tx_pkts++;
1050                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1051
1052                 ol_flags = tx_pkt->ol_flags;
1053                 tx_offload.l2_len = tx_pkt->l2_len;
1054                 tx_offload.l3_len = tx_pkt->l3_len;
1055                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1056                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1057                 tx_offload.l4_len = tx_pkt->l4_len;
1058                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1059
1060                 /* Calculate the number of context descriptors needed. */
1061                 nb_ctx = i40e_calc_context_desc(ol_flags);
1062
1063                 /**
1064                  * The number of descriptors that must be allocated for
1065                  * a packet equals to the number of the segments of that
1066                  * packet plus 1 context descriptor if needed.
1067                  * Recalculate the needed tx descs when TSO enabled in case
1068                  * the mbuf data size exceeds max data size that hw allows
1069                  * per tx desc.
1070                  */
1071                 if (ol_flags & PKT_TX_TCP_SEG)
1072                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1073                                              nb_ctx);
1074                 else
1075                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1076                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1077
1078                 /* Circular ring */
1079                 if (tx_last >= txq->nb_tx_desc)
1080                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1081
1082                 if (nb_used > txq->nb_tx_free) {
1083                         if (i40e_xmit_cleanup(txq) != 0) {
1084                                 if (nb_tx == 0)
1085                                         return 0;
1086                                 goto end_of_tx;
1087                         }
1088                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1089                                 while (nb_used > txq->nb_tx_free) {
1090                                         if (i40e_xmit_cleanup(txq) != 0) {
1091                                                 if (nb_tx == 0)
1092                                                         return 0;
1093                                                 goto end_of_tx;
1094                                         }
1095                                 }
1096                         }
1097                 }
1098
1099                 /* Descriptor based VLAN insertion */
1100                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1101                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1102                         td_tag = tx_pkt->vlan_tci;
1103                 }
1104
1105                 /* Always enable CRC offload insertion */
1106                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1107
1108                 /* Fill in tunneling parameters if necessary */
1109                 cd_tunneling_params = 0;
1110                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1111                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1112                                                     &cd_tunneling_params);
1113                 /* Enable checksum offloading */
1114                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1115                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1116                                                  &td_offset, tx_offload);
1117
1118                 if (nb_ctx) {
1119                         /* Setup TX context descriptor if required */
1120                         volatile struct i40e_tx_context_desc *ctx_txd =
1121                                 (volatile struct i40e_tx_context_desc *)\
1122                                                         &txr[tx_id];
1123                         uint16_t cd_l2tag2 = 0;
1124                         uint64_t cd_type_cmd_tso_mss =
1125                                 I40E_TX_DESC_DTYPE_CONTEXT;
1126
1127                         txn = &sw_ring[txe->next_id];
1128                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1129                         if (txe->mbuf != NULL) {
1130                                 rte_pktmbuf_free_seg(txe->mbuf);
1131                                 txe->mbuf = NULL;
1132                         }
1133
1134                         /* TSO enabled means no timestamp */
1135                         if (ol_flags & PKT_TX_TCP_SEG)
1136                                 cd_type_cmd_tso_mss |=
1137                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1138                         else {
1139 #ifdef RTE_LIBRTE_IEEE1588
1140                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1141                                         cd_type_cmd_tso_mss |=
1142                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1143                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1144 #endif
1145                         }
1146
1147                         ctx_txd->tunneling_params =
1148                                 rte_cpu_to_le_32(cd_tunneling_params);
1149                         if (ol_flags & PKT_TX_QINQ_PKT) {
1150                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1151                                 cd_type_cmd_tso_mss |=
1152                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1153                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1154                         }
1155                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1156                         ctx_txd->type_cmd_tso_mss =
1157                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1158
1159                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1160                                 "tunneling_params: %#x;\n"
1161                                 "l2tag2: %#hx;\n"
1162                                 "rsvd: %#hx;\n"
1163                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1164                                 tx_pkt, tx_id,
1165                                 ctx_txd->tunneling_params,
1166                                 ctx_txd->l2tag2,
1167                                 ctx_txd->rsvd,
1168                                 ctx_txd->type_cmd_tso_mss);
1169
1170                         txe->last_id = tx_last;
1171                         tx_id = txe->next_id;
1172                         txe = txn;
1173                 }
1174
1175                 m_seg = tx_pkt;
1176                 do {
1177                         txd = &txr[tx_id];
1178                         txn = &sw_ring[txe->next_id];
1179
1180                         if (txe->mbuf)
1181                                 rte_pktmbuf_free_seg(txe->mbuf);
1182                         txe->mbuf = m_seg;
1183
1184                         /* Setup TX Descriptor */
1185                         slen = m_seg->data_len;
1186                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1187
1188                         while ((ol_flags & PKT_TX_TCP_SEG) &&
1189                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1190                                 txd->buffer_addr =
1191                                         rte_cpu_to_le_64(buf_dma_addr);
1192                                 txd->cmd_type_offset_bsz =
1193                                         i40e_build_ctob(td_cmd,
1194                                         td_offset, I40E_MAX_DATA_PER_TXD,
1195                                         td_tag);
1196
1197                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1198                                 slen -= I40E_MAX_DATA_PER_TXD;
1199
1200                                 txe->last_id = tx_last;
1201                                 tx_id = txe->next_id;
1202                                 txe = txn;
1203                                 txd = &txr[tx_id];
1204                                 txn = &sw_ring[txe->next_id];
1205                         }
1206                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1207                                 "buf_dma_addr: %#"PRIx64";\n"
1208                                 "td_cmd: %#x;\n"
1209                                 "td_offset: %#x;\n"
1210                                 "td_len: %u;\n"
1211                                 "td_tag: %#x;\n",
1212                                 tx_pkt, tx_id, buf_dma_addr,
1213                                 td_cmd, td_offset, slen, td_tag);
1214
1215                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1216                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1217                                                 td_offset, slen, td_tag);
1218                         txe->last_id = tx_last;
1219                         tx_id = txe->next_id;
1220                         txe = txn;
1221                         m_seg = m_seg->next;
1222                 } while (m_seg != NULL);
1223
1224                 /* The last packet data descriptor needs End Of Packet (EOP) */
1225                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1226                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1227                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1228
1229                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1230                         PMD_TX_FREE_LOG(DEBUG,
1231                                         "Setting RS bit on TXD id="
1232                                         "%4u (port=%d queue=%d)",
1233                                         tx_last, txq->port_id, txq->queue_id);
1234
1235                         td_cmd |= I40E_TX_DESC_CMD_RS;
1236
1237                         /* Update txq RS bit counters */
1238                         txq->nb_tx_used = 0;
1239                 }
1240
1241                 txd->cmd_type_offset_bsz |=
1242                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1243                                         I40E_TXD_QW1_CMD_SHIFT);
1244         }
1245
1246 end_of_tx:
1247         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1248                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1249                    (unsigned) tx_id, (unsigned) nb_tx);
1250
1251         rte_cio_wmb();
1252         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1253         txq->tx_tail = tx_id;
1254
1255         return nb_tx;
1256 }
1257
1258 static __rte_always_inline int
1259 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1260 {
1261         struct i40e_tx_entry *txep;
1262         uint16_t i;
1263
1264         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1265                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1266                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1267                 return 0;
1268
1269         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1270
1271         for (i = 0; i < txq->tx_rs_thresh; i++)
1272                 rte_prefetch0((txep + i)->mbuf);
1273
1274         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1275                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1276                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1277                         txep->mbuf = NULL;
1278                 }
1279         } else {
1280                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1281                         rte_pktmbuf_free_seg(txep->mbuf);
1282                         txep->mbuf = NULL;
1283                 }
1284         }
1285
1286         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1287         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1288         if (txq->tx_next_dd >= txq->nb_tx_desc)
1289                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1290
1291         return txq->tx_rs_thresh;
1292 }
1293
1294 /* Populate 4 descriptors with data from 4 mbufs */
1295 static inline void
1296 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1297 {
1298         uint64_t dma_addr;
1299         uint32_t i;
1300
1301         for (i = 0; i < 4; i++, txdp++, pkts++) {
1302                 dma_addr = rte_mbuf_data_iova(*pkts);
1303                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1304                 txdp->cmd_type_offset_bsz =
1305                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1306                                         (*pkts)->data_len, 0);
1307         }
1308 }
1309
1310 /* Populate 1 descriptor with data from 1 mbuf */
1311 static inline void
1312 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1313 {
1314         uint64_t dma_addr;
1315
1316         dma_addr = rte_mbuf_data_iova(*pkts);
1317         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1318         txdp->cmd_type_offset_bsz =
1319                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1320                                 (*pkts)->data_len, 0);
1321 }
1322
1323 /* Fill hardware descriptor ring with mbuf data */
1324 static inline void
1325 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1326                      struct rte_mbuf **pkts,
1327                      uint16_t nb_pkts)
1328 {
1329         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1330         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1331         const int N_PER_LOOP = 4;
1332         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1333         int mainpart, leftover;
1334         int i, j;
1335
1336         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1337         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1338         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1339                 for (j = 0; j < N_PER_LOOP; ++j) {
1340                         (txep + i + j)->mbuf = *(pkts + i + j);
1341                 }
1342                 tx4(txdp + i, pkts + i);
1343         }
1344         if (unlikely(leftover > 0)) {
1345                 for (i = 0; i < leftover; ++i) {
1346                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1347                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1348                 }
1349         }
1350 }
1351
1352 static inline uint16_t
1353 tx_xmit_pkts(struct i40e_tx_queue *txq,
1354              struct rte_mbuf **tx_pkts,
1355              uint16_t nb_pkts)
1356 {
1357         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1358         uint16_t n = 0;
1359
1360         /**
1361          * Begin scanning the H/W ring for done descriptors when the number
1362          * of available descriptors drops below tx_free_thresh. For each done
1363          * descriptor, free the associated buffer.
1364          */
1365         if (txq->nb_tx_free < txq->tx_free_thresh)
1366                 i40e_tx_free_bufs(txq);
1367
1368         /* Use available descriptor only */
1369         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1370         if (unlikely(!nb_pkts))
1371                 return 0;
1372
1373         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1374         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1375                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1376                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1377                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1378                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1379                                                 I40E_TXD_QW1_CMD_SHIFT);
1380                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1381                 txq->tx_tail = 0;
1382         }
1383
1384         /* Fill hardware descriptor ring with mbuf data */
1385         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1386         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1387
1388         /* Determin if RS bit needs to be set */
1389         if (txq->tx_tail > txq->tx_next_rs) {
1390                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1391                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1392                                                 I40E_TXD_QW1_CMD_SHIFT);
1393                 txq->tx_next_rs =
1394                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1395                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1396                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1397         }
1398
1399         if (txq->tx_tail >= txq->nb_tx_desc)
1400                 txq->tx_tail = 0;
1401
1402         /* Update the tx tail register */
1403         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1404
1405         return nb_pkts;
1406 }
1407
1408 static uint16_t
1409 i40e_xmit_pkts_simple(void *tx_queue,
1410                       struct rte_mbuf **tx_pkts,
1411                       uint16_t nb_pkts)
1412 {
1413         uint16_t nb_tx = 0;
1414
1415         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1416                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1417                                                 tx_pkts, nb_pkts);
1418
1419         while (nb_pkts) {
1420                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1421                                                 I40E_TX_MAX_BURST);
1422
1423                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1424                                                 &tx_pkts[nb_tx], num);
1425                 nb_tx = (uint16_t)(nb_tx + ret);
1426                 nb_pkts = (uint16_t)(nb_pkts - ret);
1427                 if (ret < num)
1428                         break;
1429         }
1430
1431         return nb_tx;
1432 }
1433
1434 static uint16_t
1435 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1436                    uint16_t nb_pkts)
1437 {
1438         uint16_t nb_tx = 0;
1439         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1440
1441         while (nb_pkts) {
1442                 uint16_t ret, num;
1443
1444                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1445                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1446                                                 num);
1447                 nb_tx += ret;
1448                 nb_pkts -= ret;
1449                 if (ret < num)
1450                         break;
1451         }
1452
1453         return nb_tx;
1454 }
1455
1456 /*********************************************************************
1457  *
1458  *  TX prep functions
1459  *
1460  **********************************************************************/
1461 uint16_t
1462 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1463                 uint16_t nb_pkts)
1464 {
1465         int i, ret;
1466         uint64_t ol_flags;
1467         struct rte_mbuf *m;
1468
1469         for (i = 0; i < nb_pkts; i++) {
1470                 m = tx_pkts[i];
1471                 ol_flags = m->ol_flags;
1472
1473                 /* Check for m->nb_segs to not exceed the limits. */
1474                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1475                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1476                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1477                                 rte_errno = EINVAL;
1478                                 return i;
1479                         }
1480                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1481                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1482                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1483                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1484                         /* MSS outside the range (256B - 9674B) are considered
1485                          * malicious
1486                          */
1487                         rte_errno = EINVAL;
1488                         return i;
1489                 }
1490
1491                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1492                         rte_errno = ENOTSUP;
1493                         return i;
1494                 }
1495
1496                 /* check the size of packet */
1497                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1498                         rte_errno = EINVAL;
1499                         return i;
1500                 }
1501
1502 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1503                 ret = rte_validate_tx_offload(m);
1504                 if (ret != 0) {
1505                         rte_errno = -ret;
1506                         return i;
1507                 }
1508 #endif
1509                 ret = rte_net_intel_cksum_prepare(m);
1510                 if (ret != 0) {
1511                         rte_errno = -ret;
1512                         return i;
1513                 }
1514         }
1515         return i;
1516 }
1517
1518 /*
1519  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1520  * application used, which assume having sequential ones. But from driver's
1521  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1522  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1523  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1524  * use queue_idx from 0 to 95 to access queues, while real queue would be
1525  * different. This function will do a queue mapping to find VSI the queue
1526  * belongs to.
1527  */
1528 static struct i40e_vsi*
1529 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1530 {
1531         /* the queue in MAIN VSI range */
1532         if (queue_idx < pf->main_vsi->nb_qps)
1533                 return pf->main_vsi;
1534
1535         queue_idx -= pf->main_vsi->nb_qps;
1536
1537         /* queue_idx is greater than VMDQ VSIs range */
1538         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1539                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1540                 return NULL;
1541         }
1542
1543         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1544 }
1545
1546 static uint16_t
1547 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1548 {
1549         /* the queue in MAIN VSI range */
1550         if (queue_idx < pf->main_vsi->nb_qps)
1551                 return queue_idx;
1552
1553         /* It's VMDQ queues */
1554         queue_idx -= pf->main_vsi->nb_qps;
1555
1556         if (pf->nb_cfg_vmdq_vsi)
1557                 return queue_idx % pf->vmdq_nb_qps;
1558         else {
1559                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1560                 return (uint16_t)(-1);
1561         }
1562 }
1563
1564 int
1565 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1566 {
1567         struct i40e_rx_queue *rxq;
1568         int err;
1569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         PMD_INIT_FUNC_TRACE();
1572
1573         rxq = dev->data->rx_queues[rx_queue_id];
1574         if (!rxq || !rxq->q_set) {
1575                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1576                             rx_queue_id);
1577                 return -EINVAL;
1578         }
1579
1580         if (rxq->rx_deferred_start)
1581                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1582                             rx_queue_id);
1583
1584         err = i40e_alloc_rx_queue_mbufs(rxq);
1585         if (err) {
1586                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1587                 return err;
1588         }
1589
1590         /* Init the RX tail regieter. */
1591         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1592
1593         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1594         if (err) {
1595                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1596                             rx_queue_id);
1597
1598                 i40e_rx_queue_release_mbufs(rxq);
1599                 i40e_reset_rx_queue(rxq);
1600                 return err;
1601         }
1602         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1603
1604         return 0;
1605 }
1606
1607 int
1608 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1609 {
1610         struct i40e_rx_queue *rxq;
1611         int err;
1612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613
1614         rxq = dev->data->rx_queues[rx_queue_id];
1615         if (!rxq || !rxq->q_set) {
1616                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1617                                 rx_queue_id);
1618                 return -EINVAL;
1619         }
1620
1621         /*
1622          * rx_queue_id is queue id application refers to, while
1623          * rxq->reg_idx is the real queue index.
1624          */
1625         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1626         if (err) {
1627                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1628                             rx_queue_id);
1629                 return err;
1630         }
1631         i40e_rx_queue_release_mbufs(rxq);
1632         i40e_reset_rx_queue(rxq);
1633         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1634
1635         return 0;
1636 }
1637
1638 int
1639 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1640 {
1641         int err;
1642         struct i40e_tx_queue *txq;
1643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644
1645         PMD_INIT_FUNC_TRACE();
1646
1647         txq = dev->data->tx_queues[tx_queue_id];
1648         if (!txq || !txq->q_set) {
1649                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1650                             tx_queue_id);
1651                 return -EINVAL;
1652         }
1653
1654         if (txq->tx_deferred_start)
1655                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1656                             tx_queue_id);
1657
1658         /*
1659          * tx_queue_id is queue id application refers to, while
1660          * rxq->reg_idx is the real queue index.
1661          */
1662         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1663         if (err) {
1664                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1665                             tx_queue_id);
1666                 return err;
1667         }
1668         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1669
1670         return 0;
1671 }
1672
1673 int
1674 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1675 {
1676         struct i40e_tx_queue *txq;
1677         int err;
1678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679
1680         txq = dev->data->tx_queues[tx_queue_id];
1681         if (!txq || !txq->q_set) {
1682                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1683                         tx_queue_id);
1684                 return -EINVAL;
1685         }
1686
1687         /*
1688          * tx_queue_id is queue id application refers to, while
1689          * txq->reg_idx is the real queue index.
1690          */
1691         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1692         if (err) {
1693                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1694                             tx_queue_id);
1695                 return err;
1696         }
1697
1698         i40e_tx_queue_release_mbufs(txq);
1699         i40e_reset_tx_queue(txq);
1700         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1701
1702         return 0;
1703 }
1704
1705 const uint32_t *
1706 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1707 {
1708         static const uint32_t ptypes[] = {
1709                 /* refers to i40e_rxd_pkt_type_mapping() */
1710                 RTE_PTYPE_L2_ETHER,
1711                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1712                 RTE_PTYPE_L2_ETHER_LLDP,
1713                 RTE_PTYPE_L2_ETHER_ARP,
1714                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1715                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1716                 RTE_PTYPE_L4_FRAG,
1717                 RTE_PTYPE_L4_ICMP,
1718                 RTE_PTYPE_L4_NONFRAG,
1719                 RTE_PTYPE_L4_SCTP,
1720                 RTE_PTYPE_L4_TCP,
1721                 RTE_PTYPE_L4_UDP,
1722                 RTE_PTYPE_TUNNEL_GRENAT,
1723                 RTE_PTYPE_TUNNEL_IP,
1724                 RTE_PTYPE_INNER_L2_ETHER,
1725                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1726                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1727                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1728                 RTE_PTYPE_INNER_L4_FRAG,
1729                 RTE_PTYPE_INNER_L4_ICMP,
1730                 RTE_PTYPE_INNER_L4_NONFRAG,
1731                 RTE_PTYPE_INNER_L4_SCTP,
1732                 RTE_PTYPE_INNER_L4_TCP,
1733                 RTE_PTYPE_INNER_L4_UDP,
1734                 RTE_PTYPE_UNKNOWN
1735         };
1736
1737         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1738 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1739             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1740 #endif
1741             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1742             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1743             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1744             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1745             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1746                 return ptypes;
1747         return NULL;
1748 }
1749
1750 static int
1751 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1752 {
1753         uint16_t i;
1754
1755         for (i = 0; i < num; i++) {
1756                 if (i != idx && queues[i])
1757                         return 0;
1758         }
1759
1760         return 1;
1761 }
1762
1763 static int
1764 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1765                                 struct i40e_rx_queue *rxq)
1766 {
1767         struct i40e_adapter *ad =
1768                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1769         int use_def_burst_func =
1770                 check_rx_burst_bulk_alloc_preconditions(rxq);
1771         uint16_t buf_size =
1772                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1773                            RTE_PKTMBUF_HEADROOM);
1774         int use_scattered_rx =
1775                 (rxq->max_pkt_len > buf_size);
1776
1777         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1778                 PMD_DRV_LOG(ERR,
1779                             "Failed to do RX queue initialization");
1780                 return -EINVAL;
1781         }
1782
1783         if (i40e_dev_first_queue(rxq->queue_id,
1784                                  dev->data->rx_queues,
1785                                  dev->data->nb_rx_queues)) {
1786                 /**
1787                  * If it is the first queue to setup,
1788                  * set all flags to default and call
1789                  * i40e_set_rx_function.
1790                  */
1791                 ad->rx_bulk_alloc_allowed = true;
1792                 ad->rx_vec_allowed = true;
1793                 dev->data->scattered_rx = use_scattered_rx;
1794                 if (use_def_burst_func)
1795                         ad->rx_bulk_alloc_allowed = false;
1796                 i40e_set_rx_function(dev);
1797                 return 0;
1798         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1799                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1800                             " number %d of queue %d isn't power of 2",
1801                             rxq->nb_rx_desc, rxq->queue_id);
1802                 return -EINVAL;
1803         }
1804
1805         /* check bulk alloc conflict */
1806         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1807                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1808                 return -EINVAL;
1809         }
1810         /* check scatterred conflict */
1811         if (!dev->data->scattered_rx && use_scattered_rx) {
1812                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1813                 return -EINVAL;
1814         }
1815         /* check vector conflict */
1816         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1817                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1818                 return -EINVAL;
1819         }
1820
1821         return 0;
1822 }
1823
1824 int
1825 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1826                         uint16_t queue_idx,
1827                         uint16_t nb_desc,
1828                         unsigned int socket_id,
1829                         const struct rte_eth_rxconf *rx_conf,
1830                         struct rte_mempool *mp)
1831 {
1832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         struct i40e_adapter *ad =
1834                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1835         struct i40e_vsi *vsi;
1836         struct i40e_pf *pf = NULL;
1837         struct i40e_vf *vf = NULL;
1838         struct i40e_rx_queue *rxq;
1839         const struct rte_memzone *rz;
1840         uint32_t ring_size;
1841         uint16_t len, i;
1842         uint16_t reg_idx, base, bsf, tc_mapping;
1843         int q_offset, use_def_burst_func = 1;
1844         uint64_t offloads;
1845
1846         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1847
1848         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1849                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1850                 vsi = &vf->vsi;
1851                 if (!vsi)
1852                         return -EINVAL;
1853                 reg_idx = queue_idx;
1854         } else {
1855                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1856                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1857                 if (!vsi)
1858                         return -EINVAL;
1859                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1860                 if (q_offset < 0)
1861                         return -EINVAL;
1862                 reg_idx = vsi->base_queue + q_offset;
1863         }
1864
1865         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1866             (nb_desc > I40E_MAX_RING_DESC) ||
1867             (nb_desc < I40E_MIN_RING_DESC)) {
1868                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1869                             "invalid", nb_desc);
1870                 return -EINVAL;
1871         }
1872
1873         /* Free memory if needed */
1874         if (dev->data->rx_queues[queue_idx]) {
1875                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1876                 dev->data->rx_queues[queue_idx] = NULL;
1877         }
1878
1879         /* Allocate the rx queue data structure */
1880         rxq = rte_zmalloc_socket("i40e rx queue",
1881                                  sizeof(struct i40e_rx_queue),
1882                                  RTE_CACHE_LINE_SIZE,
1883                                  socket_id);
1884         if (!rxq) {
1885                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1886                             "rx queue data structure");
1887                 return -ENOMEM;
1888         }
1889         rxq->mp = mp;
1890         rxq->nb_rx_desc = nb_desc;
1891         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1892         rxq->queue_id = queue_idx;
1893         rxq->reg_idx = reg_idx;
1894         rxq->port_id = dev->data->port_id;
1895         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1896                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1897         else
1898                 rxq->crc_len = 0;
1899         rxq->drop_en = rx_conf->rx_drop_en;
1900         rxq->vsi = vsi;
1901         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1902         rxq->offloads = offloads;
1903
1904         /* Allocate the maximun number of RX ring hardware descriptor. */
1905         len = I40E_MAX_RING_DESC;
1906
1907         /**
1908          * Allocating a little more memory because vectorized/bulk_alloc Rx
1909          * functions doesn't check boundaries each time.
1910          */
1911         len += RTE_PMD_I40E_RX_MAX_BURST;
1912
1913         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1914                               I40E_DMA_MEM_ALIGN);
1915
1916         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1917                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1918         if (!rz) {
1919                 i40e_dev_rx_queue_release(rxq);
1920                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1921                 return -ENOMEM;
1922         }
1923
1924         /* Zero all the descriptors in the ring. */
1925         memset(rz->addr, 0, ring_size);
1926
1927         rxq->rx_ring_phys_addr = rz->iova;
1928         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1929
1930         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1931
1932         /* Allocate the software ring. */
1933         rxq->sw_ring =
1934                 rte_zmalloc_socket("i40e rx sw ring",
1935                                    sizeof(struct i40e_rx_entry) * len,
1936                                    RTE_CACHE_LINE_SIZE,
1937                                    socket_id);
1938         if (!rxq->sw_ring) {
1939                 i40e_dev_rx_queue_release(rxq);
1940                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1941                 return -ENOMEM;
1942         }
1943
1944         i40e_reset_rx_queue(rxq);
1945         rxq->q_set = TRUE;
1946
1947         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1948                 if (!(vsi->enabled_tc & (1 << i)))
1949                         continue;
1950                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1951                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1952                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1953                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1954                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1955
1956                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1957                         rxq->dcb_tc = i;
1958         }
1959
1960         if (dev->data->dev_started) {
1961                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1962                         i40e_dev_rx_queue_release(rxq);
1963                         return -EINVAL;
1964                 }
1965         } else {
1966                 use_def_burst_func =
1967                         check_rx_burst_bulk_alloc_preconditions(rxq);
1968                 if (!use_def_burst_func) {
1969 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1970                         PMD_INIT_LOG(DEBUG,
1971                           "Rx Burst Bulk Alloc Preconditions are "
1972                           "satisfied. Rx Burst Bulk Alloc function will be "
1973                           "used on port=%d, queue=%d.",
1974                           rxq->port_id, rxq->queue_id);
1975 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1976                 } else {
1977                         PMD_INIT_LOG(DEBUG,
1978                           "Rx Burst Bulk Alloc Preconditions are "
1979                           "not satisfied, Scattered Rx is requested, "
1980                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1981                           "not enabled on port=%d, queue=%d.",
1982                           rxq->port_id, rxq->queue_id);
1983                         ad->rx_bulk_alloc_allowed = false;
1984                 }
1985         }
1986
1987         dev->data->rx_queues[queue_idx] = rxq;
1988         return 0;
1989 }
1990
1991 void
1992 i40e_dev_rx_queue_release(void *rxq)
1993 {
1994         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1995
1996         if (!q) {
1997                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1998                 return;
1999         }
2000
2001         i40e_rx_queue_release_mbufs(q);
2002         rte_free(q->sw_ring);
2003         rte_free(q);
2004 }
2005
2006 uint32_t
2007 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2008 {
2009 #define I40E_RXQ_SCAN_INTERVAL 4
2010         volatile union i40e_rx_desc *rxdp;
2011         struct i40e_rx_queue *rxq;
2012         uint16_t desc = 0;
2013
2014         rxq = dev->data->rx_queues[rx_queue_id];
2015         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2016         while ((desc < rxq->nb_rx_desc) &&
2017                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2018                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2019                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2020                 /**
2021                  * Check the DD bit of a rx descriptor of each 4 in a group,
2022                  * to avoid checking too frequently and downgrading performance
2023                  * too much.
2024                  */
2025                 desc += I40E_RXQ_SCAN_INTERVAL;
2026                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2027                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2028                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2029                                         desc - rxq->nb_rx_desc]);
2030         }
2031
2032         return desc;
2033 }
2034
2035 int
2036 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2037 {
2038         volatile union i40e_rx_desc *rxdp;
2039         struct i40e_rx_queue *rxq = rx_queue;
2040         uint16_t desc;
2041         int ret;
2042
2043         if (unlikely(offset >= rxq->nb_rx_desc)) {
2044                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2045                 return 0;
2046         }
2047
2048         desc = rxq->rx_tail + offset;
2049         if (desc >= rxq->nb_rx_desc)
2050                 desc -= rxq->nb_rx_desc;
2051
2052         rxdp = &(rxq->rx_ring[desc]);
2053
2054         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2055                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2056                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2057
2058         return ret;
2059 }
2060
2061 int
2062 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2063 {
2064         struct i40e_rx_queue *rxq = rx_queue;
2065         volatile uint64_t *status;
2066         uint64_t mask;
2067         uint32_t desc;
2068
2069         if (unlikely(offset >= rxq->nb_rx_desc))
2070                 return -EINVAL;
2071
2072         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2073                 return RTE_ETH_RX_DESC_UNAVAIL;
2074
2075         desc = rxq->rx_tail + offset;
2076         if (desc >= rxq->nb_rx_desc)
2077                 desc -= rxq->nb_rx_desc;
2078
2079         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2080         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2081                 << I40E_RXD_QW1_STATUS_SHIFT);
2082         if (*status & mask)
2083                 return RTE_ETH_RX_DESC_DONE;
2084
2085         return RTE_ETH_RX_DESC_AVAIL;
2086 }
2087
2088 int
2089 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2090 {
2091         struct i40e_tx_queue *txq = tx_queue;
2092         volatile uint64_t *status;
2093         uint64_t mask, expect;
2094         uint32_t desc;
2095
2096         if (unlikely(offset >= txq->nb_tx_desc))
2097                 return -EINVAL;
2098
2099         desc = txq->tx_tail + offset;
2100         /* go to next desc that has the RS bit */
2101         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2102                 txq->tx_rs_thresh;
2103         if (desc >= txq->nb_tx_desc) {
2104                 desc -= txq->nb_tx_desc;
2105                 if (desc >= txq->nb_tx_desc)
2106                         desc -= txq->nb_tx_desc;
2107         }
2108
2109         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2110         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2111         expect = rte_cpu_to_le_64(
2112                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2113         if ((*status & mask) == expect)
2114                 return RTE_ETH_TX_DESC_DONE;
2115
2116         return RTE_ETH_TX_DESC_FULL;
2117 }
2118
2119 static int
2120 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2121                                 struct i40e_tx_queue *txq)
2122 {
2123         struct i40e_adapter *ad =
2124                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2125
2126         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2127                 PMD_DRV_LOG(ERR,
2128                             "Failed to do TX queue initialization");
2129                 return -EINVAL;
2130         }
2131
2132         if (i40e_dev_first_queue(txq->queue_id,
2133                                  dev->data->tx_queues,
2134                                  dev->data->nb_tx_queues)) {
2135                 /**
2136                  * If it is the first queue to setup,
2137                  * set all flags and call
2138                  * i40e_set_tx_function.
2139                  */
2140                 i40e_set_tx_function_flag(dev, txq);
2141                 i40e_set_tx_function(dev);
2142                 return 0;
2143         }
2144
2145         /* check vector conflict */
2146         if (ad->tx_vec_allowed) {
2147                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2148                     i40e_txq_vec_setup(txq)) {
2149                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2150                         return -EINVAL;
2151                 }
2152         }
2153         /* check simple tx conflict */
2154         if (ad->tx_simple_allowed) {
2155                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2156                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2157                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2158                         return -EINVAL;
2159                 }
2160         }
2161
2162         return 0;
2163 }
2164
2165 int
2166 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2167                         uint16_t queue_idx,
2168                         uint16_t nb_desc,
2169                         unsigned int socket_id,
2170                         const struct rte_eth_txconf *tx_conf)
2171 {
2172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct i40e_vsi *vsi;
2174         struct i40e_pf *pf = NULL;
2175         struct i40e_vf *vf = NULL;
2176         struct i40e_tx_queue *txq;
2177         const struct rte_memzone *tz;
2178         uint32_t ring_size;
2179         uint16_t tx_rs_thresh, tx_free_thresh;
2180         uint16_t reg_idx, i, base, bsf, tc_mapping;
2181         int q_offset;
2182         uint64_t offloads;
2183
2184         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2185
2186         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2187                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2188                 vsi = &vf->vsi;
2189                 if (!vsi)
2190                         return -EINVAL;
2191                 reg_idx = queue_idx;
2192         } else {
2193                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2195                 if (!vsi)
2196                         return -EINVAL;
2197                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2198                 if (q_offset < 0)
2199                         return -EINVAL;
2200                 reg_idx = vsi->base_queue + q_offset;
2201         }
2202
2203         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2204             (nb_desc > I40E_MAX_RING_DESC) ||
2205             (nb_desc < I40E_MIN_RING_DESC)) {
2206                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2207                             "invalid", nb_desc);
2208                 return -EINVAL;
2209         }
2210
2211         /**
2212          * The following two parameters control the setting of the RS bit on
2213          * transmit descriptors. TX descriptors will have their RS bit set
2214          * after txq->tx_rs_thresh descriptors have been used. The TX
2215          * descriptor ring will be cleaned after txq->tx_free_thresh
2216          * descriptors are used or if the number of descriptors required to
2217          * transmit a packet is greater than the number of free TX descriptors.
2218          *
2219          * The following constraints must be satisfied:
2220          *  - tx_rs_thresh must be greater than 0.
2221          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2222          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2223          *  - tx_rs_thresh must be a divisor of the ring size.
2224          *  - tx_free_thresh must be greater than 0.
2225          *  - tx_free_thresh must be less than the size of the ring minus 3.
2226          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2227          *
2228          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2229          * race condition, hence the maximum threshold constraints. When set
2230          * to zero use default values.
2231          */
2232         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2233                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2234         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2235         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2236                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2237         if (tx_conf->tx_rs_thresh > 0)
2238                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2239         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2240                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2241                                 "exceed nb_desc. (tx_rs_thresh=%u "
2242                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2243                                 (unsigned int)tx_rs_thresh,
2244                                 (unsigned int)tx_free_thresh,
2245                                 (unsigned int)nb_desc,
2246                                 (int)dev->data->port_id,
2247                                 (int)queue_idx);
2248                 return I40E_ERR_PARAM;
2249         }
2250         if (tx_rs_thresh >= (nb_desc - 2)) {
2251                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2252                              "number of TX descriptors minus 2. "
2253                              "(tx_rs_thresh=%u port=%d queue=%d)",
2254                              (unsigned int)tx_rs_thresh,
2255                              (int)dev->data->port_id,
2256                              (int)queue_idx);
2257                 return I40E_ERR_PARAM;
2258         }
2259         if (tx_free_thresh >= (nb_desc - 3)) {
2260                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2261                              "number of TX descriptors minus 3. "
2262                              "(tx_free_thresh=%u port=%d queue=%d)",
2263                              (unsigned int)tx_free_thresh,
2264                              (int)dev->data->port_id,
2265                              (int)queue_idx);
2266                 return I40E_ERR_PARAM;
2267         }
2268         if (tx_rs_thresh > tx_free_thresh) {
2269                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2270                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2271                              " tx_rs_thresh=%u port=%d queue=%d)",
2272                              (unsigned int)tx_free_thresh,
2273                              (unsigned int)tx_rs_thresh,
2274                              (int)dev->data->port_id,
2275                              (int)queue_idx);
2276                 return I40E_ERR_PARAM;
2277         }
2278         if ((nb_desc % tx_rs_thresh) != 0) {
2279                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2280                              "number of TX descriptors. (tx_rs_thresh=%u"
2281                              " port=%d queue=%d)",
2282                              (unsigned int)tx_rs_thresh,
2283                              (int)dev->data->port_id,
2284                              (int)queue_idx);
2285                 return I40E_ERR_PARAM;
2286         }
2287         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2288                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2289                              "tx_rs_thresh is greater than 1. "
2290                              "(tx_rs_thresh=%u port=%d queue=%d)",
2291                              (unsigned int)tx_rs_thresh,
2292                              (int)dev->data->port_id,
2293                              (int)queue_idx);
2294                 return I40E_ERR_PARAM;
2295         }
2296
2297         /* Free memory if needed. */
2298         if (dev->data->tx_queues[queue_idx]) {
2299                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2300                 dev->data->tx_queues[queue_idx] = NULL;
2301         }
2302
2303         /* Allocate the TX queue data structure. */
2304         txq = rte_zmalloc_socket("i40e tx queue",
2305                                   sizeof(struct i40e_tx_queue),
2306                                   RTE_CACHE_LINE_SIZE,
2307                                   socket_id);
2308         if (!txq) {
2309                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2310                             "tx queue structure");
2311                 return -ENOMEM;
2312         }
2313
2314         /* Allocate TX hardware ring descriptors. */
2315         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2316         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2317         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2318                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2319         if (!tz) {
2320                 i40e_dev_tx_queue_release(txq);
2321                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2322                 return -ENOMEM;
2323         }
2324
2325         txq->nb_tx_desc = nb_desc;
2326         txq->tx_rs_thresh = tx_rs_thresh;
2327         txq->tx_free_thresh = tx_free_thresh;
2328         txq->pthresh = tx_conf->tx_thresh.pthresh;
2329         txq->hthresh = tx_conf->tx_thresh.hthresh;
2330         txq->wthresh = tx_conf->tx_thresh.wthresh;
2331         txq->queue_id = queue_idx;
2332         txq->reg_idx = reg_idx;
2333         txq->port_id = dev->data->port_id;
2334         txq->offloads = offloads;
2335         txq->vsi = vsi;
2336         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2337
2338         txq->tx_ring_phys_addr = tz->iova;
2339         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2340
2341         /* Allocate software ring */
2342         txq->sw_ring =
2343                 rte_zmalloc_socket("i40e tx sw ring",
2344                                    sizeof(struct i40e_tx_entry) * nb_desc,
2345                                    RTE_CACHE_LINE_SIZE,
2346                                    socket_id);
2347         if (!txq->sw_ring) {
2348                 i40e_dev_tx_queue_release(txq);
2349                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2350                 return -ENOMEM;
2351         }
2352
2353         i40e_reset_tx_queue(txq);
2354         txq->q_set = TRUE;
2355
2356         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2357                 if (!(vsi->enabled_tc & (1 << i)))
2358                         continue;
2359                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2360                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2361                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2362                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2363                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2364
2365                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2366                         txq->dcb_tc = i;
2367         }
2368
2369         if (dev->data->dev_started) {
2370                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2371                         i40e_dev_tx_queue_release(txq);
2372                         return -EINVAL;
2373                 }
2374         } else {
2375                 /**
2376                  * Use a simple TX queue without offloads or
2377                  * multi segs if possible
2378                  */
2379                 i40e_set_tx_function_flag(dev, txq);
2380         }
2381         dev->data->tx_queues[queue_idx] = txq;
2382
2383         return 0;
2384 }
2385
2386 void
2387 i40e_dev_tx_queue_release(void *txq)
2388 {
2389         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2390
2391         if (!q) {
2392                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2393                 return;
2394         }
2395
2396         i40e_tx_queue_release_mbufs(q);
2397         rte_free(q->sw_ring);
2398         rte_free(q);
2399 }
2400
2401 const struct rte_memzone *
2402 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2403 {
2404         const struct rte_memzone *mz;
2405
2406         mz = rte_memzone_lookup(name);
2407         if (mz)
2408                 return mz;
2409
2410         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2411                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2412         return mz;
2413 }
2414
2415 void
2416 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2417 {
2418         uint16_t i;
2419
2420         /* SSE Vector driver has a different way of releasing mbufs. */
2421         if (rxq->rx_using_sse) {
2422                 i40e_rx_queue_release_mbufs_vec(rxq);
2423                 return;
2424         }
2425
2426         if (!rxq->sw_ring) {
2427                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2428                 return;
2429         }
2430
2431         for (i = 0; i < rxq->nb_rx_desc; i++) {
2432                 if (rxq->sw_ring[i].mbuf) {
2433                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2434                         rxq->sw_ring[i].mbuf = NULL;
2435                 }
2436         }
2437 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2438         if (rxq->rx_nb_avail == 0)
2439                 return;
2440         for (i = 0; i < rxq->rx_nb_avail; i++) {
2441                 struct rte_mbuf *mbuf;
2442
2443                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2444                 rte_pktmbuf_free_seg(mbuf);
2445         }
2446         rxq->rx_nb_avail = 0;
2447 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2448 }
2449
2450 void
2451 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2452 {
2453         unsigned i;
2454         uint16_t len;
2455
2456         if (!rxq) {
2457                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2458                 return;
2459         }
2460
2461 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2462         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2463                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2464         else
2465 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2466                 len = rxq->nb_rx_desc;
2467
2468         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2469                 ((volatile char *)rxq->rx_ring)[i] = 0;
2470
2471         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2472         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2473                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2474
2475 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2476         rxq->rx_nb_avail = 0;
2477         rxq->rx_next_avail = 0;
2478         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2479 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2480         rxq->rx_tail = 0;
2481         rxq->nb_rx_hold = 0;
2482         rxq->pkt_first_seg = NULL;
2483         rxq->pkt_last_seg = NULL;
2484
2485         rxq->rxrearm_start = 0;
2486         rxq->rxrearm_nb = 0;
2487 }
2488
2489 void
2490 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2491 {
2492         struct rte_eth_dev *dev;
2493         uint16_t i;
2494
2495         if (!txq || !txq->sw_ring) {
2496                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2497                 return;
2498         }
2499
2500         dev = &rte_eth_devices[txq->port_id];
2501
2502         /**
2503          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2504          *  so need to free remains more carefully.
2505          */
2506         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2507                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2508                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2509                 if (txq->tx_tail < i) {
2510                         for (; i < txq->nb_tx_desc; i++) {
2511                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2512                                 txq->sw_ring[i].mbuf = NULL;
2513                         }
2514                         i = 0;
2515                 }
2516                 for (; i < txq->tx_tail; i++) {
2517                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2518                         txq->sw_ring[i].mbuf = NULL;
2519                 }
2520         } else {
2521                 for (i = 0; i < txq->nb_tx_desc; i++) {
2522                         if (txq->sw_ring[i].mbuf) {
2523                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2524                                 txq->sw_ring[i].mbuf = NULL;
2525                         }
2526                 }
2527         }
2528 }
2529
2530 static int
2531 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2532                         uint32_t free_cnt)
2533 {
2534         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2535         uint16_t i, tx_last, tx_id;
2536         uint16_t nb_tx_free_last;
2537         uint16_t nb_tx_to_clean;
2538         uint32_t pkt_cnt;
2539
2540         /* Start free mbuf from the next of tx_tail */
2541         tx_last = txq->tx_tail;
2542         tx_id  = swr_ring[tx_last].next_id;
2543
2544         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2545                 return 0;
2546
2547         nb_tx_to_clean = txq->nb_tx_free;
2548         nb_tx_free_last = txq->nb_tx_free;
2549         if (!free_cnt)
2550                 free_cnt = txq->nb_tx_desc;
2551
2552         /* Loop through swr_ring to count the amount of
2553          * freeable mubfs and packets.
2554          */
2555         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2556                 for (i = 0; i < nb_tx_to_clean &&
2557                         pkt_cnt < free_cnt &&
2558                         tx_id != tx_last; i++) {
2559                         if (swr_ring[tx_id].mbuf != NULL) {
2560                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2561                                 swr_ring[tx_id].mbuf = NULL;
2562
2563                                 /*
2564                                  * last segment in the packet,
2565                                  * increment packet count
2566                                  */
2567                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2568                         }
2569
2570                         tx_id = swr_ring[tx_id].next_id;
2571                 }
2572
2573                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2574                         txq->nb_tx_free || tx_id == tx_last)
2575                         break;
2576
2577                 if (pkt_cnt < free_cnt) {
2578                         if (i40e_xmit_cleanup(txq))
2579                                 break;
2580
2581                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2582                         nb_tx_free_last = txq->nb_tx_free;
2583                 }
2584         }
2585
2586         return (int)pkt_cnt;
2587 }
2588
2589 static int
2590 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2591                         uint32_t free_cnt)
2592 {
2593         int i, n, cnt;
2594
2595         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2596                 free_cnt = txq->nb_tx_desc;
2597
2598         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2599
2600         for (i = 0; i < cnt; i += n) {
2601                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2602                         break;
2603
2604                 n = i40e_tx_free_bufs(txq);
2605
2606                 if (n == 0)
2607                         break;
2608         }
2609
2610         return i;
2611 }
2612
2613 static int
2614 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2615                         uint32_t free_cnt __rte_unused)
2616 {
2617         return -ENOTSUP;
2618 }
2619 int
2620 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2621 {
2622         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2623         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2624         struct i40e_adapter *ad =
2625                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2626
2627         if (ad->tx_simple_allowed) {
2628                 if (ad->tx_vec_allowed)
2629                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2630                 else
2631                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2632         } else {
2633                 return i40e_tx_done_cleanup_full(q, free_cnt);
2634         }
2635 }
2636
2637 void
2638 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2639 {
2640         struct i40e_tx_entry *txe;
2641         uint16_t i, prev, size;
2642
2643         if (!txq) {
2644                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2645                 return;
2646         }
2647
2648         txe = txq->sw_ring;
2649         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2650         for (i = 0; i < size; i++)
2651                 ((volatile char *)txq->tx_ring)[i] = 0;
2652
2653         prev = (uint16_t)(txq->nb_tx_desc - 1);
2654         for (i = 0; i < txq->nb_tx_desc; i++) {
2655                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2656
2657                 txd->cmd_type_offset_bsz =
2658                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2659                 txe[i].mbuf =  NULL;
2660                 txe[i].last_id = i;
2661                 txe[prev].next_id = i;
2662                 prev = i;
2663         }
2664
2665         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2666         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2667
2668         txq->tx_tail = 0;
2669         txq->nb_tx_used = 0;
2670
2671         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2672         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2673 }
2674
2675 /* Init the TX queue in hardware */
2676 int
2677 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2678 {
2679         enum i40e_status_code err = I40E_SUCCESS;
2680         struct i40e_vsi *vsi = txq->vsi;
2681         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2682         uint16_t pf_q = txq->reg_idx;
2683         struct i40e_hmc_obj_txq tx_ctx;
2684         uint32_t qtx_ctl;
2685
2686         /* clear the context structure first */
2687         memset(&tx_ctx, 0, sizeof(tx_ctx));
2688         tx_ctx.new_context = 1;
2689         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2690         tx_ctx.qlen = txq->nb_tx_desc;
2691
2692 #ifdef RTE_LIBRTE_IEEE1588
2693         tx_ctx.timesync_ena = 1;
2694 #endif
2695         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2696         if (vsi->type == I40E_VSI_FDIR)
2697                 tx_ctx.fd_ena = TRUE;
2698
2699         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2700         if (err != I40E_SUCCESS) {
2701                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2702                 return err;
2703         }
2704
2705         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2706         if (err != I40E_SUCCESS) {
2707                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2708                 return err;
2709         }
2710
2711         /* Now associate this queue with this PCI function */
2712         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2713         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2714                                         I40E_QTX_CTL_PF_INDX_MASK);
2715         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2716         I40E_WRITE_FLUSH(hw);
2717
2718         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2719
2720         return err;
2721 }
2722
2723 int
2724 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2725 {
2726         struct i40e_rx_entry *rxe = rxq->sw_ring;
2727         uint64_t dma_addr;
2728         uint16_t i;
2729
2730         for (i = 0; i < rxq->nb_rx_desc; i++) {
2731                 volatile union i40e_rx_desc *rxd;
2732                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2733
2734                 if (unlikely(!mbuf)) {
2735                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2736                         return -ENOMEM;
2737                 }
2738
2739                 rte_mbuf_refcnt_set(mbuf, 1);
2740                 mbuf->next = NULL;
2741                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2742                 mbuf->nb_segs = 1;
2743                 mbuf->port = rxq->port_id;
2744
2745                 dma_addr =
2746                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2747
2748                 rxd = &rxq->rx_ring[i];
2749                 rxd->read.pkt_addr = dma_addr;
2750                 rxd->read.hdr_addr = 0;
2751 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2752                 rxd->read.rsvd1 = 0;
2753                 rxd->read.rsvd2 = 0;
2754 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2755
2756                 rxe[i].mbuf = mbuf;
2757         }
2758
2759         return 0;
2760 }
2761
2762 /*
2763  * Calculate the buffer length, and check the jumbo frame
2764  * and maximum packet length.
2765  */
2766 static int
2767 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2768 {
2769         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2770         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2771         struct rte_eth_dev_data *data = pf->dev_data;
2772         uint16_t buf_size;
2773
2774         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2775                 RTE_PKTMBUF_HEADROOM);
2776
2777         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2778                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2779         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2780                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2781                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2782                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2783                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2784                 rxq->hs_mode = i40e_header_split_enabled;
2785                 break;
2786         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2787         default:
2788                 rxq->rx_hdr_len = 0;
2789                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2790                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2791                 rxq->hs_mode = i40e_header_split_none;
2792                 break;
2793         }
2794
2795         rxq->max_pkt_len =
2796                 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2797                         rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2798         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2799                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
2800                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2801                         PMD_DRV_LOG(ERR, "maximum packet length must "
2802                                     "be larger than %u and smaller than %u,"
2803                                     "as jumbo frame is enabled",
2804                                     (uint32_t)RTE_ETHER_MAX_LEN,
2805                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2806                         return I40E_ERR_CONFIG;
2807                 }
2808         } else {
2809                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2810                         rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
2811                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2812                                     "larger than %u and smaller than %u, "
2813                                     "as jumbo frame is disabled",
2814                                     (uint32_t)RTE_ETHER_MIN_LEN,
2815                                     (uint32_t)RTE_ETHER_MAX_LEN);
2816                         return I40E_ERR_CONFIG;
2817                 }
2818         }
2819
2820         return 0;
2821 }
2822
2823 /* Init the RX queue in hardware */
2824 int
2825 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2826 {
2827         int err = I40E_SUCCESS;
2828         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2829         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2830         uint16_t pf_q = rxq->reg_idx;
2831         uint16_t buf_size;
2832         struct i40e_hmc_obj_rxq rx_ctx;
2833
2834         err = i40e_rx_queue_config(rxq);
2835         if (err < 0) {
2836                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2837                 return err;
2838         }
2839
2840         /* Clear the context structure first */
2841         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2842         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2843         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2844
2845         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2846         rx_ctx.qlen = rxq->nb_rx_desc;
2847 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2848         rx_ctx.dsize = 1;
2849 #endif
2850         rx_ctx.dtype = rxq->hs_mode;
2851         if (rxq->hs_mode)
2852                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2853         else
2854                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2855         rx_ctx.rxmax = rxq->max_pkt_len;
2856         rx_ctx.tphrdesc_ena = 1;
2857         rx_ctx.tphwdesc_ena = 1;
2858         rx_ctx.tphdata_ena = 1;
2859         rx_ctx.tphhead_ena = 1;
2860         rx_ctx.lrxqthresh = 2;
2861         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2862         rx_ctx.l2tsel = 1;
2863         /* showiv indicates if inner VLAN is stripped inside of tunnel
2864          * packet. When set it to 1, vlan information is stripped from
2865          * the inner header, but the hardware does not put it in the
2866          * descriptor. So set it zero by default.
2867          */
2868         rx_ctx.showiv = 0;
2869         rx_ctx.prefena = 1;
2870
2871         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2872         if (err != I40E_SUCCESS) {
2873                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2874                 return err;
2875         }
2876         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2877         if (err != I40E_SUCCESS) {
2878                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2879                 return err;
2880         }
2881
2882         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2883
2884         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2885                 RTE_PKTMBUF_HEADROOM);
2886
2887         /* Check if scattered RX needs to be used. */
2888         if (rxq->max_pkt_len > buf_size)
2889                 dev_data->scattered_rx = 1;
2890
2891         /* Init the RX tail regieter. */
2892         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2893
2894         return 0;
2895 }
2896
2897 void
2898 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2899 {
2900         uint16_t i;
2901
2902         PMD_INIT_FUNC_TRACE();
2903
2904         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2905                 if (!dev->data->tx_queues[i])
2906                         continue;
2907                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2908                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2909         }
2910
2911         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2912                 if (!dev->data->rx_queues[i])
2913                         continue;
2914                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2915                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2916         }
2917 }
2918
2919 void
2920 i40e_dev_free_queues(struct rte_eth_dev *dev)
2921 {
2922         uint16_t i;
2923
2924         PMD_INIT_FUNC_TRACE();
2925
2926         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2927                 if (!dev->data->rx_queues[i])
2928                         continue;
2929                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2930                 dev->data->rx_queues[i] = NULL;
2931         }
2932
2933         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2934                 if (!dev->data->tx_queues[i])
2935                         continue;
2936                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2937                 dev->data->tx_queues[i] = NULL;
2938         }
2939 }
2940
2941 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2942 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2943
2944 enum i40e_status_code
2945 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2946 {
2947         struct i40e_tx_queue *txq;
2948         const struct rte_memzone *tz = NULL;
2949         uint32_t ring_size;
2950         struct rte_eth_dev *dev;
2951
2952         if (!pf) {
2953                 PMD_DRV_LOG(ERR, "PF is not available");
2954                 return I40E_ERR_BAD_PTR;
2955         }
2956
2957         dev = pf->adapter->eth_dev;
2958
2959         /* Allocate the TX queue data structure. */
2960         txq = rte_zmalloc_socket("i40e fdir tx queue",
2961                                   sizeof(struct i40e_tx_queue),
2962                                   RTE_CACHE_LINE_SIZE,
2963                                   SOCKET_ID_ANY);
2964         if (!txq) {
2965                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2966                                         "tx queue structure.");
2967                 return I40E_ERR_NO_MEMORY;
2968         }
2969
2970         /* Allocate TX hardware ring descriptors. */
2971         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2972         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2973
2974         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2975                                       I40E_FDIR_QUEUE_ID, ring_size,
2976                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2977         if (!tz) {
2978                 i40e_dev_tx_queue_release(txq);
2979                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2980                 return I40E_ERR_NO_MEMORY;
2981         }
2982
2983         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2984         txq->queue_id = I40E_FDIR_QUEUE_ID;
2985         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2986         txq->vsi = pf->fdir.fdir_vsi;
2987
2988         txq->tx_ring_phys_addr = tz->iova;
2989         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2990         /*
2991          * don't need to allocate software ring and reset for the fdir
2992          * program queue just set the queue has been configured.
2993          */
2994         txq->q_set = TRUE;
2995         pf->fdir.txq = txq;
2996
2997         return I40E_SUCCESS;
2998 }
2999
3000 enum i40e_status_code
3001 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3002 {
3003         struct i40e_rx_queue *rxq;
3004         const struct rte_memzone *rz = NULL;
3005         uint32_t ring_size;
3006         struct rte_eth_dev *dev;
3007
3008         if (!pf) {
3009                 PMD_DRV_LOG(ERR, "PF is not available");
3010                 return I40E_ERR_BAD_PTR;
3011         }
3012
3013         dev = pf->adapter->eth_dev;
3014
3015         /* Allocate the RX queue data structure. */
3016         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3017                                   sizeof(struct i40e_rx_queue),
3018                                   RTE_CACHE_LINE_SIZE,
3019                                   SOCKET_ID_ANY);
3020         if (!rxq) {
3021                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3022                                         "rx queue structure.");
3023                 return I40E_ERR_NO_MEMORY;
3024         }
3025
3026         /* Allocate RX hardware ring descriptors. */
3027         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3028         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3029
3030         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3031                                       I40E_FDIR_QUEUE_ID, ring_size,
3032                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3033         if (!rz) {
3034                 i40e_dev_rx_queue_release(rxq);
3035                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3036                 return I40E_ERR_NO_MEMORY;
3037         }
3038
3039         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3040         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3041         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3042         rxq->vsi = pf->fdir.fdir_vsi;
3043
3044         rxq->rx_ring_phys_addr = rz->iova;
3045         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3046         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3047
3048         /*
3049          * Don't need to allocate software ring and reset for the fdir
3050          * rx queue, just set the queue has been configured.
3051          */
3052         rxq->q_set = TRUE;
3053         pf->fdir.rxq = rxq;
3054
3055         return I40E_SUCCESS;
3056 }
3057
3058 void
3059 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3060         struct rte_eth_rxq_info *qinfo)
3061 {
3062         struct i40e_rx_queue *rxq;
3063
3064         rxq = dev->data->rx_queues[queue_id];
3065
3066         qinfo->mp = rxq->mp;
3067         qinfo->scattered_rx = dev->data->scattered_rx;
3068         qinfo->nb_desc = rxq->nb_rx_desc;
3069
3070         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3071         qinfo->conf.rx_drop_en = rxq->drop_en;
3072         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3073         qinfo->conf.offloads = rxq->offloads;
3074 }
3075
3076 void
3077 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3078         struct rte_eth_txq_info *qinfo)
3079 {
3080         struct i40e_tx_queue *txq;
3081
3082         txq = dev->data->tx_queues[queue_id];
3083
3084         qinfo->nb_desc = txq->nb_tx_desc;
3085
3086         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3087         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3088         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3089
3090         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3091         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3092         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3093         qinfo->conf.offloads = txq->offloads;
3094 }
3095
3096 static eth_rx_burst_t
3097 i40e_get_latest_rx_vec(bool scatter)
3098 {
3099 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3100         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3101                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
3102                                  i40e_recv_pkts_vec_avx2;
3103 #endif
3104         return scatter ? i40e_recv_scattered_pkts_vec :
3105                          i40e_recv_pkts_vec;
3106 }
3107
3108 static eth_rx_burst_t
3109 i40e_get_recommend_rx_vec(bool scatter)
3110 {
3111 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3112         /*
3113          * since AVX frequency can be different to base frequency, limit
3114          * use of AVX2 version to later plaforms, not all those that could
3115          * theoretically run it.
3116          */
3117         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3118                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
3119                                  i40e_recv_pkts_vec_avx2;
3120 #endif
3121         return scatter ? i40e_recv_scattered_pkts_vec :
3122                          i40e_recv_pkts_vec;
3123 }
3124
3125 void __rte_cold
3126 i40e_set_rx_function(struct rte_eth_dev *dev)
3127 {
3128         struct i40e_adapter *ad =
3129                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3130         uint16_t rx_using_sse, i;
3131         /* In order to allow Vector Rx there are a few configuration
3132          * conditions to be met and Rx Bulk Allocation should be allowed.
3133          */
3134         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3135                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3136                     !ad->rx_bulk_alloc_allowed) {
3137                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3138                                      " Vector Rx preconditions",
3139                                      dev->data->port_id);
3140
3141                         ad->rx_vec_allowed = false;
3142                 }
3143                 if (ad->rx_vec_allowed) {
3144                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3145                                 struct i40e_rx_queue *rxq =
3146                                         dev->data->rx_queues[i];
3147
3148                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3149                                         ad->rx_vec_allowed = false;
3150                                         break;
3151                                 }
3152                         }
3153                 }
3154         }
3155
3156         if (ad->rx_vec_allowed) {
3157                 /* Vec Rx path */
3158                 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
3159                                 dev->data->port_id);
3160                 if (ad->use_latest_vec)
3161                         dev->rx_pkt_burst =
3162                         i40e_get_latest_rx_vec(dev->data->scattered_rx);
3163                 else
3164                         dev->rx_pkt_burst =
3165                         i40e_get_recommend_rx_vec(dev->data->scattered_rx);
3166         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3167                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3168                                     "satisfied. Rx Burst Bulk Alloc function "
3169                                     "will be used on port=%d.",
3170                              dev->data->port_id);
3171
3172                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3173         } else {
3174                 /* Simple Rx Path. */
3175                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3176                              dev->data->port_id);
3177                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3178                                         i40e_recv_scattered_pkts :
3179                                         i40e_recv_pkts;
3180         }
3181
3182         /* Propagate information about RX function choice through all queues. */
3183         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3184                 rx_using_sse =
3185                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3186                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3187                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3188                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3189
3190                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3191                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3192
3193                         if (rxq)
3194                                 rxq->rx_using_sse = rx_using_sse;
3195                 }
3196         }
3197 }
3198
3199 static const struct {
3200         eth_rx_burst_t pkt_burst;
3201         const char *info;
3202 } i40e_rx_burst_infos[] = {
3203         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3204         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3205         { i40e_recv_pkts,                    "Scalar" },
3206 #ifdef RTE_ARCH_X86
3207         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3208         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3209         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3210         { i40e_recv_pkts_vec,                "Vector SSE" },
3211 #elif defined(RTE_ARCH_ARM64)
3212         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3213         { i40e_recv_pkts_vec,                "Vector Neon" },
3214 #elif defined(RTE_ARCH_PPC_64)
3215         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3216         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3217 #endif
3218 };
3219
3220 int
3221 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3222                        struct rte_eth_burst_mode *mode)
3223 {
3224         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3225         int ret = -EINVAL;
3226         unsigned int i;
3227
3228         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3229                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3230                         snprintf(mode->info, sizeof(mode->info), "%s",
3231                                  i40e_rx_burst_infos[i].info);
3232                         ret = 0;
3233                         break;
3234                 }
3235         }
3236
3237         return ret;
3238 }
3239
3240 void __rte_cold
3241 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3242 {
3243         struct i40e_adapter *ad =
3244                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3245
3246         /* Use a simple Tx queue if possible (only fast free is allowed) */
3247         ad->tx_simple_allowed =
3248                 (txq->offloads ==
3249                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3250                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3251         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3252                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3253
3254         if (ad->tx_vec_allowed)
3255                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3256                                 txq->queue_id);
3257         else if (ad->tx_simple_allowed)
3258                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3259                                 txq->queue_id);
3260         else
3261                 PMD_INIT_LOG(DEBUG,
3262                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3263                                 txq->queue_id);
3264 }
3265
3266 static eth_tx_burst_t
3267 i40e_get_latest_tx_vec(void)
3268 {
3269 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3270         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3271                 return i40e_xmit_pkts_vec_avx2;
3272 #endif
3273         return i40e_xmit_pkts_vec;
3274 }
3275
3276 static eth_tx_burst_t
3277 i40e_get_recommend_tx_vec(void)
3278 {
3279 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3280         /*
3281          * since AVX frequency can be different to base frequency, limit
3282          * use of AVX2 version to later plaforms, not all those that could
3283          * theoretically run it.
3284          */
3285         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3286                 return i40e_xmit_pkts_vec_avx2;
3287 #endif
3288         return i40e_xmit_pkts_vec;
3289 }
3290
3291 void __rte_cold
3292 i40e_set_tx_function(struct rte_eth_dev *dev)
3293 {
3294         struct i40e_adapter *ad =
3295                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3296         int i;
3297
3298         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3299                 if (ad->tx_vec_allowed) {
3300                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3301                                 struct i40e_tx_queue *txq =
3302                                         dev->data->tx_queues[i];
3303
3304                                 if (txq && i40e_txq_vec_setup(txq)) {
3305                                         ad->tx_vec_allowed = false;
3306                                         break;
3307                                 }
3308                         }
3309                 }
3310         }
3311
3312         if (ad->tx_simple_allowed) {
3313                 if (ad->tx_vec_allowed) {
3314                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3315                         if (ad->use_latest_vec)
3316                                 dev->tx_pkt_burst =
3317                                         i40e_get_latest_tx_vec();
3318                         else
3319                                 dev->tx_pkt_burst =
3320                                         i40e_get_recommend_tx_vec();
3321                 } else {
3322                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3323                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3324                 }
3325                 dev->tx_pkt_prepare = NULL;
3326         } else {
3327                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3328                 dev->tx_pkt_burst = i40e_xmit_pkts;
3329                 dev->tx_pkt_prepare = i40e_prep_pkts;
3330         }
3331 }
3332
3333 static const struct {
3334         eth_tx_burst_t pkt_burst;
3335         const char *info;
3336 } i40e_tx_burst_infos[] = {
3337         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3338         { i40e_xmit_pkts,          "Scalar" },
3339 #ifdef RTE_ARCH_X86
3340         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3341         { i40e_xmit_pkts_vec,      "Vector SSE" },
3342 #elif defined(RTE_ARCH_ARM64)
3343         { i40e_xmit_pkts_vec,      "Vector Neon" },
3344 #elif defined(RTE_ARCH_PPC_64)
3345         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3346 #endif
3347 };
3348
3349 int
3350 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3351                        struct rte_eth_burst_mode *mode)
3352 {
3353         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3354         int ret = -EINVAL;
3355         unsigned int i;
3356
3357         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3358                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3359                         snprintf(mode->info, sizeof(mode->info), "%s",
3360                                  i40e_tx_burst_infos[i].info);
3361                         ret = 0;
3362                         break;
3363                 }
3364         }
3365
3366         return ret;
3367 }
3368
3369 void __rte_cold
3370 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3371 {
3372         struct i40e_adapter *ad =
3373                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3374         int i;
3375
3376         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3377                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3378 }
3379
3380 void __rte_cold
3381 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3382 {
3383         struct i40e_adapter *ad =
3384                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3385         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386         int i;
3387
3388         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3389                 ad->pctypes_tbl[i] = 0ULL;
3390         ad->flow_types_mask = 0ULL;
3391         ad->pctypes_mask = 0ULL;
3392
3393         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3394                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3395         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3396                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3397         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3398                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3399         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3400                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3401         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3402                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3403         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3404                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3405         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3406                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3407         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3408                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3409         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3410                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3411         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3412                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3413         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3414                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3415
3416         if (hw->mac.type == I40E_MAC_X722 ||
3417                 hw->mac.type == I40E_MAC_X722_VF) {
3418                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3419                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3420                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3421                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3422                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3423                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3424                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3425                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3426                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3427                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3428                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3429                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3430         }
3431
3432         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3433                 if (ad->pctypes_tbl[i])
3434                         ad->flow_types_mask |= (1ULL << i);
3435                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3436         }
3437 }
3438
3439 #ifndef RTE_LIBRTE_I40E_INC_VECTOR
3440 /* Stubs needed for linkage when CONFIG_RTE_LIBRTE_I40E_INC_VECTOR is set to 'n' */
3441 int
3442 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3443 {
3444         return -1;
3445 }
3446
3447 uint16_t
3448 i40e_recv_pkts_vec(
3449         void __rte_unused *rx_queue,
3450         struct rte_mbuf __rte_unused **rx_pkts,
3451         uint16_t __rte_unused nb_pkts)
3452 {
3453         return 0;
3454 }
3455
3456 uint16_t
3457 i40e_recv_scattered_pkts_vec(
3458         void __rte_unused *rx_queue,
3459         struct rte_mbuf __rte_unused **rx_pkts,
3460         uint16_t __rte_unused nb_pkts)
3461 {
3462         return 0;
3463 }
3464
3465 int
3466 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3467 {
3468         return -1;
3469 }
3470
3471 int
3472 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3473 {
3474         return -1;
3475 }
3476
3477 void
3478 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3479 {
3480         return;
3481 }
3482
3483 uint16_t
3484 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3485                           struct rte_mbuf __rte_unused **tx_pkts,
3486                           uint16_t __rte_unused nb_pkts)
3487 {
3488         return 0;
3489 }
3490 #endif /* ifndef RTE_LIBRTE_I40E_INC_VECTOR */
3491
3492 #ifndef CC_AVX2_SUPPORT
3493 uint16_t
3494 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3495                         struct rte_mbuf __rte_unused **rx_pkts,
3496                         uint16_t __rte_unused nb_pkts)
3497 {
3498         return 0;
3499 }
3500
3501 uint16_t
3502 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3503                         struct rte_mbuf __rte_unused **rx_pkts,
3504                         uint16_t __rte_unused nb_pkts)
3505 {
3506         return 0;
3507 }
3508
3509 uint16_t
3510 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3511                           struct rte_mbuf __rte_unused **tx_pkts,
3512                           uint16_t __rte_unused nb_pkts)
3513 {
3514         return 0;
3515 }
3516 #endif /* ifndef CC_AVX2_SUPPORT */