drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "i40e_logs.h"
  29 #include "base/i40e_prototype.h"
  30 #include "base/i40e_type.h"
  31 #include "i40e_ethdev.h"
  32 #include "i40e_rxtx.h"
  33
  34 #define DEFAULT_TX_RS_THRESH   32
  35 #define DEFAULT_TX_FREE_THRESH 32
  36
  37 #define I40E_TX_MAX_BURST  32
  38
  39 #define I40E_DMA_MEM_ALIGN 4096
  40
  41 /* Base address of the HW descriptor ring should be 128B aligned. */
  42 #define I40E_RING_BASE_ALIGN    128
  43
  44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  45
  46 #ifdef RTE_LIBRTE_IEEE1588
  47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  48 #else
  49 #define I40E_TX_IEEE1588_TMST 0
  50 #endif
  51
  52 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG |                 \
  56                 PKT_TX_OUTER_IP_CKSUM)
  57
  58 #define I40E_TX_OFFLOAD_MASK (  \
  59                 PKT_TX_OUTER_IPV4 |     \
  60                 PKT_TX_OUTER_IPV6 |     \
  61                 PKT_TX_IPV4 |           \
  62                 PKT_TX_IPV6 |           \
  63                 PKT_TX_IP_CKSUM |       \
  64                 PKT_TX_L4_MASK |        \
  65                 PKT_TX_OUTER_IP_CKSUM | \
  66                 PKT_TX_TCP_SEG |        \
  67                 PKT_TX_QINQ_PKT |       \
  68                 PKT_TX_VLAN_PKT |       \
  69                 PKT_TX_TUNNEL_MASK |    \
  70                 I40E_TX_IEEE1588_TMST)
  71
  72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  73                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  74
  75 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK ( \
  76                 PKT_TX_IPV4 | \
  77                 PKT_TX_IPV6 | \
  78                 PKT_TX_OUTER_IPV4 | \
  79                 PKT_TX_OUTER_IPV6)
  80
  81 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
  82                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
  83
  84 static int
  85 i40e_monitor_callback(const uint64_t value,
  86                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  87 {
  88         const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
  89         /*
  90          * we expect the DD bit to be set to 1 if this descriptor was already
  91          * written to.
  92          */
  93         return (value & m) == m ? -1 : 0;
  94 }
  95
  96 int
  97 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  98 {
  99         struct i40e_rx_queue *rxq = rx_queue;
 100         volatile union i40e_rx_desc *rxdp;
 101         uint16_t desc;
 102
 103         desc = rxq->rx_tail;
 104         rxdp = &rxq->rx_ring[desc];
 105         /* watch for changes in status bit */
 106         pmc->addr = &rxdp->wb.qword1.status_error_len;
 107
 108         /* comparison callback */
 109         pmc->fn = i40e_monitor_callback;
 110
 111         /* registers are 64-bit */
 112         pmc->size = sizeof(uint64_t);
 113
 114         return 0;
 115 }
 116
 117 static inline void
 118 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 119 {
 120         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 121                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 122                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 123                 mb->vlan_tci =
 124                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 125                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 126                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 127         } else {
 128                 mb->vlan_tci = 0;
 129         }
 130 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 131         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 132                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 133                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
 134                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
 135                 mb->vlan_tci_outer = mb->vlan_tci;
 136                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 137                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 138                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 139                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 140         } else {
 141                 mb->vlan_tci_outer = 0;
 142         }
 143 #endif
 144         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 145                    mb->vlan_tci, mb->vlan_tci_outer);
 146 }
 147
 148 /* Translate the rx descriptor status to pkt flags */
 149 static inline uint64_t
 150 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 151 {
 152         uint64_t flags;
 153
 154         /* Check if RSS_HASH */
 155         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 156                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 157                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 158
 159         /* Check if FDIR Match */
 160         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 161                                                         PKT_RX_FDIR : 0);
 162
 163         return flags;
 164 }
 165
 166 static inline uint64_t
 167 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 168 {
 169         uint64_t flags = 0;
 170         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 171
 172 #define I40E_RX_ERR_BITS 0x3f
 173         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 174                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 175                 return flags;
 176         }
 177
 178         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 179                 flags |= PKT_RX_IP_CKSUM_BAD;
 180         else
 181                 flags |= PKT_RX_IP_CKSUM_GOOD;
 182
 183         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 184                 flags |= PKT_RX_L4_CKSUM_BAD;
 185         else
 186                 flags |= PKT_RX_L4_CKSUM_GOOD;
 187
 188         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 189                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
 190
 191         return flags;
 192 }
 193
 194 /* Function to check and set the ieee1588 timesync index and get the
 195  * appropriate flags.
 196  */
 197 #ifdef RTE_LIBRTE_IEEE1588
 198 static inline uint64_t
 199 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 200 {
 201         uint64_t pkt_flags = 0;
 202         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 203                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 204                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 205
 206         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 207                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 208                 pkt_flags = PKT_RX_IEEE1588_PTP;
 209         if (tsyn & 0x04) {
 210                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 211                 mb->timesync = tsyn & 0x03;
 212         }
 213
 214         return pkt_flags;
 215 }
 216 #endif
 217
 218 static inline uint64_t
 219 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 220 {
 221         uint64_t flags = 0;
 222 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 223         uint16_t flexbh, flexbl;
 224
 225         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 226                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 227                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 228         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 229                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 230                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 231
 232
 233         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 234                 mb->hash.fdir.hi =
 235                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 236                 flags |= PKT_RX_FDIR_ID;
 237         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 238                 mb->hash.fdir.hi =
 239                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 240                 flags |= PKT_RX_FDIR_FLX;
 241         }
 242         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 243                 mb->hash.fdir.lo =
 244                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 245                 flags |= PKT_RX_FDIR_FLX;
 246         }
 247 #else
 248         mb->hash.fdir.hi =
 249                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 250         flags |= PKT_RX_FDIR_ID;
 251 #endif
 252         return flags;
 253 }
 254
 255 static inline void
 256 i40e_parse_tunneling_params(uint64_t ol_flags,
 257                             union i40e_tx_offload tx_offload,
 258                             uint32_t *cd_tunneling)
 259 {
 260         /* EIPT: External (outer) IP header type */
 261         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 262                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 263         else if (ol_flags & PKT_TX_OUTER_IPV4)
 264                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 265         else if (ol_flags & PKT_TX_OUTER_IPV6)
 266                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 267
 268         /* EIPLEN: External (outer) IP header length, in DWords */
 269         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 270                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 271
 272         /* L4TUNT: L4 Tunneling Type */
 273         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 274         case PKT_TX_TUNNEL_IPIP:
 275                 /* for non UDP / GRE tunneling, set to 00b */
 276                 break;
 277         case PKT_TX_TUNNEL_VXLAN:
 278         case PKT_TX_TUNNEL_GENEVE:
 279                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 280                 break;
 281         case PKT_TX_TUNNEL_GRE:
 282                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 283                 break;
 284         default:
 285                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 286                 return;
 287         }
 288
 289         /* L4TUNLEN: L4 Tunneling Length, in Words
 290          *
 291          * We depend on app to set rte_mbuf.l2_len correctly.
 292          * For IP in GRE it should be set to the length of the GRE
 293          * header;
 294          * for MAC in GRE or MAC in UDP it should be set to the length
 295          * of the GRE or UDP headers plus the inner MAC up to including
 296          * its last Ethertype.
 297          */
 298         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 299                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 300 }
 301
 302 static inline void
 303 i40e_txd_enable_checksum(uint64_t ol_flags,
 304                         uint32_t *td_cmd,
 305                         uint32_t *td_offset,
 306                         union i40e_tx_offload tx_offload)
 307 {
 308         /* Set MACLEN */
 309         if (ol_flags & PKT_TX_TUNNEL_MASK)
 310                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 311                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 312         else
 313                 *td_offset |= (tx_offload.l2_len >> 1)
 314                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 315
 316         /* Enable L3 checksum offloads */
 317         if (ol_flags & PKT_TX_IP_CKSUM) {
 318                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 319                 *td_offset |= (tx_offload.l3_len >> 2)
 320                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 321         } else if (ol_flags & PKT_TX_IPV4) {
 322                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 323                 *td_offset |= (tx_offload.l3_len >> 2)
 324                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 325         } else if (ol_flags & PKT_TX_IPV6) {
 326                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 327                 *td_offset |= (tx_offload.l3_len >> 2)
 328                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 329         }
 330
 331         if (ol_flags & PKT_TX_TCP_SEG) {
 332                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 333                 *td_offset |= (tx_offload.l4_len >> 2)
 334                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 335                 return;
 336         }
 337
 338         /* Enable L4 checksum offloads */
 339         switch (ol_flags & PKT_TX_L4_MASK) {
 340         case PKT_TX_TCP_CKSUM:
 341                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 342                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 343                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 344                 break;
 345         case PKT_TX_SCTP_CKSUM:
 346                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 347                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 348                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 349                 break;
 350         case PKT_TX_UDP_CKSUM:
 351                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 352                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 353                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 354                 break;
 355         default:
 356                 break;
 357         }
 358 }
 359
 360 /* Construct the tx flags */
 361 static inline uint64_t
 362 i40e_build_ctob(uint32_t td_cmd,
 363                 uint32_t td_offset,
 364                 unsigned int size,
 365                 uint32_t td_tag)
 366 {
 367         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 368                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 369                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 370                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 371                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 372 }
 373
 374 static inline int
 375 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 376 {
 377         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 378         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 379         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 380         uint16_t nb_tx_desc = txq->nb_tx_desc;
 381         uint16_t desc_to_clean_to;
 382         uint16_t nb_tx_to_clean;
 383
 384         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 385         if (desc_to_clean_to >= nb_tx_desc)
 386                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 387
 388         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 389         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 390                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 391                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 392                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
 393                            "(port=%d queue=%d)", desc_to_clean_to,
 394                            txq->port_id, txq->queue_id);
 395                 return -1;
 396         }
 397
 398         if (last_desc_cleaned > desc_to_clean_to)
 399                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 400                                                         desc_to_clean_to);
 401         else
 402                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 403                                         last_desc_cleaned);
 404
 405         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 406
 407         txq->last_desc_cleaned = desc_to_clean_to;
 408         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 409
 410         return 0;
 411 }
 412
 413 static inline int
 414 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 415 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 416 #else
 417 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 418 #endif
 419 {
 420         int ret = 0;
 421
 422 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 423         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 424                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 425                              "rxq->rx_free_thresh=%d, "
 426                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 427                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 428                 ret = -EINVAL;
 429         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 430                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 431                              "rxq->rx_free_thresh=%d, "
 432                              "rxq->nb_rx_desc=%d",
 433                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 434                 ret = -EINVAL;
 435         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 436                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 437                              "rxq->nb_rx_desc=%d, "
 438                              "rxq->rx_free_thresh=%d",
 439                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 440                 ret = -EINVAL;
 441         }
 442 #else
 443         ret = -EINVAL;
 444 #endif
 445
 446         return ret;
 447 }
 448
 449 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 450 #define I40E_LOOK_AHEAD 8
 451 #if (I40E_LOOK_AHEAD != 8)
 452 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 453 #endif
 454 static inline int
 455 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 456 {
 457         volatile union i40e_rx_desc *rxdp;
 458         struct i40e_rx_entry *rxep;
 459         struct rte_mbuf *mb;
 460         uint16_t pkt_len;
 461         uint64_t qword1;
 462         uint32_t rx_status;
 463         int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
 464         int32_t i, j, nb_rx = 0;
 465         uint64_t pkt_flags;
 466         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 467
 468         rxdp = &rxq->rx_ring[rxq->rx_tail];
 469         rxep = &rxq->sw_ring[rxq->rx_tail];
 470
 471         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 472         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 473                                 I40E_RXD_QW1_STATUS_SHIFT;
 474
 475         /* Make sure there is at least 1 packet to receive */
 476         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 477                 return 0;
 478
 479         /**
 480          * Scan LOOK_AHEAD descriptors at a time to determine which
 481          * descriptors reference packets that are ready to be received.
 482          */
 483         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 484                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 485                 /* Read desc statuses backwards to avoid race condition */
 486                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 487                         qword1 = rte_le_to_cpu_64(\
 488                                 rxdp[j].wb.qword1.status_error_len);
 489                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 490                                         I40E_RXD_QW1_STATUS_SHIFT;
 491                 }
 492
 493                 rte_smp_rmb();
 494
 495                 /* Compute how many status bits were set */
 496                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
 497                         var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 498 #ifdef RTE_ARCH_ARM
 499                         /* For Arm platforms, only compute continuous status bits */
 500                         if (var)
 501                                 nb_dd += 1;
 502                         else
 503                                 break;
 504 #else
 505                         nb_dd += var;
 506 #endif
 507                 }
 508
 509                 nb_rx += nb_dd;
 510
 511                 /* Translate descriptor info to mbuf parameters */
 512                 for (j = 0; j < nb_dd; j++) {
 513                         mb = rxep[j].mbuf;
 514                         qword1 = rte_le_to_cpu_64(\
 515                                 rxdp[j].wb.qword1.status_error_len);
 516                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 517                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 518                         mb->data_len = pkt_len;
 519                         mb->pkt_len = pkt_len;
 520                         mb->ol_flags = 0;
 521                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 522                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 523                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 524                         mb->packet_type =
 525                                 ptype_tbl[(uint8_t)((qword1 &
 526                                 I40E_RXD_QW1_PTYPE_MASK) >>
 527                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 528                         if (pkt_flags & PKT_RX_RSS_HASH)
 529                                 mb->hash.rss = rte_le_to_cpu_32(\
 530                                         rxdp[j].wb.qword0.hi_dword.rss);
 531                         if (pkt_flags & PKT_RX_FDIR)
 532                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 533
 534 #ifdef RTE_LIBRTE_IEEE1588
 535                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 536 #endif
 537                         mb->ol_flags |= pkt_flags;
 538
 539                 }
 540
 541                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 542                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 543
 544                 if (nb_dd != I40E_LOOK_AHEAD)
 545                         break;
 546         }
 547
 548         /* Clear software ring entries */
 549         for (i = 0; i < nb_rx; i++)
 550                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 551
 552         return nb_rx;
 553 }
 554
 555 static inline uint16_t
 556 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 557                         struct rte_mbuf **rx_pkts,
 558                         uint16_t nb_pkts)
 559 {
 560         uint16_t i;
 561         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 562
 563         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 564
 565         for (i = 0; i < nb_pkts; i++)
 566                 rx_pkts[i] = stage[i];
 567
 568         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 569         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 570
 571         return nb_pkts;
 572 }
 573
 574 static inline int
 575 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 576 {
 577         volatile union i40e_rx_desc *rxdp;
 578         struct i40e_rx_entry *rxep;
 579         struct rte_mbuf *mb;
 580         uint16_t alloc_idx, i;
 581         uint64_t dma_addr;
 582         int diag;
 583
 584         /* Allocate buffers in bulk */
 585         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 586                                 (rxq->rx_free_thresh - 1));
 587         rxep = &(rxq->sw_ring[alloc_idx]);
 588         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 589                                         rxq->rx_free_thresh);
 590         if (unlikely(diag != 0)) {
 591                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 592                 return -ENOMEM;
 593         }
 594
 595         rxdp = &rxq->rx_ring[alloc_idx];
 596         for (i = 0; i < rxq->rx_free_thresh; i++) {
 597                 if (likely(i < (rxq->rx_free_thresh - 1)))
 598                         /* Prefetch next mbuf */
 599                         rte_prefetch0(rxep[i + 1].mbuf);
 600
 601                 mb = rxep[i].mbuf;
 602                 rte_mbuf_refcnt_set(mb, 1);
 603                 mb->next = NULL;
 604                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 605                 mb->nb_segs = 1;
 606                 mb->port = rxq->port_id;
 607                 dma_addr = rte_cpu_to_le_64(\
 608                         rte_mbuf_data_iova_default(mb));
 609                 rxdp[i].read.hdr_addr = 0;
 610                 rxdp[i].read.pkt_addr = dma_addr;
 611         }
 612
 613         /* Update rx tail regsiter */
 614         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 615
 616         rxq->rx_free_trigger =
 617                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 618         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 619                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 620
 621         return 0;
 622 }
 623
 624 static inline uint16_t
 625 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 626 {
 627         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 628         struct rte_eth_dev *dev;
 629         uint16_t nb_rx = 0;
 630
 631         if (!nb_pkts)
 632                 return 0;
 633
 634         if (rxq->rx_nb_avail)
 635                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 636
 637         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 638         rxq->rx_next_avail = 0;
 639         rxq->rx_nb_avail = nb_rx;
 640         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 641
 642         if (rxq->rx_tail > rxq->rx_free_trigger) {
 643                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 644                         uint16_t i, j;
 645
 646                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 647                         dev->data->rx_mbuf_alloc_failed +=
 648                                 rxq->rx_free_thresh;
 649
 650                         rxq->rx_nb_avail = 0;
 651                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 652                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 653                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 654
 655                         return 0;
 656                 }
 657         }
 658
 659         if (rxq->rx_tail >= rxq->nb_rx_desc)
 660                 rxq->rx_tail = 0;
 661
 662         if (rxq->rx_nb_avail)
 663                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 664
 665         return 0;
 666 }
 667
 668 static uint16_t
 669 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 670                           struct rte_mbuf **rx_pkts,
 671                           uint16_t nb_pkts)
 672 {
 673         uint16_t nb_rx = 0, n, count;
 674
 675         if (unlikely(nb_pkts == 0))
 676                 return 0;
 677
 678         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 679                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 680
 681         while (nb_pkts) {
 682                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 683                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 684                 nb_rx = (uint16_t)(nb_rx + count);
 685                 nb_pkts = (uint16_t)(nb_pkts - count);
 686                 if (count < n)
 687                         break;
 688         }
 689
 690         return nb_rx;
 691 }
 692 #else
 693 static uint16_t
 694 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 695                           struct rte_mbuf __rte_unused **rx_pkts,
 696                           uint16_t __rte_unused nb_pkts)
 697 {
 698         return 0;
 699 }
 700 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 701
 702 uint16_t
 703 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 704 {
 705         struct i40e_rx_queue *rxq;
 706         volatile union i40e_rx_desc *rx_ring;
 707         volatile union i40e_rx_desc *rxdp;
 708         union i40e_rx_desc rxd;
 709         struct i40e_rx_entry *sw_ring;
 710         struct i40e_rx_entry *rxe;
 711         struct rte_eth_dev *dev;
 712         struct rte_mbuf *rxm;
 713         struct rte_mbuf *nmb;
 714         uint16_t nb_rx;
 715         uint32_t rx_status;
 716         uint64_t qword1;
 717         uint16_t rx_packet_len;
 718         uint16_t rx_id, nb_hold;
 719         uint64_t dma_addr;
 720         uint64_t pkt_flags;
 721         uint32_t *ptype_tbl;
 722
 723         nb_rx = 0;
 724         nb_hold = 0;
 725         rxq = rx_queue;
 726         rx_id = rxq->rx_tail;
 727         rx_ring = rxq->rx_ring;
 728         sw_ring = rxq->sw_ring;
 729         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 730
 731         while (nb_rx < nb_pkts) {
 732                 rxdp = &rx_ring[rx_id];
 733                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 734                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 735                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 736
 737                 /* Check the DD bit first */
 738                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 739                         break;
 740
 741                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 742                 if (unlikely(!nmb)) {
 743                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 744                         dev->data->rx_mbuf_alloc_failed++;
 745                         break;
 746                 }
 747
 748                 rxd = *rxdp;
 749                 nb_hold++;
 750                 rxe = &sw_ring[rx_id];
 751                 rx_id++;
 752                 if (unlikely(rx_id == rxq->nb_rx_desc))
 753                         rx_id = 0;
 754
 755                 /* Prefetch next mbuf */
 756                 rte_prefetch0(sw_ring[rx_id].mbuf);
 757
 758                 /**
 759                  * When next RX descriptor is on a cache line boundary,
 760                  * prefetch the next 4 RX descriptors and next 8 pointers
 761                  * to mbufs.
 762                  */
 763                 if ((rx_id & 0x3) == 0) {
 764                         rte_prefetch0(&rx_ring[rx_id]);
 765                         rte_prefetch0(&sw_ring[rx_id]);
 766                 }
 767                 rxm = rxe->mbuf;
 768                 rxe->mbuf = nmb;
 769                 dma_addr =
 770                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 771                 rxdp->read.hdr_addr = 0;
 772                 rxdp->read.pkt_addr = dma_addr;
 773
 774                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 775                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 776
 777                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 778                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 779                 rxm->nb_segs = 1;
 780                 rxm->next = NULL;
 781                 rxm->pkt_len = rx_packet_len;
 782                 rxm->data_len = rx_packet_len;
 783                 rxm->port = rxq->port_id;
 784                 rxm->ol_flags = 0;
 785                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 786                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 787                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 788                 rxm->packet_type =
 789                         ptype_tbl[(uint8_t)((qword1 &
 790                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 791                 if (pkt_flags & PKT_RX_RSS_HASH)
 792                         rxm->hash.rss =
 793                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 794                 if (pkt_flags & PKT_RX_FDIR)
 795                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 796
 797 #ifdef RTE_LIBRTE_IEEE1588
 798                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 799 #endif
 800                 rxm->ol_flags |= pkt_flags;
 801
 802                 rx_pkts[nb_rx++] = rxm;
 803         }
 804         rxq->rx_tail = rx_id;
 805
 806         /**
 807          * If the number of free RX descriptors is greater than the RX free
 808          * threshold of the queue, advance the receive tail register of queue.
 809          * Update that register with the value of the last processed RX
 810          * descriptor minus 1.
 811          */
 812         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 813         if (nb_hold > rxq->rx_free_thresh) {
 814                 rx_id = (uint16_t) ((rx_id == 0) ?
 815                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 816                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 817                 nb_hold = 0;
 818         }
 819         rxq->nb_rx_hold = nb_hold;
 820
 821         return nb_rx;
 822 }
 823
 824 uint16_t
 825 i40e_recv_scattered_pkts(void *rx_queue,
 826                          struct rte_mbuf **rx_pkts,
 827                          uint16_t nb_pkts)
 828 {
 829         struct i40e_rx_queue *rxq = rx_queue;
 830         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 831         volatile union i40e_rx_desc *rxdp;
 832         union i40e_rx_desc rxd;
 833         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 834         struct i40e_rx_entry *rxe;
 835         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 836         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 837         struct rte_mbuf *nmb, *rxm;
 838         uint16_t rx_id = rxq->rx_tail;
 839         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 840         struct rte_eth_dev *dev;
 841         uint32_t rx_status;
 842         uint64_t qword1;
 843         uint64_t dma_addr;
 844         uint64_t pkt_flags;
 845         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 846
 847         while (nb_rx < nb_pkts) {
 848                 rxdp = &rx_ring[rx_id];
 849                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 850                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 851                                         I40E_RXD_QW1_STATUS_SHIFT;
 852
 853                 /* Check the DD bit */
 854                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 855                         break;
 856
 857                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 858                 if (unlikely(!nmb)) {
 859                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 860                         dev->data->rx_mbuf_alloc_failed++;
 861                         break;
 862                 }
 863
 864                 rxd = *rxdp;
 865                 nb_hold++;
 866                 rxe = &sw_ring[rx_id];
 867                 rx_id++;
 868                 if (rx_id == rxq->nb_rx_desc)
 869                         rx_id = 0;
 870
 871                 /* Prefetch next mbuf */
 872                 rte_prefetch0(sw_ring[rx_id].mbuf);
 873
 874                 /**
 875                  * When next RX descriptor is on a cache line boundary,
 876                  * prefetch the next 4 RX descriptors and next 8 pointers
 877                  * to mbufs.
 878                  */
 879                 if ((rx_id & 0x3) == 0) {
 880                         rte_prefetch0(&rx_ring[rx_id]);
 881                         rte_prefetch0(&sw_ring[rx_id]);
 882                 }
 883
 884                 rxm = rxe->mbuf;
 885                 rxe->mbuf = nmb;
 886                 dma_addr =
 887                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 888
 889                 /* Set data buffer address and data length of the mbuf */
 890                 rxdp->read.hdr_addr = 0;
 891                 rxdp->read.pkt_addr = dma_addr;
 892                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 893                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 894                 rxm->data_len = rx_packet_len;
 895                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 896
 897                 /**
 898                  * If this is the first buffer of the received packet, set the
 899                  * pointer to the first mbuf of the packet and initialize its
 900                  * context. Otherwise, update the total length and the number
 901                  * of segments of the current scattered packet, and update the
 902                  * pointer to the last mbuf of the current packet.
 903                  */
 904                 if (!first_seg) {
 905                         first_seg = rxm;
 906                         first_seg->nb_segs = 1;
 907                         first_seg->pkt_len = rx_packet_len;
 908                 } else {
 909                         first_seg->pkt_len =
 910                                 (uint16_t)(first_seg->pkt_len +
 911                                                 rx_packet_len);
 912                         first_seg->nb_segs++;
 913                         last_seg->next = rxm;
 914                 }
 915
 916                 /**
 917                  * If this is not the last buffer of the received packet,
 918                  * update the pointer to the last mbuf of the current scattered
 919                  * packet and continue to parse the RX ring.
 920                  */
 921                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 922                         last_seg = rxm;
 923                         continue;
 924                 }
 925
 926                 /**
 927                  * This is the last buffer of the received packet. If the CRC
 928                  * is not stripped by the hardware:
 929                  *  - Subtract the CRC length from the total packet length.
 930                  *  - If the last buffer only contains the whole CRC or a part
 931                  *  of it, free the mbuf associated to the last buffer. If part
 932                  *  of the CRC is also contained in the previous mbuf, subtract
 933                  *  the length of that CRC part from the data length of the
 934                  *  previous mbuf.
 935                  */
 936                 rxm->next = NULL;
 937                 if (unlikely(rxq->crc_len > 0)) {
 938                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 939                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 940                                 rte_pktmbuf_free_seg(rxm);
 941                                 first_seg->nb_segs--;
 942                                 last_seg->data_len =
 943                                         (uint16_t)(last_seg->data_len -
 944                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 945                                 last_seg->next = NULL;
 946                         } else
 947                                 rxm->data_len = (uint16_t)(rx_packet_len -
 948                                                         RTE_ETHER_CRC_LEN);
 949                 }
 950
 951                 first_seg->port = rxq->port_id;
 952                 first_seg->ol_flags = 0;
 953                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 954                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 955                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 956                 first_seg->packet_type =
 957                         ptype_tbl[(uint8_t)((qword1 &
 958                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 959                 if (pkt_flags & PKT_RX_RSS_HASH)
 960                         first_seg->hash.rss =
 961                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 962                 if (pkt_flags & PKT_RX_FDIR)
 963                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 964
 965 #ifdef RTE_LIBRTE_IEEE1588
 966                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 967 #endif
 968                 first_seg->ol_flags |= pkt_flags;
 969
 970                 /* Prefetch data of first segment, if configured to do so. */
 971                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 972                         first_seg->data_off));
 973                 rx_pkts[nb_rx++] = first_seg;
 974                 first_seg = NULL;
 975         }
 976
 977         /* Record index of the next RX descriptor to probe. */
 978         rxq->rx_tail = rx_id;
 979         rxq->pkt_first_seg = first_seg;
 980         rxq->pkt_last_seg = last_seg;
 981
 982         /**
 983          * If the number of free RX descriptors is greater than the RX free
 984          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 985          * register. Update the RDT with the value of the last processed RX
 986          * descriptor minus 1, to guarantee that the RDT register is never
 987          * equal to the RDH register, which creates a "full" ring situtation
 988          * from the hardware point of view.
 989          */
 990         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 991         if (nb_hold > rxq->rx_free_thresh) {
 992                 rx_id = (uint16_t)(rx_id == 0 ?
 993                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 994                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 995                 nb_hold = 0;
 996         }
 997         rxq->nb_rx_hold = nb_hold;
 998
 999         return nb_rx;
1000 }
1001
1002 /* Check if the context descriptor is needed for TX offloading */
1003 static inline uint16_t
1004 i40e_calc_context_desc(uint64_t flags)
1005 {
1006         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1007                 PKT_TX_TCP_SEG |
1008                 PKT_TX_QINQ_PKT |
1009                 PKT_TX_TUNNEL_MASK;
1010
1011 #ifdef RTE_LIBRTE_IEEE1588
1012         mask |= PKT_TX_IEEE1588_TMST;
1013 #endif
1014
1015         return (flags & mask) ? 1 : 0;
1016 }
1017
1018 /* set i40e TSO context descriptor */
1019 static inline uint64_t
1020 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1021 {
1022         uint64_t ctx_desc = 0;
1023         uint32_t cd_cmd, hdr_len, cd_tso_len;
1024
1025         if (!tx_offload.l4_len) {
1026                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1027                 return ctx_desc;
1028         }
1029
1030         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1031         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1032                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1033
1034         cd_cmd = I40E_TX_CTX_DESC_TSO;
1035         cd_tso_len = mbuf->pkt_len - hdr_len;
1036         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1037                 ((uint64_t)cd_tso_len <<
1038                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1039                 ((uint64_t)mbuf->tso_segsz <<
1040                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1041
1042         return ctx_desc;
1043 }
1044
1045 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1046 #define I40E_MAX_DATA_PER_TXD \
1047         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1048 /* Calculate the number of TX descriptors needed for each pkt */
1049 static inline uint16_t
1050 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1051 {
1052         struct rte_mbuf *txd = tx_pkt;
1053         uint16_t count = 0;
1054
1055         while (txd != NULL) {
1056                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1057                 txd = txd->next;
1058         }
1059
1060         return count;
1061 }
1062
1063 uint16_t
1064 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1065 {
1066         struct i40e_tx_queue *txq;
1067         struct i40e_tx_entry *sw_ring;
1068         struct i40e_tx_entry *txe, *txn;
1069         volatile struct i40e_tx_desc *txd;
1070         volatile struct i40e_tx_desc *txr;
1071         struct rte_mbuf *tx_pkt;
1072         struct rte_mbuf *m_seg;
1073         uint32_t cd_tunneling_params;
1074         uint16_t tx_id;
1075         uint16_t nb_tx;
1076         uint32_t td_cmd;
1077         uint32_t td_offset;
1078         uint32_t td_tag;
1079         uint64_t ol_flags;
1080         uint16_t nb_used;
1081         uint16_t nb_ctx;
1082         uint16_t tx_last;
1083         uint16_t slen;
1084         uint64_t buf_dma_addr;
1085         union i40e_tx_offload tx_offload = {0};
1086
1087         txq = tx_queue;
1088         sw_ring = txq->sw_ring;
1089         txr = txq->tx_ring;
1090         tx_id = txq->tx_tail;
1091         txe = &sw_ring[tx_id];
1092
1093         /* Check if the descriptor ring needs to be cleaned. */
1094         if (txq->nb_tx_free < txq->tx_free_thresh)
1095                 (void)i40e_xmit_cleanup(txq);
1096
1097         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1098                 td_cmd = 0;
1099                 td_tag = 0;
1100                 td_offset = 0;
1101
1102                 tx_pkt = *tx_pkts++;
1103                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1104
1105                 ol_flags = tx_pkt->ol_flags;
1106                 tx_offload.l2_len = tx_pkt->l2_len;
1107                 tx_offload.l3_len = tx_pkt->l3_len;
1108                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1109                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1110                 tx_offload.l4_len = tx_pkt->l4_len;
1111                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1112
1113                 /* Calculate the number of context descriptors needed. */
1114                 nb_ctx = i40e_calc_context_desc(ol_flags);
1115
1116                 /**
1117                  * The number of descriptors that must be allocated for
1118                  * a packet equals to the number of the segments of that
1119                  * packet plus 1 context descriptor if needed.
1120                  * Recalculate the needed tx descs when TSO enabled in case
1121                  * the mbuf data size exceeds max data size that hw allows
1122                  * per tx desc.
1123                  */
1124                 if (ol_flags & PKT_TX_TCP_SEG)
1125                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1126                                              nb_ctx);
1127                 else
1128                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1129                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1130
1131                 /* Circular ring */
1132                 if (tx_last >= txq->nb_tx_desc)
1133                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1134
1135                 if (nb_used > txq->nb_tx_free) {
1136                         if (i40e_xmit_cleanup(txq) != 0) {
1137                                 if (nb_tx == 0)
1138                                         return 0;
1139                                 goto end_of_tx;
1140                         }
1141                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1142                                 while (nb_used > txq->nb_tx_free) {
1143                                         if (i40e_xmit_cleanup(txq) != 0) {
1144                                                 if (nb_tx == 0)
1145                                                         return 0;
1146                                                 goto end_of_tx;
1147                                         }
1148                                 }
1149                         }
1150                 }
1151
1152                 /* Descriptor based VLAN insertion */
1153                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1154                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1155                         td_tag = tx_pkt->vlan_tci;
1156                 }
1157
1158                 /* Always enable CRC offload insertion */
1159                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1160
1161                 /* Fill in tunneling parameters if necessary */
1162                 cd_tunneling_params = 0;
1163                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1164                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1165                                                     &cd_tunneling_params);
1166                 /* Enable checksum offloading */
1167                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1168                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1169                                                  &td_offset, tx_offload);
1170
1171                 if (nb_ctx) {
1172                         /* Setup TX context descriptor if required */
1173                         volatile struct i40e_tx_context_desc *ctx_txd =
1174                                 (volatile struct i40e_tx_context_desc *)\
1175                                                         &txr[tx_id];
1176                         uint16_t cd_l2tag2 = 0;
1177                         uint64_t cd_type_cmd_tso_mss =
1178                                 I40E_TX_DESC_DTYPE_CONTEXT;
1179
1180                         txn = &sw_ring[txe->next_id];
1181                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1182                         if (txe->mbuf != NULL) {
1183                                 rte_pktmbuf_free_seg(txe->mbuf);
1184                                 txe->mbuf = NULL;
1185                         }
1186
1187                         /* TSO enabled means no timestamp */
1188                         if (ol_flags & PKT_TX_TCP_SEG)
1189                                 cd_type_cmd_tso_mss |=
1190                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1191                         else {
1192 #ifdef RTE_LIBRTE_IEEE1588
1193                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1194                                         cd_type_cmd_tso_mss |=
1195                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1196                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1197 #endif
1198                         }
1199
1200                         ctx_txd->tunneling_params =
1201                                 rte_cpu_to_le_32(cd_tunneling_params);
1202                         if (ol_flags & PKT_TX_QINQ_PKT) {
1203                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1204                                 cd_type_cmd_tso_mss |=
1205                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1206                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1207                         }
1208                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1209                         ctx_txd->type_cmd_tso_mss =
1210                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1211
1212                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1213                                 "tunneling_params: %#x;\n"
1214                                 "l2tag2: %#hx;\n"
1215                                 "rsvd: %#hx;\n"
1216                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1217                                 tx_pkt, tx_id,
1218                                 ctx_txd->tunneling_params,
1219                                 ctx_txd->l2tag2,
1220                                 ctx_txd->rsvd,
1221                                 ctx_txd->type_cmd_tso_mss);
1222
1223                         txe->last_id = tx_last;
1224                         tx_id = txe->next_id;
1225                         txe = txn;
1226                 }
1227
1228                 m_seg = tx_pkt;
1229                 do {
1230                         txd = &txr[tx_id];
1231                         txn = &sw_ring[txe->next_id];
1232
1233                         if (txe->mbuf)
1234                                 rte_pktmbuf_free_seg(txe->mbuf);
1235                         txe->mbuf = m_seg;
1236
1237                         /* Setup TX Descriptor */
1238                         slen = m_seg->data_len;
1239                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1240
1241                         while ((ol_flags & PKT_TX_TCP_SEG) &&
1242                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1243                                 txd->buffer_addr =
1244                                         rte_cpu_to_le_64(buf_dma_addr);
1245                                 txd->cmd_type_offset_bsz =
1246                                         i40e_build_ctob(td_cmd,
1247                                         td_offset, I40E_MAX_DATA_PER_TXD,
1248                                         td_tag);
1249
1250                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1251                                 slen -= I40E_MAX_DATA_PER_TXD;
1252
1253                                 txe->last_id = tx_last;
1254                                 tx_id = txe->next_id;
1255                                 txe = txn;
1256                                 txd = &txr[tx_id];
1257                                 txn = &sw_ring[txe->next_id];
1258                         }
1259                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1260                                 "buf_dma_addr: %#"PRIx64";\n"
1261                                 "td_cmd: %#x;\n"
1262                                 "td_offset: %#x;\n"
1263                                 "td_len: %u;\n"
1264                                 "td_tag: %#x;\n",
1265                                 tx_pkt, tx_id, buf_dma_addr,
1266                                 td_cmd, td_offset, slen, td_tag);
1267
1268                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1269                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1270                                                 td_offset, slen, td_tag);
1271                         txe->last_id = tx_last;
1272                         tx_id = txe->next_id;
1273                         txe = txn;
1274                         m_seg = m_seg->next;
1275                 } while (m_seg != NULL);
1276
1277                 /* The last packet data descriptor needs End Of Packet (EOP) */
1278                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1279                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1280                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1281
1282                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1283                         PMD_TX_LOG(DEBUG,
1284                                    "Setting RS bit on TXD id="
1285                                    "%4u (port=%d queue=%d)",
1286                                    tx_last, txq->port_id, txq->queue_id);
1287
1288                         td_cmd |= I40E_TX_DESC_CMD_RS;
1289
1290                         /* Update txq RS bit counters */
1291                         txq->nb_tx_used = 0;
1292                 }
1293
1294                 txd->cmd_type_offset_bsz |=
1295                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1296                                         I40E_TXD_QW1_CMD_SHIFT);
1297         }
1298
1299 end_of_tx:
1300         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1301                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1302                    (unsigned) tx_id, (unsigned) nb_tx);
1303
1304         rte_io_wmb();
1305         I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1306         txq->tx_tail = tx_id;
1307
1308         return nb_tx;
1309 }
1310
1311 static __rte_always_inline int
1312 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1313 {
1314         struct i40e_tx_entry *txep;
1315         uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1316         uint16_t i = 0, j = 0;
1317         struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1318         const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1319         const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1320
1321         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1322                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1323                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1324                 return 0;
1325
1326         txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1327
1328         for (i = 0; i < tx_rs_thresh; i++)
1329                 rte_prefetch0((txep + i)->mbuf);
1330
1331         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1332                 if (k) {
1333                         for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1334                                 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1335                                         free[i] = txep->mbuf;
1336                                         txep->mbuf = NULL;
1337                                 }
1338                                 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1339                                                 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1340                         }
1341                 }
1342
1343                 if (m) {
1344                         for (i = 0; i < m; ++i, ++txep) {
1345                                 free[i] = txep->mbuf;
1346                                 txep->mbuf = NULL;
1347                         }
1348                         rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1349                 }
1350         } else {
1351                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1352                         rte_pktmbuf_free_seg(txep->mbuf);
1353                         txep->mbuf = NULL;
1354                 }
1355         }
1356
1357         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1358         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1359         if (txq->tx_next_dd >= txq->nb_tx_desc)
1360                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1361
1362         return txq->tx_rs_thresh;
1363 }
1364
1365 /* Populate 4 descriptors with data from 4 mbufs */
1366 static inline void
1367 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1368 {
1369         uint64_t dma_addr;
1370         uint32_t i;
1371
1372         for (i = 0; i < 4; i++, txdp++, pkts++) {
1373                 dma_addr = rte_mbuf_data_iova(*pkts);
1374                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1375                 txdp->cmd_type_offset_bsz =
1376                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1377                                         (*pkts)->data_len, 0);
1378         }
1379 }
1380
1381 /* Populate 1 descriptor with data from 1 mbuf */
1382 static inline void
1383 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1384 {
1385         uint64_t dma_addr;
1386
1387         dma_addr = rte_mbuf_data_iova(*pkts);
1388         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1389         txdp->cmd_type_offset_bsz =
1390                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1391                                 (*pkts)->data_len, 0);
1392 }
1393
1394 /* Fill hardware descriptor ring with mbuf data */
1395 static inline void
1396 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1397                      struct rte_mbuf **pkts,
1398                      uint16_t nb_pkts)
1399 {
1400         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1401         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1402         const int N_PER_LOOP = 4;
1403         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1404         int mainpart, leftover;
1405         int i, j;
1406
1407         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1408         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1409         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1410                 for (j = 0; j < N_PER_LOOP; ++j) {
1411                         (txep + i + j)->mbuf = *(pkts + i + j);
1412                 }
1413                 tx4(txdp + i, pkts + i);
1414         }
1415         if (unlikely(leftover > 0)) {
1416                 for (i = 0; i < leftover; ++i) {
1417                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1418                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1419                 }
1420         }
1421 }
1422
1423 static inline uint16_t
1424 tx_xmit_pkts(struct i40e_tx_queue *txq,
1425              struct rte_mbuf **tx_pkts,
1426              uint16_t nb_pkts)
1427 {
1428         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1429         uint16_t n = 0;
1430
1431         /**
1432          * Begin scanning the H/W ring for done descriptors when the number
1433          * of available descriptors drops below tx_free_thresh. For each done
1434          * descriptor, free the associated buffer.
1435          */
1436         if (txq->nb_tx_free < txq->tx_free_thresh)
1437                 i40e_tx_free_bufs(txq);
1438
1439         /* Use available descriptor only */
1440         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1441         if (unlikely(!nb_pkts))
1442                 return 0;
1443
1444         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1445         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1446                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1447                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1448                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1449                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1450                                                 I40E_TXD_QW1_CMD_SHIFT);
1451                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1452                 txq->tx_tail = 0;
1453         }
1454
1455         /* Fill hardware descriptor ring with mbuf data */
1456         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1457         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1458
1459         /* Determin if RS bit needs to be set */
1460         if (txq->tx_tail > txq->tx_next_rs) {
1461                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1462                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1463                                                 I40E_TXD_QW1_CMD_SHIFT);
1464                 txq->tx_next_rs =
1465                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1466                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1467                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1468         }
1469
1470         if (txq->tx_tail >= txq->nb_tx_desc)
1471                 txq->tx_tail = 0;
1472
1473         /* Update the tx tail register */
1474         I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1475
1476         return nb_pkts;
1477 }
1478
1479 static uint16_t
1480 i40e_xmit_pkts_simple(void *tx_queue,
1481                       struct rte_mbuf **tx_pkts,
1482                       uint16_t nb_pkts)
1483 {
1484         uint16_t nb_tx = 0;
1485
1486         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1487                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1488                                                 tx_pkts, nb_pkts);
1489
1490         while (nb_pkts) {
1491                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1492                                                 I40E_TX_MAX_BURST);
1493
1494                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1495                                                 &tx_pkts[nb_tx], num);
1496                 nb_tx = (uint16_t)(nb_tx + ret);
1497                 nb_pkts = (uint16_t)(nb_pkts - ret);
1498                 if (ret < num)
1499                         break;
1500         }
1501
1502         return nb_tx;
1503 }
1504
1505 static uint16_t
1506 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1507                    uint16_t nb_pkts)
1508 {
1509         uint16_t nb_tx = 0;
1510         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1511
1512         while (nb_pkts) {
1513                 uint16_t ret, num;
1514
1515                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1516                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1517                                                 num);
1518                 nb_tx += ret;
1519                 nb_pkts -= ret;
1520                 if (ret < num)
1521                         break;
1522         }
1523
1524         return nb_tx;
1525 }
1526
1527 /*********************************************************************
1528  *
1529  *  TX simple prep functions
1530  *
1531  **********************************************************************/
1532 uint16_t
1533 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1534                       uint16_t nb_pkts)
1535 {
1536         int i;
1537         uint64_t ol_flags;
1538         struct rte_mbuf *m;
1539
1540         for (i = 0; i < nb_pkts; i++) {
1541                 m = tx_pkts[i];
1542                 ol_flags = m->ol_flags;
1543
1544                 if (m->nb_segs != 1) {
1545                         rte_errno = EINVAL;
1546                         return i;
1547                 }
1548
1549                 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1550                         rte_errno = ENOTSUP;
1551                         return i;
1552                 }
1553
1554                 /* check the size of packet */
1555                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1556                     m->pkt_len > I40E_FRAME_SIZE_MAX) {
1557                         rte_errno = EINVAL;
1558                         return i;
1559                 }
1560         }
1561         return i;
1562 }
1563
1564 /*********************************************************************
1565  *
1566  *  TX prep functions
1567  *
1568  **********************************************************************/
1569 uint16_t
1570 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1571                 uint16_t nb_pkts)
1572 {
1573         int i, ret;
1574         uint64_t ol_flags;
1575         struct rte_mbuf *m;
1576
1577         for (i = 0; i < nb_pkts; i++) {
1578                 m = tx_pkts[i];
1579                 ol_flags = m->ol_flags;
1580
1581                 /* Check for m->nb_segs to not exceed the limits. */
1582                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1583                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1584                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1585                                 rte_errno = EINVAL;
1586                                 return i;
1587                         }
1588                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1589                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1590                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1591                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1592                         /* MSS outside the range (256B - 9674B) are considered
1593                          * malicious
1594                          */
1595                         rte_errno = EINVAL;
1596                         return i;
1597                 }
1598
1599                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1600                         rte_errno = ENOTSUP;
1601                         return i;
1602                 }
1603
1604                 /* check the size of packet */
1605                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1606                         rte_errno = EINVAL;
1607                         return i;
1608                 }
1609
1610 #ifdef RTE_ETHDEV_DEBUG_TX
1611                 ret = rte_validate_tx_offload(m);
1612                 if (ret != 0) {
1613                         rte_errno = -ret;
1614                         return i;
1615                 }
1616 #endif
1617                 ret = rte_net_intel_cksum_prepare(m);
1618                 if (ret != 0) {
1619                         rte_errno = -ret;
1620                         return i;
1621                 }
1622         }
1623         return i;
1624 }
1625
1626 /*
1627  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1628  * application used, which assume having sequential ones. But from driver's
1629  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1630  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1631  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1632  * use queue_idx from 0 to 95 to access queues, while real queue would be
1633  * different. This function will do a queue mapping to find VSI the queue
1634  * belongs to.
1635  */
1636 static struct i40e_vsi*
1637 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1638 {
1639         /* the queue in MAIN VSI range */
1640         if (queue_idx < pf->main_vsi->nb_qps)
1641                 return pf->main_vsi;
1642
1643         queue_idx -= pf->main_vsi->nb_qps;
1644
1645         /* queue_idx is greater than VMDQ VSIs range */
1646         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1647                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1648                 return NULL;
1649         }
1650
1651         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1652 }
1653
1654 static uint16_t
1655 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1656 {
1657         /* the queue in MAIN VSI range */
1658         if (queue_idx < pf->main_vsi->nb_qps)
1659                 return queue_idx;
1660
1661         /* It's VMDQ queues */
1662         queue_idx -= pf->main_vsi->nb_qps;
1663
1664         if (pf->nb_cfg_vmdq_vsi)
1665                 return queue_idx % pf->vmdq_nb_qps;
1666         else {
1667                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1668                 return (uint16_t)(-1);
1669         }
1670 }
1671
1672 int
1673 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1674 {
1675         struct i40e_rx_queue *rxq;
1676         int err;
1677         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         rxq = dev->data->rx_queues[rx_queue_id];
1682         if (!rxq || !rxq->q_set) {
1683                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1684                             rx_queue_id);
1685                 return -EINVAL;
1686         }
1687
1688         if (rxq->rx_deferred_start)
1689                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1690                             rx_queue_id);
1691
1692         err = i40e_alloc_rx_queue_mbufs(rxq);
1693         if (err) {
1694                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1695                 return err;
1696         }
1697
1698         /* Init the RX tail regieter. */
1699         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1700
1701         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1702         if (err) {
1703                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1704                             rx_queue_id);
1705
1706                 i40e_rx_queue_release_mbufs(rxq);
1707                 i40e_reset_rx_queue(rxq);
1708                 return err;
1709         }
1710         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1711
1712         return 0;
1713 }
1714
1715 int
1716 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1717 {
1718         struct i40e_rx_queue *rxq;
1719         int err;
1720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721
1722         rxq = dev->data->rx_queues[rx_queue_id];
1723         if (!rxq || !rxq->q_set) {
1724                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1725                                 rx_queue_id);
1726                 return -EINVAL;
1727         }
1728
1729         /*
1730          * rx_queue_id is queue id application refers to, while
1731          * rxq->reg_idx is the real queue index.
1732          */
1733         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1734         if (err) {
1735                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1736                             rx_queue_id);
1737                 return err;
1738         }
1739         i40e_rx_queue_release_mbufs(rxq);
1740         i40e_reset_rx_queue(rxq);
1741         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1742
1743         return 0;
1744 }
1745
1746 int
1747 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1748 {
1749         int err;
1750         struct i40e_tx_queue *txq;
1751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752
1753         PMD_INIT_FUNC_TRACE();
1754
1755         txq = dev->data->tx_queues[tx_queue_id];
1756         if (!txq || !txq->q_set) {
1757                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1758                             tx_queue_id);
1759                 return -EINVAL;
1760         }
1761
1762         if (txq->tx_deferred_start)
1763                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1764                             tx_queue_id);
1765
1766         /*
1767          * tx_queue_id is queue id application refers to, while
1768          * rxq->reg_idx is the real queue index.
1769          */
1770         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1771         if (err) {
1772                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1773                             tx_queue_id);
1774                 return err;
1775         }
1776         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1777
1778         return 0;
1779 }
1780
1781 int
1782 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1783 {
1784         struct i40e_tx_queue *txq;
1785         int err;
1786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787
1788         txq = dev->data->tx_queues[tx_queue_id];
1789         if (!txq || !txq->q_set) {
1790                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1791                         tx_queue_id);
1792                 return -EINVAL;
1793         }
1794
1795         /*
1796          * tx_queue_id is queue id application refers to, while
1797          * txq->reg_idx is the real queue index.
1798          */
1799         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1800         if (err) {
1801                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1802                             tx_queue_id);
1803                 return err;
1804         }
1805
1806         i40e_tx_queue_release_mbufs(txq);
1807         i40e_reset_tx_queue(txq);
1808         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1809
1810         return 0;
1811 }
1812
1813 const uint32_t *
1814 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1815 {
1816         static const uint32_t ptypes[] = {
1817                 /* refers to i40e_rxd_pkt_type_mapping() */
1818                 RTE_PTYPE_L2_ETHER,
1819                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1820                 RTE_PTYPE_L2_ETHER_LLDP,
1821                 RTE_PTYPE_L2_ETHER_ARP,
1822                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1823                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1824                 RTE_PTYPE_L4_FRAG,
1825                 RTE_PTYPE_L4_ICMP,
1826                 RTE_PTYPE_L4_NONFRAG,
1827                 RTE_PTYPE_L4_SCTP,
1828                 RTE_PTYPE_L4_TCP,
1829                 RTE_PTYPE_L4_UDP,
1830                 RTE_PTYPE_TUNNEL_GRENAT,
1831                 RTE_PTYPE_TUNNEL_IP,
1832                 RTE_PTYPE_INNER_L2_ETHER,
1833                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1834                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1835                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1836                 RTE_PTYPE_INNER_L4_FRAG,
1837                 RTE_PTYPE_INNER_L4_ICMP,
1838                 RTE_PTYPE_INNER_L4_NONFRAG,
1839                 RTE_PTYPE_INNER_L4_SCTP,
1840                 RTE_PTYPE_INNER_L4_TCP,
1841                 RTE_PTYPE_INNER_L4_UDP,
1842                 RTE_PTYPE_UNKNOWN
1843         };
1844
1845         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1846 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1847             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1848 #endif
1849             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1850             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1851             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1852 #ifdef CC_AVX512_SUPPORT
1853             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1854             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1855 #endif
1856             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1857             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1858                 return ptypes;
1859         return NULL;
1860 }
1861
1862 static int
1863 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1864 {
1865         uint16_t i;
1866
1867         for (i = 0; i < num; i++) {
1868                 if (i != idx && queues[i])
1869                         return 0;
1870         }
1871
1872         return 1;
1873 }
1874
1875 static int
1876 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1877                                 struct i40e_rx_queue *rxq)
1878 {
1879         struct i40e_adapter *ad =
1880                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1881         int use_def_burst_func =
1882                 check_rx_burst_bulk_alloc_preconditions(rxq);
1883         uint16_t buf_size =
1884                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1885                            RTE_PKTMBUF_HEADROOM);
1886         int use_scattered_rx =
1887                 (rxq->max_pkt_len > buf_size);
1888
1889         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1890                 PMD_DRV_LOG(ERR,
1891                             "Failed to do RX queue initialization");
1892                 return -EINVAL;
1893         }
1894
1895         if (i40e_dev_first_queue(rxq->queue_id,
1896                                  dev->data->rx_queues,
1897                                  dev->data->nb_rx_queues)) {
1898                 /**
1899                  * If it is the first queue to setup,
1900                  * set all flags to default and call
1901                  * i40e_set_rx_function.
1902                  */
1903                 ad->rx_bulk_alloc_allowed = true;
1904                 ad->rx_vec_allowed = true;
1905                 dev->data->scattered_rx = use_scattered_rx;
1906                 if (use_def_burst_func)
1907                         ad->rx_bulk_alloc_allowed = false;
1908                 i40e_set_rx_function(dev);
1909                 return 0;
1910         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1911                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1912                             " number %d of queue %d isn't power of 2",
1913                             rxq->nb_rx_desc, rxq->queue_id);
1914                 return -EINVAL;
1915         }
1916
1917         /* check bulk alloc conflict */
1918         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1919                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1920                 return -EINVAL;
1921         }
1922         /* check scatterred conflict */
1923         if (!dev->data->scattered_rx && use_scattered_rx) {
1924                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1925                 return -EINVAL;
1926         }
1927         /* check vector conflict */
1928         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1929                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1930                 return -EINVAL;
1931         }
1932
1933         return 0;
1934 }
1935
1936 int
1937 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1938                         uint16_t queue_idx,
1939                         uint16_t nb_desc,
1940                         unsigned int socket_id,
1941                         const struct rte_eth_rxconf *rx_conf,
1942                         struct rte_mempool *mp)
1943 {
1944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945         struct i40e_adapter *ad =
1946                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1947         struct i40e_vsi *vsi;
1948         struct i40e_pf *pf = NULL;
1949         struct i40e_vf *vf = NULL;
1950         struct i40e_rx_queue *rxq;
1951         const struct rte_memzone *rz;
1952         uint32_t ring_size;
1953         uint16_t len, i;
1954         uint16_t reg_idx, base, bsf, tc_mapping;
1955         int q_offset, use_def_burst_func = 1;
1956         uint64_t offloads;
1957
1958         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1959
1960         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1961                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1962                 vsi = &vf->vsi;
1963                 if (!vsi)
1964                         return -EINVAL;
1965                 reg_idx = queue_idx;
1966         } else {
1967                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1968                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1969                 if (!vsi)
1970                         return -EINVAL;
1971                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1972                 if (q_offset < 0)
1973                         return -EINVAL;
1974                 reg_idx = vsi->base_queue + q_offset;
1975         }
1976
1977         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1978             (nb_desc > I40E_MAX_RING_DESC) ||
1979             (nb_desc < I40E_MIN_RING_DESC)) {
1980                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1981                             "invalid", nb_desc);
1982                 return -EINVAL;
1983         }
1984
1985         /* Free memory if needed */
1986         if (dev->data->rx_queues[queue_idx]) {
1987                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1988                 dev->data->rx_queues[queue_idx] = NULL;
1989         }
1990
1991         /* Allocate the rx queue data structure */
1992         rxq = rte_zmalloc_socket("i40e rx queue",
1993                                  sizeof(struct i40e_rx_queue),
1994                                  RTE_CACHE_LINE_SIZE,
1995                                  socket_id);
1996         if (!rxq) {
1997                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1998                             "rx queue data structure");
1999                 return -ENOMEM;
2000         }
2001         rxq->mp = mp;
2002         rxq->nb_rx_desc = nb_desc;
2003         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2004         rxq->queue_id = queue_idx;
2005         rxq->reg_idx = reg_idx;
2006         rxq->port_id = dev->data->port_id;
2007         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
2008                 rxq->crc_len = RTE_ETHER_CRC_LEN;
2009         else
2010                 rxq->crc_len = 0;
2011         rxq->drop_en = rx_conf->rx_drop_en;
2012         rxq->vsi = vsi;
2013         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2014         rxq->offloads = offloads;
2015
2016         /* Allocate the maximun number of RX ring hardware descriptor. */
2017         len = I40E_MAX_RING_DESC;
2018
2019         /**
2020          * Allocating a little more memory because vectorized/bulk_alloc Rx
2021          * functions doesn't check boundaries each time.
2022          */
2023         len += RTE_PMD_I40E_RX_MAX_BURST;
2024
2025         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2026                               I40E_DMA_MEM_ALIGN);
2027
2028         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2029                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2030         if (!rz) {
2031                 i40e_dev_rx_queue_release(rxq);
2032                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2033                 return -ENOMEM;
2034         }
2035
2036         /* Zero all the descriptors in the ring. */
2037         memset(rz->addr, 0, ring_size);
2038
2039         rxq->rx_ring_phys_addr = rz->iova;
2040         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2041
2042         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2043
2044         /* Allocate the software ring. */
2045         rxq->sw_ring =
2046                 rte_zmalloc_socket("i40e rx sw ring",
2047                                    sizeof(struct i40e_rx_entry) * len,
2048                                    RTE_CACHE_LINE_SIZE,
2049                                    socket_id);
2050         if (!rxq->sw_ring) {
2051                 i40e_dev_rx_queue_release(rxq);
2052                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2053                 return -ENOMEM;
2054         }
2055
2056         i40e_reset_rx_queue(rxq);
2057         rxq->q_set = TRUE;
2058
2059         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2060                 if (!(vsi->enabled_tc & (1 << i)))
2061                         continue;
2062                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2063                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2064                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2065                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2066                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2067
2068                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2069                         rxq->dcb_tc = i;
2070         }
2071
2072         if (dev->data->dev_started) {
2073                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2074                         i40e_dev_rx_queue_release(rxq);
2075                         return -EINVAL;
2076                 }
2077         } else {
2078                 use_def_burst_func =
2079                         check_rx_burst_bulk_alloc_preconditions(rxq);
2080                 if (!use_def_burst_func) {
2081 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2082                         PMD_INIT_LOG(DEBUG,
2083                           "Rx Burst Bulk Alloc Preconditions are "
2084                           "satisfied. Rx Burst Bulk Alloc function will be "
2085                           "used on port=%d, queue=%d.",
2086                           rxq->port_id, rxq->queue_id);
2087 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2088                 } else {
2089                         PMD_INIT_LOG(DEBUG,
2090                           "Rx Burst Bulk Alloc Preconditions are "
2091                           "not satisfied, Scattered Rx is requested, "
2092                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2093                           "not enabled on port=%d, queue=%d.",
2094                           rxq->port_id, rxq->queue_id);
2095                         ad->rx_bulk_alloc_allowed = false;
2096                 }
2097         }
2098
2099         dev->data->rx_queues[queue_idx] = rxq;
2100         return 0;
2101 }
2102
2103 void
2104 i40e_dev_rx_queue_release(void *rxq)
2105 {
2106         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2107
2108         if (!q) {
2109                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2110                 return;
2111         }
2112
2113         i40e_rx_queue_release_mbufs(q);
2114         rte_free(q->sw_ring);
2115         rte_free(q);
2116 }
2117
2118 uint32_t
2119 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2120 {
2121 #define I40E_RXQ_SCAN_INTERVAL 4
2122         volatile union i40e_rx_desc *rxdp;
2123         struct i40e_rx_queue *rxq;
2124         uint16_t desc = 0;
2125
2126         rxq = dev->data->rx_queues[rx_queue_id];
2127         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2128         while ((desc < rxq->nb_rx_desc) &&
2129                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2130                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2131                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2132                 /**
2133                  * Check the DD bit of a rx descriptor of each 4 in a group,
2134                  * to avoid checking too frequently and downgrading performance
2135                  * too much.
2136                  */
2137                 desc += I40E_RXQ_SCAN_INTERVAL;
2138                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2139                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2140                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2141                                         desc - rxq->nb_rx_desc]);
2142         }
2143
2144         return desc;
2145 }
2146
2147 int
2148 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2149 {
2150         volatile union i40e_rx_desc *rxdp;
2151         struct i40e_rx_queue *rxq = rx_queue;
2152         uint16_t desc;
2153         int ret;
2154
2155         if (unlikely(offset >= rxq->nb_rx_desc)) {
2156                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2157                 return 0;
2158         }
2159
2160         desc = rxq->rx_tail + offset;
2161         if (desc >= rxq->nb_rx_desc)
2162                 desc -= rxq->nb_rx_desc;
2163
2164         rxdp = &(rxq->rx_ring[desc]);
2165
2166         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2167                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2168                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2169
2170         return ret;
2171 }
2172
2173 int
2174 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2175 {
2176         struct i40e_rx_queue *rxq = rx_queue;
2177         volatile uint64_t *status;
2178         uint64_t mask;
2179         uint32_t desc;
2180
2181         if (unlikely(offset >= rxq->nb_rx_desc))
2182                 return -EINVAL;
2183
2184         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2185                 return RTE_ETH_RX_DESC_UNAVAIL;
2186
2187         desc = rxq->rx_tail + offset;
2188         if (desc >= rxq->nb_rx_desc)
2189                 desc -= rxq->nb_rx_desc;
2190
2191         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2192         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2193                 << I40E_RXD_QW1_STATUS_SHIFT);
2194         if (*status & mask)
2195                 return RTE_ETH_RX_DESC_DONE;
2196
2197         return RTE_ETH_RX_DESC_AVAIL;
2198 }
2199
2200 int
2201 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2202 {
2203         struct i40e_tx_queue *txq = tx_queue;
2204         volatile uint64_t *status;
2205         uint64_t mask, expect;
2206         uint32_t desc;
2207
2208         if (unlikely(offset >= txq->nb_tx_desc))
2209                 return -EINVAL;
2210
2211         desc = txq->tx_tail + offset;
2212         /* go to next desc that has the RS bit */
2213         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2214                 txq->tx_rs_thresh;
2215         if (desc >= txq->nb_tx_desc) {
2216                 desc -= txq->nb_tx_desc;
2217                 if (desc >= txq->nb_tx_desc)
2218                         desc -= txq->nb_tx_desc;
2219         }
2220
2221         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2222         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2223         expect = rte_cpu_to_le_64(
2224                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2225         if ((*status & mask) == expect)
2226                 return RTE_ETH_TX_DESC_DONE;
2227
2228         return RTE_ETH_TX_DESC_FULL;
2229 }
2230
2231 static int
2232 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2233                                 struct i40e_tx_queue *txq)
2234 {
2235         struct i40e_adapter *ad =
2236                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2237
2238         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2239                 PMD_DRV_LOG(ERR,
2240                             "Failed to do TX queue initialization");
2241                 return -EINVAL;
2242         }
2243
2244         if (i40e_dev_first_queue(txq->queue_id,
2245                                  dev->data->tx_queues,
2246                                  dev->data->nb_tx_queues)) {
2247                 /**
2248                  * If it is the first queue to setup,
2249                  * set all flags and call
2250                  * i40e_set_tx_function.
2251                  */
2252                 i40e_set_tx_function_flag(dev, txq);
2253                 i40e_set_tx_function(dev);
2254                 return 0;
2255         }
2256
2257         /* check vector conflict */
2258         if (ad->tx_vec_allowed) {
2259                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2260                     i40e_txq_vec_setup(txq)) {
2261                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2262                         return -EINVAL;
2263                 }
2264         }
2265         /* check simple tx conflict */
2266         if (ad->tx_simple_allowed) {
2267                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2268                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2269                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2270                         return -EINVAL;
2271                 }
2272         }
2273
2274         return 0;
2275 }
2276
2277 int
2278 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2279                         uint16_t queue_idx,
2280                         uint16_t nb_desc,
2281                         unsigned int socket_id,
2282                         const struct rte_eth_txconf *tx_conf)
2283 {
2284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285         struct i40e_vsi *vsi;
2286         struct i40e_pf *pf = NULL;
2287         struct i40e_vf *vf = NULL;
2288         struct i40e_tx_queue *txq;
2289         const struct rte_memzone *tz;
2290         uint32_t ring_size;
2291         uint16_t tx_rs_thresh, tx_free_thresh;
2292         uint16_t reg_idx, i, base, bsf, tc_mapping;
2293         int q_offset;
2294         uint64_t offloads;
2295
2296         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2297
2298         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2299                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2300                 vsi = &vf->vsi;
2301                 reg_idx = queue_idx;
2302         } else {
2303                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2304                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2305                 if (!vsi)
2306                         return -EINVAL;
2307                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2308                 if (q_offset < 0)
2309                         return -EINVAL;
2310                 reg_idx = vsi->base_queue + q_offset;
2311         }
2312
2313         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2314             (nb_desc > I40E_MAX_RING_DESC) ||
2315             (nb_desc < I40E_MIN_RING_DESC)) {
2316                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2317                             "invalid", nb_desc);
2318                 return -EINVAL;
2319         }
2320
2321         /**
2322          * The following two parameters control the setting of the RS bit on
2323          * transmit descriptors. TX descriptors will have their RS bit set
2324          * after txq->tx_rs_thresh descriptors have been used. The TX
2325          * descriptor ring will be cleaned after txq->tx_free_thresh
2326          * descriptors are used or if the number of descriptors required to
2327          * transmit a packet is greater than the number of free TX descriptors.
2328          *
2329          * The following constraints must be satisfied:
2330          *  - tx_rs_thresh must be greater than 0.
2331          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2332          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2333          *  - tx_rs_thresh must be a divisor of the ring size.
2334          *  - tx_free_thresh must be greater than 0.
2335          *  - tx_free_thresh must be less than the size of the ring minus 3.
2336          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2337          *
2338          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2339          * race condition, hence the maximum threshold constraints. When set
2340          * to zero use default values.
2341          */
2342         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2343                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2344         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2345         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2346                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2347         if (tx_conf->tx_rs_thresh > 0)
2348                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2349         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2350                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2351                                 "exceed nb_desc. (tx_rs_thresh=%u "
2352                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2353                                 (unsigned int)tx_rs_thresh,
2354                                 (unsigned int)tx_free_thresh,
2355                                 (unsigned int)nb_desc,
2356                                 (int)dev->data->port_id,
2357                                 (int)queue_idx);
2358                 return I40E_ERR_PARAM;
2359         }
2360         if (tx_rs_thresh >= (nb_desc - 2)) {
2361                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2362                              "number of TX descriptors minus 2. "
2363                              "(tx_rs_thresh=%u port=%d queue=%d)",
2364                              (unsigned int)tx_rs_thresh,
2365                              (int)dev->data->port_id,
2366                              (int)queue_idx);
2367                 return I40E_ERR_PARAM;
2368         }
2369         if (tx_free_thresh >= (nb_desc - 3)) {
2370                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2371                              "number of TX descriptors minus 3. "
2372                              "(tx_free_thresh=%u port=%d queue=%d)",
2373                              (unsigned int)tx_free_thresh,
2374                              (int)dev->data->port_id,
2375                              (int)queue_idx);
2376                 return I40E_ERR_PARAM;
2377         }
2378         if (tx_rs_thresh > tx_free_thresh) {
2379                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2380                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2381                              " tx_rs_thresh=%u port=%d queue=%d)",
2382                              (unsigned int)tx_free_thresh,
2383                              (unsigned int)tx_rs_thresh,
2384                              (int)dev->data->port_id,
2385                              (int)queue_idx);
2386                 return I40E_ERR_PARAM;
2387         }
2388         if ((nb_desc % tx_rs_thresh) != 0) {
2389                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2390                              "number of TX descriptors. (tx_rs_thresh=%u"
2391                              " port=%d queue=%d)",
2392                              (unsigned int)tx_rs_thresh,
2393                              (int)dev->data->port_id,
2394                              (int)queue_idx);
2395                 return I40E_ERR_PARAM;
2396         }
2397         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2398                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2399                              "tx_rs_thresh is greater than 1. "
2400                              "(tx_rs_thresh=%u port=%d queue=%d)",
2401                              (unsigned int)tx_rs_thresh,
2402                              (int)dev->data->port_id,
2403                              (int)queue_idx);
2404                 return I40E_ERR_PARAM;
2405         }
2406
2407         /* Free memory if needed. */
2408         if (dev->data->tx_queues[queue_idx]) {
2409                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2410                 dev->data->tx_queues[queue_idx] = NULL;
2411         }
2412
2413         /* Allocate the TX queue data structure. */
2414         txq = rte_zmalloc_socket("i40e tx queue",
2415                                   sizeof(struct i40e_tx_queue),
2416                                   RTE_CACHE_LINE_SIZE,
2417                                   socket_id);
2418         if (!txq) {
2419                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2420                             "tx queue structure");
2421                 return -ENOMEM;
2422         }
2423
2424         /* Allocate TX hardware ring descriptors. */
2425         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2426         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2427         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2428                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2429         if (!tz) {
2430                 i40e_dev_tx_queue_release(txq);
2431                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2432                 return -ENOMEM;
2433         }
2434
2435         txq->nb_tx_desc = nb_desc;
2436         txq->tx_rs_thresh = tx_rs_thresh;
2437         txq->tx_free_thresh = tx_free_thresh;
2438         txq->pthresh = tx_conf->tx_thresh.pthresh;
2439         txq->hthresh = tx_conf->tx_thresh.hthresh;
2440         txq->wthresh = tx_conf->tx_thresh.wthresh;
2441         txq->queue_id = queue_idx;
2442         txq->reg_idx = reg_idx;
2443         txq->port_id = dev->data->port_id;
2444         txq->offloads = offloads;
2445         txq->vsi = vsi;
2446         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2447
2448         txq->tx_ring_phys_addr = tz->iova;
2449         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2450
2451         /* Allocate software ring */
2452         txq->sw_ring =
2453                 rte_zmalloc_socket("i40e tx sw ring",
2454                                    sizeof(struct i40e_tx_entry) * nb_desc,
2455                                    RTE_CACHE_LINE_SIZE,
2456                                    socket_id);
2457         if (!txq->sw_ring) {
2458                 i40e_dev_tx_queue_release(txq);
2459                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2460                 return -ENOMEM;
2461         }
2462
2463         i40e_reset_tx_queue(txq);
2464         txq->q_set = TRUE;
2465
2466         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2467                 if (!(vsi->enabled_tc & (1 << i)))
2468                         continue;
2469                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2470                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2471                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2472                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2473                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2474
2475                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2476                         txq->dcb_tc = i;
2477         }
2478
2479         if (dev->data->dev_started) {
2480                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2481                         i40e_dev_tx_queue_release(txq);
2482                         return -EINVAL;
2483                 }
2484         } else {
2485                 /**
2486                  * Use a simple TX queue without offloads or
2487                  * multi segs if possible
2488                  */
2489                 i40e_set_tx_function_flag(dev, txq);
2490         }
2491         dev->data->tx_queues[queue_idx] = txq;
2492
2493         return 0;
2494 }
2495
2496 void
2497 i40e_dev_tx_queue_release(void *txq)
2498 {
2499         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2500
2501         if (!q) {
2502                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2503                 return;
2504         }
2505
2506         i40e_tx_queue_release_mbufs(q);
2507         rte_free(q->sw_ring);
2508         rte_free(q);
2509 }
2510
2511 const struct rte_memzone *
2512 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2513 {
2514         const struct rte_memzone *mz;
2515
2516         mz = rte_memzone_lookup(name);
2517         if (mz)
2518                 return mz;
2519
2520         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2521                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2522         return mz;
2523 }
2524
2525 void
2526 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2527 {
2528         uint16_t i;
2529
2530         /* SSE Vector driver has a different way of releasing mbufs. */
2531         if (rxq->rx_using_sse) {
2532                 i40e_rx_queue_release_mbufs_vec(rxq);
2533                 return;
2534         }
2535
2536         if (!rxq->sw_ring) {
2537                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2538                 return;
2539         }
2540
2541         for (i = 0; i < rxq->nb_rx_desc; i++) {
2542                 if (rxq->sw_ring[i].mbuf) {
2543                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2544                         rxq->sw_ring[i].mbuf = NULL;
2545                 }
2546         }
2547 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2548         if (rxq->rx_nb_avail == 0)
2549                 return;
2550         for (i = 0; i < rxq->rx_nb_avail; i++) {
2551                 struct rte_mbuf *mbuf;
2552
2553                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2554                 rte_pktmbuf_free_seg(mbuf);
2555         }
2556         rxq->rx_nb_avail = 0;
2557 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2558 }
2559
2560 void
2561 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2562 {
2563         unsigned i;
2564         uint16_t len;
2565
2566         if (!rxq) {
2567                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2568                 return;
2569         }
2570
2571 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2572         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2573                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2574         else
2575 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2576                 len = rxq->nb_rx_desc;
2577
2578         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2579                 ((volatile char *)rxq->rx_ring)[i] = 0;
2580
2581         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2582         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2583                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2584
2585 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2586         rxq->rx_nb_avail = 0;
2587         rxq->rx_next_avail = 0;
2588         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2589 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2590         rxq->rx_tail = 0;
2591         rxq->nb_rx_hold = 0;
2592         rxq->pkt_first_seg = NULL;
2593         rxq->pkt_last_seg = NULL;
2594
2595         rxq->rxrearm_start = 0;
2596         rxq->rxrearm_nb = 0;
2597 }
2598
2599 void
2600 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2601 {
2602         struct rte_eth_dev *dev;
2603         uint16_t i;
2604
2605         if (!txq || !txq->sw_ring) {
2606                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2607                 return;
2608         }
2609
2610         dev = &rte_eth_devices[txq->port_id];
2611
2612         /**
2613          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2614          *  so need to free remains more carefully.
2615          */
2616 #ifdef CC_AVX512_SUPPORT
2617         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2618                 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2619
2620                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2621                 if (txq->tx_tail < i) {
2622                         for (; i < txq->nb_tx_desc; i++) {
2623                                 rte_pktmbuf_free_seg(swr[i].mbuf);
2624                                 swr[i].mbuf = NULL;
2625                         }
2626                         i = 0;
2627                 }
2628                 for (; i < txq->tx_tail; i++) {
2629                         rte_pktmbuf_free_seg(swr[i].mbuf);
2630                         swr[i].mbuf = NULL;
2631                 }
2632                 return;
2633         }
2634 #endif
2635         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2636                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2637                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2638                 if (txq->tx_tail < i) {
2639                         for (; i < txq->nb_tx_desc; i++) {
2640                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2641                                 txq->sw_ring[i].mbuf = NULL;
2642                         }
2643                         i = 0;
2644                 }
2645                 for (; i < txq->tx_tail; i++) {
2646                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2647                         txq->sw_ring[i].mbuf = NULL;
2648                 }
2649         } else {
2650                 for (i = 0; i < txq->nb_tx_desc; i++) {
2651                         if (txq->sw_ring[i].mbuf) {
2652                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2653                                 txq->sw_ring[i].mbuf = NULL;
2654                         }
2655                 }
2656         }
2657 }
2658
2659 static int
2660 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2661                         uint32_t free_cnt)
2662 {
2663         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2664         uint16_t i, tx_last, tx_id;
2665         uint16_t nb_tx_free_last;
2666         uint16_t nb_tx_to_clean;
2667         uint32_t pkt_cnt;
2668
2669         /* Start free mbuf from the next of tx_tail */
2670         tx_last = txq->tx_tail;
2671         tx_id  = swr_ring[tx_last].next_id;
2672
2673         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2674                 return 0;
2675
2676         nb_tx_to_clean = txq->nb_tx_free;
2677         nb_tx_free_last = txq->nb_tx_free;
2678         if (!free_cnt)
2679                 free_cnt = txq->nb_tx_desc;
2680
2681         /* Loop through swr_ring to count the amount of
2682          * freeable mubfs and packets.
2683          */
2684         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2685                 for (i = 0; i < nb_tx_to_clean &&
2686                         pkt_cnt < free_cnt &&
2687                         tx_id != tx_last; i++) {
2688                         if (swr_ring[tx_id].mbuf != NULL) {
2689                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2690                                 swr_ring[tx_id].mbuf = NULL;
2691
2692                                 /*
2693                                  * last segment in the packet,
2694                                  * increment packet count
2695                                  */
2696                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2697                         }
2698
2699                         tx_id = swr_ring[tx_id].next_id;
2700                 }
2701
2702                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2703                         txq->nb_tx_free || tx_id == tx_last)
2704                         break;
2705
2706                 if (pkt_cnt < free_cnt) {
2707                         if (i40e_xmit_cleanup(txq))
2708                                 break;
2709
2710                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2711                         nb_tx_free_last = txq->nb_tx_free;
2712                 }
2713         }
2714
2715         return (int)pkt_cnt;
2716 }
2717
2718 static int
2719 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2720                         uint32_t free_cnt)
2721 {
2722         int i, n, cnt;
2723
2724         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2725                 free_cnt = txq->nb_tx_desc;
2726
2727         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2728
2729         for (i = 0; i < cnt; i += n) {
2730                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2731                         break;
2732
2733                 n = i40e_tx_free_bufs(txq);
2734
2735                 if (n == 0)
2736                         break;
2737         }
2738
2739         return i;
2740 }
2741
2742 static int
2743 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2744                         uint32_t free_cnt __rte_unused)
2745 {
2746         return -ENOTSUP;
2747 }
2748 int
2749 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2750 {
2751         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2752         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2753         struct i40e_adapter *ad =
2754                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2755
2756         if (ad->tx_simple_allowed) {
2757                 if (ad->tx_vec_allowed)
2758                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2759                 else
2760                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2761         } else {
2762                 return i40e_tx_done_cleanup_full(q, free_cnt);
2763         }
2764 }
2765
2766 void
2767 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2768 {
2769         struct i40e_tx_entry *txe;
2770         uint16_t i, prev, size;
2771
2772         if (!txq) {
2773                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2774                 return;
2775         }
2776
2777         txe = txq->sw_ring;
2778         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2779         for (i = 0; i < size; i++)
2780                 ((volatile char *)txq->tx_ring)[i] = 0;
2781
2782         prev = (uint16_t)(txq->nb_tx_desc - 1);
2783         for (i = 0; i < txq->nb_tx_desc; i++) {
2784                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2785
2786                 txd->cmd_type_offset_bsz =
2787                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2788                 txe[i].mbuf =  NULL;
2789                 txe[i].last_id = i;
2790                 txe[prev].next_id = i;
2791                 prev = i;
2792         }
2793
2794         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2795         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2796
2797         txq->tx_tail = 0;
2798         txq->nb_tx_used = 0;
2799
2800         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2801         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2802 }
2803
2804 /* Init the TX queue in hardware */
2805 int
2806 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2807 {
2808         enum i40e_status_code err = I40E_SUCCESS;
2809         struct i40e_vsi *vsi = txq->vsi;
2810         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2811         uint16_t pf_q = txq->reg_idx;
2812         struct i40e_hmc_obj_txq tx_ctx;
2813         uint32_t qtx_ctl;
2814
2815         /* clear the context structure first */
2816         memset(&tx_ctx, 0, sizeof(tx_ctx));
2817         tx_ctx.new_context = 1;
2818         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2819         tx_ctx.qlen = txq->nb_tx_desc;
2820
2821 #ifdef RTE_LIBRTE_IEEE1588
2822         tx_ctx.timesync_ena = 1;
2823 #endif
2824         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2825         if (vsi->type == I40E_VSI_FDIR)
2826                 tx_ctx.fd_ena = TRUE;
2827
2828         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2829         if (err != I40E_SUCCESS) {
2830                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2831                 return err;
2832         }
2833
2834         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2835         if (err != I40E_SUCCESS) {
2836                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2837                 return err;
2838         }
2839
2840         /* Now associate this queue with this PCI function */
2841         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2842         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2843                                         I40E_QTX_CTL_PF_INDX_MASK);
2844         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2845         I40E_WRITE_FLUSH(hw);
2846
2847         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2848
2849         return err;
2850 }
2851
2852 int
2853 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2854 {
2855         struct i40e_rx_entry *rxe = rxq->sw_ring;
2856         uint64_t dma_addr;
2857         uint16_t i;
2858
2859         for (i = 0; i < rxq->nb_rx_desc; i++) {
2860                 volatile union i40e_rx_desc *rxd;
2861                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2862
2863                 if (unlikely(!mbuf)) {
2864                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2865                         return -ENOMEM;
2866                 }
2867
2868                 rte_mbuf_refcnt_set(mbuf, 1);
2869                 mbuf->next = NULL;
2870                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2871                 mbuf->nb_segs = 1;
2872                 mbuf->port = rxq->port_id;
2873
2874                 dma_addr =
2875                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2876
2877                 rxd = &rxq->rx_ring[i];
2878                 rxd->read.pkt_addr = dma_addr;
2879                 rxd->read.hdr_addr = 0;
2880 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2881                 rxd->read.rsvd1 = 0;
2882                 rxd->read.rsvd2 = 0;
2883 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2884
2885                 rxe[i].mbuf = mbuf;
2886         }
2887
2888         return 0;
2889 }
2890
2891 /*
2892  * Calculate the buffer length, and check the jumbo frame
2893  * and maximum packet length.
2894  */
2895 static int
2896 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2897 {
2898         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2899         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2900         struct rte_eth_dev_data *data = pf->dev_data;
2901         uint16_t buf_size;
2902
2903         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2904                 RTE_PKTMBUF_HEADROOM);
2905
2906         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2907                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2908         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2909                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2910                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2911                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2912                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2913                 rxq->hs_mode = i40e_header_split_enabled;
2914                 break;
2915         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2916         default:
2917                 rxq->rx_hdr_len = 0;
2918                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2919                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2920                 rxq->hs_mode = i40e_header_split_none;
2921                 break;
2922         }
2923
2924         rxq->max_pkt_len =
2925                 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2926                         rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2927         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2928                 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
2929                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2930                         PMD_DRV_LOG(ERR, "maximum packet length must "
2931                                     "be larger than %u and smaller than %u,"
2932                                     "as jumbo frame is enabled",
2933                                     (uint32_t)I40E_ETH_MAX_LEN,
2934                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2935                         return I40E_ERR_CONFIG;
2936                 }
2937         } else {
2938                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2939                         rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
2940                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2941                                     "larger than %u and smaller than %u, "
2942                                     "as jumbo frame is disabled",
2943                                     (uint32_t)RTE_ETHER_MIN_LEN,
2944                                     (uint32_t)I40E_ETH_MAX_LEN);
2945                         return I40E_ERR_CONFIG;
2946                 }
2947         }
2948
2949         return 0;
2950 }
2951
2952 /* Init the RX queue in hardware */
2953 int
2954 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2955 {
2956         int err = I40E_SUCCESS;
2957         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2958         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2959         uint16_t pf_q = rxq->reg_idx;
2960         uint16_t buf_size;
2961         struct i40e_hmc_obj_rxq rx_ctx;
2962
2963         err = i40e_rx_queue_config(rxq);
2964         if (err < 0) {
2965                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2966                 return err;
2967         }
2968
2969         /* Clear the context structure first */
2970         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2971         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2972         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2973
2974         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2975         rx_ctx.qlen = rxq->nb_rx_desc;
2976 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2977         rx_ctx.dsize = 1;
2978 #endif
2979         rx_ctx.dtype = rxq->hs_mode;
2980         if (rxq->hs_mode)
2981                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2982         else
2983                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2984         rx_ctx.rxmax = rxq->max_pkt_len;
2985         rx_ctx.tphrdesc_ena = 1;
2986         rx_ctx.tphwdesc_ena = 1;
2987         rx_ctx.tphdata_ena = 1;
2988         rx_ctx.tphhead_ena = 1;
2989         rx_ctx.lrxqthresh = 2;
2990         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2991         rx_ctx.l2tsel = 1;
2992         /* showiv indicates if inner VLAN is stripped inside of tunnel
2993          * packet. When set it to 1, vlan information is stripped from
2994          * the inner header, but the hardware does not put it in the
2995          * descriptor. So set it zero by default.
2996          */
2997         rx_ctx.showiv = 0;
2998         rx_ctx.prefena = 1;
2999
3000         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
3001         if (err != I40E_SUCCESS) {
3002                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
3003                 return err;
3004         }
3005         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
3006         if (err != I40E_SUCCESS) {
3007                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
3008                 return err;
3009         }
3010
3011         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
3012
3013         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
3014                 RTE_PKTMBUF_HEADROOM);
3015
3016         /* Check if scattered RX needs to be used. */
3017         if (rxq->max_pkt_len > buf_size)
3018                 dev_data->scattered_rx = 1;
3019
3020         /* Init the RX tail regieter. */
3021         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3022
3023         return 0;
3024 }
3025
3026 void
3027 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3028 {
3029         uint16_t i;
3030
3031         PMD_INIT_FUNC_TRACE();
3032
3033         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3034                 if (!dev->data->tx_queues[i])
3035                         continue;
3036                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3037                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3038         }
3039
3040         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3041                 if (!dev->data->rx_queues[i])
3042                         continue;
3043                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3044                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3045         }
3046 }
3047
3048 void
3049 i40e_dev_free_queues(struct rte_eth_dev *dev)
3050 {
3051         uint16_t i;
3052
3053         PMD_INIT_FUNC_TRACE();
3054
3055         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3056                 if (!dev->data->rx_queues[i])
3057                         continue;
3058                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3059                 dev->data->rx_queues[i] = NULL;
3060                 rte_eth_dma_zone_free(dev, "rx_ring", i);
3061         }
3062
3063         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3064                 if (!dev->data->tx_queues[i])
3065                         continue;
3066                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3067                 dev->data->tx_queues[i] = NULL;
3068                 rte_eth_dma_zone_free(dev, "tx_ring", i);
3069         }
3070 }
3071
3072 enum i40e_status_code
3073 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3074 {
3075         struct i40e_tx_queue *txq;
3076         const struct rte_memzone *tz = NULL;
3077         struct rte_eth_dev *dev;
3078         uint32_t ring_size;
3079
3080         if (!pf) {
3081                 PMD_DRV_LOG(ERR, "PF is not available");
3082                 return I40E_ERR_BAD_PTR;
3083         }
3084
3085         dev = &rte_eth_devices[pf->dev_data->port_id];
3086
3087         /* Allocate the TX queue data structure. */
3088         txq = rte_zmalloc_socket("i40e fdir tx queue",
3089                                   sizeof(struct i40e_tx_queue),
3090                                   RTE_CACHE_LINE_SIZE,
3091                                   SOCKET_ID_ANY);
3092         if (!txq) {
3093                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3094                                         "tx queue structure.");
3095                 return I40E_ERR_NO_MEMORY;
3096         }
3097
3098         /* Allocate TX hardware ring descriptors. */
3099         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3100         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3101
3102         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3103                                       I40E_FDIR_QUEUE_ID, ring_size,
3104                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3105         if (!tz) {
3106                 i40e_dev_tx_queue_release(txq);
3107                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3108                 return I40E_ERR_NO_MEMORY;
3109         }
3110
3111         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3112         txq->queue_id = I40E_FDIR_QUEUE_ID;
3113         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3114         txq->vsi = pf->fdir.fdir_vsi;
3115
3116         txq->tx_ring_phys_addr = tz->iova;
3117         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3118
3119         /*
3120          * don't need to allocate software ring and reset for the fdir
3121          * program queue just set the queue has been configured.
3122          */
3123         txq->q_set = TRUE;
3124         pf->fdir.txq = txq;
3125         pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3126
3127         return I40E_SUCCESS;
3128 }
3129
3130 enum i40e_status_code
3131 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3132 {
3133         struct i40e_rx_queue *rxq;
3134         const struct rte_memzone *rz = NULL;
3135         uint32_t ring_size;
3136         struct rte_eth_dev *dev;
3137
3138         if (!pf) {
3139                 PMD_DRV_LOG(ERR, "PF is not available");
3140                 return I40E_ERR_BAD_PTR;
3141         }
3142
3143         dev = &rte_eth_devices[pf->dev_data->port_id];
3144
3145         /* Allocate the RX queue data structure. */
3146         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3147                                   sizeof(struct i40e_rx_queue),
3148                                   RTE_CACHE_LINE_SIZE,
3149                                   SOCKET_ID_ANY);
3150         if (!rxq) {
3151                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3152                                         "rx queue structure.");
3153                 return I40E_ERR_NO_MEMORY;
3154         }
3155
3156         /* Allocate RX hardware ring descriptors. */
3157         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3158         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3159
3160         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3161                                       I40E_FDIR_QUEUE_ID, ring_size,
3162                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3163         if (!rz) {
3164                 i40e_dev_rx_queue_release(rxq);
3165                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3166                 return I40E_ERR_NO_MEMORY;
3167         }
3168
3169         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3170         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3171         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3172         rxq->vsi = pf->fdir.fdir_vsi;
3173
3174         rxq->rx_ring_phys_addr = rz->iova;
3175         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3176         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3177
3178         /*
3179          * Don't need to allocate software ring and reset for the fdir
3180          * rx queue, just set the queue has been configured.
3181          */
3182         rxq->q_set = TRUE;
3183         pf->fdir.rxq = rxq;
3184
3185         return I40E_SUCCESS;
3186 }
3187
3188 void
3189 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3190         struct rte_eth_rxq_info *qinfo)
3191 {
3192         struct i40e_rx_queue *rxq;
3193
3194         rxq = dev->data->rx_queues[queue_id];
3195
3196         qinfo->mp = rxq->mp;
3197         qinfo->scattered_rx = dev->data->scattered_rx;
3198         qinfo->nb_desc = rxq->nb_rx_desc;
3199
3200         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3201         qinfo->conf.rx_drop_en = rxq->drop_en;
3202         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3203         qinfo->conf.offloads = rxq->offloads;
3204 }
3205
3206 void
3207 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3208         struct rte_eth_txq_info *qinfo)
3209 {
3210         struct i40e_tx_queue *txq;
3211
3212         txq = dev->data->tx_queues[queue_id];
3213
3214         qinfo->nb_desc = txq->nb_tx_desc;
3215
3216         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3217         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3218         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3219
3220         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3221         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3222         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3223         qinfo->conf.offloads = txq->offloads;
3224 }
3225
3226 static inline bool
3227 get_avx_supported(bool request_avx512)
3228 {
3229 #ifdef RTE_ARCH_X86
3230         if (request_avx512) {
3231                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3232                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3233                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3234 #ifdef CC_AVX512_SUPPORT
3235                         return true;
3236 #else
3237                 PMD_DRV_LOG(NOTICE,
3238                         "AVX512 is not supported in build env");
3239                 return false;
3240 #endif
3241         } else {
3242                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3243                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3244                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3245 #ifdef CC_AVX2_SUPPORT
3246                         return true;
3247 #else
3248                 PMD_DRV_LOG(NOTICE,
3249                         "AVX2 is not supported in build env");
3250                 return false;
3251 #endif
3252         }
3253 #else
3254         RTE_SET_USED(request_avx512);
3255 #endif /* RTE_ARCH_X86 */
3256
3257         return false;
3258 }
3259
3260
3261 void __rte_cold
3262 i40e_set_rx_function(struct rte_eth_dev *dev)
3263 {
3264         struct i40e_adapter *ad =
3265                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3266         uint16_t rx_using_sse, i;
3267         /* In order to allow Vector Rx there are a few configuration
3268          * conditions to be met and Rx Bulk Allocation should be allowed.
3269          */
3270         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3271 #ifdef RTE_ARCH_X86
3272                 ad->rx_use_avx512 = false;
3273                 ad->rx_use_avx2 = false;
3274 #endif
3275                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3276                     !ad->rx_bulk_alloc_allowed) {
3277                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3278                                      " Vector Rx preconditions",
3279                                      dev->data->port_id);
3280
3281                         ad->rx_vec_allowed = false;
3282                 }
3283                 if (ad->rx_vec_allowed) {
3284                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3285                                 struct i40e_rx_queue *rxq =
3286                                         dev->data->rx_queues[i];
3287
3288                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3289                                         ad->rx_vec_allowed = false;
3290                                         break;
3291                                 }
3292                         }
3293 #ifdef RTE_ARCH_X86
3294                         ad->rx_use_avx512 = get_avx_supported(1);
3295
3296                         if (!ad->rx_use_avx512)
3297                                 ad->rx_use_avx2 = get_avx_supported(0);
3298 #endif
3299                 }
3300         }
3301
3302         if (ad->rx_vec_allowed  &&
3303             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3304 #ifdef RTE_ARCH_X86
3305                 if (dev->data->scattered_rx) {
3306                         if (ad->rx_use_avx512) {
3307 #ifdef CC_AVX512_SUPPORT
3308                                 PMD_DRV_LOG(NOTICE,
3309                                         "Using AVX512 Vector Scattered Rx (port %d).",
3310                                         dev->data->port_id);
3311                                 dev->rx_pkt_burst =
3312                                         i40e_recv_scattered_pkts_vec_avx512;
3313 #endif
3314                         } else {
3315                                 PMD_INIT_LOG(DEBUG,
3316                                         "Using %sVector Scattered Rx (port %d).",
3317                                         ad->rx_use_avx2 ? "avx2 " : "",
3318                                         dev->data->port_id);
3319                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3320                                         i40e_recv_scattered_pkts_vec_avx2 :
3321                                         i40e_recv_scattered_pkts_vec;
3322                         }
3323                 } else {
3324                         if (ad->rx_use_avx512) {
3325 #ifdef CC_AVX512_SUPPORT
3326                                 PMD_DRV_LOG(NOTICE,
3327                                         "Using AVX512 Vector Rx (port %d).",
3328                                         dev->data->port_id);
3329                                 dev->rx_pkt_burst =
3330                                         i40e_recv_pkts_vec_avx512;
3331 #endif
3332                         } else {
3333                                 PMD_INIT_LOG(DEBUG,
3334                                         "Using %sVector Rx (port %d).",
3335                                         ad->rx_use_avx2 ? "avx2 " : "",
3336                                         dev->data->port_id);
3337                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3338                                         i40e_recv_pkts_vec_avx2 :
3339                                         i40e_recv_pkts_vec;
3340                         }
3341                 }
3342 #else /* RTE_ARCH_X86 */
3343                 if (dev->data->scattered_rx) {
3344                         PMD_INIT_LOG(DEBUG,
3345                                      "Using Vector Scattered Rx (port %d).",
3346                                      dev->data->port_id);
3347                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3348                 } else {
3349                         PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3350                                      dev->data->port_id);
3351                         dev->rx_pkt_burst = i40e_recv_pkts_vec;
3352                 }
3353 #endif /* RTE_ARCH_X86 */
3354         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3355                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3356                                     "satisfied. Rx Burst Bulk Alloc function "
3357                                     "will be used on port=%d.",
3358                              dev->data->port_id);
3359
3360                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3361         } else {
3362                 /* Simple Rx Path. */
3363                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3364                              dev->data->port_id);
3365                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3366                                         i40e_recv_scattered_pkts :
3367                                         i40e_recv_pkts;
3368         }
3369
3370         /* Propagate information about RX function choice through all queues. */
3371         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3372                 rx_using_sse =
3373                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3374                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3375 #ifdef CC_AVX512_SUPPORT
3376                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3377                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3378 #endif
3379                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3380                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3381
3382                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3383                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3384
3385                         if (rxq)
3386                                 rxq->rx_using_sse = rx_using_sse;
3387                 }
3388         }
3389 }
3390
3391 static const struct {
3392         eth_rx_burst_t pkt_burst;
3393         const char *info;
3394 } i40e_rx_burst_infos[] = {
3395         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3396         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3397         { i40e_recv_pkts,                    "Scalar" },
3398 #ifdef RTE_ARCH_X86
3399 #ifdef CC_AVX512_SUPPORT
3400         { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3401         { i40e_recv_pkts_vec_avx512,           "Vector AVX512" },
3402 #endif
3403         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3404         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3405         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3406         { i40e_recv_pkts_vec,                "Vector SSE" },
3407 #elif defined(RTE_ARCH_ARM64)
3408         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3409         { i40e_recv_pkts_vec,                "Vector Neon" },
3410 #elif defined(RTE_ARCH_PPC_64)
3411         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3412         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3413 #endif
3414 };
3415
3416 int
3417 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3418                        struct rte_eth_burst_mode *mode)
3419 {
3420         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3421         int ret = -EINVAL;
3422         unsigned int i;
3423
3424         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3425                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3426                         snprintf(mode->info, sizeof(mode->info), "%s",
3427                                  i40e_rx_burst_infos[i].info);
3428                         ret = 0;
3429                         break;
3430                 }
3431         }
3432
3433         return ret;
3434 }
3435
3436 void __rte_cold
3437 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3438 {
3439         struct i40e_adapter *ad =
3440                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3441
3442         /* Use a simple Tx queue if possible (only fast free is allowed) */
3443         ad->tx_simple_allowed =
3444                 (txq->offloads ==
3445                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3446                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3447         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3448                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3449
3450         if (ad->tx_vec_allowed)
3451                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3452                                 txq->queue_id);
3453         else if (ad->tx_simple_allowed)
3454                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3455                                 txq->queue_id);
3456         else
3457                 PMD_INIT_LOG(DEBUG,
3458                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3459                                 txq->queue_id);
3460 }
3461
3462 void __rte_cold
3463 i40e_set_tx_function(struct rte_eth_dev *dev)
3464 {
3465         struct i40e_adapter *ad =
3466                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3467         int i;
3468
3469         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3470 #ifdef RTE_ARCH_X86
3471                 ad->tx_use_avx2 = false;
3472                 ad->tx_use_avx512 = false;
3473 #endif
3474                 if (ad->tx_vec_allowed) {
3475                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3476                                 struct i40e_tx_queue *txq =
3477                                         dev->data->tx_queues[i];
3478
3479                                 if (txq && i40e_txq_vec_setup(txq)) {
3480                                         ad->tx_vec_allowed = false;
3481                                         break;
3482                                 }
3483                         }
3484 #ifdef RTE_ARCH_X86
3485                         ad->tx_use_avx512 = get_avx_supported(1);
3486
3487                         if (!ad->tx_use_avx512)
3488                                 ad->tx_use_avx2 = get_avx_supported(0);
3489 #endif
3490                 }
3491         }
3492
3493         if (ad->tx_simple_allowed) {
3494                 if (ad->tx_vec_allowed &&
3495                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3496 #ifdef RTE_ARCH_X86
3497                         if (ad->tx_use_avx512) {
3498 #ifdef CC_AVX512_SUPPORT
3499                                 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3500                                             dev->data->port_id);
3501                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3502 #endif
3503                         } else {
3504                                 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3505                                              ad->tx_use_avx2 ? "avx2 " : "",
3506                                              dev->data->port_id);
3507                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3508                                                     i40e_xmit_pkts_vec_avx2 :
3509                                                     i40e_xmit_pkts_vec;
3510                         }
3511 #else /* RTE_ARCH_X86 */
3512                         PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3513                                      dev->data->port_id);
3514                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3515 #endif /* RTE_ARCH_X86 */
3516                 } else {
3517                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3518                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3519                 }
3520                 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3521         } else {
3522                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3523                 dev->tx_pkt_burst = i40e_xmit_pkts;
3524                 dev->tx_pkt_prepare = i40e_prep_pkts;
3525         }
3526 }
3527
3528 static const struct {
3529         eth_tx_burst_t pkt_burst;
3530         const char *info;
3531 } i40e_tx_burst_infos[] = {
3532         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3533         { i40e_xmit_pkts,          "Scalar" },
3534 #ifdef RTE_ARCH_X86
3535 #ifdef CC_AVX512_SUPPORT
3536         { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3537 #endif
3538         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3539         { i40e_xmit_pkts_vec,      "Vector SSE" },
3540 #elif defined(RTE_ARCH_ARM64)
3541         { i40e_xmit_pkts_vec,      "Vector Neon" },
3542 #elif defined(RTE_ARCH_PPC_64)
3543         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3544 #endif
3545 };
3546
3547 int
3548 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3549                        struct rte_eth_burst_mode *mode)
3550 {
3551         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3552         int ret = -EINVAL;
3553         unsigned int i;
3554
3555         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3556                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3557                         snprintf(mode->info, sizeof(mode->info), "%s",
3558                                  i40e_tx_burst_infos[i].info);
3559                         ret = 0;
3560                         break;
3561                 }
3562         }
3563
3564         return ret;
3565 }
3566
3567 void __rte_cold
3568 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3569 {
3570         struct i40e_adapter *ad =
3571                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3572         int i;
3573
3574         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3575                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3576 }
3577
3578 void __rte_cold
3579 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3580 {
3581         struct i40e_adapter *ad =
3582                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584         int i;
3585
3586         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3587                 ad->pctypes_tbl[i] = 0ULL;
3588         ad->flow_types_mask = 0ULL;
3589         ad->pctypes_mask = 0ULL;
3590
3591         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3592                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3593         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3594                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3595         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3596                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3597         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3598                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3599         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3600                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3601         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3602                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3603         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3604                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3605         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3606                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3607         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3608                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3609         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3610                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3611         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3612                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3613
3614         if (hw->mac.type == I40E_MAC_X722 ||
3615                 hw->mac.type == I40E_MAC_X722_VF) {
3616                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3617                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3618                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3619                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3620                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3621                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3622                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3623                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3624                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3625                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3626                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3627                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3628         }
3629
3630         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3631                 if (ad->pctypes_tbl[i])
3632                         ad->flow_types_mask |= (1ULL << i);
3633                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3634         }
3635 }
3636
3637 #ifndef CC_AVX2_SUPPORT
3638 uint16_t
3639 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3640                         struct rte_mbuf __rte_unused **rx_pkts,
3641                         uint16_t __rte_unused nb_pkts)
3642 {
3643         return 0;
3644 }
3645
3646 uint16_t
3647 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3648                         struct rte_mbuf __rte_unused **rx_pkts,
3649                         uint16_t __rte_unused nb_pkts)
3650 {
3651         return 0;
3652 }
3653
3654 uint16_t
3655 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3656                           struct rte_mbuf __rte_unused **tx_pkts,
3657                           uint16_t __rte_unused nb_pkts)
3658 {
3659         return 0;
3660 }
3661 #endif /* ifndef CC_AVX2_SUPPORT */