1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
28 #include "i40e_logs.h"
29 #include "base/i40e_prototype.h"
30 #include "base/i40e_type.h"
31 #include "i40e_ethdev.h"
32 #include "i40e_rxtx.h"
34 #define DEFAULT_TX_RS_THRESH 32
35 #define DEFAULT_TX_FREE_THRESH 32
37 #define I40E_TX_MAX_BURST 32
39 #define I40E_DMA_MEM_ALIGN 4096
41 /* Base address of the HW descriptor ring should be 128B aligned. */
42 #define I40E_RING_BASE_ALIGN 128
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
49 #define I40E_TX_IEEE1588_TMST 0
52 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
56 PKT_TX_OUTER_IP_CKSUM)
58 #define I40E_TX_OFFLOAD_MASK ( \
65 PKT_TX_OUTER_IP_CKSUM | \
69 PKT_TX_TUNNEL_MASK | \
70 I40E_TX_IEEE1588_TMST)
72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
73 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
76 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
78 struct i40e_rx_queue *rxq = rx_queue;
79 volatile union i40e_rx_desc *rxdp;
83 rxdp = &rxq->rx_ring[desc];
84 /* watch for changes in status bit */
85 pmc->addr = &rxdp->wb.qword1.status_error_len;
88 * we expect the DD bit to be set to 1 if this descriptor was already
91 pmc->val = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
92 pmc->mask = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
94 /* registers are 64-bit */
95 pmc->size = sizeof(uint64_t);
101 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
103 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
104 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
105 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
107 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
108 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
109 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
113 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
114 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
115 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
116 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
117 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
118 mb->vlan_tci_outer = mb->vlan_tci;
119 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
120 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
121 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
122 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
124 mb->vlan_tci_outer = 0;
127 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
128 mb->vlan_tci, mb->vlan_tci_outer);
131 /* Translate the rx descriptor status to pkt flags */
132 static inline uint64_t
133 i40e_rxd_status_to_pkt_flags(uint64_t qword)
137 /* Check if RSS_HASH */
138 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
139 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
140 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
142 /* Check if FDIR Match */
143 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
149 static inline uint64_t
150 i40e_rxd_error_to_pkt_flags(uint64_t qword)
153 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
155 #define I40E_RX_ERR_BITS 0x3f
156 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
157 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
162 flags |= PKT_RX_IP_CKSUM_BAD;
164 flags |= PKT_RX_IP_CKSUM_GOOD;
166 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
167 flags |= PKT_RX_L4_CKSUM_BAD;
169 flags |= PKT_RX_L4_CKSUM_GOOD;
171 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
172 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
177 /* Function to check and set the ieee1588 timesync index and get the
180 #ifdef RTE_LIBRTE_IEEE1588
181 static inline uint64_t
182 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
184 uint64_t pkt_flags = 0;
185 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
186 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
187 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
189 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
190 == RTE_PTYPE_L2_ETHER_TIMESYNC)
191 pkt_flags = PKT_RX_IEEE1588_PTP;
193 pkt_flags |= PKT_RX_IEEE1588_TMST;
194 mb->timesync = tsyn & 0x03;
201 static inline uint64_t
202 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
205 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
206 uint16_t flexbh, flexbl;
208 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
209 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
210 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
211 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
212 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
213 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
216 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
218 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
219 flags |= PKT_RX_FDIR_ID;
220 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
222 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
223 flags |= PKT_RX_FDIR_FLX;
225 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
227 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
228 flags |= PKT_RX_FDIR_FLX;
232 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
233 flags |= PKT_RX_FDIR_ID;
239 i40e_parse_tunneling_params(uint64_t ol_flags,
240 union i40e_tx_offload tx_offload,
241 uint32_t *cd_tunneling)
243 /* EIPT: External (outer) IP header type */
244 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
245 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
246 else if (ol_flags & PKT_TX_OUTER_IPV4)
247 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
248 else if (ol_flags & PKT_TX_OUTER_IPV6)
249 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
251 /* EIPLEN: External (outer) IP header length, in DWords */
252 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
253 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
255 /* L4TUNT: L4 Tunneling Type */
256 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
257 case PKT_TX_TUNNEL_IPIP:
258 /* for non UDP / GRE tunneling, set to 00b */
260 case PKT_TX_TUNNEL_VXLAN:
261 case PKT_TX_TUNNEL_GENEVE:
262 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
264 case PKT_TX_TUNNEL_GRE:
265 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
268 PMD_TX_LOG(ERR, "Tunnel type not supported");
272 /* L4TUNLEN: L4 Tunneling Length, in Words
274 * We depend on app to set rte_mbuf.l2_len correctly.
275 * For IP in GRE it should be set to the length of the GRE
277 * for MAC in GRE or MAC in UDP it should be set to the length
278 * of the GRE or UDP headers plus the inner MAC up to including
279 * its last Ethertype.
281 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
282 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
286 i40e_txd_enable_checksum(uint64_t ol_flags,
289 union i40e_tx_offload tx_offload)
292 if (ol_flags & PKT_TX_TUNNEL_MASK)
293 *td_offset |= (tx_offload.outer_l2_len >> 1)
294 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
296 *td_offset |= (tx_offload.l2_len >> 1)
297 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
299 /* Enable L3 checksum offloads */
300 if (ol_flags & PKT_TX_IP_CKSUM) {
301 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
302 *td_offset |= (tx_offload.l3_len >> 2)
303 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
304 } else if (ol_flags & PKT_TX_IPV4) {
305 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
306 *td_offset |= (tx_offload.l3_len >> 2)
307 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
308 } else if (ol_flags & PKT_TX_IPV6) {
309 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
310 *td_offset |= (tx_offload.l3_len >> 2)
311 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
314 if (ol_flags & PKT_TX_TCP_SEG) {
315 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
316 *td_offset |= (tx_offload.l4_len >> 2)
317 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
321 /* Enable L4 checksum offloads */
322 switch (ol_flags & PKT_TX_L4_MASK) {
323 case PKT_TX_TCP_CKSUM:
324 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
325 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
326 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
328 case PKT_TX_SCTP_CKSUM:
329 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
330 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
331 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
333 case PKT_TX_UDP_CKSUM:
334 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
335 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
336 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
343 /* Construct the tx flags */
344 static inline uint64_t
345 i40e_build_ctob(uint32_t td_cmd,
350 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
351 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
352 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
353 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
354 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
358 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
360 struct i40e_tx_entry *sw_ring = txq->sw_ring;
361 volatile struct i40e_tx_desc *txd = txq->tx_ring;
362 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
363 uint16_t nb_tx_desc = txq->nb_tx_desc;
364 uint16_t desc_to_clean_to;
365 uint16_t nb_tx_to_clean;
367 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
368 if (desc_to_clean_to >= nb_tx_desc)
369 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
371 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
372 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
373 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
374 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
375 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
376 "(port=%d queue=%d)", desc_to_clean_to,
377 txq->port_id, txq->queue_id);
381 if (last_desc_cleaned > desc_to_clean_to)
382 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
385 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
388 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
390 txq->last_desc_cleaned = desc_to_clean_to;
391 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
397 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
398 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
400 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
405 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
406 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
407 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
408 "rxq->rx_free_thresh=%d, "
409 "RTE_PMD_I40E_RX_MAX_BURST=%d",
410 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
412 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
413 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
414 "rxq->rx_free_thresh=%d, "
415 "rxq->nb_rx_desc=%d",
416 rxq->rx_free_thresh, rxq->nb_rx_desc);
418 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
419 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
420 "rxq->nb_rx_desc=%d, "
421 "rxq->rx_free_thresh=%d",
422 rxq->nb_rx_desc, rxq->rx_free_thresh);
432 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
433 #define I40E_LOOK_AHEAD 8
434 #if (I40E_LOOK_AHEAD != 8)
435 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
438 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
440 volatile union i40e_rx_desc *rxdp;
441 struct i40e_rx_entry *rxep;
446 int32_t s[I40E_LOOK_AHEAD], nb_dd;
447 int32_t i, j, nb_rx = 0;
449 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
451 rxdp = &rxq->rx_ring[rxq->rx_tail];
452 rxep = &rxq->sw_ring[rxq->rx_tail];
454 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
455 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
456 I40E_RXD_QW1_STATUS_SHIFT;
458 /* Make sure there is at least 1 packet to receive */
459 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
463 * Scan LOOK_AHEAD descriptors at a time to determine which
464 * descriptors reference packets that are ready to be received.
466 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
467 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
468 /* Read desc statuses backwards to avoid race condition */
469 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
470 qword1 = rte_le_to_cpu_64(\
471 rxdp[j].wb.qword1.status_error_len);
472 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
473 I40E_RXD_QW1_STATUS_SHIFT;
478 /* Compute how many status bits were set */
479 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
480 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
484 /* Translate descriptor info to mbuf parameters */
485 for (j = 0; j < nb_dd; j++) {
487 qword1 = rte_le_to_cpu_64(\
488 rxdp[j].wb.qword1.status_error_len);
489 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
490 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
491 mb->data_len = pkt_len;
492 mb->pkt_len = pkt_len;
494 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
495 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
496 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
498 ptype_tbl[(uint8_t)((qword1 &
499 I40E_RXD_QW1_PTYPE_MASK) >>
500 I40E_RXD_QW1_PTYPE_SHIFT)];
501 if (pkt_flags & PKT_RX_RSS_HASH)
502 mb->hash.rss = rte_le_to_cpu_32(\
503 rxdp[j].wb.qword0.hi_dword.rss);
504 if (pkt_flags & PKT_RX_FDIR)
505 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
507 #ifdef RTE_LIBRTE_IEEE1588
508 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
510 mb->ol_flags |= pkt_flags;
514 for (j = 0; j < I40E_LOOK_AHEAD; j++)
515 rxq->rx_stage[i + j] = rxep[j].mbuf;
517 if (nb_dd != I40E_LOOK_AHEAD)
521 /* Clear software ring entries */
522 for (i = 0; i < nb_rx; i++)
523 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
528 static inline uint16_t
529 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
530 struct rte_mbuf **rx_pkts,
534 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
536 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
538 for (i = 0; i < nb_pkts; i++)
539 rx_pkts[i] = stage[i];
541 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
542 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
548 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
550 volatile union i40e_rx_desc *rxdp;
551 struct i40e_rx_entry *rxep;
553 uint16_t alloc_idx, i;
557 /* Allocate buffers in bulk */
558 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
559 (rxq->rx_free_thresh - 1));
560 rxep = &(rxq->sw_ring[alloc_idx]);
561 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
562 rxq->rx_free_thresh);
563 if (unlikely(diag != 0)) {
564 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
568 rxdp = &rxq->rx_ring[alloc_idx];
569 for (i = 0; i < rxq->rx_free_thresh; i++) {
570 if (likely(i < (rxq->rx_free_thresh - 1)))
571 /* Prefetch next mbuf */
572 rte_prefetch0(rxep[i + 1].mbuf);
575 rte_mbuf_refcnt_set(mb, 1);
577 mb->data_off = RTE_PKTMBUF_HEADROOM;
579 mb->port = rxq->port_id;
580 dma_addr = rte_cpu_to_le_64(\
581 rte_mbuf_data_iova_default(mb));
582 rxdp[i].read.hdr_addr = 0;
583 rxdp[i].read.pkt_addr = dma_addr;
586 /* Update rx tail regsiter */
587 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
589 rxq->rx_free_trigger =
590 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
591 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
592 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
597 static inline uint16_t
598 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
600 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
601 struct rte_eth_dev *dev;
607 if (rxq->rx_nb_avail)
608 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
610 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
611 rxq->rx_next_avail = 0;
612 rxq->rx_nb_avail = nb_rx;
613 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
615 if (rxq->rx_tail > rxq->rx_free_trigger) {
616 if (i40e_rx_alloc_bufs(rxq) != 0) {
619 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
620 dev->data->rx_mbuf_alloc_failed +=
623 rxq->rx_nb_avail = 0;
624 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
625 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
626 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
632 if (rxq->rx_tail >= rxq->nb_rx_desc)
635 if (rxq->rx_nb_avail)
636 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
642 i40e_recv_pkts_bulk_alloc(void *rx_queue,
643 struct rte_mbuf **rx_pkts,
646 uint16_t nb_rx = 0, n, count;
648 if (unlikely(nb_pkts == 0))
651 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
652 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
655 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
656 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
657 nb_rx = (uint16_t)(nb_rx + count);
658 nb_pkts = (uint16_t)(nb_pkts - count);
667 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
668 struct rte_mbuf __rte_unused **rx_pkts,
669 uint16_t __rte_unused nb_pkts)
673 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
676 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
678 struct i40e_rx_queue *rxq;
679 volatile union i40e_rx_desc *rx_ring;
680 volatile union i40e_rx_desc *rxdp;
681 union i40e_rx_desc rxd;
682 struct i40e_rx_entry *sw_ring;
683 struct i40e_rx_entry *rxe;
684 struct rte_eth_dev *dev;
685 struct rte_mbuf *rxm;
686 struct rte_mbuf *nmb;
690 uint16_t rx_packet_len;
691 uint16_t rx_id, nb_hold;
699 rx_id = rxq->rx_tail;
700 rx_ring = rxq->rx_ring;
701 sw_ring = rxq->sw_ring;
702 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
704 while (nb_rx < nb_pkts) {
705 rxdp = &rx_ring[rx_id];
706 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
707 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
708 >> I40E_RXD_QW1_STATUS_SHIFT;
710 /* Check the DD bit first */
711 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
714 nmb = rte_mbuf_raw_alloc(rxq->mp);
715 if (unlikely(!nmb)) {
716 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
717 dev->data->rx_mbuf_alloc_failed++;
723 rxe = &sw_ring[rx_id];
725 if (unlikely(rx_id == rxq->nb_rx_desc))
728 /* Prefetch next mbuf */
729 rte_prefetch0(sw_ring[rx_id].mbuf);
732 * When next RX descriptor is on a cache line boundary,
733 * prefetch the next 4 RX descriptors and next 8 pointers
736 if ((rx_id & 0x3) == 0) {
737 rte_prefetch0(&rx_ring[rx_id]);
738 rte_prefetch0(&sw_ring[rx_id]);
743 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
744 rxdp->read.hdr_addr = 0;
745 rxdp->read.pkt_addr = dma_addr;
747 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
748 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
750 rxm->data_off = RTE_PKTMBUF_HEADROOM;
751 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
754 rxm->pkt_len = rx_packet_len;
755 rxm->data_len = rx_packet_len;
756 rxm->port = rxq->port_id;
758 i40e_rxd_to_vlan_tci(rxm, &rxd);
759 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
760 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
762 ptype_tbl[(uint8_t)((qword1 &
763 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
764 if (pkt_flags & PKT_RX_RSS_HASH)
766 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
767 if (pkt_flags & PKT_RX_FDIR)
768 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
770 #ifdef RTE_LIBRTE_IEEE1588
771 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
773 rxm->ol_flags |= pkt_flags;
775 rx_pkts[nb_rx++] = rxm;
777 rxq->rx_tail = rx_id;
780 * If the number of free RX descriptors is greater than the RX free
781 * threshold of the queue, advance the receive tail register of queue.
782 * Update that register with the value of the last processed RX
783 * descriptor minus 1.
785 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
786 if (nb_hold > rxq->rx_free_thresh) {
787 rx_id = (uint16_t) ((rx_id == 0) ?
788 (rxq->nb_rx_desc - 1) : (rx_id - 1));
789 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
792 rxq->nb_rx_hold = nb_hold;
798 i40e_recv_scattered_pkts(void *rx_queue,
799 struct rte_mbuf **rx_pkts,
802 struct i40e_rx_queue *rxq = rx_queue;
803 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
804 volatile union i40e_rx_desc *rxdp;
805 union i40e_rx_desc rxd;
806 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
807 struct i40e_rx_entry *rxe;
808 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
809 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
810 struct rte_mbuf *nmb, *rxm;
811 uint16_t rx_id = rxq->rx_tail;
812 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
813 struct rte_eth_dev *dev;
818 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
820 while (nb_rx < nb_pkts) {
821 rxdp = &rx_ring[rx_id];
822 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
823 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
824 I40E_RXD_QW1_STATUS_SHIFT;
826 /* Check the DD bit */
827 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
830 nmb = rte_mbuf_raw_alloc(rxq->mp);
831 if (unlikely(!nmb)) {
832 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
833 dev->data->rx_mbuf_alloc_failed++;
839 rxe = &sw_ring[rx_id];
841 if (rx_id == rxq->nb_rx_desc)
844 /* Prefetch next mbuf */
845 rte_prefetch0(sw_ring[rx_id].mbuf);
848 * When next RX descriptor is on a cache line boundary,
849 * prefetch the next 4 RX descriptors and next 8 pointers
852 if ((rx_id & 0x3) == 0) {
853 rte_prefetch0(&rx_ring[rx_id]);
854 rte_prefetch0(&sw_ring[rx_id]);
860 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
862 /* Set data buffer address and data length of the mbuf */
863 rxdp->read.hdr_addr = 0;
864 rxdp->read.pkt_addr = dma_addr;
865 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
866 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
867 rxm->data_len = rx_packet_len;
868 rxm->data_off = RTE_PKTMBUF_HEADROOM;
871 * If this is the first buffer of the received packet, set the
872 * pointer to the first mbuf of the packet and initialize its
873 * context. Otherwise, update the total length and the number
874 * of segments of the current scattered packet, and update the
875 * pointer to the last mbuf of the current packet.
879 first_seg->nb_segs = 1;
880 first_seg->pkt_len = rx_packet_len;
883 (uint16_t)(first_seg->pkt_len +
885 first_seg->nb_segs++;
886 last_seg->next = rxm;
890 * If this is not the last buffer of the received packet,
891 * update the pointer to the last mbuf of the current scattered
892 * packet and continue to parse the RX ring.
894 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
900 * This is the last buffer of the received packet. If the CRC
901 * is not stripped by the hardware:
902 * - Subtract the CRC length from the total packet length.
903 * - If the last buffer only contains the whole CRC or a part
904 * of it, free the mbuf associated to the last buffer. If part
905 * of the CRC is also contained in the previous mbuf, subtract
906 * the length of that CRC part from the data length of the
910 if (unlikely(rxq->crc_len > 0)) {
911 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
912 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
913 rte_pktmbuf_free_seg(rxm);
914 first_seg->nb_segs--;
916 (uint16_t)(last_seg->data_len -
917 (RTE_ETHER_CRC_LEN - rx_packet_len));
918 last_seg->next = NULL;
920 rxm->data_len = (uint16_t)(rx_packet_len -
924 first_seg->port = rxq->port_id;
925 first_seg->ol_flags = 0;
926 i40e_rxd_to_vlan_tci(first_seg, &rxd);
927 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
928 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
929 first_seg->packet_type =
930 ptype_tbl[(uint8_t)((qword1 &
931 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
932 if (pkt_flags & PKT_RX_RSS_HASH)
933 first_seg->hash.rss =
934 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
935 if (pkt_flags & PKT_RX_FDIR)
936 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
938 #ifdef RTE_LIBRTE_IEEE1588
939 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
941 first_seg->ol_flags |= pkt_flags;
943 /* Prefetch data of first segment, if configured to do so. */
944 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
945 first_seg->data_off));
946 rx_pkts[nb_rx++] = first_seg;
950 /* Record index of the next RX descriptor to probe. */
951 rxq->rx_tail = rx_id;
952 rxq->pkt_first_seg = first_seg;
953 rxq->pkt_last_seg = last_seg;
956 * If the number of free RX descriptors is greater than the RX free
957 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
958 * register. Update the RDT with the value of the last processed RX
959 * descriptor minus 1, to guarantee that the RDT register is never
960 * equal to the RDH register, which creates a "full" ring situtation
961 * from the hardware point of view.
963 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
964 if (nb_hold > rxq->rx_free_thresh) {
965 rx_id = (uint16_t)(rx_id == 0 ?
966 (rxq->nb_rx_desc - 1) : (rx_id - 1));
967 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
970 rxq->nb_rx_hold = nb_hold;
975 /* Check if the context descriptor is needed for TX offloading */
976 static inline uint16_t
977 i40e_calc_context_desc(uint64_t flags)
979 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
984 #ifdef RTE_LIBRTE_IEEE1588
985 mask |= PKT_TX_IEEE1588_TMST;
988 return (flags & mask) ? 1 : 0;
991 /* set i40e TSO context descriptor */
992 static inline uint64_t
993 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
995 uint64_t ctx_desc = 0;
996 uint32_t cd_cmd, hdr_len, cd_tso_len;
998 if (!tx_offload.l4_len) {
999 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1003 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1004 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1005 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1007 cd_cmd = I40E_TX_CTX_DESC_TSO;
1008 cd_tso_len = mbuf->pkt_len - hdr_len;
1009 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1010 ((uint64_t)cd_tso_len <<
1011 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1012 ((uint64_t)mbuf->tso_segsz <<
1013 I40E_TXD_CTX_QW1_MSS_SHIFT);
1018 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1019 #define I40E_MAX_DATA_PER_TXD \
1020 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1021 /* Calculate the number of TX descriptors needed for each pkt */
1022 static inline uint16_t
1023 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1025 struct rte_mbuf *txd = tx_pkt;
1028 while (txd != NULL) {
1029 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1037 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1039 struct i40e_tx_queue *txq;
1040 struct i40e_tx_entry *sw_ring;
1041 struct i40e_tx_entry *txe, *txn;
1042 volatile struct i40e_tx_desc *txd;
1043 volatile struct i40e_tx_desc *txr;
1044 struct rte_mbuf *tx_pkt;
1045 struct rte_mbuf *m_seg;
1046 uint32_t cd_tunneling_params;
1057 uint64_t buf_dma_addr;
1058 union i40e_tx_offload tx_offload = {0};
1061 sw_ring = txq->sw_ring;
1063 tx_id = txq->tx_tail;
1064 txe = &sw_ring[tx_id];
1066 /* Check if the descriptor ring needs to be cleaned. */
1067 if (txq->nb_tx_free < txq->tx_free_thresh)
1068 (void)i40e_xmit_cleanup(txq);
1070 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1075 tx_pkt = *tx_pkts++;
1076 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1078 ol_flags = tx_pkt->ol_flags;
1079 tx_offload.l2_len = tx_pkt->l2_len;
1080 tx_offload.l3_len = tx_pkt->l3_len;
1081 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1082 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1083 tx_offload.l4_len = tx_pkt->l4_len;
1084 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1086 /* Calculate the number of context descriptors needed. */
1087 nb_ctx = i40e_calc_context_desc(ol_flags);
1090 * The number of descriptors that must be allocated for
1091 * a packet equals to the number of the segments of that
1092 * packet plus 1 context descriptor if needed.
1093 * Recalculate the needed tx descs when TSO enabled in case
1094 * the mbuf data size exceeds max data size that hw allows
1097 if (ol_flags & PKT_TX_TCP_SEG)
1098 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1101 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1102 tx_last = (uint16_t)(tx_id + nb_used - 1);
1105 if (tx_last >= txq->nb_tx_desc)
1106 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1108 if (nb_used > txq->nb_tx_free) {
1109 if (i40e_xmit_cleanup(txq) != 0) {
1114 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1115 while (nb_used > txq->nb_tx_free) {
1116 if (i40e_xmit_cleanup(txq) != 0) {
1125 /* Descriptor based VLAN insertion */
1126 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1127 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1128 td_tag = tx_pkt->vlan_tci;
1131 /* Always enable CRC offload insertion */
1132 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1134 /* Fill in tunneling parameters if necessary */
1135 cd_tunneling_params = 0;
1136 if (ol_flags & PKT_TX_TUNNEL_MASK)
1137 i40e_parse_tunneling_params(ol_flags, tx_offload,
1138 &cd_tunneling_params);
1139 /* Enable checksum offloading */
1140 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1141 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1142 &td_offset, tx_offload);
1145 /* Setup TX context descriptor if required */
1146 volatile struct i40e_tx_context_desc *ctx_txd =
1147 (volatile struct i40e_tx_context_desc *)\
1149 uint16_t cd_l2tag2 = 0;
1150 uint64_t cd_type_cmd_tso_mss =
1151 I40E_TX_DESC_DTYPE_CONTEXT;
1153 txn = &sw_ring[txe->next_id];
1154 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1155 if (txe->mbuf != NULL) {
1156 rte_pktmbuf_free_seg(txe->mbuf);
1160 /* TSO enabled means no timestamp */
1161 if (ol_flags & PKT_TX_TCP_SEG)
1162 cd_type_cmd_tso_mss |=
1163 i40e_set_tso_ctx(tx_pkt, tx_offload);
1165 #ifdef RTE_LIBRTE_IEEE1588
1166 if (ol_flags & PKT_TX_IEEE1588_TMST)
1167 cd_type_cmd_tso_mss |=
1168 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1169 I40E_TXD_CTX_QW1_CMD_SHIFT);
1173 ctx_txd->tunneling_params =
1174 rte_cpu_to_le_32(cd_tunneling_params);
1175 if (ol_flags & PKT_TX_QINQ_PKT) {
1176 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1177 cd_type_cmd_tso_mss |=
1178 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1179 I40E_TXD_CTX_QW1_CMD_SHIFT);
1181 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1182 ctx_txd->type_cmd_tso_mss =
1183 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1185 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1186 "tunneling_params: %#x;\n"
1189 "type_cmd_tso_mss: %#"PRIx64";\n",
1191 ctx_txd->tunneling_params,
1194 ctx_txd->type_cmd_tso_mss);
1196 txe->last_id = tx_last;
1197 tx_id = txe->next_id;
1204 txn = &sw_ring[txe->next_id];
1207 rte_pktmbuf_free_seg(txe->mbuf);
1210 /* Setup TX Descriptor */
1211 slen = m_seg->data_len;
1212 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1214 while ((ol_flags & PKT_TX_TCP_SEG) &&
1215 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1217 rte_cpu_to_le_64(buf_dma_addr);
1218 txd->cmd_type_offset_bsz =
1219 i40e_build_ctob(td_cmd,
1220 td_offset, I40E_MAX_DATA_PER_TXD,
1223 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1224 slen -= I40E_MAX_DATA_PER_TXD;
1226 txe->last_id = tx_last;
1227 tx_id = txe->next_id;
1230 txn = &sw_ring[txe->next_id];
1232 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1233 "buf_dma_addr: %#"PRIx64";\n"
1238 tx_pkt, tx_id, buf_dma_addr,
1239 td_cmd, td_offset, slen, td_tag);
1241 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1242 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1243 td_offset, slen, td_tag);
1244 txe->last_id = tx_last;
1245 tx_id = txe->next_id;
1247 m_seg = m_seg->next;
1248 } while (m_seg != NULL);
1250 /* The last packet data descriptor needs End Of Packet (EOP) */
1251 td_cmd |= I40E_TX_DESC_CMD_EOP;
1252 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1253 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1255 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1257 "Setting RS bit on TXD id="
1258 "%4u (port=%d queue=%d)",
1259 tx_last, txq->port_id, txq->queue_id);
1261 td_cmd |= I40E_TX_DESC_CMD_RS;
1263 /* Update txq RS bit counters */
1264 txq->nb_tx_used = 0;
1267 txd->cmd_type_offset_bsz |=
1268 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1269 I40E_TXD_QW1_CMD_SHIFT);
1273 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1274 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1275 (unsigned) tx_id, (unsigned) nb_tx);
1278 I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1279 txq->tx_tail = tx_id;
1284 static __rte_always_inline int
1285 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1287 struct i40e_tx_entry *txep;
1290 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1291 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1292 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1295 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1297 for (i = 0; i < txq->tx_rs_thresh; i++)
1298 rte_prefetch0((txep + i)->mbuf);
1300 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1301 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1302 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1306 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1307 rte_pktmbuf_free_seg(txep->mbuf);
1312 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1313 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1314 if (txq->tx_next_dd >= txq->nb_tx_desc)
1315 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1317 return txq->tx_rs_thresh;
1320 /* Populate 4 descriptors with data from 4 mbufs */
1322 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1327 for (i = 0; i < 4; i++, txdp++, pkts++) {
1328 dma_addr = rte_mbuf_data_iova(*pkts);
1329 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1330 txdp->cmd_type_offset_bsz =
1331 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1332 (*pkts)->data_len, 0);
1336 /* Populate 1 descriptor with data from 1 mbuf */
1338 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1342 dma_addr = rte_mbuf_data_iova(*pkts);
1343 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1344 txdp->cmd_type_offset_bsz =
1345 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1346 (*pkts)->data_len, 0);
1349 /* Fill hardware descriptor ring with mbuf data */
1351 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1352 struct rte_mbuf **pkts,
1355 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1356 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1357 const int N_PER_LOOP = 4;
1358 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1359 int mainpart, leftover;
1362 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1363 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1364 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1365 for (j = 0; j < N_PER_LOOP; ++j) {
1366 (txep + i + j)->mbuf = *(pkts + i + j);
1368 tx4(txdp + i, pkts + i);
1370 if (unlikely(leftover > 0)) {
1371 for (i = 0; i < leftover; ++i) {
1372 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1373 tx1(txdp + mainpart + i, pkts + mainpart + i);
1378 static inline uint16_t
1379 tx_xmit_pkts(struct i40e_tx_queue *txq,
1380 struct rte_mbuf **tx_pkts,
1383 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1387 * Begin scanning the H/W ring for done descriptors when the number
1388 * of available descriptors drops below tx_free_thresh. For each done
1389 * descriptor, free the associated buffer.
1391 if (txq->nb_tx_free < txq->tx_free_thresh)
1392 i40e_tx_free_bufs(txq);
1394 /* Use available descriptor only */
1395 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1396 if (unlikely(!nb_pkts))
1399 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1400 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1401 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1402 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1403 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1404 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1405 I40E_TXD_QW1_CMD_SHIFT);
1406 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1410 /* Fill hardware descriptor ring with mbuf data */
1411 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1412 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1414 /* Determin if RS bit needs to be set */
1415 if (txq->tx_tail > txq->tx_next_rs) {
1416 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1417 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1418 I40E_TXD_QW1_CMD_SHIFT);
1420 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1421 if (txq->tx_next_rs >= txq->nb_tx_desc)
1422 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1425 if (txq->tx_tail >= txq->nb_tx_desc)
1428 /* Update the tx tail register */
1429 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1435 i40e_xmit_pkts_simple(void *tx_queue,
1436 struct rte_mbuf **tx_pkts,
1441 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1442 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1446 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1449 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1450 &tx_pkts[nb_tx], num);
1451 nb_tx = (uint16_t)(nb_tx + ret);
1452 nb_pkts = (uint16_t)(nb_pkts - ret);
1461 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1465 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1470 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1471 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1482 /*********************************************************************
1484 * TX simple prep functions
1486 **********************************************************************/
1488 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1495 for (i = 0; i < nb_pkts; i++) {
1497 ol_flags = m->ol_flags;
1499 if (m->nb_segs != 1) {
1504 if (ol_flags & PKT_TX_OFFLOAD_MASK) {
1505 rte_errno = ENOTSUP;
1509 /* check the size of packet */
1510 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1511 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1519 /*********************************************************************
1523 **********************************************************************/
1525 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1532 for (i = 0; i < nb_pkts; i++) {
1534 ol_flags = m->ol_flags;
1536 /* Check for m->nb_segs to not exceed the limits. */
1537 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1538 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1539 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1543 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1544 m->tso_segsz < I40E_MIN_TSO_MSS ||
1545 m->tso_segsz > I40E_MAX_TSO_MSS ||
1546 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1547 /* MSS outside the range (256B - 9674B) are considered
1554 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1555 rte_errno = ENOTSUP;
1559 /* check the size of packet */
1560 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1565 #ifdef RTE_ETHDEV_DEBUG_TX
1566 ret = rte_validate_tx_offload(m);
1572 ret = rte_net_intel_cksum_prepare(m);
1582 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1583 * application used, which assume having sequential ones. But from driver's
1584 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1585 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1586 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1587 * use queue_idx from 0 to 95 to access queues, while real queue would be
1588 * different. This function will do a queue mapping to find VSI the queue
1591 static struct i40e_vsi*
1592 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1594 /* the queue in MAIN VSI range */
1595 if (queue_idx < pf->main_vsi->nb_qps)
1596 return pf->main_vsi;
1598 queue_idx -= pf->main_vsi->nb_qps;
1600 /* queue_idx is greater than VMDQ VSIs range */
1601 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1602 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1606 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1610 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1612 /* the queue in MAIN VSI range */
1613 if (queue_idx < pf->main_vsi->nb_qps)
1616 /* It's VMDQ queues */
1617 queue_idx -= pf->main_vsi->nb_qps;
1619 if (pf->nb_cfg_vmdq_vsi)
1620 return queue_idx % pf->vmdq_nb_qps;
1622 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1623 return (uint16_t)(-1);
1628 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1630 struct i40e_rx_queue *rxq;
1632 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634 PMD_INIT_FUNC_TRACE();
1636 rxq = dev->data->rx_queues[rx_queue_id];
1637 if (!rxq || !rxq->q_set) {
1638 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1643 if (rxq->rx_deferred_start)
1644 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1647 err = i40e_alloc_rx_queue_mbufs(rxq);
1649 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1653 /* Init the RX tail regieter. */
1654 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1656 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1658 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1661 i40e_rx_queue_release_mbufs(rxq);
1662 i40e_reset_rx_queue(rxq);
1665 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1671 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1673 struct i40e_rx_queue *rxq;
1675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677 rxq = dev->data->rx_queues[rx_queue_id];
1678 if (!rxq || !rxq->q_set) {
1679 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1685 * rx_queue_id is queue id application refers to, while
1686 * rxq->reg_idx is the real queue index.
1688 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1690 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1694 i40e_rx_queue_release_mbufs(rxq);
1695 i40e_reset_rx_queue(rxq);
1696 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1702 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1705 struct i40e_tx_queue *txq;
1706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1708 PMD_INIT_FUNC_TRACE();
1710 txq = dev->data->tx_queues[tx_queue_id];
1711 if (!txq || !txq->q_set) {
1712 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1717 if (txq->tx_deferred_start)
1718 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1722 * tx_queue_id is queue id application refers to, while
1723 * rxq->reg_idx is the real queue index.
1725 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1727 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1731 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1737 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1739 struct i40e_tx_queue *txq;
1741 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743 txq = dev->data->tx_queues[tx_queue_id];
1744 if (!txq || !txq->q_set) {
1745 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1751 * tx_queue_id is queue id application refers to, while
1752 * txq->reg_idx is the real queue index.
1754 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1756 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1761 i40e_tx_queue_release_mbufs(txq);
1762 i40e_reset_tx_queue(txq);
1763 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1769 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1771 static const uint32_t ptypes[] = {
1772 /* refers to i40e_rxd_pkt_type_mapping() */
1774 RTE_PTYPE_L2_ETHER_TIMESYNC,
1775 RTE_PTYPE_L2_ETHER_LLDP,
1776 RTE_PTYPE_L2_ETHER_ARP,
1777 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1778 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1781 RTE_PTYPE_L4_NONFRAG,
1785 RTE_PTYPE_TUNNEL_GRENAT,
1786 RTE_PTYPE_TUNNEL_IP,
1787 RTE_PTYPE_INNER_L2_ETHER,
1788 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1789 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1790 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1791 RTE_PTYPE_INNER_L4_FRAG,
1792 RTE_PTYPE_INNER_L4_ICMP,
1793 RTE_PTYPE_INNER_L4_NONFRAG,
1794 RTE_PTYPE_INNER_L4_SCTP,
1795 RTE_PTYPE_INNER_L4_TCP,
1796 RTE_PTYPE_INNER_L4_UDP,
1800 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1801 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1802 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1804 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1805 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1806 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1807 #ifdef CC_AVX512_SUPPORT
1808 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1809 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1811 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1812 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1818 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1822 for (i = 0; i < num; i++) {
1823 if (i != idx && queues[i])
1831 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1832 struct i40e_rx_queue *rxq)
1834 struct i40e_adapter *ad =
1835 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1836 int use_def_burst_func =
1837 check_rx_burst_bulk_alloc_preconditions(rxq);
1839 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1840 RTE_PKTMBUF_HEADROOM);
1841 int use_scattered_rx =
1842 (rxq->max_pkt_len > buf_size);
1844 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1846 "Failed to do RX queue initialization");
1850 if (i40e_dev_first_queue(rxq->queue_id,
1851 dev->data->rx_queues,
1852 dev->data->nb_rx_queues)) {
1854 * If it is the first queue to setup,
1855 * set all flags to default and call
1856 * i40e_set_rx_function.
1858 ad->rx_bulk_alloc_allowed = true;
1859 ad->rx_vec_allowed = true;
1860 dev->data->scattered_rx = use_scattered_rx;
1861 if (use_def_burst_func)
1862 ad->rx_bulk_alloc_allowed = false;
1863 i40e_set_rx_function(dev);
1865 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1866 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1867 " number %d of queue %d isn't power of 2",
1868 rxq->nb_rx_desc, rxq->queue_id);
1872 /* check bulk alloc conflict */
1873 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1874 PMD_DRV_LOG(ERR, "Can't use default burst.");
1877 /* check scatterred conflict */
1878 if (!dev->data->scattered_rx && use_scattered_rx) {
1879 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1882 /* check vector conflict */
1883 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1884 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1892 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1895 unsigned int socket_id,
1896 const struct rte_eth_rxconf *rx_conf,
1897 struct rte_mempool *mp)
1899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900 struct i40e_adapter *ad =
1901 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1902 struct i40e_vsi *vsi;
1903 struct i40e_pf *pf = NULL;
1904 struct i40e_vf *vf = NULL;
1905 struct i40e_rx_queue *rxq;
1906 const struct rte_memzone *rz;
1909 uint16_t reg_idx, base, bsf, tc_mapping;
1910 int q_offset, use_def_burst_func = 1;
1913 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1915 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1916 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1920 reg_idx = queue_idx;
1922 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1926 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1929 reg_idx = vsi->base_queue + q_offset;
1932 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1933 (nb_desc > I40E_MAX_RING_DESC) ||
1934 (nb_desc < I40E_MIN_RING_DESC)) {
1935 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1936 "invalid", nb_desc);
1940 /* Free memory if needed */
1941 if (dev->data->rx_queues[queue_idx]) {
1942 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1943 dev->data->rx_queues[queue_idx] = NULL;
1946 /* Allocate the rx queue data structure */
1947 rxq = rte_zmalloc_socket("i40e rx queue",
1948 sizeof(struct i40e_rx_queue),
1949 RTE_CACHE_LINE_SIZE,
1952 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1953 "rx queue data structure");
1957 rxq->nb_rx_desc = nb_desc;
1958 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1959 rxq->queue_id = queue_idx;
1960 rxq->reg_idx = reg_idx;
1961 rxq->port_id = dev->data->port_id;
1962 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1963 rxq->crc_len = RTE_ETHER_CRC_LEN;
1966 rxq->drop_en = rx_conf->rx_drop_en;
1968 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1969 rxq->offloads = offloads;
1971 /* Allocate the maximun number of RX ring hardware descriptor. */
1972 len = I40E_MAX_RING_DESC;
1975 * Allocating a little more memory because vectorized/bulk_alloc Rx
1976 * functions doesn't check boundaries each time.
1978 len += RTE_PMD_I40E_RX_MAX_BURST;
1980 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1981 I40E_DMA_MEM_ALIGN);
1983 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1984 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1986 i40e_dev_rx_queue_release(rxq);
1987 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1991 /* Zero all the descriptors in the ring. */
1992 memset(rz->addr, 0, ring_size);
1994 rxq->rx_ring_phys_addr = rz->iova;
1995 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1997 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1999 /* Allocate the software ring. */
2001 rte_zmalloc_socket("i40e rx sw ring",
2002 sizeof(struct i40e_rx_entry) * len,
2003 RTE_CACHE_LINE_SIZE,
2005 if (!rxq->sw_ring) {
2006 i40e_dev_rx_queue_release(rxq);
2007 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2011 i40e_reset_rx_queue(rxq);
2014 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2015 if (!(vsi->enabled_tc & (1 << i)))
2017 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2018 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2019 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2020 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2021 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2023 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2027 if (dev->data->dev_started) {
2028 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2029 i40e_dev_rx_queue_release(rxq);
2033 use_def_burst_func =
2034 check_rx_burst_bulk_alloc_preconditions(rxq);
2035 if (!use_def_burst_func) {
2036 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2038 "Rx Burst Bulk Alloc Preconditions are "
2039 "satisfied. Rx Burst Bulk Alloc function will be "
2040 "used on port=%d, queue=%d.",
2041 rxq->port_id, rxq->queue_id);
2042 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2045 "Rx Burst Bulk Alloc Preconditions are "
2046 "not satisfied, Scattered Rx is requested, "
2047 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2048 "not enabled on port=%d, queue=%d.",
2049 rxq->port_id, rxq->queue_id);
2050 ad->rx_bulk_alloc_allowed = false;
2054 dev->data->rx_queues[queue_idx] = rxq;
2059 i40e_dev_rx_queue_release(void *rxq)
2061 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2064 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2068 i40e_rx_queue_release_mbufs(q);
2069 rte_free(q->sw_ring);
2074 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2076 #define I40E_RXQ_SCAN_INTERVAL 4
2077 volatile union i40e_rx_desc *rxdp;
2078 struct i40e_rx_queue *rxq;
2081 rxq = dev->data->rx_queues[rx_queue_id];
2082 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2083 while ((desc < rxq->nb_rx_desc) &&
2084 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2085 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2086 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2088 * Check the DD bit of a rx descriptor of each 4 in a group,
2089 * to avoid checking too frequently and downgrading performance
2092 desc += I40E_RXQ_SCAN_INTERVAL;
2093 rxdp += I40E_RXQ_SCAN_INTERVAL;
2094 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2095 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2096 desc - rxq->nb_rx_desc]);
2103 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2105 volatile union i40e_rx_desc *rxdp;
2106 struct i40e_rx_queue *rxq = rx_queue;
2110 if (unlikely(offset >= rxq->nb_rx_desc)) {
2111 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2115 desc = rxq->rx_tail + offset;
2116 if (desc >= rxq->nb_rx_desc)
2117 desc -= rxq->nb_rx_desc;
2119 rxdp = &(rxq->rx_ring[desc]);
2121 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2122 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2123 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2129 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2131 struct i40e_rx_queue *rxq = rx_queue;
2132 volatile uint64_t *status;
2136 if (unlikely(offset >= rxq->nb_rx_desc))
2139 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2140 return RTE_ETH_RX_DESC_UNAVAIL;
2142 desc = rxq->rx_tail + offset;
2143 if (desc >= rxq->nb_rx_desc)
2144 desc -= rxq->nb_rx_desc;
2146 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2147 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2148 << I40E_RXD_QW1_STATUS_SHIFT);
2150 return RTE_ETH_RX_DESC_DONE;
2152 return RTE_ETH_RX_DESC_AVAIL;
2156 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2158 struct i40e_tx_queue *txq = tx_queue;
2159 volatile uint64_t *status;
2160 uint64_t mask, expect;
2163 if (unlikely(offset >= txq->nb_tx_desc))
2166 desc = txq->tx_tail + offset;
2167 /* go to next desc that has the RS bit */
2168 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2170 if (desc >= txq->nb_tx_desc) {
2171 desc -= txq->nb_tx_desc;
2172 if (desc >= txq->nb_tx_desc)
2173 desc -= txq->nb_tx_desc;
2176 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2177 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2178 expect = rte_cpu_to_le_64(
2179 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2180 if ((*status & mask) == expect)
2181 return RTE_ETH_TX_DESC_DONE;
2183 return RTE_ETH_TX_DESC_FULL;
2187 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2188 struct i40e_tx_queue *txq)
2190 struct i40e_adapter *ad =
2191 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2193 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2195 "Failed to do TX queue initialization");
2199 if (i40e_dev_first_queue(txq->queue_id,
2200 dev->data->tx_queues,
2201 dev->data->nb_tx_queues)) {
2203 * If it is the first queue to setup,
2204 * set all flags and call
2205 * i40e_set_tx_function.
2207 i40e_set_tx_function_flag(dev, txq);
2208 i40e_set_tx_function(dev);
2212 /* check vector conflict */
2213 if (ad->tx_vec_allowed) {
2214 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2215 i40e_txq_vec_setup(txq)) {
2216 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2220 /* check simple tx conflict */
2221 if (ad->tx_simple_allowed) {
2222 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2223 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2224 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2233 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2236 unsigned int socket_id,
2237 const struct rte_eth_txconf *tx_conf)
2239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240 struct i40e_vsi *vsi;
2241 struct i40e_pf *pf = NULL;
2242 struct i40e_vf *vf = NULL;
2243 struct i40e_tx_queue *txq;
2244 const struct rte_memzone *tz;
2246 uint16_t tx_rs_thresh, tx_free_thresh;
2247 uint16_t reg_idx, i, base, bsf, tc_mapping;
2251 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2253 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2254 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2258 reg_idx = queue_idx;
2260 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2264 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2267 reg_idx = vsi->base_queue + q_offset;
2270 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2271 (nb_desc > I40E_MAX_RING_DESC) ||
2272 (nb_desc < I40E_MIN_RING_DESC)) {
2273 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2274 "invalid", nb_desc);
2279 * The following two parameters control the setting of the RS bit on
2280 * transmit descriptors. TX descriptors will have their RS bit set
2281 * after txq->tx_rs_thresh descriptors have been used. The TX
2282 * descriptor ring will be cleaned after txq->tx_free_thresh
2283 * descriptors are used or if the number of descriptors required to
2284 * transmit a packet is greater than the number of free TX descriptors.
2286 * The following constraints must be satisfied:
2287 * - tx_rs_thresh must be greater than 0.
2288 * - tx_rs_thresh must be less than the size of the ring minus 2.
2289 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2290 * - tx_rs_thresh must be a divisor of the ring size.
2291 * - tx_free_thresh must be greater than 0.
2292 * - tx_free_thresh must be less than the size of the ring minus 3.
2293 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2295 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2296 * race condition, hence the maximum threshold constraints. When set
2297 * to zero use default values.
2299 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2300 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2301 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2302 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2303 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2304 if (tx_conf->tx_rs_thresh > 0)
2305 tx_rs_thresh = tx_conf->tx_rs_thresh;
2306 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2307 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2308 "exceed nb_desc. (tx_rs_thresh=%u "
2309 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2310 (unsigned int)tx_rs_thresh,
2311 (unsigned int)tx_free_thresh,
2312 (unsigned int)nb_desc,
2313 (int)dev->data->port_id,
2315 return I40E_ERR_PARAM;
2317 if (tx_rs_thresh >= (nb_desc - 2)) {
2318 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2319 "number of TX descriptors minus 2. "
2320 "(tx_rs_thresh=%u port=%d queue=%d)",
2321 (unsigned int)tx_rs_thresh,
2322 (int)dev->data->port_id,
2324 return I40E_ERR_PARAM;
2326 if (tx_free_thresh >= (nb_desc - 3)) {
2327 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2328 "number of TX descriptors minus 3. "
2329 "(tx_free_thresh=%u port=%d queue=%d)",
2330 (unsigned int)tx_free_thresh,
2331 (int)dev->data->port_id,
2333 return I40E_ERR_PARAM;
2335 if (tx_rs_thresh > tx_free_thresh) {
2336 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2337 "equal to tx_free_thresh. (tx_free_thresh=%u"
2338 " tx_rs_thresh=%u port=%d queue=%d)",
2339 (unsigned int)tx_free_thresh,
2340 (unsigned int)tx_rs_thresh,
2341 (int)dev->data->port_id,
2343 return I40E_ERR_PARAM;
2345 if ((nb_desc % tx_rs_thresh) != 0) {
2346 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2347 "number of TX descriptors. (tx_rs_thresh=%u"
2348 " port=%d queue=%d)",
2349 (unsigned int)tx_rs_thresh,
2350 (int)dev->data->port_id,
2352 return I40E_ERR_PARAM;
2354 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2355 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2356 "tx_rs_thresh is greater than 1. "
2357 "(tx_rs_thresh=%u port=%d queue=%d)",
2358 (unsigned int)tx_rs_thresh,
2359 (int)dev->data->port_id,
2361 return I40E_ERR_PARAM;
2364 /* Free memory if needed. */
2365 if (dev->data->tx_queues[queue_idx]) {
2366 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2367 dev->data->tx_queues[queue_idx] = NULL;
2370 /* Allocate the TX queue data structure. */
2371 txq = rte_zmalloc_socket("i40e tx queue",
2372 sizeof(struct i40e_tx_queue),
2373 RTE_CACHE_LINE_SIZE,
2376 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2377 "tx queue structure");
2381 /* Allocate TX hardware ring descriptors. */
2382 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2383 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2384 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2385 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2387 i40e_dev_tx_queue_release(txq);
2388 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2392 txq->nb_tx_desc = nb_desc;
2393 txq->tx_rs_thresh = tx_rs_thresh;
2394 txq->tx_free_thresh = tx_free_thresh;
2395 txq->pthresh = tx_conf->tx_thresh.pthresh;
2396 txq->hthresh = tx_conf->tx_thresh.hthresh;
2397 txq->wthresh = tx_conf->tx_thresh.wthresh;
2398 txq->queue_id = queue_idx;
2399 txq->reg_idx = reg_idx;
2400 txq->port_id = dev->data->port_id;
2401 txq->offloads = offloads;
2403 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2405 txq->tx_ring_phys_addr = tz->iova;
2406 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2408 /* Allocate software ring */
2410 rte_zmalloc_socket("i40e tx sw ring",
2411 sizeof(struct i40e_tx_entry) * nb_desc,
2412 RTE_CACHE_LINE_SIZE,
2414 if (!txq->sw_ring) {
2415 i40e_dev_tx_queue_release(txq);
2416 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2420 i40e_reset_tx_queue(txq);
2423 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2424 if (!(vsi->enabled_tc & (1 << i)))
2426 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2427 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2428 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2429 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2430 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2432 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2436 if (dev->data->dev_started) {
2437 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2438 i40e_dev_tx_queue_release(txq);
2443 * Use a simple TX queue without offloads or
2444 * multi segs if possible
2446 i40e_set_tx_function_flag(dev, txq);
2448 dev->data->tx_queues[queue_idx] = txq;
2454 i40e_dev_tx_queue_release(void *txq)
2456 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2459 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2463 i40e_tx_queue_release_mbufs(q);
2464 rte_free(q->sw_ring);
2468 const struct rte_memzone *
2469 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2471 const struct rte_memzone *mz;
2473 mz = rte_memzone_lookup(name);
2477 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2478 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2483 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2487 /* SSE Vector driver has a different way of releasing mbufs. */
2488 if (rxq->rx_using_sse) {
2489 i40e_rx_queue_release_mbufs_vec(rxq);
2493 if (!rxq->sw_ring) {
2494 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2498 for (i = 0; i < rxq->nb_rx_desc; i++) {
2499 if (rxq->sw_ring[i].mbuf) {
2500 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2501 rxq->sw_ring[i].mbuf = NULL;
2504 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2505 if (rxq->rx_nb_avail == 0)
2507 for (i = 0; i < rxq->rx_nb_avail; i++) {
2508 struct rte_mbuf *mbuf;
2510 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2511 rte_pktmbuf_free_seg(mbuf);
2513 rxq->rx_nb_avail = 0;
2514 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2518 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2524 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2528 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2529 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2530 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2532 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2533 len = rxq->nb_rx_desc;
2535 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2536 ((volatile char *)rxq->rx_ring)[i] = 0;
2538 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2539 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2540 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2542 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2543 rxq->rx_nb_avail = 0;
2544 rxq->rx_next_avail = 0;
2545 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2546 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2548 rxq->nb_rx_hold = 0;
2549 rxq->pkt_first_seg = NULL;
2550 rxq->pkt_last_seg = NULL;
2552 rxq->rxrearm_start = 0;
2553 rxq->rxrearm_nb = 0;
2557 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2559 struct rte_eth_dev *dev;
2562 if (!txq || !txq->sw_ring) {
2563 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2567 dev = &rte_eth_devices[txq->port_id];
2570 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2571 * so need to free remains more carefully.
2573 #ifdef CC_AVX512_SUPPORT
2574 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2575 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2577 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2578 if (txq->tx_tail < i) {
2579 for (; i < txq->nb_tx_desc; i++) {
2580 rte_pktmbuf_free_seg(swr[i].mbuf);
2585 for (; i < txq->tx_tail; i++) {
2586 rte_pktmbuf_free_seg(swr[i].mbuf);
2592 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2593 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2594 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2595 if (txq->tx_tail < i) {
2596 for (; i < txq->nb_tx_desc; i++) {
2597 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2598 txq->sw_ring[i].mbuf = NULL;
2602 for (; i < txq->tx_tail; i++) {
2603 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2604 txq->sw_ring[i].mbuf = NULL;
2607 for (i = 0; i < txq->nb_tx_desc; i++) {
2608 if (txq->sw_ring[i].mbuf) {
2609 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2610 txq->sw_ring[i].mbuf = NULL;
2617 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2620 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2621 uint16_t i, tx_last, tx_id;
2622 uint16_t nb_tx_free_last;
2623 uint16_t nb_tx_to_clean;
2626 /* Start free mbuf from the next of tx_tail */
2627 tx_last = txq->tx_tail;
2628 tx_id = swr_ring[tx_last].next_id;
2630 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2633 nb_tx_to_clean = txq->nb_tx_free;
2634 nb_tx_free_last = txq->nb_tx_free;
2636 free_cnt = txq->nb_tx_desc;
2638 /* Loop through swr_ring to count the amount of
2639 * freeable mubfs and packets.
2641 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2642 for (i = 0; i < nb_tx_to_clean &&
2643 pkt_cnt < free_cnt &&
2644 tx_id != tx_last; i++) {
2645 if (swr_ring[tx_id].mbuf != NULL) {
2646 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2647 swr_ring[tx_id].mbuf = NULL;
2650 * last segment in the packet,
2651 * increment packet count
2653 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2656 tx_id = swr_ring[tx_id].next_id;
2659 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2660 txq->nb_tx_free || tx_id == tx_last)
2663 if (pkt_cnt < free_cnt) {
2664 if (i40e_xmit_cleanup(txq))
2667 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2668 nb_tx_free_last = txq->nb_tx_free;
2672 return (int)pkt_cnt;
2676 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2681 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2682 free_cnt = txq->nb_tx_desc;
2684 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2686 for (i = 0; i < cnt; i += n) {
2687 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2690 n = i40e_tx_free_bufs(txq);
2700 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2701 uint32_t free_cnt __rte_unused)
2706 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2708 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2709 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2710 struct i40e_adapter *ad =
2711 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2713 if (ad->tx_simple_allowed) {
2714 if (ad->tx_vec_allowed)
2715 return i40e_tx_done_cleanup_vec(q, free_cnt);
2717 return i40e_tx_done_cleanup_simple(q, free_cnt);
2719 return i40e_tx_done_cleanup_full(q, free_cnt);
2724 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2726 struct i40e_tx_entry *txe;
2727 uint16_t i, prev, size;
2730 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2735 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2736 for (i = 0; i < size; i++)
2737 ((volatile char *)txq->tx_ring)[i] = 0;
2739 prev = (uint16_t)(txq->nb_tx_desc - 1);
2740 for (i = 0; i < txq->nb_tx_desc; i++) {
2741 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2743 txd->cmd_type_offset_bsz =
2744 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2747 txe[prev].next_id = i;
2751 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2752 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2755 txq->nb_tx_used = 0;
2757 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2758 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2761 /* Init the TX queue in hardware */
2763 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2765 enum i40e_status_code err = I40E_SUCCESS;
2766 struct i40e_vsi *vsi = txq->vsi;
2767 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2768 uint16_t pf_q = txq->reg_idx;
2769 struct i40e_hmc_obj_txq tx_ctx;
2772 /* clear the context structure first */
2773 memset(&tx_ctx, 0, sizeof(tx_ctx));
2774 tx_ctx.new_context = 1;
2775 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2776 tx_ctx.qlen = txq->nb_tx_desc;
2778 #ifdef RTE_LIBRTE_IEEE1588
2779 tx_ctx.timesync_ena = 1;
2781 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2782 if (vsi->type == I40E_VSI_FDIR)
2783 tx_ctx.fd_ena = TRUE;
2785 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2786 if (err != I40E_SUCCESS) {
2787 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2791 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2792 if (err != I40E_SUCCESS) {
2793 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2797 /* Now associate this queue with this PCI function */
2798 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2799 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2800 I40E_QTX_CTL_PF_INDX_MASK);
2801 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2802 I40E_WRITE_FLUSH(hw);
2804 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2810 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2812 struct i40e_rx_entry *rxe = rxq->sw_ring;
2816 for (i = 0; i < rxq->nb_rx_desc; i++) {
2817 volatile union i40e_rx_desc *rxd;
2818 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2820 if (unlikely(!mbuf)) {
2821 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2825 rte_mbuf_refcnt_set(mbuf, 1);
2827 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2829 mbuf->port = rxq->port_id;
2832 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2834 rxd = &rxq->rx_ring[i];
2835 rxd->read.pkt_addr = dma_addr;
2836 rxd->read.hdr_addr = 0;
2837 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2838 rxd->read.rsvd1 = 0;
2839 rxd->read.rsvd2 = 0;
2840 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2849 * Calculate the buffer length, and check the jumbo frame
2850 * and maximum packet length.
2853 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2855 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2856 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2857 struct rte_eth_dev_data *data = pf->dev_data;
2860 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2861 RTE_PKTMBUF_HEADROOM);
2863 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2864 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2865 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2866 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2867 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2868 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2869 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2870 rxq->hs_mode = i40e_header_split_enabled;
2872 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2874 rxq->rx_hdr_len = 0;
2875 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2876 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2877 rxq->hs_mode = i40e_header_split_none;
2882 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2883 rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2884 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2885 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
2886 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2887 PMD_DRV_LOG(ERR, "maximum packet length must "
2888 "be larger than %u and smaller than %u,"
2889 "as jumbo frame is enabled",
2890 (uint32_t)I40E_ETH_MAX_LEN,
2891 (uint32_t)I40E_FRAME_SIZE_MAX);
2892 return I40E_ERR_CONFIG;
2895 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2896 rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
2897 PMD_DRV_LOG(ERR, "maximum packet length must be "
2898 "larger than %u and smaller than %u, "
2899 "as jumbo frame is disabled",
2900 (uint32_t)RTE_ETHER_MIN_LEN,
2901 (uint32_t)I40E_ETH_MAX_LEN);
2902 return I40E_ERR_CONFIG;
2909 /* Init the RX queue in hardware */
2911 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2913 int err = I40E_SUCCESS;
2914 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2915 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2916 uint16_t pf_q = rxq->reg_idx;
2918 struct i40e_hmc_obj_rxq rx_ctx;
2920 err = i40e_rx_queue_config(rxq);
2922 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2926 /* Clear the context structure first */
2927 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2928 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2929 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2931 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2932 rx_ctx.qlen = rxq->nb_rx_desc;
2933 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2936 rx_ctx.dtype = rxq->hs_mode;
2938 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2940 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2941 rx_ctx.rxmax = rxq->max_pkt_len;
2942 rx_ctx.tphrdesc_ena = 1;
2943 rx_ctx.tphwdesc_ena = 1;
2944 rx_ctx.tphdata_ena = 1;
2945 rx_ctx.tphhead_ena = 1;
2946 rx_ctx.lrxqthresh = 2;
2947 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2949 /* showiv indicates if inner VLAN is stripped inside of tunnel
2950 * packet. When set it to 1, vlan information is stripped from
2951 * the inner header, but the hardware does not put it in the
2952 * descriptor. So set it zero by default.
2957 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2958 if (err != I40E_SUCCESS) {
2959 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2962 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2963 if (err != I40E_SUCCESS) {
2964 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2968 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2970 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2971 RTE_PKTMBUF_HEADROOM);
2973 /* Check if scattered RX needs to be used. */
2974 if (rxq->max_pkt_len > buf_size)
2975 dev_data->scattered_rx = 1;
2977 /* Init the RX tail regieter. */
2978 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2984 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2988 PMD_INIT_FUNC_TRACE();
2990 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2991 if (!dev->data->tx_queues[i])
2993 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2994 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2997 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2998 if (!dev->data->rx_queues[i])
3000 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3001 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3006 i40e_dev_free_queues(struct rte_eth_dev *dev)
3010 PMD_INIT_FUNC_TRACE();
3012 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3013 if (!dev->data->rx_queues[i])
3015 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3016 dev->data->rx_queues[i] = NULL;
3017 rte_eth_dma_zone_free(dev, "rx_ring", i);
3020 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3021 if (!dev->data->tx_queues[i])
3023 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3024 dev->data->tx_queues[i] = NULL;
3025 rte_eth_dma_zone_free(dev, "tx_ring", i);
3029 enum i40e_status_code
3030 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3032 struct i40e_tx_queue *txq;
3033 const struct rte_memzone *tz = NULL;
3034 struct rte_eth_dev *dev;
3038 PMD_DRV_LOG(ERR, "PF is not available");
3039 return I40E_ERR_BAD_PTR;
3042 dev = pf->adapter->eth_dev;
3044 /* Allocate the TX queue data structure. */
3045 txq = rte_zmalloc_socket("i40e fdir tx queue",
3046 sizeof(struct i40e_tx_queue),
3047 RTE_CACHE_LINE_SIZE,
3050 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3051 "tx queue structure.");
3052 return I40E_ERR_NO_MEMORY;
3055 /* Allocate TX hardware ring descriptors. */
3056 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3057 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3059 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3060 I40E_FDIR_QUEUE_ID, ring_size,
3061 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3063 i40e_dev_tx_queue_release(txq);
3064 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3065 return I40E_ERR_NO_MEMORY;
3068 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3069 txq->queue_id = I40E_FDIR_QUEUE_ID;
3070 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3071 txq->vsi = pf->fdir.fdir_vsi;
3073 txq->tx_ring_phys_addr = tz->iova;
3074 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3077 * don't need to allocate software ring and reset for the fdir
3078 * program queue just set the queue has been configured.
3082 pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3084 return I40E_SUCCESS;
3087 enum i40e_status_code
3088 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3090 struct i40e_rx_queue *rxq;
3091 const struct rte_memzone *rz = NULL;
3093 struct rte_eth_dev *dev;
3096 PMD_DRV_LOG(ERR, "PF is not available");
3097 return I40E_ERR_BAD_PTR;
3100 dev = pf->adapter->eth_dev;
3102 /* Allocate the RX queue data structure. */
3103 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3104 sizeof(struct i40e_rx_queue),
3105 RTE_CACHE_LINE_SIZE,
3108 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3109 "rx queue structure.");
3110 return I40E_ERR_NO_MEMORY;
3113 /* Allocate RX hardware ring descriptors. */
3114 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3115 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3117 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3118 I40E_FDIR_QUEUE_ID, ring_size,
3119 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3121 i40e_dev_rx_queue_release(rxq);
3122 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3123 return I40E_ERR_NO_MEMORY;
3126 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3127 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3128 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3129 rxq->vsi = pf->fdir.fdir_vsi;
3131 rxq->rx_ring_phys_addr = rz->iova;
3132 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3133 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3136 * Don't need to allocate software ring and reset for the fdir
3137 * rx queue, just set the queue has been configured.
3142 return I40E_SUCCESS;
3146 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3147 struct rte_eth_rxq_info *qinfo)
3149 struct i40e_rx_queue *rxq;
3151 rxq = dev->data->rx_queues[queue_id];
3153 qinfo->mp = rxq->mp;
3154 qinfo->scattered_rx = dev->data->scattered_rx;
3155 qinfo->nb_desc = rxq->nb_rx_desc;
3157 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3158 qinfo->conf.rx_drop_en = rxq->drop_en;
3159 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3160 qinfo->conf.offloads = rxq->offloads;
3164 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3165 struct rte_eth_txq_info *qinfo)
3167 struct i40e_tx_queue *txq;
3169 txq = dev->data->tx_queues[queue_id];
3171 qinfo->nb_desc = txq->nb_tx_desc;
3173 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3174 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3175 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3177 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3178 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3179 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3180 qinfo->conf.offloads = txq->offloads;
3184 get_avx_supported(bool request_avx512)
3187 if (request_avx512) {
3188 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3189 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3190 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3191 #ifdef CC_AVX512_SUPPORT
3195 "AVX512 is not supported in build env");
3199 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3200 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3201 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3202 #ifdef CC_AVX2_SUPPORT
3206 "AVX2 is not supported in build env");
3211 RTE_SET_USED(request_avx512);
3212 #endif /* RTE_ARCH_X86 */
3219 i40e_set_rx_function(struct rte_eth_dev *dev)
3221 struct i40e_adapter *ad =
3222 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3223 uint16_t rx_using_sse, i;
3224 bool use_avx2 = false;
3225 bool use_avx512 = false;
3226 /* In order to allow Vector Rx there are a few configuration
3227 * conditions to be met and Rx Bulk Allocation should be allowed.
3229 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3230 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3231 !ad->rx_bulk_alloc_allowed) {
3232 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3233 " Vector Rx preconditions",
3234 dev->data->port_id);
3236 ad->rx_vec_allowed = false;
3238 if (ad->rx_vec_allowed) {
3239 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3240 struct i40e_rx_queue *rxq =
3241 dev->data->rx_queues[i];
3243 if (rxq && i40e_rxq_vec_setup(rxq)) {
3244 ad->rx_vec_allowed = false;
3249 use_avx512 = get_avx_supported(1);
3252 use_avx2 = get_avx_supported(0);
3256 if (ad->rx_vec_allowed &&
3257 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3258 if (dev->data->scattered_rx) {
3260 #ifdef CC_AVX512_SUPPORT
3262 "Using AVX512 Vector Scattered Rx (port %d).",
3263 dev->data->port_id);
3265 i40e_recv_scattered_pkts_vec_avx512;
3269 "Using %sVector Scattered Rx (port %d).",
3270 use_avx2 ? "avx2 " : "",
3271 dev->data->port_id);
3272 dev->rx_pkt_burst = use_avx2 ?
3273 i40e_recv_scattered_pkts_vec_avx2 :
3274 i40e_recv_scattered_pkts_vec;
3278 #ifdef CC_AVX512_SUPPORT
3280 "Using AVX512 Vector Rx (port %d).",
3281 dev->data->port_id);
3283 i40e_recv_pkts_vec_avx512;
3287 "Using %sVector Rx (port %d).",
3288 use_avx2 ? "avx2 " : "",
3289 dev->data->port_id);
3290 dev->rx_pkt_burst = use_avx2 ?
3291 i40e_recv_pkts_vec_avx2 :
3295 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3296 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3297 "satisfied. Rx Burst Bulk Alloc function "
3298 "will be used on port=%d.",
3299 dev->data->port_id);
3301 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3303 /* Simple Rx Path. */
3304 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3305 dev->data->port_id);
3306 dev->rx_pkt_burst = dev->data->scattered_rx ?
3307 i40e_recv_scattered_pkts :
3311 /* Propagate information about RX function choice through all queues. */
3312 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3314 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3315 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3316 #ifdef CC_AVX512_SUPPORT
3317 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3318 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3320 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3321 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3323 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3324 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3327 rxq->rx_using_sse = rx_using_sse;
3332 static const struct {
3333 eth_rx_burst_t pkt_burst;
3335 } i40e_rx_burst_infos[] = {
3336 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3337 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3338 { i40e_recv_pkts, "Scalar" },
3340 #ifdef CC_AVX512_SUPPORT
3341 { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3342 { i40e_recv_pkts_vec_avx512, "Vector AVX512" },
3344 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3345 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3346 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3347 { i40e_recv_pkts_vec, "Vector SSE" },
3348 #elif defined(RTE_ARCH_ARM64)
3349 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3350 { i40e_recv_pkts_vec, "Vector Neon" },
3351 #elif defined(RTE_ARCH_PPC_64)
3352 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3353 { i40e_recv_pkts_vec, "Vector AltiVec" },
3358 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3359 struct rte_eth_burst_mode *mode)
3361 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3365 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3366 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3367 snprintf(mode->info, sizeof(mode->info), "%s",
3368 i40e_rx_burst_infos[i].info);
3378 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3380 struct i40e_adapter *ad =
3381 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3383 /* Use a simple Tx queue if possible (only fast free is allowed) */
3384 ad->tx_simple_allowed =
3386 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3387 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3388 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3389 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3391 if (ad->tx_vec_allowed)
3392 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3394 else if (ad->tx_simple_allowed)
3395 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3399 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3404 i40e_set_tx_function(struct rte_eth_dev *dev)
3406 struct i40e_adapter *ad =
3407 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3409 bool use_avx2 = false;
3410 bool use_avx512 = false;
3412 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3413 if (ad->tx_vec_allowed) {
3414 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3415 struct i40e_tx_queue *txq =
3416 dev->data->tx_queues[i];
3418 if (txq && i40e_txq_vec_setup(txq)) {
3419 ad->tx_vec_allowed = false;
3424 use_avx512 = get_avx_supported(1);
3427 use_avx2 = get_avx_supported(0);
3431 if (ad->tx_simple_allowed) {
3432 if (ad->tx_vec_allowed &&
3433 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3435 #ifdef CC_AVX512_SUPPORT
3436 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3437 dev->data->port_id);
3438 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3441 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3442 use_avx2 ? "avx2 " : "",
3443 dev->data->port_id);
3444 dev->tx_pkt_burst = use_avx2 ?
3445 i40e_xmit_pkts_vec_avx2 :
3449 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3450 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3452 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3454 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3455 dev->tx_pkt_burst = i40e_xmit_pkts;
3456 dev->tx_pkt_prepare = i40e_prep_pkts;
3460 static const struct {
3461 eth_tx_burst_t pkt_burst;
3463 } i40e_tx_burst_infos[] = {
3464 { i40e_xmit_pkts_simple, "Scalar Simple" },
3465 { i40e_xmit_pkts, "Scalar" },
3467 #ifdef CC_AVX512_SUPPORT
3468 { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3470 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3471 { i40e_xmit_pkts_vec, "Vector SSE" },
3472 #elif defined(RTE_ARCH_ARM64)
3473 { i40e_xmit_pkts_vec, "Vector Neon" },
3474 #elif defined(RTE_ARCH_PPC_64)
3475 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3480 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3481 struct rte_eth_burst_mode *mode)
3483 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3487 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3488 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3489 snprintf(mode->info, sizeof(mode->info), "%s",
3490 i40e_tx_burst_infos[i].info);
3500 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3502 struct i40e_adapter *ad =
3503 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3506 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3507 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3511 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3513 struct i40e_adapter *ad =
3514 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3519 ad->pctypes_tbl[i] = 0ULL;
3520 ad->flow_types_mask = 0ULL;
3521 ad->pctypes_mask = 0ULL;
3523 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3524 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3525 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3526 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3527 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3528 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3529 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3530 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3531 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3532 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3533 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3534 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3535 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3536 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3537 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3538 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3539 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3540 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3541 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3542 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3543 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3544 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3546 if (hw->mac.type == I40E_MAC_X722 ||
3547 hw->mac.type == I40E_MAC_X722_VF) {
3548 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3549 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3550 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3551 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3552 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3553 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3554 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3555 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3556 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3557 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3558 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3559 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3562 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3563 if (ad->pctypes_tbl[i])
3564 ad->flow_types_mask |= (1ULL << i);
3565 ad->pctypes_mask |= ad->pctypes_tbl[i];
3569 #ifndef CC_AVX2_SUPPORT
3571 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3572 struct rte_mbuf __rte_unused **rx_pkts,
3573 uint16_t __rte_unused nb_pkts)
3579 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3580 struct rte_mbuf __rte_unused **rx_pkts,
3581 uint16_t __rte_unused nb_pkts)
3587 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3588 struct rte_mbuf __rte_unused **tx_pkts,
3589 uint16_t __rte_unused nb_pkts)
3593 #endif /* ifndef CC_AVX2_SUPPORT */