drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_TX_MAX_BURST  32
  68
  69 #define I40E_DMA_MEM_ALIGN 4096
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  82         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  83
  84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  85         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  86
  87 static const struct rte_memzone *
  88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  89                            const char *ring_name,
  90                            uint16_t queue_id,
  91                            uint32_t ring_size,
  92                            int socket_id);
  93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  94                                       struct rte_mbuf **tx_pkts,
  95                                       uint16_t nb_pkts);
  96
  97 static inline void
  98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  99 {
 100         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 101                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_VLAN_PKT;
 103                 mb->vlan_tci =
 104                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 107         } else {
 108                 mb->vlan_tci = 0;
 109         }
 110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 111         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 112                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 113                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 114                 mb->vlan_tci_outer = mb->vlan_tci;
 115                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 116                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 117                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 118                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 119         } else {
 120                 mb->vlan_tci_outer = 0;
 121         }
 122 #endif
 123         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 124                    mb->vlan_tci, mb->vlan_tci_outer);
 125 }
 126
 127 /* Translate the rx descriptor status to pkt flags */
 128 static inline uint64_t
 129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 130 {
 131         uint64_t flags;
 132
 133         /* Check if RSS_HASH */
 134         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 135                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 136                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 137
 138         /* Check if FDIR Match */
 139         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 140                                                         PKT_RX_FDIR : 0);
 141
 142         return flags;
 143 }
 144
 145 static inline uint64_t
 146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 147 {
 148         uint64_t flags = 0;
 149         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 150
 151 #define I40E_RX_ERR_BITS 0x3f
 152         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 153                 return flags;
 154         /* If RXE bit set, all other status bits are meaningless */
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 156                 flags |= PKT_RX_MAC_ERR;
 157                 return flags;
 158         }
 159
 160         /* If RECIPE bit set, all other status indications should be ignored */
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 162                 flags |= PKT_RX_RECIP_ERR;
 163                 return flags;
 164         }
 165         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 166                 flags |= PKT_RX_HBUF_OVERFLOW;
 167         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 168                 flags |= PKT_RX_IP_CKSUM_BAD;
 169         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 170                 flags |= PKT_RX_L4_CKSUM_BAD;
 171         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 172                 flags |= PKT_RX_EIP_CKSUM_BAD;
 173         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 174                 flags |= PKT_RX_OVERSIZE;
 175
 176         return flags;
 177 }
 178
 179 #ifdef RTE_NEXT_ABI
 180 /* For each value it means, datasheet of hardware can tell more details */
 181 static inline uint32_t
 182 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 183 {
 184         static const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {
 185                 /* L2 types */
 186                 /* [0] reserved */
 187                 [1] = RTE_PTYPE_L2_ETHER,
 188                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 189                 /* [3] - [5] reserved */
 190                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 191                 /* [7] - [10] reserved */
 192                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 193                 /* [12] - [21] reserved */
 194
 195                 /* Non tunneled IPv4 */
 196                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 197                         RTE_PTYPE_L4_FRAG,
 198                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 199                         RTE_PTYPE_L4_NONFRAG,
 200                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 201                         RTE_PTYPE_L4_UDP,
 202                 /* [25] reserved */
 203                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                         RTE_PTYPE_L4_TCP,
 205                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 206                         RTE_PTYPE_L4_SCTP,
 207                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                         RTE_PTYPE_L4_ICMP,
 209
 210                 /* IPv4 --> IPv4 */
 211                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 212                         RTE_PTYPE_TUNNEL_IP |
 213                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 214                         RTE_PTYPE_INNER_L4_FRAG,
 215                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 216                         RTE_PTYPE_TUNNEL_IP |
 217                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 218                         RTE_PTYPE_INNER_L4_NONFRAG,
 219                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 220                         RTE_PTYPE_TUNNEL_IP |
 221                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 222                         RTE_PTYPE_INNER_L4_UDP,
 223                 /* [32] reserved */
 224                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                         RTE_PTYPE_TUNNEL_IP |
 226                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_INNER_L4_TCP,
 228                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_TUNNEL_IP |
 230                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_INNER_L4_SCTP,
 232                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_TUNNEL_IP |
 234                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_INNER_L4_ICMP,
 236
 237                 /* IPv4 --> IPv6 */
 238                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 239                         RTE_PTYPE_TUNNEL_IP |
 240                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 241                         RTE_PTYPE_INNER_L4_FRAG,
 242                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 243                         RTE_PTYPE_TUNNEL_IP |
 244                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 245                         RTE_PTYPE_INNER_L4_NONFRAG,
 246                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 247                         RTE_PTYPE_TUNNEL_IP |
 248                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 249                         RTE_PTYPE_INNER_L4_UDP,
 250                 /* [39] reserved */
 251                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                         RTE_PTYPE_TUNNEL_IP |
 253                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 254                         RTE_PTYPE_INNER_L4_TCP,
 255                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 256                         RTE_PTYPE_TUNNEL_IP |
 257                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 258                         RTE_PTYPE_INNER_L4_SCTP,
 259                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 260                         RTE_PTYPE_TUNNEL_IP |
 261                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 262                         RTE_PTYPE_INNER_L4_ICMP,
 263
 264                 /* IPv4 --> GRE/Teredo/VXLAN */
 265                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 266                         RTE_PTYPE_TUNNEL_GRENAT,
 267
 268                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 269                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 270                         RTE_PTYPE_TUNNEL_GRENAT |
 271                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 272                         RTE_PTYPE_INNER_L4_FRAG,
 273                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 274                         RTE_PTYPE_TUNNEL_GRENAT |
 275                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 276                         RTE_PTYPE_INNER_L4_NONFRAG,
 277                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 278                         RTE_PTYPE_TUNNEL_GRENAT |
 279                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 280                         RTE_PTYPE_INNER_L4_UDP,
 281                 /* [47] reserved */
 282                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 283                         RTE_PTYPE_TUNNEL_GRENAT |
 284                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 285                         RTE_PTYPE_INNER_L4_TCP,
 286                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_TUNNEL_GRENAT |
 288                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_INNER_L4_SCTP,
 290                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_TUNNEL_GRENAT |
 292                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_INNER_L4_ICMP,
 294
 295                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 296                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 297                         RTE_PTYPE_TUNNEL_GRENAT |
 298                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 299                         RTE_PTYPE_INNER_L4_FRAG,
 300                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 301                         RTE_PTYPE_TUNNEL_GRENAT |
 302                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 303                         RTE_PTYPE_INNER_L4_NONFRAG,
 304                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 305                         RTE_PTYPE_TUNNEL_GRENAT |
 306                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 307                         RTE_PTYPE_INNER_L4_UDP,
 308                 /* [54] reserved */
 309                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 310                         RTE_PTYPE_TUNNEL_GRENAT |
 311                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 312                         RTE_PTYPE_INNER_L4_TCP,
 313                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 314                         RTE_PTYPE_TUNNEL_GRENAT |
 315                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 316                         RTE_PTYPE_INNER_L4_SCTP,
 317                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 318                         RTE_PTYPE_TUNNEL_GRENAT |
 319                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 320                         RTE_PTYPE_INNER_L4_ICMP,
 321
 322                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 323                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 324                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 325
 326                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 327                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 328                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 329                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 330                         RTE_PTYPE_INNER_L4_FRAG,
 331                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 332                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 333                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 334                         RTE_PTYPE_INNER_L4_NONFRAG,
 335                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 336                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 337                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 338                         RTE_PTYPE_INNER_L4_UDP,
 339                 /* [62] reserved */
 340                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 341                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 342                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 343                         RTE_PTYPE_INNER_L4_TCP,
 344                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 346                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_INNER_L4_SCTP,
 348                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 350                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_INNER_L4_ICMP,
 352
 353                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 354                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 355                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 356                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 357                         RTE_PTYPE_INNER_L4_FRAG,
 358                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 359                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 360                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 361                         RTE_PTYPE_INNER_L4_NONFRAG,
 362                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 363                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 364                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 365                         RTE_PTYPE_INNER_L4_UDP,
 366                 /* [69] reserved */
 367                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 368                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 369                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 370                         RTE_PTYPE_INNER_L4_TCP,
 371                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 372                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 373                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 374                         RTE_PTYPE_INNER_L4_SCTP,
 375                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 376                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 377                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 378                         RTE_PTYPE_INNER_L4_ICMP,
 379
 380                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 381                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 382                         RTE_PTYPE_TUNNEL_GRENAT |
 383                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 384
 385                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 386                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 387                         RTE_PTYPE_TUNNEL_GRENAT |
 388                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 389                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 390                         RTE_PTYPE_INNER_L4_FRAG,
 391                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 392                         RTE_PTYPE_TUNNEL_GRENAT |
 393                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 394                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 395                         RTE_PTYPE_INNER_L4_NONFRAG,
 396                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 397                         RTE_PTYPE_TUNNEL_GRENAT |
 398                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 399                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 400                         RTE_PTYPE_INNER_L4_UDP,
 401                 /* [77] reserved */
 402                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 403                         RTE_PTYPE_TUNNEL_GRENAT |
 404                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 405                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 406                         RTE_PTYPE_INNER_L4_TCP,
 407                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 408                         RTE_PTYPE_TUNNEL_GRENAT |
 409                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 410                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 411                         RTE_PTYPE_INNER_L4_SCTP,
 412                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 413                         RTE_PTYPE_TUNNEL_GRENAT |
 414                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 415                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 416                         RTE_PTYPE_INNER_L4_ICMP,
 417
 418                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 419                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 420                         RTE_PTYPE_TUNNEL_GRENAT |
 421                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 422                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 423                         RTE_PTYPE_INNER_L4_FRAG,
 424                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 425                         RTE_PTYPE_TUNNEL_GRENAT |
 426                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 427                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 428                         RTE_PTYPE_INNER_L4_NONFRAG,
 429                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 430                         RTE_PTYPE_TUNNEL_GRENAT |
 431                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 432                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 433                         RTE_PTYPE_INNER_L4_UDP,
 434                 /* [84] reserved */
 435                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 436                         RTE_PTYPE_TUNNEL_GRENAT |
 437                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 438                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 439                         RTE_PTYPE_INNER_L4_TCP,
 440                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 441                         RTE_PTYPE_TUNNEL_GRENAT |
 442                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 443                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 444                         RTE_PTYPE_INNER_L4_SCTP,
 445                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 446                         RTE_PTYPE_TUNNEL_GRENAT |
 447                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 448                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 449                         RTE_PTYPE_INNER_L4_ICMP,
 450
 451                 /* Non tunneled IPv6 */
 452                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 453                         RTE_PTYPE_L4_FRAG,
 454                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 455                         RTE_PTYPE_L4_NONFRAG,
 456                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 457                         RTE_PTYPE_L4_UDP,
 458                 /* [91] reserved */
 459                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 460                         RTE_PTYPE_L4_TCP,
 461                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 462                         RTE_PTYPE_L4_SCTP,
 463                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 464                         RTE_PTYPE_L4_ICMP,
 465
 466                 /* IPv6 --> IPv4 */
 467                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 468                         RTE_PTYPE_TUNNEL_IP |
 469                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 470                         RTE_PTYPE_INNER_L4_FRAG,
 471                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_TUNNEL_IP |
 473                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 474                         RTE_PTYPE_INNER_L4_NONFRAG,
 475                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 476                         RTE_PTYPE_TUNNEL_IP |
 477                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 478                         RTE_PTYPE_INNER_L4_UDP,
 479                 /* [98] reserved */
 480                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 481                         RTE_PTYPE_TUNNEL_IP |
 482                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 483                         RTE_PTYPE_INNER_L4_TCP,
 484                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 485                         RTE_PTYPE_TUNNEL_IP |
 486                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 487                         RTE_PTYPE_INNER_L4_SCTP,
 488                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 489                         RTE_PTYPE_TUNNEL_IP |
 490                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 491                         RTE_PTYPE_INNER_L4_ICMP,
 492
 493                 /* IPv6 --> IPv6 */
 494                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 495                         RTE_PTYPE_TUNNEL_IP |
 496                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 497                         RTE_PTYPE_INNER_L4_FRAG,
 498                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 499                         RTE_PTYPE_TUNNEL_IP |
 500                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 501                         RTE_PTYPE_INNER_L4_NONFRAG,
 502                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 503                         RTE_PTYPE_TUNNEL_IP |
 504                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 505                         RTE_PTYPE_INNER_L4_UDP,
 506                 /* [105] reserved */
 507                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 508                         RTE_PTYPE_TUNNEL_IP |
 509                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 510                         RTE_PTYPE_INNER_L4_TCP,
 511                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_TUNNEL_IP |
 513                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_INNER_L4_SCTP,
 515                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_TUNNEL_IP |
 517                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_INNER_L4_ICMP,
 519
 520                 /* IPv6 --> GRE/Teredo/VXLAN */
 521                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 522                         RTE_PTYPE_TUNNEL_GRENAT,
 523
 524                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 525                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 526                         RTE_PTYPE_TUNNEL_GRENAT |
 527                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 528                         RTE_PTYPE_INNER_L4_FRAG,
 529                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 530                         RTE_PTYPE_TUNNEL_GRENAT |
 531                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 532                         RTE_PTYPE_INNER_L4_NONFRAG,
 533                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 534                         RTE_PTYPE_TUNNEL_GRENAT |
 535                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 536                         RTE_PTYPE_INNER_L4_UDP,
 537                 /* [113] reserved */
 538                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 539                         RTE_PTYPE_TUNNEL_GRENAT |
 540                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 541                         RTE_PTYPE_INNER_L4_TCP,
 542                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 543                         RTE_PTYPE_TUNNEL_GRENAT |
 544                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 545                         RTE_PTYPE_INNER_L4_SCTP,
 546                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 547                         RTE_PTYPE_TUNNEL_GRENAT |
 548                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 549                         RTE_PTYPE_INNER_L4_ICMP,
 550
 551                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 552                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 553                         RTE_PTYPE_TUNNEL_GRENAT |
 554                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 555                         RTE_PTYPE_INNER_L4_FRAG,
 556                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 557                         RTE_PTYPE_TUNNEL_GRENAT |
 558                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 559                         RTE_PTYPE_INNER_L4_NONFRAG,
 560                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 561                         RTE_PTYPE_TUNNEL_GRENAT |
 562                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 563                         RTE_PTYPE_INNER_L4_UDP,
 564                 /* [120] reserved */
 565                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 566                         RTE_PTYPE_TUNNEL_GRENAT |
 567                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 568                         RTE_PTYPE_INNER_L4_TCP,
 569                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_TUNNEL_GRENAT |
 571                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_INNER_L4_SCTP,
 573                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_TUNNEL_GRENAT |
 575                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_INNER_L4_ICMP,
 577
 578                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 579                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 580                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 581
 582                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 583                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 584                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 585                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 586                         RTE_PTYPE_INNER_L4_FRAG,
 587                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 588                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 589                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 590                         RTE_PTYPE_INNER_L4_NONFRAG,
 591                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 592                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 593                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 594                         RTE_PTYPE_INNER_L4_UDP,
 595                 /* [128] reserved */
 596                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 597                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 598                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 599                         RTE_PTYPE_INNER_L4_TCP,
 600                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 601                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 602                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 603                         RTE_PTYPE_INNER_L4_SCTP,
 604                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 605                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 606                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 607                         RTE_PTYPE_INNER_L4_ICMP,
 608
 609                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 610                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 611                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 612                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 613                         RTE_PTYPE_INNER_L4_FRAG,
 614                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 615                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 616                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 617                         RTE_PTYPE_INNER_L4_NONFRAG,
 618                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 619                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 620                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 621                         RTE_PTYPE_INNER_L4_UDP,
 622                 /* [135] reserved */
 623                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 624                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 625                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 626                         RTE_PTYPE_INNER_L4_TCP,
 627                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 629                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_INNER_L4_SCTP,
 631                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 633                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_INNER_L4_ICMP,
 635
 636                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 637                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 638                         RTE_PTYPE_TUNNEL_GRENAT |
 639                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 640
 641                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 642                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_TUNNEL_GRENAT |
 644                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 645                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 646                         RTE_PTYPE_INNER_L4_FRAG,
 647                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 648                         RTE_PTYPE_TUNNEL_GRENAT |
 649                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 650                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 651                         RTE_PTYPE_INNER_L4_NONFRAG,
 652                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 653                         RTE_PTYPE_TUNNEL_GRENAT |
 654                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 655                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 656                         RTE_PTYPE_INNER_L4_UDP,
 657                 /* [143] reserved */
 658                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 659                         RTE_PTYPE_TUNNEL_GRENAT |
 660                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 661                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 662                         RTE_PTYPE_INNER_L4_TCP,
 663                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 664                         RTE_PTYPE_TUNNEL_GRENAT |
 665                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 666                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 667                         RTE_PTYPE_INNER_L4_SCTP,
 668                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 669                         RTE_PTYPE_TUNNEL_GRENAT |
 670                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 671                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 672                         RTE_PTYPE_INNER_L4_ICMP,
 673
 674                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 675                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 676                         RTE_PTYPE_TUNNEL_GRENAT |
 677                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 678                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 679                         RTE_PTYPE_INNER_L4_FRAG,
 680                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 681                         RTE_PTYPE_TUNNEL_GRENAT |
 682                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 683                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 684                         RTE_PTYPE_INNER_L4_NONFRAG,
 685                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 686                         RTE_PTYPE_TUNNEL_GRENAT |
 687                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 688                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 689                         RTE_PTYPE_INNER_L4_UDP,
 690                 /* [150] reserved */
 691                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 692                         RTE_PTYPE_TUNNEL_GRENAT |
 693                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 695                         RTE_PTYPE_INNER_L4_TCP,
 696                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 697                         RTE_PTYPE_TUNNEL_GRENAT |
 698                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 699                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 700                         RTE_PTYPE_INNER_L4_SCTP,
 701                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 702                         RTE_PTYPE_TUNNEL_GRENAT |
 703                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 704                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 705                         RTE_PTYPE_INNER_L4_ICMP,
 706
 707                 /* All others reserved */
 708         };
 709
 710         return ptype_table[ptype];
 711 }
 712 #else /* RTE_NEXT_ABI */
 713 /* Translate pkt types to pkt flags */
 714 static inline uint64_t
 715 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 716 {
 717         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 718                                         I40E_RXD_QW1_PTYPE_SHIFT);
 719         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 720                 0, /* PTYPE 0 */
 721                 0, /* PTYPE 1 */
 722                 PKT_RX_IEEE1588_PTP, /* PTYPE 2 */
 723                 0, /* PTYPE 3 */
 724                 0, /* PTYPE 4 */
 725                 0, /* PTYPE 5 */
 726                 0, /* PTYPE 6 */
 727                 0, /* PTYPE 7 */
 728                 0, /* PTYPE 8 */
 729                 0, /* PTYPE 9 */
 730                 0, /* PTYPE 10 */
 731                 0, /* PTYPE 11 */
 732                 0, /* PTYPE 12 */
 733                 0, /* PTYPE 13 */
 734                 0, /* PTYPE 14 */
 735                 0, /* PTYPE 15 */
 736                 0, /* PTYPE 16 */
 737                 0, /* PTYPE 17 */
 738                 0, /* PTYPE 18 */
 739                 0, /* PTYPE 19 */
 740                 0, /* PTYPE 20 */
 741                 0, /* PTYPE 21 */
 742                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 743                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 744                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 745                 0, /* PTYPE 25 */
 746                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 747                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 748                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 749                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 750                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 751                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 752                 0, /* PTYPE 32 */
 753                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 754                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 755                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 756                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 757                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 758                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 759                 0, /* PTYPE 39 */
 760                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 761                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 762                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 763                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 764                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 765                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 766                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 767                 0, /* PTYPE 47 */
 768                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 769                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 770                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 771                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 772                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 773                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 774                 0, /* PTYPE 54 */
 775                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 776                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 777                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 778                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 779                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 780                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 781                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 782                 0, /* PTYPE 62 */
 783                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 784                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 785                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 786                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 787                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 788                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 789                 0, /* PTYPE 69 */
 790                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 791                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 792                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 793                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 794                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 795                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 796                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 797                 0, /* PTYPE 77 */
 798                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 799                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 800                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 801                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 802                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 803                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 804                 0, /* PTYPE 84 */
 805                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 806                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 807                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 808                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 809                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 810                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 811                 0, /* PTYPE 91 */
 812                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 813                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 814                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 815                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 816                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 817                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 818                 0, /* PTYPE 98 */
 819                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 820                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 821                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 822                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 823                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 824                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 825                 0, /* PTYPE 105 */
 826                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 827                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 828                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 829                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 830                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 831                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 832                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 833                 0, /* PTYPE 113 */
 834                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 835                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 836                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 837                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 838                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 839                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 840                 0, /* PTYPE 120 */
 841                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 842                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 843                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 844                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 845                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 846                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 847                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 848                 0, /* PTYPE 128 */
 849                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 850                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 851                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 852                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 853                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 854                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 855                 0, /* PTYPE 135 */
 856                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 857                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 858                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 859                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 860                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 861                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 862                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 863                 0, /* PTYPE 143 */
 864                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 865                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 866                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 867                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 868                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 869                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 870                 0, /* PTYPE 150 */
 871                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 872                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 873                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 874                 0, /* PTYPE 154 */
 875                 0, /* PTYPE 155 */
 876                 0, /* PTYPE 156 */
 877                 0, /* PTYPE 157 */
 878                 0, /* PTYPE 158 */
 879                 0, /* PTYPE 159 */
 880                 0, /* PTYPE 160 */
 881                 0, /* PTYPE 161 */
 882                 0, /* PTYPE 162 */
 883                 0, /* PTYPE 163 */
 884                 0, /* PTYPE 164 */
 885                 0, /* PTYPE 165 */
 886                 0, /* PTYPE 166 */
 887                 0, /* PTYPE 167 */
 888                 0, /* PTYPE 168 */
 889                 0, /* PTYPE 169 */
 890                 0, /* PTYPE 170 */
 891                 0, /* PTYPE 171 */
 892                 0, /* PTYPE 172 */
 893                 0, /* PTYPE 173 */
 894                 0, /* PTYPE 174 */
 895                 0, /* PTYPE 175 */
 896                 0, /* PTYPE 176 */
 897                 0, /* PTYPE 177 */
 898                 0, /* PTYPE 178 */
 899                 0, /* PTYPE 179 */
 900                 0, /* PTYPE 180 */
 901                 0, /* PTYPE 181 */
 902                 0, /* PTYPE 182 */
 903                 0, /* PTYPE 183 */
 904                 0, /* PTYPE 184 */
 905                 0, /* PTYPE 185 */
 906                 0, /* PTYPE 186 */
 907                 0, /* PTYPE 187 */
 908                 0, /* PTYPE 188 */
 909                 0, /* PTYPE 189 */
 910                 0, /* PTYPE 190 */
 911                 0, /* PTYPE 191 */
 912                 0, /* PTYPE 192 */
 913                 0, /* PTYPE 193 */
 914                 0, /* PTYPE 194 */
 915                 0, /* PTYPE 195 */
 916                 0, /* PTYPE 196 */
 917                 0, /* PTYPE 197 */
 918                 0, /* PTYPE 198 */
 919                 0, /* PTYPE 199 */
 920                 0, /* PTYPE 200 */
 921                 0, /* PTYPE 201 */
 922                 0, /* PTYPE 202 */
 923                 0, /* PTYPE 203 */
 924                 0, /* PTYPE 204 */
 925                 0, /* PTYPE 205 */
 926                 0, /* PTYPE 206 */
 927                 0, /* PTYPE 207 */
 928                 0, /* PTYPE 208 */
 929                 0, /* PTYPE 209 */
 930                 0, /* PTYPE 210 */
 931                 0, /* PTYPE 211 */
 932                 0, /* PTYPE 212 */
 933                 0, /* PTYPE 213 */
 934                 0, /* PTYPE 214 */
 935                 0, /* PTYPE 215 */
 936                 0, /* PTYPE 216 */
 937                 0, /* PTYPE 217 */
 938                 0, /* PTYPE 218 */
 939                 0, /* PTYPE 219 */
 940                 0, /* PTYPE 220 */
 941                 0, /* PTYPE 221 */
 942                 0, /* PTYPE 222 */
 943                 0, /* PTYPE 223 */
 944                 0, /* PTYPE 224 */
 945                 0, /* PTYPE 225 */
 946                 0, /* PTYPE 226 */
 947                 0, /* PTYPE 227 */
 948                 0, /* PTYPE 228 */
 949                 0, /* PTYPE 229 */
 950                 0, /* PTYPE 230 */
 951                 0, /* PTYPE 231 */
 952                 0, /* PTYPE 232 */
 953                 0, /* PTYPE 233 */
 954                 0, /* PTYPE 234 */
 955                 0, /* PTYPE 235 */
 956                 0, /* PTYPE 236 */
 957                 0, /* PTYPE 237 */
 958                 0, /* PTYPE 238 */
 959                 0, /* PTYPE 239 */
 960                 0, /* PTYPE 240 */
 961                 0, /* PTYPE 241 */
 962                 0, /* PTYPE 242 */
 963                 0, /* PTYPE 243 */
 964                 0, /* PTYPE 244 */
 965                 0, /* PTYPE 245 */
 966                 0, /* PTYPE 246 */
 967                 0, /* PTYPE 247 */
 968                 0, /* PTYPE 248 */
 969                 0, /* PTYPE 249 */
 970                 0, /* PTYPE 250 */
 971                 0, /* PTYPE 251 */
 972                 0, /* PTYPE 252 */
 973                 0, /* PTYPE 253 */
 974                 0, /* PTYPE 254 */
 975                 0, /* PTYPE 255 */
 976         };
 977
 978         return ip_ptype_map[ptype];
 979 }
 980 #endif /* RTE_NEXT_ABI */
 981
 982 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 983 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 984 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 985 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 986 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 987
 988 static inline uint64_t
 989 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 990 {
 991         uint64_t flags = 0;
 992 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 993         uint16_t flexbh, flexbl;
 994
 995         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 996                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 997                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 998         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 999                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
1000                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
1001
1002
1003         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1004                 mb->hash.fdir.hi =
1005                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1006                 flags |= PKT_RX_FDIR_ID;
1007         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
1008                 mb->hash.fdir.hi =
1009                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
1010                 flags |= PKT_RX_FDIR_FLX;
1011         }
1012         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
1013                 mb->hash.fdir.lo =
1014                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
1015                 flags |= PKT_RX_FDIR_FLX;
1016         }
1017 #else
1018         mb->hash.fdir.hi =
1019                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1020         flags |= PKT_RX_FDIR_ID;
1021 #endif
1022         return flags;
1023 }
1024 static inline void
1025 i40e_txd_enable_checksum(uint64_t ol_flags,
1026                         uint32_t *td_cmd,
1027                         uint32_t *td_offset,
1028                         union i40e_tx_offload tx_offload,
1029                         uint32_t *cd_tunneling)
1030 {
1031         /* UDP tunneling packet TX checksum offload */
1032         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1033
1034                 *td_offset |= (tx_offload.outer_l2_len >> 1)
1035                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1036
1037                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1038                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1039                 else if (ol_flags & PKT_TX_OUTER_IPV4)
1040                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1041                 else if (ol_flags & PKT_TX_OUTER_IPV6)
1042                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1043
1044                 /* Now set the ctx descriptor fields */
1045                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
1046                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1047                                 (tx_offload.l2_len >> 1) <<
1048                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1049
1050         } else
1051                 *td_offset |= (tx_offload.l2_len >> 1)
1052                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1053
1054         /* Enable L3 checksum offloads */
1055         if (ol_flags & PKT_TX_IP_CKSUM) {
1056                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1057                 *td_offset |= (tx_offload.l3_len >> 2)
1058                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1059         } else if (ol_flags & PKT_TX_IPV4) {
1060                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1061                 *td_offset |= (tx_offload.l3_len >> 2)
1062                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1063         } else if (ol_flags & PKT_TX_IPV6) {
1064                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1065                 *td_offset |= (tx_offload.l3_len >> 2)
1066                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1067         }
1068
1069         if (ol_flags & PKT_TX_TCP_SEG) {
1070                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1071                 *td_offset |= (tx_offload.l4_len >> 2)
1072                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1073                 return;
1074         }
1075
1076         /* Enable L4 checksum offloads */
1077         switch (ol_flags & PKT_TX_L4_MASK) {
1078         case PKT_TX_TCP_CKSUM:
1079                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1080                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1081                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1082                 break;
1083         case PKT_TX_SCTP_CKSUM:
1084                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1085                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1086                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1087                 break;
1088         case PKT_TX_UDP_CKSUM:
1089                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1090                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1091                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1092                 break;
1093         default:
1094                 break;
1095         }
1096 }
1097
1098 static inline struct rte_mbuf *
1099 rte_rxmbuf_alloc(struct rte_mempool *mp)
1100 {
1101         struct rte_mbuf *m;
1102
1103         m = __rte_mbuf_raw_alloc(mp);
1104         __rte_mbuf_sanity_check_raw(m, 0);
1105
1106         return m;
1107 }
1108
1109 /* Construct the tx flags */
1110 static inline uint64_t
1111 i40e_build_ctob(uint32_t td_cmd,
1112                 uint32_t td_offset,
1113                 unsigned int size,
1114                 uint32_t td_tag)
1115 {
1116         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1117                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
1118                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1119                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1120                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
1121 }
1122
1123 static inline int
1124 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
1125 {
1126         struct i40e_tx_entry *sw_ring = txq->sw_ring;
1127         volatile struct i40e_tx_desc *txd = txq->tx_ring;
1128         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1129         uint16_t nb_tx_desc = txq->nb_tx_desc;
1130         uint16_t desc_to_clean_to;
1131         uint16_t nb_tx_to_clean;
1132
1133         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1134         if (desc_to_clean_to >= nb_tx_desc)
1135                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1136
1137         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1138         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1139                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1140                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
1141                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1142                         "(port=%d queue=%d)", desc_to_clean_to,
1143                                 txq->port_id, txq->queue_id);
1144                 return -1;
1145         }
1146
1147         if (last_desc_cleaned > desc_to_clean_to)
1148                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1149                                                         desc_to_clean_to);
1150         else
1151                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1152                                         last_desc_cleaned);
1153
1154         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1155
1156         txq->last_desc_cleaned = desc_to_clean_to;
1157         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1158
1159         return 0;
1160 }
1161
1162 static inline int
1163 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1164 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
1165 #else
1166 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
1167 #endif
1168 {
1169         int ret = 0;
1170
1171 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1172         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
1173                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1174                              "rxq->rx_free_thresh=%d, "
1175                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
1176                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
1177                 ret = -EINVAL;
1178         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
1179                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1180                              "rxq->rx_free_thresh=%d, "
1181                              "rxq->nb_rx_desc=%d",
1182                              rxq->rx_free_thresh, rxq->nb_rx_desc);
1183                 ret = -EINVAL;
1184         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
1185                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1186                              "rxq->nb_rx_desc=%d, "
1187                              "rxq->rx_free_thresh=%d",
1188                              rxq->nb_rx_desc, rxq->rx_free_thresh);
1189                 ret = -EINVAL;
1190         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
1191                                 RTE_PMD_I40E_RX_MAX_BURST))) {
1192                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1193                              "rxq->nb_rx_desc=%d, "
1194                              "I40E_MAX_RING_DESC=%d, "
1195                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
1196                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
1197                              RTE_PMD_I40E_RX_MAX_BURST);
1198                 ret = -EINVAL;
1199         }
1200 #else
1201         ret = -EINVAL;
1202 #endif
1203
1204         return ret;
1205 }
1206
1207 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1208 #define I40E_LOOK_AHEAD 8
1209 #if (I40E_LOOK_AHEAD != 8)
1210 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
1211 #endif
1212 static inline int
1213 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
1214 {
1215         volatile union i40e_rx_desc *rxdp;
1216         struct i40e_rx_entry *rxep;
1217         struct rte_mbuf *mb;
1218         uint16_t pkt_len;
1219         uint64_t qword1;
1220         uint32_t rx_status;
1221         int32_t s[I40E_LOOK_AHEAD], nb_dd;
1222         int32_t i, j, nb_rx = 0;
1223         uint64_t pkt_flags;
1224
1225         rxdp = &rxq->rx_ring[rxq->rx_tail];
1226         rxep = &rxq->sw_ring[rxq->rx_tail];
1227
1228         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1229         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1230                                 I40E_RXD_QW1_STATUS_SHIFT;
1231
1232         /* Make sure there is at least 1 packet to receive */
1233         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1234                 return 0;
1235
1236         /**
1237          * Scan LOOK_AHEAD descriptors at a time to determine which
1238          * descriptors reference packets that are ready to be received.
1239          */
1240         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
1241                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
1242                 /* Read desc statuses backwards to avoid race condition */
1243                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
1244                         qword1 = rte_le_to_cpu_64(\
1245                                 rxdp[j].wb.qword1.status_error_len);
1246                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1247                                         I40E_RXD_QW1_STATUS_SHIFT;
1248                 }
1249
1250                 /* Compute how many status bits were set */
1251                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1252                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1253
1254                 nb_rx += nb_dd;
1255
1256                 /* Translate descriptor info to mbuf parameters */
1257                 for (j = 0; j < nb_dd; j++) {
1258                         mb = rxep[j].mbuf;
1259                         qword1 = rte_le_to_cpu_64(\
1260                                 rxdp[j].wb.qword1.status_error_len);
1261                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1262                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1263                         mb->data_len = pkt_len;
1264                         mb->pkt_len = pkt_len;
1265                         mb->ol_flags = 0;
1266                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1267                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1268                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1269 #ifdef RTE_NEXT_ABI
1270                         mb->packet_type =
1271                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1272                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1273                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1274 #else
1275                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1276
1277                         mb->packet_type = (uint16_t)((qword1 &
1278                                         I40E_RXD_QW1_PTYPE_MASK) >>
1279                                         I40E_RXD_QW1_PTYPE_SHIFT);
1280 #endif /* RTE_NEXT_ABI */
1281                         if (pkt_flags & PKT_RX_RSS_HASH)
1282                                 mb->hash.rss = rte_le_to_cpu_32(\
1283                                         rxdp[j].wb.qword0.hi_dword.rss);
1284                         if (pkt_flags & PKT_RX_FDIR)
1285                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1286
1287 #ifdef RTE_LIBRTE_IEEE1588
1288                         uint16_t tsyn = (qword1
1289                                          & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1290                                            | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1291                                          >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1292
1293                         if (tsyn & 0x04)
1294                                 pkt_flags |= PKT_RX_IEEE1588_TMST;
1295
1296                         mb->timesync = tsyn & 0x03;
1297 #endif
1298                         mb->ol_flags |= pkt_flags;
1299
1300                 }
1301
1302                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1303                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1304
1305                 if (nb_dd != I40E_LOOK_AHEAD)
1306                         break;
1307         }
1308
1309         /* Clear software ring entries */
1310         for (i = 0; i < nb_rx; i++)
1311                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1312
1313         return nb_rx;
1314 }
1315
1316 static inline uint16_t
1317 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1318                         struct rte_mbuf **rx_pkts,
1319                         uint16_t nb_pkts)
1320 {
1321         uint16_t i;
1322         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1323
1324         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1325
1326         for (i = 0; i < nb_pkts; i++)
1327                 rx_pkts[i] = stage[i];
1328
1329         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1330         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1331
1332         return nb_pkts;
1333 }
1334
1335 static inline int
1336 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1337 {
1338         volatile union i40e_rx_desc *rxdp;
1339         struct i40e_rx_entry *rxep;
1340         struct rte_mbuf *mb;
1341         uint16_t alloc_idx, i;
1342         uint64_t dma_addr;
1343         int diag;
1344
1345         /* Allocate buffers in bulk */
1346         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1347                                 (rxq->rx_free_thresh - 1));
1348         rxep = &(rxq->sw_ring[alloc_idx]);
1349         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1350                                         rxq->rx_free_thresh);
1351         if (unlikely(diag != 0)) {
1352                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1353                 return -ENOMEM;
1354         }
1355
1356         rxdp = &rxq->rx_ring[alloc_idx];
1357         for (i = 0; i < rxq->rx_free_thresh; i++) {
1358                 if (likely(i < (rxq->rx_free_thresh - 1)))
1359                         /* Prefetch next mbuf */
1360                         rte_prefetch0(rxep[i + 1].mbuf);
1361
1362                 mb = rxep[i].mbuf;
1363                 rte_mbuf_refcnt_set(mb, 1);
1364                 mb->next = NULL;
1365                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1366                 mb->nb_segs = 1;
1367                 mb->port = rxq->port_id;
1368                 dma_addr = rte_cpu_to_le_64(\
1369                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1370                 rxdp[i].read.hdr_addr = dma_addr;
1371                 rxdp[i].read.pkt_addr = dma_addr;
1372         }
1373
1374         /* Update rx tail regsiter */
1375         rte_wmb();
1376         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1377
1378         rxq->rx_free_trigger =
1379                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1380         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1381                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1382
1383         return 0;
1384 }
1385
1386 static inline uint16_t
1387 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1388 {
1389         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1390         uint16_t nb_rx = 0;
1391
1392         if (!nb_pkts)
1393                 return 0;
1394
1395         if (rxq->rx_nb_avail)
1396                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1397
1398         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1399         rxq->rx_next_avail = 0;
1400         rxq->rx_nb_avail = nb_rx;
1401         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1402
1403         if (rxq->rx_tail > rxq->rx_free_trigger) {
1404                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1405                         uint16_t i, j;
1406
1407                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1408                                    "port_id=%u, queue_id=%u",
1409                                    rxq->port_id, rxq->queue_id);
1410                         rxq->rx_nb_avail = 0;
1411                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1412                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1413                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1414
1415                         return 0;
1416                 }
1417         }
1418
1419         if (rxq->rx_tail >= rxq->nb_rx_desc)
1420                 rxq->rx_tail = 0;
1421
1422         if (rxq->rx_nb_avail)
1423                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1424
1425         return 0;
1426 }
1427
1428 static uint16_t
1429 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1430                           struct rte_mbuf **rx_pkts,
1431                           uint16_t nb_pkts)
1432 {
1433         uint16_t nb_rx = 0, n, count;
1434
1435         if (unlikely(nb_pkts == 0))
1436                 return 0;
1437
1438         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1439                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1440
1441         while (nb_pkts) {
1442                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1443                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1444                 nb_rx = (uint16_t)(nb_rx + count);
1445                 nb_pkts = (uint16_t)(nb_pkts - count);
1446                 if (count < n)
1447                         break;
1448         }
1449
1450         return nb_rx;
1451 }
1452 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1453
1454 uint16_t
1455 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1456 {
1457         struct i40e_rx_queue *rxq;
1458         volatile union i40e_rx_desc *rx_ring;
1459         volatile union i40e_rx_desc *rxdp;
1460         union i40e_rx_desc rxd;
1461         struct i40e_rx_entry *sw_ring;
1462         struct i40e_rx_entry *rxe;
1463         struct rte_mbuf *rxm;
1464         struct rte_mbuf *nmb;
1465         uint16_t nb_rx;
1466         uint32_t rx_status;
1467         uint64_t qword1;
1468         uint16_t rx_packet_len;
1469         uint16_t rx_id, nb_hold;
1470         uint64_t dma_addr;
1471         uint64_t pkt_flags;
1472
1473         nb_rx = 0;
1474         nb_hold = 0;
1475         rxq = rx_queue;
1476         rx_id = rxq->rx_tail;
1477         rx_ring = rxq->rx_ring;
1478         sw_ring = rxq->sw_ring;
1479
1480         while (nb_rx < nb_pkts) {
1481                 rxdp = &rx_ring[rx_id];
1482                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1483                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1484                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1485
1486                 /* Check the DD bit first */
1487                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1488                         break;
1489
1490                 nmb = rte_rxmbuf_alloc(rxq->mp);
1491                 if (unlikely(!nmb))
1492                         break;
1493                 rxd = *rxdp;
1494
1495                 nb_hold++;
1496                 rxe = &sw_ring[rx_id];
1497                 rx_id++;
1498                 if (unlikely(rx_id == rxq->nb_rx_desc))
1499                         rx_id = 0;
1500
1501                 /* Prefetch next mbuf */
1502                 rte_prefetch0(sw_ring[rx_id].mbuf);
1503
1504                 /**
1505                  * When next RX descriptor is on a cache line boundary,
1506                  * prefetch the next 4 RX descriptors and next 8 pointers
1507                  * to mbufs.
1508                  */
1509                 if ((rx_id & 0x3) == 0) {
1510                         rte_prefetch0(&rx_ring[rx_id]);
1511                         rte_prefetch0(&sw_ring[rx_id]);
1512                 }
1513                 rxm = rxe->mbuf;
1514                 rxe->mbuf = nmb;
1515                 dma_addr =
1516                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1517                 rxdp->read.hdr_addr = dma_addr;
1518                 rxdp->read.pkt_addr = dma_addr;
1519
1520                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1521                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1522
1523                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1524                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1525                 rxm->nb_segs = 1;
1526                 rxm->next = NULL;
1527                 rxm->pkt_len = rx_packet_len;
1528                 rxm->data_len = rx_packet_len;
1529                 rxm->port = rxq->port_id;
1530                 rxm->ol_flags = 0;
1531                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1532                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1533                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1534 #ifdef RTE_NEXT_ABI
1535                 rxm->packet_type =
1536                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1537                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1538 #else
1539                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1540                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
1541                                 I40E_RXD_QW1_PTYPE_SHIFT);
1542 #endif /* RTE_NEXT_ABI */
1543                 if (pkt_flags & PKT_RX_RSS_HASH)
1544                         rxm->hash.rss =
1545                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1546                 if (pkt_flags & PKT_RX_FDIR)
1547                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1548
1549 #ifdef RTE_LIBRTE_IEEE1588
1550                 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1551                                         | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1552                                         >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1553
1554                 if (tsyn & 0x04)
1555                         pkt_flags |= PKT_RX_IEEE1588_TMST;
1556
1557                 rxm->timesync = tsyn & 0x03;
1558 #endif
1559                 rxm->ol_flags |= pkt_flags;
1560
1561                 rx_pkts[nb_rx++] = rxm;
1562         }
1563         rxq->rx_tail = rx_id;
1564
1565         /**
1566          * If the number of free RX descriptors is greater than the RX free
1567          * threshold of the queue, advance the receive tail register of queue.
1568          * Update that register with the value of the last processed RX
1569          * descriptor minus 1.
1570          */
1571         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1572         if (nb_hold > rxq->rx_free_thresh) {
1573                 rx_id = (uint16_t) ((rx_id == 0) ?
1574                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1575                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1576                 nb_hold = 0;
1577         }
1578         rxq->nb_rx_hold = nb_hold;
1579
1580         return nb_rx;
1581 }
1582
1583 uint16_t
1584 i40e_recv_scattered_pkts(void *rx_queue,
1585                          struct rte_mbuf **rx_pkts,
1586                          uint16_t nb_pkts)
1587 {
1588         struct i40e_rx_queue *rxq = rx_queue;
1589         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1590         volatile union i40e_rx_desc *rxdp;
1591         union i40e_rx_desc rxd;
1592         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1593         struct i40e_rx_entry *rxe;
1594         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1595         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1596         struct rte_mbuf *nmb, *rxm;
1597         uint16_t rx_id = rxq->rx_tail;
1598         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1599         uint32_t rx_status;
1600         uint64_t qword1;
1601         uint64_t dma_addr;
1602         uint64_t pkt_flags;
1603
1604         while (nb_rx < nb_pkts) {
1605                 rxdp = &rx_ring[rx_id];
1606                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1607                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1608                                         I40E_RXD_QW1_STATUS_SHIFT;
1609
1610                 /* Check the DD bit */
1611                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1612                         break;
1613
1614                 nmb = rte_rxmbuf_alloc(rxq->mp);
1615                 if (unlikely(!nmb))
1616                         break;
1617                 rxd = *rxdp;
1618                 nb_hold++;
1619                 rxe = &sw_ring[rx_id];
1620                 rx_id++;
1621                 if (rx_id == rxq->nb_rx_desc)
1622                         rx_id = 0;
1623
1624                 /* Prefetch next mbuf */
1625                 rte_prefetch0(sw_ring[rx_id].mbuf);
1626
1627                 /**
1628                  * When next RX descriptor is on a cache line boundary,
1629                  * prefetch the next 4 RX descriptors and next 8 pointers
1630                  * to mbufs.
1631                  */
1632                 if ((rx_id & 0x3) == 0) {
1633                         rte_prefetch0(&rx_ring[rx_id]);
1634                         rte_prefetch0(&sw_ring[rx_id]);
1635                 }
1636
1637                 rxm = rxe->mbuf;
1638                 rxe->mbuf = nmb;
1639                 dma_addr =
1640                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1641
1642                 /* Set data buffer address and data length of the mbuf */
1643                 rxdp->read.hdr_addr = dma_addr;
1644                 rxdp->read.pkt_addr = dma_addr;
1645                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1646                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1647                 rxm->data_len = rx_packet_len;
1648                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1649
1650                 /**
1651                  * If this is the first buffer of the received packet, set the
1652                  * pointer to the first mbuf of the packet and initialize its
1653                  * context. Otherwise, update the total length and the number
1654                  * of segments of the current scattered packet, and update the
1655                  * pointer to the last mbuf of the current packet.
1656                  */
1657                 if (!first_seg) {
1658                         first_seg = rxm;
1659                         first_seg->nb_segs = 1;
1660                         first_seg->pkt_len = rx_packet_len;
1661                 } else {
1662                         first_seg->pkt_len =
1663                                 (uint16_t)(first_seg->pkt_len +
1664                                                 rx_packet_len);
1665                         first_seg->nb_segs++;
1666                         last_seg->next = rxm;
1667                 }
1668
1669                 /**
1670                  * If this is not the last buffer of the received packet,
1671                  * update the pointer to the last mbuf of the current scattered
1672                  * packet and continue to parse the RX ring.
1673                  */
1674                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1675                         last_seg = rxm;
1676                         continue;
1677                 }
1678
1679                 /**
1680                  * This is the last buffer of the received packet. If the CRC
1681                  * is not stripped by the hardware:
1682                  *  - Subtract the CRC length from the total packet length.
1683                  *  - If the last buffer only contains the whole CRC or a part
1684                  *  of it, free the mbuf associated to the last buffer. If part
1685                  *  of the CRC is also contained in the previous mbuf, subtract
1686                  *  the length of that CRC part from the data length of the
1687                  *  previous mbuf.
1688                  */
1689                 rxm->next = NULL;
1690                 if (unlikely(rxq->crc_len > 0)) {
1691                         first_seg->pkt_len -= ETHER_CRC_LEN;
1692                         if (rx_packet_len <= ETHER_CRC_LEN) {
1693                                 rte_pktmbuf_free_seg(rxm);
1694                                 first_seg->nb_segs--;
1695                                 last_seg->data_len =
1696                                         (uint16_t)(last_seg->data_len -
1697                                         (ETHER_CRC_LEN - rx_packet_len));
1698                                 last_seg->next = NULL;
1699                         } else
1700                                 rxm->data_len = (uint16_t)(rx_packet_len -
1701                                                                 ETHER_CRC_LEN);
1702                 }
1703
1704                 first_seg->port = rxq->port_id;
1705                 first_seg->ol_flags = 0;
1706                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1707                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1708                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1709 #ifdef RTE_NEXT_ABI
1710                 first_seg->packet_type =
1711                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1712                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1713 #else
1714                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1715                 first_seg->packet_type = (uint16_t)((qword1 &
1716                                         I40E_RXD_QW1_PTYPE_MASK) >>
1717                                         I40E_RXD_QW1_PTYPE_SHIFT);
1718 #endif /* RTE_NEXT_ABI */
1719                 if (pkt_flags & PKT_RX_RSS_HASH)
1720                         rxm->hash.rss =
1721                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1722                 if (pkt_flags & PKT_RX_FDIR)
1723                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1724
1725 #ifdef RTE_LIBRTE_IEEE1588
1726                 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1727                                         | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1728                                         >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1729
1730                 if (tsyn & 0x04)
1731                         pkt_flags |= PKT_RX_IEEE1588_TMST;
1732
1733                 first_seg->timesync = tsyn & 0x03;
1734 #endif
1735                 first_seg->ol_flags |= pkt_flags;
1736
1737                 /* Prefetch data of first segment, if configured to do so. */
1738                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1739                         first_seg->data_off));
1740                 rx_pkts[nb_rx++] = first_seg;
1741                 first_seg = NULL;
1742         }
1743
1744         /* Record index of the next RX descriptor to probe. */
1745         rxq->rx_tail = rx_id;
1746         rxq->pkt_first_seg = first_seg;
1747         rxq->pkt_last_seg = last_seg;
1748
1749         /**
1750          * If the number of free RX descriptors is greater than the RX free
1751          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1752          * register. Update the RDT with the value of the last processed RX
1753          * descriptor minus 1, to guarantee that the RDT register is never
1754          * equal to the RDH register, which creates a "full" ring situtation
1755          * from the hardware point of view.
1756          */
1757         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1758         if (nb_hold > rxq->rx_free_thresh) {
1759                 rx_id = (uint16_t)(rx_id == 0 ?
1760                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1761                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1762                 nb_hold = 0;
1763         }
1764         rxq->nb_rx_hold = nb_hold;
1765
1766         return nb_rx;
1767 }
1768
1769 /* Check if the context descriptor is needed for TX offloading */
1770 static inline uint16_t
1771 i40e_calc_context_desc(uint64_t flags)
1772 {
1773         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1774                 PKT_TX_TCP_SEG |
1775                 PKT_TX_QINQ_PKT;
1776
1777 #ifdef RTE_LIBRTE_IEEE1588
1778         mask |= PKT_TX_IEEE1588_TMST;
1779 #endif
1780
1781         return ((flags & mask) ? 1 : 0);
1782 }
1783
1784 /* set i40e TSO context descriptor */
1785 static inline uint64_t
1786 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1787 {
1788         uint64_t ctx_desc = 0;
1789         uint32_t cd_cmd, hdr_len, cd_tso_len;
1790
1791         if (!tx_offload.l4_len) {
1792                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1793                 return ctx_desc;
1794         }
1795
1796         /**
1797          * in case of tunneling packet, the outer_l2_len and
1798          * outer_l3_len must be 0.
1799          */
1800         hdr_len = tx_offload.outer_l2_len +
1801                 tx_offload.outer_l3_len +
1802                 tx_offload.l2_len +
1803                 tx_offload.l3_len +
1804                 tx_offload.l4_len;
1805
1806         cd_cmd = I40E_TX_CTX_DESC_TSO;
1807         cd_tso_len = mbuf->pkt_len - hdr_len;
1808         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1809                 ((uint64_t)cd_tso_len <<
1810                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1811                 ((uint64_t)mbuf->tso_segsz <<
1812                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1813
1814         return ctx_desc;
1815 }
1816
1817 uint16_t
1818 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1819 {
1820         struct i40e_tx_queue *txq;
1821         struct i40e_tx_entry *sw_ring;
1822         struct i40e_tx_entry *txe, *txn;
1823         volatile struct i40e_tx_desc *txd;
1824         volatile struct i40e_tx_desc *txr;
1825         struct rte_mbuf *tx_pkt;
1826         struct rte_mbuf *m_seg;
1827         uint32_t cd_tunneling_params;
1828         uint16_t tx_id;
1829         uint16_t nb_tx;
1830         uint32_t td_cmd;
1831         uint32_t td_offset;
1832         uint32_t tx_flags;
1833         uint32_t td_tag;
1834         uint64_t ol_flags;
1835         uint16_t nb_used;
1836         uint16_t nb_ctx;
1837         uint16_t tx_last;
1838         uint16_t slen;
1839         uint64_t buf_dma_addr;
1840         union i40e_tx_offload tx_offload = {0};
1841
1842         txq = tx_queue;
1843         sw_ring = txq->sw_ring;
1844         txr = txq->tx_ring;
1845         tx_id = txq->tx_tail;
1846         txe = &sw_ring[tx_id];
1847
1848         /* Check if the descriptor ring needs to be cleaned. */
1849         if (txq->nb_tx_free < txq->tx_free_thresh)
1850                 i40e_xmit_cleanup(txq);
1851
1852         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1853                 td_cmd = 0;
1854                 td_tag = 0;
1855                 td_offset = 0;
1856                 tx_flags = 0;
1857
1858                 tx_pkt = *tx_pkts++;
1859                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1860
1861                 ol_flags = tx_pkt->ol_flags;
1862                 tx_offload.l2_len = tx_pkt->l2_len;
1863                 tx_offload.l3_len = tx_pkt->l3_len;
1864                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1865                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1866                 tx_offload.l4_len = tx_pkt->l4_len;
1867                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1868
1869                 /* Calculate the number of context descriptors needed. */
1870                 nb_ctx = i40e_calc_context_desc(ol_flags);
1871
1872                 /**
1873                  * The number of descriptors that must be allocated for
1874                  * a packet equals to the number of the segments of that
1875                  * packet plus 1 context descriptor if needed.
1876                  */
1877                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1878                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1879
1880                 /* Circular ring */
1881                 if (tx_last >= txq->nb_tx_desc)
1882                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1883
1884                 if (nb_used > txq->nb_tx_free) {
1885                         if (i40e_xmit_cleanup(txq) != 0) {
1886                                 if (nb_tx == 0)
1887                                         return 0;
1888                                 goto end_of_tx;
1889                         }
1890                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1891                                 while (nb_used > txq->nb_tx_free) {
1892                                         if (i40e_xmit_cleanup(txq) != 0) {
1893                                                 if (nb_tx == 0)
1894                                                         return 0;
1895                                                 goto end_of_tx;
1896                                         }
1897                                 }
1898                         }
1899                 }
1900
1901                 /* Descriptor based VLAN insertion */
1902                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1903                         tx_flags |= tx_pkt->vlan_tci <<
1904                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1905                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1906                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1907                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1908                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1909                 }
1910
1911                 /* Always enable CRC offload insertion */
1912                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1913
1914                 /* Enable checksum offloading */
1915                 cd_tunneling_params = 0;
1916                 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1917                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1918                                 tx_offload, &cd_tunneling_params);
1919                 }
1920
1921                 if (unlikely(nb_ctx)) {
1922                         /* Setup TX context descriptor if required */
1923                         volatile struct i40e_tx_context_desc *ctx_txd =
1924                                 (volatile struct i40e_tx_context_desc *)\
1925                                                         &txr[tx_id];
1926                         uint16_t cd_l2tag2 = 0;
1927                         uint64_t cd_type_cmd_tso_mss =
1928                                 I40E_TX_DESC_DTYPE_CONTEXT;
1929
1930                         txn = &sw_ring[txe->next_id];
1931                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1932                         if (txe->mbuf != NULL) {
1933                                 rte_pktmbuf_free_seg(txe->mbuf);
1934                                 txe->mbuf = NULL;
1935                         }
1936
1937                         /* TSO enabled means no timestamp */
1938                         if (ol_flags & PKT_TX_TCP_SEG)
1939                                 cd_type_cmd_tso_mss |=
1940                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1941                         else {
1942 #ifdef RTE_LIBRTE_IEEE1588
1943                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1944                                         cd_type_cmd_tso_mss |=
1945                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1946                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1947 #endif
1948                         }
1949
1950                         ctx_txd->tunneling_params =
1951                                 rte_cpu_to_le_32(cd_tunneling_params);
1952                         if (ol_flags & PKT_TX_QINQ_PKT) {
1953                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1954                                 cd_type_cmd_tso_mss |=
1955                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1956                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1957                         }
1958                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1959                         ctx_txd->type_cmd_tso_mss =
1960                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1961
1962                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1963                                 "tunneling_params: %#x;\n"
1964                                 "l2tag2: %#hx;\n"
1965                                 "rsvd: %#hx;\n"
1966                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1967                                 tx_pkt, tx_id,
1968                                 ctx_txd->tunneling_params,
1969                                 ctx_txd->l2tag2,
1970                                 ctx_txd->rsvd,
1971                                 ctx_txd->type_cmd_tso_mss);
1972
1973                         txe->last_id = tx_last;
1974                         tx_id = txe->next_id;
1975                         txe = txn;
1976                 }
1977
1978                 m_seg = tx_pkt;
1979                 do {
1980                         txd = &txr[tx_id];
1981                         txn = &sw_ring[txe->next_id];
1982
1983                         if (txe->mbuf)
1984                                 rte_pktmbuf_free_seg(txe->mbuf);
1985                         txe->mbuf = m_seg;
1986
1987                         /* Setup TX Descriptor */
1988                         slen = m_seg->data_len;
1989                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1990
1991                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1992                                 "buf_dma_addr: %#"PRIx64";\n"
1993                                 "td_cmd: %#x;\n"
1994                                 "td_offset: %#x;\n"
1995                                 "td_len: %u;\n"
1996                                 "td_tag: %#x;\n",
1997                                 tx_pkt, tx_id, buf_dma_addr,
1998                                 td_cmd, td_offset, slen, td_tag);
1999
2000                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2001                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
2002                                                 td_offset, slen, td_tag);
2003                         txe->last_id = tx_last;
2004                         tx_id = txe->next_id;
2005                         txe = txn;
2006                         m_seg = m_seg->next;
2007                 } while (m_seg != NULL);
2008
2009                 /* The last packet data descriptor needs End Of Packet (EOP) */
2010                 td_cmd |= I40E_TX_DESC_CMD_EOP;
2011                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2012                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2013
2014                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2015                         PMD_TX_FREE_LOG(DEBUG,
2016                                         "Setting RS bit on TXD id="
2017                                         "%4u (port=%d queue=%d)",
2018                                         tx_last, txq->port_id, txq->queue_id);
2019
2020                         td_cmd |= I40E_TX_DESC_CMD_RS;
2021
2022                         /* Update txq RS bit counters */
2023                         txq->nb_tx_used = 0;
2024                 }
2025
2026                 txd->cmd_type_offset_bsz |=
2027                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2028                                         I40E_TXD_QW1_CMD_SHIFT);
2029         }
2030
2031 end_of_tx:
2032         rte_wmb();
2033
2034         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2035                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
2036                    (unsigned) tx_id, (unsigned) nb_tx);
2037
2038         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2039         txq->tx_tail = tx_id;
2040
2041         return nb_tx;
2042 }
2043
2044 static inline int __attribute__((always_inline))
2045 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
2046 {
2047         struct i40e_tx_entry *txep;
2048         uint16_t i;
2049
2050         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2051                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
2052                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
2053                 return 0;
2054
2055         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
2056
2057         for (i = 0; i < txq->tx_rs_thresh; i++)
2058                 rte_prefetch0((txep + i)->mbuf);
2059
2060         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
2061                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2062                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2063                         txep->mbuf = NULL;
2064                 }
2065         } else {
2066                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2067                         rte_pktmbuf_free_seg(txep->mbuf);
2068                         txep->mbuf = NULL;
2069                 }
2070         }
2071
2072         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2073         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2074         if (txq->tx_next_dd >= txq->nb_tx_desc)
2075                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2076
2077         return txq->tx_rs_thresh;
2078 }
2079
2080 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
2081                      I40E_TX_DESC_CMD_EOP)
2082
2083 /* Populate 4 descriptors with data from 4 mbufs */
2084 static inline void
2085 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
2086 {
2087         uint64_t dma_addr;
2088         uint32_t i;
2089
2090         for (i = 0; i < 4; i++, txdp++, pkts++) {
2091                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
2092                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
2093                 txdp->cmd_type_offset_bsz =
2094                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
2095                                         (*pkts)->data_len, 0);
2096         }
2097 }
2098
2099 /* Populate 1 descriptor with data from 1 mbuf */
2100 static inline void
2101 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
2102 {
2103         uint64_t dma_addr;
2104
2105         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
2106         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
2107         txdp->cmd_type_offset_bsz =
2108                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
2109                                 (*pkts)->data_len, 0);
2110 }
2111
2112 /* Fill hardware descriptor ring with mbuf data */
2113 static inline void
2114 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
2115                      struct rte_mbuf **pkts,
2116                      uint16_t nb_pkts)
2117 {
2118         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
2119         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
2120         const int N_PER_LOOP = 4;
2121         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2122         int mainpart, leftover;
2123         int i, j;
2124
2125         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
2126         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
2127         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2128                 for (j = 0; j < N_PER_LOOP; ++j) {
2129                         (txep + i + j)->mbuf = *(pkts + i + j);
2130                 }
2131                 tx4(txdp + i, pkts + i);
2132         }
2133         if (unlikely(leftover > 0)) {
2134                 for (i = 0; i < leftover; ++i) {
2135                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2136                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2137                 }
2138         }
2139 }
2140
2141 static inline uint16_t
2142 tx_xmit_pkts(struct i40e_tx_queue *txq,
2143              struct rte_mbuf **tx_pkts,
2144              uint16_t nb_pkts)
2145 {
2146         volatile struct i40e_tx_desc *txr = txq->tx_ring;
2147         uint16_t n = 0;
2148
2149         /**
2150          * Begin scanning the H/W ring for done descriptors when the number
2151          * of available descriptors drops below tx_free_thresh. For each done
2152          * descriptor, free the associated buffer.
2153          */
2154         if (txq->nb_tx_free < txq->tx_free_thresh)
2155                 i40e_tx_free_bufs(txq);
2156
2157         /* Use available descriptor only */
2158         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2159         if (unlikely(!nb_pkts))
2160                 return 0;
2161
2162         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2163         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2164                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2165                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
2166                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2167                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
2168                                                 I40E_TXD_QW1_CMD_SHIFT);
2169                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2170                 txq->tx_tail = 0;
2171         }
2172
2173         /* Fill hardware descriptor ring with mbuf data */
2174         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2175         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2176
2177         /* Determin if RS bit needs to be set */
2178         if (txq->tx_tail > txq->tx_next_rs) {
2179                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2180                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
2181                                                 I40E_TXD_QW1_CMD_SHIFT);
2182                 txq->tx_next_rs =
2183                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2184                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2185                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2186         }
2187
2188         if (txq->tx_tail >= txq->nb_tx_desc)
2189                 txq->tx_tail = 0;
2190
2191         /* Update the tx tail register */
2192         rte_wmb();
2193         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2194
2195         return nb_pkts;
2196 }
2197
2198 static uint16_t
2199 i40e_xmit_pkts_simple(void *tx_queue,
2200                       struct rte_mbuf **tx_pkts,
2201                       uint16_t nb_pkts)
2202 {
2203         uint16_t nb_tx = 0;
2204
2205         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
2206                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
2207                                                 tx_pkts, nb_pkts);
2208
2209         while (nb_pkts) {
2210                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2211                                                 I40E_TX_MAX_BURST);
2212
2213                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
2214                                                 &tx_pkts[nb_tx], num);
2215                 nb_tx = (uint16_t)(nb_tx + ret);
2216                 nb_pkts = (uint16_t)(nb_pkts - ret);
2217                 if (ret < num)
2218                         break;
2219         }
2220
2221         return nb_tx;
2222 }
2223
2224 /*
2225  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
2226  * application used, which assume having sequential ones. But from driver's
2227  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
2228  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
2229  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
2230  * use queue_idx from 0 to 95 to access queues, while real queue would be
2231  * different. This function will do a queue mapping to find VSI the queue
2232  * belongs to.
2233  */
2234 static struct i40e_vsi*
2235 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
2236 {
2237         /* the queue in MAIN VSI range */
2238         if (queue_idx < pf->main_vsi->nb_qps)
2239                 return pf->main_vsi;
2240
2241         queue_idx -= pf->main_vsi->nb_qps;
2242
2243         /* queue_idx is greater than VMDQ VSIs range */
2244         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
2245                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
2246                 return NULL;
2247         }
2248
2249         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
2250 }
2251
2252 static uint16_t
2253 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
2254 {
2255         /* the queue in MAIN VSI range */
2256         if (queue_idx < pf->main_vsi->nb_qps)
2257                 return queue_idx;
2258
2259         /* It's VMDQ queues */
2260         queue_idx -= pf->main_vsi->nb_qps;
2261
2262         if (pf->nb_cfg_vmdq_vsi)
2263                 return queue_idx % pf->vmdq_nb_qps;
2264         else {
2265                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
2266                 return (uint16_t)(-1);
2267         }
2268 }
2269
2270 int
2271 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2272 {
2273         struct i40e_rx_queue *rxq;
2274         int err = -1;
2275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276
2277         PMD_INIT_FUNC_TRACE();
2278
2279         if (rx_queue_id < dev->data->nb_rx_queues) {
2280                 rxq = dev->data->rx_queues[rx_queue_id];
2281
2282                 err = i40e_alloc_rx_queue_mbufs(rxq);
2283                 if (err) {
2284                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
2285                         return err;
2286                 }
2287
2288                 rte_wmb();
2289
2290                 /* Init the RX tail regieter. */
2291                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2292
2293                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2294
2295                 if (err) {
2296                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2297                                     rx_queue_id);
2298
2299                         i40e_rx_queue_release_mbufs(rxq);
2300                         i40e_reset_rx_queue(rxq);
2301                 }
2302         }
2303
2304         return err;
2305 }
2306
2307 int
2308 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2309 {
2310         struct i40e_rx_queue *rxq;
2311         int err;
2312         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313
2314         if (rx_queue_id < dev->data->nb_rx_queues) {
2315                 rxq = dev->data->rx_queues[rx_queue_id];
2316
2317                 /*
2318                 * rx_queue_id is queue id aplication refers to, while
2319                 * rxq->reg_idx is the real queue index.
2320                 */
2321                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2322
2323                 if (err) {
2324                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2325                                     rx_queue_id);
2326                         return err;
2327                 }
2328                 i40e_rx_queue_release_mbufs(rxq);
2329                 i40e_reset_rx_queue(rxq);
2330         }
2331
2332         return 0;
2333 }
2334
2335 int
2336 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2337 {
2338         int err = -1;
2339         struct i40e_tx_queue *txq;
2340         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341
2342         PMD_INIT_FUNC_TRACE();
2343
2344         if (tx_queue_id < dev->data->nb_tx_queues) {
2345                 txq = dev->data->tx_queues[tx_queue_id];
2346
2347                 /*
2348                 * tx_queue_id is queue id aplication refers to, while
2349                 * rxq->reg_idx is the real queue index.
2350                 */
2351                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2352                 if (err)
2353                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2354                                     tx_queue_id);
2355         }
2356
2357         return err;
2358 }
2359
2360 int
2361 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2362 {
2363         struct i40e_tx_queue *txq;
2364         int err;
2365         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366
2367         if (tx_queue_id < dev->data->nb_tx_queues) {
2368                 txq = dev->data->tx_queues[tx_queue_id];
2369
2370                 /*
2371                 * tx_queue_id is queue id aplication refers to, while
2372                 * txq->reg_idx is the real queue index.
2373                 */
2374                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2375
2376                 if (err) {
2377                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2378                                     tx_queue_id);
2379                         return err;
2380                 }
2381
2382                 i40e_tx_queue_release_mbufs(txq);
2383                 i40e_reset_tx_queue(txq);
2384         }
2385
2386         return 0;
2387 }
2388
2389 int
2390 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2391                         uint16_t queue_idx,
2392                         uint16_t nb_desc,
2393                         unsigned int socket_id,
2394                         const struct rte_eth_rxconf *rx_conf,
2395                         struct rte_mempool *mp)
2396 {
2397         struct i40e_vsi *vsi;
2398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2400         struct i40e_rx_queue *rxq;
2401         const struct rte_memzone *rz;
2402         uint32_t ring_size;
2403         uint16_t len;
2404         int use_def_burst_func = 1;
2405
2406         if (hw->mac.type == I40E_MAC_VF) {
2407                 struct i40e_vf *vf =
2408                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2409                 vsi = &vf->vsi;
2410         } else
2411                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2412
2413         if (vsi == NULL) {
2414                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2415                             "index exceeds the maximum");
2416                 return I40E_ERR_PARAM;
2417         }
2418         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
2419                                         (nb_desc > I40E_MAX_RING_DESC) ||
2420                                         (nb_desc < I40E_MIN_RING_DESC)) {
2421                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2422                             "invalid", nb_desc);
2423                 return I40E_ERR_PARAM;
2424         }
2425
2426         /* Free memory if needed */
2427         if (dev->data->rx_queues[queue_idx]) {
2428                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2429                 dev->data->rx_queues[queue_idx] = NULL;
2430         }
2431
2432         /* Allocate the rx queue data structure */
2433         rxq = rte_zmalloc_socket("i40e rx queue",
2434                                  sizeof(struct i40e_rx_queue),
2435                                  RTE_CACHE_LINE_SIZE,
2436                                  socket_id);
2437         if (!rxq) {
2438                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2439                             "rx queue data structure");
2440                 return (-ENOMEM);
2441         }
2442         rxq->mp = mp;
2443         rxq->nb_rx_desc = nb_desc;
2444         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2445         rxq->queue_id = queue_idx;
2446         if (hw->mac.type == I40E_MAC_VF)
2447                 rxq->reg_idx = queue_idx;
2448         else /* PF device */
2449                 rxq->reg_idx = vsi->base_queue +
2450                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2451
2452         rxq->port_id = dev->data->port_id;
2453         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2454                                                         0 : ETHER_CRC_LEN);
2455         rxq->drop_en = rx_conf->rx_drop_en;
2456         rxq->vsi = vsi;
2457         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2458
2459         /* Allocate the maximun number of RX ring hardware descriptor. */
2460         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2461         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2462         rz = i40e_ring_dma_zone_reserve(dev,
2463                                         "rx_ring",
2464                                         queue_idx,
2465                                         ring_size,
2466                                         socket_id);
2467         if (!rz) {
2468                 i40e_dev_rx_queue_release(rxq);
2469                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2470                 return (-ENOMEM);
2471         }
2472
2473         /* Zero all the descriptors in the ring. */
2474         memset(rz->addr, 0, ring_size);
2475
2476 #ifdef RTE_LIBRTE_XEN_DOM0
2477         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2478 #else
2479         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2480 #endif
2481
2482         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2483
2484 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2485         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2486 #else
2487         len = nb_desc;
2488 #endif
2489
2490         /* Allocate the software ring. */
2491         rxq->sw_ring =
2492                 rte_zmalloc_socket("i40e rx sw ring",
2493                                    sizeof(struct i40e_rx_entry) * len,
2494                                    RTE_CACHE_LINE_SIZE,
2495                                    socket_id);
2496         if (!rxq->sw_ring) {
2497                 i40e_dev_rx_queue_release(rxq);
2498                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2499                 return (-ENOMEM);
2500         }
2501
2502         i40e_reset_rx_queue(rxq);
2503         rxq->q_set = TRUE;
2504         dev->data->rx_queues[queue_idx] = rxq;
2505
2506         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2507
2508         if (!use_def_burst_func && !dev->data->scattered_rx) {
2509 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2510                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2511                              "satisfied. Rx Burst Bulk Alloc function will be "
2512                              "used on port=%d, queue=%d.",
2513                              rxq->port_id, rxq->queue_id);
2514                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2515 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2516         } else {
2517                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2518                              "not satisfied, Scattered Rx is requested, "
2519                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2520                              "not enabled on port=%d, queue=%d.",
2521                              rxq->port_id, rxq->queue_id);
2522         }
2523
2524         return 0;
2525 }
2526
2527 void
2528 i40e_dev_rx_queue_release(void *rxq)
2529 {
2530         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2531
2532         if (!q) {
2533                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2534                 return;
2535         }
2536
2537         i40e_rx_queue_release_mbufs(q);
2538         rte_free(q->sw_ring);
2539         rte_free(q);
2540 }
2541
2542 uint32_t
2543 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2544 {
2545 #define I40E_RXQ_SCAN_INTERVAL 4
2546         volatile union i40e_rx_desc *rxdp;
2547         struct i40e_rx_queue *rxq;
2548         uint16_t desc = 0;
2549
2550         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2551                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2552                 return 0;
2553         }
2554
2555         rxq = dev->data->rx_queues[rx_queue_id];
2556         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2557         while ((desc < rxq->nb_rx_desc) &&
2558                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2559                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2560                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2561                 /**
2562                  * Check the DD bit of a rx descriptor of each 4 in a group,
2563                  * to avoid checking too frequently and downgrading performance
2564                  * too much.
2565                  */
2566                 desc += I40E_RXQ_SCAN_INTERVAL;
2567                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2568                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2569                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2570                                         desc - rxq->nb_rx_desc]);
2571         }
2572
2573         return desc;
2574 }
2575
2576 int
2577 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2578 {
2579         volatile union i40e_rx_desc *rxdp;
2580         struct i40e_rx_queue *rxq = rx_queue;
2581         uint16_t desc;
2582         int ret;
2583
2584         if (unlikely(offset >= rxq->nb_rx_desc)) {
2585                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2586                 return 0;
2587         }
2588
2589         desc = rxq->rx_tail + offset;
2590         if (desc >= rxq->nb_rx_desc)
2591                 desc -= rxq->nb_rx_desc;
2592
2593         rxdp = &(rxq->rx_ring[desc]);
2594
2595         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2596                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2597                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2598
2599         return ret;
2600 }
2601
2602 int
2603 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2604                         uint16_t queue_idx,
2605                         uint16_t nb_desc,
2606                         unsigned int socket_id,
2607                         const struct rte_eth_txconf *tx_conf)
2608 {
2609         struct i40e_vsi *vsi;
2610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2612         struct i40e_tx_queue *txq;
2613         const struct rte_memzone *tz;
2614         uint32_t ring_size;
2615         uint16_t tx_rs_thresh, tx_free_thresh;
2616
2617         if (hw->mac.type == I40E_MAC_VF) {
2618                 struct i40e_vf *vf =
2619                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2620                 vsi = &vf->vsi;
2621         } else
2622                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2623
2624         if (vsi == NULL) {
2625                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2626                             "exceeds the maximum", queue_idx);
2627                 return I40E_ERR_PARAM;
2628         }
2629
2630         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2631                                         (nb_desc > I40E_MAX_RING_DESC) ||
2632                                         (nb_desc < I40E_MIN_RING_DESC)) {
2633                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2634                             "invalid", nb_desc);
2635                 return I40E_ERR_PARAM;
2636         }
2637
2638         /**
2639          * The following two parameters control the setting of the RS bit on
2640          * transmit descriptors. TX descriptors will have their RS bit set
2641          * after txq->tx_rs_thresh descriptors have been used. The TX
2642          * descriptor ring will be cleaned after txq->tx_free_thresh
2643          * descriptors are used or if the number of descriptors required to
2644          * transmit a packet is greater than the number of free TX descriptors.
2645          *
2646          * The following constraints must be satisfied:
2647          *  - tx_rs_thresh must be greater than 0.
2648          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2649          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2650          *  - tx_rs_thresh must be a divisor of the ring size.
2651          *  - tx_free_thresh must be greater than 0.
2652          *  - tx_free_thresh must be less than the size of the ring minus 3.
2653          *
2654          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2655          * race condition, hence the maximum threshold constraints. When set
2656          * to zero use default values.
2657          */
2658         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2659                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2660         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2661                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2662         if (tx_rs_thresh >= (nb_desc - 2)) {
2663                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2664                              "number of TX descriptors minus 2. "
2665                              "(tx_rs_thresh=%u port=%d queue=%d)",
2666                              (unsigned int)tx_rs_thresh,
2667                              (int)dev->data->port_id,
2668                              (int)queue_idx);
2669                 return I40E_ERR_PARAM;
2670         }
2671         if (tx_free_thresh >= (nb_desc - 3)) {
2672                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2673                              "tx_free_thresh must be less than the "
2674                              "number of TX descriptors minus 3. "
2675                              "(tx_free_thresh=%u port=%d queue=%d)",
2676                              (unsigned int)tx_free_thresh,
2677                              (int)dev->data->port_id,
2678                              (int)queue_idx);
2679                 return I40E_ERR_PARAM;
2680         }
2681         if (tx_rs_thresh > tx_free_thresh) {
2682                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2683                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2684                              " tx_rs_thresh=%u port=%d queue=%d)",
2685                              (unsigned int)tx_free_thresh,
2686                              (unsigned int)tx_rs_thresh,
2687                              (int)dev->data->port_id,
2688                              (int)queue_idx);
2689                 return I40E_ERR_PARAM;
2690         }
2691         if ((nb_desc % tx_rs_thresh) != 0) {
2692                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2693                              "number of TX descriptors. (tx_rs_thresh=%u"
2694                              " port=%d queue=%d)",
2695                              (unsigned int)tx_rs_thresh,
2696                              (int)dev->data->port_id,
2697                              (int)queue_idx);
2698                 return I40E_ERR_PARAM;
2699         }
2700         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2701                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2702                              "tx_rs_thresh is greater than 1. "
2703                              "(tx_rs_thresh=%u port=%d queue=%d)",
2704                              (unsigned int)tx_rs_thresh,
2705                              (int)dev->data->port_id,
2706                              (int)queue_idx);
2707                 return I40E_ERR_PARAM;
2708         }
2709
2710         /* Free memory if needed. */
2711         if (dev->data->tx_queues[queue_idx]) {
2712                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2713                 dev->data->tx_queues[queue_idx] = NULL;
2714         }
2715
2716         /* Allocate the TX queue data structure. */
2717         txq = rte_zmalloc_socket("i40e tx queue",
2718                                   sizeof(struct i40e_tx_queue),
2719                                   RTE_CACHE_LINE_SIZE,
2720                                   socket_id);
2721         if (!txq) {
2722                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2723                             "tx queue structure");
2724                 return (-ENOMEM);
2725         }
2726
2727         /* Allocate TX hardware ring descriptors. */
2728         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2729         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2730         tz = i40e_ring_dma_zone_reserve(dev,
2731                                         "tx_ring",
2732                                         queue_idx,
2733                                         ring_size,
2734                                         socket_id);
2735         if (!tz) {
2736                 i40e_dev_tx_queue_release(txq);
2737                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2738                 return (-ENOMEM);
2739         }
2740
2741         txq->nb_tx_desc = nb_desc;
2742         txq->tx_rs_thresh = tx_rs_thresh;
2743         txq->tx_free_thresh = tx_free_thresh;
2744         txq->pthresh = tx_conf->tx_thresh.pthresh;
2745         txq->hthresh = tx_conf->tx_thresh.hthresh;
2746         txq->wthresh = tx_conf->tx_thresh.wthresh;
2747         txq->queue_id = queue_idx;
2748         if (hw->mac.type == I40E_MAC_VF)
2749                 txq->reg_idx = queue_idx;
2750         else /* PF device */
2751                 txq->reg_idx = vsi->base_queue +
2752                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2753
2754         txq->port_id = dev->data->port_id;
2755         txq->txq_flags = tx_conf->txq_flags;
2756         txq->vsi = vsi;
2757         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2758
2759 #ifdef RTE_LIBRTE_XEN_DOM0
2760         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2761 #else
2762         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2763 #endif
2764         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2765
2766         /* Allocate software ring */
2767         txq->sw_ring =
2768                 rte_zmalloc_socket("i40e tx sw ring",
2769                                    sizeof(struct i40e_tx_entry) * nb_desc,
2770                                    RTE_CACHE_LINE_SIZE,
2771                                    socket_id);
2772         if (!txq->sw_ring) {
2773                 i40e_dev_tx_queue_release(txq);
2774                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2775                 return (-ENOMEM);
2776         }
2777
2778         i40e_reset_tx_queue(txq);
2779         txq->q_set = TRUE;
2780         dev->data->tx_queues[queue_idx] = txq;
2781
2782         /* Use a simple TX queue without offloads or multi segs if possible */
2783         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2784                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2785                 PMD_INIT_LOG(INFO, "Using simple tx path");
2786                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2787         } else {
2788                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2789                 dev->tx_pkt_burst = i40e_xmit_pkts;
2790         }
2791
2792         return 0;
2793 }
2794
2795 void
2796 i40e_dev_tx_queue_release(void *txq)
2797 {
2798         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2799
2800         if (!q) {
2801                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2802                 return;
2803         }
2804
2805         i40e_tx_queue_release_mbufs(q);
2806         rte_free(q->sw_ring);
2807         rte_free(q);
2808 }
2809
2810 static const struct rte_memzone *
2811 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2812                            const char *ring_name,
2813                            uint16_t queue_id,
2814                            uint32_t ring_size,
2815                            int socket_id)
2816 {
2817         char z_name[RTE_MEMZONE_NAMESIZE];
2818         const struct rte_memzone *mz;
2819
2820         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2821                         dev->driver->pci_drv.name, ring_name,
2822                                 dev->data->port_id, queue_id);
2823         mz = rte_memzone_lookup(z_name);
2824         if (mz)
2825                 return mz;
2826
2827 #ifdef RTE_LIBRTE_XEN_DOM0
2828         return rte_memzone_reserve_bounded(z_name, ring_size,
2829                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2830 #else
2831         return rte_memzone_reserve_aligned(z_name, ring_size,
2832                                 socket_id, 0, I40E_ALIGN);
2833 #endif
2834 }
2835
2836 const struct rte_memzone *
2837 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2838 {
2839         const struct rte_memzone *mz = NULL;
2840
2841         mz = rte_memzone_lookup(name);
2842         if (mz)
2843                 return mz;
2844 #ifdef RTE_LIBRTE_XEN_DOM0
2845         mz = rte_memzone_reserve_bounded(name, len,
2846                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2847 #else
2848         mz = rte_memzone_reserve_aligned(name, len,
2849                                 socket_id, 0, I40E_ALIGN);
2850 #endif
2851         return mz;
2852 }
2853
2854 void
2855 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2856 {
2857         uint16_t i;
2858
2859         if (!rxq || !rxq->sw_ring) {
2860                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2861                 return;
2862         }
2863
2864         for (i = 0; i < rxq->nb_rx_desc; i++) {
2865                 if (rxq->sw_ring[i].mbuf) {
2866                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2867                         rxq->sw_ring[i].mbuf = NULL;
2868                 }
2869         }
2870 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2871         if (rxq->rx_nb_avail == 0)
2872                 return;
2873         for (i = 0; i < rxq->rx_nb_avail; i++) {
2874                 struct rte_mbuf *mbuf;
2875
2876                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2877                 rte_pktmbuf_free_seg(mbuf);
2878         }
2879         rxq->rx_nb_avail = 0;
2880 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2881 }
2882
2883 void
2884 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2885 {
2886         unsigned i;
2887         uint16_t len;
2888
2889         if (!rxq) {
2890                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2891                 return;
2892         }
2893
2894 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2895         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2896                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2897         else
2898 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2899                 len = rxq->nb_rx_desc;
2900
2901         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2902                 ((volatile char *)rxq->rx_ring)[i] = 0;
2903
2904 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2905         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2906         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2907                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2908
2909         rxq->rx_nb_avail = 0;
2910         rxq->rx_next_avail = 0;
2911         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2912 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2913         rxq->rx_tail = 0;
2914         rxq->nb_rx_hold = 0;
2915         rxq->pkt_first_seg = NULL;
2916         rxq->pkt_last_seg = NULL;
2917 }
2918
2919 void
2920 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2921 {
2922         uint16_t i;
2923
2924         if (!txq || !txq->sw_ring) {
2925                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2926                 return;
2927         }
2928
2929         for (i = 0; i < txq->nb_tx_desc; i++) {
2930                 if (txq->sw_ring[i].mbuf) {
2931                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2932                         txq->sw_ring[i].mbuf = NULL;
2933                 }
2934         }
2935 }
2936
2937 void
2938 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2939 {
2940         struct i40e_tx_entry *txe;
2941         uint16_t i, prev, size;
2942
2943         if (!txq) {
2944                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2945                 return;
2946         }
2947
2948         txe = txq->sw_ring;
2949         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2950         for (i = 0; i < size; i++)
2951                 ((volatile char *)txq->tx_ring)[i] = 0;
2952
2953         prev = (uint16_t)(txq->nb_tx_desc - 1);
2954         for (i = 0; i < txq->nb_tx_desc; i++) {
2955                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2956
2957                 txd->cmd_type_offset_bsz =
2958                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2959                 txe[i].mbuf =  NULL;
2960                 txe[i].last_id = i;
2961                 txe[prev].next_id = i;
2962                 prev = i;
2963         }
2964
2965         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2966         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2967
2968         txq->tx_tail = 0;
2969         txq->nb_tx_used = 0;
2970
2971         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2972         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2973 }
2974
2975 /* Init the TX queue in hardware */
2976 int
2977 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2978 {
2979         enum i40e_status_code err = I40E_SUCCESS;
2980         struct i40e_vsi *vsi = txq->vsi;
2981         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2982         uint16_t pf_q = txq->reg_idx;
2983         struct i40e_hmc_obj_txq tx_ctx;
2984         uint32_t qtx_ctl;
2985
2986         /* clear the context structure first */
2987         memset(&tx_ctx, 0, sizeof(tx_ctx));
2988         tx_ctx.new_context = 1;
2989         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2990         tx_ctx.qlen = txq->nb_tx_desc;
2991
2992 #ifdef RTE_LIBRTE_IEEE1588
2993         tx_ctx.timesync_ena = 1;
2994 #endif
2995         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2996         if (vsi->type == I40E_VSI_FDIR)
2997                 tx_ctx.fd_ena = TRUE;
2998
2999         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
3000         if (err != I40E_SUCCESS) {
3001                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
3002                 return err;
3003         }
3004
3005         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
3006         if (err != I40E_SUCCESS) {
3007                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
3008                 return err;
3009         }
3010
3011         /* Now associate this queue with this PCI function */
3012         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
3013         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
3014                                         I40E_QTX_CTL_PF_INDX_MASK);
3015         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
3016         I40E_WRITE_FLUSH(hw);
3017
3018         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
3019
3020         return err;
3021 }
3022
3023 int
3024 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
3025 {
3026         struct i40e_rx_entry *rxe = rxq->sw_ring;
3027         uint64_t dma_addr;
3028         uint16_t i;
3029
3030         for (i = 0; i < rxq->nb_rx_desc; i++) {
3031                 volatile union i40e_rx_desc *rxd;
3032                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
3033
3034                 if (unlikely(!mbuf)) {
3035                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
3036                         return -ENOMEM;
3037                 }
3038
3039                 rte_mbuf_refcnt_set(mbuf, 1);
3040                 mbuf->next = NULL;
3041                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3042                 mbuf->nb_segs = 1;
3043                 mbuf->port = rxq->port_id;
3044
3045                 dma_addr =
3046                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3047
3048                 rxd = &rxq->rx_ring[i];
3049                 rxd->read.pkt_addr = dma_addr;
3050                 rxd->read.hdr_addr = dma_addr;
3051 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
3052                 rxd->read.rsvd1 = 0;
3053                 rxd->read.rsvd2 = 0;
3054 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
3055
3056                 rxe[i].mbuf = mbuf;
3057         }
3058
3059         return 0;
3060 }
3061
3062 /*
3063  * Calculate the buffer length, and check the jumbo frame
3064  * and maximum packet length.
3065  */
3066 static int
3067 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
3068 {
3069         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
3070         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
3071         struct rte_eth_dev_data *data = pf->dev_data;
3072         uint16_t buf_size, len;
3073
3074         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
3075                 RTE_PKTMBUF_HEADROOM);
3076
3077         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
3078                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
3079         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
3080                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
3081                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
3082                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
3083                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
3084                 rxq->hs_mode = i40e_header_split_enabled;
3085                 break;
3086         case I40E_FLAG_HEADER_SPLIT_DISABLED:
3087         default:
3088                 rxq->rx_hdr_len = 0;
3089                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
3090                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
3091                 rxq->hs_mode = i40e_header_split_none;
3092                 break;
3093         }
3094
3095         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
3096         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
3097         if (data->dev_conf.rxmode.jumbo_frame == 1) {
3098                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
3099                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
3100                         PMD_DRV_LOG(ERR, "maximum packet length must "
3101                                     "be larger than %u and smaller than %u,"
3102                                     "as jumbo frame is enabled",
3103                                     (uint32_t)ETHER_MAX_LEN,
3104                                     (uint32_t)I40E_FRAME_SIZE_MAX);
3105                         return I40E_ERR_CONFIG;
3106                 }
3107         } else {
3108                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
3109                         rxq->max_pkt_len > ETHER_MAX_LEN) {
3110                         PMD_DRV_LOG(ERR, "maximum packet length must be "
3111                                     "larger than %u and smaller than %u, "
3112                                     "as jumbo frame is disabled",
3113                                     (uint32_t)ETHER_MIN_LEN,
3114                                     (uint32_t)ETHER_MAX_LEN);
3115                         return I40E_ERR_CONFIG;
3116                 }
3117         }
3118
3119         return 0;
3120 }
3121
3122 /* Init the RX queue in hardware */
3123 int
3124 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
3125 {
3126         int err = I40E_SUCCESS;
3127         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
3128         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
3129         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
3130         uint16_t pf_q = rxq->reg_idx;
3131         uint16_t buf_size;
3132         struct i40e_hmc_obj_rxq rx_ctx;
3133
3134         err = i40e_rx_queue_config(rxq);
3135         if (err < 0) {
3136                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
3137                 return err;
3138         }
3139
3140         /* Clear the context structure first */
3141         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
3142         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
3143         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
3144
3145         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
3146         rx_ctx.qlen = rxq->nb_rx_desc;
3147 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
3148         rx_ctx.dsize = 1;
3149 #endif
3150         rx_ctx.dtype = rxq->hs_mode;
3151         if (rxq->hs_mode)
3152                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
3153         else
3154                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
3155         rx_ctx.rxmax = rxq->max_pkt_len;
3156         rx_ctx.tphrdesc_ena = 1;
3157         rx_ctx.tphwdesc_ena = 1;
3158         rx_ctx.tphdata_ena = 1;
3159         rx_ctx.tphhead_ena = 1;
3160         rx_ctx.lrxqthresh = 2;
3161         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
3162         rx_ctx.l2tsel = 1;
3163         rx_ctx.showiv = 1;
3164         rx_ctx.prefena = 1;
3165
3166         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
3167         if (err != I40E_SUCCESS) {
3168                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
3169                 return err;
3170         }
3171         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
3172         if (err != I40E_SUCCESS) {
3173                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
3174                 return err;
3175         }
3176
3177         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
3178
3179         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
3180                 RTE_PKTMBUF_HEADROOM);
3181
3182         /* Check if scattered RX needs to be used. */
3183         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
3184                 dev_data->scattered_rx = 1;
3185                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3186         }
3187
3188         /* Init the RX tail regieter. */
3189         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3190
3191         return 0;
3192 }
3193
3194 void
3195 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3196 {
3197         uint16_t i;
3198
3199         PMD_INIT_FUNC_TRACE();
3200
3201         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3202                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3203                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3204         }
3205
3206         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3207                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3208                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3209         }
3210 }
3211
3212 void
3213 i40e_dev_free_queues(struct rte_eth_dev *dev)
3214 {
3215         uint16_t i;
3216
3217         PMD_INIT_FUNC_TRACE();
3218
3219         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3220                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3221                 dev->data->rx_queues[i] = NULL;
3222         }
3223         dev->data->nb_rx_queues = 0;
3224
3225         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3226                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3227                 dev->data->tx_queues[i] = NULL;
3228         }
3229         dev->data->nb_tx_queues = 0;
3230 }
3231
3232 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
3233 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
3234
3235 enum i40e_status_code
3236 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3237 {
3238         struct i40e_tx_queue *txq;
3239         const struct rte_memzone *tz = NULL;
3240         uint32_t ring_size;
3241         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3242
3243         if (!pf) {
3244                 PMD_DRV_LOG(ERR, "PF is not available");
3245                 return I40E_ERR_BAD_PTR;
3246         }
3247
3248         /* Allocate the TX queue data structure. */
3249         txq = rte_zmalloc_socket("i40e fdir tx queue",
3250                                   sizeof(struct i40e_tx_queue),
3251                                   RTE_CACHE_LINE_SIZE,
3252                                   SOCKET_ID_ANY);
3253         if (!txq) {
3254                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3255                                         "tx queue structure.");
3256                 return I40E_ERR_NO_MEMORY;
3257         }
3258
3259         /* Allocate TX hardware ring descriptors. */
3260         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3261         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3262
3263         tz = i40e_ring_dma_zone_reserve(dev,
3264                                         "fdir_tx_ring",
3265                                         I40E_FDIR_QUEUE_ID,
3266                                         ring_size,
3267                                         SOCKET_ID_ANY);
3268         if (!tz) {
3269                 i40e_dev_tx_queue_release(txq);
3270                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3271                 return I40E_ERR_NO_MEMORY;
3272         }
3273
3274         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3275         txq->queue_id = I40E_FDIR_QUEUE_ID;
3276         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3277         txq->vsi = pf->fdir.fdir_vsi;
3278
3279 #ifdef RTE_LIBRTE_XEN_DOM0
3280         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3281 #else
3282         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
3283 #endif
3284         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3285         /*
3286          * don't need to allocate software ring and reset for the fdir
3287          * program queue just set the queue has been configured.
3288          */
3289         txq->q_set = TRUE;
3290         pf->fdir.txq = txq;
3291
3292         return I40E_SUCCESS;
3293 }
3294
3295 enum i40e_status_code
3296 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3297 {
3298         struct i40e_rx_queue *rxq;
3299         const struct rte_memzone *rz = NULL;
3300         uint32_t ring_size;
3301         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3302
3303         if (!pf) {
3304                 PMD_DRV_LOG(ERR, "PF is not available");
3305                 return I40E_ERR_BAD_PTR;
3306         }
3307
3308         /* Allocate the RX queue data structure. */
3309         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3310                                   sizeof(struct i40e_rx_queue),
3311                                   RTE_CACHE_LINE_SIZE,
3312                                   SOCKET_ID_ANY);
3313         if (!rxq) {
3314                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3315                                         "rx queue structure.");
3316                 return I40E_ERR_NO_MEMORY;
3317         }
3318
3319         /* Allocate RX hardware ring descriptors. */
3320         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3321         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3322
3323         rz = i40e_ring_dma_zone_reserve(dev,
3324                                         "fdir_rx_ring",
3325                                         I40E_FDIR_QUEUE_ID,
3326                                         ring_size,
3327                                         SOCKET_ID_ANY);
3328         if (!rz) {
3329                 i40e_dev_rx_queue_release(rxq);
3330                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3331                 return I40E_ERR_NO_MEMORY;
3332         }
3333
3334         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3335         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3336         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3337         rxq->vsi = pf->fdir.fdir_vsi;
3338
3339 #ifdef RTE_LIBRTE_XEN_DOM0
3340         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3341 #else
3342         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
3343 #endif
3344         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3345
3346         /*
3347          * Don't need to allocate software ring and reset for the fdir
3348          * rx queue, just set the queue has been configured.
3349          */
3350         rxq->q_set = TRUE;
3351         pf->fdir.rxq = rxq;
3352
3353         return I40E_SUCCESS;
3354 }