1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
28 #include "i40e_logs.h"
29 #include "base/i40e_prototype.h"
30 #include "base/i40e_type.h"
31 #include "i40e_ethdev.h"
32 #include "i40e_rxtx.h"
34 #define DEFAULT_TX_RS_THRESH 32
35 #define DEFAULT_TX_FREE_THRESH 32
37 #define I40E_TX_MAX_BURST 32
39 #define I40E_DMA_MEM_ALIGN 4096
41 /* Base address of the HW descriptor ring should be 128B aligned. */
42 #define I40E_RING_BASE_ALIGN 128
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
49 #define I40E_TX_IEEE1588_TMST 0
52 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
56 PKT_TX_OUTER_IP_CKSUM)
58 #define I40E_TX_OFFLOAD_MASK ( \
65 PKT_TX_OUTER_IP_CKSUM | \
69 PKT_TX_TUNNEL_MASK | \
70 I40E_TX_IEEE1588_TMST)
72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
73 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
75 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK ( \
81 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
82 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
85 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
87 struct i40e_rx_queue *rxq = rx_queue;
88 volatile union i40e_rx_desc *rxdp;
92 rxdp = &rxq->rx_ring[desc];
93 /* watch for changes in status bit */
94 pmc->addr = &rxdp->wb.qword1.status_error_len;
97 * we expect the DD bit to be set to 1 if this descriptor was already
100 pmc->val = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
101 pmc->mask = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
103 /* registers are 64-bit */
104 pmc->size = sizeof(uint64_t);
110 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
112 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
113 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
114 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
116 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
117 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
118 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
122 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
123 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
124 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
125 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
126 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
127 mb->vlan_tci_outer = mb->vlan_tci;
128 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
129 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
130 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
131 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
133 mb->vlan_tci_outer = 0;
136 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
137 mb->vlan_tci, mb->vlan_tci_outer);
140 /* Translate the rx descriptor status to pkt flags */
141 static inline uint64_t
142 i40e_rxd_status_to_pkt_flags(uint64_t qword)
146 /* Check if RSS_HASH */
147 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
148 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
149 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
151 /* Check if FDIR Match */
152 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
158 static inline uint64_t
159 i40e_rxd_error_to_pkt_flags(uint64_t qword)
162 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
164 #define I40E_RX_ERR_BITS 0x3f
165 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
166 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
170 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
171 flags |= PKT_RX_IP_CKSUM_BAD;
173 flags |= PKT_RX_IP_CKSUM_GOOD;
175 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
176 flags |= PKT_RX_L4_CKSUM_BAD;
178 flags |= PKT_RX_L4_CKSUM_GOOD;
180 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
181 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
186 /* Function to check and set the ieee1588 timesync index and get the
189 #ifdef RTE_LIBRTE_IEEE1588
190 static inline uint64_t
191 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
193 uint64_t pkt_flags = 0;
194 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
195 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
196 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
198 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
199 == RTE_PTYPE_L2_ETHER_TIMESYNC)
200 pkt_flags = PKT_RX_IEEE1588_PTP;
202 pkt_flags |= PKT_RX_IEEE1588_TMST;
203 mb->timesync = tsyn & 0x03;
210 static inline uint64_t
211 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
214 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
215 uint16_t flexbh, flexbl;
217 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
218 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
219 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
220 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
221 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
222 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
225 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
227 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
228 flags |= PKT_RX_FDIR_ID;
229 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
231 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
232 flags |= PKT_RX_FDIR_FLX;
234 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
236 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
237 flags |= PKT_RX_FDIR_FLX;
241 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
242 flags |= PKT_RX_FDIR_ID;
248 i40e_parse_tunneling_params(uint64_t ol_flags,
249 union i40e_tx_offload tx_offload,
250 uint32_t *cd_tunneling)
252 /* EIPT: External (outer) IP header type */
253 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
254 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
255 else if (ol_flags & PKT_TX_OUTER_IPV4)
256 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
257 else if (ol_flags & PKT_TX_OUTER_IPV6)
258 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
260 /* EIPLEN: External (outer) IP header length, in DWords */
261 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
262 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
264 /* L4TUNT: L4 Tunneling Type */
265 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
266 case PKT_TX_TUNNEL_IPIP:
267 /* for non UDP / GRE tunneling, set to 00b */
269 case PKT_TX_TUNNEL_VXLAN:
270 case PKT_TX_TUNNEL_GENEVE:
271 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
273 case PKT_TX_TUNNEL_GRE:
274 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
277 PMD_TX_LOG(ERR, "Tunnel type not supported");
281 /* L4TUNLEN: L4 Tunneling Length, in Words
283 * We depend on app to set rte_mbuf.l2_len correctly.
284 * For IP in GRE it should be set to the length of the GRE
286 * for MAC in GRE or MAC in UDP it should be set to the length
287 * of the GRE or UDP headers plus the inner MAC up to including
288 * its last Ethertype.
290 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
291 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
295 i40e_txd_enable_checksum(uint64_t ol_flags,
298 union i40e_tx_offload tx_offload)
301 if (ol_flags & PKT_TX_TUNNEL_MASK)
302 *td_offset |= (tx_offload.outer_l2_len >> 1)
303 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
305 *td_offset |= (tx_offload.l2_len >> 1)
306 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
308 /* Enable L3 checksum offloads */
309 if (ol_flags & PKT_TX_IP_CKSUM) {
310 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
311 *td_offset |= (tx_offload.l3_len >> 2)
312 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
313 } else if (ol_flags & PKT_TX_IPV4) {
314 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
315 *td_offset |= (tx_offload.l3_len >> 2)
316 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
317 } else if (ol_flags & PKT_TX_IPV6) {
318 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
319 *td_offset |= (tx_offload.l3_len >> 2)
320 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
323 if (ol_flags & PKT_TX_TCP_SEG) {
324 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
325 *td_offset |= (tx_offload.l4_len >> 2)
326 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
330 /* Enable L4 checksum offloads */
331 switch (ol_flags & PKT_TX_L4_MASK) {
332 case PKT_TX_TCP_CKSUM:
333 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
334 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
335 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
337 case PKT_TX_SCTP_CKSUM:
338 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
339 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
340 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
342 case PKT_TX_UDP_CKSUM:
343 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
344 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
345 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
352 /* Construct the tx flags */
353 static inline uint64_t
354 i40e_build_ctob(uint32_t td_cmd,
359 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
360 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
361 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
362 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
363 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
367 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
369 struct i40e_tx_entry *sw_ring = txq->sw_ring;
370 volatile struct i40e_tx_desc *txd = txq->tx_ring;
371 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
372 uint16_t nb_tx_desc = txq->nb_tx_desc;
373 uint16_t desc_to_clean_to;
374 uint16_t nb_tx_to_clean;
376 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
377 if (desc_to_clean_to >= nb_tx_desc)
378 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
380 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
381 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
382 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
383 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
384 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
385 "(port=%d queue=%d)", desc_to_clean_to,
386 txq->port_id, txq->queue_id);
390 if (last_desc_cleaned > desc_to_clean_to)
391 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
394 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
397 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
399 txq->last_desc_cleaned = desc_to_clean_to;
400 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
407 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
409 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
414 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
415 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
416 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
417 "rxq->rx_free_thresh=%d, "
418 "RTE_PMD_I40E_RX_MAX_BURST=%d",
419 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
421 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
422 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
423 "rxq->rx_free_thresh=%d, "
424 "rxq->nb_rx_desc=%d",
425 rxq->rx_free_thresh, rxq->nb_rx_desc);
427 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
428 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
429 "rxq->nb_rx_desc=%d, "
430 "rxq->rx_free_thresh=%d",
431 rxq->nb_rx_desc, rxq->rx_free_thresh);
441 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
442 #define I40E_LOOK_AHEAD 8
443 #if (I40E_LOOK_AHEAD != 8)
444 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
447 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
449 volatile union i40e_rx_desc *rxdp;
450 struct i40e_rx_entry *rxep;
455 int32_t s[I40E_LOOK_AHEAD], nb_dd;
456 int32_t i, j, nb_rx = 0;
458 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
460 rxdp = &rxq->rx_ring[rxq->rx_tail];
461 rxep = &rxq->sw_ring[rxq->rx_tail];
463 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
464 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
465 I40E_RXD_QW1_STATUS_SHIFT;
467 /* Make sure there is at least 1 packet to receive */
468 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
472 * Scan LOOK_AHEAD descriptors at a time to determine which
473 * descriptors reference packets that are ready to be received.
475 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
476 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
477 /* Read desc statuses backwards to avoid race condition */
478 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
479 qword1 = rte_le_to_cpu_64(\
480 rxdp[j].wb.qword1.status_error_len);
481 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
482 I40E_RXD_QW1_STATUS_SHIFT;
487 /* Compute how many status bits were set */
488 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
489 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
493 /* Translate descriptor info to mbuf parameters */
494 for (j = 0; j < nb_dd; j++) {
496 qword1 = rte_le_to_cpu_64(\
497 rxdp[j].wb.qword1.status_error_len);
498 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
499 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
500 mb->data_len = pkt_len;
501 mb->pkt_len = pkt_len;
503 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
504 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
505 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
507 ptype_tbl[(uint8_t)((qword1 &
508 I40E_RXD_QW1_PTYPE_MASK) >>
509 I40E_RXD_QW1_PTYPE_SHIFT)];
510 if (pkt_flags & PKT_RX_RSS_HASH)
511 mb->hash.rss = rte_le_to_cpu_32(\
512 rxdp[j].wb.qword0.hi_dword.rss);
513 if (pkt_flags & PKT_RX_FDIR)
514 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
516 #ifdef RTE_LIBRTE_IEEE1588
517 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
519 mb->ol_flags |= pkt_flags;
523 for (j = 0; j < I40E_LOOK_AHEAD; j++)
524 rxq->rx_stage[i + j] = rxep[j].mbuf;
526 if (nb_dd != I40E_LOOK_AHEAD)
530 /* Clear software ring entries */
531 for (i = 0; i < nb_rx; i++)
532 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
537 static inline uint16_t
538 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
539 struct rte_mbuf **rx_pkts,
543 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
545 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
547 for (i = 0; i < nb_pkts; i++)
548 rx_pkts[i] = stage[i];
550 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
551 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
557 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
559 volatile union i40e_rx_desc *rxdp;
560 struct i40e_rx_entry *rxep;
562 uint16_t alloc_idx, i;
566 /* Allocate buffers in bulk */
567 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
568 (rxq->rx_free_thresh - 1));
569 rxep = &(rxq->sw_ring[alloc_idx]);
570 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
571 rxq->rx_free_thresh);
572 if (unlikely(diag != 0)) {
573 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
577 rxdp = &rxq->rx_ring[alloc_idx];
578 for (i = 0; i < rxq->rx_free_thresh; i++) {
579 if (likely(i < (rxq->rx_free_thresh - 1)))
580 /* Prefetch next mbuf */
581 rte_prefetch0(rxep[i + 1].mbuf);
584 rte_mbuf_refcnt_set(mb, 1);
586 mb->data_off = RTE_PKTMBUF_HEADROOM;
588 mb->port = rxq->port_id;
589 dma_addr = rte_cpu_to_le_64(\
590 rte_mbuf_data_iova_default(mb));
591 rxdp[i].read.hdr_addr = 0;
592 rxdp[i].read.pkt_addr = dma_addr;
595 /* Update rx tail regsiter */
596 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
598 rxq->rx_free_trigger =
599 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
600 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
601 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
606 static inline uint16_t
607 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
609 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
610 struct rte_eth_dev *dev;
616 if (rxq->rx_nb_avail)
617 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
619 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
620 rxq->rx_next_avail = 0;
621 rxq->rx_nb_avail = nb_rx;
622 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
624 if (rxq->rx_tail > rxq->rx_free_trigger) {
625 if (i40e_rx_alloc_bufs(rxq) != 0) {
628 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
629 dev->data->rx_mbuf_alloc_failed +=
632 rxq->rx_nb_avail = 0;
633 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
634 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
635 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
641 if (rxq->rx_tail >= rxq->nb_rx_desc)
644 if (rxq->rx_nb_avail)
645 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
651 i40e_recv_pkts_bulk_alloc(void *rx_queue,
652 struct rte_mbuf **rx_pkts,
655 uint16_t nb_rx = 0, n, count;
657 if (unlikely(nb_pkts == 0))
660 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
661 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
664 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
665 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
666 nb_rx = (uint16_t)(nb_rx + count);
667 nb_pkts = (uint16_t)(nb_pkts - count);
676 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
677 struct rte_mbuf __rte_unused **rx_pkts,
678 uint16_t __rte_unused nb_pkts)
682 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
685 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
687 struct i40e_rx_queue *rxq;
688 volatile union i40e_rx_desc *rx_ring;
689 volatile union i40e_rx_desc *rxdp;
690 union i40e_rx_desc rxd;
691 struct i40e_rx_entry *sw_ring;
692 struct i40e_rx_entry *rxe;
693 struct rte_eth_dev *dev;
694 struct rte_mbuf *rxm;
695 struct rte_mbuf *nmb;
699 uint16_t rx_packet_len;
700 uint16_t rx_id, nb_hold;
708 rx_id = rxq->rx_tail;
709 rx_ring = rxq->rx_ring;
710 sw_ring = rxq->sw_ring;
711 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
713 while (nb_rx < nb_pkts) {
714 rxdp = &rx_ring[rx_id];
715 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
716 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
717 >> I40E_RXD_QW1_STATUS_SHIFT;
719 /* Check the DD bit first */
720 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
723 nmb = rte_mbuf_raw_alloc(rxq->mp);
724 if (unlikely(!nmb)) {
725 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
726 dev->data->rx_mbuf_alloc_failed++;
732 rxe = &sw_ring[rx_id];
734 if (unlikely(rx_id == rxq->nb_rx_desc))
737 /* Prefetch next mbuf */
738 rte_prefetch0(sw_ring[rx_id].mbuf);
741 * When next RX descriptor is on a cache line boundary,
742 * prefetch the next 4 RX descriptors and next 8 pointers
745 if ((rx_id & 0x3) == 0) {
746 rte_prefetch0(&rx_ring[rx_id]);
747 rte_prefetch0(&sw_ring[rx_id]);
752 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
753 rxdp->read.hdr_addr = 0;
754 rxdp->read.pkt_addr = dma_addr;
756 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
757 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
759 rxm->data_off = RTE_PKTMBUF_HEADROOM;
760 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
763 rxm->pkt_len = rx_packet_len;
764 rxm->data_len = rx_packet_len;
765 rxm->port = rxq->port_id;
767 i40e_rxd_to_vlan_tci(rxm, &rxd);
768 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
769 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
771 ptype_tbl[(uint8_t)((qword1 &
772 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
773 if (pkt_flags & PKT_RX_RSS_HASH)
775 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
776 if (pkt_flags & PKT_RX_FDIR)
777 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
779 #ifdef RTE_LIBRTE_IEEE1588
780 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
782 rxm->ol_flags |= pkt_flags;
784 rx_pkts[nb_rx++] = rxm;
786 rxq->rx_tail = rx_id;
789 * If the number of free RX descriptors is greater than the RX free
790 * threshold of the queue, advance the receive tail register of queue.
791 * Update that register with the value of the last processed RX
792 * descriptor minus 1.
794 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
795 if (nb_hold > rxq->rx_free_thresh) {
796 rx_id = (uint16_t) ((rx_id == 0) ?
797 (rxq->nb_rx_desc - 1) : (rx_id - 1));
798 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
801 rxq->nb_rx_hold = nb_hold;
807 i40e_recv_scattered_pkts(void *rx_queue,
808 struct rte_mbuf **rx_pkts,
811 struct i40e_rx_queue *rxq = rx_queue;
812 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
813 volatile union i40e_rx_desc *rxdp;
814 union i40e_rx_desc rxd;
815 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
816 struct i40e_rx_entry *rxe;
817 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
818 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
819 struct rte_mbuf *nmb, *rxm;
820 uint16_t rx_id = rxq->rx_tail;
821 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
822 struct rte_eth_dev *dev;
827 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
829 while (nb_rx < nb_pkts) {
830 rxdp = &rx_ring[rx_id];
831 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
832 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
833 I40E_RXD_QW1_STATUS_SHIFT;
835 /* Check the DD bit */
836 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
839 nmb = rte_mbuf_raw_alloc(rxq->mp);
840 if (unlikely(!nmb)) {
841 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
842 dev->data->rx_mbuf_alloc_failed++;
848 rxe = &sw_ring[rx_id];
850 if (rx_id == rxq->nb_rx_desc)
853 /* Prefetch next mbuf */
854 rte_prefetch0(sw_ring[rx_id].mbuf);
857 * When next RX descriptor is on a cache line boundary,
858 * prefetch the next 4 RX descriptors and next 8 pointers
861 if ((rx_id & 0x3) == 0) {
862 rte_prefetch0(&rx_ring[rx_id]);
863 rte_prefetch0(&sw_ring[rx_id]);
869 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
871 /* Set data buffer address and data length of the mbuf */
872 rxdp->read.hdr_addr = 0;
873 rxdp->read.pkt_addr = dma_addr;
874 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
875 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
876 rxm->data_len = rx_packet_len;
877 rxm->data_off = RTE_PKTMBUF_HEADROOM;
880 * If this is the first buffer of the received packet, set the
881 * pointer to the first mbuf of the packet and initialize its
882 * context. Otherwise, update the total length and the number
883 * of segments of the current scattered packet, and update the
884 * pointer to the last mbuf of the current packet.
888 first_seg->nb_segs = 1;
889 first_seg->pkt_len = rx_packet_len;
892 (uint16_t)(first_seg->pkt_len +
894 first_seg->nb_segs++;
895 last_seg->next = rxm;
899 * If this is not the last buffer of the received packet,
900 * update the pointer to the last mbuf of the current scattered
901 * packet and continue to parse the RX ring.
903 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
909 * This is the last buffer of the received packet. If the CRC
910 * is not stripped by the hardware:
911 * - Subtract the CRC length from the total packet length.
912 * - If the last buffer only contains the whole CRC or a part
913 * of it, free the mbuf associated to the last buffer. If part
914 * of the CRC is also contained in the previous mbuf, subtract
915 * the length of that CRC part from the data length of the
919 if (unlikely(rxq->crc_len > 0)) {
920 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
921 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
922 rte_pktmbuf_free_seg(rxm);
923 first_seg->nb_segs--;
925 (uint16_t)(last_seg->data_len -
926 (RTE_ETHER_CRC_LEN - rx_packet_len));
927 last_seg->next = NULL;
929 rxm->data_len = (uint16_t)(rx_packet_len -
933 first_seg->port = rxq->port_id;
934 first_seg->ol_flags = 0;
935 i40e_rxd_to_vlan_tci(first_seg, &rxd);
936 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
937 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
938 first_seg->packet_type =
939 ptype_tbl[(uint8_t)((qword1 &
940 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
941 if (pkt_flags & PKT_RX_RSS_HASH)
942 first_seg->hash.rss =
943 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
944 if (pkt_flags & PKT_RX_FDIR)
945 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
947 #ifdef RTE_LIBRTE_IEEE1588
948 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
950 first_seg->ol_flags |= pkt_flags;
952 /* Prefetch data of first segment, if configured to do so. */
953 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
954 first_seg->data_off));
955 rx_pkts[nb_rx++] = first_seg;
959 /* Record index of the next RX descriptor to probe. */
960 rxq->rx_tail = rx_id;
961 rxq->pkt_first_seg = first_seg;
962 rxq->pkt_last_seg = last_seg;
965 * If the number of free RX descriptors is greater than the RX free
966 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
967 * register. Update the RDT with the value of the last processed RX
968 * descriptor minus 1, to guarantee that the RDT register is never
969 * equal to the RDH register, which creates a "full" ring situtation
970 * from the hardware point of view.
972 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
973 if (nb_hold > rxq->rx_free_thresh) {
974 rx_id = (uint16_t)(rx_id == 0 ?
975 (rxq->nb_rx_desc - 1) : (rx_id - 1));
976 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
979 rxq->nb_rx_hold = nb_hold;
984 /* Check if the context descriptor is needed for TX offloading */
985 static inline uint16_t
986 i40e_calc_context_desc(uint64_t flags)
988 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
993 #ifdef RTE_LIBRTE_IEEE1588
994 mask |= PKT_TX_IEEE1588_TMST;
997 return (flags & mask) ? 1 : 0;
1000 /* set i40e TSO context descriptor */
1001 static inline uint64_t
1002 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1004 uint64_t ctx_desc = 0;
1005 uint32_t cd_cmd, hdr_len, cd_tso_len;
1007 if (!tx_offload.l4_len) {
1008 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1012 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1013 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1014 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1016 cd_cmd = I40E_TX_CTX_DESC_TSO;
1017 cd_tso_len = mbuf->pkt_len - hdr_len;
1018 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1019 ((uint64_t)cd_tso_len <<
1020 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1021 ((uint64_t)mbuf->tso_segsz <<
1022 I40E_TXD_CTX_QW1_MSS_SHIFT);
1027 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1028 #define I40E_MAX_DATA_PER_TXD \
1029 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1030 /* Calculate the number of TX descriptors needed for each pkt */
1031 static inline uint16_t
1032 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1034 struct rte_mbuf *txd = tx_pkt;
1037 while (txd != NULL) {
1038 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1046 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1048 struct i40e_tx_queue *txq;
1049 struct i40e_tx_entry *sw_ring;
1050 struct i40e_tx_entry *txe, *txn;
1051 volatile struct i40e_tx_desc *txd;
1052 volatile struct i40e_tx_desc *txr;
1053 struct rte_mbuf *tx_pkt;
1054 struct rte_mbuf *m_seg;
1055 uint32_t cd_tunneling_params;
1066 uint64_t buf_dma_addr;
1067 union i40e_tx_offload tx_offload = {0};
1070 sw_ring = txq->sw_ring;
1072 tx_id = txq->tx_tail;
1073 txe = &sw_ring[tx_id];
1075 /* Check if the descriptor ring needs to be cleaned. */
1076 if (txq->nb_tx_free < txq->tx_free_thresh)
1077 (void)i40e_xmit_cleanup(txq);
1079 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1084 tx_pkt = *tx_pkts++;
1085 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1087 ol_flags = tx_pkt->ol_flags;
1088 tx_offload.l2_len = tx_pkt->l2_len;
1089 tx_offload.l3_len = tx_pkt->l3_len;
1090 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1091 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1092 tx_offload.l4_len = tx_pkt->l4_len;
1093 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1095 /* Calculate the number of context descriptors needed. */
1096 nb_ctx = i40e_calc_context_desc(ol_flags);
1099 * The number of descriptors that must be allocated for
1100 * a packet equals to the number of the segments of that
1101 * packet plus 1 context descriptor if needed.
1102 * Recalculate the needed tx descs when TSO enabled in case
1103 * the mbuf data size exceeds max data size that hw allows
1106 if (ol_flags & PKT_TX_TCP_SEG)
1107 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1110 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1111 tx_last = (uint16_t)(tx_id + nb_used - 1);
1114 if (tx_last >= txq->nb_tx_desc)
1115 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1117 if (nb_used > txq->nb_tx_free) {
1118 if (i40e_xmit_cleanup(txq) != 0) {
1123 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1124 while (nb_used > txq->nb_tx_free) {
1125 if (i40e_xmit_cleanup(txq) != 0) {
1134 /* Descriptor based VLAN insertion */
1135 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1136 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1137 td_tag = tx_pkt->vlan_tci;
1140 /* Always enable CRC offload insertion */
1141 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1143 /* Fill in tunneling parameters if necessary */
1144 cd_tunneling_params = 0;
1145 if (ol_flags & PKT_TX_TUNNEL_MASK)
1146 i40e_parse_tunneling_params(ol_flags, tx_offload,
1147 &cd_tunneling_params);
1148 /* Enable checksum offloading */
1149 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1150 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1151 &td_offset, tx_offload);
1154 /* Setup TX context descriptor if required */
1155 volatile struct i40e_tx_context_desc *ctx_txd =
1156 (volatile struct i40e_tx_context_desc *)\
1158 uint16_t cd_l2tag2 = 0;
1159 uint64_t cd_type_cmd_tso_mss =
1160 I40E_TX_DESC_DTYPE_CONTEXT;
1162 txn = &sw_ring[txe->next_id];
1163 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1164 if (txe->mbuf != NULL) {
1165 rte_pktmbuf_free_seg(txe->mbuf);
1169 /* TSO enabled means no timestamp */
1170 if (ol_flags & PKT_TX_TCP_SEG)
1171 cd_type_cmd_tso_mss |=
1172 i40e_set_tso_ctx(tx_pkt, tx_offload);
1174 #ifdef RTE_LIBRTE_IEEE1588
1175 if (ol_flags & PKT_TX_IEEE1588_TMST)
1176 cd_type_cmd_tso_mss |=
1177 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1178 I40E_TXD_CTX_QW1_CMD_SHIFT);
1182 ctx_txd->tunneling_params =
1183 rte_cpu_to_le_32(cd_tunneling_params);
1184 if (ol_flags & PKT_TX_QINQ_PKT) {
1185 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1186 cd_type_cmd_tso_mss |=
1187 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1188 I40E_TXD_CTX_QW1_CMD_SHIFT);
1190 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1191 ctx_txd->type_cmd_tso_mss =
1192 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1194 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1195 "tunneling_params: %#x;\n"
1198 "type_cmd_tso_mss: %#"PRIx64";\n",
1200 ctx_txd->tunneling_params,
1203 ctx_txd->type_cmd_tso_mss);
1205 txe->last_id = tx_last;
1206 tx_id = txe->next_id;
1213 txn = &sw_ring[txe->next_id];
1216 rte_pktmbuf_free_seg(txe->mbuf);
1219 /* Setup TX Descriptor */
1220 slen = m_seg->data_len;
1221 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1223 while ((ol_flags & PKT_TX_TCP_SEG) &&
1224 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1226 rte_cpu_to_le_64(buf_dma_addr);
1227 txd->cmd_type_offset_bsz =
1228 i40e_build_ctob(td_cmd,
1229 td_offset, I40E_MAX_DATA_PER_TXD,
1232 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1233 slen -= I40E_MAX_DATA_PER_TXD;
1235 txe->last_id = tx_last;
1236 tx_id = txe->next_id;
1239 txn = &sw_ring[txe->next_id];
1241 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1242 "buf_dma_addr: %#"PRIx64";\n"
1247 tx_pkt, tx_id, buf_dma_addr,
1248 td_cmd, td_offset, slen, td_tag);
1250 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1251 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1252 td_offset, slen, td_tag);
1253 txe->last_id = tx_last;
1254 tx_id = txe->next_id;
1256 m_seg = m_seg->next;
1257 } while (m_seg != NULL);
1259 /* The last packet data descriptor needs End Of Packet (EOP) */
1260 td_cmd |= I40E_TX_DESC_CMD_EOP;
1261 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1262 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1264 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1266 "Setting RS bit on TXD id="
1267 "%4u (port=%d queue=%d)",
1268 tx_last, txq->port_id, txq->queue_id);
1270 td_cmd |= I40E_TX_DESC_CMD_RS;
1272 /* Update txq RS bit counters */
1273 txq->nb_tx_used = 0;
1276 txd->cmd_type_offset_bsz |=
1277 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1278 I40E_TXD_QW1_CMD_SHIFT);
1282 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1283 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1284 (unsigned) tx_id, (unsigned) nb_tx);
1287 I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1288 txq->tx_tail = tx_id;
1293 static __rte_always_inline int
1294 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1296 struct i40e_tx_entry *txep;
1297 uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1298 uint16_t i = 0, j = 0;
1299 struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1300 const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1301 const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1303 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1304 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1305 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1308 txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1310 for (i = 0; i < tx_rs_thresh; i++)
1311 rte_prefetch0((txep + i)->mbuf);
1313 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1315 for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1316 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1317 free[i] = txep->mbuf;
1320 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1321 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1326 for (i = 0; i < m; ++i, ++txep) {
1327 free[i] = txep->mbuf;
1330 rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1333 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1334 rte_pktmbuf_free_seg(txep->mbuf);
1339 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1340 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1341 if (txq->tx_next_dd >= txq->nb_tx_desc)
1342 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1344 return txq->tx_rs_thresh;
1347 /* Populate 4 descriptors with data from 4 mbufs */
1349 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1354 for (i = 0; i < 4; i++, txdp++, pkts++) {
1355 dma_addr = rte_mbuf_data_iova(*pkts);
1356 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1357 txdp->cmd_type_offset_bsz =
1358 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1359 (*pkts)->data_len, 0);
1363 /* Populate 1 descriptor with data from 1 mbuf */
1365 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1369 dma_addr = rte_mbuf_data_iova(*pkts);
1370 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1371 txdp->cmd_type_offset_bsz =
1372 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1373 (*pkts)->data_len, 0);
1376 /* Fill hardware descriptor ring with mbuf data */
1378 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1379 struct rte_mbuf **pkts,
1382 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1383 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1384 const int N_PER_LOOP = 4;
1385 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1386 int mainpart, leftover;
1389 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1390 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1391 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1392 for (j = 0; j < N_PER_LOOP; ++j) {
1393 (txep + i + j)->mbuf = *(pkts + i + j);
1395 tx4(txdp + i, pkts + i);
1397 if (unlikely(leftover > 0)) {
1398 for (i = 0; i < leftover; ++i) {
1399 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1400 tx1(txdp + mainpart + i, pkts + mainpart + i);
1405 static inline uint16_t
1406 tx_xmit_pkts(struct i40e_tx_queue *txq,
1407 struct rte_mbuf **tx_pkts,
1410 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1414 * Begin scanning the H/W ring for done descriptors when the number
1415 * of available descriptors drops below tx_free_thresh. For each done
1416 * descriptor, free the associated buffer.
1418 if (txq->nb_tx_free < txq->tx_free_thresh)
1419 i40e_tx_free_bufs(txq);
1421 /* Use available descriptor only */
1422 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1423 if (unlikely(!nb_pkts))
1426 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1427 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1428 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1429 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1430 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1431 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1432 I40E_TXD_QW1_CMD_SHIFT);
1433 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1437 /* Fill hardware descriptor ring with mbuf data */
1438 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1439 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1441 /* Determin if RS bit needs to be set */
1442 if (txq->tx_tail > txq->tx_next_rs) {
1443 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1444 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1445 I40E_TXD_QW1_CMD_SHIFT);
1447 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1448 if (txq->tx_next_rs >= txq->nb_tx_desc)
1449 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1452 if (txq->tx_tail >= txq->nb_tx_desc)
1455 /* Update the tx tail register */
1456 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1462 i40e_xmit_pkts_simple(void *tx_queue,
1463 struct rte_mbuf **tx_pkts,
1468 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1469 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1473 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1476 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1477 &tx_pkts[nb_tx], num);
1478 nb_tx = (uint16_t)(nb_tx + ret);
1479 nb_pkts = (uint16_t)(nb_pkts - ret);
1488 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1492 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1497 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1498 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1509 /*********************************************************************
1511 * TX simple prep functions
1513 **********************************************************************/
1515 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1522 for (i = 0; i < nb_pkts; i++) {
1524 ol_flags = m->ol_flags;
1526 if (m->nb_segs != 1) {
1531 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1532 rte_errno = ENOTSUP;
1536 /* check the size of packet */
1537 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1538 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1546 /*********************************************************************
1550 **********************************************************************/
1552 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1559 for (i = 0; i < nb_pkts; i++) {
1561 ol_flags = m->ol_flags;
1563 /* Check for m->nb_segs to not exceed the limits. */
1564 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1565 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1566 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1570 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1571 m->tso_segsz < I40E_MIN_TSO_MSS ||
1572 m->tso_segsz > I40E_MAX_TSO_MSS ||
1573 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1574 /* MSS outside the range (256B - 9674B) are considered
1581 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1582 rte_errno = ENOTSUP;
1586 /* check the size of packet */
1587 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1592 #ifdef RTE_ETHDEV_DEBUG_TX
1593 ret = rte_validate_tx_offload(m);
1599 ret = rte_net_intel_cksum_prepare(m);
1609 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1610 * application used, which assume having sequential ones. But from driver's
1611 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1612 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1613 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1614 * use queue_idx from 0 to 95 to access queues, while real queue would be
1615 * different. This function will do a queue mapping to find VSI the queue
1618 static struct i40e_vsi*
1619 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1621 /* the queue in MAIN VSI range */
1622 if (queue_idx < pf->main_vsi->nb_qps)
1623 return pf->main_vsi;
1625 queue_idx -= pf->main_vsi->nb_qps;
1627 /* queue_idx is greater than VMDQ VSIs range */
1628 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1629 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1633 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1637 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1639 /* the queue in MAIN VSI range */
1640 if (queue_idx < pf->main_vsi->nb_qps)
1643 /* It's VMDQ queues */
1644 queue_idx -= pf->main_vsi->nb_qps;
1646 if (pf->nb_cfg_vmdq_vsi)
1647 return queue_idx % pf->vmdq_nb_qps;
1649 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1650 return (uint16_t)(-1);
1655 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1657 struct i40e_rx_queue *rxq;
1659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661 PMD_INIT_FUNC_TRACE();
1663 rxq = dev->data->rx_queues[rx_queue_id];
1664 if (!rxq || !rxq->q_set) {
1665 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1670 if (rxq->rx_deferred_start)
1671 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1674 err = i40e_alloc_rx_queue_mbufs(rxq);
1676 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1680 /* Init the RX tail regieter. */
1681 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1683 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1685 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1688 i40e_rx_queue_release_mbufs(rxq);
1689 i40e_reset_rx_queue(rxq);
1692 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1698 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1700 struct i40e_rx_queue *rxq;
1702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 rxq = dev->data->rx_queues[rx_queue_id];
1705 if (!rxq || !rxq->q_set) {
1706 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1712 * rx_queue_id is queue id application refers to, while
1713 * rxq->reg_idx is the real queue index.
1715 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1717 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1721 i40e_rx_queue_release_mbufs(rxq);
1722 i40e_reset_rx_queue(rxq);
1723 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1729 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1732 struct i40e_tx_queue *txq;
1733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735 PMD_INIT_FUNC_TRACE();
1737 txq = dev->data->tx_queues[tx_queue_id];
1738 if (!txq || !txq->q_set) {
1739 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1744 if (txq->tx_deferred_start)
1745 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1749 * tx_queue_id is queue id application refers to, while
1750 * rxq->reg_idx is the real queue index.
1752 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1754 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1758 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1764 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1766 struct i40e_tx_queue *txq;
1768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770 txq = dev->data->tx_queues[tx_queue_id];
1771 if (!txq || !txq->q_set) {
1772 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1778 * tx_queue_id is queue id application refers to, while
1779 * txq->reg_idx is the real queue index.
1781 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1783 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1788 i40e_tx_queue_release_mbufs(txq);
1789 i40e_reset_tx_queue(txq);
1790 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1796 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1798 static const uint32_t ptypes[] = {
1799 /* refers to i40e_rxd_pkt_type_mapping() */
1801 RTE_PTYPE_L2_ETHER_TIMESYNC,
1802 RTE_PTYPE_L2_ETHER_LLDP,
1803 RTE_PTYPE_L2_ETHER_ARP,
1804 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1805 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1808 RTE_PTYPE_L4_NONFRAG,
1812 RTE_PTYPE_TUNNEL_GRENAT,
1813 RTE_PTYPE_TUNNEL_IP,
1814 RTE_PTYPE_INNER_L2_ETHER,
1815 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1816 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1817 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1818 RTE_PTYPE_INNER_L4_FRAG,
1819 RTE_PTYPE_INNER_L4_ICMP,
1820 RTE_PTYPE_INNER_L4_NONFRAG,
1821 RTE_PTYPE_INNER_L4_SCTP,
1822 RTE_PTYPE_INNER_L4_TCP,
1823 RTE_PTYPE_INNER_L4_UDP,
1827 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1828 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1829 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1831 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1832 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1833 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1834 #ifdef CC_AVX512_SUPPORT
1835 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1836 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1838 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1839 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1845 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1849 for (i = 0; i < num; i++) {
1850 if (i != idx && queues[i])
1858 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1859 struct i40e_rx_queue *rxq)
1861 struct i40e_adapter *ad =
1862 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1863 int use_def_burst_func =
1864 check_rx_burst_bulk_alloc_preconditions(rxq);
1866 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1867 RTE_PKTMBUF_HEADROOM);
1868 int use_scattered_rx =
1869 (rxq->max_pkt_len > buf_size);
1871 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1873 "Failed to do RX queue initialization");
1877 if (i40e_dev_first_queue(rxq->queue_id,
1878 dev->data->rx_queues,
1879 dev->data->nb_rx_queues)) {
1881 * If it is the first queue to setup,
1882 * set all flags to default and call
1883 * i40e_set_rx_function.
1885 ad->rx_bulk_alloc_allowed = true;
1886 ad->rx_vec_allowed = true;
1887 dev->data->scattered_rx = use_scattered_rx;
1888 if (use_def_burst_func)
1889 ad->rx_bulk_alloc_allowed = false;
1890 i40e_set_rx_function(dev);
1892 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1893 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1894 " number %d of queue %d isn't power of 2",
1895 rxq->nb_rx_desc, rxq->queue_id);
1899 /* check bulk alloc conflict */
1900 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1901 PMD_DRV_LOG(ERR, "Can't use default burst.");
1904 /* check scatterred conflict */
1905 if (!dev->data->scattered_rx && use_scattered_rx) {
1906 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1909 /* check vector conflict */
1910 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1911 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1919 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1922 unsigned int socket_id,
1923 const struct rte_eth_rxconf *rx_conf,
1924 struct rte_mempool *mp)
1926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927 struct i40e_adapter *ad =
1928 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1929 struct i40e_vsi *vsi;
1930 struct i40e_pf *pf = NULL;
1931 struct i40e_vf *vf = NULL;
1932 struct i40e_rx_queue *rxq;
1933 const struct rte_memzone *rz;
1936 uint16_t reg_idx, base, bsf, tc_mapping;
1937 int q_offset, use_def_burst_func = 1;
1940 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1942 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1943 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1947 reg_idx = queue_idx;
1949 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1950 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1953 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1956 reg_idx = vsi->base_queue + q_offset;
1959 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1960 (nb_desc > I40E_MAX_RING_DESC) ||
1961 (nb_desc < I40E_MIN_RING_DESC)) {
1962 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1963 "invalid", nb_desc);
1967 /* Free memory if needed */
1968 if (dev->data->rx_queues[queue_idx]) {
1969 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1970 dev->data->rx_queues[queue_idx] = NULL;
1973 /* Allocate the rx queue data structure */
1974 rxq = rte_zmalloc_socket("i40e rx queue",
1975 sizeof(struct i40e_rx_queue),
1976 RTE_CACHE_LINE_SIZE,
1979 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1980 "rx queue data structure");
1984 rxq->nb_rx_desc = nb_desc;
1985 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1986 rxq->queue_id = queue_idx;
1987 rxq->reg_idx = reg_idx;
1988 rxq->port_id = dev->data->port_id;
1989 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1990 rxq->crc_len = RTE_ETHER_CRC_LEN;
1993 rxq->drop_en = rx_conf->rx_drop_en;
1995 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1996 rxq->offloads = offloads;
1998 /* Allocate the maximun number of RX ring hardware descriptor. */
1999 len = I40E_MAX_RING_DESC;
2002 * Allocating a little more memory because vectorized/bulk_alloc Rx
2003 * functions doesn't check boundaries each time.
2005 len += RTE_PMD_I40E_RX_MAX_BURST;
2007 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2008 I40E_DMA_MEM_ALIGN);
2010 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2011 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2013 i40e_dev_rx_queue_release(rxq);
2014 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2018 /* Zero all the descriptors in the ring. */
2019 memset(rz->addr, 0, ring_size);
2021 rxq->rx_ring_phys_addr = rz->iova;
2022 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2024 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2026 /* Allocate the software ring. */
2028 rte_zmalloc_socket("i40e rx sw ring",
2029 sizeof(struct i40e_rx_entry) * len,
2030 RTE_CACHE_LINE_SIZE,
2032 if (!rxq->sw_ring) {
2033 i40e_dev_rx_queue_release(rxq);
2034 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2038 i40e_reset_rx_queue(rxq);
2041 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2042 if (!(vsi->enabled_tc & (1 << i)))
2044 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2045 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2046 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2047 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2048 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2050 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2054 if (dev->data->dev_started) {
2055 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2056 i40e_dev_rx_queue_release(rxq);
2060 use_def_burst_func =
2061 check_rx_burst_bulk_alloc_preconditions(rxq);
2062 if (!use_def_burst_func) {
2063 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2065 "Rx Burst Bulk Alloc Preconditions are "
2066 "satisfied. Rx Burst Bulk Alloc function will be "
2067 "used on port=%d, queue=%d.",
2068 rxq->port_id, rxq->queue_id);
2069 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2072 "Rx Burst Bulk Alloc Preconditions are "
2073 "not satisfied, Scattered Rx is requested, "
2074 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2075 "not enabled on port=%d, queue=%d.",
2076 rxq->port_id, rxq->queue_id);
2077 ad->rx_bulk_alloc_allowed = false;
2081 dev->data->rx_queues[queue_idx] = rxq;
2086 i40e_dev_rx_queue_release(void *rxq)
2088 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2091 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2095 i40e_rx_queue_release_mbufs(q);
2096 rte_free(q->sw_ring);
2101 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2103 #define I40E_RXQ_SCAN_INTERVAL 4
2104 volatile union i40e_rx_desc *rxdp;
2105 struct i40e_rx_queue *rxq;
2108 rxq = dev->data->rx_queues[rx_queue_id];
2109 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2110 while ((desc < rxq->nb_rx_desc) &&
2111 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2112 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2113 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2115 * Check the DD bit of a rx descriptor of each 4 in a group,
2116 * to avoid checking too frequently and downgrading performance
2119 desc += I40E_RXQ_SCAN_INTERVAL;
2120 rxdp += I40E_RXQ_SCAN_INTERVAL;
2121 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2122 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2123 desc - rxq->nb_rx_desc]);
2130 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2132 volatile union i40e_rx_desc *rxdp;
2133 struct i40e_rx_queue *rxq = rx_queue;
2137 if (unlikely(offset >= rxq->nb_rx_desc)) {
2138 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2142 desc = rxq->rx_tail + offset;
2143 if (desc >= rxq->nb_rx_desc)
2144 desc -= rxq->nb_rx_desc;
2146 rxdp = &(rxq->rx_ring[desc]);
2148 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2149 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2150 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2156 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2158 struct i40e_rx_queue *rxq = rx_queue;
2159 volatile uint64_t *status;
2163 if (unlikely(offset >= rxq->nb_rx_desc))
2166 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2167 return RTE_ETH_RX_DESC_UNAVAIL;
2169 desc = rxq->rx_tail + offset;
2170 if (desc >= rxq->nb_rx_desc)
2171 desc -= rxq->nb_rx_desc;
2173 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2174 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2175 << I40E_RXD_QW1_STATUS_SHIFT);
2177 return RTE_ETH_RX_DESC_DONE;
2179 return RTE_ETH_RX_DESC_AVAIL;
2183 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2185 struct i40e_tx_queue *txq = tx_queue;
2186 volatile uint64_t *status;
2187 uint64_t mask, expect;
2190 if (unlikely(offset >= txq->nb_tx_desc))
2193 desc = txq->tx_tail + offset;
2194 /* go to next desc that has the RS bit */
2195 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2197 if (desc >= txq->nb_tx_desc) {
2198 desc -= txq->nb_tx_desc;
2199 if (desc >= txq->nb_tx_desc)
2200 desc -= txq->nb_tx_desc;
2203 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2204 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2205 expect = rte_cpu_to_le_64(
2206 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2207 if ((*status & mask) == expect)
2208 return RTE_ETH_TX_DESC_DONE;
2210 return RTE_ETH_TX_DESC_FULL;
2214 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2215 struct i40e_tx_queue *txq)
2217 struct i40e_adapter *ad =
2218 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2220 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2222 "Failed to do TX queue initialization");
2226 if (i40e_dev_first_queue(txq->queue_id,
2227 dev->data->tx_queues,
2228 dev->data->nb_tx_queues)) {
2230 * If it is the first queue to setup,
2231 * set all flags and call
2232 * i40e_set_tx_function.
2234 i40e_set_tx_function_flag(dev, txq);
2235 i40e_set_tx_function(dev);
2239 /* check vector conflict */
2240 if (ad->tx_vec_allowed) {
2241 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2242 i40e_txq_vec_setup(txq)) {
2243 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2247 /* check simple tx conflict */
2248 if (ad->tx_simple_allowed) {
2249 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2250 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2251 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2260 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2263 unsigned int socket_id,
2264 const struct rte_eth_txconf *tx_conf)
2266 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267 struct i40e_vsi *vsi;
2268 struct i40e_pf *pf = NULL;
2269 struct i40e_vf *vf = NULL;
2270 struct i40e_tx_queue *txq;
2271 const struct rte_memzone *tz;
2273 uint16_t tx_rs_thresh, tx_free_thresh;
2274 uint16_t reg_idx, i, base, bsf, tc_mapping;
2278 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2280 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2281 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2283 reg_idx = queue_idx;
2285 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2289 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2292 reg_idx = vsi->base_queue + q_offset;
2295 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2296 (nb_desc > I40E_MAX_RING_DESC) ||
2297 (nb_desc < I40E_MIN_RING_DESC)) {
2298 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2299 "invalid", nb_desc);
2304 * The following two parameters control the setting of the RS bit on
2305 * transmit descriptors. TX descriptors will have their RS bit set
2306 * after txq->tx_rs_thresh descriptors have been used. The TX
2307 * descriptor ring will be cleaned after txq->tx_free_thresh
2308 * descriptors are used or if the number of descriptors required to
2309 * transmit a packet is greater than the number of free TX descriptors.
2311 * The following constraints must be satisfied:
2312 * - tx_rs_thresh must be greater than 0.
2313 * - tx_rs_thresh must be less than the size of the ring minus 2.
2314 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2315 * - tx_rs_thresh must be a divisor of the ring size.
2316 * - tx_free_thresh must be greater than 0.
2317 * - tx_free_thresh must be less than the size of the ring minus 3.
2318 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2320 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2321 * race condition, hence the maximum threshold constraints. When set
2322 * to zero use default values.
2324 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2325 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2326 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2327 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2328 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2329 if (tx_conf->tx_rs_thresh > 0)
2330 tx_rs_thresh = tx_conf->tx_rs_thresh;
2331 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2332 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2333 "exceed nb_desc. (tx_rs_thresh=%u "
2334 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2335 (unsigned int)tx_rs_thresh,
2336 (unsigned int)tx_free_thresh,
2337 (unsigned int)nb_desc,
2338 (int)dev->data->port_id,
2340 return I40E_ERR_PARAM;
2342 if (tx_rs_thresh >= (nb_desc - 2)) {
2343 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2344 "number of TX descriptors minus 2. "
2345 "(tx_rs_thresh=%u port=%d queue=%d)",
2346 (unsigned int)tx_rs_thresh,
2347 (int)dev->data->port_id,
2349 return I40E_ERR_PARAM;
2351 if (tx_free_thresh >= (nb_desc - 3)) {
2352 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2353 "number of TX descriptors minus 3. "
2354 "(tx_free_thresh=%u port=%d queue=%d)",
2355 (unsigned int)tx_free_thresh,
2356 (int)dev->data->port_id,
2358 return I40E_ERR_PARAM;
2360 if (tx_rs_thresh > tx_free_thresh) {
2361 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2362 "equal to tx_free_thresh. (tx_free_thresh=%u"
2363 " tx_rs_thresh=%u port=%d queue=%d)",
2364 (unsigned int)tx_free_thresh,
2365 (unsigned int)tx_rs_thresh,
2366 (int)dev->data->port_id,
2368 return I40E_ERR_PARAM;
2370 if ((nb_desc % tx_rs_thresh) != 0) {
2371 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2372 "number of TX descriptors. (tx_rs_thresh=%u"
2373 " port=%d queue=%d)",
2374 (unsigned int)tx_rs_thresh,
2375 (int)dev->data->port_id,
2377 return I40E_ERR_PARAM;
2379 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2380 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2381 "tx_rs_thresh is greater than 1. "
2382 "(tx_rs_thresh=%u port=%d queue=%d)",
2383 (unsigned int)tx_rs_thresh,
2384 (int)dev->data->port_id,
2386 return I40E_ERR_PARAM;
2389 /* Free memory if needed. */
2390 if (dev->data->tx_queues[queue_idx]) {
2391 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2392 dev->data->tx_queues[queue_idx] = NULL;
2395 /* Allocate the TX queue data structure. */
2396 txq = rte_zmalloc_socket("i40e tx queue",
2397 sizeof(struct i40e_tx_queue),
2398 RTE_CACHE_LINE_SIZE,
2401 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2402 "tx queue structure");
2406 /* Allocate TX hardware ring descriptors. */
2407 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2408 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2409 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2410 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2412 i40e_dev_tx_queue_release(txq);
2413 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2417 txq->nb_tx_desc = nb_desc;
2418 txq->tx_rs_thresh = tx_rs_thresh;
2419 txq->tx_free_thresh = tx_free_thresh;
2420 txq->pthresh = tx_conf->tx_thresh.pthresh;
2421 txq->hthresh = tx_conf->tx_thresh.hthresh;
2422 txq->wthresh = tx_conf->tx_thresh.wthresh;
2423 txq->queue_id = queue_idx;
2424 txq->reg_idx = reg_idx;
2425 txq->port_id = dev->data->port_id;
2426 txq->offloads = offloads;
2428 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2430 txq->tx_ring_phys_addr = tz->iova;
2431 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2433 /* Allocate software ring */
2435 rte_zmalloc_socket("i40e tx sw ring",
2436 sizeof(struct i40e_tx_entry) * nb_desc,
2437 RTE_CACHE_LINE_SIZE,
2439 if (!txq->sw_ring) {
2440 i40e_dev_tx_queue_release(txq);
2441 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2445 i40e_reset_tx_queue(txq);
2448 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2449 if (!(vsi->enabled_tc & (1 << i)))
2451 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2452 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2453 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2454 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2455 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2457 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2461 if (dev->data->dev_started) {
2462 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2463 i40e_dev_tx_queue_release(txq);
2468 * Use a simple TX queue without offloads or
2469 * multi segs if possible
2471 i40e_set_tx_function_flag(dev, txq);
2473 dev->data->tx_queues[queue_idx] = txq;
2479 i40e_dev_tx_queue_release(void *txq)
2481 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2484 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2488 i40e_tx_queue_release_mbufs(q);
2489 rte_free(q->sw_ring);
2493 const struct rte_memzone *
2494 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2496 const struct rte_memzone *mz;
2498 mz = rte_memzone_lookup(name);
2502 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2503 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2508 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2512 /* SSE Vector driver has a different way of releasing mbufs. */
2513 if (rxq->rx_using_sse) {
2514 i40e_rx_queue_release_mbufs_vec(rxq);
2518 if (!rxq->sw_ring) {
2519 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2523 for (i = 0; i < rxq->nb_rx_desc; i++) {
2524 if (rxq->sw_ring[i].mbuf) {
2525 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2526 rxq->sw_ring[i].mbuf = NULL;
2529 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2530 if (rxq->rx_nb_avail == 0)
2532 for (i = 0; i < rxq->rx_nb_avail; i++) {
2533 struct rte_mbuf *mbuf;
2535 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2536 rte_pktmbuf_free_seg(mbuf);
2538 rxq->rx_nb_avail = 0;
2539 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2543 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2549 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2553 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2554 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2555 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2557 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2558 len = rxq->nb_rx_desc;
2560 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2561 ((volatile char *)rxq->rx_ring)[i] = 0;
2563 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2564 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2565 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2567 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2568 rxq->rx_nb_avail = 0;
2569 rxq->rx_next_avail = 0;
2570 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2571 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2573 rxq->nb_rx_hold = 0;
2574 rxq->pkt_first_seg = NULL;
2575 rxq->pkt_last_seg = NULL;
2577 rxq->rxrearm_start = 0;
2578 rxq->rxrearm_nb = 0;
2582 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2584 struct rte_eth_dev *dev;
2587 if (!txq || !txq->sw_ring) {
2588 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2592 dev = &rte_eth_devices[txq->port_id];
2595 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2596 * so need to free remains more carefully.
2598 #ifdef CC_AVX512_SUPPORT
2599 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2600 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2602 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2603 if (txq->tx_tail < i) {
2604 for (; i < txq->nb_tx_desc; i++) {
2605 rte_pktmbuf_free_seg(swr[i].mbuf);
2610 for (; i < txq->tx_tail; i++) {
2611 rte_pktmbuf_free_seg(swr[i].mbuf);
2617 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2618 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2619 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2620 if (txq->tx_tail < i) {
2621 for (; i < txq->nb_tx_desc; i++) {
2622 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2623 txq->sw_ring[i].mbuf = NULL;
2627 for (; i < txq->tx_tail; i++) {
2628 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2629 txq->sw_ring[i].mbuf = NULL;
2632 for (i = 0; i < txq->nb_tx_desc; i++) {
2633 if (txq->sw_ring[i].mbuf) {
2634 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2635 txq->sw_ring[i].mbuf = NULL;
2642 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2645 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2646 uint16_t i, tx_last, tx_id;
2647 uint16_t nb_tx_free_last;
2648 uint16_t nb_tx_to_clean;
2651 /* Start free mbuf from the next of tx_tail */
2652 tx_last = txq->tx_tail;
2653 tx_id = swr_ring[tx_last].next_id;
2655 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2658 nb_tx_to_clean = txq->nb_tx_free;
2659 nb_tx_free_last = txq->nb_tx_free;
2661 free_cnt = txq->nb_tx_desc;
2663 /* Loop through swr_ring to count the amount of
2664 * freeable mubfs and packets.
2666 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2667 for (i = 0; i < nb_tx_to_clean &&
2668 pkt_cnt < free_cnt &&
2669 tx_id != tx_last; i++) {
2670 if (swr_ring[tx_id].mbuf != NULL) {
2671 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2672 swr_ring[tx_id].mbuf = NULL;
2675 * last segment in the packet,
2676 * increment packet count
2678 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2681 tx_id = swr_ring[tx_id].next_id;
2684 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2685 txq->nb_tx_free || tx_id == tx_last)
2688 if (pkt_cnt < free_cnt) {
2689 if (i40e_xmit_cleanup(txq))
2692 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2693 nb_tx_free_last = txq->nb_tx_free;
2697 return (int)pkt_cnt;
2701 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2706 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2707 free_cnt = txq->nb_tx_desc;
2709 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2711 for (i = 0; i < cnt; i += n) {
2712 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2715 n = i40e_tx_free_bufs(txq);
2725 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2726 uint32_t free_cnt __rte_unused)
2731 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2733 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2734 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2735 struct i40e_adapter *ad =
2736 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2738 if (ad->tx_simple_allowed) {
2739 if (ad->tx_vec_allowed)
2740 return i40e_tx_done_cleanup_vec(q, free_cnt);
2742 return i40e_tx_done_cleanup_simple(q, free_cnt);
2744 return i40e_tx_done_cleanup_full(q, free_cnt);
2749 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2751 struct i40e_tx_entry *txe;
2752 uint16_t i, prev, size;
2755 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2760 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2761 for (i = 0; i < size; i++)
2762 ((volatile char *)txq->tx_ring)[i] = 0;
2764 prev = (uint16_t)(txq->nb_tx_desc - 1);
2765 for (i = 0; i < txq->nb_tx_desc; i++) {
2766 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2768 txd->cmd_type_offset_bsz =
2769 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2772 txe[prev].next_id = i;
2776 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2777 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2780 txq->nb_tx_used = 0;
2782 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2783 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2786 /* Init the TX queue in hardware */
2788 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2790 enum i40e_status_code err = I40E_SUCCESS;
2791 struct i40e_vsi *vsi = txq->vsi;
2792 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2793 uint16_t pf_q = txq->reg_idx;
2794 struct i40e_hmc_obj_txq tx_ctx;
2797 /* clear the context structure first */
2798 memset(&tx_ctx, 0, sizeof(tx_ctx));
2799 tx_ctx.new_context = 1;
2800 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2801 tx_ctx.qlen = txq->nb_tx_desc;
2803 #ifdef RTE_LIBRTE_IEEE1588
2804 tx_ctx.timesync_ena = 1;
2806 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2807 if (vsi->type == I40E_VSI_FDIR)
2808 tx_ctx.fd_ena = TRUE;
2810 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2811 if (err != I40E_SUCCESS) {
2812 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2816 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2817 if (err != I40E_SUCCESS) {
2818 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2822 /* Now associate this queue with this PCI function */
2823 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2824 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2825 I40E_QTX_CTL_PF_INDX_MASK);
2826 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2827 I40E_WRITE_FLUSH(hw);
2829 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2835 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2837 struct i40e_rx_entry *rxe = rxq->sw_ring;
2841 for (i = 0; i < rxq->nb_rx_desc; i++) {
2842 volatile union i40e_rx_desc *rxd;
2843 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2845 if (unlikely(!mbuf)) {
2846 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2850 rte_mbuf_refcnt_set(mbuf, 1);
2852 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2854 mbuf->port = rxq->port_id;
2857 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2859 rxd = &rxq->rx_ring[i];
2860 rxd->read.pkt_addr = dma_addr;
2861 rxd->read.hdr_addr = 0;
2862 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2863 rxd->read.rsvd1 = 0;
2864 rxd->read.rsvd2 = 0;
2865 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2874 * Calculate the buffer length, and check the jumbo frame
2875 * and maximum packet length.
2878 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2880 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2881 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2882 struct rte_eth_dev_data *data = pf->dev_data;
2885 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2886 RTE_PKTMBUF_HEADROOM);
2888 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2889 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2890 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2891 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2892 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2893 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2894 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2895 rxq->hs_mode = i40e_header_split_enabled;
2897 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2899 rxq->rx_hdr_len = 0;
2900 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2901 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2902 rxq->hs_mode = i40e_header_split_none;
2907 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2908 rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2909 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2910 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
2911 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2912 PMD_DRV_LOG(ERR, "maximum packet length must "
2913 "be larger than %u and smaller than %u,"
2914 "as jumbo frame is enabled",
2915 (uint32_t)I40E_ETH_MAX_LEN,
2916 (uint32_t)I40E_FRAME_SIZE_MAX);
2917 return I40E_ERR_CONFIG;
2920 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2921 rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
2922 PMD_DRV_LOG(ERR, "maximum packet length must be "
2923 "larger than %u and smaller than %u, "
2924 "as jumbo frame is disabled",
2925 (uint32_t)RTE_ETHER_MIN_LEN,
2926 (uint32_t)I40E_ETH_MAX_LEN);
2927 return I40E_ERR_CONFIG;
2934 /* Init the RX queue in hardware */
2936 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2938 int err = I40E_SUCCESS;
2939 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2940 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2941 uint16_t pf_q = rxq->reg_idx;
2943 struct i40e_hmc_obj_rxq rx_ctx;
2945 err = i40e_rx_queue_config(rxq);
2947 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2951 /* Clear the context structure first */
2952 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2953 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2954 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2956 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2957 rx_ctx.qlen = rxq->nb_rx_desc;
2958 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2961 rx_ctx.dtype = rxq->hs_mode;
2963 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2965 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2966 rx_ctx.rxmax = rxq->max_pkt_len;
2967 rx_ctx.tphrdesc_ena = 1;
2968 rx_ctx.tphwdesc_ena = 1;
2969 rx_ctx.tphdata_ena = 1;
2970 rx_ctx.tphhead_ena = 1;
2971 rx_ctx.lrxqthresh = 2;
2972 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2974 /* showiv indicates if inner VLAN is stripped inside of tunnel
2975 * packet. When set it to 1, vlan information is stripped from
2976 * the inner header, but the hardware does not put it in the
2977 * descriptor. So set it zero by default.
2982 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2983 if (err != I40E_SUCCESS) {
2984 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2987 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2988 if (err != I40E_SUCCESS) {
2989 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2993 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2995 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2996 RTE_PKTMBUF_HEADROOM);
2998 /* Check if scattered RX needs to be used. */
2999 if (rxq->max_pkt_len > buf_size)
3000 dev_data->scattered_rx = 1;
3002 /* Init the RX tail regieter. */
3003 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3009 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3013 PMD_INIT_FUNC_TRACE();
3015 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3016 if (!dev->data->tx_queues[i])
3018 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3019 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3022 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3023 if (!dev->data->rx_queues[i])
3025 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3026 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3031 i40e_dev_free_queues(struct rte_eth_dev *dev)
3035 PMD_INIT_FUNC_TRACE();
3037 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3038 if (!dev->data->rx_queues[i])
3040 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3041 dev->data->rx_queues[i] = NULL;
3042 rte_eth_dma_zone_free(dev, "rx_ring", i);
3045 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3046 if (!dev->data->tx_queues[i])
3048 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3049 dev->data->tx_queues[i] = NULL;
3050 rte_eth_dma_zone_free(dev, "tx_ring", i);
3054 enum i40e_status_code
3055 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3057 struct i40e_tx_queue *txq;
3058 const struct rte_memzone *tz = NULL;
3059 struct rte_eth_dev *dev;
3063 PMD_DRV_LOG(ERR, "PF is not available");
3064 return I40E_ERR_BAD_PTR;
3067 dev = &rte_eth_devices[pf->dev_data->port_id];
3069 /* Allocate the TX queue data structure. */
3070 txq = rte_zmalloc_socket("i40e fdir tx queue",
3071 sizeof(struct i40e_tx_queue),
3072 RTE_CACHE_LINE_SIZE,
3075 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3076 "tx queue structure.");
3077 return I40E_ERR_NO_MEMORY;
3080 /* Allocate TX hardware ring descriptors. */
3081 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3082 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3084 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3085 I40E_FDIR_QUEUE_ID, ring_size,
3086 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3088 i40e_dev_tx_queue_release(txq);
3089 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3090 return I40E_ERR_NO_MEMORY;
3093 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3094 txq->queue_id = I40E_FDIR_QUEUE_ID;
3095 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3096 txq->vsi = pf->fdir.fdir_vsi;
3098 txq->tx_ring_phys_addr = tz->iova;
3099 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3102 * don't need to allocate software ring and reset for the fdir
3103 * program queue just set the queue has been configured.
3107 pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3109 return I40E_SUCCESS;
3112 enum i40e_status_code
3113 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3115 struct i40e_rx_queue *rxq;
3116 const struct rte_memzone *rz = NULL;
3118 struct rte_eth_dev *dev;
3121 PMD_DRV_LOG(ERR, "PF is not available");
3122 return I40E_ERR_BAD_PTR;
3125 dev = &rte_eth_devices[pf->dev_data->port_id];
3127 /* Allocate the RX queue data structure. */
3128 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3129 sizeof(struct i40e_rx_queue),
3130 RTE_CACHE_LINE_SIZE,
3133 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3134 "rx queue structure.");
3135 return I40E_ERR_NO_MEMORY;
3138 /* Allocate RX hardware ring descriptors. */
3139 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3140 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3142 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3143 I40E_FDIR_QUEUE_ID, ring_size,
3144 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3146 i40e_dev_rx_queue_release(rxq);
3147 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3148 return I40E_ERR_NO_MEMORY;
3151 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3152 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3153 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3154 rxq->vsi = pf->fdir.fdir_vsi;
3156 rxq->rx_ring_phys_addr = rz->iova;
3157 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3158 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3161 * Don't need to allocate software ring and reset for the fdir
3162 * rx queue, just set the queue has been configured.
3167 return I40E_SUCCESS;
3171 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3172 struct rte_eth_rxq_info *qinfo)
3174 struct i40e_rx_queue *rxq;
3176 rxq = dev->data->rx_queues[queue_id];
3178 qinfo->mp = rxq->mp;
3179 qinfo->scattered_rx = dev->data->scattered_rx;
3180 qinfo->nb_desc = rxq->nb_rx_desc;
3182 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3183 qinfo->conf.rx_drop_en = rxq->drop_en;
3184 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3185 qinfo->conf.offloads = rxq->offloads;
3189 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3190 struct rte_eth_txq_info *qinfo)
3192 struct i40e_tx_queue *txq;
3194 txq = dev->data->tx_queues[queue_id];
3196 qinfo->nb_desc = txq->nb_tx_desc;
3198 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3199 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3200 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3202 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3203 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3204 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3205 qinfo->conf.offloads = txq->offloads;
3209 get_avx_supported(bool request_avx512)
3212 if (request_avx512) {
3213 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3214 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3215 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3216 #ifdef CC_AVX512_SUPPORT
3220 "AVX512 is not supported in build env");
3224 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3225 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3226 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3227 #ifdef CC_AVX2_SUPPORT
3231 "AVX2 is not supported in build env");
3236 RTE_SET_USED(request_avx512);
3237 #endif /* RTE_ARCH_X86 */
3244 i40e_set_rx_function(struct rte_eth_dev *dev)
3246 struct i40e_adapter *ad =
3247 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3248 uint16_t rx_using_sse, i;
3249 /* In order to allow Vector Rx there are a few configuration
3250 * conditions to be met and Rx Bulk Allocation should be allowed.
3252 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3254 ad->rx_use_avx512 = false;
3255 ad->rx_use_avx2 = false;
3257 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3258 !ad->rx_bulk_alloc_allowed) {
3259 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3260 " Vector Rx preconditions",
3261 dev->data->port_id);
3263 ad->rx_vec_allowed = false;
3265 if (ad->rx_vec_allowed) {
3266 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3267 struct i40e_rx_queue *rxq =
3268 dev->data->rx_queues[i];
3270 if (rxq && i40e_rxq_vec_setup(rxq)) {
3271 ad->rx_vec_allowed = false;
3276 ad->rx_use_avx512 = get_avx_supported(1);
3278 if (!ad->rx_use_avx512)
3279 ad->rx_use_avx2 = get_avx_supported(0);
3284 if (ad->rx_vec_allowed &&
3285 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3287 if (dev->data->scattered_rx) {
3288 if (ad->rx_use_avx512) {
3289 #ifdef CC_AVX512_SUPPORT
3291 "Using AVX512 Vector Scattered Rx (port %d).",
3292 dev->data->port_id);
3294 i40e_recv_scattered_pkts_vec_avx512;
3298 "Using %sVector Scattered Rx (port %d).",
3299 ad->rx_use_avx2 ? "avx2 " : "",
3300 dev->data->port_id);
3301 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3302 i40e_recv_scattered_pkts_vec_avx2 :
3303 i40e_recv_scattered_pkts_vec;
3306 if (ad->rx_use_avx512) {
3307 #ifdef CC_AVX512_SUPPORT
3309 "Using AVX512 Vector Rx (port %d).",
3310 dev->data->port_id);
3312 i40e_recv_pkts_vec_avx512;
3316 "Using %sVector Rx (port %d).",
3317 ad->rx_use_avx2 ? "avx2 " : "",
3318 dev->data->port_id);
3319 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3320 i40e_recv_pkts_vec_avx2 :
3324 #else /* RTE_ARCH_X86 */
3325 if (dev->data->scattered_rx) {
3327 "Using Vector Scattered Rx (port %d).",
3328 dev->data->port_id);
3329 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3331 PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3332 dev->data->port_id);
3333 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3335 #endif /* RTE_ARCH_X86 */
3336 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3337 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3338 "satisfied. Rx Burst Bulk Alloc function "
3339 "will be used on port=%d.",
3340 dev->data->port_id);
3342 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3344 /* Simple Rx Path. */
3345 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3346 dev->data->port_id);
3347 dev->rx_pkt_burst = dev->data->scattered_rx ?
3348 i40e_recv_scattered_pkts :
3352 /* Propagate information about RX function choice through all queues. */
3353 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3355 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3356 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3357 #ifdef CC_AVX512_SUPPORT
3358 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3359 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3361 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3362 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3364 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3365 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3368 rxq->rx_using_sse = rx_using_sse;
3373 static const struct {
3374 eth_rx_burst_t pkt_burst;
3376 } i40e_rx_burst_infos[] = {
3377 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3378 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3379 { i40e_recv_pkts, "Scalar" },
3381 #ifdef CC_AVX512_SUPPORT
3382 { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3383 { i40e_recv_pkts_vec_avx512, "Vector AVX512" },
3385 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3386 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3387 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3388 { i40e_recv_pkts_vec, "Vector SSE" },
3389 #elif defined(RTE_ARCH_ARM64)
3390 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3391 { i40e_recv_pkts_vec, "Vector Neon" },
3392 #elif defined(RTE_ARCH_PPC_64)
3393 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3394 { i40e_recv_pkts_vec, "Vector AltiVec" },
3399 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3400 struct rte_eth_burst_mode *mode)
3402 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3406 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3407 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3408 snprintf(mode->info, sizeof(mode->info), "%s",
3409 i40e_rx_burst_infos[i].info);
3419 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3421 struct i40e_adapter *ad =
3422 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3424 /* Use a simple Tx queue if possible (only fast free is allowed) */
3425 ad->tx_simple_allowed =
3427 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3428 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3429 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3430 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3432 if (ad->tx_vec_allowed)
3433 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3435 else if (ad->tx_simple_allowed)
3436 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3440 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3445 i40e_set_tx_function(struct rte_eth_dev *dev)
3447 struct i40e_adapter *ad =
3448 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3451 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3453 ad->tx_use_avx2 = false;
3454 ad->tx_use_avx512 = false;
3456 if (ad->tx_vec_allowed) {
3457 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3458 struct i40e_tx_queue *txq =
3459 dev->data->tx_queues[i];
3461 if (txq && i40e_txq_vec_setup(txq)) {
3462 ad->tx_vec_allowed = false;
3467 ad->tx_use_avx512 = get_avx_supported(1);
3469 if (!ad->tx_use_avx512)
3470 ad->tx_use_avx2 = get_avx_supported(0);
3475 if (ad->tx_simple_allowed) {
3476 if (ad->tx_vec_allowed &&
3477 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3479 if (ad->tx_use_avx512) {
3480 #ifdef CC_AVX512_SUPPORT
3481 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3482 dev->data->port_id);
3483 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3486 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3487 ad->tx_use_avx2 ? "avx2 " : "",
3488 dev->data->port_id);
3489 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3490 i40e_xmit_pkts_vec_avx2 :
3493 #else /* RTE_ARCH_X86 */
3494 PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3495 dev->data->port_id);
3496 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3497 #endif /* RTE_ARCH_X86 */
3499 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3500 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3502 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3504 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3505 dev->tx_pkt_burst = i40e_xmit_pkts;
3506 dev->tx_pkt_prepare = i40e_prep_pkts;
3510 static const struct {
3511 eth_tx_burst_t pkt_burst;
3513 } i40e_tx_burst_infos[] = {
3514 { i40e_xmit_pkts_simple, "Scalar Simple" },
3515 { i40e_xmit_pkts, "Scalar" },
3517 #ifdef CC_AVX512_SUPPORT
3518 { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3520 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3521 { i40e_xmit_pkts_vec, "Vector SSE" },
3522 #elif defined(RTE_ARCH_ARM64)
3523 { i40e_xmit_pkts_vec, "Vector Neon" },
3524 #elif defined(RTE_ARCH_PPC_64)
3525 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3530 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3531 struct rte_eth_burst_mode *mode)
3533 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3537 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3538 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3539 snprintf(mode->info, sizeof(mode->info), "%s",
3540 i40e_tx_burst_infos[i].info);
3550 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3552 struct i40e_adapter *ad =
3553 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3556 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3557 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3561 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3563 struct i40e_adapter *ad =
3564 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3565 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3569 ad->pctypes_tbl[i] = 0ULL;
3570 ad->flow_types_mask = 0ULL;
3571 ad->pctypes_mask = 0ULL;
3573 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3574 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3575 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3576 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3577 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3578 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3579 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3580 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3581 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3582 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3583 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3584 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3585 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3586 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3587 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3588 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3589 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3590 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3591 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3592 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3593 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3594 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3596 if (hw->mac.type == I40E_MAC_X722 ||
3597 hw->mac.type == I40E_MAC_X722_VF) {
3598 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3599 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3600 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3601 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3602 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3603 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3604 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3605 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3606 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3607 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3608 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3609 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3612 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3613 if (ad->pctypes_tbl[i])
3614 ad->flow_types_mask |= (1ULL << i);
3615 ad->pctypes_mask |= ad->pctypes_tbl[i];
3619 #ifndef CC_AVX2_SUPPORT
3621 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3622 struct rte_mbuf __rte_unused **rx_pkts,
3623 uint16_t __rte_unused nb_pkts)
3629 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3630 struct rte_mbuf __rte_unused **rx_pkts,
3631 uint16_t __rte_unused nb_pkts)
3637 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3638 struct rte_mbuf __rte_unused **tx_pkts,
3639 uint16_t __rte_unused nb_pkts)
3643 #endif /* ifndef CC_AVX2_SUPPORT */