1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
27 #include "i40e_logs.h"
28 #include "base/i40e_prototype.h"
29 #include "base/i40e_type.h"
30 #include "i40e_ethdev.h"
31 #include "i40e_rxtx.h"
33 #define DEFAULT_TX_RS_THRESH 32
34 #define DEFAULT_TX_FREE_THRESH 32
36 #define I40E_TX_MAX_BURST 32
38 #define I40E_DMA_MEM_ALIGN 4096
40 /* Base address of the HW descriptor ring should be 128B aligned. */
41 #define I40E_RING_BASE_ALIGN 128
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
45 #ifdef RTE_LIBRTE_IEEE1588
46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
48 #define I40E_TX_IEEE1588_TMST 0
51 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
55 PKT_TX_OUTER_IP_CKSUM)
57 #define I40E_TX_OFFLOAD_MASK ( \
64 PKT_TX_OUTER_IP_CKSUM | \
68 PKT_TX_TUNNEL_MASK | \
69 I40E_TX_IEEE1588_TMST)
71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
72 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
77 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
78 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
79 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
81 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
82 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
83 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
88 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
89 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
90 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
91 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
92 mb->vlan_tci_outer = mb->vlan_tci;
93 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
94 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
95 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
96 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
98 mb->vlan_tci_outer = 0;
101 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
102 mb->vlan_tci, mb->vlan_tci_outer);
105 /* Translate the rx descriptor status to pkt flags */
106 static inline uint64_t
107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
111 /* Check if RSS_HASH */
112 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
113 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
114 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
116 /* Check if FDIR Match */
117 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
123 static inline uint64_t
124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
127 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
129 #define I40E_RX_ERR_BITS 0x3f
130 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
131 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
136 flags |= PKT_RX_IP_CKSUM_BAD;
138 flags |= PKT_RX_IP_CKSUM_GOOD;
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
141 flags |= PKT_RX_L4_CKSUM_BAD;
143 flags |= PKT_RX_L4_CKSUM_GOOD;
145 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
146 flags |= PKT_RX_EIP_CKSUM_BAD;
151 /* Function to check and set the ieee1588 timesync index and get the
154 #ifdef RTE_LIBRTE_IEEE1588
155 static inline uint64_t
156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
158 uint64_t pkt_flags = 0;
159 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
160 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
161 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
163 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
164 == RTE_PTYPE_L2_ETHER_TIMESYNC)
165 pkt_flags = PKT_RX_IEEE1588_PTP;
167 pkt_flags |= PKT_RX_IEEE1588_TMST;
168 mb->timesync = tsyn & 0x03;
175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
176 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
177 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
178 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
179 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
181 static inline uint64_t
182 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
185 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
186 uint16_t flexbh, flexbl;
188 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
189 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
190 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
191 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
192 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
193 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
196 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
198 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
199 flags |= PKT_RX_FDIR_ID;
200 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
202 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
203 flags |= PKT_RX_FDIR_FLX;
205 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
207 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
208 flags |= PKT_RX_FDIR_FLX;
212 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
213 flags |= PKT_RX_FDIR_ID;
219 i40e_parse_tunneling_params(uint64_t ol_flags,
220 union i40e_tx_offload tx_offload,
221 uint32_t *cd_tunneling)
223 /* EIPT: External (outer) IP header type */
224 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
225 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
226 else if (ol_flags & PKT_TX_OUTER_IPV4)
227 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
228 else if (ol_flags & PKT_TX_OUTER_IPV6)
229 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
231 /* EIPLEN: External (outer) IP header length, in DWords */
232 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
233 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
235 /* L4TUNT: L4 Tunneling Type */
236 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
237 case PKT_TX_TUNNEL_IPIP:
238 /* for non UDP / GRE tunneling, set to 00b */
240 case PKT_TX_TUNNEL_VXLAN:
241 case PKT_TX_TUNNEL_GENEVE:
242 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
244 case PKT_TX_TUNNEL_GRE:
245 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
248 PMD_TX_LOG(ERR, "Tunnel type not supported");
252 /* L4TUNLEN: L4 Tunneling Length, in Words
254 * We depend on app to set rte_mbuf.l2_len correctly.
255 * For IP in GRE it should be set to the length of the GRE
257 * for MAC in GRE or MAC in UDP it should be set to the length
258 * of the GRE or UDP headers plus the inner MAC up to including
259 * its last Ethertype.
261 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
262 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
266 i40e_txd_enable_checksum(uint64_t ol_flags,
269 union i40e_tx_offload tx_offload)
272 if (ol_flags & PKT_TX_TUNNEL_MASK)
273 *td_offset |= (tx_offload.outer_l2_len >> 1)
274 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
276 *td_offset |= (tx_offload.l2_len >> 1)
277 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
279 /* Enable L3 checksum offloads */
280 if (ol_flags & PKT_TX_IP_CKSUM) {
281 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
282 *td_offset |= (tx_offload.l3_len >> 2)
283 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
284 } else if (ol_flags & PKT_TX_IPV4) {
285 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
286 *td_offset |= (tx_offload.l3_len >> 2)
287 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
288 } else if (ol_flags & PKT_TX_IPV6) {
289 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
290 *td_offset |= (tx_offload.l3_len >> 2)
291 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
294 if (ol_flags & PKT_TX_TCP_SEG) {
295 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
296 *td_offset |= (tx_offload.l4_len >> 2)
297 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
301 /* Enable L4 checksum offloads */
302 switch (ol_flags & PKT_TX_L4_MASK) {
303 case PKT_TX_TCP_CKSUM:
304 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
305 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
306 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
308 case PKT_TX_SCTP_CKSUM:
309 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
310 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
311 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
313 case PKT_TX_UDP_CKSUM:
314 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
315 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
316 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
323 /* Construct the tx flags */
324 static inline uint64_t
325 i40e_build_ctob(uint32_t td_cmd,
330 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
331 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
332 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
333 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
334 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
338 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
340 struct i40e_tx_entry *sw_ring = txq->sw_ring;
341 volatile struct i40e_tx_desc *txd = txq->tx_ring;
342 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
343 uint16_t nb_tx_desc = txq->nb_tx_desc;
344 uint16_t desc_to_clean_to;
345 uint16_t nb_tx_to_clean;
347 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
348 if (desc_to_clean_to >= nb_tx_desc)
349 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
351 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
352 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
353 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
354 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
355 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
356 "(port=%d queue=%d)", desc_to_clean_to,
357 txq->port_id, txq->queue_id);
361 if (last_desc_cleaned > desc_to_clean_to)
362 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
365 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
368 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
370 txq->last_desc_cleaned = desc_to_clean_to;
371 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
377 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
378 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
380 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
385 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
386 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
387 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
388 "rxq->rx_free_thresh=%d, "
389 "RTE_PMD_I40E_RX_MAX_BURST=%d",
390 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
392 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
393 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
394 "rxq->rx_free_thresh=%d, "
395 "rxq->nb_rx_desc=%d",
396 rxq->rx_free_thresh, rxq->nb_rx_desc);
398 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
399 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
400 "rxq->nb_rx_desc=%d, "
401 "rxq->rx_free_thresh=%d",
402 rxq->nb_rx_desc, rxq->rx_free_thresh);
412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
413 #define I40E_LOOK_AHEAD 8
414 #if (I40E_LOOK_AHEAD != 8)
415 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
418 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
420 volatile union i40e_rx_desc *rxdp;
421 struct i40e_rx_entry *rxep;
426 int32_t s[I40E_LOOK_AHEAD], nb_dd;
427 int32_t i, j, nb_rx = 0;
429 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
431 rxdp = &rxq->rx_ring[rxq->rx_tail];
432 rxep = &rxq->sw_ring[rxq->rx_tail];
434 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
435 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
436 I40E_RXD_QW1_STATUS_SHIFT;
438 /* Make sure there is at least 1 packet to receive */
439 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
443 * Scan LOOK_AHEAD descriptors at a time to determine which
444 * descriptors reference packets that are ready to be received.
446 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
447 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
448 /* Read desc statuses backwards to avoid race condition */
449 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
450 qword1 = rte_le_to_cpu_64(\
451 rxdp[j].wb.qword1.status_error_len);
452 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
453 I40E_RXD_QW1_STATUS_SHIFT;
458 /* Compute how many status bits were set */
459 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
460 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
464 /* Translate descriptor info to mbuf parameters */
465 for (j = 0; j < nb_dd; j++) {
467 qword1 = rte_le_to_cpu_64(\
468 rxdp[j].wb.qword1.status_error_len);
469 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
470 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
471 mb->data_len = pkt_len;
472 mb->pkt_len = pkt_len;
474 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
475 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
476 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
478 ptype_tbl[(uint8_t)((qword1 &
479 I40E_RXD_QW1_PTYPE_MASK) >>
480 I40E_RXD_QW1_PTYPE_SHIFT)];
481 if (pkt_flags & PKT_RX_RSS_HASH)
482 mb->hash.rss = rte_le_to_cpu_32(\
483 rxdp[j].wb.qword0.hi_dword.rss);
484 if (pkt_flags & PKT_RX_FDIR)
485 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
487 #ifdef RTE_LIBRTE_IEEE1588
488 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
490 mb->ol_flags |= pkt_flags;
494 for (j = 0; j < I40E_LOOK_AHEAD; j++)
495 rxq->rx_stage[i + j] = rxep[j].mbuf;
497 if (nb_dd != I40E_LOOK_AHEAD)
501 /* Clear software ring entries */
502 for (i = 0; i < nb_rx; i++)
503 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
508 static inline uint16_t
509 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
510 struct rte_mbuf **rx_pkts,
514 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
516 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
518 for (i = 0; i < nb_pkts; i++)
519 rx_pkts[i] = stage[i];
521 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
522 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
528 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
530 volatile union i40e_rx_desc *rxdp;
531 struct i40e_rx_entry *rxep;
533 uint16_t alloc_idx, i;
537 /* Allocate buffers in bulk */
538 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
539 (rxq->rx_free_thresh - 1));
540 rxep = &(rxq->sw_ring[alloc_idx]);
541 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
542 rxq->rx_free_thresh);
543 if (unlikely(diag != 0)) {
544 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
548 rxdp = &rxq->rx_ring[alloc_idx];
549 for (i = 0; i < rxq->rx_free_thresh; i++) {
550 if (likely(i < (rxq->rx_free_thresh - 1)))
551 /* Prefetch next mbuf */
552 rte_prefetch0(rxep[i + 1].mbuf);
555 rte_mbuf_refcnt_set(mb, 1);
557 mb->data_off = RTE_PKTMBUF_HEADROOM;
559 mb->port = rxq->port_id;
560 dma_addr = rte_cpu_to_le_64(\
561 rte_mbuf_data_iova_default(mb));
562 rxdp[i].read.hdr_addr = 0;
563 rxdp[i].read.pkt_addr = dma_addr;
566 /* Update rx tail regsiter */
568 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
570 rxq->rx_free_trigger =
571 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
572 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
573 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
578 static inline uint16_t
579 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
581 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
582 struct rte_eth_dev *dev;
588 if (rxq->rx_nb_avail)
589 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
591 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
592 rxq->rx_next_avail = 0;
593 rxq->rx_nb_avail = nb_rx;
594 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
596 if (rxq->rx_tail > rxq->rx_free_trigger) {
597 if (i40e_rx_alloc_bufs(rxq) != 0) {
600 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
601 dev->data->rx_mbuf_alloc_failed +=
604 rxq->rx_nb_avail = 0;
605 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
606 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
607 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
613 if (rxq->rx_tail >= rxq->nb_rx_desc)
616 if (rxq->rx_nb_avail)
617 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
623 i40e_recv_pkts_bulk_alloc(void *rx_queue,
624 struct rte_mbuf **rx_pkts,
627 uint16_t nb_rx = 0, n, count;
629 if (unlikely(nb_pkts == 0))
632 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
633 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
636 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
637 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
638 nb_rx = (uint16_t)(nb_rx + count);
639 nb_pkts = (uint16_t)(nb_pkts - count);
648 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
649 struct rte_mbuf __rte_unused **rx_pkts,
650 uint16_t __rte_unused nb_pkts)
654 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
657 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
659 struct i40e_rx_queue *rxq;
660 volatile union i40e_rx_desc *rx_ring;
661 volatile union i40e_rx_desc *rxdp;
662 union i40e_rx_desc rxd;
663 struct i40e_rx_entry *sw_ring;
664 struct i40e_rx_entry *rxe;
665 struct rte_eth_dev *dev;
666 struct rte_mbuf *rxm;
667 struct rte_mbuf *nmb;
671 uint16_t rx_packet_len;
672 uint16_t rx_id, nb_hold;
680 rx_id = rxq->rx_tail;
681 rx_ring = rxq->rx_ring;
682 sw_ring = rxq->sw_ring;
683 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
685 while (nb_rx < nb_pkts) {
686 rxdp = &rx_ring[rx_id];
687 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
688 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
689 >> I40E_RXD_QW1_STATUS_SHIFT;
691 /* Check the DD bit first */
692 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
695 nmb = rte_mbuf_raw_alloc(rxq->mp);
696 if (unlikely(!nmb)) {
697 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
698 dev->data->rx_mbuf_alloc_failed++;
704 rxe = &sw_ring[rx_id];
706 if (unlikely(rx_id == rxq->nb_rx_desc))
709 /* Prefetch next mbuf */
710 rte_prefetch0(sw_ring[rx_id].mbuf);
713 * When next RX descriptor is on a cache line boundary,
714 * prefetch the next 4 RX descriptors and next 8 pointers
717 if ((rx_id & 0x3) == 0) {
718 rte_prefetch0(&rx_ring[rx_id]);
719 rte_prefetch0(&sw_ring[rx_id]);
724 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
725 rxdp->read.hdr_addr = 0;
726 rxdp->read.pkt_addr = dma_addr;
728 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
729 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
731 rxm->data_off = RTE_PKTMBUF_HEADROOM;
732 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
735 rxm->pkt_len = rx_packet_len;
736 rxm->data_len = rx_packet_len;
737 rxm->port = rxq->port_id;
739 i40e_rxd_to_vlan_tci(rxm, &rxd);
740 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
741 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
743 ptype_tbl[(uint8_t)((qword1 &
744 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
745 if (pkt_flags & PKT_RX_RSS_HASH)
747 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
748 if (pkt_flags & PKT_RX_FDIR)
749 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
751 #ifdef RTE_LIBRTE_IEEE1588
752 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
754 rxm->ol_flags |= pkt_flags;
756 rx_pkts[nb_rx++] = rxm;
758 rxq->rx_tail = rx_id;
761 * If the number of free RX descriptors is greater than the RX free
762 * threshold of the queue, advance the receive tail register of queue.
763 * Update that register with the value of the last processed RX
764 * descriptor minus 1.
766 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
767 if (nb_hold > rxq->rx_free_thresh) {
768 rx_id = (uint16_t) ((rx_id == 0) ?
769 (rxq->nb_rx_desc - 1) : (rx_id - 1));
770 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
773 rxq->nb_rx_hold = nb_hold;
779 i40e_recv_scattered_pkts(void *rx_queue,
780 struct rte_mbuf **rx_pkts,
783 struct i40e_rx_queue *rxq = rx_queue;
784 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
785 volatile union i40e_rx_desc *rxdp;
786 union i40e_rx_desc rxd;
787 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
788 struct i40e_rx_entry *rxe;
789 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
790 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
791 struct rte_mbuf *nmb, *rxm;
792 uint16_t rx_id = rxq->rx_tail;
793 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
794 struct rte_eth_dev *dev;
799 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
801 while (nb_rx < nb_pkts) {
802 rxdp = &rx_ring[rx_id];
803 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
804 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
805 I40E_RXD_QW1_STATUS_SHIFT;
807 /* Check the DD bit */
808 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
811 nmb = rte_mbuf_raw_alloc(rxq->mp);
812 if (unlikely(!nmb)) {
813 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
814 dev->data->rx_mbuf_alloc_failed++;
820 rxe = &sw_ring[rx_id];
822 if (rx_id == rxq->nb_rx_desc)
825 /* Prefetch next mbuf */
826 rte_prefetch0(sw_ring[rx_id].mbuf);
829 * When next RX descriptor is on a cache line boundary,
830 * prefetch the next 4 RX descriptors and next 8 pointers
833 if ((rx_id & 0x3) == 0) {
834 rte_prefetch0(&rx_ring[rx_id]);
835 rte_prefetch0(&sw_ring[rx_id]);
841 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
843 /* Set data buffer address and data length of the mbuf */
844 rxdp->read.hdr_addr = 0;
845 rxdp->read.pkt_addr = dma_addr;
846 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
847 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
848 rxm->data_len = rx_packet_len;
849 rxm->data_off = RTE_PKTMBUF_HEADROOM;
852 * If this is the first buffer of the received packet, set the
853 * pointer to the first mbuf of the packet and initialize its
854 * context. Otherwise, update the total length and the number
855 * of segments of the current scattered packet, and update the
856 * pointer to the last mbuf of the current packet.
860 first_seg->nb_segs = 1;
861 first_seg->pkt_len = rx_packet_len;
864 (uint16_t)(first_seg->pkt_len +
866 first_seg->nb_segs++;
867 last_seg->next = rxm;
871 * If this is not the last buffer of the received packet,
872 * update the pointer to the last mbuf of the current scattered
873 * packet and continue to parse the RX ring.
875 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
881 * This is the last buffer of the received packet. If the CRC
882 * is not stripped by the hardware:
883 * - Subtract the CRC length from the total packet length.
884 * - If the last buffer only contains the whole CRC or a part
885 * of it, free the mbuf associated to the last buffer. If part
886 * of the CRC is also contained in the previous mbuf, subtract
887 * the length of that CRC part from the data length of the
891 if (unlikely(rxq->crc_len > 0)) {
892 first_seg->pkt_len -= ETHER_CRC_LEN;
893 if (rx_packet_len <= ETHER_CRC_LEN) {
894 rte_pktmbuf_free_seg(rxm);
895 first_seg->nb_segs--;
897 (uint16_t)(last_seg->data_len -
898 (ETHER_CRC_LEN - rx_packet_len));
899 last_seg->next = NULL;
901 rxm->data_len = (uint16_t)(rx_packet_len -
905 first_seg->port = rxq->port_id;
906 first_seg->ol_flags = 0;
907 i40e_rxd_to_vlan_tci(first_seg, &rxd);
908 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
909 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
910 first_seg->packet_type =
911 ptype_tbl[(uint8_t)((qword1 &
912 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
913 if (pkt_flags & PKT_RX_RSS_HASH)
914 first_seg->hash.rss =
915 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
916 if (pkt_flags & PKT_RX_FDIR)
917 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
919 #ifdef RTE_LIBRTE_IEEE1588
920 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
922 first_seg->ol_flags |= pkt_flags;
924 /* Prefetch data of first segment, if configured to do so. */
925 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
926 first_seg->data_off));
927 rx_pkts[nb_rx++] = first_seg;
931 /* Record index of the next RX descriptor to probe. */
932 rxq->rx_tail = rx_id;
933 rxq->pkt_first_seg = first_seg;
934 rxq->pkt_last_seg = last_seg;
937 * If the number of free RX descriptors is greater than the RX free
938 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
939 * register. Update the RDT with the value of the last processed RX
940 * descriptor minus 1, to guarantee that the RDT register is never
941 * equal to the RDH register, which creates a "full" ring situtation
942 * from the hardware point of view.
944 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
945 if (nb_hold > rxq->rx_free_thresh) {
946 rx_id = (uint16_t)(rx_id == 0 ?
947 (rxq->nb_rx_desc - 1) : (rx_id - 1));
948 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
951 rxq->nb_rx_hold = nb_hold;
956 /* Check if the context descriptor is needed for TX offloading */
957 static inline uint16_t
958 i40e_calc_context_desc(uint64_t flags)
960 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
965 #ifdef RTE_LIBRTE_IEEE1588
966 mask |= PKT_TX_IEEE1588_TMST;
969 return (flags & mask) ? 1 : 0;
972 /* set i40e TSO context descriptor */
973 static inline uint64_t
974 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
976 uint64_t ctx_desc = 0;
977 uint32_t cd_cmd, hdr_len, cd_tso_len;
979 if (!tx_offload.l4_len) {
980 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
985 * in case of non tunneling packet, the outer_l2_len and
986 * outer_l3_len must be 0.
988 hdr_len = tx_offload.outer_l2_len +
989 tx_offload.outer_l3_len +
994 cd_cmd = I40E_TX_CTX_DESC_TSO;
995 cd_tso_len = mbuf->pkt_len - hdr_len;
996 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
997 ((uint64_t)cd_tso_len <<
998 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
999 ((uint64_t)mbuf->tso_segsz <<
1000 I40E_TXD_CTX_QW1_MSS_SHIFT);
1006 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1008 struct i40e_tx_queue *txq;
1009 struct i40e_tx_entry *sw_ring;
1010 struct i40e_tx_entry *txe, *txn;
1011 volatile struct i40e_tx_desc *txd;
1012 volatile struct i40e_tx_desc *txr;
1013 struct rte_mbuf *tx_pkt;
1014 struct rte_mbuf *m_seg;
1015 uint32_t cd_tunneling_params;
1026 uint64_t buf_dma_addr;
1027 union i40e_tx_offload tx_offload = {0};
1030 sw_ring = txq->sw_ring;
1032 tx_id = txq->tx_tail;
1033 txe = &sw_ring[tx_id];
1035 /* Check if the descriptor ring needs to be cleaned. */
1036 if (txq->nb_tx_free < txq->tx_free_thresh)
1037 i40e_xmit_cleanup(txq);
1039 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1044 tx_pkt = *tx_pkts++;
1045 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1047 ol_flags = tx_pkt->ol_flags;
1048 tx_offload.l2_len = tx_pkt->l2_len;
1049 tx_offload.l3_len = tx_pkt->l3_len;
1050 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1051 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1052 tx_offload.l4_len = tx_pkt->l4_len;
1053 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1055 /* Calculate the number of context descriptors needed. */
1056 nb_ctx = i40e_calc_context_desc(ol_flags);
1059 * The number of descriptors that must be allocated for
1060 * a packet equals to the number of the segments of that
1061 * packet plus 1 context descriptor if needed.
1063 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1064 tx_last = (uint16_t)(tx_id + nb_used - 1);
1067 if (tx_last >= txq->nb_tx_desc)
1068 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1070 if (nb_used > txq->nb_tx_free) {
1071 if (i40e_xmit_cleanup(txq) != 0) {
1076 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1077 while (nb_used > txq->nb_tx_free) {
1078 if (i40e_xmit_cleanup(txq) != 0) {
1087 /* Descriptor based VLAN insertion */
1088 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1089 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1090 td_tag = tx_pkt->vlan_tci;
1093 /* Always enable CRC offload insertion */
1094 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1096 /* Fill in tunneling parameters if necessary */
1097 cd_tunneling_params = 0;
1098 if (ol_flags & PKT_TX_TUNNEL_MASK)
1099 i40e_parse_tunneling_params(ol_flags, tx_offload,
1100 &cd_tunneling_params);
1101 /* Enable checksum offloading */
1102 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1103 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1104 &td_offset, tx_offload);
1107 /* Setup TX context descriptor if required */
1108 volatile struct i40e_tx_context_desc *ctx_txd =
1109 (volatile struct i40e_tx_context_desc *)\
1111 uint16_t cd_l2tag2 = 0;
1112 uint64_t cd_type_cmd_tso_mss =
1113 I40E_TX_DESC_DTYPE_CONTEXT;
1115 txn = &sw_ring[txe->next_id];
1116 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1117 if (txe->mbuf != NULL) {
1118 rte_pktmbuf_free_seg(txe->mbuf);
1122 /* TSO enabled means no timestamp */
1123 if (ol_flags & PKT_TX_TCP_SEG)
1124 cd_type_cmd_tso_mss |=
1125 i40e_set_tso_ctx(tx_pkt, tx_offload);
1127 #ifdef RTE_LIBRTE_IEEE1588
1128 if (ol_flags & PKT_TX_IEEE1588_TMST)
1129 cd_type_cmd_tso_mss |=
1130 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1131 I40E_TXD_CTX_QW1_CMD_SHIFT);
1135 ctx_txd->tunneling_params =
1136 rte_cpu_to_le_32(cd_tunneling_params);
1137 if (ol_flags & PKT_TX_QINQ_PKT) {
1138 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1139 cd_type_cmd_tso_mss |=
1140 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1141 I40E_TXD_CTX_QW1_CMD_SHIFT);
1143 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1144 ctx_txd->type_cmd_tso_mss =
1145 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1147 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1148 "tunneling_params: %#x;\n"
1151 "type_cmd_tso_mss: %#"PRIx64";\n",
1153 ctx_txd->tunneling_params,
1156 ctx_txd->type_cmd_tso_mss);
1158 txe->last_id = tx_last;
1159 tx_id = txe->next_id;
1166 txn = &sw_ring[txe->next_id];
1169 rte_pktmbuf_free_seg(txe->mbuf);
1172 /* Setup TX Descriptor */
1173 slen = m_seg->data_len;
1174 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1176 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1177 "buf_dma_addr: %#"PRIx64";\n"
1182 tx_pkt, tx_id, buf_dma_addr,
1183 td_cmd, td_offset, slen, td_tag);
1185 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1186 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1187 td_offset, slen, td_tag);
1188 txe->last_id = tx_last;
1189 tx_id = txe->next_id;
1191 m_seg = m_seg->next;
1192 } while (m_seg != NULL);
1194 /* The last packet data descriptor needs End Of Packet (EOP) */
1195 td_cmd |= I40E_TX_DESC_CMD_EOP;
1196 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1197 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1199 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1200 PMD_TX_FREE_LOG(DEBUG,
1201 "Setting RS bit on TXD id="
1202 "%4u (port=%d queue=%d)",
1203 tx_last, txq->port_id, txq->queue_id);
1205 td_cmd |= I40E_TX_DESC_CMD_RS;
1207 /* Update txq RS bit counters */
1208 txq->nb_tx_used = 0;
1211 txd->cmd_type_offset_bsz |=
1212 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1213 I40E_TXD_QW1_CMD_SHIFT);
1219 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1220 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1221 (unsigned) tx_id, (unsigned) nb_tx);
1223 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1224 txq->tx_tail = tx_id;
1229 static __rte_always_inline int
1230 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1232 struct i40e_tx_entry *txep;
1235 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1236 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1237 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1240 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1242 for (i = 0; i < txq->tx_rs_thresh; i++)
1243 rte_prefetch0((txep + i)->mbuf);
1245 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1246 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1247 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1251 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1252 rte_pktmbuf_free_seg(txep->mbuf);
1257 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1258 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1259 if (txq->tx_next_dd >= txq->nb_tx_desc)
1260 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1262 return txq->tx_rs_thresh;
1265 /* Populate 4 descriptors with data from 4 mbufs */
1267 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1272 for (i = 0; i < 4; i++, txdp++, pkts++) {
1273 dma_addr = rte_mbuf_data_iova(*pkts);
1274 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1275 txdp->cmd_type_offset_bsz =
1276 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1277 (*pkts)->data_len, 0);
1281 /* Populate 1 descriptor with data from 1 mbuf */
1283 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1287 dma_addr = rte_mbuf_data_iova(*pkts);
1288 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1289 txdp->cmd_type_offset_bsz =
1290 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1291 (*pkts)->data_len, 0);
1294 /* Fill hardware descriptor ring with mbuf data */
1296 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1297 struct rte_mbuf **pkts,
1300 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1301 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1302 const int N_PER_LOOP = 4;
1303 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1304 int mainpart, leftover;
1307 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1308 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1309 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1310 for (j = 0; j < N_PER_LOOP; ++j) {
1311 (txep + i + j)->mbuf = *(pkts + i + j);
1313 tx4(txdp + i, pkts + i);
1315 if (unlikely(leftover > 0)) {
1316 for (i = 0; i < leftover; ++i) {
1317 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1318 tx1(txdp + mainpart + i, pkts + mainpart + i);
1323 static inline uint16_t
1324 tx_xmit_pkts(struct i40e_tx_queue *txq,
1325 struct rte_mbuf **tx_pkts,
1328 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1332 * Begin scanning the H/W ring for done descriptors when the number
1333 * of available descriptors drops below tx_free_thresh. For each done
1334 * descriptor, free the associated buffer.
1336 if (txq->nb_tx_free < txq->tx_free_thresh)
1337 i40e_tx_free_bufs(txq);
1339 /* Use available descriptor only */
1340 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1341 if (unlikely(!nb_pkts))
1344 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1345 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1346 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1347 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1348 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1349 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1350 I40E_TXD_QW1_CMD_SHIFT);
1351 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1355 /* Fill hardware descriptor ring with mbuf data */
1356 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1357 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1359 /* Determin if RS bit needs to be set */
1360 if (txq->tx_tail > txq->tx_next_rs) {
1361 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1362 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1363 I40E_TXD_QW1_CMD_SHIFT);
1365 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1366 if (txq->tx_next_rs >= txq->nb_tx_desc)
1367 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1370 if (txq->tx_tail >= txq->nb_tx_desc)
1373 /* Update the tx tail register */
1375 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1381 i40e_xmit_pkts_simple(void *tx_queue,
1382 struct rte_mbuf **tx_pkts,
1387 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1388 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1392 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1395 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1396 &tx_pkts[nb_tx], num);
1397 nb_tx = (uint16_t)(nb_tx + ret);
1398 nb_pkts = (uint16_t)(nb_pkts - ret);
1407 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1411 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1416 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1417 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1428 /*********************************************************************
1432 **********************************************************************/
1434 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1441 for (i = 0; i < nb_pkts; i++) {
1443 ol_flags = m->ol_flags;
1445 /* Check for m->nb_segs to not exceed the limits. */
1446 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1447 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1448 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1449 rte_errno = -EINVAL;
1452 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1453 m->tso_segsz < I40E_MIN_TSO_MSS ||
1454 m->tso_segsz > I40E_MAX_TSO_MSS ||
1455 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1456 /* MSS outside the range (256B - 9674B) are considered
1459 rte_errno = -EINVAL;
1463 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1464 rte_errno = -ENOTSUP;
1468 /* check the size of packet */
1469 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1470 rte_errno = -EINVAL;
1474 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1475 ret = rte_validate_tx_offload(m);
1481 ret = rte_net_intel_cksum_prepare(m);
1491 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1492 * application used, which assume having sequential ones. But from driver's
1493 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1494 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1495 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1496 * use queue_idx from 0 to 95 to access queues, while real queue would be
1497 * different. This function will do a queue mapping to find VSI the queue
1500 static struct i40e_vsi*
1501 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1503 /* the queue in MAIN VSI range */
1504 if (queue_idx < pf->main_vsi->nb_qps)
1505 return pf->main_vsi;
1507 queue_idx -= pf->main_vsi->nb_qps;
1509 /* queue_idx is greater than VMDQ VSIs range */
1510 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1511 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1515 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1519 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1521 /* the queue in MAIN VSI range */
1522 if (queue_idx < pf->main_vsi->nb_qps)
1525 /* It's VMDQ queues */
1526 queue_idx -= pf->main_vsi->nb_qps;
1528 if (pf->nb_cfg_vmdq_vsi)
1529 return queue_idx % pf->vmdq_nb_qps;
1531 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1532 return (uint16_t)(-1);
1537 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1539 struct i40e_rx_queue *rxq;
1541 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543 PMD_INIT_FUNC_TRACE();
1545 rxq = dev->data->rx_queues[rx_queue_id];
1547 err = i40e_alloc_rx_queue_mbufs(rxq);
1549 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1555 /* Init the RX tail regieter. */
1556 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1558 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1560 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1563 i40e_rx_queue_release_mbufs(rxq);
1564 i40e_reset_rx_queue(rxq);
1567 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1573 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1575 struct i40e_rx_queue *rxq;
1577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 rxq = dev->data->rx_queues[rx_queue_id];
1582 * rx_queue_id is queue id application refers to, while
1583 * rxq->reg_idx is the real queue index.
1585 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1587 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1591 i40e_rx_queue_release_mbufs(rxq);
1592 i40e_reset_rx_queue(rxq);
1593 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1599 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1602 struct i40e_tx_queue *txq;
1603 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605 PMD_INIT_FUNC_TRACE();
1607 txq = dev->data->tx_queues[tx_queue_id];
1610 * tx_queue_id is queue id application refers to, while
1611 * rxq->reg_idx is the real queue index.
1613 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1615 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1619 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1625 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1627 struct i40e_tx_queue *txq;
1629 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 txq = dev->data->tx_queues[tx_queue_id];
1634 * tx_queue_id is queue id application refers to, while
1635 * txq->reg_idx is the real queue index.
1637 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1639 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1644 i40e_tx_queue_release_mbufs(txq);
1645 i40e_reset_tx_queue(txq);
1646 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1652 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1654 static const uint32_t ptypes[] = {
1655 /* refers to i40e_rxd_pkt_type_mapping() */
1657 RTE_PTYPE_L2_ETHER_TIMESYNC,
1658 RTE_PTYPE_L2_ETHER_LLDP,
1659 RTE_PTYPE_L2_ETHER_ARP,
1660 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1661 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1664 RTE_PTYPE_L4_NONFRAG,
1668 RTE_PTYPE_TUNNEL_GRENAT,
1669 RTE_PTYPE_TUNNEL_IP,
1670 RTE_PTYPE_INNER_L2_ETHER,
1671 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1672 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1673 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1674 RTE_PTYPE_INNER_L4_FRAG,
1675 RTE_PTYPE_INNER_L4_ICMP,
1676 RTE_PTYPE_INNER_L4_NONFRAG,
1677 RTE_PTYPE_INNER_L4_SCTP,
1678 RTE_PTYPE_INNER_L4_TCP,
1679 RTE_PTYPE_INNER_L4_UDP,
1683 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1684 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1685 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1687 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1688 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1689 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1690 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1691 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1697 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1701 for (i = 0; i < num; i++) {
1702 if (i != idx && queues[i])
1710 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1711 struct i40e_rx_queue *rxq)
1713 struct i40e_adapter *ad =
1714 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1715 int use_def_burst_func =
1716 check_rx_burst_bulk_alloc_preconditions(rxq);
1718 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1719 RTE_PKTMBUF_HEADROOM);
1720 int use_scattered_rx =
1721 ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size);
1723 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1725 "Failed to do RX queue initialization");
1729 if (i40e_dev_first_queue(rxq->queue_id,
1730 dev->data->rx_queues,
1731 dev->data->nb_rx_queues)) {
1733 * If it is the first queue to setup,
1734 * set all flags to default and call
1735 * i40e_set_rx_function.
1737 ad->rx_bulk_alloc_allowed = true;
1738 ad->rx_vec_allowed = true;
1739 dev->data->scattered_rx = use_scattered_rx;
1740 if (use_def_burst_func)
1741 ad->rx_bulk_alloc_allowed = false;
1742 i40e_set_rx_function(dev);
1744 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1745 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1746 " number %d of queue %d isn't power of 2",
1747 rxq->nb_rx_desc, rxq->queue_id);
1751 /* check bulk alloc conflict */
1752 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1753 PMD_DRV_LOG(ERR, "Can't use default burst.");
1756 /* check scatterred conflict */
1757 if (!dev->data->scattered_rx && use_scattered_rx) {
1758 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1761 /* check vector conflict */
1762 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1763 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1771 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1774 unsigned int socket_id,
1775 const struct rte_eth_rxconf *rx_conf,
1776 struct rte_mempool *mp)
1778 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779 struct i40e_adapter *ad =
1780 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1781 struct i40e_vsi *vsi;
1782 struct i40e_pf *pf = NULL;
1783 struct i40e_vf *vf = NULL;
1784 struct i40e_rx_queue *rxq;
1785 const struct rte_memzone *rz;
1788 uint16_t reg_idx, base, bsf, tc_mapping;
1789 int q_offset, use_def_burst_func = 1;
1792 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1794 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1795 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1799 reg_idx = queue_idx;
1801 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1802 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1805 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1808 reg_idx = vsi->base_queue + q_offset;
1811 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1812 (nb_desc > I40E_MAX_RING_DESC) ||
1813 (nb_desc < I40E_MIN_RING_DESC)) {
1814 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1815 "invalid", nb_desc);
1819 /* Free memory if needed */
1820 if (dev->data->rx_queues[queue_idx]) {
1821 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1822 dev->data->rx_queues[queue_idx] = NULL;
1825 /* Allocate the rx queue data structure */
1826 rxq = rte_zmalloc_socket("i40e rx queue",
1827 sizeof(struct i40e_rx_queue),
1828 RTE_CACHE_LINE_SIZE,
1831 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1832 "rx queue data structure");
1836 rxq->nb_rx_desc = nb_desc;
1837 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1838 rxq->queue_id = queue_idx;
1839 rxq->reg_idx = reg_idx;
1840 rxq->port_id = dev->data->port_id;
1841 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1842 rxq->crc_len = ETHER_CRC_LEN;
1845 rxq->drop_en = rx_conf->rx_drop_en;
1847 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1848 rxq->offloads = offloads;
1850 /* Allocate the maximun number of RX ring hardware descriptor. */
1851 len = I40E_MAX_RING_DESC;
1854 * Allocating a little more memory because vectorized/bulk_alloc Rx
1855 * functions doesn't check boundaries each time.
1857 len += RTE_PMD_I40E_RX_MAX_BURST;
1859 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1860 I40E_DMA_MEM_ALIGN);
1862 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1863 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1865 i40e_dev_rx_queue_release(rxq);
1866 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1870 /* Zero all the descriptors in the ring. */
1871 memset(rz->addr, 0, ring_size);
1873 rxq->rx_ring_phys_addr = rz->iova;
1874 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1876 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1878 /* Allocate the software ring. */
1880 rte_zmalloc_socket("i40e rx sw ring",
1881 sizeof(struct i40e_rx_entry) * len,
1882 RTE_CACHE_LINE_SIZE,
1884 if (!rxq->sw_ring) {
1885 i40e_dev_rx_queue_release(rxq);
1886 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1890 i40e_reset_rx_queue(rxq);
1893 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1894 if (!(vsi->enabled_tc & (1 << i)))
1896 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1897 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1898 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1899 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1900 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1902 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1906 if (dev->data->dev_started) {
1907 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1908 i40e_dev_rx_queue_release(rxq);
1912 use_def_burst_func =
1913 check_rx_burst_bulk_alloc_preconditions(rxq);
1914 if (!use_def_burst_func) {
1915 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1917 "Rx Burst Bulk Alloc Preconditions are "
1918 "satisfied. Rx Burst Bulk Alloc function will be "
1919 "used on port=%d, queue=%d.",
1920 rxq->port_id, rxq->queue_id);
1921 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1924 "Rx Burst Bulk Alloc Preconditions are "
1925 "not satisfied, Scattered Rx is requested, "
1926 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1927 "not enabled on port=%d, queue=%d.",
1928 rxq->port_id, rxq->queue_id);
1929 ad->rx_bulk_alloc_allowed = false;
1933 dev->data->rx_queues[queue_idx] = rxq;
1938 i40e_dev_rx_queue_release(void *rxq)
1940 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1943 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1947 i40e_rx_queue_release_mbufs(q);
1948 rte_free(q->sw_ring);
1953 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1955 #define I40E_RXQ_SCAN_INTERVAL 4
1956 volatile union i40e_rx_desc *rxdp;
1957 struct i40e_rx_queue *rxq;
1960 rxq = dev->data->rx_queues[rx_queue_id];
1961 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1962 while ((desc < rxq->nb_rx_desc) &&
1963 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1964 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1965 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1967 * Check the DD bit of a rx descriptor of each 4 in a group,
1968 * to avoid checking too frequently and downgrading performance
1971 desc += I40E_RXQ_SCAN_INTERVAL;
1972 rxdp += I40E_RXQ_SCAN_INTERVAL;
1973 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1974 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1975 desc - rxq->nb_rx_desc]);
1982 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1984 volatile union i40e_rx_desc *rxdp;
1985 struct i40e_rx_queue *rxq = rx_queue;
1989 if (unlikely(offset >= rxq->nb_rx_desc)) {
1990 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1994 desc = rxq->rx_tail + offset;
1995 if (desc >= rxq->nb_rx_desc)
1996 desc -= rxq->nb_rx_desc;
1998 rxdp = &(rxq->rx_ring[desc]);
2000 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2001 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2002 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2008 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2010 struct i40e_rx_queue *rxq = rx_queue;
2011 volatile uint64_t *status;
2015 if (unlikely(offset >= rxq->nb_rx_desc))
2018 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2019 return RTE_ETH_RX_DESC_UNAVAIL;
2021 desc = rxq->rx_tail + offset;
2022 if (desc >= rxq->nb_rx_desc)
2023 desc -= rxq->nb_rx_desc;
2025 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2026 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2027 << I40E_RXD_QW1_STATUS_SHIFT);
2029 return RTE_ETH_RX_DESC_DONE;
2031 return RTE_ETH_RX_DESC_AVAIL;
2035 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2037 struct i40e_tx_queue *txq = tx_queue;
2038 volatile uint64_t *status;
2039 uint64_t mask, expect;
2042 if (unlikely(offset >= txq->nb_tx_desc))
2045 desc = txq->tx_tail + offset;
2046 /* go to next desc that has the RS bit */
2047 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2049 if (desc >= txq->nb_tx_desc) {
2050 desc -= txq->nb_tx_desc;
2051 if (desc >= txq->nb_tx_desc)
2052 desc -= txq->nb_tx_desc;
2055 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2056 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2057 expect = rte_cpu_to_le_64(
2058 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2059 if ((*status & mask) == expect)
2060 return RTE_ETH_TX_DESC_DONE;
2062 return RTE_ETH_TX_DESC_FULL;
2066 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2067 struct i40e_tx_queue *txq)
2069 struct i40e_adapter *ad =
2070 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2072 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2074 "Failed to do TX queue initialization");
2078 if (i40e_dev_first_queue(txq->queue_id,
2079 dev->data->tx_queues,
2080 dev->data->nb_tx_queues)) {
2082 * If it is the first queue to setup,
2083 * set all flags and call
2084 * i40e_set_tx_function.
2086 i40e_set_tx_function_flag(dev, txq);
2087 i40e_set_tx_function(dev);
2091 /* check vector conflict */
2092 if (ad->tx_vec_allowed) {
2093 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2094 i40e_txq_vec_setup(txq)) {
2095 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2099 /* check simple tx conflict */
2100 if (ad->tx_simple_allowed) {
2101 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2102 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2103 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2112 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2115 unsigned int socket_id,
2116 const struct rte_eth_txconf *tx_conf)
2118 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119 struct i40e_vsi *vsi;
2120 struct i40e_pf *pf = NULL;
2121 struct i40e_vf *vf = NULL;
2122 struct i40e_tx_queue *txq;
2123 const struct rte_memzone *tz;
2125 uint16_t tx_rs_thresh, tx_free_thresh;
2126 uint16_t reg_idx, i, base, bsf, tc_mapping;
2130 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2132 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2133 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2137 reg_idx = queue_idx;
2139 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2140 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2143 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2146 reg_idx = vsi->base_queue + q_offset;
2149 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2150 (nb_desc > I40E_MAX_RING_DESC) ||
2151 (nb_desc < I40E_MIN_RING_DESC)) {
2152 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2153 "invalid", nb_desc);
2158 * The following two parameters control the setting of the RS bit on
2159 * transmit descriptors. TX descriptors will have their RS bit set
2160 * after txq->tx_rs_thresh descriptors have been used. The TX
2161 * descriptor ring will be cleaned after txq->tx_free_thresh
2162 * descriptors are used or if the number of descriptors required to
2163 * transmit a packet is greater than the number of free TX descriptors.
2165 * The following constraints must be satisfied:
2166 * - tx_rs_thresh must be greater than 0.
2167 * - tx_rs_thresh must be less than the size of the ring minus 2.
2168 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2169 * - tx_rs_thresh must be a divisor of the ring size.
2170 * - tx_free_thresh must be greater than 0.
2171 * - tx_free_thresh must be less than the size of the ring minus 3.
2173 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2174 * race condition, hence the maximum threshold constraints. When set
2175 * to zero use default values.
2177 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2178 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2179 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2180 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2181 if (tx_rs_thresh >= (nb_desc - 2)) {
2182 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2183 "number of TX descriptors minus 2. "
2184 "(tx_rs_thresh=%u port=%d queue=%d)",
2185 (unsigned int)tx_rs_thresh,
2186 (int)dev->data->port_id,
2188 return I40E_ERR_PARAM;
2190 if (tx_free_thresh >= (nb_desc - 3)) {
2191 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2192 "number of TX descriptors minus 3. "
2193 "(tx_free_thresh=%u port=%d queue=%d)",
2194 (unsigned int)tx_free_thresh,
2195 (int)dev->data->port_id,
2197 return I40E_ERR_PARAM;
2199 if (tx_rs_thresh > tx_free_thresh) {
2200 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2201 "equal to tx_free_thresh. (tx_free_thresh=%u"
2202 " tx_rs_thresh=%u port=%d queue=%d)",
2203 (unsigned int)tx_free_thresh,
2204 (unsigned int)tx_rs_thresh,
2205 (int)dev->data->port_id,
2207 return I40E_ERR_PARAM;
2209 if ((nb_desc % tx_rs_thresh) != 0) {
2210 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2211 "number of TX descriptors. (tx_rs_thresh=%u"
2212 " port=%d queue=%d)",
2213 (unsigned int)tx_rs_thresh,
2214 (int)dev->data->port_id,
2216 return I40E_ERR_PARAM;
2218 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2219 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2220 "tx_rs_thresh is greater than 1. "
2221 "(tx_rs_thresh=%u port=%d queue=%d)",
2222 (unsigned int)tx_rs_thresh,
2223 (int)dev->data->port_id,
2225 return I40E_ERR_PARAM;
2228 /* Free memory if needed. */
2229 if (dev->data->tx_queues[queue_idx]) {
2230 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2231 dev->data->tx_queues[queue_idx] = NULL;
2234 /* Allocate the TX queue data structure. */
2235 txq = rte_zmalloc_socket("i40e tx queue",
2236 sizeof(struct i40e_tx_queue),
2237 RTE_CACHE_LINE_SIZE,
2240 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2241 "tx queue structure");
2245 /* Allocate TX hardware ring descriptors. */
2246 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2247 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2248 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2249 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2251 i40e_dev_tx_queue_release(txq);
2252 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2256 txq->nb_tx_desc = nb_desc;
2257 txq->tx_rs_thresh = tx_rs_thresh;
2258 txq->tx_free_thresh = tx_free_thresh;
2259 txq->pthresh = tx_conf->tx_thresh.pthresh;
2260 txq->hthresh = tx_conf->tx_thresh.hthresh;
2261 txq->wthresh = tx_conf->tx_thresh.wthresh;
2262 txq->queue_id = queue_idx;
2263 txq->reg_idx = reg_idx;
2264 txq->port_id = dev->data->port_id;
2265 txq->offloads = offloads;
2267 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2269 txq->tx_ring_phys_addr = tz->iova;
2270 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2272 /* Allocate software ring */
2274 rte_zmalloc_socket("i40e tx sw ring",
2275 sizeof(struct i40e_tx_entry) * nb_desc,
2276 RTE_CACHE_LINE_SIZE,
2278 if (!txq->sw_ring) {
2279 i40e_dev_tx_queue_release(txq);
2280 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2284 i40e_reset_tx_queue(txq);
2287 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2288 if (!(vsi->enabled_tc & (1 << i)))
2290 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2291 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2292 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2293 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2294 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2296 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2300 if (dev->data->dev_started) {
2301 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2302 i40e_dev_tx_queue_release(txq);
2307 * Use a simple TX queue without offloads or
2308 * multi segs if possible
2310 i40e_set_tx_function_flag(dev, txq);
2312 dev->data->tx_queues[queue_idx] = txq;
2318 i40e_dev_tx_queue_release(void *txq)
2320 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2323 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2327 i40e_tx_queue_release_mbufs(q);
2328 rte_free(q->sw_ring);
2332 const struct rte_memzone *
2333 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2335 const struct rte_memzone *mz;
2337 mz = rte_memzone_lookup(name);
2341 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2342 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2347 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2351 /* SSE Vector driver has a different way of releasing mbufs. */
2352 if (rxq->rx_using_sse) {
2353 i40e_rx_queue_release_mbufs_vec(rxq);
2357 if (!rxq->sw_ring) {
2358 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2362 for (i = 0; i < rxq->nb_rx_desc; i++) {
2363 if (rxq->sw_ring[i].mbuf) {
2364 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2365 rxq->sw_ring[i].mbuf = NULL;
2368 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2369 if (rxq->rx_nb_avail == 0)
2371 for (i = 0; i < rxq->rx_nb_avail; i++) {
2372 struct rte_mbuf *mbuf;
2374 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2375 rte_pktmbuf_free_seg(mbuf);
2377 rxq->rx_nb_avail = 0;
2378 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2382 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2388 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2392 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2393 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2394 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2396 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2397 len = rxq->nb_rx_desc;
2399 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2400 ((volatile char *)rxq->rx_ring)[i] = 0;
2402 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2403 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2404 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2407 rxq->rx_nb_avail = 0;
2408 rxq->rx_next_avail = 0;
2409 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2410 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2412 rxq->nb_rx_hold = 0;
2413 rxq->pkt_first_seg = NULL;
2414 rxq->pkt_last_seg = NULL;
2416 rxq->rxrearm_start = 0;
2417 rxq->rxrearm_nb = 0;
2421 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2423 struct rte_eth_dev *dev;
2426 dev = &rte_eth_devices[txq->port_id];
2428 if (!txq || !txq->sw_ring) {
2429 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2434 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2435 * so need to free remains more carefully.
2437 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2438 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2439 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2440 if (txq->tx_tail < i) {
2441 for (; i < txq->nb_tx_desc; i++) {
2442 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2443 txq->sw_ring[i].mbuf = NULL;
2447 for (; i < txq->tx_tail; i++) {
2448 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2449 txq->sw_ring[i].mbuf = NULL;
2452 for (i = 0; i < txq->nb_tx_desc; i++) {
2453 if (txq->sw_ring[i].mbuf) {
2454 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2455 txq->sw_ring[i].mbuf = NULL;
2462 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2464 struct i40e_tx_entry *txe;
2465 uint16_t i, prev, size;
2468 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2473 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2474 for (i = 0; i < size; i++)
2475 ((volatile char *)txq->tx_ring)[i] = 0;
2477 prev = (uint16_t)(txq->nb_tx_desc - 1);
2478 for (i = 0; i < txq->nb_tx_desc; i++) {
2479 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2481 txd->cmd_type_offset_bsz =
2482 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2485 txe[prev].next_id = i;
2489 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2490 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2493 txq->nb_tx_used = 0;
2495 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2496 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2499 /* Init the TX queue in hardware */
2501 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2503 enum i40e_status_code err = I40E_SUCCESS;
2504 struct i40e_vsi *vsi = txq->vsi;
2505 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2506 uint16_t pf_q = txq->reg_idx;
2507 struct i40e_hmc_obj_txq tx_ctx;
2510 /* clear the context structure first */
2511 memset(&tx_ctx, 0, sizeof(tx_ctx));
2512 tx_ctx.new_context = 1;
2513 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2514 tx_ctx.qlen = txq->nb_tx_desc;
2516 #ifdef RTE_LIBRTE_IEEE1588
2517 tx_ctx.timesync_ena = 1;
2519 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2520 if (vsi->type == I40E_VSI_FDIR)
2521 tx_ctx.fd_ena = TRUE;
2523 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2524 if (err != I40E_SUCCESS) {
2525 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2529 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2530 if (err != I40E_SUCCESS) {
2531 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2535 /* Now associate this queue with this PCI function */
2536 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2537 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2538 I40E_QTX_CTL_PF_INDX_MASK);
2539 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2540 I40E_WRITE_FLUSH(hw);
2542 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2548 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2550 struct i40e_rx_entry *rxe = rxq->sw_ring;
2554 for (i = 0; i < rxq->nb_rx_desc; i++) {
2555 volatile union i40e_rx_desc *rxd;
2556 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2558 if (unlikely(!mbuf)) {
2559 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2563 rte_mbuf_refcnt_set(mbuf, 1);
2565 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2567 mbuf->port = rxq->port_id;
2570 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2572 rxd = &rxq->rx_ring[i];
2573 rxd->read.pkt_addr = dma_addr;
2574 rxd->read.hdr_addr = 0;
2575 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2576 rxd->read.rsvd1 = 0;
2577 rxd->read.rsvd2 = 0;
2578 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2587 * Calculate the buffer length, and check the jumbo frame
2588 * and maximum packet length.
2591 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2593 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2594 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2595 struct rte_eth_dev_data *data = pf->dev_data;
2596 uint16_t buf_size, len;
2598 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2599 RTE_PKTMBUF_HEADROOM);
2601 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2602 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2603 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2604 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2605 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2606 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2607 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2608 rxq->hs_mode = i40e_header_split_enabled;
2610 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2612 rxq->rx_hdr_len = 0;
2613 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2614 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2615 rxq->hs_mode = i40e_header_split_none;
2619 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2620 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2621 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2622 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2623 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2624 PMD_DRV_LOG(ERR, "maximum packet length must "
2625 "be larger than %u and smaller than %u,"
2626 "as jumbo frame is enabled",
2627 (uint32_t)ETHER_MAX_LEN,
2628 (uint32_t)I40E_FRAME_SIZE_MAX);
2629 return I40E_ERR_CONFIG;
2632 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2633 rxq->max_pkt_len > ETHER_MAX_LEN) {
2634 PMD_DRV_LOG(ERR, "maximum packet length must be "
2635 "larger than %u and smaller than %u, "
2636 "as jumbo frame is disabled",
2637 (uint32_t)ETHER_MIN_LEN,
2638 (uint32_t)ETHER_MAX_LEN);
2639 return I40E_ERR_CONFIG;
2646 /* Init the RX queue in hardware */
2648 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2650 int err = I40E_SUCCESS;
2651 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2652 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2653 uint16_t pf_q = rxq->reg_idx;
2655 struct i40e_hmc_obj_rxq rx_ctx;
2657 err = i40e_rx_queue_config(rxq);
2659 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2663 /* Clear the context structure first */
2664 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2665 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2666 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2668 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2669 rx_ctx.qlen = rxq->nb_rx_desc;
2670 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2673 rx_ctx.dtype = rxq->hs_mode;
2675 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2677 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2678 rx_ctx.rxmax = rxq->max_pkt_len;
2679 rx_ctx.tphrdesc_ena = 1;
2680 rx_ctx.tphwdesc_ena = 1;
2681 rx_ctx.tphdata_ena = 1;
2682 rx_ctx.tphhead_ena = 1;
2683 rx_ctx.lrxqthresh = 2;
2684 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2686 /* showiv indicates if inner VLAN is stripped inside of tunnel
2687 * packet. When set it to 1, vlan information is stripped from
2688 * the inner header, but the hardware does not put it in the
2689 * descriptor. So set it zero by default.
2694 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2695 if (err != I40E_SUCCESS) {
2696 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2699 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2700 if (err != I40E_SUCCESS) {
2701 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2705 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2707 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2708 RTE_PKTMBUF_HEADROOM);
2710 /* Check if scattered RX needs to be used. */
2711 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2712 dev_data->scattered_rx = 1;
2715 /* Init the RX tail regieter. */
2716 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2722 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2726 PMD_INIT_FUNC_TRACE();
2728 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2729 if (!dev->data->tx_queues[i])
2731 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2732 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2735 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2736 if (!dev->data->rx_queues[i])
2738 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2739 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2744 i40e_dev_free_queues(struct rte_eth_dev *dev)
2748 PMD_INIT_FUNC_TRACE();
2750 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2751 if (!dev->data->rx_queues[i])
2753 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2754 dev->data->rx_queues[i] = NULL;
2757 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2758 if (!dev->data->tx_queues[i])
2760 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2761 dev->data->tx_queues[i] = NULL;
2765 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2766 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2768 enum i40e_status_code
2769 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2771 struct i40e_tx_queue *txq;
2772 const struct rte_memzone *tz = NULL;
2774 struct rte_eth_dev *dev;
2777 PMD_DRV_LOG(ERR, "PF is not available");
2778 return I40E_ERR_BAD_PTR;
2781 dev = pf->adapter->eth_dev;
2783 /* Allocate the TX queue data structure. */
2784 txq = rte_zmalloc_socket("i40e fdir tx queue",
2785 sizeof(struct i40e_tx_queue),
2786 RTE_CACHE_LINE_SIZE,
2789 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2790 "tx queue structure.");
2791 return I40E_ERR_NO_MEMORY;
2794 /* Allocate TX hardware ring descriptors. */
2795 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2796 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2798 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2799 I40E_FDIR_QUEUE_ID, ring_size,
2800 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2802 i40e_dev_tx_queue_release(txq);
2803 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2804 return I40E_ERR_NO_MEMORY;
2807 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2808 txq->queue_id = I40E_FDIR_QUEUE_ID;
2809 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2810 txq->vsi = pf->fdir.fdir_vsi;
2812 txq->tx_ring_phys_addr = tz->iova;
2813 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2815 * don't need to allocate software ring and reset for the fdir
2816 * program queue just set the queue has been configured.
2821 return I40E_SUCCESS;
2824 enum i40e_status_code
2825 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2827 struct i40e_rx_queue *rxq;
2828 const struct rte_memzone *rz = NULL;
2830 struct rte_eth_dev *dev;
2833 PMD_DRV_LOG(ERR, "PF is not available");
2834 return I40E_ERR_BAD_PTR;
2837 dev = pf->adapter->eth_dev;
2839 /* Allocate the RX queue data structure. */
2840 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2841 sizeof(struct i40e_rx_queue),
2842 RTE_CACHE_LINE_SIZE,
2845 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2846 "rx queue structure.");
2847 return I40E_ERR_NO_MEMORY;
2850 /* Allocate RX hardware ring descriptors. */
2851 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2852 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2854 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2855 I40E_FDIR_QUEUE_ID, ring_size,
2856 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2858 i40e_dev_rx_queue_release(rxq);
2859 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2860 return I40E_ERR_NO_MEMORY;
2863 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2864 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2865 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2866 rxq->vsi = pf->fdir.fdir_vsi;
2868 rxq->rx_ring_phys_addr = rz->iova;
2869 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2870 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2873 * Don't need to allocate software ring and reset for the fdir
2874 * rx queue, just set the queue has been configured.
2879 return I40E_SUCCESS;
2883 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2884 struct rte_eth_rxq_info *qinfo)
2886 struct i40e_rx_queue *rxq;
2888 rxq = dev->data->rx_queues[queue_id];
2890 qinfo->mp = rxq->mp;
2891 qinfo->scattered_rx = dev->data->scattered_rx;
2892 qinfo->nb_desc = rxq->nb_rx_desc;
2894 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2895 qinfo->conf.rx_drop_en = rxq->drop_en;
2896 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2897 qinfo->conf.offloads = rxq->offloads;
2901 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2902 struct rte_eth_txq_info *qinfo)
2904 struct i40e_tx_queue *txq;
2906 txq = dev->data->tx_queues[queue_id];
2908 qinfo->nb_desc = txq->nb_tx_desc;
2910 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2911 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2912 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2914 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2915 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2916 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2917 qinfo->conf.offloads = txq->offloads;
2920 static eth_rx_burst_t
2921 i40e_get_latest_rx_vec(bool scatter)
2924 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
2925 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2926 i40e_recv_pkts_vec_avx2;
2928 return scatter ? i40e_recv_scattered_pkts_vec :
2932 static eth_rx_burst_t
2933 i40e_get_recommend_rx_vec(bool scatter)
2937 * since AVX frequency can be different to base frequency, limit
2938 * use of AVX2 version to later plaforms, not all those that could
2939 * theoretically run it.
2941 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2942 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2943 i40e_recv_pkts_vec_avx2;
2945 return scatter ? i40e_recv_scattered_pkts_vec :
2949 void __attribute__((cold))
2950 i40e_set_rx_function(struct rte_eth_dev *dev)
2952 struct i40e_adapter *ad =
2953 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2954 uint16_t rx_using_sse, i;
2955 /* In order to allow Vector Rx there are a few configuration
2956 * conditions to be met and Rx Bulk Allocation should be allowed.
2958 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2959 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2960 !ad->rx_bulk_alloc_allowed) {
2961 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2962 " Vector Rx preconditions",
2963 dev->data->port_id);
2965 ad->rx_vec_allowed = false;
2967 if (ad->rx_vec_allowed) {
2968 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2969 struct i40e_rx_queue *rxq =
2970 dev->data->rx_queues[i];
2972 if (rxq && i40e_rxq_vec_setup(rxq)) {
2973 ad->rx_vec_allowed = false;
2980 if (ad->rx_vec_allowed) {
2982 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
2983 dev->data->port_id);
2984 if (ad->use_latest_vec)
2986 i40e_get_latest_rx_vec(dev->data->scattered_rx);
2989 i40e_get_recommend_rx_vec(dev->data->scattered_rx);
2990 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
2991 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2992 "satisfied. Rx Burst Bulk Alloc function "
2993 "will be used on port=%d.",
2994 dev->data->port_id);
2996 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2998 /* Simple Rx Path. */
2999 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3000 dev->data->port_id);
3001 dev->rx_pkt_burst = dev->data->scattered_rx ?
3002 i40e_recv_scattered_pkts :
3006 /* Propagate information about RX function choice through all queues. */
3007 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3009 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3010 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3011 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3012 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3014 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3015 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3018 rxq->rx_using_sse = rx_using_sse;
3023 void __attribute__((cold))
3024 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3026 struct i40e_adapter *ad =
3027 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3029 /* Use a simple Tx queue if possible (only fast free is allowed) */
3030 ad->tx_simple_allowed =
3032 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3033 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3034 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3035 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3037 if (ad->tx_vec_allowed)
3038 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3040 else if (ad->tx_simple_allowed)
3041 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3045 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3049 static eth_tx_burst_t
3050 i40e_get_latest_tx_vec(void)
3053 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3054 return i40e_xmit_pkts_vec_avx2;
3056 return i40e_xmit_pkts_vec;
3059 static eth_tx_burst_t
3060 i40e_get_recommend_tx_vec(void)
3064 * since AVX frequency can be different to base frequency, limit
3065 * use of AVX2 version to later plaforms, not all those that could
3066 * theoretically run it.
3068 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3069 return i40e_xmit_pkts_vec_avx2;
3071 return i40e_xmit_pkts_vec;
3074 void __attribute__((cold))
3075 i40e_set_tx_function(struct rte_eth_dev *dev)
3077 struct i40e_adapter *ad =
3078 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3081 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3082 if (ad->tx_vec_allowed) {
3083 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3084 struct i40e_tx_queue *txq =
3085 dev->data->tx_queues[i];
3087 if (txq && i40e_txq_vec_setup(txq)) {
3088 ad->tx_vec_allowed = false;
3095 if (ad->tx_simple_allowed) {
3096 if (ad->tx_vec_allowed) {
3097 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3098 if (ad->use_latest_vec)
3100 i40e_get_latest_tx_vec();
3103 i40e_get_recommend_tx_vec();
3105 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3106 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3108 dev->tx_pkt_prepare = NULL;
3110 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3111 dev->tx_pkt_burst = i40e_xmit_pkts;
3112 dev->tx_pkt_prepare = i40e_prep_pkts;
3116 void __attribute__((cold))
3117 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3119 struct i40e_adapter *ad =
3120 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3123 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3124 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3127 void __attribute__((cold))
3128 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3130 struct i40e_adapter *ad =
3131 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3136 ad->pctypes_tbl[i] = 0ULL;
3137 ad->flow_types_mask = 0ULL;
3138 ad->pctypes_mask = 0ULL;
3140 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3141 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3142 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3143 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3144 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3146 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3148 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3150 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3151 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3152 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3153 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3154 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3155 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3156 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3158 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3160 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3161 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3163 if (hw->mac.type == I40E_MAC_X722) {
3164 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3165 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3166 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3167 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3168 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3170 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3171 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3172 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3173 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3174 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3178 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3179 if (ad->pctypes_tbl[i])
3180 ad->flow_types_mask |= (1ULL << i);
3181 ad->pctypes_mask |= ad->pctypes_tbl[i];
3185 /* Stubs needed for linkage when CONFIG_RTE_LIBRTE_I40E_INC_VECTOR is set to 'n' */
3187 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3194 void __rte_unused *rx_queue,
3195 struct rte_mbuf __rte_unused **rx_pkts,
3196 uint16_t __rte_unused nb_pkts)
3202 i40e_recv_scattered_pkts_vec(
3203 void __rte_unused *rx_queue,
3204 struct rte_mbuf __rte_unused **rx_pkts,
3205 uint16_t __rte_unused nb_pkts)
3211 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3212 struct rte_mbuf __rte_unused **rx_pkts,
3213 uint16_t __rte_unused nb_pkts)
3219 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3220 struct rte_mbuf __rte_unused **rx_pkts,
3221 uint16_t __rte_unused nb_pkts)
3227 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3233 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3239 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3245 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3246 struct rte_mbuf __rte_unused **tx_pkts,
3247 uint16_t __rte_unused nb_pkts)
3253 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3254 struct rte_mbuf __rte_unused **tx_pkts,
3255 uint16_t __rte_unused nb_pkts)