4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define DEFAULT_TX_RS_THRESH 32
61 #define DEFAULT_TX_FREE_THRESH 32
62 #define I40E_MAX_PKT_TYPE 256
64 #define I40E_TX_MAX_BURST 32
66 #define I40E_DMA_MEM_ALIGN 4096
68 /* Base address of the HW descriptor ring should be 128B aligned. */
69 #define I40E_RING_BASE_ALIGN 128
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
80 PKT_TX_OUTER_IP_CKSUM)
82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
83 struct rte_mbuf **tx_pkts,
87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
89 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
90 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
91 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
93 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
94 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
95 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
100 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
101 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
102 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
103 mb->vlan_tci_outer = mb->vlan_tci;
104 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
105 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
106 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
107 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
109 mb->vlan_tci_outer = 0;
112 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
113 mb->vlan_tci, mb->vlan_tci_outer);
116 /* Translate the rx descriptor status to pkt flags */
117 static inline uint64_t
118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
122 /* Check if RSS_HASH */
123 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
124 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
125 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
127 /* Check if FDIR Match */
128 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
134 static inline uint64_t
135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
138 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
140 #define I40E_RX_ERR_BITS 0x3f
141 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
143 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
144 flags |= PKT_RX_IP_CKSUM_BAD;
145 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
146 flags |= PKT_RX_L4_CKSUM_BAD;
147 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
148 flags |= PKT_RX_EIP_CKSUM_BAD;
153 /* Function to check and set the ieee1588 timesync index and get the
156 #ifdef RTE_LIBRTE_IEEE1588
157 static inline uint64_t
158 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
160 uint64_t pkt_flags = 0;
161 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
162 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
163 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
165 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
166 == RTE_PTYPE_L2_ETHER_TIMESYNC)
167 pkt_flags = PKT_RX_IEEE1588_PTP;
169 pkt_flags |= PKT_RX_IEEE1588_TMST;
170 mb->timesync = tsyn & 0x03;
177 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
178 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
179 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
180 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
181 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
183 static inline uint64_t
184 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
187 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
188 uint16_t flexbh, flexbl;
190 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
191 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
192 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
193 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
194 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
195 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
198 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
200 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
201 flags |= PKT_RX_FDIR_ID;
202 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
204 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
205 flags |= PKT_RX_FDIR_FLX;
207 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
209 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
210 flags |= PKT_RX_FDIR_FLX;
214 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
215 flags |= PKT_RX_FDIR_ID;
221 i40e_parse_tunneling_params(uint64_t ol_flags,
222 union i40e_tx_offload tx_offload,
223 uint32_t *cd_tunneling)
225 /* EIPT: External (outer) IP header type */
226 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
227 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
228 else if (ol_flags & PKT_TX_OUTER_IPV4)
229 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
230 else if (ol_flags & PKT_TX_OUTER_IPV6)
231 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
233 /* EIPLEN: External (outer) IP header length, in DWords */
234 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
235 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
237 /* L4TUNT: L4 Tunneling Type */
238 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
239 case PKT_TX_TUNNEL_IPIP:
240 /* for non UDP / GRE tunneling, set to 00b */
242 case PKT_TX_TUNNEL_VXLAN:
243 case PKT_TX_TUNNEL_GENEVE:
244 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
246 case PKT_TX_TUNNEL_GRE:
247 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
250 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
254 /* L4TUNLEN: L4 Tunneling Length, in Words
256 * We depend on app to set rte_mbuf.l2_len correctly.
257 * For IP in GRE it should be set to the length of the GRE
259 * for MAC in GRE or MAC in UDP it should be set to the length
260 * of the GRE or UDP headers plus the inner MAC up to including
261 * its last Ethertype.
263 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
264 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
268 i40e_txd_enable_checksum(uint64_t ol_flags,
271 union i40e_tx_offload tx_offload)
274 if (ol_flags & PKT_TX_TUNNEL_MASK)
275 *td_offset |= (tx_offload.outer_l2_len >> 1)
276 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
278 *td_offset |= (tx_offload.l2_len >> 1)
279 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
281 /* Enable L3 checksum offloads */
282 if (ol_flags & PKT_TX_IP_CKSUM) {
283 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
284 *td_offset |= (tx_offload.l3_len >> 2)
285 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
286 } else if (ol_flags & PKT_TX_IPV4) {
287 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
288 *td_offset |= (tx_offload.l3_len >> 2)
289 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
290 } else if (ol_flags & PKT_TX_IPV6) {
291 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
292 *td_offset |= (tx_offload.l3_len >> 2)
293 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
296 if (ol_flags & PKT_TX_TCP_SEG) {
297 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
298 *td_offset |= (tx_offload.l4_len >> 2)
299 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
303 /* Enable L4 checksum offloads */
304 switch (ol_flags & PKT_TX_L4_MASK) {
305 case PKT_TX_TCP_CKSUM:
306 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
307 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
308 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
310 case PKT_TX_SCTP_CKSUM:
311 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
312 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
313 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
315 case PKT_TX_UDP_CKSUM:
316 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
317 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
318 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
325 /* Construct the tx flags */
326 static inline uint64_t
327 i40e_build_ctob(uint32_t td_cmd,
332 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
333 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
334 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
335 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
336 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
340 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
342 struct i40e_tx_entry *sw_ring = txq->sw_ring;
343 volatile struct i40e_tx_desc *txd = txq->tx_ring;
344 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
345 uint16_t nb_tx_desc = txq->nb_tx_desc;
346 uint16_t desc_to_clean_to;
347 uint16_t nb_tx_to_clean;
349 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
350 if (desc_to_clean_to >= nb_tx_desc)
351 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
353 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
354 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
355 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
356 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
357 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
358 "(port=%d queue=%d)", desc_to_clean_to,
359 txq->port_id, txq->queue_id);
363 if (last_desc_cleaned > desc_to_clean_to)
364 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
367 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
370 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
372 txq->last_desc_cleaned = desc_to_clean_to;
373 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
379 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
380 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
382 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
387 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
388 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
389 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
390 "rxq->rx_free_thresh=%d, "
391 "RTE_PMD_I40E_RX_MAX_BURST=%d",
392 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
394 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
395 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
396 "rxq->rx_free_thresh=%d, "
397 "rxq->nb_rx_desc=%d",
398 rxq->rx_free_thresh, rxq->nb_rx_desc);
400 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
401 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
402 "rxq->nb_rx_desc=%d, "
403 "rxq->rx_free_thresh=%d",
404 rxq->nb_rx_desc, rxq->rx_free_thresh);
406 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
407 RTE_PMD_I40E_RX_MAX_BURST))) {
408 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
409 "rxq->nb_rx_desc=%d, "
410 "I40E_MAX_RING_DESC=%d, "
411 "RTE_PMD_I40E_RX_MAX_BURST=%d",
412 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
413 RTE_PMD_I40E_RX_MAX_BURST);
423 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
424 #define I40E_LOOK_AHEAD 8
425 #if (I40E_LOOK_AHEAD != 8)
426 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
429 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
431 volatile union i40e_rx_desc *rxdp;
432 struct i40e_rx_entry *rxep;
437 int32_t s[I40E_LOOK_AHEAD], nb_dd;
438 int32_t i, j, nb_rx = 0;
441 rxdp = &rxq->rx_ring[rxq->rx_tail];
442 rxep = &rxq->sw_ring[rxq->rx_tail];
444 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
445 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
446 I40E_RXD_QW1_STATUS_SHIFT;
448 /* Make sure there is at least 1 packet to receive */
449 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
453 * Scan LOOK_AHEAD descriptors at a time to determine which
454 * descriptors reference packets that are ready to be received.
456 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
457 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
458 /* Read desc statuses backwards to avoid race condition */
459 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
460 qword1 = rte_le_to_cpu_64(\
461 rxdp[j].wb.qword1.status_error_len);
462 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
463 I40E_RXD_QW1_STATUS_SHIFT;
468 /* Compute how many status bits were set */
469 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
470 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
474 /* Translate descriptor info to mbuf parameters */
475 for (j = 0; j < nb_dd; j++) {
477 qword1 = rte_le_to_cpu_64(\
478 rxdp[j].wb.qword1.status_error_len);
479 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
480 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
481 mb->data_len = pkt_len;
482 mb->pkt_len = pkt_len;
484 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
485 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
486 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
488 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
489 I40E_RXD_QW1_PTYPE_MASK) >>
490 I40E_RXD_QW1_PTYPE_SHIFT));
491 if (pkt_flags & PKT_RX_RSS_HASH)
492 mb->hash.rss = rte_le_to_cpu_32(\
493 rxdp[j].wb.qword0.hi_dword.rss);
494 if (pkt_flags & PKT_RX_FDIR)
495 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
497 #ifdef RTE_LIBRTE_IEEE1588
498 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
500 mb->ol_flags |= pkt_flags;
504 for (j = 0; j < I40E_LOOK_AHEAD; j++)
505 rxq->rx_stage[i + j] = rxep[j].mbuf;
507 if (nb_dd != I40E_LOOK_AHEAD)
511 /* Clear software ring entries */
512 for (i = 0; i < nb_rx; i++)
513 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
518 static inline uint16_t
519 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
520 struct rte_mbuf **rx_pkts,
524 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
526 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
528 for (i = 0; i < nb_pkts; i++)
529 rx_pkts[i] = stage[i];
531 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
532 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
538 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
540 volatile union i40e_rx_desc *rxdp;
541 struct i40e_rx_entry *rxep;
543 uint16_t alloc_idx, i;
547 /* Allocate buffers in bulk */
548 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
549 (rxq->rx_free_thresh - 1));
550 rxep = &(rxq->sw_ring[alloc_idx]);
551 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
552 rxq->rx_free_thresh);
553 if (unlikely(diag != 0)) {
554 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
558 rxdp = &rxq->rx_ring[alloc_idx];
559 for (i = 0; i < rxq->rx_free_thresh; i++) {
560 if (likely(i < (rxq->rx_free_thresh - 1)))
561 /* Prefetch next mbuf */
562 rte_prefetch0(rxep[i + 1].mbuf);
565 rte_mbuf_refcnt_set(mb, 1);
567 mb->data_off = RTE_PKTMBUF_HEADROOM;
569 mb->port = rxq->port_id;
570 dma_addr = rte_cpu_to_le_64(\
571 rte_mbuf_data_dma_addr_default(mb));
572 rxdp[i].read.hdr_addr = 0;
573 rxdp[i].read.pkt_addr = dma_addr;
576 /* Update rx tail regsiter */
578 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
580 rxq->rx_free_trigger =
581 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
582 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
583 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
588 static inline uint16_t
589 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
591 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
597 if (rxq->rx_nb_avail)
598 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
600 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
601 rxq->rx_next_avail = 0;
602 rxq->rx_nb_avail = nb_rx;
603 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
605 if (rxq->rx_tail > rxq->rx_free_trigger) {
606 if (i40e_rx_alloc_bufs(rxq) != 0) {
609 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
610 "port_id=%u, queue_id=%u",
611 rxq->port_id, rxq->queue_id);
612 rxq->rx_nb_avail = 0;
613 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
614 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
615 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
621 if (rxq->rx_tail >= rxq->nb_rx_desc)
624 if (rxq->rx_nb_avail)
625 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
631 i40e_recv_pkts_bulk_alloc(void *rx_queue,
632 struct rte_mbuf **rx_pkts,
635 uint16_t nb_rx = 0, n, count;
637 if (unlikely(nb_pkts == 0))
640 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
641 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
644 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
645 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
646 nb_rx = (uint16_t)(nb_rx + count);
647 nb_pkts = (uint16_t)(nb_pkts - count);
656 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
657 struct rte_mbuf __rte_unused **rx_pkts,
658 uint16_t __rte_unused nb_pkts)
662 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
665 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
667 struct i40e_rx_queue *rxq;
668 volatile union i40e_rx_desc *rx_ring;
669 volatile union i40e_rx_desc *rxdp;
670 union i40e_rx_desc rxd;
671 struct i40e_rx_entry *sw_ring;
672 struct i40e_rx_entry *rxe;
673 struct rte_mbuf *rxm;
674 struct rte_mbuf *nmb;
678 uint16_t rx_packet_len;
679 uint16_t rx_id, nb_hold;
686 rx_id = rxq->rx_tail;
687 rx_ring = rxq->rx_ring;
688 sw_ring = rxq->sw_ring;
690 while (nb_rx < nb_pkts) {
691 rxdp = &rx_ring[rx_id];
692 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
693 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
694 >> I40E_RXD_QW1_STATUS_SHIFT;
696 /* Check the DD bit first */
697 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
700 nmb = rte_mbuf_raw_alloc(rxq->mp);
706 rxe = &sw_ring[rx_id];
708 if (unlikely(rx_id == rxq->nb_rx_desc))
711 /* Prefetch next mbuf */
712 rte_prefetch0(sw_ring[rx_id].mbuf);
715 * When next RX descriptor is on a cache line boundary,
716 * prefetch the next 4 RX descriptors and next 8 pointers
719 if ((rx_id & 0x3) == 0) {
720 rte_prefetch0(&rx_ring[rx_id]);
721 rte_prefetch0(&sw_ring[rx_id]);
726 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
727 rxdp->read.hdr_addr = 0;
728 rxdp->read.pkt_addr = dma_addr;
730 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
731 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
733 rxm->data_off = RTE_PKTMBUF_HEADROOM;
734 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
737 rxm->pkt_len = rx_packet_len;
738 rxm->data_len = rx_packet_len;
739 rxm->port = rxq->port_id;
741 i40e_rxd_to_vlan_tci(rxm, &rxd);
742 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
743 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
745 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
746 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
747 if (pkt_flags & PKT_RX_RSS_HASH)
749 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
750 if (pkt_flags & PKT_RX_FDIR)
751 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
753 #ifdef RTE_LIBRTE_IEEE1588
754 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
756 rxm->ol_flags |= pkt_flags;
758 rx_pkts[nb_rx++] = rxm;
760 rxq->rx_tail = rx_id;
763 * If the number of free RX descriptors is greater than the RX free
764 * threshold of the queue, advance the receive tail register of queue.
765 * Update that register with the value of the last processed RX
766 * descriptor minus 1.
768 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
769 if (nb_hold > rxq->rx_free_thresh) {
770 rx_id = (uint16_t) ((rx_id == 0) ?
771 (rxq->nb_rx_desc - 1) : (rx_id - 1));
772 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
775 rxq->nb_rx_hold = nb_hold;
781 i40e_recv_scattered_pkts(void *rx_queue,
782 struct rte_mbuf **rx_pkts,
785 struct i40e_rx_queue *rxq = rx_queue;
786 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
787 volatile union i40e_rx_desc *rxdp;
788 union i40e_rx_desc rxd;
789 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
790 struct i40e_rx_entry *rxe;
791 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
792 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
793 struct rte_mbuf *nmb, *rxm;
794 uint16_t rx_id = rxq->rx_tail;
795 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
801 while (nb_rx < nb_pkts) {
802 rxdp = &rx_ring[rx_id];
803 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
804 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
805 I40E_RXD_QW1_STATUS_SHIFT;
807 /* Check the DD bit */
808 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
811 nmb = rte_mbuf_raw_alloc(rxq->mp);
816 rxe = &sw_ring[rx_id];
818 if (rx_id == rxq->nb_rx_desc)
821 /* Prefetch next mbuf */
822 rte_prefetch0(sw_ring[rx_id].mbuf);
825 * When next RX descriptor is on a cache line boundary,
826 * prefetch the next 4 RX descriptors and next 8 pointers
829 if ((rx_id & 0x3) == 0) {
830 rte_prefetch0(&rx_ring[rx_id]);
831 rte_prefetch0(&sw_ring[rx_id]);
837 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
839 /* Set data buffer address and data length of the mbuf */
840 rxdp->read.hdr_addr = 0;
841 rxdp->read.pkt_addr = dma_addr;
842 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
843 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
844 rxm->data_len = rx_packet_len;
845 rxm->data_off = RTE_PKTMBUF_HEADROOM;
848 * If this is the first buffer of the received packet, set the
849 * pointer to the first mbuf of the packet and initialize its
850 * context. Otherwise, update the total length and the number
851 * of segments of the current scattered packet, and update the
852 * pointer to the last mbuf of the current packet.
856 first_seg->nb_segs = 1;
857 first_seg->pkt_len = rx_packet_len;
860 (uint16_t)(first_seg->pkt_len +
862 first_seg->nb_segs++;
863 last_seg->next = rxm;
867 * If this is not the last buffer of the received packet,
868 * update the pointer to the last mbuf of the current scattered
869 * packet and continue to parse the RX ring.
871 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
877 * This is the last buffer of the received packet. If the CRC
878 * is not stripped by the hardware:
879 * - Subtract the CRC length from the total packet length.
880 * - If the last buffer only contains the whole CRC or a part
881 * of it, free the mbuf associated to the last buffer. If part
882 * of the CRC is also contained in the previous mbuf, subtract
883 * the length of that CRC part from the data length of the
887 if (unlikely(rxq->crc_len > 0)) {
888 first_seg->pkt_len -= ETHER_CRC_LEN;
889 if (rx_packet_len <= ETHER_CRC_LEN) {
890 rte_pktmbuf_free_seg(rxm);
891 first_seg->nb_segs--;
893 (uint16_t)(last_seg->data_len -
894 (ETHER_CRC_LEN - rx_packet_len));
895 last_seg->next = NULL;
897 rxm->data_len = (uint16_t)(rx_packet_len -
901 first_seg->port = rxq->port_id;
902 first_seg->ol_flags = 0;
903 i40e_rxd_to_vlan_tci(first_seg, &rxd);
904 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
905 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
906 first_seg->packet_type =
907 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
908 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
909 if (pkt_flags & PKT_RX_RSS_HASH)
910 first_seg->hash.rss =
911 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
912 if (pkt_flags & PKT_RX_FDIR)
913 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
915 #ifdef RTE_LIBRTE_IEEE1588
916 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
918 first_seg->ol_flags |= pkt_flags;
920 /* Prefetch data of first segment, if configured to do so. */
921 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
922 first_seg->data_off));
923 rx_pkts[nb_rx++] = first_seg;
927 /* Record index of the next RX descriptor to probe. */
928 rxq->rx_tail = rx_id;
929 rxq->pkt_first_seg = first_seg;
930 rxq->pkt_last_seg = last_seg;
933 * If the number of free RX descriptors is greater than the RX free
934 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
935 * register. Update the RDT with the value of the last processed RX
936 * descriptor minus 1, to guarantee that the RDT register is never
937 * equal to the RDH register, which creates a "full" ring situtation
938 * from the hardware point of view.
940 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
941 if (nb_hold > rxq->rx_free_thresh) {
942 rx_id = (uint16_t)(rx_id == 0 ?
943 (rxq->nb_rx_desc - 1) : (rx_id - 1));
944 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
947 rxq->nb_rx_hold = nb_hold;
952 /* Check if the context descriptor is needed for TX offloading */
953 static inline uint16_t
954 i40e_calc_context_desc(uint64_t flags)
956 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
961 #ifdef RTE_LIBRTE_IEEE1588
962 mask |= PKT_TX_IEEE1588_TMST;
965 return (flags & mask) ? 1 : 0;
968 /* set i40e TSO context descriptor */
969 static inline uint64_t
970 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
972 uint64_t ctx_desc = 0;
973 uint32_t cd_cmd, hdr_len, cd_tso_len;
975 if (!tx_offload.l4_len) {
976 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
981 * in case of non tunneling packet, the outer_l2_len and
982 * outer_l3_len must be 0.
984 hdr_len = tx_offload.outer_l2_len +
985 tx_offload.outer_l3_len +
990 cd_cmd = I40E_TX_CTX_DESC_TSO;
991 cd_tso_len = mbuf->pkt_len - hdr_len;
992 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
993 ((uint64_t)cd_tso_len <<
994 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
995 ((uint64_t)mbuf->tso_segsz <<
996 I40E_TXD_CTX_QW1_MSS_SHIFT);
1002 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1004 struct i40e_tx_queue *txq;
1005 struct i40e_tx_entry *sw_ring;
1006 struct i40e_tx_entry *txe, *txn;
1007 volatile struct i40e_tx_desc *txd;
1008 volatile struct i40e_tx_desc *txr;
1009 struct rte_mbuf *tx_pkt;
1010 struct rte_mbuf *m_seg;
1011 uint32_t cd_tunneling_params;
1023 uint64_t buf_dma_addr;
1024 union i40e_tx_offload tx_offload = {0};
1027 sw_ring = txq->sw_ring;
1029 tx_id = txq->tx_tail;
1030 txe = &sw_ring[tx_id];
1032 /* Check if the descriptor ring needs to be cleaned. */
1033 if (txq->nb_tx_free < txq->tx_free_thresh)
1034 i40e_xmit_cleanup(txq);
1036 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1042 tx_pkt = *tx_pkts++;
1043 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1045 ol_flags = tx_pkt->ol_flags;
1046 tx_offload.l2_len = tx_pkt->l2_len;
1047 tx_offload.l3_len = tx_pkt->l3_len;
1048 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1049 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1050 tx_offload.l4_len = tx_pkt->l4_len;
1051 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1053 /* Calculate the number of context descriptors needed. */
1054 nb_ctx = i40e_calc_context_desc(ol_flags);
1057 * The number of descriptors that must be allocated for
1058 * a packet equals to the number of the segments of that
1059 * packet plus 1 context descriptor if needed.
1061 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1062 tx_last = (uint16_t)(tx_id + nb_used - 1);
1065 if (tx_last >= txq->nb_tx_desc)
1066 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1068 if (nb_used > txq->nb_tx_free) {
1069 if (i40e_xmit_cleanup(txq) != 0) {
1074 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1075 while (nb_used > txq->nb_tx_free) {
1076 if (i40e_xmit_cleanup(txq) != 0) {
1085 /* Descriptor based VLAN insertion */
1086 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1087 tx_flags |= tx_pkt->vlan_tci <<
1088 I40E_TX_FLAG_L2TAG1_SHIFT;
1089 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1090 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1091 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1092 I40E_TX_FLAG_L2TAG1_SHIFT;
1095 /* Always enable CRC offload insertion */
1096 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1098 /* Fill in tunneling parameters if necessary */
1099 cd_tunneling_params = 0;
1100 if (ol_flags & PKT_TX_TUNNEL_MASK)
1101 i40e_parse_tunneling_params(ol_flags, tx_offload,
1102 &cd_tunneling_params);
1103 /* Enable checksum offloading */
1104 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1105 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1106 &td_offset, tx_offload);
1109 /* Setup TX context descriptor if required */
1110 volatile struct i40e_tx_context_desc *ctx_txd =
1111 (volatile struct i40e_tx_context_desc *)\
1113 uint16_t cd_l2tag2 = 0;
1114 uint64_t cd_type_cmd_tso_mss =
1115 I40E_TX_DESC_DTYPE_CONTEXT;
1117 txn = &sw_ring[txe->next_id];
1118 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1119 if (txe->mbuf != NULL) {
1120 rte_pktmbuf_free_seg(txe->mbuf);
1124 /* TSO enabled means no timestamp */
1125 if (ol_flags & PKT_TX_TCP_SEG)
1126 cd_type_cmd_tso_mss |=
1127 i40e_set_tso_ctx(tx_pkt, tx_offload);
1129 #ifdef RTE_LIBRTE_IEEE1588
1130 if (ol_flags & PKT_TX_IEEE1588_TMST)
1131 cd_type_cmd_tso_mss |=
1132 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1133 I40E_TXD_CTX_QW1_CMD_SHIFT);
1137 ctx_txd->tunneling_params =
1138 rte_cpu_to_le_32(cd_tunneling_params);
1139 if (ol_flags & PKT_TX_QINQ_PKT) {
1140 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1141 cd_type_cmd_tso_mss |=
1142 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1143 I40E_TXD_CTX_QW1_CMD_SHIFT);
1145 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1146 ctx_txd->type_cmd_tso_mss =
1147 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1149 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1150 "tunneling_params: %#x;\n"
1153 "type_cmd_tso_mss: %#"PRIx64";\n",
1155 ctx_txd->tunneling_params,
1158 ctx_txd->type_cmd_tso_mss);
1160 txe->last_id = tx_last;
1161 tx_id = txe->next_id;
1168 txn = &sw_ring[txe->next_id];
1171 rte_pktmbuf_free_seg(txe->mbuf);
1174 /* Setup TX Descriptor */
1175 slen = m_seg->data_len;
1176 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1178 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1179 "buf_dma_addr: %#"PRIx64";\n"
1184 tx_pkt, tx_id, buf_dma_addr,
1185 td_cmd, td_offset, slen, td_tag);
1187 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1188 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1189 td_offset, slen, td_tag);
1190 txe->last_id = tx_last;
1191 tx_id = txe->next_id;
1193 m_seg = m_seg->next;
1194 } while (m_seg != NULL);
1196 /* The last packet data descriptor needs End Of Packet (EOP) */
1197 td_cmd |= I40E_TX_DESC_CMD_EOP;
1198 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1199 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1201 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1202 PMD_TX_FREE_LOG(DEBUG,
1203 "Setting RS bit on TXD id="
1204 "%4u (port=%d queue=%d)",
1205 tx_last, txq->port_id, txq->queue_id);
1207 td_cmd |= I40E_TX_DESC_CMD_RS;
1209 /* Update txq RS bit counters */
1210 txq->nb_tx_used = 0;
1213 txd->cmd_type_offset_bsz |=
1214 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1215 I40E_TXD_QW1_CMD_SHIFT);
1221 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1222 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1223 (unsigned) tx_id, (unsigned) nb_tx);
1225 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1226 txq->tx_tail = tx_id;
1231 static inline int __attribute__((always_inline))
1232 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1234 struct i40e_tx_entry *txep;
1237 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1238 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1239 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1242 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1244 for (i = 0; i < txq->tx_rs_thresh; i++)
1245 rte_prefetch0((txep + i)->mbuf);
1247 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1248 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1249 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1253 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1254 rte_pktmbuf_free_seg(txep->mbuf);
1259 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1260 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1261 if (txq->tx_next_dd >= txq->nb_tx_desc)
1262 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1264 return txq->tx_rs_thresh;
1267 /* Populate 4 descriptors with data from 4 mbufs */
1269 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1274 for (i = 0; i < 4; i++, txdp++, pkts++) {
1275 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1276 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1277 txdp->cmd_type_offset_bsz =
1278 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1279 (*pkts)->data_len, 0);
1283 /* Populate 1 descriptor with data from 1 mbuf */
1285 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1289 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1290 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1291 txdp->cmd_type_offset_bsz =
1292 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1293 (*pkts)->data_len, 0);
1296 /* Fill hardware descriptor ring with mbuf data */
1298 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1299 struct rte_mbuf **pkts,
1302 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1303 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1304 const int N_PER_LOOP = 4;
1305 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1306 int mainpart, leftover;
1309 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1310 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1311 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1312 for (j = 0; j < N_PER_LOOP; ++j) {
1313 (txep + i + j)->mbuf = *(pkts + i + j);
1315 tx4(txdp + i, pkts + i);
1317 if (unlikely(leftover > 0)) {
1318 for (i = 0; i < leftover; ++i) {
1319 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1320 tx1(txdp + mainpart + i, pkts + mainpart + i);
1325 static inline uint16_t
1326 tx_xmit_pkts(struct i40e_tx_queue *txq,
1327 struct rte_mbuf **tx_pkts,
1330 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1334 * Begin scanning the H/W ring for done descriptors when the number
1335 * of available descriptors drops below tx_free_thresh. For each done
1336 * descriptor, free the associated buffer.
1338 if (txq->nb_tx_free < txq->tx_free_thresh)
1339 i40e_tx_free_bufs(txq);
1341 /* Use available descriptor only */
1342 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1343 if (unlikely(!nb_pkts))
1346 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1347 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1348 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1349 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1350 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1351 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1352 I40E_TXD_QW1_CMD_SHIFT);
1353 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1357 /* Fill hardware descriptor ring with mbuf data */
1358 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1359 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1361 /* Determin if RS bit needs to be set */
1362 if (txq->tx_tail > txq->tx_next_rs) {
1363 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1364 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1365 I40E_TXD_QW1_CMD_SHIFT);
1367 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1368 if (txq->tx_next_rs >= txq->nb_tx_desc)
1369 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1372 if (txq->tx_tail >= txq->nb_tx_desc)
1375 /* Update the tx tail register */
1377 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1383 i40e_xmit_pkts_simple(void *tx_queue,
1384 struct rte_mbuf **tx_pkts,
1389 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1390 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1394 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1397 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1398 &tx_pkts[nb_tx], num);
1399 nb_tx = (uint16_t)(nb_tx + ret);
1400 nb_pkts = (uint16_t)(nb_pkts - ret);
1409 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1410 * application used, which assume having sequential ones. But from driver's
1411 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1412 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1413 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1414 * use queue_idx from 0 to 95 to access queues, while real queue would be
1415 * different. This function will do a queue mapping to find VSI the queue
1418 static struct i40e_vsi*
1419 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1421 /* the queue in MAIN VSI range */
1422 if (queue_idx < pf->main_vsi->nb_qps)
1423 return pf->main_vsi;
1425 queue_idx -= pf->main_vsi->nb_qps;
1427 /* queue_idx is greater than VMDQ VSIs range */
1428 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1429 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1433 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1437 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1439 /* the queue in MAIN VSI range */
1440 if (queue_idx < pf->main_vsi->nb_qps)
1443 /* It's VMDQ queues */
1444 queue_idx -= pf->main_vsi->nb_qps;
1446 if (pf->nb_cfg_vmdq_vsi)
1447 return queue_idx % pf->vmdq_nb_qps;
1449 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1450 return (uint16_t)(-1);
1455 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1457 struct i40e_rx_queue *rxq;
1459 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 PMD_INIT_FUNC_TRACE();
1463 if (rx_queue_id < dev->data->nb_rx_queues) {
1464 rxq = dev->data->rx_queues[rx_queue_id];
1466 err = i40e_alloc_rx_queue_mbufs(rxq);
1468 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1474 /* Init the RX tail regieter. */
1475 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1477 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1480 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1483 i40e_rx_queue_release_mbufs(rxq);
1484 i40e_reset_rx_queue(rxq);
1486 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1493 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1495 struct i40e_rx_queue *rxq;
1497 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499 if (rx_queue_id < dev->data->nb_rx_queues) {
1500 rxq = dev->data->rx_queues[rx_queue_id];
1503 * rx_queue_id is queue id aplication refers to, while
1504 * rxq->reg_idx is the real queue index.
1506 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1509 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1513 i40e_rx_queue_release_mbufs(rxq);
1514 i40e_reset_rx_queue(rxq);
1515 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1522 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1525 struct i40e_tx_queue *txq;
1526 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1528 PMD_INIT_FUNC_TRACE();
1530 if (tx_queue_id < dev->data->nb_tx_queues) {
1531 txq = dev->data->tx_queues[tx_queue_id];
1534 * tx_queue_id is queue id aplication refers to, while
1535 * rxq->reg_idx is the real queue index.
1537 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1539 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1542 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1549 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1551 struct i40e_tx_queue *txq;
1553 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 if (tx_queue_id < dev->data->nb_tx_queues) {
1556 txq = dev->data->tx_queues[tx_queue_id];
1559 * tx_queue_id is queue id aplication refers to, while
1560 * txq->reg_idx is the real queue index.
1562 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1565 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1570 i40e_tx_queue_release_mbufs(txq);
1571 i40e_reset_tx_queue(txq);
1572 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1579 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1581 static const uint32_t ptypes[] = {
1582 /* refers to i40e_rxd_pkt_type_mapping() */
1584 RTE_PTYPE_L2_ETHER_TIMESYNC,
1585 RTE_PTYPE_L2_ETHER_LLDP,
1586 RTE_PTYPE_L2_ETHER_ARP,
1587 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1588 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1591 RTE_PTYPE_L4_NONFRAG,
1595 RTE_PTYPE_TUNNEL_GRENAT,
1596 RTE_PTYPE_TUNNEL_IP,
1597 RTE_PTYPE_INNER_L2_ETHER,
1598 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1599 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1600 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1601 RTE_PTYPE_INNER_L4_FRAG,
1602 RTE_PTYPE_INNER_L4_ICMP,
1603 RTE_PTYPE_INNER_L4_NONFRAG,
1604 RTE_PTYPE_INNER_L4_SCTP,
1605 RTE_PTYPE_INNER_L4_TCP,
1606 RTE_PTYPE_INNER_L4_UDP,
1610 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1611 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1612 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1614 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1615 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1616 dev->rx_pkt_burst == i40e_recv_pkts_vec)
1622 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1625 unsigned int socket_id,
1626 const struct rte_eth_rxconf *rx_conf,
1627 struct rte_mempool *mp)
1629 struct i40e_vsi *vsi;
1630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1632 struct i40e_adapter *ad =
1633 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1634 struct i40e_rx_queue *rxq;
1635 const struct rte_memzone *rz;
1638 uint16_t base, bsf, tc_mapping;
1639 int use_def_burst_func = 1;
1641 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1642 struct i40e_vf *vf =
1643 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1646 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1649 PMD_DRV_LOG(ERR, "VSI not available or queue "
1650 "index exceeds the maximum");
1651 return I40E_ERR_PARAM;
1653 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1654 (nb_desc > I40E_MAX_RING_DESC) ||
1655 (nb_desc < I40E_MIN_RING_DESC)) {
1656 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1657 "invalid", nb_desc);
1658 return I40E_ERR_PARAM;
1661 /* Free memory if needed */
1662 if (dev->data->rx_queues[queue_idx]) {
1663 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1664 dev->data->rx_queues[queue_idx] = NULL;
1667 /* Allocate the rx queue data structure */
1668 rxq = rte_zmalloc_socket("i40e rx queue",
1669 sizeof(struct i40e_rx_queue),
1670 RTE_CACHE_LINE_SIZE,
1673 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1674 "rx queue data structure");
1678 rxq->nb_rx_desc = nb_desc;
1679 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1680 rxq->queue_id = queue_idx;
1681 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1682 rxq->reg_idx = queue_idx;
1683 else /* PF device */
1684 rxq->reg_idx = vsi->base_queue +
1685 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1687 rxq->port_id = dev->data->port_id;
1688 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1690 rxq->drop_en = rx_conf->rx_drop_en;
1692 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1694 /* Allocate the maximun number of RX ring hardware descriptor. */
1695 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1696 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1697 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1698 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1700 i40e_dev_rx_queue_release(rxq);
1701 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1705 /* Zero all the descriptors in the ring. */
1706 memset(rz->addr, 0, ring_size);
1708 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1709 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1711 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1712 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1717 /* Allocate the software ring. */
1719 rte_zmalloc_socket("i40e rx sw ring",
1720 sizeof(struct i40e_rx_entry) * len,
1721 RTE_CACHE_LINE_SIZE,
1723 if (!rxq->sw_ring) {
1724 i40e_dev_rx_queue_release(rxq);
1725 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1729 i40e_reset_rx_queue(rxq);
1731 dev->data->rx_queues[queue_idx] = rxq;
1733 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1735 if (!use_def_burst_func) {
1736 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1737 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1738 "satisfied. Rx Burst Bulk Alloc function will be "
1739 "used on port=%d, queue=%d.",
1740 rxq->port_id, rxq->queue_id);
1741 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1743 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1744 "not satisfied, Scattered Rx is requested, "
1745 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1746 "not enabled on port=%d, queue=%d.",
1747 rxq->port_id, rxq->queue_id);
1748 ad->rx_bulk_alloc_allowed = false;
1751 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1752 if (!(vsi->enabled_tc & (1 << i)))
1754 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1755 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1756 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1757 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1758 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1760 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1768 i40e_dev_rx_queue_release(void *rxq)
1770 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1773 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1777 i40e_rx_queue_release_mbufs(q);
1778 rte_free(q->sw_ring);
1783 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1785 #define I40E_RXQ_SCAN_INTERVAL 4
1786 volatile union i40e_rx_desc *rxdp;
1787 struct i40e_rx_queue *rxq;
1790 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1791 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1795 rxq = dev->data->rx_queues[rx_queue_id];
1796 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1797 while ((desc < rxq->nb_rx_desc) &&
1798 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1799 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1800 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1802 * Check the DD bit of a rx descriptor of each 4 in a group,
1803 * to avoid checking too frequently and downgrading performance
1806 desc += I40E_RXQ_SCAN_INTERVAL;
1807 rxdp += I40E_RXQ_SCAN_INTERVAL;
1808 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1809 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1810 desc - rxq->nb_rx_desc]);
1817 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1819 volatile union i40e_rx_desc *rxdp;
1820 struct i40e_rx_queue *rxq = rx_queue;
1824 if (unlikely(offset >= rxq->nb_rx_desc)) {
1825 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1829 desc = rxq->rx_tail + offset;
1830 if (desc >= rxq->nb_rx_desc)
1831 desc -= rxq->nb_rx_desc;
1833 rxdp = &(rxq->rx_ring[desc]);
1835 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1836 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1837 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1843 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1846 unsigned int socket_id,
1847 const struct rte_eth_txconf *tx_conf)
1849 struct i40e_vsi *vsi;
1850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1851 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1852 struct i40e_tx_queue *txq;
1853 const struct rte_memzone *tz;
1855 uint16_t tx_rs_thresh, tx_free_thresh;
1856 uint16_t i, base, bsf, tc_mapping;
1858 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1859 struct i40e_vf *vf =
1860 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1863 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1866 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1867 "exceeds the maximum", queue_idx);
1868 return I40E_ERR_PARAM;
1871 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1872 (nb_desc > I40E_MAX_RING_DESC) ||
1873 (nb_desc < I40E_MIN_RING_DESC)) {
1874 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1875 "invalid", nb_desc);
1876 return I40E_ERR_PARAM;
1880 * The following two parameters control the setting of the RS bit on
1881 * transmit descriptors. TX descriptors will have their RS bit set
1882 * after txq->tx_rs_thresh descriptors have been used. The TX
1883 * descriptor ring will be cleaned after txq->tx_free_thresh
1884 * descriptors are used or if the number of descriptors required to
1885 * transmit a packet is greater than the number of free TX descriptors.
1887 * The following constraints must be satisfied:
1888 * - tx_rs_thresh must be greater than 0.
1889 * - tx_rs_thresh must be less than the size of the ring minus 2.
1890 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1891 * - tx_rs_thresh must be a divisor of the ring size.
1892 * - tx_free_thresh must be greater than 0.
1893 * - tx_free_thresh must be less than the size of the ring minus 3.
1895 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1896 * race condition, hence the maximum threshold constraints. When set
1897 * to zero use default values.
1899 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1900 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1901 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1902 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1903 if (tx_rs_thresh >= (nb_desc - 2)) {
1904 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1905 "number of TX descriptors minus 2. "
1906 "(tx_rs_thresh=%u port=%d queue=%d)",
1907 (unsigned int)tx_rs_thresh,
1908 (int)dev->data->port_id,
1910 return I40E_ERR_PARAM;
1912 if (tx_free_thresh >= (nb_desc - 3)) {
1913 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1914 "tx_free_thresh must be less than the "
1915 "number of TX descriptors minus 3. "
1916 "(tx_free_thresh=%u port=%d queue=%d)",
1917 (unsigned int)tx_free_thresh,
1918 (int)dev->data->port_id,
1920 return I40E_ERR_PARAM;
1922 if (tx_rs_thresh > tx_free_thresh) {
1923 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1924 "equal to tx_free_thresh. (tx_free_thresh=%u"
1925 " tx_rs_thresh=%u port=%d queue=%d)",
1926 (unsigned int)tx_free_thresh,
1927 (unsigned int)tx_rs_thresh,
1928 (int)dev->data->port_id,
1930 return I40E_ERR_PARAM;
1932 if ((nb_desc % tx_rs_thresh) != 0) {
1933 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1934 "number of TX descriptors. (tx_rs_thresh=%u"
1935 " port=%d queue=%d)",
1936 (unsigned int)tx_rs_thresh,
1937 (int)dev->data->port_id,
1939 return I40E_ERR_PARAM;
1941 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1942 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1943 "tx_rs_thresh is greater than 1. "
1944 "(tx_rs_thresh=%u port=%d queue=%d)",
1945 (unsigned int)tx_rs_thresh,
1946 (int)dev->data->port_id,
1948 return I40E_ERR_PARAM;
1951 /* Free memory if needed. */
1952 if (dev->data->tx_queues[queue_idx]) {
1953 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1954 dev->data->tx_queues[queue_idx] = NULL;
1957 /* Allocate the TX queue data structure. */
1958 txq = rte_zmalloc_socket("i40e tx queue",
1959 sizeof(struct i40e_tx_queue),
1960 RTE_CACHE_LINE_SIZE,
1963 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1964 "tx queue structure");
1968 /* Allocate TX hardware ring descriptors. */
1969 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1970 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1971 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1972 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1974 i40e_dev_tx_queue_release(txq);
1975 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1979 txq->nb_tx_desc = nb_desc;
1980 txq->tx_rs_thresh = tx_rs_thresh;
1981 txq->tx_free_thresh = tx_free_thresh;
1982 txq->pthresh = tx_conf->tx_thresh.pthresh;
1983 txq->hthresh = tx_conf->tx_thresh.hthresh;
1984 txq->wthresh = tx_conf->tx_thresh.wthresh;
1985 txq->queue_id = queue_idx;
1986 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1987 txq->reg_idx = queue_idx;
1988 else /* PF device */
1989 txq->reg_idx = vsi->base_queue +
1990 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1992 txq->port_id = dev->data->port_id;
1993 txq->txq_flags = tx_conf->txq_flags;
1995 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1997 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1998 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2000 /* Allocate software ring */
2002 rte_zmalloc_socket("i40e tx sw ring",
2003 sizeof(struct i40e_tx_entry) * nb_desc,
2004 RTE_CACHE_LINE_SIZE,
2006 if (!txq->sw_ring) {
2007 i40e_dev_tx_queue_release(txq);
2008 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2012 i40e_reset_tx_queue(txq);
2014 dev->data->tx_queues[queue_idx] = txq;
2016 /* Use a simple TX queue without offloads or multi segs if possible */
2017 i40e_set_tx_function_flag(dev, txq);
2019 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2020 if (!(vsi->enabled_tc & (1 << i)))
2022 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2023 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2024 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2025 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2026 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2028 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2036 i40e_dev_tx_queue_release(void *txq)
2038 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2041 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2045 i40e_tx_queue_release_mbufs(q);
2046 rte_free(q->sw_ring);
2050 const struct rte_memzone *
2051 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2053 const struct rte_memzone *mz;
2055 mz = rte_memzone_lookup(name);
2059 if (rte_xen_dom0_supported())
2060 mz = rte_memzone_reserve_bounded(name, len,
2061 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2063 mz = rte_memzone_reserve_aligned(name, len,
2064 socket_id, 0, I40E_RING_BASE_ALIGN);
2069 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2073 /* SSE Vector driver has a different way of releasing mbufs. */
2074 if (rxq->rx_using_sse) {
2075 i40e_rx_queue_release_mbufs_vec(rxq);
2079 if (!rxq->sw_ring) {
2080 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2084 for (i = 0; i < rxq->nb_rx_desc; i++) {
2085 if (rxq->sw_ring[i].mbuf) {
2086 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2087 rxq->sw_ring[i].mbuf = NULL;
2090 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2091 if (rxq->rx_nb_avail == 0)
2093 for (i = 0; i < rxq->rx_nb_avail; i++) {
2094 struct rte_mbuf *mbuf;
2096 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2097 rte_pktmbuf_free_seg(mbuf);
2099 rxq->rx_nb_avail = 0;
2100 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2104 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2110 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2114 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2115 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2116 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2118 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2119 len = rxq->nb_rx_desc;
2121 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2122 ((volatile char *)rxq->rx_ring)[i] = 0;
2124 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2125 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2126 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2127 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2129 rxq->rx_nb_avail = 0;
2130 rxq->rx_next_avail = 0;
2131 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2132 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2134 rxq->nb_rx_hold = 0;
2135 rxq->pkt_first_seg = NULL;
2136 rxq->pkt_last_seg = NULL;
2138 rxq->rxrearm_start = 0;
2139 rxq->rxrearm_nb = 0;
2143 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2147 if (!txq || !txq->sw_ring) {
2148 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2152 for (i = 0; i < txq->nb_tx_desc; i++) {
2153 if (txq->sw_ring[i].mbuf) {
2154 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2155 txq->sw_ring[i].mbuf = NULL;
2161 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2163 struct i40e_tx_entry *txe;
2164 uint16_t i, prev, size;
2167 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2172 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2173 for (i = 0; i < size; i++)
2174 ((volatile char *)txq->tx_ring)[i] = 0;
2176 prev = (uint16_t)(txq->nb_tx_desc - 1);
2177 for (i = 0; i < txq->nb_tx_desc; i++) {
2178 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2180 txd->cmd_type_offset_bsz =
2181 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2184 txe[prev].next_id = i;
2188 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2189 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2192 txq->nb_tx_used = 0;
2194 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2195 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2198 /* Init the TX queue in hardware */
2200 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2202 enum i40e_status_code err = I40E_SUCCESS;
2203 struct i40e_vsi *vsi = txq->vsi;
2204 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2205 uint16_t pf_q = txq->reg_idx;
2206 struct i40e_hmc_obj_txq tx_ctx;
2209 /* clear the context structure first */
2210 memset(&tx_ctx, 0, sizeof(tx_ctx));
2211 tx_ctx.new_context = 1;
2212 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2213 tx_ctx.qlen = txq->nb_tx_desc;
2215 #ifdef RTE_LIBRTE_IEEE1588
2216 tx_ctx.timesync_ena = 1;
2218 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2219 if (vsi->type == I40E_VSI_FDIR)
2220 tx_ctx.fd_ena = TRUE;
2222 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2223 if (err != I40E_SUCCESS) {
2224 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2228 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2229 if (err != I40E_SUCCESS) {
2230 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2234 /* Now associate this queue with this PCI function */
2235 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2236 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2237 I40E_QTX_CTL_PF_INDX_MASK);
2238 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2239 I40E_WRITE_FLUSH(hw);
2241 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2247 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2249 struct i40e_rx_entry *rxe = rxq->sw_ring;
2253 for (i = 0; i < rxq->nb_rx_desc; i++) {
2254 volatile union i40e_rx_desc *rxd;
2255 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2257 if (unlikely(!mbuf)) {
2258 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2262 rte_mbuf_refcnt_set(mbuf, 1);
2264 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2266 mbuf->port = rxq->port_id;
2269 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2271 rxd = &rxq->rx_ring[i];
2272 rxd->read.pkt_addr = dma_addr;
2273 rxd->read.hdr_addr = 0;
2274 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2275 rxd->read.rsvd1 = 0;
2276 rxd->read.rsvd2 = 0;
2277 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2286 * Calculate the buffer length, and check the jumbo frame
2287 * and maximum packet length.
2290 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2292 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2293 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2294 struct rte_eth_dev_data *data = pf->dev_data;
2295 uint16_t buf_size, len;
2297 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2298 RTE_PKTMBUF_HEADROOM);
2300 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2301 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2302 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2303 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2304 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2305 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2306 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2307 rxq->hs_mode = i40e_header_split_enabled;
2309 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2311 rxq->rx_hdr_len = 0;
2312 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2313 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2314 rxq->hs_mode = i40e_header_split_none;
2318 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2319 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2320 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2321 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2322 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2323 PMD_DRV_LOG(ERR, "maximum packet length must "
2324 "be larger than %u and smaller than %u,"
2325 "as jumbo frame is enabled",
2326 (uint32_t)ETHER_MAX_LEN,
2327 (uint32_t)I40E_FRAME_SIZE_MAX);
2328 return I40E_ERR_CONFIG;
2331 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2332 rxq->max_pkt_len > ETHER_MAX_LEN) {
2333 PMD_DRV_LOG(ERR, "maximum packet length must be "
2334 "larger than %u and smaller than %u, "
2335 "as jumbo frame is disabled",
2336 (uint32_t)ETHER_MIN_LEN,
2337 (uint32_t)ETHER_MAX_LEN);
2338 return I40E_ERR_CONFIG;
2345 /* Init the RX queue in hardware */
2347 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2349 int err = I40E_SUCCESS;
2350 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2351 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2352 uint16_t pf_q = rxq->reg_idx;
2354 struct i40e_hmc_obj_rxq rx_ctx;
2356 err = i40e_rx_queue_config(rxq);
2358 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2362 /* Clear the context structure first */
2363 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2364 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2365 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2367 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2368 rx_ctx.qlen = rxq->nb_rx_desc;
2369 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2372 rx_ctx.dtype = rxq->hs_mode;
2374 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2376 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2377 rx_ctx.rxmax = rxq->max_pkt_len;
2378 rx_ctx.tphrdesc_ena = 1;
2379 rx_ctx.tphwdesc_ena = 1;
2380 rx_ctx.tphdata_ena = 1;
2381 rx_ctx.tphhead_ena = 1;
2382 rx_ctx.lrxqthresh = 2;
2383 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2385 /* showiv indicates if inner VLAN is stripped inside of tunnel
2386 * packet. When set it to 1, vlan information is stripped from
2387 * the inner header, but the hardware does not put it in the
2388 * descriptor. So set it zero by default.
2393 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2394 if (err != I40E_SUCCESS) {
2395 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2398 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2399 if (err != I40E_SUCCESS) {
2400 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2404 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2406 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2407 RTE_PKTMBUF_HEADROOM);
2409 /* Check if scattered RX needs to be used. */
2410 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2411 dev_data->scattered_rx = 1;
2414 /* Init the RX tail regieter. */
2415 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2421 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2425 PMD_INIT_FUNC_TRACE();
2427 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2428 if (!dev->data->tx_queues[i])
2430 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2431 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2434 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2435 if (!dev->data->rx_queues[i])
2437 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2438 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2443 i40e_dev_free_queues(struct rte_eth_dev *dev)
2447 PMD_INIT_FUNC_TRACE();
2449 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2450 if (!dev->data->rx_queues[i])
2452 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2453 dev->data->rx_queues[i] = NULL;
2455 dev->data->nb_rx_queues = 0;
2457 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2458 if (!dev->data->tx_queues[i])
2460 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2461 dev->data->tx_queues[i] = NULL;
2463 dev->data->nb_tx_queues = 0;
2466 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2467 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2469 enum i40e_status_code
2470 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2472 struct i40e_tx_queue *txq;
2473 const struct rte_memzone *tz = NULL;
2475 struct rte_eth_dev *dev;
2478 PMD_DRV_LOG(ERR, "PF is not available");
2479 return I40E_ERR_BAD_PTR;
2482 dev = pf->adapter->eth_dev;
2484 /* Allocate the TX queue data structure. */
2485 txq = rte_zmalloc_socket("i40e fdir tx queue",
2486 sizeof(struct i40e_tx_queue),
2487 RTE_CACHE_LINE_SIZE,
2490 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2491 "tx queue structure.");
2492 return I40E_ERR_NO_MEMORY;
2495 /* Allocate TX hardware ring descriptors. */
2496 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2497 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2499 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2500 I40E_FDIR_QUEUE_ID, ring_size,
2501 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2503 i40e_dev_tx_queue_release(txq);
2504 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2505 return I40E_ERR_NO_MEMORY;
2508 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2509 txq->queue_id = I40E_FDIR_QUEUE_ID;
2510 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2511 txq->vsi = pf->fdir.fdir_vsi;
2513 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2514 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2516 * don't need to allocate software ring and reset for the fdir
2517 * program queue just set the queue has been configured.
2522 return I40E_SUCCESS;
2525 enum i40e_status_code
2526 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2528 struct i40e_rx_queue *rxq;
2529 const struct rte_memzone *rz = NULL;
2531 struct rte_eth_dev *dev;
2534 PMD_DRV_LOG(ERR, "PF is not available");
2535 return I40E_ERR_BAD_PTR;
2538 dev = pf->adapter->eth_dev;
2540 /* Allocate the RX queue data structure. */
2541 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2542 sizeof(struct i40e_rx_queue),
2543 RTE_CACHE_LINE_SIZE,
2546 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2547 "rx queue structure.");
2548 return I40E_ERR_NO_MEMORY;
2551 /* Allocate RX hardware ring descriptors. */
2552 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2553 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2555 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2556 I40E_FDIR_QUEUE_ID, ring_size,
2557 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2559 i40e_dev_rx_queue_release(rxq);
2560 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2561 return I40E_ERR_NO_MEMORY;
2564 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2565 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2566 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2567 rxq->vsi = pf->fdir.fdir_vsi;
2569 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2570 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2573 * Don't need to allocate software ring and reset for the fdir
2574 * rx queue, just set the queue has been configured.
2579 return I40E_SUCCESS;
2583 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2584 struct rte_eth_rxq_info *qinfo)
2586 struct i40e_rx_queue *rxq;
2588 rxq = dev->data->rx_queues[queue_id];
2590 qinfo->mp = rxq->mp;
2591 qinfo->scattered_rx = dev->data->scattered_rx;
2592 qinfo->nb_desc = rxq->nb_rx_desc;
2594 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2595 qinfo->conf.rx_drop_en = rxq->drop_en;
2596 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2600 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2601 struct rte_eth_txq_info *qinfo)
2603 struct i40e_tx_queue *txq;
2605 txq = dev->data->tx_queues[queue_id];
2607 qinfo->nb_desc = txq->nb_tx_desc;
2609 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2610 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2611 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2613 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2614 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2615 qinfo->conf.txq_flags = txq->txq_flags;
2616 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2619 void __attribute__((cold))
2620 i40e_set_rx_function(struct rte_eth_dev *dev)
2622 struct i40e_adapter *ad =
2623 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2624 uint16_t rx_using_sse, i;
2625 /* In order to allow Vector Rx there are a few configuration
2626 * conditions to be met and Rx Bulk Allocation should be allowed.
2628 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2629 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2630 !ad->rx_bulk_alloc_allowed) {
2631 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2632 " Vector Rx preconditions",
2633 dev->data->port_id);
2635 ad->rx_vec_allowed = false;
2637 if (ad->rx_vec_allowed) {
2638 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2639 struct i40e_rx_queue *rxq =
2640 dev->data->rx_queues[i];
2642 if (rxq && i40e_rxq_vec_setup(rxq)) {
2643 ad->rx_vec_allowed = false;
2650 if (dev->data->scattered_rx) {
2651 /* Set the non-LRO scattered callback: there are Vector and
2652 * single allocation versions.
2654 if (ad->rx_vec_allowed) {
2655 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2656 "callback (port=%d).",
2657 dev->data->port_id);
2659 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2661 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2662 "allocation callback (port=%d).",
2663 dev->data->port_id);
2664 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2666 /* If parameters allow we are going to choose between the following
2670 * - Single buffer allocation (the simplest one)
2672 } else if (ad->rx_vec_allowed) {
2673 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2674 "burst size no less than %d (port=%d).",
2675 RTE_I40E_DESCS_PER_LOOP,
2676 dev->data->port_id);
2678 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2679 } else if (ad->rx_bulk_alloc_allowed) {
2680 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2681 "satisfied. Rx Burst Bulk Alloc function "
2682 "will be used on port=%d.",
2683 dev->data->port_id);
2685 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2687 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2688 "satisfied, or Scattered Rx is requested "
2690 dev->data->port_id);
2692 dev->rx_pkt_burst = i40e_recv_pkts;
2695 /* Propagate information about RX function choice through all queues. */
2696 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2698 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2699 dev->rx_pkt_burst == i40e_recv_pkts_vec);
2701 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2702 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2705 rxq->rx_using_sse = rx_using_sse;
2710 void __attribute__((cold))
2711 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2713 struct i40e_adapter *ad =
2714 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2716 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2717 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2718 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2719 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2720 PMD_INIT_LOG(DEBUG, "Vector tx"
2721 " can be enabled on this txq.");
2724 ad->tx_vec_allowed = false;
2727 ad->tx_simple_allowed = false;
2731 void __attribute__((cold))
2732 i40e_set_tx_function(struct rte_eth_dev *dev)
2734 struct i40e_adapter *ad =
2735 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2738 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2739 if (ad->tx_vec_allowed) {
2740 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2741 struct i40e_tx_queue *txq =
2742 dev->data->tx_queues[i];
2744 if (txq && i40e_txq_vec_setup(txq)) {
2745 ad->tx_vec_allowed = false;
2752 if (ad->tx_simple_allowed) {
2753 if (ad->tx_vec_allowed) {
2754 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2755 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2757 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2758 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2761 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2762 dev->tx_pkt_burst = i40e_xmit_pkts;
2766 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2767 int __attribute__((weak))
2768 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2773 uint16_t __attribute__((weak))
2775 void __rte_unused *rx_queue,
2776 struct rte_mbuf __rte_unused **rx_pkts,
2777 uint16_t __rte_unused nb_pkts)
2782 uint16_t __attribute__((weak))
2783 i40e_recv_scattered_pkts_vec(
2784 void __rte_unused *rx_queue,
2785 struct rte_mbuf __rte_unused **rx_pkts,
2786 uint16_t __rte_unused nb_pkts)
2791 int __attribute__((weak))
2792 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2797 int __attribute__((weak))
2798 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2803 void __attribute__((weak))
2804 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2809 uint16_t __attribute__((weak))
2810 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2811 struct rte_mbuf __rte_unused **tx_pkts,
2812 uint16_t __rte_unused nb_pkts)