4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define DEFAULT_TX_RS_THRESH 32
61 #define DEFAULT_TX_FREE_THRESH 32
62 #define I40E_MAX_PKT_TYPE 256
64 #define I40E_TX_MAX_BURST 32
66 #define I40E_DMA_MEM_ALIGN 4096
68 /* Base address of the HW descriptor ring should be 128B aligned. */
69 #define I40E_RING_BASE_ALIGN 128
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
79 PKT_TX_OUTER_IP_CKSUM)
81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
82 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
85 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
87 static const struct rte_memzone *
88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
89 const char *ring_name,
93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
94 struct rte_mbuf **tx_pkts,
98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
100 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
101 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
102 mb->ol_flags |= PKT_RX_VLAN_PKT;
104 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
105 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
106 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
111 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
112 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
113 mb->ol_flags |= PKT_RX_QINQ_PKT;
114 mb->vlan_tci_outer = mb->vlan_tci;
115 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
116 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
117 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
118 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
120 mb->vlan_tci_outer = 0;
123 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
124 mb->vlan_tci, mb->vlan_tci_outer);
127 /* Translate the rx descriptor status to pkt flags */
128 static inline uint64_t
129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
133 /* Check if RSS_HASH */
134 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
135 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
136 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
138 /* Check if FDIR Match */
139 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
145 static inline uint64_t
146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
149 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
151 #define I40E_RX_ERR_BITS 0x3f
152 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
154 /* If RXE bit set, all other status bits are meaningless */
155 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
156 flags |= PKT_RX_MAC_ERR;
160 /* If RECIPE bit set, all other status indications should be ignored */
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
162 flags |= PKT_RX_RECIP_ERR;
165 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
166 flags |= PKT_RX_HBUF_OVERFLOW;
167 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
168 flags |= PKT_RX_IP_CKSUM_BAD;
169 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
170 flags |= PKT_RX_L4_CKSUM_BAD;
171 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
172 flags |= PKT_RX_EIP_CKSUM_BAD;
173 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
174 flags |= PKT_RX_OVERSIZE;
179 /* Function to check and set the ieee1588 timesync index and get the
182 #ifdef RTE_LIBRTE_IEEE1588
183 static inline uint64_t
184 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
186 uint64_t pkt_flags = 0;
187 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
188 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
189 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
191 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
192 == RTE_PTYPE_L2_ETHER_TIMESYNC)
193 pkt_flags = PKT_RX_IEEE1588_PTP;
195 pkt_flags |= PKT_RX_IEEE1588_TMST;
196 mb->timesync = tsyn & 0x03;
203 /* For each value it means, datasheet of hardware can tell more details */
204 static inline uint32_t
205 i40e_rxd_pkt_type_mapping(uint8_t ptype)
207 static const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {
210 [1] = RTE_PTYPE_L2_ETHER,
211 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
212 /* [3] - [5] reserved */
213 [6] = RTE_PTYPE_L2_ETHER_LLDP,
214 /* [7] - [10] reserved */
215 [11] = RTE_PTYPE_L2_ETHER_ARP,
216 /* [12] - [21] reserved */
218 /* Non tunneled IPv4 */
219 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
222 RTE_PTYPE_L4_NONFRAG,
223 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
226 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
228 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
235 RTE_PTYPE_TUNNEL_IP |
236 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_FRAG,
238 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_TUNNEL_IP |
240 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L4_NONFRAG,
242 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_TUNNEL_IP |
244 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L4_UDP,
247 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
248 RTE_PTYPE_TUNNEL_IP |
249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L4_TCP,
251 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_TUNNEL_IP |
253 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L4_SCTP,
255 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_TUNNEL_IP |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_ICMP,
261 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
262 RTE_PTYPE_TUNNEL_IP |
263 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_FRAG,
265 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
266 RTE_PTYPE_TUNNEL_IP |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_NONFRAG,
269 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_TUNNEL_IP |
271 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_UDP,
274 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
275 RTE_PTYPE_TUNNEL_IP |
276 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_TCP,
278 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
279 RTE_PTYPE_TUNNEL_IP |
280 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_SCTP,
282 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_TUNNEL_IP |
284 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
285 RTE_PTYPE_INNER_L4_ICMP,
287 /* IPv4 --> GRE/Teredo/VXLAN */
288 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
289 RTE_PTYPE_TUNNEL_GRENAT,
291 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
292 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
293 RTE_PTYPE_TUNNEL_GRENAT |
294 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
295 RTE_PTYPE_INNER_L4_FRAG,
296 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
297 RTE_PTYPE_TUNNEL_GRENAT |
298 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
299 RTE_PTYPE_INNER_L4_NONFRAG,
300 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
301 RTE_PTYPE_TUNNEL_GRENAT |
302 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
303 RTE_PTYPE_INNER_L4_UDP,
305 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
306 RTE_PTYPE_TUNNEL_GRENAT |
307 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
308 RTE_PTYPE_INNER_L4_TCP,
309 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
310 RTE_PTYPE_TUNNEL_GRENAT |
311 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
312 RTE_PTYPE_INNER_L4_SCTP,
313 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_TUNNEL_GRENAT |
315 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
316 RTE_PTYPE_INNER_L4_ICMP,
318 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
319 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
320 RTE_PTYPE_TUNNEL_GRENAT |
321 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
322 RTE_PTYPE_INNER_L4_FRAG,
323 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
324 RTE_PTYPE_TUNNEL_GRENAT |
325 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
326 RTE_PTYPE_INNER_L4_NONFRAG,
327 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
328 RTE_PTYPE_TUNNEL_GRENAT |
329 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
330 RTE_PTYPE_INNER_L4_UDP,
332 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
333 RTE_PTYPE_TUNNEL_GRENAT |
334 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
335 RTE_PTYPE_INNER_L4_TCP,
336 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
337 RTE_PTYPE_TUNNEL_GRENAT |
338 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
339 RTE_PTYPE_INNER_L4_SCTP,
340 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
341 RTE_PTYPE_TUNNEL_GRENAT |
342 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
343 RTE_PTYPE_INNER_L4_ICMP,
345 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
346 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
347 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
349 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
350 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
351 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
352 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
353 RTE_PTYPE_INNER_L4_FRAG,
354 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
355 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
356 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
357 RTE_PTYPE_INNER_L4_NONFRAG,
358 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
359 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
360 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
361 RTE_PTYPE_INNER_L4_UDP,
363 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
364 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
365 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
366 RTE_PTYPE_INNER_L4_TCP,
367 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
368 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
369 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
370 RTE_PTYPE_INNER_L4_SCTP,
371 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
372 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
373 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
374 RTE_PTYPE_INNER_L4_ICMP,
376 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
377 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
378 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
379 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
380 RTE_PTYPE_INNER_L4_FRAG,
381 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
382 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
383 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
384 RTE_PTYPE_INNER_L4_NONFRAG,
385 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
386 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
387 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
388 RTE_PTYPE_INNER_L4_UDP,
390 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
391 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
392 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
393 RTE_PTYPE_INNER_L4_TCP,
394 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
395 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
396 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
397 RTE_PTYPE_INNER_L4_SCTP,
398 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
399 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
400 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
401 RTE_PTYPE_INNER_L4_ICMP,
403 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
404 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
405 RTE_PTYPE_TUNNEL_GRENAT |
406 RTE_PTYPE_INNER_L2_ETHER_VLAN,
408 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
409 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
410 RTE_PTYPE_TUNNEL_GRENAT |
411 RTE_PTYPE_INNER_L2_ETHER_VLAN |
412 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
413 RTE_PTYPE_INNER_L4_FRAG,
414 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
415 RTE_PTYPE_TUNNEL_GRENAT |
416 RTE_PTYPE_INNER_L2_ETHER_VLAN |
417 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
418 RTE_PTYPE_INNER_L4_NONFRAG,
419 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
420 RTE_PTYPE_TUNNEL_GRENAT |
421 RTE_PTYPE_INNER_L2_ETHER_VLAN |
422 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
423 RTE_PTYPE_INNER_L4_UDP,
425 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
426 RTE_PTYPE_TUNNEL_GRENAT |
427 RTE_PTYPE_INNER_L2_ETHER_VLAN |
428 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
429 RTE_PTYPE_INNER_L4_TCP,
430 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
431 RTE_PTYPE_TUNNEL_GRENAT |
432 RTE_PTYPE_INNER_L2_ETHER_VLAN |
433 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
434 RTE_PTYPE_INNER_L4_SCTP,
435 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
436 RTE_PTYPE_TUNNEL_GRENAT |
437 RTE_PTYPE_INNER_L2_ETHER_VLAN |
438 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
439 RTE_PTYPE_INNER_L4_ICMP,
441 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
442 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
443 RTE_PTYPE_TUNNEL_GRENAT |
444 RTE_PTYPE_INNER_L2_ETHER_VLAN |
445 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
446 RTE_PTYPE_INNER_L4_FRAG,
447 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
448 RTE_PTYPE_TUNNEL_GRENAT |
449 RTE_PTYPE_INNER_L2_ETHER_VLAN |
450 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
451 RTE_PTYPE_INNER_L4_NONFRAG,
452 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
453 RTE_PTYPE_TUNNEL_GRENAT |
454 RTE_PTYPE_INNER_L2_ETHER_VLAN |
455 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
456 RTE_PTYPE_INNER_L4_UDP,
458 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
459 RTE_PTYPE_TUNNEL_GRENAT |
460 RTE_PTYPE_INNER_L2_ETHER_VLAN |
461 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
462 RTE_PTYPE_INNER_L4_TCP,
463 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
464 RTE_PTYPE_TUNNEL_GRENAT |
465 RTE_PTYPE_INNER_L2_ETHER_VLAN |
466 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
467 RTE_PTYPE_INNER_L4_SCTP,
468 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
469 RTE_PTYPE_TUNNEL_GRENAT |
470 RTE_PTYPE_INNER_L2_ETHER_VLAN |
471 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
472 RTE_PTYPE_INNER_L4_ICMP,
474 /* Non tunneled IPv6 */
475 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
477 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
478 RTE_PTYPE_L4_NONFRAG,
479 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
482 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
484 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
486 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
490 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
491 RTE_PTYPE_TUNNEL_IP |
492 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
493 RTE_PTYPE_INNER_L4_FRAG,
494 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
495 RTE_PTYPE_TUNNEL_IP |
496 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
497 RTE_PTYPE_INNER_L4_NONFRAG,
498 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
499 RTE_PTYPE_TUNNEL_IP |
500 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
501 RTE_PTYPE_INNER_L4_UDP,
503 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
504 RTE_PTYPE_TUNNEL_IP |
505 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
506 RTE_PTYPE_INNER_L4_TCP,
507 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
508 RTE_PTYPE_TUNNEL_IP |
509 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
510 RTE_PTYPE_INNER_L4_SCTP,
511 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
512 RTE_PTYPE_TUNNEL_IP |
513 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
514 RTE_PTYPE_INNER_L4_ICMP,
517 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
518 RTE_PTYPE_TUNNEL_IP |
519 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
520 RTE_PTYPE_INNER_L4_FRAG,
521 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
522 RTE_PTYPE_TUNNEL_IP |
523 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
524 RTE_PTYPE_INNER_L4_NONFRAG,
525 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
526 RTE_PTYPE_TUNNEL_IP |
527 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
528 RTE_PTYPE_INNER_L4_UDP,
530 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
531 RTE_PTYPE_TUNNEL_IP |
532 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
533 RTE_PTYPE_INNER_L4_TCP,
534 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
535 RTE_PTYPE_TUNNEL_IP |
536 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
537 RTE_PTYPE_INNER_L4_SCTP,
538 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
539 RTE_PTYPE_TUNNEL_IP |
540 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
541 RTE_PTYPE_INNER_L4_ICMP,
543 /* IPv6 --> GRE/Teredo/VXLAN */
544 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
545 RTE_PTYPE_TUNNEL_GRENAT,
547 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
548 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
549 RTE_PTYPE_TUNNEL_GRENAT |
550 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
551 RTE_PTYPE_INNER_L4_FRAG,
552 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
553 RTE_PTYPE_TUNNEL_GRENAT |
554 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
555 RTE_PTYPE_INNER_L4_NONFRAG,
556 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
557 RTE_PTYPE_TUNNEL_GRENAT |
558 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
559 RTE_PTYPE_INNER_L4_UDP,
561 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
562 RTE_PTYPE_TUNNEL_GRENAT |
563 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
564 RTE_PTYPE_INNER_L4_TCP,
565 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
566 RTE_PTYPE_TUNNEL_GRENAT |
567 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
568 RTE_PTYPE_INNER_L4_SCTP,
569 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
570 RTE_PTYPE_TUNNEL_GRENAT |
571 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
572 RTE_PTYPE_INNER_L4_ICMP,
574 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
575 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
576 RTE_PTYPE_TUNNEL_GRENAT |
577 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
578 RTE_PTYPE_INNER_L4_FRAG,
579 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
580 RTE_PTYPE_TUNNEL_GRENAT |
581 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
582 RTE_PTYPE_INNER_L4_NONFRAG,
583 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
584 RTE_PTYPE_TUNNEL_GRENAT |
585 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
586 RTE_PTYPE_INNER_L4_UDP,
588 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
589 RTE_PTYPE_TUNNEL_GRENAT |
590 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
591 RTE_PTYPE_INNER_L4_TCP,
592 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
593 RTE_PTYPE_TUNNEL_GRENAT |
594 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
595 RTE_PTYPE_INNER_L4_SCTP,
596 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
597 RTE_PTYPE_TUNNEL_GRENAT |
598 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
599 RTE_PTYPE_INNER_L4_ICMP,
601 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
602 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
603 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
605 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
606 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
607 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
608 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
609 RTE_PTYPE_INNER_L4_FRAG,
610 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
611 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
612 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
613 RTE_PTYPE_INNER_L4_NONFRAG,
614 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
615 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
616 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
617 RTE_PTYPE_INNER_L4_UDP,
619 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
620 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
621 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
622 RTE_PTYPE_INNER_L4_TCP,
623 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
624 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
625 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
626 RTE_PTYPE_INNER_L4_SCTP,
627 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
628 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
629 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
630 RTE_PTYPE_INNER_L4_ICMP,
632 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
633 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
634 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
635 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
636 RTE_PTYPE_INNER_L4_FRAG,
637 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
638 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
639 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
640 RTE_PTYPE_INNER_L4_NONFRAG,
641 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
642 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
643 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
644 RTE_PTYPE_INNER_L4_UDP,
646 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
647 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
648 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
649 RTE_PTYPE_INNER_L4_TCP,
650 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
651 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
652 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
653 RTE_PTYPE_INNER_L4_SCTP,
654 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
655 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
656 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
657 RTE_PTYPE_INNER_L4_ICMP,
659 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
660 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
661 RTE_PTYPE_TUNNEL_GRENAT |
662 RTE_PTYPE_INNER_L2_ETHER_VLAN,
664 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
665 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
666 RTE_PTYPE_TUNNEL_GRENAT |
667 RTE_PTYPE_INNER_L2_ETHER_VLAN |
668 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
669 RTE_PTYPE_INNER_L4_FRAG,
670 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
671 RTE_PTYPE_TUNNEL_GRENAT |
672 RTE_PTYPE_INNER_L2_ETHER_VLAN |
673 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
674 RTE_PTYPE_INNER_L4_NONFRAG,
675 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
676 RTE_PTYPE_TUNNEL_GRENAT |
677 RTE_PTYPE_INNER_L2_ETHER_VLAN |
678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
679 RTE_PTYPE_INNER_L4_UDP,
681 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
682 RTE_PTYPE_TUNNEL_GRENAT |
683 RTE_PTYPE_INNER_L2_ETHER_VLAN |
684 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
685 RTE_PTYPE_INNER_L4_TCP,
686 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
687 RTE_PTYPE_TUNNEL_GRENAT |
688 RTE_PTYPE_INNER_L2_ETHER_VLAN |
689 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
690 RTE_PTYPE_INNER_L4_SCTP,
691 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
692 RTE_PTYPE_TUNNEL_GRENAT |
693 RTE_PTYPE_INNER_L2_ETHER_VLAN |
694 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
695 RTE_PTYPE_INNER_L4_ICMP,
697 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
698 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
699 RTE_PTYPE_TUNNEL_GRENAT |
700 RTE_PTYPE_INNER_L2_ETHER_VLAN |
701 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
702 RTE_PTYPE_INNER_L4_FRAG,
703 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
704 RTE_PTYPE_TUNNEL_GRENAT |
705 RTE_PTYPE_INNER_L2_ETHER_VLAN |
706 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
707 RTE_PTYPE_INNER_L4_NONFRAG,
708 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
709 RTE_PTYPE_TUNNEL_GRENAT |
710 RTE_PTYPE_INNER_L2_ETHER_VLAN |
711 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
712 RTE_PTYPE_INNER_L4_UDP,
714 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
715 RTE_PTYPE_TUNNEL_GRENAT |
716 RTE_PTYPE_INNER_L2_ETHER_VLAN |
717 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
718 RTE_PTYPE_INNER_L4_TCP,
719 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
720 RTE_PTYPE_TUNNEL_GRENAT |
721 RTE_PTYPE_INNER_L2_ETHER_VLAN |
722 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
723 RTE_PTYPE_INNER_L4_SCTP,
724 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
725 RTE_PTYPE_TUNNEL_GRENAT |
726 RTE_PTYPE_INNER_L2_ETHER_VLAN |
727 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
728 RTE_PTYPE_INNER_L4_ICMP,
730 /* All others reserved */
733 return ptype_table[ptype];
736 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
737 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
738 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
739 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
740 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
742 static inline uint64_t
743 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
746 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
747 uint16_t flexbh, flexbl;
749 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
750 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
751 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
752 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
753 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
754 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
757 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
759 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
760 flags |= PKT_RX_FDIR_ID;
761 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
763 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
764 flags |= PKT_RX_FDIR_FLX;
766 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
768 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
769 flags |= PKT_RX_FDIR_FLX;
773 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
774 flags |= PKT_RX_FDIR_ID;
779 i40e_txd_enable_checksum(uint64_t ol_flags,
782 union i40e_tx_offload tx_offload,
783 uint32_t *cd_tunneling)
785 /* UDP tunneling packet TX checksum offload */
786 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
788 *td_offset |= (tx_offload.outer_l2_len >> 1)
789 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
791 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
792 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
793 else if (ol_flags & PKT_TX_OUTER_IPV4)
794 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
795 else if (ol_flags & PKT_TX_OUTER_IPV6)
796 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
798 /* Now set the ctx descriptor fields */
799 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
800 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
801 (tx_offload.l2_len >> 1) <<
802 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
805 *td_offset |= (tx_offload.l2_len >> 1)
806 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
808 /* Enable L3 checksum offloads */
809 if (ol_flags & PKT_TX_IP_CKSUM) {
810 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
811 *td_offset |= (tx_offload.l3_len >> 2)
812 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
813 } else if (ol_flags & PKT_TX_IPV4) {
814 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
815 *td_offset |= (tx_offload.l3_len >> 2)
816 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
817 } else if (ol_flags & PKT_TX_IPV6) {
818 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
819 *td_offset |= (tx_offload.l3_len >> 2)
820 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
823 if (ol_flags & PKT_TX_TCP_SEG) {
824 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
825 *td_offset |= (tx_offload.l4_len >> 2)
826 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
830 /* Enable L4 checksum offloads */
831 switch (ol_flags & PKT_TX_L4_MASK) {
832 case PKT_TX_TCP_CKSUM:
833 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
834 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
835 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
837 case PKT_TX_SCTP_CKSUM:
838 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
839 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
840 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
842 case PKT_TX_UDP_CKSUM:
843 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
844 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
845 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
852 static inline struct rte_mbuf *
853 rte_rxmbuf_alloc(struct rte_mempool *mp)
857 m = __rte_mbuf_raw_alloc(mp);
858 __rte_mbuf_sanity_check_raw(m, 0);
863 /* Construct the tx flags */
864 static inline uint64_t
865 i40e_build_ctob(uint32_t td_cmd,
870 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
871 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
872 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
873 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
874 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
878 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
880 struct i40e_tx_entry *sw_ring = txq->sw_ring;
881 volatile struct i40e_tx_desc *txd = txq->tx_ring;
882 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
883 uint16_t nb_tx_desc = txq->nb_tx_desc;
884 uint16_t desc_to_clean_to;
885 uint16_t nb_tx_to_clean;
887 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
888 if (desc_to_clean_to >= nb_tx_desc)
889 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
891 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
892 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
893 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
894 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
895 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
896 "(port=%d queue=%d)", desc_to_clean_to,
897 txq->port_id, txq->queue_id);
901 if (last_desc_cleaned > desc_to_clean_to)
902 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
905 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
908 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
910 txq->last_desc_cleaned = desc_to_clean_to;
911 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
917 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
918 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
920 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
925 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
926 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
927 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
928 "rxq->rx_free_thresh=%d, "
929 "RTE_PMD_I40E_RX_MAX_BURST=%d",
930 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
932 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
933 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
934 "rxq->rx_free_thresh=%d, "
935 "rxq->nb_rx_desc=%d",
936 rxq->rx_free_thresh, rxq->nb_rx_desc);
938 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
939 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
940 "rxq->nb_rx_desc=%d, "
941 "rxq->rx_free_thresh=%d",
942 rxq->nb_rx_desc, rxq->rx_free_thresh);
944 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
945 RTE_PMD_I40E_RX_MAX_BURST))) {
946 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
947 "rxq->nb_rx_desc=%d, "
948 "I40E_MAX_RING_DESC=%d, "
949 "RTE_PMD_I40E_RX_MAX_BURST=%d",
950 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
951 RTE_PMD_I40E_RX_MAX_BURST);
961 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
962 #define I40E_LOOK_AHEAD 8
963 #if (I40E_LOOK_AHEAD != 8)
964 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
967 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
969 volatile union i40e_rx_desc *rxdp;
970 struct i40e_rx_entry *rxep;
975 int32_t s[I40E_LOOK_AHEAD], nb_dd;
976 int32_t i, j, nb_rx = 0;
979 rxdp = &rxq->rx_ring[rxq->rx_tail];
980 rxep = &rxq->sw_ring[rxq->rx_tail];
982 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
983 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
984 I40E_RXD_QW1_STATUS_SHIFT;
986 /* Make sure there is at least 1 packet to receive */
987 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
991 * Scan LOOK_AHEAD descriptors at a time to determine which
992 * descriptors reference packets that are ready to be received.
994 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
995 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
996 /* Read desc statuses backwards to avoid race condition */
997 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
998 qword1 = rte_le_to_cpu_64(\
999 rxdp[j].wb.qword1.status_error_len);
1000 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1001 I40E_RXD_QW1_STATUS_SHIFT;
1004 /* Compute how many status bits were set */
1005 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1006 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1010 /* Translate descriptor info to mbuf parameters */
1011 for (j = 0; j < nb_dd; j++) {
1013 qword1 = rte_le_to_cpu_64(\
1014 rxdp[j].wb.qword1.status_error_len);
1015 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1016 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1017 mb->data_len = pkt_len;
1018 mb->pkt_len = pkt_len;
1020 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1021 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1022 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1024 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1025 I40E_RXD_QW1_PTYPE_MASK) >>
1026 I40E_RXD_QW1_PTYPE_SHIFT));
1027 if (pkt_flags & PKT_RX_RSS_HASH)
1028 mb->hash.rss = rte_le_to_cpu_32(\
1029 rxdp[j].wb.qword0.hi_dword.rss);
1030 if (pkt_flags & PKT_RX_FDIR)
1031 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1033 #ifdef RTE_LIBRTE_IEEE1588
1034 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1036 mb->ol_flags |= pkt_flags;
1040 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1041 rxq->rx_stage[i + j] = rxep[j].mbuf;
1043 if (nb_dd != I40E_LOOK_AHEAD)
1047 /* Clear software ring entries */
1048 for (i = 0; i < nb_rx; i++)
1049 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1054 static inline uint16_t
1055 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1056 struct rte_mbuf **rx_pkts,
1060 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1062 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1064 for (i = 0; i < nb_pkts; i++)
1065 rx_pkts[i] = stage[i];
1067 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1068 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1074 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1076 volatile union i40e_rx_desc *rxdp;
1077 struct i40e_rx_entry *rxep;
1078 struct rte_mbuf *mb;
1079 uint16_t alloc_idx, i;
1083 /* Allocate buffers in bulk */
1084 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1085 (rxq->rx_free_thresh - 1));
1086 rxep = &(rxq->sw_ring[alloc_idx]);
1087 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1088 rxq->rx_free_thresh);
1089 if (unlikely(diag != 0)) {
1090 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1094 rxdp = &rxq->rx_ring[alloc_idx];
1095 for (i = 0; i < rxq->rx_free_thresh; i++) {
1096 if (likely(i < (rxq->rx_free_thresh - 1)))
1097 /* Prefetch next mbuf */
1098 rte_prefetch0(rxep[i + 1].mbuf);
1101 rte_mbuf_refcnt_set(mb, 1);
1103 mb->data_off = RTE_PKTMBUF_HEADROOM;
1105 mb->port = rxq->port_id;
1106 dma_addr = rte_cpu_to_le_64(\
1107 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1108 rxdp[i].read.hdr_addr = 0;
1109 rxdp[i].read.pkt_addr = dma_addr;
1112 /* Update rx tail regsiter */
1114 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1116 rxq->rx_free_trigger =
1117 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1118 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1119 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1124 static inline uint16_t
1125 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1127 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1133 if (rxq->rx_nb_avail)
1134 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1136 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1137 rxq->rx_next_avail = 0;
1138 rxq->rx_nb_avail = nb_rx;
1139 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1141 if (rxq->rx_tail > rxq->rx_free_trigger) {
1142 if (i40e_rx_alloc_bufs(rxq) != 0) {
1145 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1146 "port_id=%u, queue_id=%u",
1147 rxq->port_id, rxq->queue_id);
1148 rxq->rx_nb_avail = 0;
1149 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1150 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1151 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1157 if (rxq->rx_tail >= rxq->nb_rx_desc)
1160 if (rxq->rx_nb_avail)
1161 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1167 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1168 struct rte_mbuf **rx_pkts,
1171 uint16_t nb_rx = 0, n, count;
1173 if (unlikely(nb_pkts == 0))
1176 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1177 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1180 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1181 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1182 nb_rx = (uint16_t)(nb_rx + count);
1183 nb_pkts = (uint16_t)(nb_pkts - count);
1190 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1193 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1195 struct i40e_rx_queue *rxq;
1196 volatile union i40e_rx_desc *rx_ring;
1197 volatile union i40e_rx_desc *rxdp;
1198 union i40e_rx_desc rxd;
1199 struct i40e_rx_entry *sw_ring;
1200 struct i40e_rx_entry *rxe;
1201 struct rte_mbuf *rxm;
1202 struct rte_mbuf *nmb;
1206 uint16_t rx_packet_len;
1207 uint16_t rx_id, nb_hold;
1214 rx_id = rxq->rx_tail;
1215 rx_ring = rxq->rx_ring;
1216 sw_ring = rxq->sw_ring;
1218 while (nb_rx < nb_pkts) {
1219 rxdp = &rx_ring[rx_id];
1220 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1221 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1222 >> I40E_RXD_QW1_STATUS_SHIFT;
1224 /* Check the DD bit first */
1225 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1228 nmb = rte_rxmbuf_alloc(rxq->mp);
1234 rxe = &sw_ring[rx_id];
1236 if (unlikely(rx_id == rxq->nb_rx_desc))
1239 /* Prefetch next mbuf */
1240 rte_prefetch0(sw_ring[rx_id].mbuf);
1243 * When next RX descriptor is on a cache line boundary,
1244 * prefetch the next 4 RX descriptors and next 8 pointers
1247 if ((rx_id & 0x3) == 0) {
1248 rte_prefetch0(&rx_ring[rx_id]);
1249 rte_prefetch0(&sw_ring[rx_id]);
1254 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1255 rxdp->read.hdr_addr = 0;
1256 rxdp->read.pkt_addr = dma_addr;
1258 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1259 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1261 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1262 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1265 rxm->pkt_len = rx_packet_len;
1266 rxm->data_len = rx_packet_len;
1267 rxm->port = rxq->port_id;
1269 i40e_rxd_to_vlan_tci(rxm, &rxd);
1270 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1271 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1273 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1274 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1275 if (pkt_flags & PKT_RX_RSS_HASH)
1277 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1278 if (pkt_flags & PKT_RX_FDIR)
1279 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1281 #ifdef RTE_LIBRTE_IEEE1588
1282 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1284 rxm->ol_flags |= pkt_flags;
1286 rx_pkts[nb_rx++] = rxm;
1288 rxq->rx_tail = rx_id;
1291 * If the number of free RX descriptors is greater than the RX free
1292 * threshold of the queue, advance the receive tail register of queue.
1293 * Update that register with the value of the last processed RX
1294 * descriptor minus 1.
1296 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1297 if (nb_hold > rxq->rx_free_thresh) {
1298 rx_id = (uint16_t) ((rx_id == 0) ?
1299 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1300 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1303 rxq->nb_rx_hold = nb_hold;
1309 i40e_recv_scattered_pkts(void *rx_queue,
1310 struct rte_mbuf **rx_pkts,
1313 struct i40e_rx_queue *rxq = rx_queue;
1314 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1315 volatile union i40e_rx_desc *rxdp;
1316 union i40e_rx_desc rxd;
1317 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1318 struct i40e_rx_entry *rxe;
1319 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1320 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1321 struct rte_mbuf *nmb, *rxm;
1322 uint16_t rx_id = rxq->rx_tail;
1323 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1329 while (nb_rx < nb_pkts) {
1330 rxdp = &rx_ring[rx_id];
1331 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1332 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1333 I40E_RXD_QW1_STATUS_SHIFT;
1335 /* Check the DD bit */
1336 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1339 nmb = rte_rxmbuf_alloc(rxq->mp);
1344 rxe = &sw_ring[rx_id];
1346 if (rx_id == rxq->nb_rx_desc)
1349 /* Prefetch next mbuf */
1350 rte_prefetch0(sw_ring[rx_id].mbuf);
1353 * When next RX descriptor is on a cache line boundary,
1354 * prefetch the next 4 RX descriptors and next 8 pointers
1357 if ((rx_id & 0x3) == 0) {
1358 rte_prefetch0(&rx_ring[rx_id]);
1359 rte_prefetch0(&sw_ring[rx_id]);
1365 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1367 /* Set data buffer address and data length of the mbuf */
1368 rxdp->read.hdr_addr = 0;
1369 rxdp->read.pkt_addr = dma_addr;
1370 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1371 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1372 rxm->data_len = rx_packet_len;
1373 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1376 * If this is the first buffer of the received packet, set the
1377 * pointer to the first mbuf of the packet and initialize its
1378 * context. Otherwise, update the total length and the number
1379 * of segments of the current scattered packet, and update the
1380 * pointer to the last mbuf of the current packet.
1384 first_seg->nb_segs = 1;
1385 first_seg->pkt_len = rx_packet_len;
1387 first_seg->pkt_len =
1388 (uint16_t)(first_seg->pkt_len +
1390 first_seg->nb_segs++;
1391 last_seg->next = rxm;
1395 * If this is not the last buffer of the received packet,
1396 * update the pointer to the last mbuf of the current scattered
1397 * packet and continue to parse the RX ring.
1399 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1405 * This is the last buffer of the received packet. If the CRC
1406 * is not stripped by the hardware:
1407 * - Subtract the CRC length from the total packet length.
1408 * - If the last buffer only contains the whole CRC or a part
1409 * of it, free the mbuf associated to the last buffer. If part
1410 * of the CRC is also contained in the previous mbuf, subtract
1411 * the length of that CRC part from the data length of the
1415 if (unlikely(rxq->crc_len > 0)) {
1416 first_seg->pkt_len -= ETHER_CRC_LEN;
1417 if (rx_packet_len <= ETHER_CRC_LEN) {
1418 rte_pktmbuf_free_seg(rxm);
1419 first_seg->nb_segs--;
1420 last_seg->data_len =
1421 (uint16_t)(last_seg->data_len -
1422 (ETHER_CRC_LEN - rx_packet_len));
1423 last_seg->next = NULL;
1425 rxm->data_len = (uint16_t)(rx_packet_len -
1429 first_seg->port = rxq->port_id;
1430 first_seg->ol_flags = 0;
1431 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1432 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1433 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1434 first_seg->packet_type =
1435 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1436 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1437 if (pkt_flags & PKT_RX_RSS_HASH)
1439 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1440 if (pkt_flags & PKT_RX_FDIR)
1441 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1443 #ifdef RTE_LIBRTE_IEEE1588
1444 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1446 first_seg->ol_flags |= pkt_flags;
1448 /* Prefetch data of first segment, if configured to do so. */
1449 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1450 first_seg->data_off));
1451 rx_pkts[nb_rx++] = first_seg;
1455 /* Record index of the next RX descriptor to probe. */
1456 rxq->rx_tail = rx_id;
1457 rxq->pkt_first_seg = first_seg;
1458 rxq->pkt_last_seg = last_seg;
1461 * If the number of free RX descriptors is greater than the RX free
1462 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1463 * register. Update the RDT with the value of the last processed RX
1464 * descriptor minus 1, to guarantee that the RDT register is never
1465 * equal to the RDH register, which creates a "full" ring situtation
1466 * from the hardware point of view.
1468 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1469 if (nb_hold > rxq->rx_free_thresh) {
1470 rx_id = (uint16_t)(rx_id == 0 ?
1471 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1472 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1475 rxq->nb_rx_hold = nb_hold;
1480 /* Check if the context descriptor is needed for TX offloading */
1481 static inline uint16_t
1482 i40e_calc_context_desc(uint64_t flags)
1484 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1488 #ifdef RTE_LIBRTE_IEEE1588
1489 mask |= PKT_TX_IEEE1588_TMST;
1492 return ((flags & mask) ? 1 : 0);
1495 /* set i40e TSO context descriptor */
1496 static inline uint64_t
1497 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1499 uint64_t ctx_desc = 0;
1500 uint32_t cd_cmd, hdr_len, cd_tso_len;
1502 if (!tx_offload.l4_len) {
1503 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1508 * in case of tunneling packet, the outer_l2_len and
1509 * outer_l3_len must be 0.
1511 hdr_len = tx_offload.outer_l2_len +
1512 tx_offload.outer_l3_len +
1517 cd_cmd = I40E_TX_CTX_DESC_TSO;
1518 cd_tso_len = mbuf->pkt_len - hdr_len;
1519 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1520 ((uint64_t)cd_tso_len <<
1521 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1522 ((uint64_t)mbuf->tso_segsz <<
1523 I40E_TXD_CTX_QW1_MSS_SHIFT);
1529 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1531 struct i40e_tx_queue *txq;
1532 struct i40e_tx_entry *sw_ring;
1533 struct i40e_tx_entry *txe, *txn;
1534 volatile struct i40e_tx_desc *txd;
1535 volatile struct i40e_tx_desc *txr;
1536 struct rte_mbuf *tx_pkt;
1537 struct rte_mbuf *m_seg;
1538 uint32_t cd_tunneling_params;
1550 uint64_t buf_dma_addr;
1551 union i40e_tx_offload tx_offload = {0};
1554 sw_ring = txq->sw_ring;
1556 tx_id = txq->tx_tail;
1557 txe = &sw_ring[tx_id];
1559 /* Check if the descriptor ring needs to be cleaned. */
1560 if (txq->nb_tx_free < txq->tx_free_thresh)
1561 i40e_xmit_cleanup(txq);
1563 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1569 tx_pkt = *tx_pkts++;
1570 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1572 ol_flags = tx_pkt->ol_flags;
1573 tx_offload.l2_len = tx_pkt->l2_len;
1574 tx_offload.l3_len = tx_pkt->l3_len;
1575 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1576 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1577 tx_offload.l4_len = tx_pkt->l4_len;
1578 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1580 /* Calculate the number of context descriptors needed. */
1581 nb_ctx = i40e_calc_context_desc(ol_flags);
1584 * The number of descriptors that must be allocated for
1585 * a packet equals to the number of the segments of that
1586 * packet plus 1 context descriptor if needed.
1588 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1589 tx_last = (uint16_t)(tx_id + nb_used - 1);
1592 if (tx_last >= txq->nb_tx_desc)
1593 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1595 if (nb_used > txq->nb_tx_free) {
1596 if (i40e_xmit_cleanup(txq) != 0) {
1601 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1602 while (nb_used > txq->nb_tx_free) {
1603 if (i40e_xmit_cleanup(txq) != 0) {
1612 /* Descriptor based VLAN insertion */
1613 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1614 tx_flags |= tx_pkt->vlan_tci <<
1615 I40E_TX_FLAG_L2TAG1_SHIFT;
1616 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1617 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1618 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1619 I40E_TX_FLAG_L2TAG1_SHIFT;
1622 /* Always enable CRC offload insertion */
1623 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1625 /* Enable checksum offloading */
1626 cd_tunneling_params = 0;
1627 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1628 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1629 tx_offload, &cd_tunneling_params);
1633 /* Setup TX context descriptor if required */
1634 volatile struct i40e_tx_context_desc *ctx_txd =
1635 (volatile struct i40e_tx_context_desc *)\
1637 uint16_t cd_l2tag2 = 0;
1638 uint64_t cd_type_cmd_tso_mss =
1639 I40E_TX_DESC_DTYPE_CONTEXT;
1641 txn = &sw_ring[txe->next_id];
1642 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1643 if (txe->mbuf != NULL) {
1644 rte_pktmbuf_free_seg(txe->mbuf);
1648 /* TSO enabled means no timestamp */
1649 if (ol_flags & PKT_TX_TCP_SEG)
1650 cd_type_cmd_tso_mss |=
1651 i40e_set_tso_ctx(tx_pkt, tx_offload);
1653 #ifdef RTE_LIBRTE_IEEE1588
1654 if (ol_flags & PKT_TX_IEEE1588_TMST)
1655 cd_type_cmd_tso_mss |=
1656 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1657 I40E_TXD_CTX_QW1_CMD_SHIFT);
1661 ctx_txd->tunneling_params =
1662 rte_cpu_to_le_32(cd_tunneling_params);
1663 if (ol_flags & PKT_TX_QINQ_PKT) {
1664 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1665 cd_type_cmd_tso_mss |=
1666 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1667 I40E_TXD_CTX_QW1_CMD_SHIFT);
1669 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1670 ctx_txd->type_cmd_tso_mss =
1671 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1673 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1674 "tunneling_params: %#x;\n"
1677 "type_cmd_tso_mss: %#"PRIx64";\n",
1679 ctx_txd->tunneling_params,
1682 ctx_txd->type_cmd_tso_mss);
1684 txe->last_id = tx_last;
1685 tx_id = txe->next_id;
1692 txn = &sw_ring[txe->next_id];
1695 rte_pktmbuf_free_seg(txe->mbuf);
1698 /* Setup TX Descriptor */
1699 slen = m_seg->data_len;
1700 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1702 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1703 "buf_dma_addr: %#"PRIx64";\n"
1708 tx_pkt, tx_id, buf_dma_addr,
1709 td_cmd, td_offset, slen, td_tag);
1711 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1712 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1713 td_offset, slen, td_tag);
1714 txe->last_id = tx_last;
1715 tx_id = txe->next_id;
1717 m_seg = m_seg->next;
1718 } while (m_seg != NULL);
1720 /* The last packet data descriptor needs End Of Packet (EOP) */
1721 td_cmd |= I40E_TX_DESC_CMD_EOP;
1722 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1723 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1725 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1726 PMD_TX_FREE_LOG(DEBUG,
1727 "Setting RS bit on TXD id="
1728 "%4u (port=%d queue=%d)",
1729 tx_last, txq->port_id, txq->queue_id);
1731 td_cmd |= I40E_TX_DESC_CMD_RS;
1733 /* Update txq RS bit counters */
1734 txq->nb_tx_used = 0;
1737 txd->cmd_type_offset_bsz |=
1738 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1739 I40E_TXD_QW1_CMD_SHIFT);
1745 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1746 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1747 (unsigned) tx_id, (unsigned) nb_tx);
1749 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1750 txq->tx_tail = tx_id;
1755 static inline int __attribute__((always_inline))
1756 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1758 struct i40e_tx_entry *txep;
1761 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1762 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1763 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1766 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1768 for (i = 0; i < txq->tx_rs_thresh; i++)
1769 rte_prefetch0((txep + i)->mbuf);
1771 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1772 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1773 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1777 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1778 rte_pktmbuf_free_seg(txep->mbuf);
1783 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1784 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1785 if (txq->tx_next_dd >= txq->nb_tx_desc)
1786 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1788 return txq->tx_rs_thresh;
1791 /* Populate 4 descriptors with data from 4 mbufs */
1793 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1798 for (i = 0; i < 4; i++, txdp++, pkts++) {
1799 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1800 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1801 txdp->cmd_type_offset_bsz =
1802 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1803 (*pkts)->data_len, 0);
1807 /* Populate 1 descriptor with data from 1 mbuf */
1809 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1813 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1814 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1815 txdp->cmd_type_offset_bsz =
1816 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1817 (*pkts)->data_len, 0);
1820 /* Fill hardware descriptor ring with mbuf data */
1822 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1823 struct rte_mbuf **pkts,
1826 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1827 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1828 const int N_PER_LOOP = 4;
1829 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1830 int mainpart, leftover;
1833 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1834 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1835 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1836 for (j = 0; j < N_PER_LOOP; ++j) {
1837 (txep + i + j)->mbuf = *(pkts + i + j);
1839 tx4(txdp + i, pkts + i);
1841 if (unlikely(leftover > 0)) {
1842 for (i = 0; i < leftover; ++i) {
1843 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1844 tx1(txdp + mainpart + i, pkts + mainpart + i);
1849 static inline uint16_t
1850 tx_xmit_pkts(struct i40e_tx_queue *txq,
1851 struct rte_mbuf **tx_pkts,
1854 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1858 * Begin scanning the H/W ring for done descriptors when the number
1859 * of available descriptors drops below tx_free_thresh. For each done
1860 * descriptor, free the associated buffer.
1862 if (txq->nb_tx_free < txq->tx_free_thresh)
1863 i40e_tx_free_bufs(txq);
1865 /* Use available descriptor only */
1866 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1867 if (unlikely(!nb_pkts))
1870 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1871 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1872 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1873 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1874 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1875 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1876 I40E_TXD_QW1_CMD_SHIFT);
1877 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1881 /* Fill hardware descriptor ring with mbuf data */
1882 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1883 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1885 /* Determin if RS bit needs to be set */
1886 if (txq->tx_tail > txq->tx_next_rs) {
1887 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1888 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1889 I40E_TXD_QW1_CMD_SHIFT);
1891 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1892 if (txq->tx_next_rs >= txq->nb_tx_desc)
1893 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1896 if (txq->tx_tail >= txq->nb_tx_desc)
1899 /* Update the tx tail register */
1901 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1907 i40e_xmit_pkts_simple(void *tx_queue,
1908 struct rte_mbuf **tx_pkts,
1913 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1914 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1918 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1921 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1922 &tx_pkts[nb_tx], num);
1923 nb_tx = (uint16_t)(nb_tx + ret);
1924 nb_pkts = (uint16_t)(nb_pkts - ret);
1933 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1934 * application used, which assume having sequential ones. But from driver's
1935 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1936 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1937 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1938 * use queue_idx from 0 to 95 to access queues, while real queue would be
1939 * different. This function will do a queue mapping to find VSI the queue
1942 static struct i40e_vsi*
1943 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1945 /* the queue in MAIN VSI range */
1946 if (queue_idx < pf->main_vsi->nb_qps)
1947 return pf->main_vsi;
1949 queue_idx -= pf->main_vsi->nb_qps;
1951 /* queue_idx is greater than VMDQ VSIs range */
1952 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1953 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1957 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1961 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1963 /* the queue in MAIN VSI range */
1964 if (queue_idx < pf->main_vsi->nb_qps)
1967 /* It's VMDQ queues */
1968 queue_idx -= pf->main_vsi->nb_qps;
1970 if (pf->nb_cfg_vmdq_vsi)
1971 return queue_idx % pf->vmdq_nb_qps;
1973 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1974 return (uint16_t)(-1);
1979 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1981 struct i40e_rx_queue *rxq;
1983 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 PMD_INIT_FUNC_TRACE();
1987 if (rx_queue_id < dev->data->nb_rx_queues) {
1988 rxq = dev->data->rx_queues[rx_queue_id];
1990 err = i40e_alloc_rx_queue_mbufs(rxq);
1992 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1998 /* Init the RX tail regieter. */
1999 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2001 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2004 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2007 i40e_rx_queue_release_mbufs(rxq);
2008 i40e_reset_rx_queue(rxq);
2010 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2017 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2019 struct i40e_rx_queue *rxq;
2021 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023 if (rx_queue_id < dev->data->nb_rx_queues) {
2024 rxq = dev->data->rx_queues[rx_queue_id];
2027 * rx_queue_id is queue id aplication refers to, while
2028 * rxq->reg_idx is the real queue index.
2030 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2033 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2037 i40e_rx_queue_release_mbufs(rxq);
2038 i40e_reset_rx_queue(rxq);
2039 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2046 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2049 struct i40e_tx_queue *txq;
2050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052 PMD_INIT_FUNC_TRACE();
2054 if (tx_queue_id < dev->data->nb_tx_queues) {
2055 txq = dev->data->tx_queues[tx_queue_id];
2058 * tx_queue_id is queue id aplication refers to, while
2059 * rxq->reg_idx is the real queue index.
2061 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2063 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2066 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2073 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2075 struct i40e_tx_queue *txq;
2077 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 if (tx_queue_id < dev->data->nb_tx_queues) {
2080 txq = dev->data->tx_queues[tx_queue_id];
2083 * tx_queue_id is queue id aplication refers to, while
2084 * txq->reg_idx is the real queue index.
2086 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2089 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2094 i40e_tx_queue_release_mbufs(txq);
2095 i40e_reset_tx_queue(txq);
2096 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2103 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2106 unsigned int socket_id,
2107 const struct rte_eth_rxconf *rx_conf,
2108 struct rte_mempool *mp)
2110 struct i40e_vsi *vsi;
2111 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2113 struct i40e_adapter *ad =
2114 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2115 struct i40e_rx_queue *rxq;
2116 const struct rte_memzone *rz;
2119 uint16_t base, bsf, tc_mapping;
2120 int use_def_burst_func = 1;
2122 if (hw->mac.type == I40E_MAC_VF) {
2123 struct i40e_vf *vf =
2124 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2127 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2130 PMD_DRV_LOG(ERR, "VSI not available or queue "
2131 "index exceeds the maximum");
2132 return I40E_ERR_PARAM;
2134 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2135 (nb_desc > I40E_MAX_RING_DESC) ||
2136 (nb_desc < I40E_MIN_RING_DESC)) {
2137 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2138 "invalid", nb_desc);
2139 return I40E_ERR_PARAM;
2142 /* Free memory if needed */
2143 if (dev->data->rx_queues[queue_idx]) {
2144 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2145 dev->data->rx_queues[queue_idx] = NULL;
2148 /* Allocate the rx queue data structure */
2149 rxq = rte_zmalloc_socket("i40e rx queue",
2150 sizeof(struct i40e_rx_queue),
2151 RTE_CACHE_LINE_SIZE,
2154 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2155 "rx queue data structure");
2159 rxq->nb_rx_desc = nb_desc;
2160 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2161 rxq->queue_id = queue_idx;
2162 if (hw->mac.type == I40E_MAC_VF)
2163 rxq->reg_idx = queue_idx;
2164 else /* PF device */
2165 rxq->reg_idx = vsi->base_queue +
2166 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2168 rxq->port_id = dev->data->port_id;
2169 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2171 rxq->drop_en = rx_conf->rx_drop_en;
2173 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2175 /* Allocate the maximun number of RX ring hardware descriptor. */
2176 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2177 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2178 rz = i40e_ring_dma_zone_reserve(dev,
2184 i40e_dev_rx_queue_release(rxq);
2185 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2189 /* Zero all the descriptors in the ring. */
2190 memset(rz->addr, 0, ring_size);
2192 #ifdef RTE_LIBRTE_XEN_DOM0
2193 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2195 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2198 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2200 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2201 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2206 /* Allocate the software ring. */
2208 rte_zmalloc_socket("i40e rx sw ring",
2209 sizeof(struct i40e_rx_entry) * len,
2210 RTE_CACHE_LINE_SIZE,
2212 if (!rxq->sw_ring) {
2213 i40e_dev_rx_queue_release(rxq);
2214 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2218 i40e_reset_rx_queue(rxq);
2220 dev->data->rx_queues[queue_idx] = rxq;
2222 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2224 if (!use_def_burst_func) {
2225 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2226 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2227 "satisfied. Rx Burst Bulk Alloc function will be "
2228 "used on port=%d, queue=%d.",
2229 rxq->port_id, rxq->queue_id);
2230 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2232 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2233 "not satisfied, Scattered Rx is requested, "
2234 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2235 "not enabled on port=%d, queue=%d.",
2236 rxq->port_id, rxq->queue_id);
2237 ad->rx_bulk_alloc_allowed = false;
2240 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2241 if (!(vsi->enabled_tc & (1 << i)))
2243 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2244 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2245 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2246 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2247 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2249 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2257 i40e_dev_rx_queue_release(void *rxq)
2259 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2262 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2266 i40e_rx_queue_release_mbufs(q);
2267 rte_free(q->sw_ring);
2272 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2274 #define I40E_RXQ_SCAN_INTERVAL 4
2275 volatile union i40e_rx_desc *rxdp;
2276 struct i40e_rx_queue *rxq;
2279 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2280 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2284 rxq = dev->data->rx_queues[rx_queue_id];
2285 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2286 while ((desc < rxq->nb_rx_desc) &&
2287 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2288 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2289 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2291 * Check the DD bit of a rx descriptor of each 4 in a group,
2292 * to avoid checking too frequently and downgrading performance
2295 desc += I40E_RXQ_SCAN_INTERVAL;
2296 rxdp += I40E_RXQ_SCAN_INTERVAL;
2297 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2298 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2299 desc - rxq->nb_rx_desc]);
2306 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2308 volatile union i40e_rx_desc *rxdp;
2309 struct i40e_rx_queue *rxq = rx_queue;
2313 if (unlikely(offset >= rxq->nb_rx_desc)) {
2314 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2318 desc = rxq->rx_tail + offset;
2319 if (desc >= rxq->nb_rx_desc)
2320 desc -= rxq->nb_rx_desc;
2322 rxdp = &(rxq->rx_ring[desc]);
2324 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2325 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2326 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2332 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2335 unsigned int socket_id,
2336 const struct rte_eth_txconf *tx_conf)
2338 struct i40e_vsi *vsi;
2339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2341 struct i40e_tx_queue *txq;
2342 const struct rte_memzone *tz;
2344 uint16_t tx_rs_thresh, tx_free_thresh;
2345 uint16_t i, base, bsf, tc_mapping;
2347 if (hw->mac.type == I40E_MAC_VF) {
2348 struct i40e_vf *vf =
2349 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2352 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2355 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2356 "exceeds the maximum", queue_idx);
2357 return I40E_ERR_PARAM;
2360 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2361 (nb_desc > I40E_MAX_RING_DESC) ||
2362 (nb_desc < I40E_MIN_RING_DESC)) {
2363 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2364 "invalid", nb_desc);
2365 return I40E_ERR_PARAM;
2369 * The following two parameters control the setting of the RS bit on
2370 * transmit descriptors. TX descriptors will have their RS bit set
2371 * after txq->tx_rs_thresh descriptors have been used. The TX
2372 * descriptor ring will be cleaned after txq->tx_free_thresh
2373 * descriptors are used or if the number of descriptors required to
2374 * transmit a packet is greater than the number of free TX descriptors.
2376 * The following constraints must be satisfied:
2377 * - tx_rs_thresh must be greater than 0.
2378 * - tx_rs_thresh must be less than the size of the ring minus 2.
2379 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2380 * - tx_rs_thresh must be a divisor of the ring size.
2381 * - tx_free_thresh must be greater than 0.
2382 * - tx_free_thresh must be less than the size of the ring minus 3.
2384 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2385 * race condition, hence the maximum threshold constraints. When set
2386 * to zero use default values.
2388 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2389 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2390 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2391 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2392 if (tx_rs_thresh >= (nb_desc - 2)) {
2393 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2394 "number of TX descriptors minus 2. "
2395 "(tx_rs_thresh=%u port=%d queue=%d)",
2396 (unsigned int)tx_rs_thresh,
2397 (int)dev->data->port_id,
2399 return I40E_ERR_PARAM;
2401 if (tx_free_thresh >= (nb_desc - 3)) {
2402 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2403 "tx_free_thresh must be less than the "
2404 "number of TX descriptors minus 3. "
2405 "(tx_free_thresh=%u port=%d queue=%d)",
2406 (unsigned int)tx_free_thresh,
2407 (int)dev->data->port_id,
2409 return I40E_ERR_PARAM;
2411 if (tx_rs_thresh > tx_free_thresh) {
2412 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2413 "equal to tx_free_thresh. (tx_free_thresh=%u"
2414 " tx_rs_thresh=%u port=%d queue=%d)",
2415 (unsigned int)tx_free_thresh,
2416 (unsigned int)tx_rs_thresh,
2417 (int)dev->data->port_id,
2419 return I40E_ERR_PARAM;
2421 if ((nb_desc % tx_rs_thresh) != 0) {
2422 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2423 "number of TX descriptors. (tx_rs_thresh=%u"
2424 " port=%d queue=%d)",
2425 (unsigned int)tx_rs_thresh,
2426 (int)dev->data->port_id,
2428 return I40E_ERR_PARAM;
2430 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2431 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2432 "tx_rs_thresh is greater than 1. "
2433 "(tx_rs_thresh=%u port=%d queue=%d)",
2434 (unsigned int)tx_rs_thresh,
2435 (int)dev->data->port_id,
2437 return I40E_ERR_PARAM;
2440 /* Free memory if needed. */
2441 if (dev->data->tx_queues[queue_idx]) {
2442 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2443 dev->data->tx_queues[queue_idx] = NULL;
2446 /* Allocate the TX queue data structure. */
2447 txq = rte_zmalloc_socket("i40e tx queue",
2448 sizeof(struct i40e_tx_queue),
2449 RTE_CACHE_LINE_SIZE,
2452 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2453 "tx queue structure");
2457 /* Allocate TX hardware ring descriptors. */
2458 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2459 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2460 tz = i40e_ring_dma_zone_reserve(dev,
2466 i40e_dev_tx_queue_release(txq);
2467 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2471 txq->nb_tx_desc = nb_desc;
2472 txq->tx_rs_thresh = tx_rs_thresh;
2473 txq->tx_free_thresh = tx_free_thresh;
2474 txq->pthresh = tx_conf->tx_thresh.pthresh;
2475 txq->hthresh = tx_conf->tx_thresh.hthresh;
2476 txq->wthresh = tx_conf->tx_thresh.wthresh;
2477 txq->queue_id = queue_idx;
2478 if (hw->mac.type == I40E_MAC_VF)
2479 txq->reg_idx = queue_idx;
2480 else /* PF device */
2481 txq->reg_idx = vsi->base_queue +
2482 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2484 txq->port_id = dev->data->port_id;
2485 txq->txq_flags = tx_conf->txq_flags;
2487 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2489 #ifdef RTE_LIBRTE_XEN_DOM0
2490 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2492 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2494 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2496 /* Allocate software ring */
2498 rte_zmalloc_socket("i40e tx sw ring",
2499 sizeof(struct i40e_tx_entry) * nb_desc,
2500 RTE_CACHE_LINE_SIZE,
2502 if (!txq->sw_ring) {
2503 i40e_dev_tx_queue_release(txq);
2504 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2508 i40e_reset_tx_queue(txq);
2510 dev->data->tx_queues[queue_idx] = txq;
2512 /* Use a simple TX queue without offloads or multi segs if possible */
2513 i40e_set_tx_function_flag(dev, txq);
2515 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2516 if (!(vsi->enabled_tc & (1 << i)))
2518 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2519 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2520 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2521 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2522 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2524 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2532 i40e_dev_tx_queue_release(void *txq)
2534 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2537 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2541 i40e_tx_queue_release_mbufs(q);
2542 rte_free(q->sw_ring);
2546 static const struct rte_memzone *
2547 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2548 const char *ring_name,
2553 char z_name[RTE_MEMZONE_NAMESIZE];
2554 const struct rte_memzone *mz;
2556 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2557 dev->driver->pci_drv.name, ring_name,
2558 dev->data->port_id, queue_id);
2559 mz = rte_memzone_lookup(z_name);
2563 #ifdef RTE_LIBRTE_XEN_DOM0
2564 return rte_memzone_reserve_bounded(z_name, ring_size,
2565 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2567 return rte_memzone_reserve_aligned(z_name, ring_size,
2568 socket_id, 0, I40E_RING_BASE_ALIGN);
2572 const struct rte_memzone *
2573 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2575 const struct rte_memzone *mz = NULL;
2577 mz = rte_memzone_lookup(name);
2580 #ifdef RTE_LIBRTE_XEN_DOM0
2581 mz = rte_memzone_reserve_bounded(name, len,
2582 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2584 mz = rte_memzone_reserve_aligned(name, len,
2585 socket_id, 0, I40E_RING_BASE_ALIGN);
2591 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2595 /* SSE Vector driver has a different way of releasing mbufs. */
2596 if (rxq->rx_using_sse) {
2597 i40e_rx_queue_release_mbufs_vec(rxq);
2601 if (!rxq || !rxq->sw_ring) {
2602 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2606 for (i = 0; i < rxq->nb_rx_desc; i++) {
2607 if (rxq->sw_ring[i].mbuf) {
2608 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2609 rxq->sw_ring[i].mbuf = NULL;
2612 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2613 if (rxq->rx_nb_avail == 0)
2615 for (i = 0; i < rxq->rx_nb_avail; i++) {
2616 struct rte_mbuf *mbuf;
2618 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2619 rte_pktmbuf_free_seg(mbuf);
2621 rxq->rx_nb_avail = 0;
2622 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2626 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2632 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2636 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2637 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2638 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2640 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2641 len = rxq->nb_rx_desc;
2643 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2644 ((volatile char *)rxq->rx_ring)[i] = 0;
2646 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2647 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2648 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2649 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2651 rxq->rx_nb_avail = 0;
2652 rxq->rx_next_avail = 0;
2653 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2654 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2656 rxq->nb_rx_hold = 0;
2657 rxq->pkt_first_seg = NULL;
2658 rxq->pkt_last_seg = NULL;
2660 rxq->rxrearm_start = 0;
2661 rxq->rxrearm_nb = 0;
2665 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2669 if (!txq || !txq->sw_ring) {
2670 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2674 for (i = 0; i < txq->nb_tx_desc; i++) {
2675 if (txq->sw_ring[i].mbuf) {
2676 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2677 txq->sw_ring[i].mbuf = NULL;
2683 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2685 struct i40e_tx_entry *txe;
2686 uint16_t i, prev, size;
2689 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2694 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2695 for (i = 0; i < size; i++)
2696 ((volatile char *)txq->tx_ring)[i] = 0;
2698 prev = (uint16_t)(txq->nb_tx_desc - 1);
2699 for (i = 0; i < txq->nb_tx_desc; i++) {
2700 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2702 txd->cmd_type_offset_bsz =
2703 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2706 txe[prev].next_id = i;
2710 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2711 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2714 txq->nb_tx_used = 0;
2716 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2717 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2720 /* Init the TX queue in hardware */
2722 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2724 enum i40e_status_code err = I40E_SUCCESS;
2725 struct i40e_vsi *vsi = txq->vsi;
2726 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2727 uint16_t pf_q = txq->reg_idx;
2728 struct i40e_hmc_obj_txq tx_ctx;
2731 /* clear the context structure first */
2732 memset(&tx_ctx, 0, sizeof(tx_ctx));
2733 tx_ctx.new_context = 1;
2734 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2735 tx_ctx.qlen = txq->nb_tx_desc;
2737 #ifdef RTE_LIBRTE_IEEE1588
2738 tx_ctx.timesync_ena = 1;
2740 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2741 if (vsi->type == I40E_VSI_FDIR)
2742 tx_ctx.fd_ena = TRUE;
2744 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2745 if (err != I40E_SUCCESS) {
2746 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2750 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2751 if (err != I40E_SUCCESS) {
2752 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2756 /* Now associate this queue with this PCI function */
2757 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2758 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2759 I40E_QTX_CTL_PF_INDX_MASK);
2760 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2761 I40E_WRITE_FLUSH(hw);
2763 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2769 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2771 struct i40e_rx_entry *rxe = rxq->sw_ring;
2775 for (i = 0; i < rxq->nb_rx_desc; i++) {
2776 volatile union i40e_rx_desc *rxd;
2777 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2779 if (unlikely(!mbuf)) {
2780 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2784 rte_mbuf_refcnt_set(mbuf, 1);
2786 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2788 mbuf->port = rxq->port_id;
2791 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2793 rxd = &rxq->rx_ring[i];
2794 rxd->read.pkt_addr = dma_addr;
2795 rxd->read.hdr_addr = 0;
2796 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2797 rxd->read.rsvd1 = 0;
2798 rxd->read.rsvd2 = 0;
2799 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2808 * Calculate the buffer length, and check the jumbo frame
2809 * and maximum packet length.
2812 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2814 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2815 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2816 struct rte_eth_dev_data *data = pf->dev_data;
2817 uint16_t buf_size, len;
2819 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2820 RTE_PKTMBUF_HEADROOM);
2822 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2823 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2824 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2825 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2826 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2827 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2828 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2829 rxq->hs_mode = i40e_header_split_enabled;
2831 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2833 rxq->rx_hdr_len = 0;
2834 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2835 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2836 rxq->hs_mode = i40e_header_split_none;
2840 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2841 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2842 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2843 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2844 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2845 PMD_DRV_LOG(ERR, "maximum packet length must "
2846 "be larger than %u and smaller than %u,"
2847 "as jumbo frame is enabled",
2848 (uint32_t)ETHER_MAX_LEN,
2849 (uint32_t)I40E_FRAME_SIZE_MAX);
2850 return I40E_ERR_CONFIG;
2853 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2854 rxq->max_pkt_len > ETHER_MAX_LEN) {
2855 PMD_DRV_LOG(ERR, "maximum packet length must be "
2856 "larger than %u and smaller than %u, "
2857 "as jumbo frame is disabled",
2858 (uint32_t)ETHER_MIN_LEN,
2859 (uint32_t)ETHER_MAX_LEN);
2860 return I40E_ERR_CONFIG;
2867 /* Init the RX queue in hardware */
2869 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2871 int err = I40E_SUCCESS;
2872 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2873 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2874 uint16_t pf_q = rxq->reg_idx;
2876 struct i40e_hmc_obj_rxq rx_ctx;
2878 err = i40e_rx_queue_config(rxq);
2880 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2884 /* Clear the context structure first */
2885 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2886 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2887 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2889 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2890 rx_ctx.qlen = rxq->nb_rx_desc;
2891 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2894 rx_ctx.dtype = rxq->hs_mode;
2896 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2898 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2899 rx_ctx.rxmax = rxq->max_pkt_len;
2900 rx_ctx.tphrdesc_ena = 1;
2901 rx_ctx.tphwdesc_ena = 1;
2902 rx_ctx.tphdata_ena = 1;
2903 rx_ctx.tphhead_ena = 1;
2904 rx_ctx.lrxqthresh = 2;
2905 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2910 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2911 if (err != I40E_SUCCESS) {
2912 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2915 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2916 if (err != I40E_SUCCESS) {
2917 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2921 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2923 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2924 RTE_PKTMBUF_HEADROOM);
2926 /* Check if scattered RX needs to be used. */
2927 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2928 dev_data->scattered_rx = 1;
2931 /* Init the RX tail regieter. */
2932 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2938 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2942 PMD_INIT_FUNC_TRACE();
2944 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2945 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2946 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2949 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2950 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2951 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2956 i40e_dev_free_queues(struct rte_eth_dev *dev)
2960 PMD_INIT_FUNC_TRACE();
2962 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2963 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2964 dev->data->rx_queues[i] = NULL;
2966 dev->data->nb_rx_queues = 0;
2968 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2969 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2970 dev->data->tx_queues[i] = NULL;
2972 dev->data->nb_tx_queues = 0;
2975 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2976 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2978 enum i40e_status_code
2979 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2981 struct i40e_tx_queue *txq;
2982 const struct rte_memzone *tz = NULL;
2984 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2987 PMD_DRV_LOG(ERR, "PF is not available");
2988 return I40E_ERR_BAD_PTR;
2991 /* Allocate the TX queue data structure. */
2992 txq = rte_zmalloc_socket("i40e fdir tx queue",
2993 sizeof(struct i40e_tx_queue),
2994 RTE_CACHE_LINE_SIZE,
2997 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2998 "tx queue structure.");
2999 return I40E_ERR_NO_MEMORY;
3002 /* Allocate TX hardware ring descriptors. */
3003 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3004 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3006 tz = i40e_ring_dma_zone_reserve(dev,
3012 i40e_dev_tx_queue_release(txq);
3013 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3014 return I40E_ERR_NO_MEMORY;
3017 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3018 txq->queue_id = I40E_FDIR_QUEUE_ID;
3019 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3020 txq->vsi = pf->fdir.fdir_vsi;
3022 #ifdef RTE_LIBRTE_XEN_DOM0
3023 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3025 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
3027 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3029 * don't need to allocate software ring and reset for the fdir
3030 * program queue just set the queue has been configured.
3035 return I40E_SUCCESS;
3038 enum i40e_status_code
3039 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3041 struct i40e_rx_queue *rxq;
3042 const struct rte_memzone *rz = NULL;
3044 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3047 PMD_DRV_LOG(ERR, "PF is not available");
3048 return I40E_ERR_BAD_PTR;
3051 /* Allocate the RX queue data structure. */
3052 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3053 sizeof(struct i40e_rx_queue),
3054 RTE_CACHE_LINE_SIZE,
3057 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3058 "rx queue structure.");
3059 return I40E_ERR_NO_MEMORY;
3062 /* Allocate RX hardware ring descriptors. */
3063 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3064 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3066 rz = i40e_ring_dma_zone_reserve(dev,
3072 i40e_dev_rx_queue_release(rxq);
3073 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3074 return I40E_ERR_NO_MEMORY;
3077 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3078 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3079 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3080 rxq->vsi = pf->fdir.fdir_vsi;
3082 #ifdef RTE_LIBRTE_XEN_DOM0
3083 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3085 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
3087 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3090 * Don't need to allocate software ring and reset for the fdir
3091 * rx queue, just set the queue has been configured.
3096 return I40E_SUCCESS;
3100 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3101 struct rte_eth_rxq_info *qinfo)
3103 struct i40e_rx_queue *rxq;
3105 rxq = dev->data->rx_queues[queue_id];
3107 qinfo->mp = rxq->mp;
3108 qinfo->scattered_rx = dev->data->scattered_rx;
3109 qinfo->nb_desc = rxq->nb_rx_desc;
3111 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3112 qinfo->conf.rx_drop_en = rxq->drop_en;
3113 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3117 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3118 struct rte_eth_txq_info *qinfo)
3120 struct i40e_tx_queue *txq;
3122 txq = dev->data->tx_queues[queue_id];
3124 qinfo->nb_desc = txq->nb_tx_desc;
3126 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3127 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3128 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3130 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3131 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3132 qinfo->conf.txq_flags = txq->txq_flags;
3133 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3136 void __attribute__((cold))
3137 i40e_set_rx_function(struct rte_eth_dev *dev)
3139 struct i40e_adapter *ad =
3140 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3141 uint16_t rx_using_sse, i;
3142 /* In order to allow Vector Rx there are a few configuration
3143 * conditions to be met and Rx Bulk Allocation should be allowed.
3145 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3146 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3147 !ad->rx_bulk_alloc_allowed) {
3148 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3149 " Vector Rx preconditions",
3150 dev->data->port_id);
3152 ad->rx_vec_allowed = false;
3154 if (ad->rx_vec_allowed) {
3155 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3156 struct i40e_rx_queue *rxq =
3157 dev->data->rx_queues[i];
3159 if (i40e_rxq_vec_setup(rxq)) {
3160 ad->rx_vec_allowed = false;
3167 if (dev->data->scattered_rx) {
3168 /* Set the non-LRO scattered callback: there are Vector and
3169 * single allocation versions.
3171 if (ad->rx_vec_allowed) {
3172 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3173 "callback (port=%d).",
3174 dev->data->port_id);
3176 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3178 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3179 "allocation callback (port=%d).",
3180 dev->data->port_id);
3181 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3183 /* If parameters allow we are going to choose between the following
3187 * - Single buffer allocation (the simplest one)
3189 } else if (ad->rx_vec_allowed) {
3190 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3191 "burst size no less than %d (port=%d).",
3192 RTE_I40E_DESCS_PER_LOOP,
3193 dev->data->port_id);
3195 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3196 } else if (ad->rx_bulk_alloc_allowed) {
3197 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3198 "satisfied. Rx Burst Bulk Alloc function "
3199 "will be used on port=%d.",
3200 dev->data->port_id);
3202 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3204 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3205 "satisfied, or Scattered Rx is requested "
3207 dev->data->port_id);
3209 dev->rx_pkt_burst = i40e_recv_pkts;
3212 /* Propagate information about RX function choice through all queues. */
3213 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3215 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3216 dev->rx_pkt_burst == i40e_recv_pkts_vec);
3218 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3219 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3221 rxq->rx_using_sse = rx_using_sse;
3226 void __attribute__((cold))
3227 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3229 struct i40e_adapter *ad =
3230 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3232 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3233 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3234 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3235 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3236 PMD_INIT_LOG(DEBUG, "Vector tx"
3237 " can be enabled on this txq.");
3240 ad->tx_vec_allowed = false;
3243 ad->tx_simple_allowed = false;
3247 void __attribute__((cold))
3248 i40e_set_tx_function(struct rte_eth_dev *dev)
3250 struct i40e_adapter *ad =
3251 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3254 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3255 if (ad->tx_vec_allowed) {
3256 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3257 struct i40e_tx_queue *txq =
3258 dev->data->tx_queues[i];
3260 if (i40e_txq_vec_setup(txq)) {
3261 ad->tx_vec_allowed = false;
3268 if (ad->tx_simple_allowed) {
3269 if (ad->tx_vec_allowed) {
3270 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3271 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3273 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3274 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3277 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3278 dev->tx_pkt_burst = i40e_xmit_pkts;
3282 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3283 int __attribute__((weak))
3284 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3289 uint16_t __attribute__((weak))
3291 void __rte_unused *rx_queue,
3292 struct rte_mbuf __rte_unused **rx_pkts,
3293 uint16_t __rte_unused nb_pkts)
3298 uint16_t __attribute__((weak))
3299 i40e_recv_scattered_pkts_vec(
3300 void __rte_unused *rx_queue,
3301 struct rte_mbuf __rte_unused **rx_pkts,
3302 uint16_t __rte_unused nb_pkts)
3307 int __attribute__((weak))
3308 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3313 int __attribute__((weak))
3314 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3319 void __attribute__((weak))
3320 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3325 uint16_t __attribute__((weak))
3326 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3327 struct rte_mbuf __rte_unused **tx_pkts,
3328 uint16_t __rte_unused nb_pkts)