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42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define DEFAULT_TX_RS_THRESH 32
61 #define DEFAULT_TX_FREE_THRESH 32
62 #define I40E_MAX_PKT_TYPE 256
64 #define I40E_TX_MAX_BURST 32
66 #define I40E_DMA_MEM_ALIGN 4096
68 /* Base address of the HW descriptor ring should be 128B aligned. */
69 #define I40E_RING_BASE_ALIGN 128
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
80 PKT_TX_OUTER_IP_CKSUM)
82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
83 struct rte_mbuf **tx_pkts,
87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
89 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
90 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
91 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
93 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
94 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
95 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
100 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
101 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
102 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
103 mb->vlan_tci_outer = mb->vlan_tci;
104 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
105 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
106 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
107 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
109 mb->vlan_tci_outer = 0;
112 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
113 mb->vlan_tci, mb->vlan_tci_outer);
116 /* Translate the rx descriptor status to pkt flags */
117 static inline uint64_t
118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
122 /* Check if RSS_HASH */
123 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
124 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
125 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
127 /* Check if FDIR Match */
128 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
134 static inline uint64_t
135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
138 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
140 #define I40E_RX_ERR_BITS 0x3f
141 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
143 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
144 flags |= PKT_RX_IP_CKSUM_BAD;
145 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
146 flags |= PKT_RX_L4_CKSUM_BAD;
147 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
148 flags |= PKT_RX_EIP_CKSUM_BAD;
153 /* Function to check and set the ieee1588 timesync index and get the
156 #ifdef RTE_LIBRTE_IEEE1588
157 static inline uint64_t
158 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
160 uint64_t pkt_flags = 0;
161 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
162 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
163 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
165 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
166 == RTE_PTYPE_L2_ETHER_TIMESYNC)
167 pkt_flags = PKT_RX_IEEE1588_PTP;
169 pkt_flags |= PKT_RX_IEEE1588_TMST;
170 mb->timesync = tsyn & 0x03;
177 /* For each value it means, datasheet of hardware can tell more details
179 * @note: fix i40e_dev_supported_ptypes_get() if any change here.
181 static inline uint32_t
182 i40e_rxd_pkt_type_mapping(uint8_t ptype)
184 static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
187 [1] = RTE_PTYPE_L2_ETHER,
188 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
189 /* [3] - [5] reserved */
190 [6] = RTE_PTYPE_L2_ETHER_LLDP,
191 /* [7] - [10] reserved */
192 [11] = RTE_PTYPE_L2_ETHER_ARP,
193 /* [12] - [21] reserved */
195 /* Non tunneled IPv4 */
196 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
199 RTE_PTYPE_L4_NONFRAG,
200 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 RTE_PTYPE_TUNNEL_IP |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_FRAG,
215 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
216 RTE_PTYPE_TUNNEL_IP |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_NONFRAG,
219 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_TUNNEL_IP |
221 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_UDP,
224 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_TUNNEL_IP |
226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_TCP,
228 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
229 RTE_PTYPE_TUNNEL_IP |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_SCTP,
232 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_TUNNEL_IP |
234 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_ICMP,
238 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_TUNNEL_IP |
240 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L4_FRAG,
242 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_TUNNEL_IP |
244 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L4_NONFRAG,
246 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
247 RTE_PTYPE_TUNNEL_IP |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_UDP,
251 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_TUNNEL_IP |
253 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L4_TCP,
255 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_TUNNEL_IP |
257 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_SCTP,
259 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
260 RTE_PTYPE_TUNNEL_IP |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_ICMP,
264 /* IPv4 --> GRE/Teredo/VXLAN */
265 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
266 RTE_PTYPE_TUNNEL_GRENAT,
268 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
269 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_TUNNEL_GRENAT |
271 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_FRAG,
273 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
274 RTE_PTYPE_TUNNEL_GRENAT |
275 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L4_NONFRAG,
277 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
278 RTE_PTYPE_TUNNEL_GRENAT |
279 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L4_UDP,
282 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_TUNNEL_GRENAT |
284 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
285 RTE_PTYPE_INNER_L4_TCP,
286 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
287 RTE_PTYPE_TUNNEL_GRENAT |
288 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
289 RTE_PTYPE_INNER_L4_SCTP,
290 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
291 RTE_PTYPE_TUNNEL_GRENAT |
292 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
293 RTE_PTYPE_INNER_L4_ICMP,
295 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
296 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
297 RTE_PTYPE_TUNNEL_GRENAT |
298 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
299 RTE_PTYPE_INNER_L4_FRAG,
300 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
301 RTE_PTYPE_TUNNEL_GRENAT |
302 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
303 RTE_PTYPE_INNER_L4_NONFRAG,
304 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
305 RTE_PTYPE_TUNNEL_GRENAT |
306 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
307 RTE_PTYPE_INNER_L4_UDP,
309 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
310 RTE_PTYPE_TUNNEL_GRENAT |
311 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
312 RTE_PTYPE_INNER_L4_TCP,
313 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_TUNNEL_GRENAT |
315 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
316 RTE_PTYPE_INNER_L4_SCTP,
317 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
318 RTE_PTYPE_TUNNEL_GRENAT |
319 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
320 RTE_PTYPE_INNER_L4_ICMP,
322 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
323 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
324 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
326 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
327 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
328 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
329 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
330 RTE_PTYPE_INNER_L4_FRAG,
331 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
332 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
333 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
334 RTE_PTYPE_INNER_L4_NONFRAG,
335 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
336 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
337 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
338 RTE_PTYPE_INNER_L4_UDP,
340 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
341 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
342 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
343 RTE_PTYPE_INNER_L4_TCP,
344 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
345 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
346 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
347 RTE_PTYPE_INNER_L4_SCTP,
348 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
349 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
350 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
351 RTE_PTYPE_INNER_L4_ICMP,
353 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
354 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
355 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
356 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
357 RTE_PTYPE_INNER_L4_FRAG,
358 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
359 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
360 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
361 RTE_PTYPE_INNER_L4_NONFRAG,
362 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
363 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
364 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
365 RTE_PTYPE_INNER_L4_UDP,
367 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
368 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
369 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
370 RTE_PTYPE_INNER_L4_TCP,
371 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
372 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
373 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
374 RTE_PTYPE_INNER_L4_SCTP,
375 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
376 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
377 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
378 RTE_PTYPE_INNER_L4_ICMP,
380 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
381 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
382 RTE_PTYPE_TUNNEL_GRENAT |
383 RTE_PTYPE_INNER_L2_ETHER_VLAN,
385 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
386 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
387 RTE_PTYPE_TUNNEL_GRENAT |
388 RTE_PTYPE_INNER_L2_ETHER_VLAN |
389 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
390 RTE_PTYPE_INNER_L4_FRAG,
391 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
392 RTE_PTYPE_TUNNEL_GRENAT |
393 RTE_PTYPE_INNER_L2_ETHER_VLAN |
394 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
395 RTE_PTYPE_INNER_L4_NONFRAG,
396 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
397 RTE_PTYPE_TUNNEL_GRENAT |
398 RTE_PTYPE_INNER_L2_ETHER_VLAN |
399 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
400 RTE_PTYPE_INNER_L4_UDP,
402 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
403 RTE_PTYPE_TUNNEL_GRENAT |
404 RTE_PTYPE_INNER_L2_ETHER_VLAN |
405 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
406 RTE_PTYPE_INNER_L4_TCP,
407 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
408 RTE_PTYPE_TUNNEL_GRENAT |
409 RTE_PTYPE_INNER_L2_ETHER_VLAN |
410 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
411 RTE_PTYPE_INNER_L4_SCTP,
412 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
413 RTE_PTYPE_TUNNEL_GRENAT |
414 RTE_PTYPE_INNER_L2_ETHER_VLAN |
415 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
416 RTE_PTYPE_INNER_L4_ICMP,
418 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
419 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
420 RTE_PTYPE_TUNNEL_GRENAT |
421 RTE_PTYPE_INNER_L2_ETHER_VLAN |
422 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
423 RTE_PTYPE_INNER_L4_FRAG,
424 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
425 RTE_PTYPE_TUNNEL_GRENAT |
426 RTE_PTYPE_INNER_L2_ETHER_VLAN |
427 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
428 RTE_PTYPE_INNER_L4_NONFRAG,
429 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
430 RTE_PTYPE_TUNNEL_GRENAT |
431 RTE_PTYPE_INNER_L2_ETHER_VLAN |
432 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
433 RTE_PTYPE_INNER_L4_UDP,
435 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
436 RTE_PTYPE_TUNNEL_GRENAT |
437 RTE_PTYPE_INNER_L2_ETHER_VLAN |
438 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
439 RTE_PTYPE_INNER_L4_TCP,
440 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
441 RTE_PTYPE_TUNNEL_GRENAT |
442 RTE_PTYPE_INNER_L2_ETHER_VLAN |
443 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
444 RTE_PTYPE_INNER_L4_SCTP,
445 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
446 RTE_PTYPE_TUNNEL_GRENAT |
447 RTE_PTYPE_INNER_L2_ETHER_VLAN |
448 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
449 RTE_PTYPE_INNER_L4_ICMP,
451 /* Non tunneled IPv6 */
452 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
454 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
455 RTE_PTYPE_L4_NONFRAG,
456 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
459 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
461 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
463 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
467 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
468 RTE_PTYPE_TUNNEL_IP |
469 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
470 RTE_PTYPE_INNER_L4_FRAG,
471 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
472 RTE_PTYPE_TUNNEL_IP |
473 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
474 RTE_PTYPE_INNER_L4_NONFRAG,
475 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
476 RTE_PTYPE_TUNNEL_IP |
477 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
478 RTE_PTYPE_INNER_L4_UDP,
480 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
481 RTE_PTYPE_TUNNEL_IP |
482 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
483 RTE_PTYPE_INNER_L4_TCP,
484 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
485 RTE_PTYPE_TUNNEL_IP |
486 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
487 RTE_PTYPE_INNER_L4_SCTP,
488 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
489 RTE_PTYPE_TUNNEL_IP |
490 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
491 RTE_PTYPE_INNER_L4_ICMP,
494 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
495 RTE_PTYPE_TUNNEL_IP |
496 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
497 RTE_PTYPE_INNER_L4_FRAG,
498 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
499 RTE_PTYPE_TUNNEL_IP |
500 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
501 RTE_PTYPE_INNER_L4_NONFRAG,
502 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
503 RTE_PTYPE_TUNNEL_IP |
504 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
505 RTE_PTYPE_INNER_L4_UDP,
507 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
508 RTE_PTYPE_TUNNEL_IP |
509 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
510 RTE_PTYPE_INNER_L4_TCP,
511 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
512 RTE_PTYPE_TUNNEL_IP |
513 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
514 RTE_PTYPE_INNER_L4_SCTP,
515 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
516 RTE_PTYPE_TUNNEL_IP |
517 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
518 RTE_PTYPE_INNER_L4_ICMP,
520 /* IPv6 --> GRE/Teredo/VXLAN */
521 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
522 RTE_PTYPE_TUNNEL_GRENAT,
524 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
525 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
526 RTE_PTYPE_TUNNEL_GRENAT |
527 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
528 RTE_PTYPE_INNER_L4_FRAG,
529 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
530 RTE_PTYPE_TUNNEL_GRENAT |
531 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
532 RTE_PTYPE_INNER_L4_NONFRAG,
533 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
534 RTE_PTYPE_TUNNEL_GRENAT |
535 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
536 RTE_PTYPE_INNER_L4_UDP,
538 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
539 RTE_PTYPE_TUNNEL_GRENAT |
540 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
541 RTE_PTYPE_INNER_L4_TCP,
542 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
543 RTE_PTYPE_TUNNEL_GRENAT |
544 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
545 RTE_PTYPE_INNER_L4_SCTP,
546 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
547 RTE_PTYPE_TUNNEL_GRENAT |
548 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
549 RTE_PTYPE_INNER_L4_ICMP,
551 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
552 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
553 RTE_PTYPE_TUNNEL_GRENAT |
554 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
555 RTE_PTYPE_INNER_L4_FRAG,
556 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
557 RTE_PTYPE_TUNNEL_GRENAT |
558 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
559 RTE_PTYPE_INNER_L4_NONFRAG,
560 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
561 RTE_PTYPE_TUNNEL_GRENAT |
562 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
563 RTE_PTYPE_INNER_L4_UDP,
565 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
566 RTE_PTYPE_TUNNEL_GRENAT |
567 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
568 RTE_PTYPE_INNER_L4_TCP,
569 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
570 RTE_PTYPE_TUNNEL_GRENAT |
571 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
572 RTE_PTYPE_INNER_L4_SCTP,
573 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
574 RTE_PTYPE_TUNNEL_GRENAT |
575 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
576 RTE_PTYPE_INNER_L4_ICMP,
578 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
579 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
580 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
582 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
583 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
584 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
585 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
586 RTE_PTYPE_INNER_L4_FRAG,
587 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
588 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
589 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
590 RTE_PTYPE_INNER_L4_NONFRAG,
591 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
592 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
593 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
594 RTE_PTYPE_INNER_L4_UDP,
596 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
597 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
598 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
599 RTE_PTYPE_INNER_L4_TCP,
600 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
601 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
602 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
603 RTE_PTYPE_INNER_L4_SCTP,
604 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
605 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
606 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
607 RTE_PTYPE_INNER_L4_ICMP,
609 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
610 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
611 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
612 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
613 RTE_PTYPE_INNER_L4_FRAG,
614 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
615 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
616 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
617 RTE_PTYPE_INNER_L4_NONFRAG,
618 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
619 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
620 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
621 RTE_PTYPE_INNER_L4_UDP,
623 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
624 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
625 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
626 RTE_PTYPE_INNER_L4_TCP,
627 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
628 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
629 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
630 RTE_PTYPE_INNER_L4_SCTP,
631 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
632 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
633 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
634 RTE_PTYPE_INNER_L4_ICMP,
636 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
637 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
638 RTE_PTYPE_TUNNEL_GRENAT |
639 RTE_PTYPE_INNER_L2_ETHER_VLAN,
641 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
642 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
643 RTE_PTYPE_TUNNEL_GRENAT |
644 RTE_PTYPE_INNER_L2_ETHER_VLAN |
645 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
646 RTE_PTYPE_INNER_L4_FRAG,
647 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
648 RTE_PTYPE_TUNNEL_GRENAT |
649 RTE_PTYPE_INNER_L2_ETHER_VLAN |
650 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
651 RTE_PTYPE_INNER_L4_NONFRAG,
652 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
653 RTE_PTYPE_TUNNEL_GRENAT |
654 RTE_PTYPE_INNER_L2_ETHER_VLAN |
655 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
656 RTE_PTYPE_INNER_L4_UDP,
658 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
659 RTE_PTYPE_TUNNEL_GRENAT |
660 RTE_PTYPE_INNER_L2_ETHER_VLAN |
661 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
662 RTE_PTYPE_INNER_L4_TCP,
663 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
664 RTE_PTYPE_TUNNEL_GRENAT |
665 RTE_PTYPE_INNER_L2_ETHER_VLAN |
666 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
667 RTE_PTYPE_INNER_L4_SCTP,
668 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
669 RTE_PTYPE_TUNNEL_GRENAT |
670 RTE_PTYPE_INNER_L2_ETHER_VLAN |
671 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
672 RTE_PTYPE_INNER_L4_ICMP,
674 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
675 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
676 RTE_PTYPE_TUNNEL_GRENAT |
677 RTE_PTYPE_INNER_L2_ETHER_VLAN |
678 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
679 RTE_PTYPE_INNER_L4_FRAG,
680 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
681 RTE_PTYPE_TUNNEL_GRENAT |
682 RTE_PTYPE_INNER_L2_ETHER_VLAN |
683 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
684 RTE_PTYPE_INNER_L4_NONFRAG,
685 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
686 RTE_PTYPE_TUNNEL_GRENAT |
687 RTE_PTYPE_INNER_L2_ETHER_VLAN |
688 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
689 RTE_PTYPE_INNER_L4_UDP,
691 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
692 RTE_PTYPE_TUNNEL_GRENAT |
693 RTE_PTYPE_INNER_L2_ETHER_VLAN |
694 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
695 RTE_PTYPE_INNER_L4_TCP,
696 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
697 RTE_PTYPE_TUNNEL_GRENAT |
698 RTE_PTYPE_INNER_L2_ETHER_VLAN |
699 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
700 RTE_PTYPE_INNER_L4_SCTP,
701 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
702 RTE_PTYPE_TUNNEL_GRENAT |
703 RTE_PTYPE_INNER_L2_ETHER_VLAN |
704 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
705 RTE_PTYPE_INNER_L4_ICMP,
707 /* L2 NSH packet type */
708 [154] = RTE_PTYPE_L2_ETHER_NSH,
709 [155] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
711 [156] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
712 RTE_PTYPE_L4_NONFRAG,
713 [157] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
715 [158] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
717 [159] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
719 [160] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
721 [161] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
723 [162] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
724 RTE_PTYPE_L4_NONFRAG,
725 [163] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
727 [164] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
729 [165] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
731 [166] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
734 /* All others reserved */
737 return type_table[ptype];
740 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
741 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
742 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
743 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
744 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
746 static inline uint64_t
747 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
750 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
751 uint16_t flexbh, flexbl;
753 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
754 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
755 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
756 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
757 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
758 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
761 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
763 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
764 flags |= PKT_RX_FDIR_ID;
765 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
767 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
768 flags |= PKT_RX_FDIR_FLX;
770 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
772 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
773 flags |= PKT_RX_FDIR_FLX;
777 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
778 flags |= PKT_RX_FDIR_ID;
783 i40e_txd_enable_checksum(uint64_t ol_flags,
786 union i40e_tx_offload tx_offload,
787 uint32_t *cd_tunneling)
789 /* UDP tunneling packet TX checksum offload */
790 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
792 *td_offset |= (tx_offload.outer_l2_len >> 1)
793 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
795 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
796 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
797 else if (ol_flags & PKT_TX_OUTER_IPV4)
798 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
799 else if (ol_flags & PKT_TX_OUTER_IPV6)
800 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
802 /* Now set the ctx descriptor fields */
803 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
804 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
805 (tx_offload.l2_len >> 1) <<
806 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
809 *td_offset |= (tx_offload.l2_len >> 1)
810 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
812 /* Enable L3 checksum offloads */
813 if (ol_flags & PKT_TX_IP_CKSUM) {
814 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
815 *td_offset |= (tx_offload.l3_len >> 2)
816 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
817 } else if (ol_flags & PKT_TX_IPV4) {
818 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
819 *td_offset |= (tx_offload.l3_len >> 2)
820 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
821 } else if (ol_flags & PKT_TX_IPV6) {
822 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
823 *td_offset |= (tx_offload.l3_len >> 2)
824 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
827 if (ol_flags & PKT_TX_TCP_SEG) {
828 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
829 *td_offset |= (tx_offload.l4_len >> 2)
830 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
834 /* Enable L4 checksum offloads */
835 switch (ol_flags & PKT_TX_L4_MASK) {
836 case PKT_TX_TCP_CKSUM:
837 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
838 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
839 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
841 case PKT_TX_SCTP_CKSUM:
842 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
843 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
844 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
846 case PKT_TX_UDP_CKSUM:
847 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
848 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
849 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
856 /* Construct the tx flags */
857 static inline uint64_t
858 i40e_build_ctob(uint32_t td_cmd,
863 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
864 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
865 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
866 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
867 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
871 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
873 struct i40e_tx_entry *sw_ring = txq->sw_ring;
874 volatile struct i40e_tx_desc *txd = txq->tx_ring;
875 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
876 uint16_t nb_tx_desc = txq->nb_tx_desc;
877 uint16_t desc_to_clean_to;
878 uint16_t nb_tx_to_clean;
880 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
881 if (desc_to_clean_to >= nb_tx_desc)
882 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
884 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
885 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
886 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
887 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
888 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
889 "(port=%d queue=%d)", desc_to_clean_to,
890 txq->port_id, txq->queue_id);
894 if (last_desc_cleaned > desc_to_clean_to)
895 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
898 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
901 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
903 txq->last_desc_cleaned = desc_to_clean_to;
904 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
910 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
911 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
913 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
918 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
919 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
920 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
921 "rxq->rx_free_thresh=%d, "
922 "RTE_PMD_I40E_RX_MAX_BURST=%d",
923 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
925 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
926 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
927 "rxq->rx_free_thresh=%d, "
928 "rxq->nb_rx_desc=%d",
929 rxq->rx_free_thresh, rxq->nb_rx_desc);
931 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
932 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
933 "rxq->nb_rx_desc=%d, "
934 "rxq->rx_free_thresh=%d",
935 rxq->nb_rx_desc, rxq->rx_free_thresh);
937 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
938 RTE_PMD_I40E_RX_MAX_BURST))) {
939 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
940 "rxq->nb_rx_desc=%d, "
941 "I40E_MAX_RING_DESC=%d, "
942 "RTE_PMD_I40E_RX_MAX_BURST=%d",
943 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
944 RTE_PMD_I40E_RX_MAX_BURST);
954 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
955 #define I40E_LOOK_AHEAD 8
956 #if (I40E_LOOK_AHEAD != 8)
957 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
960 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
962 volatile union i40e_rx_desc *rxdp;
963 struct i40e_rx_entry *rxep;
968 int32_t s[I40E_LOOK_AHEAD], nb_dd;
969 int32_t i, j, nb_rx = 0;
972 rxdp = &rxq->rx_ring[rxq->rx_tail];
973 rxep = &rxq->sw_ring[rxq->rx_tail];
975 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
976 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
977 I40E_RXD_QW1_STATUS_SHIFT;
979 /* Make sure there is at least 1 packet to receive */
980 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
984 * Scan LOOK_AHEAD descriptors at a time to determine which
985 * descriptors reference packets that are ready to be received.
987 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
988 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
989 /* Read desc statuses backwards to avoid race condition */
990 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
991 qword1 = rte_le_to_cpu_64(\
992 rxdp[j].wb.qword1.status_error_len);
993 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
994 I40E_RXD_QW1_STATUS_SHIFT;
999 /* Compute how many status bits were set */
1000 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1001 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1005 /* Translate descriptor info to mbuf parameters */
1006 for (j = 0; j < nb_dd; j++) {
1008 qword1 = rte_le_to_cpu_64(\
1009 rxdp[j].wb.qword1.status_error_len);
1010 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1011 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1012 mb->data_len = pkt_len;
1013 mb->pkt_len = pkt_len;
1015 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1016 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1017 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1019 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1020 I40E_RXD_QW1_PTYPE_MASK) >>
1021 I40E_RXD_QW1_PTYPE_SHIFT));
1022 if (pkt_flags & PKT_RX_RSS_HASH)
1023 mb->hash.rss = rte_le_to_cpu_32(\
1024 rxdp[j].wb.qword0.hi_dword.rss);
1025 if (pkt_flags & PKT_RX_FDIR)
1026 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1028 #ifdef RTE_LIBRTE_IEEE1588
1029 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1031 mb->ol_flags |= pkt_flags;
1035 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1036 rxq->rx_stage[i + j] = rxep[j].mbuf;
1038 if (nb_dd != I40E_LOOK_AHEAD)
1042 /* Clear software ring entries */
1043 for (i = 0; i < nb_rx; i++)
1044 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1049 static inline uint16_t
1050 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1051 struct rte_mbuf **rx_pkts,
1055 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1057 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1059 for (i = 0; i < nb_pkts; i++)
1060 rx_pkts[i] = stage[i];
1062 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1063 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1069 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1071 volatile union i40e_rx_desc *rxdp;
1072 struct i40e_rx_entry *rxep;
1073 struct rte_mbuf *mb;
1074 uint16_t alloc_idx, i;
1078 /* Allocate buffers in bulk */
1079 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1080 (rxq->rx_free_thresh - 1));
1081 rxep = &(rxq->sw_ring[alloc_idx]);
1082 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1083 rxq->rx_free_thresh);
1084 if (unlikely(diag != 0)) {
1085 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1089 rxdp = &rxq->rx_ring[alloc_idx];
1090 for (i = 0; i < rxq->rx_free_thresh; i++) {
1091 if (likely(i < (rxq->rx_free_thresh - 1)))
1092 /* Prefetch next mbuf */
1093 rte_prefetch0(rxep[i + 1].mbuf);
1096 rte_mbuf_refcnt_set(mb, 1);
1098 mb->data_off = RTE_PKTMBUF_HEADROOM;
1100 mb->port = rxq->port_id;
1101 dma_addr = rte_cpu_to_le_64(\
1102 rte_mbuf_data_dma_addr_default(mb));
1103 rxdp[i].read.hdr_addr = 0;
1104 rxdp[i].read.pkt_addr = dma_addr;
1107 /* Update rx tail regsiter */
1109 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1111 rxq->rx_free_trigger =
1112 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1113 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1114 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1119 static inline uint16_t
1120 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1122 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1128 if (rxq->rx_nb_avail)
1129 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1131 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1132 rxq->rx_next_avail = 0;
1133 rxq->rx_nb_avail = nb_rx;
1134 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1136 if (rxq->rx_tail > rxq->rx_free_trigger) {
1137 if (i40e_rx_alloc_bufs(rxq) != 0) {
1140 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1141 "port_id=%u, queue_id=%u",
1142 rxq->port_id, rxq->queue_id);
1143 rxq->rx_nb_avail = 0;
1144 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1145 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1146 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1152 if (rxq->rx_tail >= rxq->nb_rx_desc)
1155 if (rxq->rx_nb_avail)
1156 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1162 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1163 struct rte_mbuf **rx_pkts,
1166 uint16_t nb_rx = 0, n, count;
1168 if (unlikely(nb_pkts == 0))
1171 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1172 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1175 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1176 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1177 nb_rx = (uint16_t)(nb_rx + count);
1178 nb_pkts = (uint16_t)(nb_pkts - count);
1187 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1188 struct rte_mbuf __rte_unused **rx_pkts,
1189 uint16_t __rte_unused nb_pkts)
1193 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1196 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1198 struct i40e_rx_queue *rxq;
1199 volatile union i40e_rx_desc *rx_ring;
1200 volatile union i40e_rx_desc *rxdp;
1201 union i40e_rx_desc rxd;
1202 struct i40e_rx_entry *sw_ring;
1203 struct i40e_rx_entry *rxe;
1204 struct rte_mbuf *rxm;
1205 struct rte_mbuf *nmb;
1209 uint16_t rx_packet_len;
1210 uint16_t rx_id, nb_hold;
1217 rx_id = rxq->rx_tail;
1218 rx_ring = rxq->rx_ring;
1219 sw_ring = rxq->sw_ring;
1221 while (nb_rx < nb_pkts) {
1222 rxdp = &rx_ring[rx_id];
1223 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1224 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1225 >> I40E_RXD_QW1_STATUS_SHIFT;
1227 /* Check the DD bit first */
1228 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1231 nmb = rte_mbuf_raw_alloc(rxq->mp);
1237 rxe = &sw_ring[rx_id];
1239 if (unlikely(rx_id == rxq->nb_rx_desc))
1242 /* Prefetch next mbuf */
1243 rte_prefetch0(sw_ring[rx_id].mbuf);
1246 * When next RX descriptor is on a cache line boundary,
1247 * prefetch the next 4 RX descriptors and next 8 pointers
1250 if ((rx_id & 0x3) == 0) {
1251 rte_prefetch0(&rx_ring[rx_id]);
1252 rte_prefetch0(&sw_ring[rx_id]);
1257 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1258 rxdp->read.hdr_addr = 0;
1259 rxdp->read.pkt_addr = dma_addr;
1261 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1262 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1264 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1265 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1268 rxm->pkt_len = rx_packet_len;
1269 rxm->data_len = rx_packet_len;
1270 rxm->port = rxq->port_id;
1272 i40e_rxd_to_vlan_tci(rxm, &rxd);
1273 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1274 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1276 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1277 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1278 if (pkt_flags & PKT_RX_RSS_HASH)
1280 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1281 if (pkt_flags & PKT_RX_FDIR)
1282 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1284 #ifdef RTE_LIBRTE_IEEE1588
1285 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1287 rxm->ol_flags |= pkt_flags;
1289 rx_pkts[nb_rx++] = rxm;
1291 rxq->rx_tail = rx_id;
1294 * If the number of free RX descriptors is greater than the RX free
1295 * threshold of the queue, advance the receive tail register of queue.
1296 * Update that register with the value of the last processed RX
1297 * descriptor minus 1.
1299 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1300 if (nb_hold > rxq->rx_free_thresh) {
1301 rx_id = (uint16_t) ((rx_id == 0) ?
1302 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1303 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1306 rxq->nb_rx_hold = nb_hold;
1312 i40e_recv_scattered_pkts(void *rx_queue,
1313 struct rte_mbuf **rx_pkts,
1316 struct i40e_rx_queue *rxq = rx_queue;
1317 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1318 volatile union i40e_rx_desc *rxdp;
1319 union i40e_rx_desc rxd;
1320 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1321 struct i40e_rx_entry *rxe;
1322 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1323 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1324 struct rte_mbuf *nmb, *rxm;
1325 uint16_t rx_id = rxq->rx_tail;
1326 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1332 while (nb_rx < nb_pkts) {
1333 rxdp = &rx_ring[rx_id];
1334 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1335 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1336 I40E_RXD_QW1_STATUS_SHIFT;
1338 /* Check the DD bit */
1339 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1342 nmb = rte_mbuf_raw_alloc(rxq->mp);
1347 rxe = &sw_ring[rx_id];
1349 if (rx_id == rxq->nb_rx_desc)
1352 /* Prefetch next mbuf */
1353 rte_prefetch0(sw_ring[rx_id].mbuf);
1356 * When next RX descriptor is on a cache line boundary,
1357 * prefetch the next 4 RX descriptors and next 8 pointers
1360 if ((rx_id & 0x3) == 0) {
1361 rte_prefetch0(&rx_ring[rx_id]);
1362 rte_prefetch0(&sw_ring[rx_id]);
1368 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1370 /* Set data buffer address and data length of the mbuf */
1371 rxdp->read.hdr_addr = 0;
1372 rxdp->read.pkt_addr = dma_addr;
1373 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1374 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1375 rxm->data_len = rx_packet_len;
1376 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1379 * If this is the first buffer of the received packet, set the
1380 * pointer to the first mbuf of the packet and initialize its
1381 * context. Otherwise, update the total length and the number
1382 * of segments of the current scattered packet, and update the
1383 * pointer to the last mbuf of the current packet.
1387 first_seg->nb_segs = 1;
1388 first_seg->pkt_len = rx_packet_len;
1390 first_seg->pkt_len =
1391 (uint16_t)(first_seg->pkt_len +
1393 first_seg->nb_segs++;
1394 last_seg->next = rxm;
1398 * If this is not the last buffer of the received packet,
1399 * update the pointer to the last mbuf of the current scattered
1400 * packet and continue to parse the RX ring.
1402 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1408 * This is the last buffer of the received packet. If the CRC
1409 * is not stripped by the hardware:
1410 * - Subtract the CRC length from the total packet length.
1411 * - If the last buffer only contains the whole CRC or a part
1412 * of it, free the mbuf associated to the last buffer. If part
1413 * of the CRC is also contained in the previous mbuf, subtract
1414 * the length of that CRC part from the data length of the
1418 if (unlikely(rxq->crc_len > 0)) {
1419 first_seg->pkt_len -= ETHER_CRC_LEN;
1420 if (rx_packet_len <= ETHER_CRC_LEN) {
1421 rte_pktmbuf_free_seg(rxm);
1422 first_seg->nb_segs--;
1423 last_seg->data_len =
1424 (uint16_t)(last_seg->data_len -
1425 (ETHER_CRC_LEN - rx_packet_len));
1426 last_seg->next = NULL;
1428 rxm->data_len = (uint16_t)(rx_packet_len -
1432 first_seg->port = rxq->port_id;
1433 first_seg->ol_flags = 0;
1434 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1435 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1436 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1437 first_seg->packet_type =
1438 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1439 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1440 if (pkt_flags & PKT_RX_RSS_HASH)
1441 first_seg->hash.rss =
1442 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1443 if (pkt_flags & PKT_RX_FDIR)
1444 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
1446 #ifdef RTE_LIBRTE_IEEE1588
1447 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1449 first_seg->ol_flags |= pkt_flags;
1451 /* Prefetch data of first segment, if configured to do so. */
1452 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1453 first_seg->data_off));
1454 rx_pkts[nb_rx++] = first_seg;
1458 /* Record index of the next RX descriptor to probe. */
1459 rxq->rx_tail = rx_id;
1460 rxq->pkt_first_seg = first_seg;
1461 rxq->pkt_last_seg = last_seg;
1464 * If the number of free RX descriptors is greater than the RX free
1465 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1466 * register. Update the RDT with the value of the last processed RX
1467 * descriptor minus 1, to guarantee that the RDT register is never
1468 * equal to the RDH register, which creates a "full" ring situtation
1469 * from the hardware point of view.
1471 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1472 if (nb_hold > rxq->rx_free_thresh) {
1473 rx_id = (uint16_t)(rx_id == 0 ?
1474 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1475 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1478 rxq->nb_rx_hold = nb_hold;
1483 /* Check if the context descriptor is needed for TX offloading */
1484 static inline uint16_t
1485 i40e_calc_context_desc(uint64_t flags)
1487 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1491 #ifdef RTE_LIBRTE_IEEE1588
1492 mask |= PKT_TX_IEEE1588_TMST;
1495 return (flags & mask) ? 1 : 0;
1498 /* set i40e TSO context descriptor */
1499 static inline uint64_t
1500 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1502 uint64_t ctx_desc = 0;
1503 uint32_t cd_cmd, hdr_len, cd_tso_len;
1505 if (!tx_offload.l4_len) {
1506 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1511 * in case of tunneling packet, the outer_l2_len and
1512 * outer_l3_len must be 0.
1514 hdr_len = tx_offload.outer_l2_len +
1515 tx_offload.outer_l3_len +
1520 cd_cmd = I40E_TX_CTX_DESC_TSO;
1521 cd_tso_len = mbuf->pkt_len - hdr_len;
1522 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1523 ((uint64_t)cd_tso_len <<
1524 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1525 ((uint64_t)mbuf->tso_segsz <<
1526 I40E_TXD_CTX_QW1_MSS_SHIFT);
1532 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1534 struct i40e_tx_queue *txq;
1535 struct i40e_tx_entry *sw_ring;
1536 struct i40e_tx_entry *txe, *txn;
1537 volatile struct i40e_tx_desc *txd;
1538 volatile struct i40e_tx_desc *txr;
1539 struct rte_mbuf *tx_pkt;
1540 struct rte_mbuf *m_seg;
1541 uint32_t cd_tunneling_params;
1553 uint64_t buf_dma_addr;
1554 union i40e_tx_offload tx_offload = {0};
1557 sw_ring = txq->sw_ring;
1559 tx_id = txq->tx_tail;
1560 txe = &sw_ring[tx_id];
1562 /* Check if the descriptor ring needs to be cleaned. */
1563 if (txq->nb_tx_free < txq->tx_free_thresh)
1564 i40e_xmit_cleanup(txq);
1566 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1572 tx_pkt = *tx_pkts++;
1573 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1575 ol_flags = tx_pkt->ol_flags;
1576 tx_offload.l2_len = tx_pkt->l2_len;
1577 tx_offload.l3_len = tx_pkt->l3_len;
1578 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1579 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1580 tx_offload.l4_len = tx_pkt->l4_len;
1581 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1583 /* Calculate the number of context descriptors needed. */
1584 nb_ctx = i40e_calc_context_desc(ol_flags);
1587 * The number of descriptors that must be allocated for
1588 * a packet equals to the number of the segments of that
1589 * packet plus 1 context descriptor if needed.
1591 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1592 tx_last = (uint16_t)(tx_id + nb_used - 1);
1595 if (tx_last >= txq->nb_tx_desc)
1596 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1598 if (nb_used > txq->nb_tx_free) {
1599 if (i40e_xmit_cleanup(txq) != 0) {
1604 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1605 while (nb_used > txq->nb_tx_free) {
1606 if (i40e_xmit_cleanup(txq) != 0) {
1615 /* Descriptor based VLAN insertion */
1616 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1617 tx_flags |= tx_pkt->vlan_tci <<
1618 I40E_TX_FLAG_L2TAG1_SHIFT;
1619 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1620 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1621 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1622 I40E_TX_FLAG_L2TAG1_SHIFT;
1625 /* Always enable CRC offload insertion */
1626 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1628 /* Enable checksum offloading */
1629 cd_tunneling_params = 0;
1630 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1631 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1632 tx_offload, &cd_tunneling_params);
1636 /* Setup TX context descriptor if required */
1637 volatile struct i40e_tx_context_desc *ctx_txd =
1638 (volatile struct i40e_tx_context_desc *)\
1640 uint16_t cd_l2tag2 = 0;
1641 uint64_t cd_type_cmd_tso_mss =
1642 I40E_TX_DESC_DTYPE_CONTEXT;
1644 txn = &sw_ring[txe->next_id];
1645 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1646 if (txe->mbuf != NULL) {
1647 rte_pktmbuf_free_seg(txe->mbuf);
1651 /* TSO enabled means no timestamp */
1652 if (ol_flags & PKT_TX_TCP_SEG)
1653 cd_type_cmd_tso_mss |=
1654 i40e_set_tso_ctx(tx_pkt, tx_offload);
1656 #ifdef RTE_LIBRTE_IEEE1588
1657 if (ol_flags & PKT_TX_IEEE1588_TMST)
1658 cd_type_cmd_tso_mss |=
1659 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1660 I40E_TXD_CTX_QW1_CMD_SHIFT);
1664 ctx_txd->tunneling_params =
1665 rte_cpu_to_le_32(cd_tunneling_params);
1666 if (ol_flags & PKT_TX_QINQ_PKT) {
1667 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1668 cd_type_cmd_tso_mss |=
1669 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1670 I40E_TXD_CTX_QW1_CMD_SHIFT);
1672 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1673 ctx_txd->type_cmd_tso_mss =
1674 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1676 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1677 "tunneling_params: %#x;\n"
1680 "type_cmd_tso_mss: %#"PRIx64";\n",
1682 ctx_txd->tunneling_params,
1685 ctx_txd->type_cmd_tso_mss);
1687 txe->last_id = tx_last;
1688 tx_id = txe->next_id;
1695 txn = &sw_ring[txe->next_id];
1698 rte_pktmbuf_free_seg(txe->mbuf);
1701 /* Setup TX Descriptor */
1702 slen = m_seg->data_len;
1703 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1705 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1706 "buf_dma_addr: %#"PRIx64";\n"
1711 tx_pkt, tx_id, buf_dma_addr,
1712 td_cmd, td_offset, slen, td_tag);
1714 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1715 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1716 td_offset, slen, td_tag);
1717 txe->last_id = tx_last;
1718 tx_id = txe->next_id;
1720 m_seg = m_seg->next;
1721 } while (m_seg != NULL);
1723 /* The last packet data descriptor needs End Of Packet (EOP) */
1724 td_cmd |= I40E_TX_DESC_CMD_EOP;
1725 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1726 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1728 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1729 PMD_TX_FREE_LOG(DEBUG,
1730 "Setting RS bit on TXD id="
1731 "%4u (port=%d queue=%d)",
1732 tx_last, txq->port_id, txq->queue_id);
1734 td_cmd |= I40E_TX_DESC_CMD_RS;
1736 /* Update txq RS bit counters */
1737 txq->nb_tx_used = 0;
1740 txd->cmd_type_offset_bsz |=
1741 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1742 I40E_TXD_QW1_CMD_SHIFT);
1748 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1749 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1750 (unsigned) tx_id, (unsigned) nb_tx);
1752 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1753 txq->tx_tail = tx_id;
1758 static inline int __attribute__((always_inline))
1759 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1761 struct i40e_tx_entry *txep;
1764 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1765 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1766 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1769 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1771 for (i = 0; i < txq->tx_rs_thresh; i++)
1772 rte_prefetch0((txep + i)->mbuf);
1774 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1775 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1776 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1780 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1781 rte_pktmbuf_free_seg(txep->mbuf);
1786 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1787 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1788 if (txq->tx_next_dd >= txq->nb_tx_desc)
1789 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1791 return txq->tx_rs_thresh;
1794 /* Populate 4 descriptors with data from 4 mbufs */
1796 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1801 for (i = 0; i < 4; i++, txdp++, pkts++) {
1802 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1803 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1804 txdp->cmd_type_offset_bsz =
1805 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1806 (*pkts)->data_len, 0);
1810 /* Populate 1 descriptor with data from 1 mbuf */
1812 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1816 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1817 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1818 txdp->cmd_type_offset_bsz =
1819 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1820 (*pkts)->data_len, 0);
1823 /* Fill hardware descriptor ring with mbuf data */
1825 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1826 struct rte_mbuf **pkts,
1829 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1830 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1831 const int N_PER_LOOP = 4;
1832 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1833 int mainpart, leftover;
1836 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1837 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1838 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1839 for (j = 0; j < N_PER_LOOP; ++j) {
1840 (txep + i + j)->mbuf = *(pkts + i + j);
1842 tx4(txdp + i, pkts + i);
1844 if (unlikely(leftover > 0)) {
1845 for (i = 0; i < leftover; ++i) {
1846 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1847 tx1(txdp + mainpart + i, pkts + mainpart + i);
1852 static inline uint16_t
1853 tx_xmit_pkts(struct i40e_tx_queue *txq,
1854 struct rte_mbuf **tx_pkts,
1857 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1861 * Begin scanning the H/W ring for done descriptors when the number
1862 * of available descriptors drops below tx_free_thresh. For each done
1863 * descriptor, free the associated buffer.
1865 if (txq->nb_tx_free < txq->tx_free_thresh)
1866 i40e_tx_free_bufs(txq);
1868 /* Use available descriptor only */
1869 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1870 if (unlikely(!nb_pkts))
1873 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1874 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1875 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1876 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1877 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1878 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1879 I40E_TXD_QW1_CMD_SHIFT);
1880 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1884 /* Fill hardware descriptor ring with mbuf data */
1885 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1886 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1888 /* Determin if RS bit needs to be set */
1889 if (txq->tx_tail > txq->tx_next_rs) {
1890 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1891 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1892 I40E_TXD_QW1_CMD_SHIFT);
1894 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1895 if (txq->tx_next_rs >= txq->nb_tx_desc)
1896 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1899 if (txq->tx_tail >= txq->nb_tx_desc)
1902 /* Update the tx tail register */
1904 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1910 i40e_xmit_pkts_simple(void *tx_queue,
1911 struct rte_mbuf **tx_pkts,
1916 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1917 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1921 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1924 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1925 &tx_pkts[nb_tx], num);
1926 nb_tx = (uint16_t)(nb_tx + ret);
1927 nb_pkts = (uint16_t)(nb_pkts - ret);
1936 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1937 * application used, which assume having sequential ones. But from driver's
1938 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1939 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1940 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1941 * use queue_idx from 0 to 95 to access queues, while real queue would be
1942 * different. This function will do a queue mapping to find VSI the queue
1945 static struct i40e_vsi*
1946 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1948 /* the queue in MAIN VSI range */
1949 if (queue_idx < pf->main_vsi->nb_qps)
1950 return pf->main_vsi;
1952 queue_idx -= pf->main_vsi->nb_qps;
1954 /* queue_idx is greater than VMDQ VSIs range */
1955 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1956 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1960 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1964 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1966 /* the queue in MAIN VSI range */
1967 if (queue_idx < pf->main_vsi->nb_qps)
1970 /* It's VMDQ queues */
1971 queue_idx -= pf->main_vsi->nb_qps;
1973 if (pf->nb_cfg_vmdq_vsi)
1974 return queue_idx % pf->vmdq_nb_qps;
1976 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1977 return (uint16_t)(-1);
1982 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1984 struct i40e_rx_queue *rxq;
1986 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988 PMD_INIT_FUNC_TRACE();
1990 if (rx_queue_id < dev->data->nb_rx_queues) {
1991 rxq = dev->data->rx_queues[rx_queue_id];
1993 err = i40e_alloc_rx_queue_mbufs(rxq);
1995 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
2001 /* Init the RX tail regieter. */
2002 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2004 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2007 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2010 i40e_rx_queue_release_mbufs(rxq);
2011 i40e_reset_rx_queue(rxq);
2013 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2020 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2022 struct i40e_rx_queue *rxq;
2024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026 if (rx_queue_id < dev->data->nb_rx_queues) {
2027 rxq = dev->data->rx_queues[rx_queue_id];
2030 * rx_queue_id is queue id aplication refers to, while
2031 * rxq->reg_idx is the real queue index.
2033 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2036 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2040 i40e_rx_queue_release_mbufs(rxq);
2041 i40e_reset_rx_queue(rxq);
2042 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2049 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2052 struct i40e_tx_queue *txq;
2053 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055 PMD_INIT_FUNC_TRACE();
2057 if (tx_queue_id < dev->data->nb_tx_queues) {
2058 txq = dev->data->tx_queues[tx_queue_id];
2061 * tx_queue_id is queue id aplication refers to, while
2062 * rxq->reg_idx is the real queue index.
2064 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2066 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2069 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2076 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2078 struct i40e_tx_queue *txq;
2080 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 if (tx_queue_id < dev->data->nb_tx_queues) {
2083 txq = dev->data->tx_queues[tx_queue_id];
2086 * tx_queue_id is queue id aplication refers to, while
2087 * txq->reg_idx is the real queue index.
2089 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2092 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2097 i40e_tx_queue_release_mbufs(txq);
2098 i40e_reset_tx_queue(txq);
2099 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2106 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2108 static const uint32_t ptypes[] = {
2109 /* refers to i40e_rxd_pkt_type_mapping() */
2111 RTE_PTYPE_L2_ETHER_TIMESYNC,
2112 RTE_PTYPE_L2_ETHER_LLDP,
2113 RTE_PTYPE_L2_ETHER_ARP,
2114 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2115 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2118 RTE_PTYPE_L4_NONFRAG,
2122 RTE_PTYPE_TUNNEL_GRENAT,
2123 RTE_PTYPE_TUNNEL_IP,
2124 RTE_PTYPE_INNER_L2_ETHER,
2125 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2126 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2127 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2128 RTE_PTYPE_INNER_L4_FRAG,
2129 RTE_PTYPE_INNER_L4_ICMP,
2130 RTE_PTYPE_INNER_L4_NONFRAG,
2131 RTE_PTYPE_INNER_L4_SCTP,
2132 RTE_PTYPE_INNER_L4_TCP,
2133 RTE_PTYPE_INNER_L4_UDP,
2137 if (dev->rx_pkt_burst == i40e_recv_pkts ||
2138 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2139 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2141 dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2147 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2150 unsigned int socket_id,
2151 const struct rte_eth_rxconf *rx_conf,
2152 struct rte_mempool *mp)
2154 struct i40e_vsi *vsi;
2155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157 struct i40e_adapter *ad =
2158 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2159 struct i40e_rx_queue *rxq;
2160 const struct rte_memzone *rz;
2163 uint16_t base, bsf, tc_mapping;
2164 int use_def_burst_func = 1;
2166 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2167 struct i40e_vf *vf =
2168 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2171 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2174 PMD_DRV_LOG(ERR, "VSI not available or queue "
2175 "index exceeds the maximum");
2176 return I40E_ERR_PARAM;
2178 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2179 (nb_desc > I40E_MAX_RING_DESC) ||
2180 (nb_desc < I40E_MIN_RING_DESC)) {
2181 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2182 "invalid", nb_desc);
2183 return I40E_ERR_PARAM;
2186 /* Free memory if needed */
2187 if (dev->data->rx_queues[queue_idx]) {
2188 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2189 dev->data->rx_queues[queue_idx] = NULL;
2192 /* Allocate the rx queue data structure */
2193 rxq = rte_zmalloc_socket("i40e rx queue",
2194 sizeof(struct i40e_rx_queue),
2195 RTE_CACHE_LINE_SIZE,
2198 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2199 "rx queue data structure");
2203 rxq->nb_rx_desc = nb_desc;
2204 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2205 rxq->queue_id = queue_idx;
2206 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2207 rxq->reg_idx = queue_idx;
2208 else /* PF device */
2209 rxq->reg_idx = vsi->base_queue +
2210 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2212 rxq->port_id = dev->data->port_id;
2213 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2215 rxq->drop_en = rx_conf->rx_drop_en;
2217 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2219 /* Allocate the maximun number of RX ring hardware descriptor. */
2220 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2221 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2222 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2223 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2225 i40e_dev_rx_queue_release(rxq);
2226 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2230 /* Zero all the descriptors in the ring. */
2231 memset(rz->addr, 0, ring_size);
2233 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2234 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2236 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2237 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2242 /* Allocate the software ring. */
2244 rte_zmalloc_socket("i40e rx sw ring",
2245 sizeof(struct i40e_rx_entry) * len,
2246 RTE_CACHE_LINE_SIZE,
2248 if (!rxq->sw_ring) {
2249 i40e_dev_rx_queue_release(rxq);
2250 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2254 i40e_reset_rx_queue(rxq);
2256 dev->data->rx_queues[queue_idx] = rxq;
2258 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2260 if (!use_def_burst_func) {
2261 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2262 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2263 "satisfied. Rx Burst Bulk Alloc function will be "
2264 "used on port=%d, queue=%d.",
2265 rxq->port_id, rxq->queue_id);
2266 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2268 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2269 "not satisfied, Scattered Rx is requested, "
2270 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2271 "not enabled on port=%d, queue=%d.",
2272 rxq->port_id, rxq->queue_id);
2273 ad->rx_bulk_alloc_allowed = false;
2276 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2277 if (!(vsi->enabled_tc & (1 << i)))
2279 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2280 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2281 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2282 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2283 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2285 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2293 i40e_dev_rx_queue_release(void *rxq)
2295 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2298 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2302 i40e_rx_queue_release_mbufs(q);
2303 rte_free(q->sw_ring);
2308 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2310 #define I40E_RXQ_SCAN_INTERVAL 4
2311 volatile union i40e_rx_desc *rxdp;
2312 struct i40e_rx_queue *rxq;
2315 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2316 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2320 rxq = dev->data->rx_queues[rx_queue_id];
2321 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2322 while ((desc < rxq->nb_rx_desc) &&
2323 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2324 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2325 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2327 * Check the DD bit of a rx descriptor of each 4 in a group,
2328 * to avoid checking too frequently and downgrading performance
2331 desc += I40E_RXQ_SCAN_INTERVAL;
2332 rxdp += I40E_RXQ_SCAN_INTERVAL;
2333 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2334 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2335 desc - rxq->nb_rx_desc]);
2342 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2344 volatile union i40e_rx_desc *rxdp;
2345 struct i40e_rx_queue *rxq = rx_queue;
2349 if (unlikely(offset >= rxq->nb_rx_desc)) {
2350 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2354 desc = rxq->rx_tail + offset;
2355 if (desc >= rxq->nb_rx_desc)
2356 desc -= rxq->nb_rx_desc;
2358 rxdp = &(rxq->rx_ring[desc]);
2360 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2361 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2362 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2368 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2371 unsigned int socket_id,
2372 const struct rte_eth_txconf *tx_conf)
2374 struct i40e_vsi *vsi;
2375 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2377 struct i40e_tx_queue *txq;
2378 const struct rte_memzone *tz;
2380 uint16_t tx_rs_thresh, tx_free_thresh;
2381 uint16_t i, base, bsf, tc_mapping;
2383 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2384 struct i40e_vf *vf =
2385 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2388 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2391 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2392 "exceeds the maximum", queue_idx);
2393 return I40E_ERR_PARAM;
2396 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2397 (nb_desc > I40E_MAX_RING_DESC) ||
2398 (nb_desc < I40E_MIN_RING_DESC)) {
2399 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2400 "invalid", nb_desc);
2401 return I40E_ERR_PARAM;
2405 * The following two parameters control the setting of the RS bit on
2406 * transmit descriptors. TX descriptors will have their RS bit set
2407 * after txq->tx_rs_thresh descriptors have been used. The TX
2408 * descriptor ring will be cleaned after txq->tx_free_thresh
2409 * descriptors are used or if the number of descriptors required to
2410 * transmit a packet is greater than the number of free TX descriptors.
2412 * The following constraints must be satisfied:
2413 * - tx_rs_thresh must be greater than 0.
2414 * - tx_rs_thresh must be less than the size of the ring minus 2.
2415 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2416 * - tx_rs_thresh must be a divisor of the ring size.
2417 * - tx_free_thresh must be greater than 0.
2418 * - tx_free_thresh must be less than the size of the ring minus 3.
2420 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2421 * race condition, hence the maximum threshold constraints. When set
2422 * to zero use default values.
2424 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2425 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2426 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2427 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2428 if (tx_rs_thresh >= (nb_desc - 2)) {
2429 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2430 "number of TX descriptors minus 2. "
2431 "(tx_rs_thresh=%u port=%d queue=%d)",
2432 (unsigned int)tx_rs_thresh,
2433 (int)dev->data->port_id,
2435 return I40E_ERR_PARAM;
2437 if (tx_free_thresh >= (nb_desc - 3)) {
2438 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2439 "tx_free_thresh must be less than the "
2440 "number of TX descriptors minus 3. "
2441 "(tx_free_thresh=%u port=%d queue=%d)",
2442 (unsigned int)tx_free_thresh,
2443 (int)dev->data->port_id,
2445 return I40E_ERR_PARAM;
2447 if (tx_rs_thresh > tx_free_thresh) {
2448 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2449 "equal to tx_free_thresh. (tx_free_thresh=%u"
2450 " tx_rs_thresh=%u port=%d queue=%d)",
2451 (unsigned int)tx_free_thresh,
2452 (unsigned int)tx_rs_thresh,
2453 (int)dev->data->port_id,
2455 return I40E_ERR_PARAM;
2457 if ((nb_desc % tx_rs_thresh) != 0) {
2458 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2459 "number of TX descriptors. (tx_rs_thresh=%u"
2460 " port=%d queue=%d)",
2461 (unsigned int)tx_rs_thresh,
2462 (int)dev->data->port_id,
2464 return I40E_ERR_PARAM;
2466 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2467 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2468 "tx_rs_thresh is greater than 1. "
2469 "(tx_rs_thresh=%u port=%d queue=%d)",
2470 (unsigned int)tx_rs_thresh,
2471 (int)dev->data->port_id,
2473 return I40E_ERR_PARAM;
2476 /* Free memory if needed. */
2477 if (dev->data->tx_queues[queue_idx]) {
2478 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2479 dev->data->tx_queues[queue_idx] = NULL;
2482 /* Allocate the TX queue data structure. */
2483 txq = rte_zmalloc_socket("i40e tx queue",
2484 sizeof(struct i40e_tx_queue),
2485 RTE_CACHE_LINE_SIZE,
2488 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2489 "tx queue structure");
2493 /* Allocate TX hardware ring descriptors. */
2494 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2495 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2496 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2497 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2499 i40e_dev_tx_queue_release(txq);
2500 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2504 txq->nb_tx_desc = nb_desc;
2505 txq->tx_rs_thresh = tx_rs_thresh;
2506 txq->tx_free_thresh = tx_free_thresh;
2507 txq->pthresh = tx_conf->tx_thresh.pthresh;
2508 txq->hthresh = tx_conf->tx_thresh.hthresh;
2509 txq->wthresh = tx_conf->tx_thresh.wthresh;
2510 txq->queue_id = queue_idx;
2511 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2512 txq->reg_idx = queue_idx;
2513 else /* PF device */
2514 txq->reg_idx = vsi->base_queue +
2515 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2517 txq->port_id = dev->data->port_id;
2518 txq->txq_flags = tx_conf->txq_flags;
2520 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2522 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2523 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2525 /* Allocate software ring */
2527 rte_zmalloc_socket("i40e tx sw ring",
2528 sizeof(struct i40e_tx_entry) * nb_desc,
2529 RTE_CACHE_LINE_SIZE,
2531 if (!txq->sw_ring) {
2532 i40e_dev_tx_queue_release(txq);
2533 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2537 i40e_reset_tx_queue(txq);
2539 dev->data->tx_queues[queue_idx] = txq;
2541 /* Use a simple TX queue without offloads or multi segs if possible */
2542 i40e_set_tx_function_flag(dev, txq);
2544 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2545 if (!(vsi->enabled_tc & (1 << i)))
2547 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2548 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2549 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2550 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2551 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2553 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2561 i40e_dev_tx_queue_release(void *txq)
2563 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2566 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2570 i40e_tx_queue_release_mbufs(q);
2571 rte_free(q->sw_ring);
2575 const struct rte_memzone *
2576 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2578 const struct rte_memzone *mz;
2580 mz = rte_memzone_lookup(name);
2584 if (rte_xen_dom0_supported())
2585 mz = rte_memzone_reserve_bounded(name, len,
2586 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2588 mz = rte_memzone_reserve_aligned(name, len,
2589 socket_id, 0, I40E_RING_BASE_ALIGN);
2594 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2598 /* SSE Vector driver has a different way of releasing mbufs. */
2599 if (rxq->rx_using_sse) {
2600 i40e_rx_queue_release_mbufs_vec(rxq);
2604 if (!rxq->sw_ring) {
2605 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2609 for (i = 0; i < rxq->nb_rx_desc; i++) {
2610 if (rxq->sw_ring[i].mbuf) {
2611 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2612 rxq->sw_ring[i].mbuf = NULL;
2615 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2616 if (rxq->rx_nb_avail == 0)
2618 for (i = 0; i < rxq->rx_nb_avail; i++) {
2619 struct rte_mbuf *mbuf;
2621 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2622 rte_pktmbuf_free_seg(mbuf);
2624 rxq->rx_nb_avail = 0;
2625 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2629 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2635 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2639 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2640 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2641 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2643 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2644 len = rxq->nb_rx_desc;
2646 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2647 ((volatile char *)rxq->rx_ring)[i] = 0;
2649 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2650 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2651 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2652 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2654 rxq->rx_nb_avail = 0;
2655 rxq->rx_next_avail = 0;
2656 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2657 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2659 rxq->nb_rx_hold = 0;
2660 rxq->pkt_first_seg = NULL;
2661 rxq->pkt_last_seg = NULL;
2663 rxq->rxrearm_start = 0;
2664 rxq->rxrearm_nb = 0;
2668 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2672 if (!txq || !txq->sw_ring) {
2673 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2677 for (i = 0; i < txq->nb_tx_desc; i++) {
2678 if (txq->sw_ring[i].mbuf) {
2679 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2680 txq->sw_ring[i].mbuf = NULL;
2686 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2688 struct i40e_tx_entry *txe;
2689 uint16_t i, prev, size;
2692 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2697 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2698 for (i = 0; i < size; i++)
2699 ((volatile char *)txq->tx_ring)[i] = 0;
2701 prev = (uint16_t)(txq->nb_tx_desc - 1);
2702 for (i = 0; i < txq->nb_tx_desc; i++) {
2703 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2705 txd->cmd_type_offset_bsz =
2706 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2709 txe[prev].next_id = i;
2713 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2714 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2717 txq->nb_tx_used = 0;
2719 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2720 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2723 /* Init the TX queue in hardware */
2725 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2727 enum i40e_status_code err = I40E_SUCCESS;
2728 struct i40e_vsi *vsi = txq->vsi;
2729 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2730 uint16_t pf_q = txq->reg_idx;
2731 struct i40e_hmc_obj_txq tx_ctx;
2734 /* clear the context structure first */
2735 memset(&tx_ctx, 0, sizeof(tx_ctx));
2736 tx_ctx.new_context = 1;
2737 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2738 tx_ctx.qlen = txq->nb_tx_desc;
2740 #ifdef RTE_LIBRTE_IEEE1588
2741 tx_ctx.timesync_ena = 1;
2743 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2744 if (vsi->type == I40E_VSI_FDIR)
2745 tx_ctx.fd_ena = TRUE;
2747 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2748 if (err != I40E_SUCCESS) {
2749 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2753 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2754 if (err != I40E_SUCCESS) {
2755 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2759 /* Now associate this queue with this PCI function */
2760 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2761 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2762 I40E_QTX_CTL_PF_INDX_MASK);
2763 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2764 I40E_WRITE_FLUSH(hw);
2766 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2772 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2774 struct i40e_rx_entry *rxe = rxq->sw_ring;
2778 for (i = 0; i < rxq->nb_rx_desc; i++) {
2779 volatile union i40e_rx_desc *rxd;
2780 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2782 if (unlikely(!mbuf)) {
2783 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2787 rte_mbuf_refcnt_set(mbuf, 1);
2789 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2791 mbuf->port = rxq->port_id;
2794 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2796 rxd = &rxq->rx_ring[i];
2797 rxd->read.pkt_addr = dma_addr;
2798 rxd->read.hdr_addr = 0;
2799 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2800 rxd->read.rsvd1 = 0;
2801 rxd->read.rsvd2 = 0;
2802 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2811 * Calculate the buffer length, and check the jumbo frame
2812 * and maximum packet length.
2815 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2817 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2818 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2819 struct rte_eth_dev_data *data = pf->dev_data;
2820 uint16_t buf_size, len;
2822 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2823 RTE_PKTMBUF_HEADROOM);
2825 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2826 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2827 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2828 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2829 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2830 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2831 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2832 rxq->hs_mode = i40e_header_split_enabled;
2834 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2836 rxq->rx_hdr_len = 0;
2837 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2838 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2839 rxq->hs_mode = i40e_header_split_none;
2843 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2844 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2845 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2846 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2847 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2848 PMD_DRV_LOG(ERR, "maximum packet length must "
2849 "be larger than %u and smaller than %u,"
2850 "as jumbo frame is enabled",
2851 (uint32_t)ETHER_MAX_LEN,
2852 (uint32_t)I40E_FRAME_SIZE_MAX);
2853 return I40E_ERR_CONFIG;
2856 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2857 rxq->max_pkt_len > ETHER_MAX_LEN) {
2858 PMD_DRV_LOG(ERR, "maximum packet length must be "
2859 "larger than %u and smaller than %u, "
2860 "as jumbo frame is disabled",
2861 (uint32_t)ETHER_MIN_LEN,
2862 (uint32_t)ETHER_MAX_LEN);
2863 return I40E_ERR_CONFIG;
2870 /* Init the RX queue in hardware */
2872 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2874 int err = I40E_SUCCESS;
2875 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2876 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2877 uint16_t pf_q = rxq->reg_idx;
2879 struct i40e_hmc_obj_rxq rx_ctx;
2881 err = i40e_rx_queue_config(rxq);
2883 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2887 /* Clear the context structure first */
2888 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2889 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2890 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2892 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2893 rx_ctx.qlen = rxq->nb_rx_desc;
2894 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2897 rx_ctx.dtype = rxq->hs_mode;
2899 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2901 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2902 rx_ctx.rxmax = rxq->max_pkt_len;
2903 rx_ctx.tphrdesc_ena = 1;
2904 rx_ctx.tphwdesc_ena = 1;
2905 rx_ctx.tphdata_ena = 1;
2906 rx_ctx.tphhead_ena = 1;
2907 rx_ctx.lrxqthresh = 2;
2908 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2910 /* showiv indicates if inner VLAN is stripped inside of tunnel
2911 * packet. When set it to 1, vlan information is stripped from
2912 * the inner header, but the hardware does not put it in the
2913 * descriptor. So set it zero by default.
2918 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2919 if (err != I40E_SUCCESS) {
2920 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2923 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2924 if (err != I40E_SUCCESS) {
2925 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2929 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2931 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2932 RTE_PKTMBUF_HEADROOM);
2934 /* Check if scattered RX needs to be used. */
2935 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2936 dev_data->scattered_rx = 1;
2939 /* Init the RX tail regieter. */
2940 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2946 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2950 PMD_INIT_FUNC_TRACE();
2952 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2953 if (!dev->data->tx_queues[i])
2955 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2956 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2959 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2960 if (!dev->data->rx_queues[i])
2962 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2963 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2968 i40e_dev_free_queues(struct rte_eth_dev *dev)
2972 PMD_INIT_FUNC_TRACE();
2974 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2975 if (!dev->data->rx_queues[i])
2977 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2978 dev->data->rx_queues[i] = NULL;
2980 dev->data->nb_rx_queues = 0;
2982 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2983 if (!dev->data->tx_queues[i])
2985 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2986 dev->data->tx_queues[i] = NULL;
2988 dev->data->nb_tx_queues = 0;
2991 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2992 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2994 enum i40e_status_code
2995 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2997 struct i40e_tx_queue *txq;
2998 const struct rte_memzone *tz = NULL;
3000 struct rte_eth_dev *dev;
3003 PMD_DRV_LOG(ERR, "PF is not available");
3004 return I40E_ERR_BAD_PTR;
3007 dev = pf->adapter->eth_dev;
3009 /* Allocate the TX queue data structure. */
3010 txq = rte_zmalloc_socket("i40e fdir tx queue",
3011 sizeof(struct i40e_tx_queue),
3012 RTE_CACHE_LINE_SIZE,
3015 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3016 "tx queue structure.");
3017 return I40E_ERR_NO_MEMORY;
3020 /* Allocate TX hardware ring descriptors. */
3021 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3022 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3024 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3025 I40E_FDIR_QUEUE_ID, ring_size,
3026 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3028 i40e_dev_tx_queue_release(txq);
3029 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3030 return I40E_ERR_NO_MEMORY;
3033 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3034 txq->queue_id = I40E_FDIR_QUEUE_ID;
3035 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3036 txq->vsi = pf->fdir.fdir_vsi;
3038 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3039 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3041 * don't need to allocate software ring and reset for the fdir
3042 * program queue just set the queue has been configured.
3047 return I40E_SUCCESS;
3050 enum i40e_status_code
3051 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3053 struct i40e_rx_queue *rxq;
3054 const struct rte_memzone *rz = NULL;
3056 struct rte_eth_dev *dev;
3059 PMD_DRV_LOG(ERR, "PF is not available");
3060 return I40E_ERR_BAD_PTR;
3063 dev = pf->adapter->eth_dev;
3065 /* Allocate the RX queue data structure. */
3066 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3067 sizeof(struct i40e_rx_queue),
3068 RTE_CACHE_LINE_SIZE,
3071 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3072 "rx queue structure.");
3073 return I40E_ERR_NO_MEMORY;
3076 /* Allocate RX hardware ring descriptors. */
3077 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3078 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3080 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3081 I40E_FDIR_QUEUE_ID, ring_size,
3082 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3084 i40e_dev_rx_queue_release(rxq);
3085 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3086 return I40E_ERR_NO_MEMORY;
3089 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3090 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3091 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3092 rxq->vsi = pf->fdir.fdir_vsi;
3094 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3095 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3098 * Don't need to allocate software ring and reset for the fdir
3099 * rx queue, just set the queue has been configured.
3104 return I40E_SUCCESS;
3108 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3109 struct rte_eth_rxq_info *qinfo)
3111 struct i40e_rx_queue *rxq;
3113 rxq = dev->data->rx_queues[queue_id];
3115 qinfo->mp = rxq->mp;
3116 qinfo->scattered_rx = dev->data->scattered_rx;
3117 qinfo->nb_desc = rxq->nb_rx_desc;
3119 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3120 qinfo->conf.rx_drop_en = rxq->drop_en;
3121 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3125 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3126 struct rte_eth_txq_info *qinfo)
3128 struct i40e_tx_queue *txq;
3130 txq = dev->data->tx_queues[queue_id];
3132 qinfo->nb_desc = txq->nb_tx_desc;
3134 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3135 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3136 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3138 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3139 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3140 qinfo->conf.txq_flags = txq->txq_flags;
3141 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3144 void __attribute__((cold))
3145 i40e_set_rx_function(struct rte_eth_dev *dev)
3147 struct i40e_adapter *ad =
3148 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3149 uint16_t rx_using_sse, i;
3150 /* In order to allow Vector Rx there are a few configuration
3151 * conditions to be met and Rx Bulk Allocation should be allowed.
3153 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3154 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3155 !ad->rx_bulk_alloc_allowed) {
3156 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3157 " Vector Rx preconditions",
3158 dev->data->port_id);
3160 ad->rx_vec_allowed = false;
3162 if (ad->rx_vec_allowed) {
3163 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3164 struct i40e_rx_queue *rxq =
3165 dev->data->rx_queues[i];
3167 if (rxq && i40e_rxq_vec_setup(rxq)) {
3168 ad->rx_vec_allowed = false;
3175 if (dev->data->scattered_rx) {
3176 /* Set the non-LRO scattered callback: there are Vector and
3177 * single allocation versions.
3179 if (ad->rx_vec_allowed) {
3180 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3181 "callback (port=%d).",
3182 dev->data->port_id);
3184 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3186 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3187 "allocation callback (port=%d).",
3188 dev->data->port_id);
3189 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3191 /* If parameters allow we are going to choose between the following
3195 * - Single buffer allocation (the simplest one)
3197 } else if (ad->rx_vec_allowed) {
3198 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3199 "burst size no less than %d (port=%d).",
3200 RTE_I40E_DESCS_PER_LOOP,
3201 dev->data->port_id);
3203 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3204 } else if (ad->rx_bulk_alloc_allowed) {
3205 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3206 "satisfied. Rx Burst Bulk Alloc function "
3207 "will be used on port=%d.",
3208 dev->data->port_id);
3210 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3212 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3213 "satisfied, or Scattered Rx is requested "
3215 dev->data->port_id);
3217 dev->rx_pkt_burst = i40e_recv_pkts;
3220 /* Propagate information about RX function choice through all queues. */
3221 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3223 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3224 dev->rx_pkt_burst == i40e_recv_pkts_vec);
3226 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3227 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3230 rxq->rx_using_sse = rx_using_sse;
3235 void __attribute__((cold))
3236 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3238 struct i40e_adapter *ad =
3239 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3241 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3242 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3243 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3244 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3245 PMD_INIT_LOG(DEBUG, "Vector tx"
3246 " can be enabled on this txq.");
3249 ad->tx_vec_allowed = false;
3252 ad->tx_simple_allowed = false;
3256 void __attribute__((cold))
3257 i40e_set_tx_function(struct rte_eth_dev *dev)
3259 struct i40e_adapter *ad =
3260 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3263 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3264 if (ad->tx_vec_allowed) {
3265 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3266 struct i40e_tx_queue *txq =
3267 dev->data->tx_queues[i];
3269 if (txq && i40e_txq_vec_setup(txq)) {
3270 ad->tx_vec_allowed = false;
3277 if (ad->tx_simple_allowed) {
3278 if (ad->tx_vec_allowed) {
3279 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3280 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3282 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3283 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3286 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3287 dev->tx_pkt_burst = i40e_xmit_pkts;
3291 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3292 int __attribute__((weak))
3293 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3298 uint16_t __attribute__((weak))
3300 void __rte_unused *rx_queue,
3301 struct rte_mbuf __rte_unused **rx_pkts,
3302 uint16_t __rte_unused nb_pkts)
3307 uint16_t __attribute__((weak))
3308 i40e_recv_scattered_pkts_vec(
3309 void __rte_unused *rx_queue,
3310 struct rte_mbuf __rte_unused **rx_pkts,
3311 uint16_t __rte_unused nb_pkts)
3316 int __attribute__((weak))
3317 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3322 int __attribute__((weak))
3323 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3328 void __attribute__((weak))
3329 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3334 uint16_t __attribute__((weak))
3335 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3336 struct rte_mbuf __rte_unused **tx_pkts,
3337 uint16_t __rte_unused nb_pkts)