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42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_TX_MAX_BURST 32
69 #define I40E_DMA_MEM_ALIGN 4096
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
79 PKT_TX_OUTER_IP_CKSUM)
81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
82 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
85 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
87 static const struct rte_memzone *
88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
89 const char *ring_name,
93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
94 struct rte_mbuf **tx_pkts,
98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
100 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
101 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
102 mb->ol_flags |= PKT_RX_VLAN_PKT;
104 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
105 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
106 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
111 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
112 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
113 mb->ol_flags |= PKT_RX_QINQ_PKT;
114 mb->vlan_tci_outer = mb->vlan_tci;
115 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
116 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
117 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
118 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
120 mb->vlan_tci_outer = 0;
123 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
124 mb->vlan_tci, mb->vlan_tci_outer);
127 /* Translate the rx descriptor status to pkt flags */
128 static inline uint64_t
129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
133 /* Check if RSS_HASH */
134 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
135 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
136 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
138 /* Check if FDIR Match */
139 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
145 static inline uint64_t
146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
149 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
151 #define I40E_RX_ERR_BITS 0x3f
152 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
154 /* If RXE bit set, all other status bits are meaningless */
155 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
156 flags |= PKT_RX_MAC_ERR;
160 /* If RECIPE bit set, all other status indications should be ignored */
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
162 flags |= PKT_RX_RECIP_ERR;
165 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
166 flags |= PKT_RX_HBUF_OVERFLOW;
167 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
168 flags |= PKT_RX_IP_CKSUM_BAD;
169 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
170 flags |= PKT_RX_L4_CKSUM_BAD;
171 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
172 flags |= PKT_RX_EIP_CKSUM_BAD;
173 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
174 flags |= PKT_RX_OVERSIZE;
179 /* Translate pkt types to pkt flags */
180 static inline uint64_t
181 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
183 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
184 I40E_RXD_QW1_PTYPE_SHIFT);
185 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
188 PKT_RX_IEEE1588_PTP, /* PTYPE 2 */
208 PKT_RX_IPV4_HDR, /* PTYPE 22 */
209 PKT_RX_IPV4_HDR, /* PTYPE 23 */
210 PKT_RX_IPV4_HDR, /* PTYPE 24 */
212 PKT_RX_IPV4_HDR, /* PTYPE 26 */
213 PKT_RX_IPV4_HDR, /* PTYPE 27 */
214 PKT_RX_IPV4_HDR, /* PTYPE 28 */
215 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
220 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
221 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
222 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
223 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
224 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
226 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
227 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
228 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
229 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
230 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
231 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
232 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
234 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
235 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
236 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
237 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
238 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
239 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
241 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
242 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
243 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
244 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
245 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
246 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
247 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
249 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
250 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
251 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
252 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
253 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
254 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
256 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
257 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
258 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
259 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
260 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
261 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
262 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
264 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
265 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
266 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
267 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
268 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
269 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
271 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
272 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
273 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
274 PKT_RX_IPV6_HDR, /* PTYPE 88 */
275 PKT_RX_IPV6_HDR, /* PTYPE 89 */
276 PKT_RX_IPV6_HDR, /* PTYPE 90 */
278 PKT_RX_IPV6_HDR, /* PTYPE 92 */
279 PKT_RX_IPV6_HDR, /* PTYPE 93 */
280 PKT_RX_IPV6_HDR, /* PTYPE 94 */
281 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
286 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
287 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
288 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
289 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
290 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
292 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
293 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
294 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
295 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
296 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
297 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
298 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
300 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
301 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
302 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
303 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
304 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
305 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
307 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
308 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
309 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
310 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
311 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
312 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
313 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
315 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
316 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
317 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
318 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
319 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
320 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
322 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
323 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
324 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
325 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
326 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
327 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
328 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
330 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
331 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
332 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
333 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
334 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
335 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
337 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
338 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
339 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
444 return ip_ptype_map[ptype];
447 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
448 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
449 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
450 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
451 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
453 static inline uint64_t
454 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
457 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
458 uint16_t flexbh, flexbl;
460 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
461 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
462 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
463 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
464 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
465 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
468 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
470 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
471 flags |= PKT_RX_FDIR_ID;
472 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
474 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
475 flags |= PKT_RX_FDIR_FLX;
477 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
479 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
480 flags |= PKT_RX_FDIR_FLX;
484 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
485 flags |= PKT_RX_FDIR_ID;
490 i40e_txd_enable_checksum(uint64_t ol_flags,
493 union i40e_tx_offload tx_offload,
494 uint32_t *cd_tunneling)
496 /* UDP tunneling packet TX checksum offload */
497 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
499 *td_offset |= (tx_offload.outer_l2_len >> 1)
500 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
502 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
503 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
504 else if (ol_flags & PKT_TX_OUTER_IPV4)
505 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
506 else if (ol_flags & PKT_TX_OUTER_IPV6)
507 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
509 /* Now set the ctx descriptor fields */
510 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
511 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
512 (tx_offload.l2_len >> 1) <<
513 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
516 *td_offset |= (tx_offload.l2_len >> 1)
517 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
519 /* Enable L3 checksum offloads */
520 if (ol_flags & PKT_TX_IP_CKSUM) {
521 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
522 *td_offset |= (tx_offload.l3_len >> 2)
523 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
524 } else if (ol_flags & PKT_TX_IPV4) {
525 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
526 *td_offset |= (tx_offload.l3_len >> 2)
527 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
528 } else if (ol_flags & PKT_TX_IPV6) {
529 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
530 *td_offset |= (tx_offload.l3_len >> 2)
531 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
534 if (ol_flags & PKT_TX_TCP_SEG) {
535 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
536 *td_offset |= (tx_offload.l4_len >> 2)
537 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
541 /* Enable L4 checksum offloads */
542 switch (ol_flags & PKT_TX_L4_MASK) {
543 case PKT_TX_TCP_CKSUM:
544 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
545 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
546 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
548 case PKT_TX_SCTP_CKSUM:
549 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
550 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
551 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
553 case PKT_TX_UDP_CKSUM:
554 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
555 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
556 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
563 static inline struct rte_mbuf *
564 rte_rxmbuf_alloc(struct rte_mempool *mp)
568 m = __rte_mbuf_raw_alloc(mp);
569 __rte_mbuf_sanity_check_raw(m, 0);
574 /* Construct the tx flags */
575 static inline uint64_t
576 i40e_build_ctob(uint32_t td_cmd,
581 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
582 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
583 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
584 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
585 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
589 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
591 struct i40e_tx_entry *sw_ring = txq->sw_ring;
592 volatile struct i40e_tx_desc *txd = txq->tx_ring;
593 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
594 uint16_t nb_tx_desc = txq->nb_tx_desc;
595 uint16_t desc_to_clean_to;
596 uint16_t nb_tx_to_clean;
598 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
599 if (desc_to_clean_to >= nb_tx_desc)
600 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
602 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
603 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
604 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
605 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
606 "(port=%d queue=%d)", desc_to_clean_to,
607 txq->port_id, txq->queue_id);
611 if (last_desc_cleaned > desc_to_clean_to)
612 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
615 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
618 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
620 txq->last_desc_cleaned = desc_to_clean_to;
621 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
627 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
628 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
630 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
635 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
636 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
637 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
638 "rxq->rx_free_thresh=%d, "
639 "RTE_PMD_I40E_RX_MAX_BURST=%d",
640 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
642 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
643 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
644 "rxq->rx_free_thresh=%d, "
645 "rxq->nb_rx_desc=%d",
646 rxq->rx_free_thresh, rxq->nb_rx_desc);
648 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
649 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
650 "rxq->nb_rx_desc=%d, "
651 "rxq->rx_free_thresh=%d",
652 rxq->nb_rx_desc, rxq->rx_free_thresh);
654 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
655 RTE_PMD_I40E_RX_MAX_BURST))) {
656 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
657 "rxq->nb_rx_desc=%d, "
658 "I40E_MAX_RING_DESC=%d, "
659 "RTE_PMD_I40E_RX_MAX_BURST=%d",
660 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
661 RTE_PMD_I40E_RX_MAX_BURST);
671 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
672 #define I40E_LOOK_AHEAD 8
673 #if (I40E_LOOK_AHEAD != 8)
674 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
677 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
679 volatile union i40e_rx_desc *rxdp;
680 struct i40e_rx_entry *rxep;
685 int32_t s[I40E_LOOK_AHEAD], nb_dd;
686 int32_t i, j, nb_rx = 0;
689 rxdp = &rxq->rx_ring[rxq->rx_tail];
690 rxep = &rxq->sw_ring[rxq->rx_tail];
692 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
693 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
694 I40E_RXD_QW1_STATUS_SHIFT;
696 /* Make sure there is at least 1 packet to receive */
697 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
701 * Scan LOOK_AHEAD descriptors at a time to determine which
702 * descriptors reference packets that are ready to be received.
704 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
705 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
706 /* Read desc statuses backwards to avoid race condition */
707 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
708 qword1 = rte_le_to_cpu_64(\
709 rxdp[j].wb.qword1.status_error_len);
710 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
711 I40E_RXD_QW1_STATUS_SHIFT;
714 /* Compute how many status bits were set */
715 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
716 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
720 /* Translate descriptor info to mbuf parameters */
721 for (j = 0; j < nb_dd; j++) {
723 qword1 = rte_le_to_cpu_64(\
724 rxdp[j].wb.qword1.status_error_len);
725 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
726 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
727 mb->data_len = pkt_len;
728 mb->pkt_len = pkt_len;
730 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
731 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
732 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
733 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
735 mb->packet_type = (uint16_t)((qword1 &
736 I40E_RXD_QW1_PTYPE_MASK) >>
737 I40E_RXD_QW1_PTYPE_SHIFT);
738 if (pkt_flags & PKT_RX_RSS_HASH)
739 mb->hash.rss = rte_le_to_cpu_32(\
740 rxdp[j].wb.qword0.hi_dword.rss);
741 if (pkt_flags & PKT_RX_FDIR)
742 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
744 #ifdef RTE_LIBRTE_IEEE1588
745 uint16_t tsyn = (qword1
746 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
747 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
748 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
751 pkt_flags |= PKT_RX_IEEE1588_TMST;
753 mb->timesync = tsyn & 0x03;
755 mb->ol_flags |= pkt_flags;
759 for (j = 0; j < I40E_LOOK_AHEAD; j++)
760 rxq->rx_stage[i + j] = rxep[j].mbuf;
762 if (nb_dd != I40E_LOOK_AHEAD)
766 /* Clear software ring entries */
767 for (i = 0; i < nb_rx; i++)
768 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
773 static inline uint16_t
774 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
775 struct rte_mbuf **rx_pkts,
779 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
781 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
783 for (i = 0; i < nb_pkts; i++)
784 rx_pkts[i] = stage[i];
786 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
787 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
793 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
795 volatile union i40e_rx_desc *rxdp;
796 struct i40e_rx_entry *rxep;
798 uint16_t alloc_idx, i;
802 /* Allocate buffers in bulk */
803 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
804 (rxq->rx_free_thresh - 1));
805 rxep = &(rxq->sw_ring[alloc_idx]);
806 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
807 rxq->rx_free_thresh);
808 if (unlikely(diag != 0)) {
809 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
813 rxdp = &rxq->rx_ring[alloc_idx];
814 for (i = 0; i < rxq->rx_free_thresh; i++) {
816 rte_mbuf_refcnt_set(mb, 1);
818 mb->data_off = RTE_PKTMBUF_HEADROOM;
820 mb->port = rxq->port_id;
821 dma_addr = rte_cpu_to_le_64(\
822 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
823 rxdp[i].read.hdr_addr = dma_addr;
824 rxdp[i].read.pkt_addr = dma_addr;
827 /* Update rx tail regsiter */
829 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
831 rxq->rx_free_trigger =
832 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
833 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
834 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
839 static inline uint16_t
840 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
842 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
848 if (rxq->rx_nb_avail)
849 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
851 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
852 rxq->rx_next_avail = 0;
853 rxq->rx_nb_avail = nb_rx;
854 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
856 if (rxq->rx_tail > rxq->rx_free_trigger) {
857 if (i40e_rx_alloc_bufs(rxq) != 0) {
860 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
861 "port_id=%u, queue_id=%u",
862 rxq->port_id, rxq->queue_id);
863 rxq->rx_nb_avail = 0;
864 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
865 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
866 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
872 if (rxq->rx_tail >= rxq->nb_rx_desc)
875 if (rxq->rx_nb_avail)
876 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
882 i40e_recv_pkts_bulk_alloc(void *rx_queue,
883 struct rte_mbuf **rx_pkts,
886 uint16_t nb_rx = 0, n, count;
888 if (unlikely(nb_pkts == 0))
891 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
892 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
895 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
896 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
897 nb_rx = (uint16_t)(nb_rx + count);
898 nb_pkts = (uint16_t)(nb_pkts - count);
905 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
908 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
910 struct i40e_rx_queue *rxq;
911 volatile union i40e_rx_desc *rx_ring;
912 volatile union i40e_rx_desc *rxdp;
913 union i40e_rx_desc rxd;
914 struct i40e_rx_entry *sw_ring;
915 struct i40e_rx_entry *rxe;
916 struct rte_mbuf *rxm;
917 struct rte_mbuf *nmb;
921 uint16_t rx_packet_len;
922 uint16_t rx_id, nb_hold;
929 rx_id = rxq->rx_tail;
930 rx_ring = rxq->rx_ring;
931 sw_ring = rxq->sw_ring;
933 while (nb_rx < nb_pkts) {
934 rxdp = &rx_ring[rx_id];
935 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
936 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
937 >> I40E_RXD_QW1_STATUS_SHIFT;
939 /* Check the DD bit first */
940 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
943 nmb = rte_rxmbuf_alloc(rxq->mp);
949 rxe = &sw_ring[rx_id];
951 if (unlikely(rx_id == rxq->nb_rx_desc))
954 /* Prefetch next mbuf */
955 rte_prefetch0(sw_ring[rx_id].mbuf);
958 * When next RX descriptor is on a cache line boundary,
959 * prefetch the next 4 RX descriptors and next 8 pointers
962 if ((rx_id & 0x3) == 0) {
963 rte_prefetch0(&rx_ring[rx_id]);
964 rte_prefetch0(&sw_ring[rx_id]);
969 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
970 rxdp->read.hdr_addr = dma_addr;
971 rxdp->read.pkt_addr = dma_addr;
973 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
974 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
976 rxm->data_off = RTE_PKTMBUF_HEADROOM;
977 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
980 rxm->pkt_len = rx_packet_len;
981 rxm->data_len = rx_packet_len;
982 rxm->port = rxq->port_id;
984 i40e_rxd_to_vlan_tci(rxm, &rxd);
985 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
986 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
987 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
988 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
989 I40E_RXD_QW1_PTYPE_SHIFT);
990 if (pkt_flags & PKT_RX_RSS_HASH)
992 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
993 if (pkt_flags & PKT_RX_FDIR)
994 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
996 #ifdef RTE_LIBRTE_IEEE1588
997 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
998 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
999 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1002 pkt_flags |= PKT_RX_IEEE1588_TMST;
1004 rxm->timesync = tsyn & 0x03;
1006 rxm->ol_flags |= pkt_flags;
1008 rx_pkts[nb_rx++] = rxm;
1010 rxq->rx_tail = rx_id;
1013 * If the number of free RX descriptors is greater than the RX free
1014 * threshold of the queue, advance the receive tail register of queue.
1015 * Update that register with the value of the last processed RX
1016 * descriptor minus 1.
1018 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1019 if (nb_hold > rxq->rx_free_thresh) {
1020 rx_id = (uint16_t) ((rx_id == 0) ?
1021 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1022 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1025 rxq->nb_rx_hold = nb_hold;
1031 i40e_recv_scattered_pkts(void *rx_queue,
1032 struct rte_mbuf **rx_pkts,
1035 struct i40e_rx_queue *rxq = rx_queue;
1036 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1037 volatile union i40e_rx_desc *rxdp;
1038 union i40e_rx_desc rxd;
1039 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1040 struct i40e_rx_entry *rxe;
1041 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1042 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1043 struct rte_mbuf *nmb, *rxm;
1044 uint16_t rx_id = rxq->rx_tail;
1045 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1051 while (nb_rx < nb_pkts) {
1052 rxdp = &rx_ring[rx_id];
1053 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1054 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1055 I40E_RXD_QW1_STATUS_SHIFT;
1057 /* Check the DD bit */
1058 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1061 nmb = rte_rxmbuf_alloc(rxq->mp);
1066 rxe = &sw_ring[rx_id];
1068 if (rx_id == rxq->nb_rx_desc)
1071 /* Prefetch next mbuf */
1072 rte_prefetch0(sw_ring[rx_id].mbuf);
1075 * When next RX descriptor is on a cache line boundary,
1076 * prefetch the next 4 RX descriptors and next 8 pointers
1079 if ((rx_id & 0x3) == 0) {
1080 rte_prefetch0(&rx_ring[rx_id]);
1081 rte_prefetch0(&sw_ring[rx_id]);
1087 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1089 /* Set data buffer address and data length of the mbuf */
1090 rxdp->read.hdr_addr = dma_addr;
1091 rxdp->read.pkt_addr = dma_addr;
1092 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1093 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1094 rxm->data_len = rx_packet_len;
1095 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1098 * If this is the first buffer of the received packet, set the
1099 * pointer to the first mbuf of the packet and initialize its
1100 * context. Otherwise, update the total length and the number
1101 * of segments of the current scattered packet, and update the
1102 * pointer to the last mbuf of the current packet.
1106 first_seg->nb_segs = 1;
1107 first_seg->pkt_len = rx_packet_len;
1109 first_seg->pkt_len =
1110 (uint16_t)(first_seg->pkt_len +
1112 first_seg->nb_segs++;
1113 last_seg->next = rxm;
1117 * If this is not the last buffer of the received packet,
1118 * update the pointer to the last mbuf of the current scattered
1119 * packet and continue to parse the RX ring.
1121 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1127 * This is the last buffer of the received packet. If the CRC
1128 * is not stripped by the hardware:
1129 * - Subtract the CRC length from the total packet length.
1130 * - If the last buffer only contains the whole CRC or a part
1131 * of it, free the mbuf associated to the last buffer. If part
1132 * of the CRC is also contained in the previous mbuf, subtract
1133 * the length of that CRC part from the data length of the
1137 if (unlikely(rxq->crc_len > 0)) {
1138 first_seg->pkt_len -= ETHER_CRC_LEN;
1139 if (rx_packet_len <= ETHER_CRC_LEN) {
1140 rte_pktmbuf_free_seg(rxm);
1141 first_seg->nb_segs--;
1142 last_seg->data_len =
1143 (uint16_t)(last_seg->data_len -
1144 (ETHER_CRC_LEN - rx_packet_len));
1145 last_seg->next = NULL;
1147 rxm->data_len = (uint16_t)(rx_packet_len -
1151 first_seg->port = rxq->port_id;
1152 first_seg->ol_flags = 0;
1153 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1154 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1155 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1156 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1157 first_seg->packet_type = (uint16_t)((qword1 &
1158 I40E_RXD_QW1_PTYPE_MASK) >>
1159 I40E_RXD_QW1_PTYPE_SHIFT);
1160 if (pkt_flags & PKT_RX_RSS_HASH)
1162 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1163 if (pkt_flags & PKT_RX_FDIR)
1164 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1166 #ifdef RTE_LIBRTE_IEEE1588
1167 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1168 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1169 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1172 pkt_flags |= PKT_RX_IEEE1588_TMST;
1174 first_seg->timesync = tsyn & 0x03;
1176 first_seg->ol_flags |= pkt_flags;
1178 /* Prefetch data of first segment, if configured to do so. */
1179 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1180 first_seg->data_off));
1181 rx_pkts[nb_rx++] = first_seg;
1185 /* Record index of the next RX descriptor to probe. */
1186 rxq->rx_tail = rx_id;
1187 rxq->pkt_first_seg = first_seg;
1188 rxq->pkt_last_seg = last_seg;
1191 * If the number of free RX descriptors is greater than the RX free
1192 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1193 * register. Update the RDT with the value of the last processed RX
1194 * descriptor minus 1, to guarantee that the RDT register is never
1195 * equal to the RDH register, which creates a "full" ring situtation
1196 * from the hardware point of view.
1198 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1199 if (nb_hold > rxq->rx_free_thresh) {
1200 rx_id = (uint16_t)(rx_id == 0 ?
1201 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1202 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1205 rxq->nb_rx_hold = nb_hold;
1210 /* Check if the context descriptor is needed for TX offloading */
1211 static inline uint16_t
1212 i40e_calc_context_desc(uint64_t flags)
1214 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1218 #ifdef RTE_LIBRTE_IEEE1588
1219 mask |= PKT_TX_IEEE1588_TMST;
1222 return ((flags & mask) ? 1 : 0);
1225 /* set i40e TSO context descriptor */
1226 static inline uint64_t
1227 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1229 uint64_t ctx_desc = 0;
1230 uint32_t cd_cmd, hdr_len, cd_tso_len;
1232 if (!tx_offload.l4_len) {
1233 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1238 * in case of tunneling packet, the outer_l2_len and
1239 * outer_l3_len must be 0.
1241 hdr_len = tx_offload.outer_l2_len +
1242 tx_offload.outer_l3_len +
1247 cd_cmd = I40E_TX_CTX_DESC_TSO;
1248 cd_tso_len = mbuf->pkt_len - hdr_len;
1249 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1250 ((uint64_t)cd_tso_len <<
1251 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1252 ((uint64_t)mbuf->tso_segsz <<
1253 I40E_TXD_CTX_QW1_MSS_SHIFT);
1259 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1261 struct i40e_tx_queue *txq;
1262 struct i40e_tx_entry *sw_ring;
1263 struct i40e_tx_entry *txe, *txn;
1264 volatile struct i40e_tx_desc *txd;
1265 volatile struct i40e_tx_desc *txr;
1266 struct rte_mbuf *tx_pkt;
1267 struct rte_mbuf *m_seg;
1268 uint32_t cd_tunneling_params;
1280 uint64_t buf_dma_addr;
1281 union i40e_tx_offload tx_offload = {0};
1284 sw_ring = txq->sw_ring;
1286 tx_id = txq->tx_tail;
1287 txe = &sw_ring[tx_id];
1289 /* Check if the descriptor ring needs to be cleaned. */
1290 if (txq->nb_tx_free < txq->tx_free_thresh)
1291 i40e_xmit_cleanup(txq);
1293 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1299 tx_pkt = *tx_pkts++;
1300 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1302 ol_flags = tx_pkt->ol_flags;
1303 tx_offload.l2_len = tx_pkt->l2_len;
1304 tx_offload.l3_len = tx_pkt->l3_len;
1305 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1306 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1307 tx_offload.l4_len = tx_pkt->l4_len;
1308 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1310 /* Calculate the number of context descriptors needed. */
1311 nb_ctx = i40e_calc_context_desc(ol_flags);
1314 * The number of descriptors that must be allocated for
1315 * a packet equals to the number of the segments of that
1316 * packet plus 1 context descriptor if needed.
1318 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1319 tx_last = (uint16_t)(tx_id + nb_used - 1);
1322 if (tx_last >= txq->nb_tx_desc)
1323 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1325 if (nb_used > txq->nb_tx_free) {
1326 if (i40e_xmit_cleanup(txq) != 0) {
1331 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1332 while (nb_used > txq->nb_tx_free) {
1333 if (i40e_xmit_cleanup(txq) != 0) {
1342 /* Descriptor based VLAN insertion */
1343 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1344 tx_flags |= tx_pkt->vlan_tci <<
1345 I40E_TX_FLAG_L2TAG1_SHIFT;
1346 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1347 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1348 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1349 I40E_TX_FLAG_L2TAG1_SHIFT;
1352 /* Always enable CRC offload insertion */
1353 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1355 /* Enable checksum offloading */
1356 cd_tunneling_params = 0;
1357 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1358 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1359 tx_offload, &cd_tunneling_params);
1362 if (unlikely(nb_ctx)) {
1363 /* Setup TX context descriptor if required */
1364 volatile struct i40e_tx_context_desc *ctx_txd =
1365 (volatile struct i40e_tx_context_desc *)\
1367 uint16_t cd_l2tag2 = 0;
1368 uint64_t cd_type_cmd_tso_mss =
1369 I40E_TX_DESC_DTYPE_CONTEXT;
1371 txn = &sw_ring[txe->next_id];
1372 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1373 if (txe->mbuf != NULL) {
1374 rte_pktmbuf_free_seg(txe->mbuf);
1378 /* TSO enabled means no timestamp */
1379 if (ol_flags & PKT_TX_TCP_SEG)
1380 cd_type_cmd_tso_mss |=
1381 i40e_set_tso_ctx(tx_pkt, tx_offload);
1383 #ifdef RTE_LIBRTE_IEEE1588
1384 if (ol_flags & PKT_TX_IEEE1588_TMST)
1385 cd_type_cmd_tso_mss |=
1386 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1387 I40E_TXD_CTX_QW1_CMD_SHIFT);
1391 ctx_txd->tunneling_params =
1392 rte_cpu_to_le_32(cd_tunneling_params);
1393 if (ol_flags & PKT_TX_QINQ_PKT) {
1394 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1395 cd_type_cmd_tso_mss |=
1396 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1397 I40E_TXD_CTX_QW1_CMD_SHIFT);
1399 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1400 ctx_txd->type_cmd_tso_mss =
1401 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1403 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1404 "tunneling_params: %#x;\n"
1407 "type_cmd_tso_mss: %#"PRIx64";\n",
1409 ctx_txd->tunneling_params,
1412 ctx_txd->type_cmd_tso_mss);
1414 txe->last_id = tx_last;
1415 tx_id = txe->next_id;
1422 txn = &sw_ring[txe->next_id];
1425 rte_pktmbuf_free_seg(txe->mbuf);
1428 /* Setup TX Descriptor */
1429 slen = m_seg->data_len;
1430 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1432 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1433 "buf_dma_addr: %#"PRIx64";\n"
1438 tx_pkt, tx_id, buf_dma_addr,
1439 td_cmd, td_offset, slen, td_tag);
1441 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1442 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1443 td_offset, slen, td_tag);
1444 txe->last_id = tx_last;
1445 tx_id = txe->next_id;
1447 m_seg = m_seg->next;
1448 } while (m_seg != NULL);
1450 /* The last packet data descriptor needs End Of Packet (EOP) */
1451 td_cmd |= I40E_TX_DESC_CMD_EOP;
1452 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1453 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1455 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1456 PMD_TX_FREE_LOG(DEBUG,
1457 "Setting RS bit on TXD id="
1458 "%4u (port=%d queue=%d)",
1459 tx_last, txq->port_id, txq->queue_id);
1461 td_cmd |= I40E_TX_DESC_CMD_RS;
1463 /* Update txq RS bit counters */
1464 txq->nb_tx_used = 0;
1467 txd->cmd_type_offset_bsz |=
1468 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1469 I40E_TXD_QW1_CMD_SHIFT);
1475 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1476 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1477 (unsigned) tx_id, (unsigned) nb_tx);
1479 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1480 txq->tx_tail = tx_id;
1485 static inline int __attribute__((always_inline))
1486 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1488 struct i40e_tx_entry *txep;
1491 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1492 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1495 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1497 for (i = 0; i < txq->tx_rs_thresh; i++)
1498 rte_prefetch0((txep + i)->mbuf);
1500 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1501 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1502 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1506 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1507 rte_pktmbuf_free_seg(txep->mbuf);
1512 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1513 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1514 if (txq->tx_next_dd >= txq->nb_tx_desc)
1515 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1517 return txq->tx_rs_thresh;
1520 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1521 I40E_TX_DESC_CMD_EOP)
1523 /* Populate 4 descriptors with data from 4 mbufs */
1525 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1530 for (i = 0; i < 4; i++, txdp++, pkts++) {
1531 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1532 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1533 txdp->cmd_type_offset_bsz =
1534 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1535 (*pkts)->data_len, 0);
1539 /* Populate 1 descriptor with data from 1 mbuf */
1541 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1545 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1546 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1547 txdp->cmd_type_offset_bsz =
1548 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1549 (*pkts)->data_len, 0);
1552 /* Fill hardware descriptor ring with mbuf data */
1554 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1555 struct rte_mbuf **pkts,
1558 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1559 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1560 const int N_PER_LOOP = 4;
1561 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1562 int mainpart, leftover;
1565 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1566 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1567 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1568 for (j = 0; j < N_PER_LOOP; ++j) {
1569 (txep + i + j)->mbuf = *(pkts + i + j);
1571 tx4(txdp + i, pkts + i);
1573 if (unlikely(leftover > 0)) {
1574 for (i = 0; i < leftover; ++i) {
1575 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1576 tx1(txdp + mainpart + i, pkts + mainpart + i);
1581 static inline uint16_t
1582 tx_xmit_pkts(struct i40e_tx_queue *txq,
1583 struct rte_mbuf **tx_pkts,
1586 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1590 * Begin scanning the H/W ring for done descriptors when the number
1591 * of available descriptors drops below tx_free_thresh. For each done
1592 * descriptor, free the associated buffer.
1594 if (txq->nb_tx_free < txq->tx_free_thresh)
1595 i40e_tx_free_bufs(txq);
1597 /* Use available descriptor only */
1598 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1599 if (unlikely(!nb_pkts))
1602 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1603 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1604 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1605 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1606 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1607 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1608 I40E_TXD_QW1_CMD_SHIFT);
1609 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1613 /* Fill hardware descriptor ring with mbuf data */
1614 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1615 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1617 /* Determin if RS bit needs to be set */
1618 if (txq->tx_tail > txq->tx_next_rs) {
1619 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1620 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1621 I40E_TXD_QW1_CMD_SHIFT);
1623 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1624 if (txq->tx_next_rs >= txq->nb_tx_desc)
1625 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1628 if (txq->tx_tail >= txq->nb_tx_desc)
1631 /* Update the tx tail register */
1633 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1639 i40e_xmit_pkts_simple(void *tx_queue,
1640 struct rte_mbuf **tx_pkts,
1645 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1646 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1650 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1653 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1654 &tx_pkts[nb_tx], num);
1655 nb_tx = (uint16_t)(nb_tx + ret);
1656 nb_pkts = (uint16_t)(nb_pkts - ret);
1665 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1666 * application used, which assume having sequential ones. But from driver's
1667 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1668 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1669 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1670 * use queue_idx from 0 to 95 to access queues, while real queue would be
1671 * different. This function will do a queue mapping to find VSI the queue
1674 static struct i40e_vsi*
1675 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1677 /* the queue in MAIN VSI range */
1678 if (queue_idx < pf->main_vsi->nb_qps)
1679 return pf->main_vsi;
1681 queue_idx -= pf->main_vsi->nb_qps;
1683 /* queue_idx is greater than VMDQ VSIs range */
1684 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1685 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1689 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1693 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1695 /* the queue in MAIN VSI range */
1696 if (queue_idx < pf->main_vsi->nb_qps)
1699 /* It's VMDQ queues */
1700 queue_idx -= pf->main_vsi->nb_qps;
1702 if (pf->nb_cfg_vmdq_vsi)
1703 return queue_idx % pf->vmdq_nb_qps;
1705 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1706 return (uint16_t)(-1);
1711 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1713 struct i40e_rx_queue *rxq;
1715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1717 PMD_INIT_FUNC_TRACE();
1719 if (rx_queue_id < dev->data->nb_rx_queues) {
1720 rxq = dev->data->rx_queues[rx_queue_id];
1722 err = i40e_alloc_rx_queue_mbufs(rxq);
1724 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1730 /* Init the RX tail regieter. */
1731 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1733 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1736 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1739 i40e_rx_queue_release_mbufs(rxq);
1740 i40e_reset_rx_queue(rxq);
1748 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1750 struct i40e_rx_queue *rxq;
1752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 if (rx_queue_id < dev->data->nb_rx_queues) {
1755 rxq = dev->data->rx_queues[rx_queue_id];
1758 * rx_queue_id is queue id aplication refers to, while
1759 * rxq->reg_idx is the real queue index.
1761 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1764 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1768 i40e_rx_queue_release_mbufs(rxq);
1769 i40e_reset_rx_queue(rxq);
1776 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1779 struct i40e_tx_queue *txq;
1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782 PMD_INIT_FUNC_TRACE();
1784 if (tx_queue_id < dev->data->nb_tx_queues) {
1785 txq = dev->data->tx_queues[tx_queue_id];
1788 * tx_queue_id is queue id aplication refers to, while
1789 * rxq->reg_idx is the real queue index.
1791 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1793 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1801 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1803 struct i40e_tx_queue *txq;
1805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807 if (tx_queue_id < dev->data->nb_tx_queues) {
1808 txq = dev->data->tx_queues[tx_queue_id];
1811 * tx_queue_id is queue id aplication refers to, while
1812 * txq->reg_idx is the real queue index.
1814 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1817 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1822 i40e_tx_queue_release_mbufs(txq);
1823 i40e_reset_tx_queue(txq);
1830 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1833 unsigned int socket_id,
1834 const struct rte_eth_rxconf *rx_conf,
1835 struct rte_mempool *mp)
1837 struct i40e_vsi *vsi;
1838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1840 struct i40e_rx_queue *rxq;
1841 const struct rte_memzone *rz;
1844 int use_def_burst_func = 1;
1846 if (hw->mac.type == I40E_MAC_VF) {
1847 struct i40e_vf *vf =
1848 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1851 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1854 PMD_DRV_LOG(ERR, "VSI not available or queue "
1855 "index exceeds the maximum");
1856 return I40E_ERR_PARAM;
1858 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1859 (nb_desc > I40E_MAX_RING_DESC) ||
1860 (nb_desc < I40E_MIN_RING_DESC)) {
1861 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1862 "invalid", nb_desc);
1863 return I40E_ERR_PARAM;
1866 /* Free memory if needed */
1867 if (dev->data->rx_queues[queue_idx]) {
1868 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1869 dev->data->rx_queues[queue_idx] = NULL;
1872 /* Allocate the rx queue data structure */
1873 rxq = rte_zmalloc_socket("i40e rx queue",
1874 sizeof(struct i40e_rx_queue),
1875 RTE_CACHE_LINE_SIZE,
1878 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1879 "rx queue data structure");
1883 rxq->nb_rx_desc = nb_desc;
1884 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1885 rxq->queue_id = queue_idx;
1886 if (hw->mac.type == I40E_MAC_VF)
1887 rxq->reg_idx = queue_idx;
1888 else /* PF device */
1889 rxq->reg_idx = vsi->base_queue +
1890 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1892 rxq->port_id = dev->data->port_id;
1893 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1895 rxq->drop_en = rx_conf->rx_drop_en;
1897 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1899 /* Allocate the maximun number of RX ring hardware descriptor. */
1900 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1901 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1902 rz = i40e_ring_dma_zone_reserve(dev,
1908 i40e_dev_rx_queue_release(rxq);
1909 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1913 /* Zero all the descriptors in the ring. */
1914 memset(rz->addr, 0, ring_size);
1916 #ifdef RTE_LIBRTE_XEN_DOM0
1917 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1919 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1922 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1924 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1925 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1930 /* Allocate the software ring. */
1932 rte_zmalloc_socket("i40e rx sw ring",
1933 sizeof(struct i40e_rx_entry) * len,
1934 RTE_CACHE_LINE_SIZE,
1936 if (!rxq->sw_ring) {
1937 i40e_dev_rx_queue_release(rxq);
1938 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1942 i40e_reset_rx_queue(rxq);
1944 dev->data->rx_queues[queue_idx] = rxq;
1946 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1948 if (!use_def_burst_func && !dev->data->scattered_rx) {
1949 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1950 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1951 "satisfied. Rx Burst Bulk Alloc function will be "
1952 "used on port=%d, queue=%d.",
1953 rxq->port_id, rxq->queue_id);
1954 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1955 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1957 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1958 "not satisfied, Scattered Rx is requested, "
1959 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1960 "not enabled on port=%d, queue=%d.",
1961 rxq->port_id, rxq->queue_id);
1968 i40e_dev_rx_queue_release(void *rxq)
1970 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1973 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1977 i40e_rx_queue_release_mbufs(q);
1978 rte_free(q->sw_ring);
1983 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1985 #define I40E_RXQ_SCAN_INTERVAL 4
1986 volatile union i40e_rx_desc *rxdp;
1987 struct i40e_rx_queue *rxq;
1990 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1991 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1995 rxq = dev->data->rx_queues[rx_queue_id];
1996 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1997 while ((desc < rxq->nb_rx_desc) &&
1998 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1999 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2000 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2002 * Check the DD bit of a rx descriptor of each 4 in a group,
2003 * to avoid checking too frequently and downgrading performance
2006 desc += I40E_RXQ_SCAN_INTERVAL;
2007 rxdp += I40E_RXQ_SCAN_INTERVAL;
2008 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2009 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2010 desc - rxq->nb_rx_desc]);
2017 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2019 volatile union i40e_rx_desc *rxdp;
2020 struct i40e_rx_queue *rxq = rx_queue;
2024 if (unlikely(offset >= rxq->nb_rx_desc)) {
2025 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2029 desc = rxq->rx_tail + offset;
2030 if (desc >= rxq->nb_rx_desc)
2031 desc -= rxq->nb_rx_desc;
2033 rxdp = &(rxq->rx_ring[desc]);
2035 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2036 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2037 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2043 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2046 unsigned int socket_id,
2047 const struct rte_eth_txconf *tx_conf)
2049 struct i40e_vsi *vsi;
2050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2052 struct i40e_tx_queue *txq;
2053 const struct rte_memzone *tz;
2055 uint16_t tx_rs_thresh, tx_free_thresh;
2057 if (hw->mac.type == I40E_MAC_VF) {
2058 struct i40e_vf *vf =
2059 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2062 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2065 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2066 "exceeds the maximum", queue_idx);
2067 return I40E_ERR_PARAM;
2070 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2071 (nb_desc > I40E_MAX_RING_DESC) ||
2072 (nb_desc < I40E_MIN_RING_DESC)) {
2073 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2074 "invalid", nb_desc);
2075 return I40E_ERR_PARAM;
2079 * The following two parameters control the setting of the RS bit on
2080 * transmit descriptors. TX descriptors will have their RS bit set
2081 * after txq->tx_rs_thresh descriptors have been used. The TX
2082 * descriptor ring will be cleaned after txq->tx_free_thresh
2083 * descriptors are used or if the number of descriptors required to
2084 * transmit a packet is greater than the number of free TX descriptors.
2086 * The following constraints must be satisfied:
2087 * - tx_rs_thresh must be greater than 0.
2088 * - tx_rs_thresh must be less than the size of the ring minus 2.
2089 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2090 * - tx_rs_thresh must be a divisor of the ring size.
2091 * - tx_free_thresh must be greater than 0.
2092 * - tx_free_thresh must be less than the size of the ring minus 3.
2094 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2095 * race condition, hence the maximum threshold constraints. When set
2096 * to zero use default values.
2098 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2099 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2100 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2101 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2102 if (tx_rs_thresh >= (nb_desc - 2)) {
2103 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2104 "number of TX descriptors minus 2. "
2105 "(tx_rs_thresh=%u port=%d queue=%d)",
2106 (unsigned int)tx_rs_thresh,
2107 (int)dev->data->port_id,
2109 return I40E_ERR_PARAM;
2111 if (tx_free_thresh >= (nb_desc - 3)) {
2112 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2113 "tx_free_thresh must be less than the "
2114 "number of TX descriptors minus 3. "
2115 "(tx_free_thresh=%u port=%d queue=%d)",
2116 (unsigned int)tx_free_thresh,
2117 (int)dev->data->port_id,
2119 return I40E_ERR_PARAM;
2121 if (tx_rs_thresh > tx_free_thresh) {
2122 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2123 "equal to tx_free_thresh. (tx_free_thresh=%u"
2124 " tx_rs_thresh=%u port=%d queue=%d)",
2125 (unsigned int)tx_free_thresh,
2126 (unsigned int)tx_rs_thresh,
2127 (int)dev->data->port_id,
2129 return I40E_ERR_PARAM;
2131 if ((nb_desc % tx_rs_thresh) != 0) {
2132 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2133 "number of TX descriptors. (tx_rs_thresh=%u"
2134 " port=%d queue=%d)",
2135 (unsigned int)tx_rs_thresh,
2136 (int)dev->data->port_id,
2138 return I40E_ERR_PARAM;
2140 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2141 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2142 "tx_rs_thresh is greater than 1. "
2143 "(tx_rs_thresh=%u port=%d queue=%d)",
2144 (unsigned int)tx_rs_thresh,
2145 (int)dev->data->port_id,
2147 return I40E_ERR_PARAM;
2150 /* Free memory if needed. */
2151 if (dev->data->tx_queues[queue_idx]) {
2152 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2153 dev->data->tx_queues[queue_idx] = NULL;
2156 /* Allocate the TX queue data structure. */
2157 txq = rte_zmalloc_socket("i40e tx queue",
2158 sizeof(struct i40e_tx_queue),
2159 RTE_CACHE_LINE_SIZE,
2162 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2163 "tx queue structure");
2167 /* Allocate TX hardware ring descriptors. */
2168 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2169 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2170 tz = i40e_ring_dma_zone_reserve(dev,
2176 i40e_dev_tx_queue_release(txq);
2177 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2181 txq->nb_tx_desc = nb_desc;
2182 txq->tx_rs_thresh = tx_rs_thresh;
2183 txq->tx_free_thresh = tx_free_thresh;
2184 txq->pthresh = tx_conf->tx_thresh.pthresh;
2185 txq->hthresh = tx_conf->tx_thresh.hthresh;
2186 txq->wthresh = tx_conf->tx_thresh.wthresh;
2187 txq->queue_id = queue_idx;
2188 if (hw->mac.type == I40E_MAC_VF)
2189 txq->reg_idx = queue_idx;
2190 else /* PF device */
2191 txq->reg_idx = vsi->base_queue +
2192 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2194 txq->port_id = dev->data->port_id;
2195 txq->txq_flags = tx_conf->txq_flags;
2197 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2199 #ifdef RTE_LIBRTE_XEN_DOM0
2200 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2202 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2204 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2206 /* Allocate software ring */
2208 rte_zmalloc_socket("i40e tx sw ring",
2209 sizeof(struct i40e_tx_entry) * nb_desc,
2210 RTE_CACHE_LINE_SIZE,
2212 if (!txq->sw_ring) {
2213 i40e_dev_tx_queue_release(txq);
2214 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2218 i40e_reset_tx_queue(txq);
2220 dev->data->tx_queues[queue_idx] = txq;
2222 /* Use a simple TX queue without offloads or multi segs if possible */
2223 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2224 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2225 PMD_INIT_LOG(INFO, "Using simple tx path");
2226 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2228 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2229 dev->tx_pkt_burst = i40e_xmit_pkts;
2236 i40e_dev_tx_queue_release(void *txq)
2238 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2241 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2245 i40e_tx_queue_release_mbufs(q);
2246 rte_free(q->sw_ring);
2250 static const struct rte_memzone *
2251 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2252 const char *ring_name,
2257 char z_name[RTE_MEMZONE_NAMESIZE];
2258 const struct rte_memzone *mz;
2260 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2261 dev->driver->pci_drv.name, ring_name,
2262 dev->data->port_id, queue_id);
2263 mz = rte_memzone_lookup(z_name);
2267 #ifdef RTE_LIBRTE_XEN_DOM0
2268 return rte_memzone_reserve_bounded(z_name, ring_size,
2269 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2271 return rte_memzone_reserve_aligned(z_name, ring_size,
2272 socket_id, 0, I40E_ALIGN);
2276 const struct rte_memzone *
2277 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2279 const struct rte_memzone *mz = NULL;
2281 mz = rte_memzone_lookup(name);
2284 #ifdef RTE_LIBRTE_XEN_DOM0
2285 mz = rte_memzone_reserve_bounded(name, len,
2286 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2288 mz = rte_memzone_reserve_aligned(name, len,
2289 socket_id, 0, I40E_ALIGN);
2295 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2299 if (!rxq || !rxq->sw_ring) {
2300 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2304 for (i = 0; i < rxq->nb_rx_desc; i++) {
2305 if (rxq->sw_ring[i].mbuf) {
2306 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2307 rxq->sw_ring[i].mbuf = NULL;
2310 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2311 if (rxq->rx_nb_avail == 0)
2313 for (i = 0; i < rxq->rx_nb_avail; i++) {
2314 struct rte_mbuf *mbuf;
2316 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2317 rte_pktmbuf_free_seg(mbuf);
2319 rxq->rx_nb_avail = 0;
2320 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2324 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2329 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2330 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2331 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2333 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2334 len = rxq->nb_rx_desc;
2336 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2337 ((volatile char *)rxq->rx_ring)[i] = 0;
2339 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2340 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2341 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2342 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2344 rxq->rx_nb_avail = 0;
2345 rxq->rx_next_avail = 0;
2346 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2347 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2349 rxq->nb_rx_hold = 0;
2350 rxq->pkt_first_seg = NULL;
2351 rxq->pkt_last_seg = NULL;
2355 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2359 if (!txq || !txq->sw_ring) {
2360 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2364 for (i = 0; i < txq->nb_tx_desc; i++) {
2365 if (txq->sw_ring[i].mbuf) {
2366 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2367 txq->sw_ring[i].mbuf = NULL;
2373 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2375 struct i40e_tx_entry *txe;
2376 uint16_t i, prev, size;
2379 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2384 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2385 for (i = 0; i < size; i++)
2386 ((volatile char *)txq->tx_ring)[i] = 0;
2388 prev = (uint16_t)(txq->nb_tx_desc - 1);
2389 for (i = 0; i < txq->nb_tx_desc; i++) {
2390 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2392 txd->cmd_type_offset_bsz =
2393 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2396 txe[prev].next_id = i;
2400 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2401 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2404 txq->nb_tx_used = 0;
2406 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2407 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2410 /* Init the TX queue in hardware */
2412 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2414 enum i40e_status_code err = I40E_SUCCESS;
2415 struct i40e_vsi *vsi = txq->vsi;
2416 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2417 uint16_t pf_q = txq->reg_idx;
2418 struct i40e_hmc_obj_txq tx_ctx;
2421 /* clear the context structure first */
2422 memset(&tx_ctx, 0, sizeof(tx_ctx));
2423 tx_ctx.new_context = 1;
2424 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2425 tx_ctx.qlen = txq->nb_tx_desc;
2427 #ifdef RTE_LIBRTE_IEEE1588
2428 tx_ctx.timesync_ena = 1;
2430 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2431 if (vsi->type == I40E_VSI_FDIR)
2432 tx_ctx.fd_ena = TRUE;
2434 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2435 if (err != I40E_SUCCESS) {
2436 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2440 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2441 if (err != I40E_SUCCESS) {
2442 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2446 /* Now associate this queue with this PCI function */
2447 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2448 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2449 I40E_QTX_CTL_PF_INDX_MASK);
2450 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2451 I40E_WRITE_FLUSH(hw);
2453 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2459 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2461 struct i40e_rx_entry *rxe = rxq->sw_ring;
2465 for (i = 0; i < rxq->nb_rx_desc; i++) {
2466 volatile union i40e_rx_desc *rxd;
2467 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2469 if (unlikely(!mbuf)) {
2470 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2474 rte_mbuf_refcnt_set(mbuf, 1);
2476 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2478 mbuf->port = rxq->port_id;
2481 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2483 rxd = &rxq->rx_ring[i];
2484 rxd->read.pkt_addr = dma_addr;
2485 rxd->read.hdr_addr = dma_addr;
2486 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2487 rxd->read.rsvd1 = 0;
2488 rxd->read.rsvd2 = 0;
2489 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2498 * Calculate the buffer length, and check the jumbo frame
2499 * and maximum packet length.
2502 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2504 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2505 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2506 struct rte_eth_dev_data *data = pf->dev_data;
2507 uint16_t buf_size, len;
2509 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2510 RTE_PKTMBUF_HEADROOM);
2512 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2513 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2514 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2515 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2516 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2517 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2518 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2519 rxq->hs_mode = i40e_header_split_enabled;
2521 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2523 rxq->rx_hdr_len = 0;
2524 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2525 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2526 rxq->hs_mode = i40e_header_split_none;
2530 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2531 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2532 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2533 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2534 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2535 PMD_DRV_LOG(ERR, "maximum packet length must "
2536 "be larger than %u and smaller than %u,"
2537 "as jumbo frame is enabled",
2538 (uint32_t)ETHER_MAX_LEN,
2539 (uint32_t)I40E_FRAME_SIZE_MAX);
2540 return I40E_ERR_CONFIG;
2543 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2544 rxq->max_pkt_len > ETHER_MAX_LEN) {
2545 PMD_DRV_LOG(ERR, "maximum packet length must be "
2546 "larger than %u and smaller than %u, "
2547 "as jumbo frame is disabled",
2548 (uint32_t)ETHER_MIN_LEN,
2549 (uint32_t)ETHER_MAX_LEN);
2550 return I40E_ERR_CONFIG;
2557 /* Init the RX queue in hardware */
2559 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2561 int err = I40E_SUCCESS;
2562 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2563 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2564 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2565 uint16_t pf_q = rxq->reg_idx;
2567 struct i40e_hmc_obj_rxq rx_ctx;
2569 err = i40e_rx_queue_config(rxq);
2571 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2575 /* Clear the context structure first */
2576 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2577 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2578 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2580 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2581 rx_ctx.qlen = rxq->nb_rx_desc;
2582 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2585 rx_ctx.dtype = rxq->hs_mode;
2587 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2589 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2590 rx_ctx.rxmax = rxq->max_pkt_len;
2591 rx_ctx.tphrdesc_ena = 1;
2592 rx_ctx.tphwdesc_ena = 1;
2593 rx_ctx.tphdata_ena = 1;
2594 rx_ctx.tphhead_ena = 1;
2595 rx_ctx.lrxqthresh = 2;
2596 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2601 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2602 if (err != I40E_SUCCESS) {
2603 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2606 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2607 if (err != I40E_SUCCESS) {
2608 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2612 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2614 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2615 RTE_PKTMBUF_HEADROOM);
2617 /* Check if scattered RX needs to be used. */
2618 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2619 dev_data->scattered_rx = 1;
2620 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2623 /* Init the RX tail regieter. */
2624 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2630 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2634 PMD_INIT_FUNC_TRACE();
2636 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2637 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2638 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2641 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2642 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2643 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2647 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2648 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2650 enum i40e_status_code
2651 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2653 struct i40e_tx_queue *txq;
2654 const struct rte_memzone *tz = NULL;
2656 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2659 PMD_DRV_LOG(ERR, "PF is not available");
2660 return I40E_ERR_BAD_PTR;
2663 /* Allocate the TX queue data structure. */
2664 txq = rte_zmalloc_socket("i40e fdir tx queue",
2665 sizeof(struct i40e_tx_queue),
2666 RTE_CACHE_LINE_SIZE,
2669 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2670 "tx queue structure.");
2671 return I40E_ERR_NO_MEMORY;
2674 /* Allocate TX hardware ring descriptors. */
2675 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2676 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2678 tz = i40e_ring_dma_zone_reserve(dev,
2684 i40e_dev_tx_queue_release(txq);
2685 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2686 return I40E_ERR_NO_MEMORY;
2689 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2690 txq->queue_id = I40E_FDIR_QUEUE_ID;
2691 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2692 txq->vsi = pf->fdir.fdir_vsi;
2694 #ifdef RTE_LIBRTE_XEN_DOM0
2695 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2697 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2699 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2701 * don't need to allocate software ring and reset for the fdir
2702 * program queue just set the queue has been configured.
2707 return I40E_SUCCESS;
2710 enum i40e_status_code
2711 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2713 struct i40e_rx_queue *rxq;
2714 const struct rte_memzone *rz = NULL;
2716 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2719 PMD_DRV_LOG(ERR, "PF is not available");
2720 return I40E_ERR_BAD_PTR;
2723 /* Allocate the RX queue data structure. */
2724 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2725 sizeof(struct i40e_rx_queue),
2726 RTE_CACHE_LINE_SIZE,
2729 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2730 "rx queue structure.");
2731 return I40E_ERR_NO_MEMORY;
2734 /* Allocate RX hardware ring descriptors. */
2735 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2736 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2738 rz = i40e_ring_dma_zone_reserve(dev,
2744 i40e_dev_rx_queue_release(rxq);
2745 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2746 return I40E_ERR_NO_MEMORY;
2749 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2750 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2751 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2752 rxq->vsi = pf->fdir.fdir_vsi;
2754 #ifdef RTE_LIBRTE_XEN_DOM0
2755 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2757 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2759 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2762 * Don't need to allocate software ring and reset for the fdir
2763 * rx queue, just set the queue has been configured.
2768 return I40E_SUCCESS;