4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_type.h"
59 #include "i40e_ethdev.h"
60 #include "i40e_rxtx.h"
62 #define DEFAULT_TX_RS_THRESH 32
63 #define DEFAULT_TX_FREE_THRESH 32
64 #define I40E_MAX_PKT_TYPE 256
66 #define I40E_TX_MAX_BURST 32
68 #define I40E_DMA_MEM_ALIGN 4096
70 /* Base address of the HW descriptor ring should be 128B aligned. */
71 #define I40E_RING_BASE_ALIGN 128
73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
74 ETH_TXQ_FLAGS_NOOFFLOADS)
76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
78 #ifdef RTE_LIBRTE_IEEE1588
79 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
81 #define I40E_TX_IEEE1588_TMST 0
84 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
88 PKT_TX_OUTER_IP_CKSUM)
90 #define I40E_TX_OFFLOAD_MASK ( \
93 PKT_TX_OUTER_IP_CKSUM | \
97 PKT_TX_TUNNEL_MASK | \
98 I40E_TX_IEEE1588_TMST)
100 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
101 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
103 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
104 struct rte_mbuf **tx_pkts,
108 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
110 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
111 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
112 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
114 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
115 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
116 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
120 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
121 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
122 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
123 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
124 mb->vlan_tci_outer = mb->vlan_tci;
125 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
126 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
127 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
128 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
130 mb->vlan_tci_outer = 0;
133 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
134 mb->vlan_tci, mb->vlan_tci_outer);
137 /* Translate the rx descriptor status to pkt flags */
138 static inline uint64_t
139 i40e_rxd_status_to_pkt_flags(uint64_t qword)
143 /* Check if RSS_HASH */
144 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
145 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
146 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
148 /* Check if FDIR Match */
149 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
155 static inline uint64_t
156 i40e_rxd_error_to_pkt_flags(uint64_t qword)
159 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
161 #define I40E_RX_ERR_BITS 0x3f
162 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
163 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
167 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
168 flags |= PKT_RX_IP_CKSUM_BAD;
170 flags |= PKT_RX_IP_CKSUM_GOOD;
172 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
173 flags |= PKT_RX_L4_CKSUM_BAD;
175 flags |= PKT_RX_L4_CKSUM_GOOD;
177 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
178 flags |= PKT_RX_EIP_CKSUM_BAD;
183 /* Function to check and set the ieee1588 timesync index and get the
186 #ifdef RTE_LIBRTE_IEEE1588
187 static inline uint64_t
188 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
190 uint64_t pkt_flags = 0;
191 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
192 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
193 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
195 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
196 == RTE_PTYPE_L2_ETHER_TIMESYNC)
197 pkt_flags = PKT_RX_IEEE1588_PTP;
199 pkt_flags |= PKT_RX_IEEE1588_TMST;
200 mb->timesync = tsyn & 0x03;
207 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
208 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
209 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
210 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
211 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
213 static inline uint64_t
214 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
217 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
218 uint16_t flexbh, flexbl;
220 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
221 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
222 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
223 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
224 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
225 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
228 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
230 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
231 flags |= PKT_RX_FDIR_ID;
232 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
234 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
235 flags |= PKT_RX_FDIR_FLX;
237 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
239 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
240 flags |= PKT_RX_FDIR_FLX;
244 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
245 flags |= PKT_RX_FDIR_ID;
251 i40e_parse_tunneling_params(uint64_t ol_flags,
252 union i40e_tx_offload tx_offload,
253 uint32_t *cd_tunneling)
255 /* EIPT: External (outer) IP header type */
256 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
257 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
258 else if (ol_flags & PKT_TX_OUTER_IPV4)
259 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
260 else if (ol_flags & PKT_TX_OUTER_IPV6)
261 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
263 /* EIPLEN: External (outer) IP header length, in DWords */
264 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
265 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
267 /* L4TUNT: L4 Tunneling Type */
268 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
269 case PKT_TX_TUNNEL_IPIP:
270 /* for non UDP / GRE tunneling, set to 00b */
272 case PKT_TX_TUNNEL_VXLAN:
273 case PKT_TX_TUNNEL_GENEVE:
274 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
276 case PKT_TX_TUNNEL_GRE:
277 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
280 PMD_TX_LOG(ERR, "Tunnel type not supported");
284 /* L4TUNLEN: L4 Tunneling Length, in Words
286 * We depend on app to set rte_mbuf.l2_len correctly.
287 * For IP in GRE it should be set to the length of the GRE
289 * for MAC in GRE or MAC in UDP it should be set to the length
290 * of the GRE or UDP headers plus the inner MAC up to including
291 * its last Ethertype.
293 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
294 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
298 i40e_txd_enable_checksum(uint64_t ol_flags,
301 union i40e_tx_offload tx_offload)
304 if (ol_flags & PKT_TX_TUNNEL_MASK)
305 *td_offset |= (tx_offload.outer_l2_len >> 1)
306 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
308 *td_offset |= (tx_offload.l2_len >> 1)
309 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
311 /* Enable L3 checksum offloads */
312 if (ol_flags & PKT_TX_IP_CKSUM) {
313 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
314 *td_offset |= (tx_offload.l3_len >> 2)
315 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
316 } else if (ol_flags & PKT_TX_IPV4) {
317 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
318 *td_offset |= (tx_offload.l3_len >> 2)
319 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
320 } else if (ol_flags & PKT_TX_IPV6) {
321 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
322 *td_offset |= (tx_offload.l3_len >> 2)
323 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
326 if (ol_flags & PKT_TX_TCP_SEG) {
327 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
328 *td_offset |= (tx_offload.l4_len >> 2)
329 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
333 /* Enable L4 checksum offloads */
334 switch (ol_flags & PKT_TX_L4_MASK) {
335 case PKT_TX_TCP_CKSUM:
336 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
337 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
338 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
340 case PKT_TX_SCTP_CKSUM:
341 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
342 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
343 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
345 case PKT_TX_UDP_CKSUM:
346 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
347 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
348 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
355 /* Construct the tx flags */
356 static inline uint64_t
357 i40e_build_ctob(uint32_t td_cmd,
362 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
363 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
364 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
365 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
366 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
370 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
372 struct i40e_tx_entry *sw_ring = txq->sw_ring;
373 volatile struct i40e_tx_desc *txd = txq->tx_ring;
374 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
375 uint16_t nb_tx_desc = txq->nb_tx_desc;
376 uint16_t desc_to_clean_to;
377 uint16_t nb_tx_to_clean;
379 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
380 if (desc_to_clean_to >= nb_tx_desc)
381 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
383 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
384 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
385 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
386 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
387 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
388 "(port=%d queue=%d)", desc_to_clean_to,
389 txq->port_id, txq->queue_id);
393 if (last_desc_cleaned > desc_to_clean_to)
394 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
397 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
400 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
402 txq->last_desc_cleaned = desc_to_clean_to;
403 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
409 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
410 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
412 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
417 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
418 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
419 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
420 "rxq->rx_free_thresh=%d, "
421 "RTE_PMD_I40E_RX_MAX_BURST=%d",
422 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
424 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
425 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
426 "rxq->rx_free_thresh=%d, "
427 "rxq->nb_rx_desc=%d",
428 rxq->rx_free_thresh, rxq->nb_rx_desc);
430 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
431 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
432 "rxq->nb_rx_desc=%d, "
433 "rxq->rx_free_thresh=%d",
434 rxq->nb_rx_desc, rxq->rx_free_thresh);
444 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
445 #define I40E_LOOK_AHEAD 8
446 #if (I40E_LOOK_AHEAD != 8)
447 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
450 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
452 volatile union i40e_rx_desc *rxdp;
453 struct i40e_rx_entry *rxep;
458 int32_t s[I40E_LOOK_AHEAD], nb_dd;
459 int32_t i, j, nb_rx = 0;
462 rxdp = &rxq->rx_ring[rxq->rx_tail];
463 rxep = &rxq->sw_ring[rxq->rx_tail];
465 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
466 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
467 I40E_RXD_QW1_STATUS_SHIFT;
469 /* Make sure there is at least 1 packet to receive */
470 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
474 * Scan LOOK_AHEAD descriptors at a time to determine which
475 * descriptors reference packets that are ready to be received.
477 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
478 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
479 /* Read desc statuses backwards to avoid race condition */
480 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
481 qword1 = rte_le_to_cpu_64(\
482 rxdp[j].wb.qword1.status_error_len);
483 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
484 I40E_RXD_QW1_STATUS_SHIFT;
489 /* Compute how many status bits were set */
490 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
491 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
495 /* Translate descriptor info to mbuf parameters */
496 for (j = 0; j < nb_dd; j++) {
498 qword1 = rte_le_to_cpu_64(\
499 rxdp[j].wb.qword1.status_error_len);
500 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
501 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
502 mb->data_len = pkt_len;
503 mb->pkt_len = pkt_len;
505 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
506 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
507 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
509 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
510 I40E_RXD_QW1_PTYPE_MASK) >>
511 I40E_RXD_QW1_PTYPE_SHIFT));
512 if (pkt_flags & PKT_RX_RSS_HASH)
513 mb->hash.rss = rte_le_to_cpu_32(\
514 rxdp[j].wb.qword0.hi_dword.rss);
515 if (pkt_flags & PKT_RX_FDIR)
516 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
518 #ifdef RTE_LIBRTE_IEEE1588
519 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
521 mb->ol_flags |= pkt_flags;
525 for (j = 0; j < I40E_LOOK_AHEAD; j++)
526 rxq->rx_stage[i + j] = rxep[j].mbuf;
528 if (nb_dd != I40E_LOOK_AHEAD)
532 /* Clear software ring entries */
533 for (i = 0; i < nb_rx; i++)
534 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
539 static inline uint16_t
540 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
541 struct rte_mbuf **rx_pkts,
545 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
547 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
549 for (i = 0; i < nb_pkts; i++)
550 rx_pkts[i] = stage[i];
552 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
553 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
559 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
561 volatile union i40e_rx_desc *rxdp;
562 struct i40e_rx_entry *rxep;
564 uint16_t alloc_idx, i;
568 /* Allocate buffers in bulk */
569 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
570 (rxq->rx_free_thresh - 1));
571 rxep = &(rxq->sw_ring[alloc_idx]);
572 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
573 rxq->rx_free_thresh);
574 if (unlikely(diag != 0)) {
575 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
579 rxdp = &rxq->rx_ring[alloc_idx];
580 for (i = 0; i < rxq->rx_free_thresh; i++) {
581 if (likely(i < (rxq->rx_free_thresh - 1)))
582 /* Prefetch next mbuf */
583 rte_prefetch0(rxep[i + 1].mbuf);
586 rte_mbuf_refcnt_set(mb, 1);
588 mb->data_off = RTE_PKTMBUF_HEADROOM;
590 mb->port = rxq->port_id;
591 dma_addr = rte_cpu_to_le_64(\
592 rte_mbuf_data_dma_addr_default(mb));
593 rxdp[i].read.hdr_addr = 0;
594 rxdp[i].read.pkt_addr = dma_addr;
597 /* Update rx tail regsiter */
599 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
601 rxq->rx_free_trigger =
602 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
603 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
604 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
609 static inline uint16_t
610 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
612 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
618 if (rxq->rx_nb_avail)
619 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
621 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
622 rxq->rx_next_avail = 0;
623 rxq->rx_nb_avail = nb_rx;
624 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
626 if (rxq->rx_tail > rxq->rx_free_trigger) {
627 if (i40e_rx_alloc_bufs(rxq) != 0) {
630 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
631 "port_id=%u, queue_id=%u",
632 rxq->port_id, rxq->queue_id);
633 rxq->rx_nb_avail = 0;
634 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
635 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
636 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
642 if (rxq->rx_tail >= rxq->nb_rx_desc)
645 if (rxq->rx_nb_avail)
646 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
652 i40e_recv_pkts_bulk_alloc(void *rx_queue,
653 struct rte_mbuf **rx_pkts,
656 uint16_t nb_rx = 0, n, count;
658 if (unlikely(nb_pkts == 0))
661 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
662 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
665 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
666 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
667 nb_rx = (uint16_t)(nb_rx + count);
668 nb_pkts = (uint16_t)(nb_pkts - count);
677 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
678 struct rte_mbuf __rte_unused **rx_pkts,
679 uint16_t __rte_unused nb_pkts)
683 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
686 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
688 struct i40e_rx_queue *rxq;
689 volatile union i40e_rx_desc *rx_ring;
690 volatile union i40e_rx_desc *rxdp;
691 union i40e_rx_desc rxd;
692 struct i40e_rx_entry *sw_ring;
693 struct i40e_rx_entry *rxe;
694 struct rte_mbuf *rxm;
695 struct rte_mbuf *nmb;
699 uint16_t rx_packet_len;
700 uint16_t rx_id, nb_hold;
707 rx_id = rxq->rx_tail;
708 rx_ring = rxq->rx_ring;
709 sw_ring = rxq->sw_ring;
711 while (nb_rx < nb_pkts) {
712 rxdp = &rx_ring[rx_id];
713 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
714 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
715 >> I40E_RXD_QW1_STATUS_SHIFT;
717 /* Check the DD bit first */
718 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
721 nmb = rte_mbuf_raw_alloc(rxq->mp);
727 rxe = &sw_ring[rx_id];
729 if (unlikely(rx_id == rxq->nb_rx_desc))
732 /* Prefetch next mbuf */
733 rte_prefetch0(sw_ring[rx_id].mbuf);
736 * When next RX descriptor is on a cache line boundary,
737 * prefetch the next 4 RX descriptors and next 8 pointers
740 if ((rx_id & 0x3) == 0) {
741 rte_prefetch0(&rx_ring[rx_id]);
742 rte_prefetch0(&sw_ring[rx_id]);
747 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
748 rxdp->read.hdr_addr = 0;
749 rxdp->read.pkt_addr = dma_addr;
751 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
752 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
754 rxm->data_off = RTE_PKTMBUF_HEADROOM;
755 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
758 rxm->pkt_len = rx_packet_len;
759 rxm->data_len = rx_packet_len;
760 rxm->port = rxq->port_id;
762 i40e_rxd_to_vlan_tci(rxm, &rxd);
763 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
764 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
766 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
767 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
768 if (pkt_flags & PKT_RX_RSS_HASH)
770 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
771 if (pkt_flags & PKT_RX_FDIR)
772 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
774 #ifdef RTE_LIBRTE_IEEE1588
775 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
777 rxm->ol_flags |= pkt_flags;
779 rx_pkts[nb_rx++] = rxm;
781 rxq->rx_tail = rx_id;
784 * If the number of free RX descriptors is greater than the RX free
785 * threshold of the queue, advance the receive tail register of queue.
786 * Update that register with the value of the last processed RX
787 * descriptor minus 1.
789 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
790 if (nb_hold > rxq->rx_free_thresh) {
791 rx_id = (uint16_t) ((rx_id == 0) ?
792 (rxq->nb_rx_desc - 1) : (rx_id - 1));
793 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
796 rxq->nb_rx_hold = nb_hold;
802 i40e_recv_scattered_pkts(void *rx_queue,
803 struct rte_mbuf **rx_pkts,
806 struct i40e_rx_queue *rxq = rx_queue;
807 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
808 volatile union i40e_rx_desc *rxdp;
809 union i40e_rx_desc rxd;
810 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
811 struct i40e_rx_entry *rxe;
812 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
813 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
814 struct rte_mbuf *nmb, *rxm;
815 uint16_t rx_id = rxq->rx_tail;
816 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
822 while (nb_rx < nb_pkts) {
823 rxdp = &rx_ring[rx_id];
824 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
825 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
826 I40E_RXD_QW1_STATUS_SHIFT;
828 /* Check the DD bit */
829 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
832 nmb = rte_mbuf_raw_alloc(rxq->mp);
837 rxe = &sw_ring[rx_id];
839 if (rx_id == rxq->nb_rx_desc)
842 /* Prefetch next mbuf */
843 rte_prefetch0(sw_ring[rx_id].mbuf);
846 * When next RX descriptor is on a cache line boundary,
847 * prefetch the next 4 RX descriptors and next 8 pointers
850 if ((rx_id & 0x3) == 0) {
851 rte_prefetch0(&rx_ring[rx_id]);
852 rte_prefetch0(&sw_ring[rx_id]);
858 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
860 /* Set data buffer address and data length of the mbuf */
861 rxdp->read.hdr_addr = 0;
862 rxdp->read.pkt_addr = dma_addr;
863 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
864 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
865 rxm->data_len = rx_packet_len;
866 rxm->data_off = RTE_PKTMBUF_HEADROOM;
869 * If this is the first buffer of the received packet, set the
870 * pointer to the first mbuf of the packet and initialize its
871 * context. Otherwise, update the total length and the number
872 * of segments of the current scattered packet, and update the
873 * pointer to the last mbuf of the current packet.
877 first_seg->nb_segs = 1;
878 first_seg->pkt_len = rx_packet_len;
881 (uint16_t)(first_seg->pkt_len +
883 first_seg->nb_segs++;
884 last_seg->next = rxm;
888 * If this is not the last buffer of the received packet,
889 * update the pointer to the last mbuf of the current scattered
890 * packet and continue to parse the RX ring.
892 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
898 * This is the last buffer of the received packet. If the CRC
899 * is not stripped by the hardware:
900 * - Subtract the CRC length from the total packet length.
901 * - If the last buffer only contains the whole CRC or a part
902 * of it, free the mbuf associated to the last buffer. If part
903 * of the CRC is also contained in the previous mbuf, subtract
904 * the length of that CRC part from the data length of the
908 if (unlikely(rxq->crc_len > 0)) {
909 first_seg->pkt_len -= ETHER_CRC_LEN;
910 if (rx_packet_len <= ETHER_CRC_LEN) {
911 rte_pktmbuf_free_seg(rxm);
912 first_seg->nb_segs--;
914 (uint16_t)(last_seg->data_len -
915 (ETHER_CRC_LEN - rx_packet_len));
916 last_seg->next = NULL;
918 rxm->data_len = (uint16_t)(rx_packet_len -
922 first_seg->port = rxq->port_id;
923 first_seg->ol_flags = 0;
924 i40e_rxd_to_vlan_tci(first_seg, &rxd);
925 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
926 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
927 first_seg->packet_type =
928 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
929 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
930 if (pkt_flags & PKT_RX_RSS_HASH)
931 first_seg->hash.rss =
932 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
933 if (pkt_flags & PKT_RX_FDIR)
934 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
936 #ifdef RTE_LIBRTE_IEEE1588
937 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
939 first_seg->ol_flags |= pkt_flags;
941 /* Prefetch data of first segment, if configured to do so. */
942 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
943 first_seg->data_off));
944 rx_pkts[nb_rx++] = first_seg;
948 /* Record index of the next RX descriptor to probe. */
949 rxq->rx_tail = rx_id;
950 rxq->pkt_first_seg = first_seg;
951 rxq->pkt_last_seg = last_seg;
954 * If the number of free RX descriptors is greater than the RX free
955 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
956 * register. Update the RDT with the value of the last processed RX
957 * descriptor minus 1, to guarantee that the RDT register is never
958 * equal to the RDH register, which creates a "full" ring situtation
959 * from the hardware point of view.
961 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
962 if (nb_hold > rxq->rx_free_thresh) {
963 rx_id = (uint16_t)(rx_id == 0 ?
964 (rxq->nb_rx_desc - 1) : (rx_id - 1));
965 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
968 rxq->nb_rx_hold = nb_hold;
973 /* Check if the context descriptor is needed for TX offloading */
974 static inline uint16_t
975 i40e_calc_context_desc(uint64_t flags)
977 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
982 #ifdef RTE_LIBRTE_IEEE1588
983 mask |= PKT_TX_IEEE1588_TMST;
986 return (flags & mask) ? 1 : 0;
989 /* set i40e TSO context descriptor */
990 static inline uint64_t
991 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
993 uint64_t ctx_desc = 0;
994 uint32_t cd_cmd, hdr_len, cd_tso_len;
996 if (!tx_offload.l4_len) {
997 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1002 * in case of non tunneling packet, the outer_l2_len and
1003 * outer_l3_len must be 0.
1005 hdr_len = tx_offload.outer_l2_len +
1006 tx_offload.outer_l3_len +
1011 cd_cmd = I40E_TX_CTX_DESC_TSO;
1012 cd_tso_len = mbuf->pkt_len - hdr_len;
1013 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1014 ((uint64_t)cd_tso_len <<
1015 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1016 ((uint64_t)mbuf->tso_segsz <<
1017 I40E_TXD_CTX_QW1_MSS_SHIFT);
1023 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1025 struct i40e_tx_queue *txq;
1026 struct i40e_tx_entry *sw_ring;
1027 struct i40e_tx_entry *txe, *txn;
1028 volatile struct i40e_tx_desc *txd;
1029 volatile struct i40e_tx_desc *txr;
1030 struct rte_mbuf *tx_pkt;
1031 struct rte_mbuf *m_seg;
1032 uint32_t cd_tunneling_params;
1043 uint64_t buf_dma_addr;
1044 union i40e_tx_offload tx_offload = {0};
1047 sw_ring = txq->sw_ring;
1049 tx_id = txq->tx_tail;
1050 txe = &sw_ring[tx_id];
1052 /* Check if the descriptor ring needs to be cleaned. */
1053 if (txq->nb_tx_free < txq->tx_free_thresh)
1054 i40e_xmit_cleanup(txq);
1056 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1061 tx_pkt = *tx_pkts++;
1062 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1064 ol_flags = tx_pkt->ol_flags;
1065 tx_offload.l2_len = tx_pkt->l2_len;
1066 tx_offload.l3_len = tx_pkt->l3_len;
1067 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1068 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1069 tx_offload.l4_len = tx_pkt->l4_len;
1070 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1072 /* Calculate the number of context descriptors needed. */
1073 nb_ctx = i40e_calc_context_desc(ol_flags);
1076 * The number of descriptors that must be allocated for
1077 * a packet equals to the number of the segments of that
1078 * packet plus 1 context descriptor if needed.
1080 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1081 tx_last = (uint16_t)(tx_id + nb_used - 1);
1084 if (tx_last >= txq->nb_tx_desc)
1085 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1087 if (nb_used > txq->nb_tx_free) {
1088 if (i40e_xmit_cleanup(txq) != 0) {
1093 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1094 while (nb_used > txq->nb_tx_free) {
1095 if (i40e_xmit_cleanup(txq) != 0) {
1104 /* Descriptor based VLAN insertion */
1105 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1106 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1107 td_tag = tx_pkt->vlan_tci;
1110 /* Always enable CRC offload insertion */
1111 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1113 /* Fill in tunneling parameters if necessary */
1114 cd_tunneling_params = 0;
1115 if (ol_flags & PKT_TX_TUNNEL_MASK)
1116 i40e_parse_tunneling_params(ol_flags, tx_offload,
1117 &cd_tunneling_params);
1118 /* Enable checksum offloading */
1119 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1120 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1121 &td_offset, tx_offload);
1124 /* Setup TX context descriptor if required */
1125 volatile struct i40e_tx_context_desc *ctx_txd =
1126 (volatile struct i40e_tx_context_desc *)\
1128 uint16_t cd_l2tag2 = 0;
1129 uint64_t cd_type_cmd_tso_mss =
1130 I40E_TX_DESC_DTYPE_CONTEXT;
1132 txn = &sw_ring[txe->next_id];
1133 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1134 if (txe->mbuf != NULL) {
1135 rte_pktmbuf_free_seg(txe->mbuf);
1139 /* TSO enabled means no timestamp */
1140 if (ol_flags & PKT_TX_TCP_SEG)
1141 cd_type_cmd_tso_mss |=
1142 i40e_set_tso_ctx(tx_pkt, tx_offload);
1144 #ifdef RTE_LIBRTE_IEEE1588
1145 if (ol_flags & PKT_TX_IEEE1588_TMST)
1146 cd_type_cmd_tso_mss |=
1147 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1148 I40E_TXD_CTX_QW1_CMD_SHIFT);
1152 ctx_txd->tunneling_params =
1153 rte_cpu_to_le_32(cd_tunneling_params);
1154 if (ol_flags & PKT_TX_QINQ_PKT) {
1155 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1156 cd_type_cmd_tso_mss |=
1157 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1158 I40E_TXD_CTX_QW1_CMD_SHIFT);
1160 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1161 ctx_txd->type_cmd_tso_mss =
1162 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1164 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1165 "tunneling_params: %#x;\n"
1168 "type_cmd_tso_mss: %#"PRIx64";\n",
1170 ctx_txd->tunneling_params,
1173 ctx_txd->type_cmd_tso_mss);
1175 txe->last_id = tx_last;
1176 tx_id = txe->next_id;
1183 txn = &sw_ring[txe->next_id];
1186 rte_pktmbuf_free_seg(txe->mbuf);
1189 /* Setup TX Descriptor */
1190 slen = m_seg->data_len;
1191 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1193 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1194 "buf_dma_addr: %#"PRIx64";\n"
1199 tx_pkt, tx_id, buf_dma_addr,
1200 td_cmd, td_offset, slen, td_tag);
1202 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1203 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1204 td_offset, slen, td_tag);
1205 txe->last_id = tx_last;
1206 tx_id = txe->next_id;
1208 m_seg = m_seg->next;
1209 } while (m_seg != NULL);
1211 /* The last packet data descriptor needs End Of Packet (EOP) */
1212 td_cmd |= I40E_TX_DESC_CMD_EOP;
1213 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1214 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1216 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1217 PMD_TX_FREE_LOG(DEBUG,
1218 "Setting RS bit on TXD id="
1219 "%4u (port=%d queue=%d)",
1220 tx_last, txq->port_id, txq->queue_id);
1222 td_cmd |= I40E_TX_DESC_CMD_RS;
1224 /* Update txq RS bit counters */
1225 txq->nb_tx_used = 0;
1228 txd->cmd_type_offset_bsz |=
1229 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1230 I40E_TXD_QW1_CMD_SHIFT);
1236 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1237 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1238 (unsigned) tx_id, (unsigned) nb_tx);
1240 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1241 txq->tx_tail = tx_id;
1246 static inline int __attribute__((always_inline))
1247 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1249 struct i40e_tx_entry *txep;
1252 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1253 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1254 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1257 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1259 for (i = 0; i < txq->tx_rs_thresh; i++)
1260 rte_prefetch0((txep + i)->mbuf);
1262 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1263 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1264 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1268 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1269 rte_pktmbuf_free_seg(txep->mbuf);
1274 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1275 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1276 if (txq->tx_next_dd >= txq->nb_tx_desc)
1277 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1279 return txq->tx_rs_thresh;
1282 /* Populate 4 descriptors with data from 4 mbufs */
1284 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1289 for (i = 0; i < 4; i++, txdp++, pkts++) {
1290 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1291 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1292 txdp->cmd_type_offset_bsz =
1293 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1294 (*pkts)->data_len, 0);
1298 /* Populate 1 descriptor with data from 1 mbuf */
1300 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1304 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1305 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1306 txdp->cmd_type_offset_bsz =
1307 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1308 (*pkts)->data_len, 0);
1311 /* Fill hardware descriptor ring with mbuf data */
1313 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1314 struct rte_mbuf **pkts,
1317 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1318 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1319 const int N_PER_LOOP = 4;
1320 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1321 int mainpart, leftover;
1324 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1325 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1326 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1327 for (j = 0; j < N_PER_LOOP; ++j) {
1328 (txep + i + j)->mbuf = *(pkts + i + j);
1330 tx4(txdp + i, pkts + i);
1332 if (unlikely(leftover > 0)) {
1333 for (i = 0; i < leftover; ++i) {
1334 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1335 tx1(txdp + mainpart + i, pkts + mainpart + i);
1340 static inline uint16_t
1341 tx_xmit_pkts(struct i40e_tx_queue *txq,
1342 struct rte_mbuf **tx_pkts,
1345 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1349 * Begin scanning the H/W ring for done descriptors when the number
1350 * of available descriptors drops below tx_free_thresh. For each done
1351 * descriptor, free the associated buffer.
1353 if (txq->nb_tx_free < txq->tx_free_thresh)
1354 i40e_tx_free_bufs(txq);
1356 /* Use available descriptor only */
1357 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1358 if (unlikely(!nb_pkts))
1361 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1362 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1363 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1364 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1365 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1366 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1367 I40E_TXD_QW1_CMD_SHIFT);
1368 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1372 /* Fill hardware descriptor ring with mbuf data */
1373 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1374 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1376 /* Determin if RS bit needs to be set */
1377 if (txq->tx_tail > txq->tx_next_rs) {
1378 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1379 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1380 I40E_TXD_QW1_CMD_SHIFT);
1382 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1383 if (txq->tx_next_rs >= txq->nb_tx_desc)
1384 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1387 if (txq->tx_tail >= txq->nb_tx_desc)
1390 /* Update the tx tail register */
1392 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1398 i40e_xmit_pkts_simple(void *tx_queue,
1399 struct rte_mbuf **tx_pkts,
1404 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1405 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1409 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1412 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1413 &tx_pkts[nb_tx], num);
1414 nb_tx = (uint16_t)(nb_tx + ret);
1415 nb_pkts = (uint16_t)(nb_pkts - ret);
1423 /*********************************************************************
1427 **********************************************************************/
1429 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1436 for (i = 0; i < nb_pkts; i++) {
1438 ol_flags = m->ol_flags;
1441 * m->nb_segs is uint8_t, so nb_segs is always less than
1443 * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1445 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1446 if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1447 rte_errno = -EINVAL;
1450 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1451 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1452 /* MSS outside the range (256B - 9674B) are considered
1455 rte_errno = -EINVAL;
1459 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1460 rte_errno = -ENOTSUP;
1464 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1465 ret = rte_validate_tx_offload(m);
1471 ret = rte_net_intel_cksum_prepare(m);
1481 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1482 * application used, which assume having sequential ones. But from driver's
1483 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1484 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1485 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1486 * use queue_idx from 0 to 95 to access queues, while real queue would be
1487 * different. This function will do a queue mapping to find VSI the queue
1490 static struct i40e_vsi*
1491 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1493 /* the queue in MAIN VSI range */
1494 if (queue_idx < pf->main_vsi->nb_qps)
1495 return pf->main_vsi;
1497 queue_idx -= pf->main_vsi->nb_qps;
1499 /* queue_idx is greater than VMDQ VSIs range */
1500 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1501 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1505 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1509 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1511 /* the queue in MAIN VSI range */
1512 if (queue_idx < pf->main_vsi->nb_qps)
1515 /* It's VMDQ queues */
1516 queue_idx -= pf->main_vsi->nb_qps;
1518 if (pf->nb_cfg_vmdq_vsi)
1519 return queue_idx % pf->vmdq_nb_qps;
1521 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1522 return (uint16_t)(-1);
1527 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1529 struct i40e_rx_queue *rxq;
1531 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533 PMD_INIT_FUNC_TRACE();
1535 if (rx_queue_id < dev->data->nb_rx_queues) {
1536 rxq = dev->data->rx_queues[rx_queue_id];
1538 err = i40e_alloc_rx_queue_mbufs(rxq);
1540 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1546 /* Init the RX tail regieter. */
1547 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1549 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1552 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1555 i40e_rx_queue_release_mbufs(rxq);
1556 i40e_reset_rx_queue(rxq);
1558 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1565 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1567 struct i40e_rx_queue *rxq;
1569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571 if (rx_queue_id < dev->data->nb_rx_queues) {
1572 rxq = dev->data->rx_queues[rx_queue_id];
1575 * rx_queue_id is queue id aplication refers to, while
1576 * rxq->reg_idx is the real queue index.
1578 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1581 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1585 i40e_rx_queue_release_mbufs(rxq);
1586 i40e_reset_rx_queue(rxq);
1587 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1594 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1597 struct i40e_tx_queue *txq;
1598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 if (tx_queue_id < dev->data->nb_tx_queues) {
1603 txq = dev->data->tx_queues[tx_queue_id];
1606 * tx_queue_id is queue id aplication refers to, while
1607 * rxq->reg_idx is the real queue index.
1609 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1611 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1614 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1621 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1623 struct i40e_tx_queue *txq;
1625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627 if (tx_queue_id < dev->data->nb_tx_queues) {
1628 txq = dev->data->tx_queues[tx_queue_id];
1631 * tx_queue_id is queue id aplication refers to, while
1632 * txq->reg_idx is the real queue index.
1634 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1637 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1642 i40e_tx_queue_release_mbufs(txq);
1643 i40e_reset_tx_queue(txq);
1644 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1651 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1653 static const uint32_t ptypes[] = {
1654 /* refers to i40e_rxd_pkt_type_mapping() */
1656 RTE_PTYPE_L2_ETHER_TIMESYNC,
1657 RTE_PTYPE_L2_ETHER_LLDP,
1658 RTE_PTYPE_L2_ETHER_ARP,
1659 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1660 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1663 RTE_PTYPE_L4_NONFRAG,
1667 RTE_PTYPE_TUNNEL_GRENAT,
1668 RTE_PTYPE_TUNNEL_IP,
1669 RTE_PTYPE_INNER_L2_ETHER,
1670 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1671 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1672 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1673 RTE_PTYPE_INNER_L4_FRAG,
1674 RTE_PTYPE_INNER_L4_ICMP,
1675 RTE_PTYPE_INNER_L4_NONFRAG,
1676 RTE_PTYPE_INNER_L4_SCTP,
1677 RTE_PTYPE_INNER_L4_TCP,
1678 RTE_PTYPE_INNER_L4_UDP,
1682 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1683 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1684 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1686 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1687 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1688 dev->rx_pkt_burst == i40e_recv_pkts_vec)
1694 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1697 unsigned int socket_id,
1698 const struct rte_eth_rxconf *rx_conf,
1699 struct rte_mempool *mp)
1701 struct i40e_vsi *vsi;
1702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1704 struct i40e_adapter *ad =
1705 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1706 struct i40e_rx_queue *rxq;
1707 const struct rte_memzone *rz;
1710 uint16_t base, bsf, tc_mapping;
1711 int use_def_burst_func = 1;
1713 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1714 struct i40e_vf *vf =
1715 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1718 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1721 PMD_DRV_LOG(ERR, "VSI not available or queue "
1722 "index exceeds the maximum");
1723 return I40E_ERR_PARAM;
1725 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1726 (nb_desc > I40E_MAX_RING_DESC) ||
1727 (nb_desc < I40E_MIN_RING_DESC)) {
1728 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1729 "invalid", nb_desc);
1730 return I40E_ERR_PARAM;
1733 /* Free memory if needed */
1734 if (dev->data->rx_queues[queue_idx]) {
1735 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1736 dev->data->rx_queues[queue_idx] = NULL;
1739 /* Allocate the rx queue data structure */
1740 rxq = rte_zmalloc_socket("i40e rx queue",
1741 sizeof(struct i40e_rx_queue),
1742 RTE_CACHE_LINE_SIZE,
1745 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1746 "rx queue data structure");
1750 rxq->nb_rx_desc = nb_desc;
1751 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1752 rxq->queue_id = queue_idx;
1753 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1754 rxq->reg_idx = queue_idx;
1755 else /* PF device */
1756 rxq->reg_idx = vsi->base_queue +
1757 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1759 rxq->port_id = dev->data->port_id;
1760 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1762 rxq->drop_en = rx_conf->rx_drop_en;
1764 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1766 /* Allocate the maximun number of RX ring hardware descriptor. */
1767 len = I40E_MAX_RING_DESC;
1769 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1771 * Allocating a little more memory because vectorized/bulk_alloc Rx
1772 * functions doesn't check boundaries each time.
1774 len += RTE_PMD_I40E_RX_MAX_BURST;
1777 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1778 I40E_DMA_MEM_ALIGN);
1780 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1781 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1783 i40e_dev_rx_queue_release(rxq);
1784 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1788 /* Zero all the descriptors in the ring. */
1789 memset(rz->addr, 0, ring_size);
1791 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1792 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1794 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1795 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1800 /* Allocate the software ring. */
1802 rte_zmalloc_socket("i40e rx sw ring",
1803 sizeof(struct i40e_rx_entry) * len,
1804 RTE_CACHE_LINE_SIZE,
1806 if (!rxq->sw_ring) {
1807 i40e_dev_rx_queue_release(rxq);
1808 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1812 i40e_reset_rx_queue(rxq);
1814 dev->data->rx_queues[queue_idx] = rxq;
1816 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1818 if (!use_def_burst_func) {
1819 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1820 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1821 "satisfied. Rx Burst Bulk Alloc function will be "
1822 "used on port=%d, queue=%d.",
1823 rxq->port_id, rxq->queue_id);
1824 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1826 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1827 "not satisfied, Scattered Rx is requested, "
1828 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1829 "not enabled on port=%d, queue=%d.",
1830 rxq->port_id, rxq->queue_id);
1831 ad->rx_bulk_alloc_allowed = false;
1834 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1835 if (!(vsi->enabled_tc & (1 << i)))
1837 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1838 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1839 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1840 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1841 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1843 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1851 i40e_dev_rx_queue_release(void *rxq)
1853 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1856 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1860 i40e_rx_queue_release_mbufs(q);
1861 rte_free(q->sw_ring);
1866 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1868 #define I40E_RXQ_SCAN_INTERVAL 4
1869 volatile union i40e_rx_desc *rxdp;
1870 struct i40e_rx_queue *rxq;
1873 rxq = dev->data->rx_queues[rx_queue_id];
1874 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1875 while ((desc < rxq->nb_rx_desc) &&
1876 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1877 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1878 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1880 * Check the DD bit of a rx descriptor of each 4 in a group,
1881 * to avoid checking too frequently and downgrading performance
1884 desc += I40E_RXQ_SCAN_INTERVAL;
1885 rxdp += I40E_RXQ_SCAN_INTERVAL;
1886 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1887 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1888 desc - rxq->nb_rx_desc]);
1895 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1897 volatile union i40e_rx_desc *rxdp;
1898 struct i40e_rx_queue *rxq = rx_queue;
1902 if (unlikely(offset >= rxq->nb_rx_desc)) {
1903 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1907 desc = rxq->rx_tail + offset;
1908 if (desc >= rxq->nb_rx_desc)
1909 desc -= rxq->nb_rx_desc;
1911 rxdp = &(rxq->rx_ring[desc]);
1913 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1914 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1915 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1921 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1923 struct i40e_rx_queue *rxq = rx_queue;
1924 volatile uint64_t *status;
1928 if (unlikely(offset >= rxq->nb_rx_desc))
1931 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1932 return RTE_ETH_RX_DESC_UNAVAIL;
1934 desc = rxq->rx_tail + offset;
1935 if (desc >= rxq->nb_rx_desc)
1936 desc -= rxq->nb_rx_desc;
1938 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1939 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1940 << I40E_RXD_QW1_STATUS_SHIFT);
1942 return RTE_ETH_RX_DESC_DONE;
1944 return RTE_ETH_RX_DESC_AVAIL;
1948 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1950 struct i40e_tx_queue *txq = tx_queue;
1951 volatile uint64_t *status;
1952 uint64_t mask, expect;
1955 if (unlikely(offset >= txq->nb_tx_desc))
1958 desc = txq->tx_tail + offset;
1959 /* go to next desc that has the RS bit */
1960 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1962 if (desc >= txq->nb_tx_desc) {
1963 desc -= txq->nb_tx_desc;
1964 if (desc >= txq->nb_tx_desc)
1965 desc -= txq->nb_tx_desc;
1968 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1969 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
1970 expect = rte_cpu_to_le_64(
1971 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
1972 if ((*status & mask) == expect)
1973 return RTE_ETH_TX_DESC_DONE;
1975 return RTE_ETH_TX_DESC_FULL;
1979 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1982 unsigned int socket_id,
1983 const struct rte_eth_txconf *tx_conf)
1985 struct i40e_vsi *vsi;
1986 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1988 struct i40e_tx_queue *txq;
1989 const struct rte_memzone *tz;
1991 uint16_t tx_rs_thresh, tx_free_thresh;
1992 uint16_t i, base, bsf, tc_mapping;
1994 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1995 struct i40e_vf *vf =
1996 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1999 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2002 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2003 "exceeds the maximum", queue_idx);
2004 return I40E_ERR_PARAM;
2007 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2008 (nb_desc > I40E_MAX_RING_DESC) ||
2009 (nb_desc < I40E_MIN_RING_DESC)) {
2010 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2011 "invalid", nb_desc);
2012 return I40E_ERR_PARAM;
2016 * The following two parameters control the setting of the RS bit on
2017 * transmit descriptors. TX descriptors will have their RS bit set
2018 * after txq->tx_rs_thresh descriptors have been used. The TX
2019 * descriptor ring will be cleaned after txq->tx_free_thresh
2020 * descriptors are used or if the number of descriptors required to
2021 * transmit a packet is greater than the number of free TX descriptors.
2023 * The following constraints must be satisfied:
2024 * - tx_rs_thresh must be greater than 0.
2025 * - tx_rs_thresh must be less than the size of the ring minus 2.
2026 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2027 * - tx_rs_thresh must be a divisor of the ring size.
2028 * - tx_free_thresh must be greater than 0.
2029 * - tx_free_thresh must be less than the size of the ring minus 3.
2031 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2032 * race condition, hence the maximum threshold constraints. When set
2033 * to zero use default values.
2035 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2036 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2037 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2038 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2039 if (tx_rs_thresh >= (nb_desc - 2)) {
2040 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2041 "number of TX descriptors minus 2. "
2042 "(tx_rs_thresh=%u port=%d queue=%d)",
2043 (unsigned int)tx_rs_thresh,
2044 (int)dev->data->port_id,
2046 return I40E_ERR_PARAM;
2048 if (tx_free_thresh >= (nb_desc - 3)) {
2049 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2050 "number of TX descriptors minus 3. "
2051 "(tx_free_thresh=%u port=%d queue=%d)",
2052 (unsigned int)tx_free_thresh,
2053 (int)dev->data->port_id,
2055 return I40E_ERR_PARAM;
2057 if (tx_rs_thresh > tx_free_thresh) {
2058 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2059 "equal to tx_free_thresh. (tx_free_thresh=%u"
2060 " tx_rs_thresh=%u port=%d queue=%d)",
2061 (unsigned int)tx_free_thresh,
2062 (unsigned int)tx_rs_thresh,
2063 (int)dev->data->port_id,
2065 return I40E_ERR_PARAM;
2067 if ((nb_desc % tx_rs_thresh) != 0) {
2068 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2069 "number of TX descriptors. (tx_rs_thresh=%u"
2070 " port=%d queue=%d)",
2071 (unsigned int)tx_rs_thresh,
2072 (int)dev->data->port_id,
2074 return I40E_ERR_PARAM;
2076 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2077 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2078 "tx_rs_thresh is greater than 1. "
2079 "(tx_rs_thresh=%u port=%d queue=%d)",
2080 (unsigned int)tx_rs_thresh,
2081 (int)dev->data->port_id,
2083 return I40E_ERR_PARAM;
2086 /* Free memory if needed. */
2087 if (dev->data->tx_queues[queue_idx]) {
2088 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2089 dev->data->tx_queues[queue_idx] = NULL;
2092 /* Allocate the TX queue data structure. */
2093 txq = rte_zmalloc_socket("i40e tx queue",
2094 sizeof(struct i40e_tx_queue),
2095 RTE_CACHE_LINE_SIZE,
2098 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2099 "tx queue structure");
2103 /* Allocate TX hardware ring descriptors. */
2104 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2105 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2106 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2107 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2109 i40e_dev_tx_queue_release(txq);
2110 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2114 txq->nb_tx_desc = nb_desc;
2115 txq->tx_rs_thresh = tx_rs_thresh;
2116 txq->tx_free_thresh = tx_free_thresh;
2117 txq->pthresh = tx_conf->tx_thresh.pthresh;
2118 txq->hthresh = tx_conf->tx_thresh.hthresh;
2119 txq->wthresh = tx_conf->tx_thresh.wthresh;
2120 txq->queue_id = queue_idx;
2121 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2122 txq->reg_idx = queue_idx;
2123 else /* PF device */
2124 txq->reg_idx = vsi->base_queue +
2125 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2127 txq->port_id = dev->data->port_id;
2128 txq->txq_flags = tx_conf->txq_flags;
2130 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2132 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2133 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2135 /* Allocate software ring */
2137 rte_zmalloc_socket("i40e tx sw ring",
2138 sizeof(struct i40e_tx_entry) * nb_desc,
2139 RTE_CACHE_LINE_SIZE,
2141 if (!txq->sw_ring) {
2142 i40e_dev_tx_queue_release(txq);
2143 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2147 i40e_reset_tx_queue(txq);
2149 dev->data->tx_queues[queue_idx] = txq;
2151 /* Use a simple TX queue without offloads or multi segs if possible */
2152 i40e_set_tx_function_flag(dev, txq);
2154 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2155 if (!(vsi->enabled_tc & (1 << i)))
2157 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2158 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2159 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2160 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2161 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2163 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2171 i40e_dev_tx_queue_release(void *txq)
2173 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2176 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2180 i40e_tx_queue_release_mbufs(q);
2181 rte_free(q->sw_ring);
2185 const struct rte_memzone *
2186 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2188 const struct rte_memzone *mz;
2190 mz = rte_memzone_lookup(name);
2194 if (rte_xen_dom0_supported())
2195 mz = rte_memzone_reserve_bounded(name, len,
2196 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2198 mz = rte_memzone_reserve_aligned(name, len,
2199 socket_id, 0, I40E_RING_BASE_ALIGN);
2204 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2208 /* SSE Vector driver has a different way of releasing mbufs. */
2209 if (rxq->rx_using_sse) {
2210 i40e_rx_queue_release_mbufs_vec(rxq);
2214 if (!rxq->sw_ring) {
2215 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2219 for (i = 0; i < rxq->nb_rx_desc; i++) {
2220 if (rxq->sw_ring[i].mbuf) {
2221 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2222 rxq->sw_ring[i].mbuf = NULL;
2225 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2226 if (rxq->rx_nb_avail == 0)
2228 for (i = 0; i < rxq->rx_nb_avail; i++) {
2229 struct rte_mbuf *mbuf;
2231 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2232 rte_pktmbuf_free_seg(mbuf);
2234 rxq->rx_nb_avail = 0;
2235 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2239 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2245 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2249 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2250 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2251 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2253 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2254 len = rxq->nb_rx_desc;
2256 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2257 ((volatile char *)rxq->rx_ring)[i] = 0;
2259 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2260 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2261 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2262 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2264 rxq->rx_nb_avail = 0;
2265 rxq->rx_next_avail = 0;
2266 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2267 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2269 rxq->nb_rx_hold = 0;
2270 rxq->pkt_first_seg = NULL;
2271 rxq->pkt_last_seg = NULL;
2273 rxq->rxrearm_start = 0;
2274 rxq->rxrearm_nb = 0;
2278 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2282 if (!txq || !txq->sw_ring) {
2283 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2287 for (i = 0; i < txq->nb_tx_desc; i++) {
2288 if (txq->sw_ring[i].mbuf) {
2289 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2290 txq->sw_ring[i].mbuf = NULL;
2296 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2298 struct i40e_tx_entry *txe;
2299 uint16_t i, prev, size;
2302 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2307 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2308 for (i = 0; i < size; i++)
2309 ((volatile char *)txq->tx_ring)[i] = 0;
2311 prev = (uint16_t)(txq->nb_tx_desc - 1);
2312 for (i = 0; i < txq->nb_tx_desc; i++) {
2313 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2315 txd->cmd_type_offset_bsz =
2316 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2319 txe[prev].next_id = i;
2323 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2324 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2327 txq->nb_tx_used = 0;
2329 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2330 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2333 /* Init the TX queue in hardware */
2335 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2337 enum i40e_status_code err = I40E_SUCCESS;
2338 struct i40e_vsi *vsi = txq->vsi;
2339 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2340 uint16_t pf_q = txq->reg_idx;
2341 struct i40e_hmc_obj_txq tx_ctx;
2344 /* clear the context structure first */
2345 memset(&tx_ctx, 0, sizeof(tx_ctx));
2346 tx_ctx.new_context = 1;
2347 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2348 tx_ctx.qlen = txq->nb_tx_desc;
2350 #ifdef RTE_LIBRTE_IEEE1588
2351 tx_ctx.timesync_ena = 1;
2353 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2354 if (vsi->type == I40E_VSI_FDIR)
2355 tx_ctx.fd_ena = TRUE;
2357 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2358 if (err != I40E_SUCCESS) {
2359 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2363 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2364 if (err != I40E_SUCCESS) {
2365 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2369 /* Now associate this queue with this PCI function */
2370 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2371 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2372 I40E_QTX_CTL_PF_INDX_MASK);
2373 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2374 I40E_WRITE_FLUSH(hw);
2376 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2382 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2384 struct i40e_rx_entry *rxe = rxq->sw_ring;
2388 for (i = 0; i < rxq->nb_rx_desc; i++) {
2389 volatile union i40e_rx_desc *rxd;
2390 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2392 if (unlikely(!mbuf)) {
2393 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2397 rte_mbuf_refcnt_set(mbuf, 1);
2399 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2401 mbuf->port = rxq->port_id;
2404 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2406 rxd = &rxq->rx_ring[i];
2407 rxd->read.pkt_addr = dma_addr;
2408 rxd->read.hdr_addr = 0;
2409 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2410 rxd->read.rsvd1 = 0;
2411 rxd->read.rsvd2 = 0;
2412 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2421 * Calculate the buffer length, and check the jumbo frame
2422 * and maximum packet length.
2425 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2427 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2428 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2429 struct rte_eth_dev_data *data = pf->dev_data;
2430 uint16_t buf_size, len;
2432 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2433 RTE_PKTMBUF_HEADROOM);
2435 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2436 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2437 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2438 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2439 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2440 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2441 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2442 rxq->hs_mode = i40e_header_split_enabled;
2444 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2446 rxq->rx_hdr_len = 0;
2447 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2448 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2449 rxq->hs_mode = i40e_header_split_none;
2453 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2454 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2455 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2456 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2457 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2458 PMD_DRV_LOG(ERR, "maximum packet length must "
2459 "be larger than %u and smaller than %u,"
2460 "as jumbo frame is enabled",
2461 (uint32_t)ETHER_MAX_LEN,
2462 (uint32_t)I40E_FRAME_SIZE_MAX);
2463 return I40E_ERR_CONFIG;
2466 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2467 rxq->max_pkt_len > ETHER_MAX_LEN) {
2468 PMD_DRV_LOG(ERR, "maximum packet length must be "
2469 "larger than %u and smaller than %u, "
2470 "as jumbo frame is disabled",
2471 (uint32_t)ETHER_MIN_LEN,
2472 (uint32_t)ETHER_MAX_LEN);
2473 return I40E_ERR_CONFIG;
2480 /* Init the RX queue in hardware */
2482 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2484 int err = I40E_SUCCESS;
2485 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2486 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2487 uint16_t pf_q = rxq->reg_idx;
2489 struct i40e_hmc_obj_rxq rx_ctx;
2491 err = i40e_rx_queue_config(rxq);
2493 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2497 /* Clear the context structure first */
2498 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2499 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2500 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2502 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2503 rx_ctx.qlen = rxq->nb_rx_desc;
2504 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2507 rx_ctx.dtype = rxq->hs_mode;
2509 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2511 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2512 rx_ctx.rxmax = rxq->max_pkt_len;
2513 rx_ctx.tphrdesc_ena = 1;
2514 rx_ctx.tphwdesc_ena = 1;
2515 rx_ctx.tphdata_ena = 1;
2516 rx_ctx.tphhead_ena = 1;
2517 rx_ctx.lrxqthresh = 2;
2518 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2520 /* showiv indicates if inner VLAN is stripped inside of tunnel
2521 * packet. When set it to 1, vlan information is stripped from
2522 * the inner header, but the hardware does not put it in the
2523 * descriptor. So set it zero by default.
2528 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2529 if (err != I40E_SUCCESS) {
2530 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2533 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2534 if (err != I40E_SUCCESS) {
2535 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2539 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2541 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2542 RTE_PKTMBUF_HEADROOM);
2544 /* Check if scattered RX needs to be used. */
2545 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2546 dev_data->scattered_rx = 1;
2549 /* Init the RX tail regieter. */
2550 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2556 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2560 PMD_INIT_FUNC_TRACE();
2562 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2563 if (!dev->data->tx_queues[i])
2565 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2566 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2569 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2570 if (!dev->data->rx_queues[i])
2572 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2573 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2578 i40e_dev_free_queues(struct rte_eth_dev *dev)
2582 PMD_INIT_FUNC_TRACE();
2584 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2585 if (!dev->data->rx_queues[i])
2587 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2588 dev->data->rx_queues[i] = NULL;
2590 dev->data->nb_rx_queues = 0;
2592 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2593 if (!dev->data->tx_queues[i])
2595 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2596 dev->data->tx_queues[i] = NULL;
2598 dev->data->nb_tx_queues = 0;
2601 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2602 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2604 enum i40e_status_code
2605 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2607 struct i40e_tx_queue *txq;
2608 const struct rte_memzone *tz = NULL;
2610 struct rte_eth_dev *dev;
2613 PMD_DRV_LOG(ERR, "PF is not available");
2614 return I40E_ERR_BAD_PTR;
2617 dev = pf->adapter->eth_dev;
2619 /* Allocate the TX queue data structure. */
2620 txq = rte_zmalloc_socket("i40e fdir tx queue",
2621 sizeof(struct i40e_tx_queue),
2622 RTE_CACHE_LINE_SIZE,
2625 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2626 "tx queue structure.");
2627 return I40E_ERR_NO_MEMORY;
2630 /* Allocate TX hardware ring descriptors. */
2631 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2632 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2634 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2635 I40E_FDIR_QUEUE_ID, ring_size,
2636 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2638 i40e_dev_tx_queue_release(txq);
2639 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2640 return I40E_ERR_NO_MEMORY;
2643 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2644 txq->queue_id = I40E_FDIR_QUEUE_ID;
2645 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2646 txq->vsi = pf->fdir.fdir_vsi;
2648 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2649 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2651 * don't need to allocate software ring and reset for the fdir
2652 * program queue just set the queue has been configured.
2657 return I40E_SUCCESS;
2660 enum i40e_status_code
2661 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2663 struct i40e_rx_queue *rxq;
2664 const struct rte_memzone *rz = NULL;
2666 struct rte_eth_dev *dev;
2669 PMD_DRV_LOG(ERR, "PF is not available");
2670 return I40E_ERR_BAD_PTR;
2673 dev = pf->adapter->eth_dev;
2675 /* Allocate the RX queue data structure. */
2676 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2677 sizeof(struct i40e_rx_queue),
2678 RTE_CACHE_LINE_SIZE,
2681 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2682 "rx queue structure.");
2683 return I40E_ERR_NO_MEMORY;
2686 /* Allocate RX hardware ring descriptors. */
2687 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2688 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2690 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2691 I40E_FDIR_QUEUE_ID, ring_size,
2692 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2694 i40e_dev_rx_queue_release(rxq);
2695 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2696 return I40E_ERR_NO_MEMORY;
2699 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2700 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2701 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2702 rxq->vsi = pf->fdir.fdir_vsi;
2704 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2705 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2708 * Don't need to allocate software ring and reset for the fdir
2709 * rx queue, just set the queue has been configured.
2714 return I40E_SUCCESS;
2718 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2719 struct rte_eth_rxq_info *qinfo)
2721 struct i40e_rx_queue *rxq;
2723 rxq = dev->data->rx_queues[queue_id];
2725 qinfo->mp = rxq->mp;
2726 qinfo->scattered_rx = dev->data->scattered_rx;
2727 qinfo->nb_desc = rxq->nb_rx_desc;
2729 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2730 qinfo->conf.rx_drop_en = rxq->drop_en;
2731 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2735 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2736 struct rte_eth_txq_info *qinfo)
2738 struct i40e_tx_queue *txq;
2740 txq = dev->data->tx_queues[queue_id];
2742 qinfo->nb_desc = txq->nb_tx_desc;
2744 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2745 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2746 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2748 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2749 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2750 qinfo->conf.txq_flags = txq->txq_flags;
2751 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2754 void __attribute__((cold))
2755 i40e_set_rx_function(struct rte_eth_dev *dev)
2757 struct i40e_adapter *ad =
2758 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2759 uint16_t rx_using_sse, i;
2760 /* In order to allow Vector Rx there are a few configuration
2761 * conditions to be met and Rx Bulk Allocation should be allowed.
2763 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2764 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2765 !ad->rx_bulk_alloc_allowed) {
2766 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2767 " Vector Rx preconditions",
2768 dev->data->port_id);
2770 ad->rx_vec_allowed = false;
2772 if (ad->rx_vec_allowed) {
2773 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2774 struct i40e_rx_queue *rxq =
2775 dev->data->rx_queues[i];
2777 if (rxq && i40e_rxq_vec_setup(rxq)) {
2778 ad->rx_vec_allowed = false;
2785 if (dev->data->scattered_rx) {
2786 /* Set the non-LRO scattered callback: there are Vector and
2787 * single allocation versions.
2789 if (ad->rx_vec_allowed) {
2790 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2791 "callback (port=%d).",
2792 dev->data->port_id);
2794 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2796 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2797 "allocation callback (port=%d).",
2798 dev->data->port_id);
2799 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2801 /* If parameters allow we are going to choose between the following
2805 * - Single buffer allocation (the simplest one)
2807 } else if (ad->rx_vec_allowed) {
2808 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2809 "burst size no less than %d (port=%d).",
2810 RTE_I40E_DESCS_PER_LOOP,
2811 dev->data->port_id);
2813 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2814 } else if (ad->rx_bulk_alloc_allowed) {
2815 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2816 "satisfied. Rx Burst Bulk Alloc function "
2817 "will be used on port=%d.",
2818 dev->data->port_id);
2820 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2822 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2823 "satisfied, or Scattered Rx is requested "
2825 dev->data->port_id);
2827 dev->rx_pkt_burst = i40e_recv_pkts;
2830 /* Propagate information about RX function choice through all queues. */
2831 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2833 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2834 dev->rx_pkt_burst == i40e_recv_pkts_vec);
2836 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2837 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2840 rxq->rx_using_sse = rx_using_sse;
2845 void __attribute__((cold))
2846 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2848 struct i40e_adapter *ad =
2849 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2851 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2852 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2853 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2854 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2855 PMD_INIT_LOG(DEBUG, "Vector tx"
2856 " can be enabled on this txq.");
2859 ad->tx_vec_allowed = false;
2862 ad->tx_simple_allowed = false;
2866 void __attribute__((cold))
2867 i40e_set_tx_function(struct rte_eth_dev *dev)
2869 struct i40e_adapter *ad =
2870 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2873 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2874 if (ad->tx_vec_allowed) {
2875 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2876 struct i40e_tx_queue *txq =
2877 dev->data->tx_queues[i];
2879 if (txq && i40e_txq_vec_setup(txq)) {
2880 ad->tx_vec_allowed = false;
2887 if (ad->tx_simple_allowed) {
2888 if (ad->tx_vec_allowed) {
2889 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2890 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2892 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2893 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2895 dev->tx_pkt_prepare = NULL;
2897 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2898 dev->tx_pkt_burst = i40e_xmit_pkts;
2899 dev->tx_pkt_prepare = i40e_prep_pkts;
2903 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2904 int __attribute__((weak))
2905 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2910 uint16_t __attribute__((weak))
2912 void __rte_unused *rx_queue,
2913 struct rte_mbuf __rte_unused **rx_pkts,
2914 uint16_t __rte_unused nb_pkts)
2919 uint16_t __attribute__((weak))
2920 i40e_recv_scattered_pkts_vec(
2921 void __rte_unused *rx_queue,
2922 struct rte_mbuf __rte_unused **rx_pkts,
2923 uint16_t __rte_unused nb_pkts)
2928 int __attribute__((weak))
2929 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2934 int __attribute__((weak))
2935 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2940 void __attribute__((weak))
2941 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2946 uint16_t __attribute__((weak))
2947 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2948 struct rte_mbuf __rte_unused **tx_pkts,
2949 uint16_t __rte_unused nb_pkts)