1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
27 #include "i40e_logs.h"
28 #include "base/i40e_prototype.h"
29 #include "base/i40e_type.h"
30 #include "i40e_ethdev.h"
31 #include "i40e_rxtx.h"
33 #define DEFAULT_TX_RS_THRESH 32
34 #define DEFAULT_TX_FREE_THRESH 32
36 #define I40E_TX_MAX_BURST 32
38 #define I40E_DMA_MEM_ALIGN 4096
40 /* Base address of the HW descriptor ring should be 128B aligned. */
41 #define I40E_RING_BASE_ALIGN 128
43 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
44 ETH_TXQ_FLAGS_NOOFFLOADS)
46 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
48 #ifdef RTE_LIBRTE_IEEE1588
49 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
51 #define I40E_TX_IEEE1588_TMST 0
54 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
58 PKT_TX_OUTER_IP_CKSUM)
60 #define I40E_TX_OFFLOAD_MASK ( \
63 PKT_TX_OUTER_IP_CKSUM | \
67 PKT_TX_TUNNEL_MASK | \
68 I40E_TX_IEEE1588_TMST)
70 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
71 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
74 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
76 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
77 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
78 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
80 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
81 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
82 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
86 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
87 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
88 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
89 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
90 mb->vlan_tci_outer = mb->vlan_tci;
91 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
92 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
93 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
94 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
96 mb->vlan_tci_outer = 0;
99 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
100 mb->vlan_tci, mb->vlan_tci_outer);
103 /* Translate the rx descriptor status to pkt flags */
104 static inline uint64_t
105 i40e_rxd_status_to_pkt_flags(uint64_t qword)
109 /* Check if RSS_HASH */
110 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
111 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
112 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
114 /* Check if FDIR Match */
115 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
121 static inline uint64_t
122 i40e_rxd_error_to_pkt_flags(uint64_t qword)
125 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
127 #define I40E_RX_ERR_BITS 0x3f
128 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
129 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
133 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
134 flags |= PKT_RX_IP_CKSUM_BAD;
136 flags |= PKT_RX_IP_CKSUM_GOOD;
138 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
139 flags |= PKT_RX_L4_CKSUM_BAD;
141 flags |= PKT_RX_L4_CKSUM_GOOD;
143 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
144 flags |= PKT_RX_EIP_CKSUM_BAD;
149 /* Function to check and set the ieee1588 timesync index and get the
152 #ifdef RTE_LIBRTE_IEEE1588
153 static inline uint64_t
154 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
156 uint64_t pkt_flags = 0;
157 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
158 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
159 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
161 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
162 == RTE_PTYPE_L2_ETHER_TIMESYNC)
163 pkt_flags = PKT_RX_IEEE1588_PTP;
165 pkt_flags |= PKT_RX_IEEE1588_TMST;
166 mb->timesync = tsyn & 0x03;
173 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
174 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
176 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
177 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
179 static inline uint64_t
180 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
183 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
184 uint16_t flexbh, flexbl;
186 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
187 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
188 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
189 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
190 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
191 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
194 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
196 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
197 flags |= PKT_RX_FDIR_ID;
198 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
200 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
201 flags |= PKT_RX_FDIR_FLX;
203 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
205 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
206 flags |= PKT_RX_FDIR_FLX;
210 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
211 flags |= PKT_RX_FDIR_ID;
217 i40e_parse_tunneling_params(uint64_t ol_flags,
218 union i40e_tx_offload tx_offload,
219 uint32_t *cd_tunneling)
221 /* EIPT: External (outer) IP header type */
222 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
223 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
224 else if (ol_flags & PKT_TX_OUTER_IPV4)
225 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
226 else if (ol_flags & PKT_TX_OUTER_IPV6)
227 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
229 /* EIPLEN: External (outer) IP header length, in DWords */
230 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
231 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
233 /* L4TUNT: L4 Tunneling Type */
234 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
235 case PKT_TX_TUNNEL_IPIP:
236 /* for non UDP / GRE tunneling, set to 00b */
238 case PKT_TX_TUNNEL_VXLAN:
239 case PKT_TX_TUNNEL_GENEVE:
240 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
242 case PKT_TX_TUNNEL_GRE:
243 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
246 PMD_TX_LOG(ERR, "Tunnel type not supported");
250 /* L4TUNLEN: L4 Tunneling Length, in Words
252 * We depend on app to set rte_mbuf.l2_len correctly.
253 * For IP in GRE it should be set to the length of the GRE
255 * for MAC in GRE or MAC in UDP it should be set to the length
256 * of the GRE or UDP headers plus the inner MAC up to including
257 * its last Ethertype.
259 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
260 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
264 i40e_txd_enable_checksum(uint64_t ol_flags,
267 union i40e_tx_offload tx_offload)
270 if (ol_flags & PKT_TX_TUNNEL_MASK)
271 *td_offset |= (tx_offload.outer_l2_len >> 1)
272 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
274 *td_offset |= (tx_offload.l2_len >> 1)
275 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
277 /* Enable L3 checksum offloads */
278 if (ol_flags & PKT_TX_IP_CKSUM) {
279 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
280 *td_offset |= (tx_offload.l3_len >> 2)
281 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
282 } else if (ol_flags & PKT_TX_IPV4) {
283 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
284 *td_offset |= (tx_offload.l3_len >> 2)
285 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
286 } else if (ol_flags & PKT_TX_IPV6) {
287 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
288 *td_offset |= (tx_offload.l3_len >> 2)
289 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
292 if (ol_flags & PKT_TX_TCP_SEG) {
293 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
294 *td_offset |= (tx_offload.l4_len >> 2)
295 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
299 /* Enable L4 checksum offloads */
300 switch (ol_flags & PKT_TX_L4_MASK) {
301 case PKT_TX_TCP_CKSUM:
302 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
303 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
304 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
306 case PKT_TX_SCTP_CKSUM:
307 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
308 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
309 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
311 case PKT_TX_UDP_CKSUM:
312 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
313 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
314 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
321 /* Construct the tx flags */
322 static inline uint64_t
323 i40e_build_ctob(uint32_t td_cmd,
328 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
329 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
330 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
331 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
332 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
336 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
338 struct i40e_tx_entry *sw_ring = txq->sw_ring;
339 volatile struct i40e_tx_desc *txd = txq->tx_ring;
340 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
341 uint16_t nb_tx_desc = txq->nb_tx_desc;
342 uint16_t desc_to_clean_to;
343 uint16_t nb_tx_to_clean;
345 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
346 if (desc_to_clean_to >= nb_tx_desc)
347 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
349 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
350 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
351 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
352 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
353 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
354 "(port=%d queue=%d)", desc_to_clean_to,
355 txq->port_id, txq->queue_id);
359 if (last_desc_cleaned > desc_to_clean_to)
360 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
363 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
366 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
368 txq->last_desc_cleaned = desc_to_clean_to;
369 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
375 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
376 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
378 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
383 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
384 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
385 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
386 "rxq->rx_free_thresh=%d, "
387 "RTE_PMD_I40E_RX_MAX_BURST=%d",
388 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
390 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
391 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
392 "rxq->rx_free_thresh=%d, "
393 "rxq->nb_rx_desc=%d",
394 rxq->rx_free_thresh, rxq->nb_rx_desc);
396 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
397 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
398 "rxq->nb_rx_desc=%d, "
399 "rxq->rx_free_thresh=%d",
400 rxq->nb_rx_desc, rxq->rx_free_thresh);
410 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
411 #define I40E_LOOK_AHEAD 8
412 #if (I40E_LOOK_AHEAD != 8)
413 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
416 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
418 volatile union i40e_rx_desc *rxdp;
419 struct i40e_rx_entry *rxep;
424 int32_t s[I40E_LOOK_AHEAD], nb_dd;
425 int32_t i, j, nb_rx = 0;
427 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
429 rxdp = &rxq->rx_ring[rxq->rx_tail];
430 rxep = &rxq->sw_ring[rxq->rx_tail];
432 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
433 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
434 I40E_RXD_QW1_STATUS_SHIFT;
436 /* Make sure there is at least 1 packet to receive */
437 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
441 * Scan LOOK_AHEAD descriptors at a time to determine which
442 * descriptors reference packets that are ready to be received.
444 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
445 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
446 /* Read desc statuses backwards to avoid race condition */
447 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
448 qword1 = rte_le_to_cpu_64(\
449 rxdp[j].wb.qword1.status_error_len);
450 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
451 I40E_RXD_QW1_STATUS_SHIFT;
456 /* Compute how many status bits were set */
457 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
458 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
462 /* Translate descriptor info to mbuf parameters */
463 for (j = 0; j < nb_dd; j++) {
465 qword1 = rte_le_to_cpu_64(\
466 rxdp[j].wb.qword1.status_error_len);
467 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
468 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
469 mb->data_len = pkt_len;
470 mb->pkt_len = pkt_len;
472 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
473 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
474 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
476 ptype_tbl[(uint8_t)((qword1 &
477 I40E_RXD_QW1_PTYPE_MASK) >>
478 I40E_RXD_QW1_PTYPE_SHIFT)];
479 if (pkt_flags & PKT_RX_RSS_HASH)
480 mb->hash.rss = rte_le_to_cpu_32(\
481 rxdp[j].wb.qword0.hi_dword.rss);
482 if (pkt_flags & PKT_RX_FDIR)
483 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
485 #ifdef RTE_LIBRTE_IEEE1588
486 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
488 mb->ol_flags |= pkt_flags;
492 for (j = 0; j < I40E_LOOK_AHEAD; j++)
493 rxq->rx_stage[i + j] = rxep[j].mbuf;
495 if (nb_dd != I40E_LOOK_AHEAD)
499 /* Clear software ring entries */
500 for (i = 0; i < nb_rx; i++)
501 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
506 static inline uint16_t
507 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
508 struct rte_mbuf **rx_pkts,
512 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
514 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
516 for (i = 0; i < nb_pkts; i++)
517 rx_pkts[i] = stage[i];
519 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
520 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
526 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
528 volatile union i40e_rx_desc *rxdp;
529 struct i40e_rx_entry *rxep;
531 uint16_t alloc_idx, i;
535 /* Allocate buffers in bulk */
536 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
537 (rxq->rx_free_thresh - 1));
538 rxep = &(rxq->sw_ring[alloc_idx]);
539 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
540 rxq->rx_free_thresh);
541 if (unlikely(diag != 0)) {
542 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
546 rxdp = &rxq->rx_ring[alloc_idx];
547 for (i = 0; i < rxq->rx_free_thresh; i++) {
548 if (likely(i < (rxq->rx_free_thresh - 1)))
549 /* Prefetch next mbuf */
550 rte_prefetch0(rxep[i + 1].mbuf);
553 rte_mbuf_refcnt_set(mb, 1);
555 mb->data_off = RTE_PKTMBUF_HEADROOM;
557 mb->port = rxq->port_id;
558 dma_addr = rte_cpu_to_le_64(\
559 rte_mbuf_data_iova_default(mb));
560 rxdp[i].read.hdr_addr = 0;
561 rxdp[i].read.pkt_addr = dma_addr;
564 /* Update rx tail regsiter */
566 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
568 rxq->rx_free_trigger =
569 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
570 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
571 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
576 static inline uint16_t
577 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
579 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
580 struct rte_eth_dev *dev;
586 if (rxq->rx_nb_avail)
587 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
589 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
590 rxq->rx_next_avail = 0;
591 rxq->rx_nb_avail = nb_rx;
592 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
594 if (rxq->rx_tail > rxq->rx_free_trigger) {
595 if (i40e_rx_alloc_bufs(rxq) != 0) {
598 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
599 dev->data->rx_mbuf_alloc_failed +=
602 rxq->rx_nb_avail = 0;
603 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
604 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
605 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
611 if (rxq->rx_tail >= rxq->nb_rx_desc)
614 if (rxq->rx_nb_avail)
615 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
621 i40e_recv_pkts_bulk_alloc(void *rx_queue,
622 struct rte_mbuf **rx_pkts,
625 uint16_t nb_rx = 0, n, count;
627 if (unlikely(nb_pkts == 0))
630 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
631 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
634 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
635 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
636 nb_rx = (uint16_t)(nb_rx + count);
637 nb_pkts = (uint16_t)(nb_pkts - count);
646 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
647 struct rte_mbuf __rte_unused **rx_pkts,
648 uint16_t __rte_unused nb_pkts)
652 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
655 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
657 struct i40e_rx_queue *rxq;
658 volatile union i40e_rx_desc *rx_ring;
659 volatile union i40e_rx_desc *rxdp;
660 union i40e_rx_desc rxd;
661 struct i40e_rx_entry *sw_ring;
662 struct i40e_rx_entry *rxe;
663 struct rte_eth_dev *dev;
664 struct rte_mbuf *rxm;
665 struct rte_mbuf *nmb;
669 uint16_t rx_packet_len;
670 uint16_t rx_id, nb_hold;
678 rx_id = rxq->rx_tail;
679 rx_ring = rxq->rx_ring;
680 sw_ring = rxq->sw_ring;
681 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
683 while (nb_rx < nb_pkts) {
684 rxdp = &rx_ring[rx_id];
685 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
686 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
687 >> I40E_RXD_QW1_STATUS_SHIFT;
689 /* Check the DD bit first */
690 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
693 nmb = rte_mbuf_raw_alloc(rxq->mp);
694 if (unlikely(!nmb)) {
695 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
696 dev->data->rx_mbuf_alloc_failed++;
702 rxe = &sw_ring[rx_id];
704 if (unlikely(rx_id == rxq->nb_rx_desc))
707 /* Prefetch next mbuf */
708 rte_prefetch0(sw_ring[rx_id].mbuf);
711 * When next RX descriptor is on a cache line boundary,
712 * prefetch the next 4 RX descriptors and next 8 pointers
715 if ((rx_id & 0x3) == 0) {
716 rte_prefetch0(&rx_ring[rx_id]);
717 rte_prefetch0(&sw_ring[rx_id]);
722 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
723 rxdp->read.hdr_addr = 0;
724 rxdp->read.pkt_addr = dma_addr;
726 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
727 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
729 rxm->data_off = RTE_PKTMBUF_HEADROOM;
730 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
733 rxm->pkt_len = rx_packet_len;
734 rxm->data_len = rx_packet_len;
735 rxm->port = rxq->port_id;
737 i40e_rxd_to_vlan_tci(rxm, &rxd);
738 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
739 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
741 ptype_tbl[(uint8_t)((qword1 &
742 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
743 if (pkt_flags & PKT_RX_RSS_HASH)
745 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
746 if (pkt_flags & PKT_RX_FDIR)
747 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
749 #ifdef RTE_LIBRTE_IEEE1588
750 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
752 rxm->ol_flags |= pkt_flags;
754 rx_pkts[nb_rx++] = rxm;
756 rxq->rx_tail = rx_id;
759 * If the number of free RX descriptors is greater than the RX free
760 * threshold of the queue, advance the receive tail register of queue.
761 * Update that register with the value of the last processed RX
762 * descriptor minus 1.
764 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
765 if (nb_hold > rxq->rx_free_thresh) {
766 rx_id = (uint16_t) ((rx_id == 0) ?
767 (rxq->nb_rx_desc - 1) : (rx_id - 1));
768 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
771 rxq->nb_rx_hold = nb_hold;
777 i40e_recv_scattered_pkts(void *rx_queue,
778 struct rte_mbuf **rx_pkts,
781 struct i40e_rx_queue *rxq = rx_queue;
782 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
783 volatile union i40e_rx_desc *rxdp;
784 union i40e_rx_desc rxd;
785 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
786 struct i40e_rx_entry *rxe;
787 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
788 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
789 struct rte_mbuf *nmb, *rxm;
790 uint16_t rx_id = rxq->rx_tail;
791 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
792 struct rte_eth_dev *dev;
797 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
799 while (nb_rx < nb_pkts) {
800 rxdp = &rx_ring[rx_id];
801 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
802 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
803 I40E_RXD_QW1_STATUS_SHIFT;
805 /* Check the DD bit */
806 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
809 nmb = rte_mbuf_raw_alloc(rxq->mp);
810 if (unlikely(!nmb)) {
811 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
812 dev->data->rx_mbuf_alloc_failed++;
818 rxe = &sw_ring[rx_id];
820 if (rx_id == rxq->nb_rx_desc)
823 /* Prefetch next mbuf */
824 rte_prefetch0(sw_ring[rx_id].mbuf);
827 * When next RX descriptor is on a cache line boundary,
828 * prefetch the next 4 RX descriptors and next 8 pointers
831 if ((rx_id & 0x3) == 0) {
832 rte_prefetch0(&rx_ring[rx_id]);
833 rte_prefetch0(&sw_ring[rx_id]);
839 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
841 /* Set data buffer address and data length of the mbuf */
842 rxdp->read.hdr_addr = 0;
843 rxdp->read.pkt_addr = dma_addr;
844 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
845 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
846 rxm->data_len = rx_packet_len;
847 rxm->data_off = RTE_PKTMBUF_HEADROOM;
850 * If this is the first buffer of the received packet, set the
851 * pointer to the first mbuf of the packet and initialize its
852 * context. Otherwise, update the total length and the number
853 * of segments of the current scattered packet, and update the
854 * pointer to the last mbuf of the current packet.
858 first_seg->nb_segs = 1;
859 first_seg->pkt_len = rx_packet_len;
862 (uint16_t)(first_seg->pkt_len +
864 first_seg->nb_segs++;
865 last_seg->next = rxm;
869 * If this is not the last buffer of the received packet,
870 * update the pointer to the last mbuf of the current scattered
871 * packet and continue to parse the RX ring.
873 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
879 * This is the last buffer of the received packet. If the CRC
880 * is not stripped by the hardware:
881 * - Subtract the CRC length from the total packet length.
882 * - If the last buffer only contains the whole CRC or a part
883 * of it, free the mbuf associated to the last buffer. If part
884 * of the CRC is also contained in the previous mbuf, subtract
885 * the length of that CRC part from the data length of the
889 if (unlikely(rxq->crc_len > 0)) {
890 first_seg->pkt_len -= ETHER_CRC_LEN;
891 if (rx_packet_len <= ETHER_CRC_LEN) {
892 rte_pktmbuf_free_seg(rxm);
893 first_seg->nb_segs--;
895 (uint16_t)(last_seg->data_len -
896 (ETHER_CRC_LEN - rx_packet_len));
897 last_seg->next = NULL;
899 rxm->data_len = (uint16_t)(rx_packet_len -
903 first_seg->port = rxq->port_id;
904 first_seg->ol_flags = 0;
905 i40e_rxd_to_vlan_tci(first_seg, &rxd);
906 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
907 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
908 first_seg->packet_type =
909 ptype_tbl[(uint8_t)((qword1 &
910 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
911 if (pkt_flags & PKT_RX_RSS_HASH)
912 first_seg->hash.rss =
913 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
914 if (pkt_flags & PKT_RX_FDIR)
915 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
917 #ifdef RTE_LIBRTE_IEEE1588
918 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
920 first_seg->ol_flags |= pkt_flags;
922 /* Prefetch data of first segment, if configured to do so. */
923 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
924 first_seg->data_off));
925 rx_pkts[nb_rx++] = first_seg;
929 /* Record index of the next RX descriptor to probe. */
930 rxq->rx_tail = rx_id;
931 rxq->pkt_first_seg = first_seg;
932 rxq->pkt_last_seg = last_seg;
935 * If the number of free RX descriptors is greater than the RX free
936 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
937 * register. Update the RDT with the value of the last processed RX
938 * descriptor minus 1, to guarantee that the RDT register is never
939 * equal to the RDH register, which creates a "full" ring situtation
940 * from the hardware point of view.
942 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
943 if (nb_hold > rxq->rx_free_thresh) {
944 rx_id = (uint16_t)(rx_id == 0 ?
945 (rxq->nb_rx_desc - 1) : (rx_id - 1));
946 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
949 rxq->nb_rx_hold = nb_hold;
954 /* Check if the context descriptor is needed for TX offloading */
955 static inline uint16_t
956 i40e_calc_context_desc(uint64_t flags)
958 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
963 #ifdef RTE_LIBRTE_IEEE1588
964 mask |= PKT_TX_IEEE1588_TMST;
967 return (flags & mask) ? 1 : 0;
970 /* set i40e TSO context descriptor */
971 static inline uint64_t
972 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
974 uint64_t ctx_desc = 0;
975 uint32_t cd_cmd, hdr_len, cd_tso_len;
977 if (!tx_offload.l4_len) {
978 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
983 * in case of non tunneling packet, the outer_l2_len and
984 * outer_l3_len must be 0.
986 hdr_len = tx_offload.outer_l2_len +
987 tx_offload.outer_l3_len +
992 cd_cmd = I40E_TX_CTX_DESC_TSO;
993 cd_tso_len = mbuf->pkt_len - hdr_len;
994 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
995 ((uint64_t)cd_tso_len <<
996 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
997 ((uint64_t)mbuf->tso_segsz <<
998 I40E_TXD_CTX_QW1_MSS_SHIFT);
1004 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1006 struct i40e_tx_queue *txq;
1007 struct i40e_tx_entry *sw_ring;
1008 struct i40e_tx_entry *txe, *txn;
1009 volatile struct i40e_tx_desc *txd;
1010 volatile struct i40e_tx_desc *txr;
1011 struct rte_mbuf *tx_pkt;
1012 struct rte_mbuf *m_seg;
1013 uint32_t cd_tunneling_params;
1024 uint64_t buf_dma_addr;
1025 union i40e_tx_offload tx_offload = {0};
1028 sw_ring = txq->sw_ring;
1030 tx_id = txq->tx_tail;
1031 txe = &sw_ring[tx_id];
1033 /* Check if the descriptor ring needs to be cleaned. */
1034 if (txq->nb_tx_free < txq->tx_free_thresh)
1035 i40e_xmit_cleanup(txq);
1037 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1042 tx_pkt = *tx_pkts++;
1043 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1045 ol_flags = tx_pkt->ol_flags;
1046 tx_offload.l2_len = tx_pkt->l2_len;
1047 tx_offload.l3_len = tx_pkt->l3_len;
1048 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1049 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1050 tx_offload.l4_len = tx_pkt->l4_len;
1051 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1053 /* Calculate the number of context descriptors needed. */
1054 nb_ctx = i40e_calc_context_desc(ol_flags);
1057 * The number of descriptors that must be allocated for
1058 * a packet equals to the number of the segments of that
1059 * packet plus 1 context descriptor if needed.
1061 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1062 tx_last = (uint16_t)(tx_id + nb_used - 1);
1065 if (tx_last >= txq->nb_tx_desc)
1066 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1068 if (nb_used > txq->nb_tx_free) {
1069 if (i40e_xmit_cleanup(txq) != 0) {
1074 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1075 while (nb_used > txq->nb_tx_free) {
1076 if (i40e_xmit_cleanup(txq) != 0) {
1085 /* Descriptor based VLAN insertion */
1086 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1087 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1088 td_tag = tx_pkt->vlan_tci;
1091 /* Always enable CRC offload insertion */
1092 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1094 /* Fill in tunneling parameters if necessary */
1095 cd_tunneling_params = 0;
1096 if (ol_flags & PKT_TX_TUNNEL_MASK)
1097 i40e_parse_tunneling_params(ol_flags, tx_offload,
1098 &cd_tunneling_params);
1099 /* Enable checksum offloading */
1100 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1101 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1102 &td_offset, tx_offload);
1105 /* Setup TX context descriptor if required */
1106 volatile struct i40e_tx_context_desc *ctx_txd =
1107 (volatile struct i40e_tx_context_desc *)\
1109 uint16_t cd_l2tag2 = 0;
1110 uint64_t cd_type_cmd_tso_mss =
1111 I40E_TX_DESC_DTYPE_CONTEXT;
1113 txn = &sw_ring[txe->next_id];
1114 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1115 if (txe->mbuf != NULL) {
1116 rte_pktmbuf_free_seg(txe->mbuf);
1120 /* TSO enabled means no timestamp */
1121 if (ol_flags & PKT_TX_TCP_SEG)
1122 cd_type_cmd_tso_mss |=
1123 i40e_set_tso_ctx(tx_pkt, tx_offload);
1125 #ifdef RTE_LIBRTE_IEEE1588
1126 if (ol_flags & PKT_TX_IEEE1588_TMST)
1127 cd_type_cmd_tso_mss |=
1128 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1129 I40E_TXD_CTX_QW1_CMD_SHIFT);
1133 ctx_txd->tunneling_params =
1134 rte_cpu_to_le_32(cd_tunneling_params);
1135 if (ol_flags & PKT_TX_QINQ_PKT) {
1136 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1137 cd_type_cmd_tso_mss |=
1138 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1139 I40E_TXD_CTX_QW1_CMD_SHIFT);
1141 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1142 ctx_txd->type_cmd_tso_mss =
1143 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1145 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1146 "tunneling_params: %#x;\n"
1149 "type_cmd_tso_mss: %#"PRIx64";\n",
1151 ctx_txd->tunneling_params,
1154 ctx_txd->type_cmd_tso_mss);
1156 txe->last_id = tx_last;
1157 tx_id = txe->next_id;
1164 txn = &sw_ring[txe->next_id];
1167 rte_pktmbuf_free_seg(txe->mbuf);
1170 /* Setup TX Descriptor */
1171 slen = m_seg->data_len;
1172 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1174 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1175 "buf_dma_addr: %#"PRIx64";\n"
1180 tx_pkt, tx_id, buf_dma_addr,
1181 td_cmd, td_offset, slen, td_tag);
1183 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1184 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1185 td_offset, slen, td_tag);
1186 txe->last_id = tx_last;
1187 tx_id = txe->next_id;
1189 m_seg = m_seg->next;
1190 } while (m_seg != NULL);
1192 /* The last packet data descriptor needs End Of Packet (EOP) */
1193 td_cmd |= I40E_TX_DESC_CMD_EOP;
1194 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1195 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1197 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1198 PMD_TX_FREE_LOG(DEBUG,
1199 "Setting RS bit on TXD id="
1200 "%4u (port=%d queue=%d)",
1201 tx_last, txq->port_id, txq->queue_id);
1203 td_cmd |= I40E_TX_DESC_CMD_RS;
1205 /* Update txq RS bit counters */
1206 txq->nb_tx_used = 0;
1209 txd->cmd_type_offset_bsz |=
1210 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1211 I40E_TXD_QW1_CMD_SHIFT);
1217 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1218 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1219 (unsigned) tx_id, (unsigned) nb_tx);
1221 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1222 txq->tx_tail = tx_id;
1227 static __rte_always_inline int
1228 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1230 struct i40e_tx_entry *txep;
1233 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1234 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1235 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1238 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1240 for (i = 0; i < txq->tx_rs_thresh; i++)
1241 rte_prefetch0((txep + i)->mbuf);
1243 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1244 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1245 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1249 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1250 rte_pktmbuf_free_seg(txep->mbuf);
1255 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1256 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1257 if (txq->tx_next_dd >= txq->nb_tx_desc)
1258 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1260 return txq->tx_rs_thresh;
1263 /* Populate 4 descriptors with data from 4 mbufs */
1265 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1270 for (i = 0; i < 4; i++, txdp++, pkts++) {
1271 dma_addr = rte_mbuf_data_iova(*pkts);
1272 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1273 txdp->cmd_type_offset_bsz =
1274 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1275 (*pkts)->data_len, 0);
1279 /* Populate 1 descriptor with data from 1 mbuf */
1281 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1285 dma_addr = rte_mbuf_data_iova(*pkts);
1286 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1287 txdp->cmd_type_offset_bsz =
1288 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1289 (*pkts)->data_len, 0);
1292 /* Fill hardware descriptor ring with mbuf data */
1294 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1295 struct rte_mbuf **pkts,
1298 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1299 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1300 const int N_PER_LOOP = 4;
1301 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1302 int mainpart, leftover;
1305 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1306 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1307 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1308 for (j = 0; j < N_PER_LOOP; ++j) {
1309 (txep + i + j)->mbuf = *(pkts + i + j);
1311 tx4(txdp + i, pkts + i);
1313 if (unlikely(leftover > 0)) {
1314 for (i = 0; i < leftover; ++i) {
1315 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1316 tx1(txdp + mainpart + i, pkts + mainpart + i);
1321 static inline uint16_t
1322 tx_xmit_pkts(struct i40e_tx_queue *txq,
1323 struct rte_mbuf **tx_pkts,
1326 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1330 * Begin scanning the H/W ring for done descriptors when the number
1331 * of available descriptors drops below tx_free_thresh. For each done
1332 * descriptor, free the associated buffer.
1334 if (txq->nb_tx_free < txq->tx_free_thresh)
1335 i40e_tx_free_bufs(txq);
1337 /* Use available descriptor only */
1338 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1339 if (unlikely(!nb_pkts))
1342 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1343 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1344 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1345 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1346 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1347 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1348 I40E_TXD_QW1_CMD_SHIFT);
1349 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1353 /* Fill hardware descriptor ring with mbuf data */
1354 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1355 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1357 /* Determin if RS bit needs to be set */
1358 if (txq->tx_tail > txq->tx_next_rs) {
1359 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1360 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1361 I40E_TXD_QW1_CMD_SHIFT);
1363 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1364 if (txq->tx_next_rs >= txq->nb_tx_desc)
1365 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1368 if (txq->tx_tail >= txq->nb_tx_desc)
1371 /* Update the tx tail register */
1373 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1379 i40e_xmit_pkts_simple(void *tx_queue,
1380 struct rte_mbuf **tx_pkts,
1385 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1386 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1390 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1393 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1394 &tx_pkts[nb_tx], num);
1395 nb_tx = (uint16_t)(nb_tx + ret);
1396 nb_pkts = (uint16_t)(nb_pkts - ret);
1405 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1409 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1414 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1415 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1426 /*********************************************************************
1430 **********************************************************************/
1432 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1439 for (i = 0; i < nb_pkts; i++) {
1441 ol_flags = m->ol_flags;
1443 /* Check for m->nb_segs to not exceed the limits. */
1444 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1445 if (m->nb_segs > I40E_TX_MAX_SEG ||
1446 m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1447 rte_errno = -EINVAL;
1450 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1451 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1452 /* MSS outside the range (256B - 9674B) are considered
1455 rte_errno = -EINVAL;
1459 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1460 rte_errno = -ENOTSUP;
1464 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1465 ret = rte_validate_tx_offload(m);
1471 ret = rte_net_intel_cksum_prepare(m);
1481 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1482 * application used, which assume having sequential ones. But from driver's
1483 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1484 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1485 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1486 * use queue_idx from 0 to 95 to access queues, while real queue would be
1487 * different. This function will do a queue mapping to find VSI the queue
1490 static struct i40e_vsi*
1491 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1493 /* the queue in MAIN VSI range */
1494 if (queue_idx < pf->main_vsi->nb_qps)
1495 return pf->main_vsi;
1497 queue_idx -= pf->main_vsi->nb_qps;
1499 /* queue_idx is greater than VMDQ VSIs range */
1500 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1501 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1505 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1509 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1511 /* the queue in MAIN VSI range */
1512 if (queue_idx < pf->main_vsi->nb_qps)
1515 /* It's VMDQ queues */
1516 queue_idx -= pf->main_vsi->nb_qps;
1518 if (pf->nb_cfg_vmdq_vsi)
1519 return queue_idx % pf->vmdq_nb_qps;
1521 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1522 return (uint16_t)(-1);
1527 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1529 struct i40e_rx_queue *rxq;
1531 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533 PMD_INIT_FUNC_TRACE();
1535 if (rx_queue_id < dev->data->nb_rx_queues) {
1536 rxq = dev->data->rx_queues[rx_queue_id];
1538 err = i40e_alloc_rx_queue_mbufs(rxq);
1540 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1546 /* Init the RX tail regieter. */
1547 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1549 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1552 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1555 i40e_rx_queue_release_mbufs(rxq);
1556 i40e_reset_rx_queue(rxq);
1558 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1565 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1567 struct i40e_rx_queue *rxq;
1569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571 if (rx_queue_id < dev->data->nb_rx_queues) {
1572 rxq = dev->data->rx_queues[rx_queue_id];
1575 * rx_queue_id is queue id application refers to, while
1576 * rxq->reg_idx is the real queue index.
1578 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1581 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1585 i40e_rx_queue_release_mbufs(rxq);
1586 i40e_reset_rx_queue(rxq);
1587 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1594 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1597 struct i40e_tx_queue *txq;
1598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 if (tx_queue_id < dev->data->nb_tx_queues) {
1603 txq = dev->data->tx_queues[tx_queue_id];
1606 * tx_queue_id is queue id application refers to, while
1607 * rxq->reg_idx is the real queue index.
1609 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1611 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1614 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1621 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1623 struct i40e_tx_queue *txq;
1625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627 if (tx_queue_id < dev->data->nb_tx_queues) {
1628 txq = dev->data->tx_queues[tx_queue_id];
1631 * tx_queue_id is queue id application refers to, while
1632 * txq->reg_idx is the real queue index.
1634 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1637 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1642 i40e_tx_queue_release_mbufs(txq);
1643 i40e_reset_tx_queue(txq);
1644 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1651 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1653 static const uint32_t ptypes[] = {
1654 /* refers to i40e_rxd_pkt_type_mapping() */
1656 RTE_PTYPE_L2_ETHER_TIMESYNC,
1657 RTE_PTYPE_L2_ETHER_LLDP,
1658 RTE_PTYPE_L2_ETHER_ARP,
1659 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1660 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1663 RTE_PTYPE_L4_NONFRAG,
1667 RTE_PTYPE_TUNNEL_GRENAT,
1668 RTE_PTYPE_TUNNEL_IP,
1669 RTE_PTYPE_INNER_L2_ETHER,
1670 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1671 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1672 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1673 RTE_PTYPE_INNER_L4_FRAG,
1674 RTE_PTYPE_INNER_L4_ICMP,
1675 RTE_PTYPE_INNER_L4_NONFRAG,
1676 RTE_PTYPE_INNER_L4_SCTP,
1677 RTE_PTYPE_INNER_L4_TCP,
1678 RTE_PTYPE_INNER_L4_UDP,
1682 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1683 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1684 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1686 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1687 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1688 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1689 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1690 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1696 i40e_check_rx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
1698 struct rte_eth_dev_info dev_info;
1699 uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1700 uint64_t supported; /* All per port offloads */
1702 dev->dev_ops->dev_infos_get(dev, &dev_info);
1703 supported = dev_info.rx_offload_capa ^ dev_info.rx_queue_offload_capa;
1704 if ((requested & dev_info.rx_offload_capa) != requested)
1705 return 0; /* requested range check */
1706 return !((mandatory ^ requested) & supported);
1710 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1714 for (i = 0; i < num; i++) {
1715 if (i != idx && queues[i])
1723 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1724 struct i40e_rx_queue *rxq)
1726 struct i40e_adapter *ad =
1727 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1728 int use_def_burst_func =
1729 check_rx_burst_bulk_alloc_preconditions(rxq);
1731 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1732 RTE_PKTMBUF_HEADROOM);
1733 int use_scattered_rx =
1734 ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size);
1736 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1738 "Failed to do RX queue initialization");
1742 if (i40e_dev_first_queue(rxq->queue_id,
1743 dev->data->rx_queues,
1744 dev->data->nb_rx_queues)) {
1746 * If it is the first queue to setup,
1747 * set all flags to default and call
1748 * i40e_set_rx_function.
1750 ad->rx_bulk_alloc_allowed = true;
1751 ad->rx_vec_allowed = true;
1752 dev->data->scattered_rx = use_scattered_rx;
1753 if (use_def_burst_func)
1754 ad->rx_bulk_alloc_allowed = false;
1755 i40e_set_rx_function(dev);
1759 /* check bulk alloc conflict */
1760 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1761 PMD_DRV_LOG(ERR, "Can't use default burst.");
1764 /* check scatterred conflict */
1765 if (!dev->data->scattered_rx && use_scattered_rx) {
1766 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1769 /* check vector conflict */
1770 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1771 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1779 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1782 unsigned int socket_id,
1783 const struct rte_eth_rxconf *rx_conf,
1784 struct rte_mempool *mp)
1786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787 struct i40e_adapter *ad =
1788 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1789 struct i40e_vsi *vsi;
1790 struct i40e_pf *pf = NULL;
1791 struct i40e_vf *vf = NULL;
1792 struct i40e_rx_queue *rxq;
1793 const struct rte_memzone *rz;
1796 uint16_t reg_idx, base, bsf, tc_mapping;
1797 int q_offset, use_def_burst_func = 1;
1798 struct rte_eth_dev_info dev_info;
1800 if (!i40e_check_rx_queue_offloads(dev, rx_conf->offloads)) {
1801 dev->dev_ops->dev_infos_get(dev, &dev_info);
1802 PMD_INIT_LOG(ERR, "%p: Rx queue offloads 0x%" PRIx64
1803 " don't match port offloads 0x%" PRIx64
1804 " or supported offloads 0x%" PRIx64,
1805 (void *)dev, rx_conf->offloads,
1806 dev->data->dev_conf.rxmode.offloads,
1807 dev_info.rx_offload_capa);
1811 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1812 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1816 reg_idx = queue_idx;
1818 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1819 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1822 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1825 reg_idx = vsi->base_queue + q_offset;
1828 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1829 (nb_desc > I40E_MAX_RING_DESC) ||
1830 (nb_desc < I40E_MIN_RING_DESC)) {
1831 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1832 "invalid", nb_desc);
1836 /* Free memory if needed */
1837 if (dev->data->rx_queues[queue_idx]) {
1838 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1839 dev->data->rx_queues[queue_idx] = NULL;
1842 /* Allocate the rx queue data structure */
1843 rxq = rte_zmalloc_socket("i40e rx queue",
1844 sizeof(struct i40e_rx_queue),
1845 RTE_CACHE_LINE_SIZE,
1848 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1849 "rx queue data structure");
1853 rxq->nb_rx_desc = nb_desc;
1854 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1855 rxq->queue_id = queue_idx;
1856 rxq->reg_idx = reg_idx;
1857 rxq->port_id = dev->data->port_id;
1858 rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.offloads &
1859 DEV_RX_OFFLOAD_CRC_STRIP) ? 0 : ETHER_CRC_LEN);
1860 rxq->drop_en = rx_conf->rx_drop_en;
1862 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1864 /* Allocate the maximun number of RX ring hardware descriptor. */
1865 len = I40E_MAX_RING_DESC;
1868 * Allocating a little more memory because vectorized/bulk_alloc Rx
1869 * functions doesn't check boundaries each time.
1871 len += RTE_PMD_I40E_RX_MAX_BURST;
1873 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1874 I40E_DMA_MEM_ALIGN);
1876 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1877 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1879 i40e_dev_rx_queue_release(rxq);
1880 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1884 /* Zero all the descriptors in the ring. */
1885 memset(rz->addr, 0, ring_size);
1887 rxq->rx_ring_phys_addr = rz->iova;
1888 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1890 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1892 /* Allocate the software ring. */
1894 rte_zmalloc_socket("i40e rx sw ring",
1895 sizeof(struct i40e_rx_entry) * len,
1896 RTE_CACHE_LINE_SIZE,
1898 if (!rxq->sw_ring) {
1899 i40e_dev_rx_queue_release(rxq);
1900 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1904 i40e_reset_rx_queue(rxq);
1907 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1908 if (!(vsi->enabled_tc & (1 << i)))
1910 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1911 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1912 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1913 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1914 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1916 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1920 if (dev->data->dev_started) {
1921 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1922 i40e_dev_rx_queue_release(rxq);
1926 use_def_burst_func =
1927 check_rx_burst_bulk_alloc_preconditions(rxq);
1928 if (!use_def_burst_func) {
1929 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1931 "Rx Burst Bulk Alloc Preconditions are "
1932 "satisfied. Rx Burst Bulk Alloc function will be "
1933 "used on port=%d, queue=%d.",
1934 rxq->port_id, rxq->queue_id);
1935 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1938 "Rx Burst Bulk Alloc Preconditions are "
1939 "not satisfied, Scattered Rx is requested, "
1940 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1941 "not enabled on port=%d, queue=%d.",
1942 rxq->port_id, rxq->queue_id);
1943 ad->rx_bulk_alloc_allowed = false;
1947 dev->data->rx_queues[queue_idx] = rxq;
1952 i40e_dev_rx_queue_release(void *rxq)
1954 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1957 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1961 i40e_rx_queue_release_mbufs(q);
1962 rte_free(q->sw_ring);
1967 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1969 #define I40E_RXQ_SCAN_INTERVAL 4
1970 volatile union i40e_rx_desc *rxdp;
1971 struct i40e_rx_queue *rxq;
1974 rxq = dev->data->rx_queues[rx_queue_id];
1975 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1976 while ((desc < rxq->nb_rx_desc) &&
1977 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1978 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1979 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1981 * Check the DD bit of a rx descriptor of each 4 in a group,
1982 * to avoid checking too frequently and downgrading performance
1985 desc += I40E_RXQ_SCAN_INTERVAL;
1986 rxdp += I40E_RXQ_SCAN_INTERVAL;
1987 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1988 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1989 desc - rxq->nb_rx_desc]);
1996 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1998 volatile union i40e_rx_desc *rxdp;
1999 struct i40e_rx_queue *rxq = rx_queue;
2003 if (unlikely(offset >= rxq->nb_rx_desc)) {
2004 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2008 desc = rxq->rx_tail + offset;
2009 if (desc >= rxq->nb_rx_desc)
2010 desc -= rxq->nb_rx_desc;
2012 rxdp = &(rxq->rx_ring[desc]);
2014 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2015 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2016 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2022 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2024 struct i40e_rx_queue *rxq = rx_queue;
2025 volatile uint64_t *status;
2029 if (unlikely(offset >= rxq->nb_rx_desc))
2032 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2033 return RTE_ETH_RX_DESC_UNAVAIL;
2035 desc = rxq->rx_tail + offset;
2036 if (desc >= rxq->nb_rx_desc)
2037 desc -= rxq->nb_rx_desc;
2039 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2040 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2041 << I40E_RXD_QW1_STATUS_SHIFT);
2043 return RTE_ETH_RX_DESC_DONE;
2045 return RTE_ETH_RX_DESC_AVAIL;
2049 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2051 struct i40e_tx_queue *txq = tx_queue;
2052 volatile uint64_t *status;
2053 uint64_t mask, expect;
2056 if (unlikely(offset >= txq->nb_tx_desc))
2059 desc = txq->tx_tail + offset;
2060 /* go to next desc that has the RS bit */
2061 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2063 if (desc >= txq->nb_tx_desc) {
2064 desc -= txq->nb_tx_desc;
2065 if (desc >= txq->nb_tx_desc)
2066 desc -= txq->nb_tx_desc;
2069 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2070 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2071 expect = rte_cpu_to_le_64(
2072 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2073 if ((*status & mask) == expect)
2074 return RTE_ETH_TX_DESC_DONE;
2076 return RTE_ETH_TX_DESC_FULL;
2080 i40e_check_tx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
2082 struct rte_eth_dev_info dev_info;
2083 uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
2084 uint64_t supported; /* All per port offloads */
2086 dev->dev_ops->dev_infos_get(dev, &dev_info);
2087 supported = dev_info.tx_offload_capa ^ dev_info.tx_queue_offload_capa;
2088 if ((requested & dev_info.tx_offload_capa) != requested)
2089 return 0; /* requested range check */
2090 return !((mandatory ^ requested) & supported);
2094 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2095 struct i40e_tx_queue *txq)
2097 struct i40e_adapter *ad =
2098 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2100 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2102 "Failed to do TX queue initialization");
2106 if (i40e_dev_first_queue(txq->queue_id,
2107 dev->data->tx_queues,
2108 dev->data->nb_tx_queues)) {
2110 * If it is the first queue to setup,
2111 * set all flags to default and call
2112 * i40e_set_tx_function.
2114 ad->tx_simple_allowed = true;
2115 ad->tx_vec_allowed = true;
2116 i40e_set_tx_function_flag(dev, txq);
2117 i40e_set_tx_function(dev);
2121 /* check vector conflict */
2122 if (ad->tx_vec_allowed) {
2123 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2124 i40e_txq_vec_setup(txq)) {
2125 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2129 /* check simple tx conflict */
2130 if (ad->tx_simple_allowed) {
2131 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) !=
2132 I40E_SIMPLE_FLAGS) ||
2133 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2134 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2143 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2146 unsigned int socket_id,
2147 const struct rte_eth_txconf *tx_conf)
2149 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 struct i40e_vsi *vsi;
2151 struct i40e_pf *pf = NULL;
2152 struct i40e_vf *vf = NULL;
2153 struct i40e_tx_queue *txq;
2154 const struct rte_memzone *tz;
2156 uint16_t tx_rs_thresh, tx_free_thresh;
2157 uint16_t reg_idx, i, base, bsf, tc_mapping;
2159 struct rte_eth_dev_info dev_info;
2161 if (!i40e_check_tx_queue_offloads(dev, tx_conf->offloads)) {
2162 dev->dev_ops->dev_infos_get(dev, &dev_info);
2163 PMD_INIT_LOG(ERR, "%p: Tx queue offloads 0x%" PRIx64
2164 " don't match port offloads 0x%" PRIx64
2165 " or supported offloads 0x%" PRIx64,
2166 (void *)dev, tx_conf->offloads,
2167 dev->data->dev_conf.txmode.offloads,
2168 dev_info.tx_offload_capa); }
2170 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2171 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2175 reg_idx = queue_idx;
2177 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2178 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2181 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2184 reg_idx = vsi->base_queue + q_offset;
2187 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2188 (nb_desc > I40E_MAX_RING_DESC) ||
2189 (nb_desc < I40E_MIN_RING_DESC)) {
2190 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2191 "invalid", nb_desc);
2196 * The following two parameters control the setting of the RS bit on
2197 * transmit descriptors. TX descriptors will have their RS bit set
2198 * after txq->tx_rs_thresh descriptors have been used. The TX
2199 * descriptor ring will be cleaned after txq->tx_free_thresh
2200 * descriptors are used or if the number of descriptors required to
2201 * transmit a packet is greater than the number of free TX descriptors.
2203 * The following constraints must be satisfied:
2204 * - tx_rs_thresh must be greater than 0.
2205 * - tx_rs_thresh must be less than the size of the ring minus 2.
2206 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2207 * - tx_rs_thresh must be a divisor of the ring size.
2208 * - tx_free_thresh must be greater than 0.
2209 * - tx_free_thresh must be less than the size of the ring minus 3.
2211 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2212 * race condition, hence the maximum threshold constraints. When set
2213 * to zero use default values.
2215 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2216 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2217 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2218 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2219 if (tx_rs_thresh >= (nb_desc - 2)) {
2220 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2221 "number of TX descriptors minus 2. "
2222 "(tx_rs_thresh=%u port=%d queue=%d)",
2223 (unsigned int)tx_rs_thresh,
2224 (int)dev->data->port_id,
2226 return I40E_ERR_PARAM;
2228 if (tx_free_thresh >= (nb_desc - 3)) {
2229 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2230 "number of TX descriptors minus 3. "
2231 "(tx_free_thresh=%u port=%d queue=%d)",
2232 (unsigned int)tx_free_thresh,
2233 (int)dev->data->port_id,
2235 return I40E_ERR_PARAM;
2237 if (tx_rs_thresh > tx_free_thresh) {
2238 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2239 "equal to tx_free_thresh. (tx_free_thresh=%u"
2240 " tx_rs_thresh=%u port=%d queue=%d)",
2241 (unsigned int)tx_free_thresh,
2242 (unsigned int)tx_rs_thresh,
2243 (int)dev->data->port_id,
2245 return I40E_ERR_PARAM;
2247 if ((nb_desc % tx_rs_thresh) != 0) {
2248 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2249 "number of TX descriptors. (tx_rs_thresh=%u"
2250 " port=%d queue=%d)",
2251 (unsigned int)tx_rs_thresh,
2252 (int)dev->data->port_id,
2254 return I40E_ERR_PARAM;
2256 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2257 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2258 "tx_rs_thresh is greater than 1. "
2259 "(tx_rs_thresh=%u port=%d queue=%d)",
2260 (unsigned int)tx_rs_thresh,
2261 (int)dev->data->port_id,
2263 return I40E_ERR_PARAM;
2266 /* Free memory if needed. */
2267 if (dev->data->tx_queues[queue_idx]) {
2268 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2269 dev->data->tx_queues[queue_idx] = NULL;
2272 /* Allocate the TX queue data structure. */
2273 txq = rte_zmalloc_socket("i40e tx queue",
2274 sizeof(struct i40e_tx_queue),
2275 RTE_CACHE_LINE_SIZE,
2278 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2279 "tx queue structure");
2283 /* Allocate TX hardware ring descriptors. */
2284 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2285 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2286 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2287 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2289 i40e_dev_tx_queue_release(txq);
2290 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2294 txq->nb_tx_desc = nb_desc;
2295 txq->tx_rs_thresh = tx_rs_thresh;
2296 txq->tx_free_thresh = tx_free_thresh;
2297 txq->pthresh = tx_conf->tx_thresh.pthresh;
2298 txq->hthresh = tx_conf->tx_thresh.hthresh;
2299 txq->wthresh = tx_conf->tx_thresh.wthresh;
2300 txq->queue_id = queue_idx;
2301 txq->reg_idx = reg_idx;
2302 txq->port_id = dev->data->port_id;
2303 txq->txq_flags = tx_conf->txq_flags;
2305 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2307 txq->tx_ring_phys_addr = tz->iova;
2308 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2310 /* Allocate software ring */
2312 rte_zmalloc_socket("i40e tx sw ring",
2313 sizeof(struct i40e_tx_entry) * nb_desc,
2314 RTE_CACHE_LINE_SIZE,
2316 if (!txq->sw_ring) {
2317 i40e_dev_tx_queue_release(txq);
2318 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2322 i40e_reset_tx_queue(txq);
2325 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2326 if (!(vsi->enabled_tc & (1 << i)))
2328 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2329 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2330 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2331 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2332 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2334 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2338 if (dev->data->dev_started) {
2339 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2340 i40e_dev_tx_queue_release(txq);
2345 * Use a simple TX queue without offloads or
2346 * multi segs if possible
2348 i40e_set_tx_function_flag(dev, txq);
2350 dev->data->tx_queues[queue_idx] = txq;
2356 i40e_dev_tx_queue_release(void *txq)
2358 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2361 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2365 i40e_tx_queue_release_mbufs(q);
2366 rte_free(q->sw_ring);
2370 const struct rte_memzone *
2371 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2373 const struct rte_memzone *mz;
2375 mz = rte_memzone_lookup(name);
2379 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2380 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2385 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2389 /* SSE Vector driver has a different way of releasing mbufs. */
2390 if (rxq->rx_using_sse) {
2391 i40e_rx_queue_release_mbufs_vec(rxq);
2395 if (!rxq->sw_ring) {
2396 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2400 for (i = 0; i < rxq->nb_rx_desc; i++) {
2401 if (rxq->sw_ring[i].mbuf) {
2402 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2403 rxq->sw_ring[i].mbuf = NULL;
2406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2407 if (rxq->rx_nb_avail == 0)
2409 for (i = 0; i < rxq->rx_nb_avail; i++) {
2410 struct rte_mbuf *mbuf;
2412 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2413 rte_pktmbuf_free_seg(mbuf);
2415 rxq->rx_nb_avail = 0;
2416 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2420 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2426 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2430 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2431 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2432 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2434 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2435 len = rxq->nb_rx_desc;
2437 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2438 ((volatile char *)rxq->rx_ring)[i] = 0;
2440 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2441 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2442 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2444 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2445 rxq->rx_nb_avail = 0;
2446 rxq->rx_next_avail = 0;
2447 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2448 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2450 rxq->nb_rx_hold = 0;
2451 rxq->pkt_first_seg = NULL;
2452 rxq->pkt_last_seg = NULL;
2454 rxq->rxrearm_start = 0;
2455 rxq->rxrearm_nb = 0;
2459 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2461 struct rte_eth_dev *dev;
2464 dev = &rte_eth_devices[txq->port_id];
2466 if (!txq || !txq->sw_ring) {
2467 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2472 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2473 * so need to free remains more carefully.
2475 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2476 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2477 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2478 if (txq->tx_tail < i) {
2479 for (; i < txq->nb_tx_desc; i++) {
2480 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2481 txq->sw_ring[i].mbuf = NULL;
2485 for (; i < txq->tx_tail; i++) {
2486 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2487 txq->sw_ring[i].mbuf = NULL;
2490 for (i = 0; i < txq->nb_tx_desc; i++) {
2491 if (txq->sw_ring[i].mbuf) {
2492 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2493 txq->sw_ring[i].mbuf = NULL;
2500 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2502 struct i40e_tx_entry *txe;
2503 uint16_t i, prev, size;
2506 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2511 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2512 for (i = 0; i < size; i++)
2513 ((volatile char *)txq->tx_ring)[i] = 0;
2515 prev = (uint16_t)(txq->nb_tx_desc - 1);
2516 for (i = 0; i < txq->nb_tx_desc; i++) {
2517 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2519 txd->cmd_type_offset_bsz =
2520 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2523 txe[prev].next_id = i;
2527 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2528 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2531 txq->nb_tx_used = 0;
2533 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2534 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2537 /* Init the TX queue in hardware */
2539 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2541 enum i40e_status_code err = I40E_SUCCESS;
2542 struct i40e_vsi *vsi = txq->vsi;
2543 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2544 uint16_t pf_q = txq->reg_idx;
2545 struct i40e_hmc_obj_txq tx_ctx;
2548 /* clear the context structure first */
2549 memset(&tx_ctx, 0, sizeof(tx_ctx));
2550 tx_ctx.new_context = 1;
2551 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2552 tx_ctx.qlen = txq->nb_tx_desc;
2554 #ifdef RTE_LIBRTE_IEEE1588
2555 tx_ctx.timesync_ena = 1;
2557 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2558 if (vsi->type == I40E_VSI_FDIR)
2559 tx_ctx.fd_ena = TRUE;
2561 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2562 if (err != I40E_SUCCESS) {
2563 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2567 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2568 if (err != I40E_SUCCESS) {
2569 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2573 /* Now associate this queue with this PCI function */
2574 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2575 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2576 I40E_QTX_CTL_PF_INDX_MASK);
2577 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2578 I40E_WRITE_FLUSH(hw);
2580 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2586 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2588 struct i40e_rx_entry *rxe = rxq->sw_ring;
2592 for (i = 0; i < rxq->nb_rx_desc; i++) {
2593 volatile union i40e_rx_desc *rxd;
2594 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2596 if (unlikely(!mbuf)) {
2597 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2601 rte_mbuf_refcnt_set(mbuf, 1);
2603 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2605 mbuf->port = rxq->port_id;
2608 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2610 rxd = &rxq->rx_ring[i];
2611 rxd->read.pkt_addr = dma_addr;
2612 rxd->read.hdr_addr = 0;
2613 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2614 rxd->read.rsvd1 = 0;
2615 rxd->read.rsvd2 = 0;
2616 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2625 * Calculate the buffer length, and check the jumbo frame
2626 * and maximum packet length.
2629 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2631 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2632 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2633 struct rte_eth_dev_data *data = pf->dev_data;
2634 uint16_t buf_size, len;
2636 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2637 RTE_PKTMBUF_HEADROOM);
2639 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2640 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2641 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2642 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2643 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2644 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2645 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2646 rxq->hs_mode = i40e_header_split_enabled;
2648 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2650 rxq->rx_hdr_len = 0;
2651 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2652 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2653 rxq->hs_mode = i40e_header_split_none;
2657 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2658 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2659 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2660 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2661 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2662 PMD_DRV_LOG(ERR, "maximum packet length must "
2663 "be larger than %u and smaller than %u,"
2664 "as jumbo frame is enabled",
2665 (uint32_t)ETHER_MAX_LEN,
2666 (uint32_t)I40E_FRAME_SIZE_MAX);
2667 return I40E_ERR_CONFIG;
2670 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2671 rxq->max_pkt_len > ETHER_MAX_LEN) {
2672 PMD_DRV_LOG(ERR, "maximum packet length must be "
2673 "larger than %u and smaller than %u, "
2674 "as jumbo frame is disabled",
2675 (uint32_t)ETHER_MIN_LEN,
2676 (uint32_t)ETHER_MAX_LEN);
2677 return I40E_ERR_CONFIG;
2684 /* Init the RX queue in hardware */
2686 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2688 int err = I40E_SUCCESS;
2689 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2690 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2691 uint16_t pf_q = rxq->reg_idx;
2693 struct i40e_hmc_obj_rxq rx_ctx;
2695 err = i40e_rx_queue_config(rxq);
2697 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2701 /* Clear the context structure first */
2702 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2703 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2704 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2706 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2707 rx_ctx.qlen = rxq->nb_rx_desc;
2708 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2711 rx_ctx.dtype = rxq->hs_mode;
2713 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2715 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2716 rx_ctx.rxmax = rxq->max_pkt_len;
2717 rx_ctx.tphrdesc_ena = 1;
2718 rx_ctx.tphwdesc_ena = 1;
2719 rx_ctx.tphdata_ena = 1;
2720 rx_ctx.tphhead_ena = 1;
2721 rx_ctx.lrxqthresh = 2;
2722 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2724 /* showiv indicates if inner VLAN is stripped inside of tunnel
2725 * packet. When set it to 1, vlan information is stripped from
2726 * the inner header, but the hardware does not put it in the
2727 * descriptor. So set it zero by default.
2732 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2733 if (err != I40E_SUCCESS) {
2734 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2737 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2738 if (err != I40E_SUCCESS) {
2739 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2743 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2745 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2746 RTE_PKTMBUF_HEADROOM);
2748 /* Check if scattered RX needs to be used. */
2749 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2750 dev_data->scattered_rx = 1;
2753 /* Init the RX tail regieter. */
2754 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2760 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2764 PMD_INIT_FUNC_TRACE();
2766 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2767 if (!dev->data->tx_queues[i])
2769 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2770 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2773 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2774 if (!dev->data->rx_queues[i])
2776 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2777 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2782 i40e_dev_free_queues(struct rte_eth_dev *dev)
2786 PMD_INIT_FUNC_TRACE();
2788 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2789 if (!dev->data->rx_queues[i])
2791 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2792 dev->data->rx_queues[i] = NULL;
2794 dev->data->nb_rx_queues = 0;
2796 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2797 if (!dev->data->tx_queues[i])
2799 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2800 dev->data->tx_queues[i] = NULL;
2802 dev->data->nb_tx_queues = 0;
2805 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2806 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2808 enum i40e_status_code
2809 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2811 struct i40e_tx_queue *txq;
2812 const struct rte_memzone *tz = NULL;
2814 struct rte_eth_dev *dev;
2817 PMD_DRV_LOG(ERR, "PF is not available");
2818 return I40E_ERR_BAD_PTR;
2821 dev = pf->adapter->eth_dev;
2823 /* Allocate the TX queue data structure. */
2824 txq = rte_zmalloc_socket("i40e fdir tx queue",
2825 sizeof(struct i40e_tx_queue),
2826 RTE_CACHE_LINE_SIZE,
2829 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2830 "tx queue structure.");
2831 return I40E_ERR_NO_MEMORY;
2834 /* Allocate TX hardware ring descriptors. */
2835 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2836 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2838 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2839 I40E_FDIR_QUEUE_ID, ring_size,
2840 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2842 i40e_dev_tx_queue_release(txq);
2843 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2844 return I40E_ERR_NO_MEMORY;
2847 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2848 txq->queue_id = I40E_FDIR_QUEUE_ID;
2849 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2850 txq->vsi = pf->fdir.fdir_vsi;
2852 txq->tx_ring_phys_addr = tz->iova;
2853 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2855 * don't need to allocate software ring and reset for the fdir
2856 * program queue just set the queue has been configured.
2861 return I40E_SUCCESS;
2864 enum i40e_status_code
2865 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2867 struct i40e_rx_queue *rxq;
2868 const struct rte_memzone *rz = NULL;
2870 struct rte_eth_dev *dev;
2873 PMD_DRV_LOG(ERR, "PF is not available");
2874 return I40E_ERR_BAD_PTR;
2877 dev = pf->adapter->eth_dev;
2879 /* Allocate the RX queue data structure. */
2880 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2881 sizeof(struct i40e_rx_queue),
2882 RTE_CACHE_LINE_SIZE,
2885 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2886 "rx queue structure.");
2887 return I40E_ERR_NO_MEMORY;
2890 /* Allocate RX hardware ring descriptors. */
2891 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2892 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2894 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2895 I40E_FDIR_QUEUE_ID, ring_size,
2896 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2898 i40e_dev_rx_queue_release(rxq);
2899 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2900 return I40E_ERR_NO_MEMORY;
2903 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2904 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2905 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2906 rxq->vsi = pf->fdir.fdir_vsi;
2908 rxq->rx_ring_phys_addr = rz->iova;
2909 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2910 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2913 * Don't need to allocate software ring and reset for the fdir
2914 * rx queue, just set the queue has been configured.
2919 return I40E_SUCCESS;
2923 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2924 struct rte_eth_rxq_info *qinfo)
2926 struct i40e_rx_queue *rxq;
2928 rxq = dev->data->rx_queues[queue_id];
2930 qinfo->mp = rxq->mp;
2931 qinfo->scattered_rx = dev->data->scattered_rx;
2932 qinfo->nb_desc = rxq->nb_rx_desc;
2934 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2935 qinfo->conf.rx_drop_en = rxq->drop_en;
2936 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2937 qinfo->conf.offloads = rxq->offloads;
2941 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2942 struct rte_eth_txq_info *qinfo)
2944 struct i40e_tx_queue *txq;
2946 txq = dev->data->tx_queues[queue_id];
2948 qinfo->nb_desc = txq->nb_tx_desc;
2950 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2951 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2952 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2954 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2955 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2956 qinfo->conf.txq_flags = txq->txq_flags;
2957 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2960 void __attribute__((cold))
2961 i40e_set_rx_function(struct rte_eth_dev *dev)
2963 struct i40e_adapter *ad =
2964 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2965 uint16_t rx_using_sse, i;
2966 /* In order to allow Vector Rx there are a few configuration
2967 * conditions to be met and Rx Bulk Allocation should be allowed.
2969 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2970 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2971 !ad->rx_bulk_alloc_allowed) {
2972 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2973 " Vector Rx preconditions",
2974 dev->data->port_id);
2976 ad->rx_vec_allowed = false;
2978 if (ad->rx_vec_allowed) {
2979 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2980 struct i40e_rx_queue *rxq =
2981 dev->data->rx_queues[i];
2983 if (rxq && i40e_rxq_vec_setup(rxq)) {
2984 ad->rx_vec_allowed = false;
2991 if (dev->data->scattered_rx) {
2992 /* Set the non-LRO scattered callback: there are Vector and
2993 * single allocation versions.
2995 if (ad->rx_vec_allowed) {
2996 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2997 "callback (port=%d).",
2998 dev->data->port_id);
3000 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3003 * since AVX frequency can be different to base
3004 * frequency, limit use of AVX2 version to later
3005 * plaforms, not all those that could theoretically
3008 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3010 i40e_recv_scattered_pkts_vec_avx2;
3013 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3014 "allocation callback (port=%d).",
3015 dev->data->port_id);
3016 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3018 /* If parameters allow we are going to choose between the following
3022 * - Single buffer allocation (the simplest one)
3024 } else if (ad->rx_vec_allowed) {
3025 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3026 "burst size no less than %d (port=%d).",
3027 RTE_I40E_DESCS_PER_LOOP,
3028 dev->data->port_id);
3030 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3033 * since AVX frequency can be different to base
3034 * frequency, limit use of AVX2 version to later
3035 * plaforms, not all those that could theoretically
3038 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3039 dev->rx_pkt_burst = i40e_recv_pkts_vec_avx2;
3041 } else if (ad->rx_bulk_alloc_allowed) {
3042 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3043 "satisfied. Rx Burst Bulk Alloc function "
3044 "will be used on port=%d.",
3045 dev->data->port_id);
3047 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3049 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3050 "satisfied, or Scattered Rx is requested "
3052 dev->data->port_id);
3054 dev->rx_pkt_burst = i40e_recv_pkts;
3057 /* Propagate information about RX function choice through all queues. */
3058 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3060 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3061 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3062 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3063 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3065 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3066 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3069 rxq->rx_using_sse = rx_using_sse;
3074 void __attribute__((cold))
3075 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3077 struct i40e_adapter *ad =
3078 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3080 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3081 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3082 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3083 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3084 PMD_INIT_LOG(DEBUG, "Vector tx"
3085 " can be enabled on this txq.");
3088 ad->tx_vec_allowed = false;
3091 ad->tx_simple_allowed = false;
3095 void __attribute__((cold))
3096 i40e_set_tx_function(struct rte_eth_dev *dev)
3098 struct i40e_adapter *ad =
3099 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3102 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3103 if (ad->tx_vec_allowed) {
3104 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3105 struct i40e_tx_queue *txq =
3106 dev->data->tx_queues[i];
3108 if (txq && i40e_txq_vec_setup(txq)) {
3109 ad->tx_vec_allowed = false;
3116 if (ad->tx_simple_allowed) {
3117 if (ad->tx_vec_allowed) {
3118 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3119 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3122 * since AVX frequency can be different to base
3123 * frequency, limit use of AVX2 version to later
3124 * plaforms, not all those that could theoretically
3127 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3128 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx2;
3131 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3132 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3134 dev->tx_pkt_prepare = NULL;
3136 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3137 dev->tx_pkt_burst = i40e_xmit_pkts;
3138 dev->tx_pkt_prepare = i40e_prep_pkts;
3142 void __attribute__((cold))
3143 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3145 struct i40e_adapter *ad =
3146 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3149 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3150 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3153 void __attribute__((cold))
3154 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3156 struct i40e_adapter *ad =
3157 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3162 ad->pctypes_tbl[i] = 0ULL;
3163 ad->flow_types_mask = 0ULL;
3164 ad->pctypes_mask = 0ULL;
3166 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3167 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3168 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3170 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3172 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3174 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3176 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3177 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3178 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3180 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3181 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3182 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3183 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3184 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3185 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3186 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3187 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3189 if (hw->mac.type == I40E_MAC_X722) {
3190 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3191 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3192 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3193 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3194 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3195 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3196 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3197 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3198 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3199 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3200 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3201 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3204 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3205 if (ad->pctypes_tbl[i])
3206 ad->flow_types_mask |= (1ULL << i);
3207 ad->pctypes_mask |= ad->pctypes_tbl[i];
3211 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3212 int __attribute__((weak))
3213 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3218 uint16_t __attribute__((weak))
3220 void __rte_unused *rx_queue,
3221 struct rte_mbuf __rte_unused **rx_pkts,
3222 uint16_t __rte_unused nb_pkts)
3227 uint16_t __attribute__((weak))
3228 i40e_recv_scattered_pkts_vec(
3229 void __rte_unused *rx_queue,
3230 struct rte_mbuf __rte_unused **rx_pkts,
3231 uint16_t __rte_unused nb_pkts)
3236 uint16_t __attribute__((weak))
3237 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3238 struct rte_mbuf __rte_unused **rx_pkts,
3239 uint16_t __rte_unused nb_pkts)
3244 uint16_t __attribute__((weak))
3245 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3246 struct rte_mbuf __rte_unused **rx_pkts,
3247 uint16_t __rte_unused nb_pkts)
3252 int __attribute__((weak))
3253 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3258 int __attribute__((weak))
3259 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3264 void __attribute__((weak))
3265 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3270 uint16_t __attribute__((weak))
3271 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3272 struct rte_mbuf __rte_unused **tx_pkts,
3273 uint16_t __rte_unused nb_pkts)
3278 uint16_t __attribute__((weak))
3279 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3280 struct rte_mbuf __rte_unused **tx_pkts,
3281 uint16_t __rte_unused nb_pkts)