4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_type.h"
59 #include "i40e_ethdev.h"
60 #include "i40e_rxtx.h"
62 #define DEFAULT_TX_RS_THRESH 32
63 #define DEFAULT_TX_FREE_THRESH 32
64 #define I40E_MAX_PKT_TYPE 256
66 #define I40E_TX_MAX_BURST 32
68 #define I40E_DMA_MEM_ALIGN 4096
70 /* Base address of the HW descriptor ring should be 128B aligned. */
71 #define I40E_RING_BASE_ALIGN 128
73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
74 ETH_TXQ_FLAGS_NOOFFLOADS)
76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
78 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
82 PKT_TX_OUTER_IP_CKSUM)
84 #define I40E_TX_OFFLOAD_MASK ( \
87 PKT_TX_OUTER_IP_CKSUM | \
92 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
93 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
95 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
96 struct rte_mbuf **tx_pkts,
100 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
102 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
103 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
104 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
106 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
107 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
108 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
112 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
113 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
114 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
115 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
116 mb->vlan_tci_outer = mb->vlan_tci;
117 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
118 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
119 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
120 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
122 mb->vlan_tci_outer = 0;
125 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
126 mb->vlan_tci, mb->vlan_tci_outer);
129 /* Translate the rx descriptor status to pkt flags */
130 static inline uint64_t
131 i40e_rxd_status_to_pkt_flags(uint64_t qword)
135 /* Check if RSS_HASH */
136 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
137 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
138 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
140 /* Check if FDIR Match */
141 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
147 static inline uint64_t
148 i40e_rxd_error_to_pkt_flags(uint64_t qword)
151 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
153 #define I40E_RX_ERR_BITS 0x3f
154 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
156 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
157 flags |= PKT_RX_IP_CKSUM_BAD;
159 flags |= PKT_RX_IP_CKSUM_GOOD;
161 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
162 flags |= PKT_RX_L4_CKSUM_BAD;
164 flags |= PKT_RX_L4_CKSUM_GOOD;
166 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
167 flags |= PKT_RX_EIP_CKSUM_BAD;
172 /* Function to check and set the ieee1588 timesync index and get the
175 #ifdef RTE_LIBRTE_IEEE1588
176 static inline uint64_t
177 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
179 uint64_t pkt_flags = 0;
180 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
181 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
182 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
184 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
185 == RTE_PTYPE_L2_ETHER_TIMESYNC)
186 pkt_flags = PKT_RX_IEEE1588_PTP;
188 pkt_flags |= PKT_RX_IEEE1588_TMST;
189 mb->timesync = tsyn & 0x03;
196 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
197 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
198 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
199 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
200 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
202 static inline uint64_t
203 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
206 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
207 uint16_t flexbh, flexbl;
209 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
210 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
211 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
212 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
213 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
214 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
217 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
219 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
220 flags |= PKT_RX_FDIR_ID;
221 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
223 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
224 flags |= PKT_RX_FDIR_FLX;
226 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
228 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
229 flags |= PKT_RX_FDIR_FLX;
233 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
234 flags |= PKT_RX_FDIR_ID;
240 i40e_parse_tunneling_params(uint64_t ol_flags,
241 union i40e_tx_offload tx_offload,
242 uint32_t *cd_tunneling)
244 /* EIPT: External (outer) IP header type */
245 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
246 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
247 else if (ol_flags & PKT_TX_OUTER_IPV4)
248 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
249 else if (ol_flags & PKT_TX_OUTER_IPV6)
250 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
252 /* EIPLEN: External (outer) IP header length, in DWords */
253 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
254 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
256 /* L4TUNT: L4 Tunneling Type */
257 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
258 case PKT_TX_TUNNEL_IPIP:
259 /* for non UDP / GRE tunneling, set to 00b */
261 case PKT_TX_TUNNEL_VXLAN:
262 case PKT_TX_TUNNEL_GENEVE:
263 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
265 case PKT_TX_TUNNEL_GRE:
266 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
269 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
273 /* L4TUNLEN: L4 Tunneling Length, in Words
275 * We depend on app to set rte_mbuf.l2_len correctly.
276 * For IP in GRE it should be set to the length of the GRE
278 * for MAC in GRE or MAC in UDP it should be set to the length
279 * of the GRE or UDP headers plus the inner MAC up to including
280 * its last Ethertype.
282 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
283 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
287 i40e_txd_enable_checksum(uint64_t ol_flags,
290 union i40e_tx_offload tx_offload)
293 if (ol_flags & PKT_TX_TUNNEL_MASK)
294 *td_offset |= (tx_offload.outer_l2_len >> 1)
295 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
297 *td_offset |= (tx_offload.l2_len >> 1)
298 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
300 /* Enable L3 checksum offloads */
301 if (ol_flags & PKT_TX_IP_CKSUM) {
302 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
303 *td_offset |= (tx_offload.l3_len >> 2)
304 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
305 } else if (ol_flags & PKT_TX_IPV4) {
306 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
307 *td_offset |= (tx_offload.l3_len >> 2)
308 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
309 } else if (ol_flags & PKT_TX_IPV6) {
310 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
311 *td_offset |= (tx_offload.l3_len >> 2)
312 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
315 if (ol_flags & PKT_TX_TCP_SEG) {
316 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
317 *td_offset |= (tx_offload.l4_len >> 2)
318 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
322 /* Enable L4 checksum offloads */
323 switch (ol_flags & PKT_TX_L4_MASK) {
324 case PKT_TX_TCP_CKSUM:
325 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
326 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
327 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
329 case PKT_TX_SCTP_CKSUM:
330 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
331 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
332 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
334 case PKT_TX_UDP_CKSUM:
335 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
336 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
337 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
344 /* Construct the tx flags */
345 static inline uint64_t
346 i40e_build_ctob(uint32_t td_cmd,
351 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
352 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
353 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
354 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
355 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
359 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
361 struct i40e_tx_entry *sw_ring = txq->sw_ring;
362 volatile struct i40e_tx_desc *txd = txq->tx_ring;
363 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
364 uint16_t nb_tx_desc = txq->nb_tx_desc;
365 uint16_t desc_to_clean_to;
366 uint16_t nb_tx_to_clean;
368 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
369 if (desc_to_clean_to >= nb_tx_desc)
370 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
372 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
373 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
374 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
375 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
376 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
377 "(port=%d queue=%d)", desc_to_clean_to,
378 txq->port_id, txq->queue_id);
382 if (last_desc_cleaned > desc_to_clean_to)
383 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
386 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
389 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
391 txq->last_desc_cleaned = desc_to_clean_to;
392 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
398 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
399 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
401 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
407 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
408 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
409 "rxq->rx_free_thresh=%d, "
410 "RTE_PMD_I40E_RX_MAX_BURST=%d",
411 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
413 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
414 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
415 "rxq->rx_free_thresh=%d, "
416 "rxq->nb_rx_desc=%d",
417 rxq->rx_free_thresh, rxq->nb_rx_desc);
419 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
420 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
421 "rxq->nb_rx_desc=%d, "
422 "rxq->rx_free_thresh=%d",
423 rxq->nb_rx_desc, rxq->rx_free_thresh);
433 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
434 #define I40E_LOOK_AHEAD 8
435 #if (I40E_LOOK_AHEAD != 8)
436 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
439 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
441 volatile union i40e_rx_desc *rxdp;
442 struct i40e_rx_entry *rxep;
447 int32_t s[I40E_LOOK_AHEAD], nb_dd;
448 int32_t i, j, nb_rx = 0;
451 rxdp = &rxq->rx_ring[rxq->rx_tail];
452 rxep = &rxq->sw_ring[rxq->rx_tail];
454 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
455 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
456 I40E_RXD_QW1_STATUS_SHIFT;
458 /* Make sure there is at least 1 packet to receive */
459 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
463 * Scan LOOK_AHEAD descriptors at a time to determine which
464 * descriptors reference packets that are ready to be received.
466 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
467 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
468 /* Read desc statuses backwards to avoid race condition */
469 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
470 qword1 = rte_le_to_cpu_64(\
471 rxdp[j].wb.qword1.status_error_len);
472 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
473 I40E_RXD_QW1_STATUS_SHIFT;
478 /* Compute how many status bits were set */
479 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
480 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
484 /* Translate descriptor info to mbuf parameters */
485 for (j = 0; j < nb_dd; j++) {
487 qword1 = rte_le_to_cpu_64(\
488 rxdp[j].wb.qword1.status_error_len);
489 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
490 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
491 mb->data_len = pkt_len;
492 mb->pkt_len = pkt_len;
494 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
495 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
496 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
498 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
499 I40E_RXD_QW1_PTYPE_MASK) >>
500 I40E_RXD_QW1_PTYPE_SHIFT));
501 if (pkt_flags & PKT_RX_RSS_HASH)
502 mb->hash.rss = rte_le_to_cpu_32(\
503 rxdp[j].wb.qword0.hi_dword.rss);
504 if (pkt_flags & PKT_RX_FDIR)
505 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
507 #ifdef RTE_LIBRTE_IEEE1588
508 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
510 mb->ol_flags |= pkt_flags;
514 for (j = 0; j < I40E_LOOK_AHEAD; j++)
515 rxq->rx_stage[i + j] = rxep[j].mbuf;
517 if (nb_dd != I40E_LOOK_AHEAD)
521 /* Clear software ring entries */
522 for (i = 0; i < nb_rx; i++)
523 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
528 static inline uint16_t
529 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
530 struct rte_mbuf **rx_pkts,
534 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
536 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
538 for (i = 0; i < nb_pkts; i++)
539 rx_pkts[i] = stage[i];
541 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
542 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
548 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
550 volatile union i40e_rx_desc *rxdp;
551 struct i40e_rx_entry *rxep;
553 uint16_t alloc_idx, i;
557 /* Allocate buffers in bulk */
558 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
559 (rxq->rx_free_thresh - 1));
560 rxep = &(rxq->sw_ring[alloc_idx]);
561 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
562 rxq->rx_free_thresh);
563 if (unlikely(diag != 0)) {
564 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
568 rxdp = &rxq->rx_ring[alloc_idx];
569 for (i = 0; i < rxq->rx_free_thresh; i++) {
570 if (likely(i < (rxq->rx_free_thresh - 1)))
571 /* Prefetch next mbuf */
572 rte_prefetch0(rxep[i + 1].mbuf);
575 rte_mbuf_refcnt_set(mb, 1);
577 mb->data_off = RTE_PKTMBUF_HEADROOM;
579 mb->port = rxq->port_id;
580 dma_addr = rte_cpu_to_le_64(\
581 rte_mbuf_data_dma_addr_default(mb));
582 rxdp[i].read.hdr_addr = 0;
583 rxdp[i].read.pkt_addr = dma_addr;
586 /* Update rx tail regsiter */
588 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
590 rxq->rx_free_trigger =
591 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
592 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
593 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
598 static inline uint16_t
599 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
601 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
607 if (rxq->rx_nb_avail)
608 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
610 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
611 rxq->rx_next_avail = 0;
612 rxq->rx_nb_avail = nb_rx;
613 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
615 if (rxq->rx_tail > rxq->rx_free_trigger) {
616 if (i40e_rx_alloc_bufs(rxq) != 0) {
619 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
620 "port_id=%u, queue_id=%u",
621 rxq->port_id, rxq->queue_id);
622 rxq->rx_nb_avail = 0;
623 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
624 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
625 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
631 if (rxq->rx_tail >= rxq->nb_rx_desc)
634 if (rxq->rx_nb_avail)
635 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
641 i40e_recv_pkts_bulk_alloc(void *rx_queue,
642 struct rte_mbuf **rx_pkts,
645 uint16_t nb_rx = 0, n, count;
647 if (unlikely(nb_pkts == 0))
650 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
651 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
654 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
655 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
656 nb_rx = (uint16_t)(nb_rx + count);
657 nb_pkts = (uint16_t)(nb_pkts - count);
666 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
667 struct rte_mbuf __rte_unused **rx_pkts,
668 uint16_t __rte_unused nb_pkts)
672 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
675 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
677 struct i40e_rx_queue *rxq;
678 volatile union i40e_rx_desc *rx_ring;
679 volatile union i40e_rx_desc *rxdp;
680 union i40e_rx_desc rxd;
681 struct i40e_rx_entry *sw_ring;
682 struct i40e_rx_entry *rxe;
683 struct rte_mbuf *rxm;
684 struct rte_mbuf *nmb;
688 uint16_t rx_packet_len;
689 uint16_t rx_id, nb_hold;
696 rx_id = rxq->rx_tail;
697 rx_ring = rxq->rx_ring;
698 sw_ring = rxq->sw_ring;
700 while (nb_rx < nb_pkts) {
701 rxdp = &rx_ring[rx_id];
702 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
703 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
704 >> I40E_RXD_QW1_STATUS_SHIFT;
706 /* Check the DD bit first */
707 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
710 nmb = rte_mbuf_raw_alloc(rxq->mp);
716 rxe = &sw_ring[rx_id];
718 if (unlikely(rx_id == rxq->nb_rx_desc))
721 /* Prefetch next mbuf */
722 rte_prefetch0(sw_ring[rx_id].mbuf);
725 * When next RX descriptor is on a cache line boundary,
726 * prefetch the next 4 RX descriptors and next 8 pointers
729 if ((rx_id & 0x3) == 0) {
730 rte_prefetch0(&rx_ring[rx_id]);
731 rte_prefetch0(&sw_ring[rx_id]);
736 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
737 rxdp->read.hdr_addr = 0;
738 rxdp->read.pkt_addr = dma_addr;
740 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
741 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
743 rxm->data_off = RTE_PKTMBUF_HEADROOM;
744 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
747 rxm->pkt_len = rx_packet_len;
748 rxm->data_len = rx_packet_len;
749 rxm->port = rxq->port_id;
751 i40e_rxd_to_vlan_tci(rxm, &rxd);
752 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
753 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
755 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
756 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
757 if (pkt_flags & PKT_RX_RSS_HASH)
759 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
760 if (pkt_flags & PKT_RX_FDIR)
761 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
763 #ifdef RTE_LIBRTE_IEEE1588
764 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
766 rxm->ol_flags |= pkt_flags;
768 rx_pkts[nb_rx++] = rxm;
770 rxq->rx_tail = rx_id;
773 * If the number of free RX descriptors is greater than the RX free
774 * threshold of the queue, advance the receive tail register of queue.
775 * Update that register with the value of the last processed RX
776 * descriptor minus 1.
778 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
779 if (nb_hold > rxq->rx_free_thresh) {
780 rx_id = (uint16_t) ((rx_id == 0) ?
781 (rxq->nb_rx_desc - 1) : (rx_id - 1));
782 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
785 rxq->nb_rx_hold = nb_hold;
791 i40e_recv_scattered_pkts(void *rx_queue,
792 struct rte_mbuf **rx_pkts,
795 struct i40e_rx_queue *rxq = rx_queue;
796 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
797 volatile union i40e_rx_desc *rxdp;
798 union i40e_rx_desc rxd;
799 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
800 struct i40e_rx_entry *rxe;
801 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
802 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
803 struct rte_mbuf *nmb, *rxm;
804 uint16_t rx_id = rxq->rx_tail;
805 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
811 while (nb_rx < nb_pkts) {
812 rxdp = &rx_ring[rx_id];
813 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
814 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
815 I40E_RXD_QW1_STATUS_SHIFT;
817 /* Check the DD bit */
818 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
821 nmb = rte_mbuf_raw_alloc(rxq->mp);
826 rxe = &sw_ring[rx_id];
828 if (rx_id == rxq->nb_rx_desc)
831 /* Prefetch next mbuf */
832 rte_prefetch0(sw_ring[rx_id].mbuf);
835 * When next RX descriptor is on a cache line boundary,
836 * prefetch the next 4 RX descriptors and next 8 pointers
839 if ((rx_id & 0x3) == 0) {
840 rte_prefetch0(&rx_ring[rx_id]);
841 rte_prefetch0(&sw_ring[rx_id]);
847 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
849 /* Set data buffer address and data length of the mbuf */
850 rxdp->read.hdr_addr = 0;
851 rxdp->read.pkt_addr = dma_addr;
852 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
853 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
854 rxm->data_len = rx_packet_len;
855 rxm->data_off = RTE_PKTMBUF_HEADROOM;
858 * If this is the first buffer of the received packet, set the
859 * pointer to the first mbuf of the packet and initialize its
860 * context. Otherwise, update the total length and the number
861 * of segments of the current scattered packet, and update the
862 * pointer to the last mbuf of the current packet.
866 first_seg->nb_segs = 1;
867 first_seg->pkt_len = rx_packet_len;
870 (uint16_t)(first_seg->pkt_len +
872 first_seg->nb_segs++;
873 last_seg->next = rxm;
877 * If this is not the last buffer of the received packet,
878 * update the pointer to the last mbuf of the current scattered
879 * packet and continue to parse the RX ring.
881 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
887 * This is the last buffer of the received packet. If the CRC
888 * is not stripped by the hardware:
889 * - Subtract the CRC length from the total packet length.
890 * - If the last buffer only contains the whole CRC or a part
891 * of it, free the mbuf associated to the last buffer. If part
892 * of the CRC is also contained in the previous mbuf, subtract
893 * the length of that CRC part from the data length of the
897 if (unlikely(rxq->crc_len > 0)) {
898 first_seg->pkt_len -= ETHER_CRC_LEN;
899 if (rx_packet_len <= ETHER_CRC_LEN) {
900 rte_pktmbuf_free_seg(rxm);
901 first_seg->nb_segs--;
903 (uint16_t)(last_seg->data_len -
904 (ETHER_CRC_LEN - rx_packet_len));
905 last_seg->next = NULL;
907 rxm->data_len = (uint16_t)(rx_packet_len -
911 first_seg->port = rxq->port_id;
912 first_seg->ol_flags = 0;
913 i40e_rxd_to_vlan_tci(first_seg, &rxd);
914 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
915 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
916 first_seg->packet_type =
917 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
918 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
919 if (pkt_flags & PKT_RX_RSS_HASH)
920 first_seg->hash.rss =
921 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
922 if (pkt_flags & PKT_RX_FDIR)
923 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
925 #ifdef RTE_LIBRTE_IEEE1588
926 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
928 first_seg->ol_flags |= pkt_flags;
930 /* Prefetch data of first segment, if configured to do so. */
931 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
932 first_seg->data_off));
933 rx_pkts[nb_rx++] = first_seg;
937 /* Record index of the next RX descriptor to probe. */
938 rxq->rx_tail = rx_id;
939 rxq->pkt_first_seg = first_seg;
940 rxq->pkt_last_seg = last_seg;
943 * If the number of free RX descriptors is greater than the RX free
944 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
945 * register. Update the RDT with the value of the last processed RX
946 * descriptor minus 1, to guarantee that the RDT register is never
947 * equal to the RDH register, which creates a "full" ring situtation
948 * from the hardware point of view.
950 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
951 if (nb_hold > rxq->rx_free_thresh) {
952 rx_id = (uint16_t)(rx_id == 0 ?
953 (rxq->nb_rx_desc - 1) : (rx_id - 1));
954 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
957 rxq->nb_rx_hold = nb_hold;
962 /* Check if the context descriptor is needed for TX offloading */
963 static inline uint16_t
964 i40e_calc_context_desc(uint64_t flags)
966 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
971 #ifdef RTE_LIBRTE_IEEE1588
972 mask |= PKT_TX_IEEE1588_TMST;
975 return (flags & mask) ? 1 : 0;
978 /* set i40e TSO context descriptor */
979 static inline uint64_t
980 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
982 uint64_t ctx_desc = 0;
983 uint32_t cd_cmd, hdr_len, cd_tso_len;
985 if (!tx_offload.l4_len) {
986 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
991 * in case of non tunneling packet, the outer_l2_len and
992 * outer_l3_len must be 0.
994 hdr_len = tx_offload.outer_l2_len +
995 tx_offload.outer_l3_len +
1000 cd_cmd = I40E_TX_CTX_DESC_TSO;
1001 cd_tso_len = mbuf->pkt_len - hdr_len;
1002 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1003 ((uint64_t)cd_tso_len <<
1004 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1005 ((uint64_t)mbuf->tso_segsz <<
1006 I40E_TXD_CTX_QW1_MSS_SHIFT);
1012 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1014 struct i40e_tx_queue *txq;
1015 struct i40e_tx_entry *sw_ring;
1016 struct i40e_tx_entry *txe, *txn;
1017 volatile struct i40e_tx_desc *txd;
1018 volatile struct i40e_tx_desc *txr;
1019 struct rte_mbuf *tx_pkt;
1020 struct rte_mbuf *m_seg;
1021 uint32_t cd_tunneling_params;
1033 uint64_t buf_dma_addr;
1034 union i40e_tx_offload tx_offload = {0};
1037 sw_ring = txq->sw_ring;
1039 tx_id = txq->tx_tail;
1040 txe = &sw_ring[tx_id];
1042 /* Check if the descriptor ring needs to be cleaned. */
1043 if (txq->nb_tx_free < txq->tx_free_thresh)
1044 i40e_xmit_cleanup(txq);
1046 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1052 tx_pkt = *tx_pkts++;
1053 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1055 ol_flags = tx_pkt->ol_flags;
1056 tx_offload.l2_len = tx_pkt->l2_len;
1057 tx_offload.l3_len = tx_pkt->l3_len;
1058 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1059 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1060 tx_offload.l4_len = tx_pkt->l4_len;
1061 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1063 /* Calculate the number of context descriptors needed. */
1064 nb_ctx = i40e_calc_context_desc(ol_flags);
1067 * The number of descriptors that must be allocated for
1068 * a packet equals to the number of the segments of that
1069 * packet plus 1 context descriptor if needed.
1071 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1072 tx_last = (uint16_t)(tx_id + nb_used - 1);
1075 if (tx_last >= txq->nb_tx_desc)
1076 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1078 if (nb_used > txq->nb_tx_free) {
1079 if (i40e_xmit_cleanup(txq) != 0) {
1084 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1085 while (nb_used > txq->nb_tx_free) {
1086 if (i40e_xmit_cleanup(txq) != 0) {
1095 /* Descriptor based VLAN insertion */
1096 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1097 tx_flags |= tx_pkt->vlan_tci <<
1098 I40E_TX_FLAG_L2TAG1_SHIFT;
1099 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1100 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1101 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1102 I40E_TX_FLAG_L2TAG1_SHIFT;
1105 /* Always enable CRC offload insertion */
1106 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1108 /* Fill in tunneling parameters if necessary */
1109 cd_tunneling_params = 0;
1110 if (ol_flags & PKT_TX_TUNNEL_MASK)
1111 i40e_parse_tunneling_params(ol_flags, tx_offload,
1112 &cd_tunneling_params);
1113 /* Enable checksum offloading */
1114 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1115 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1116 &td_offset, tx_offload);
1119 /* Setup TX context descriptor if required */
1120 volatile struct i40e_tx_context_desc *ctx_txd =
1121 (volatile struct i40e_tx_context_desc *)\
1123 uint16_t cd_l2tag2 = 0;
1124 uint64_t cd_type_cmd_tso_mss =
1125 I40E_TX_DESC_DTYPE_CONTEXT;
1127 txn = &sw_ring[txe->next_id];
1128 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1129 if (txe->mbuf != NULL) {
1130 rte_pktmbuf_free_seg(txe->mbuf);
1134 /* TSO enabled means no timestamp */
1135 if (ol_flags & PKT_TX_TCP_SEG)
1136 cd_type_cmd_tso_mss |=
1137 i40e_set_tso_ctx(tx_pkt, tx_offload);
1139 #ifdef RTE_LIBRTE_IEEE1588
1140 if (ol_flags & PKT_TX_IEEE1588_TMST)
1141 cd_type_cmd_tso_mss |=
1142 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1143 I40E_TXD_CTX_QW1_CMD_SHIFT);
1147 ctx_txd->tunneling_params =
1148 rte_cpu_to_le_32(cd_tunneling_params);
1149 if (ol_flags & PKT_TX_QINQ_PKT) {
1150 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1151 cd_type_cmd_tso_mss |=
1152 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1153 I40E_TXD_CTX_QW1_CMD_SHIFT);
1155 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1156 ctx_txd->type_cmd_tso_mss =
1157 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1159 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1160 "tunneling_params: %#x;\n"
1163 "type_cmd_tso_mss: %#"PRIx64";\n",
1165 ctx_txd->tunneling_params,
1168 ctx_txd->type_cmd_tso_mss);
1170 txe->last_id = tx_last;
1171 tx_id = txe->next_id;
1178 txn = &sw_ring[txe->next_id];
1181 rte_pktmbuf_free_seg(txe->mbuf);
1184 /* Setup TX Descriptor */
1185 slen = m_seg->data_len;
1186 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1188 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1189 "buf_dma_addr: %#"PRIx64";\n"
1194 tx_pkt, tx_id, buf_dma_addr,
1195 td_cmd, td_offset, slen, td_tag);
1197 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1198 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1199 td_offset, slen, td_tag);
1200 txe->last_id = tx_last;
1201 tx_id = txe->next_id;
1203 m_seg = m_seg->next;
1204 } while (m_seg != NULL);
1206 /* The last packet data descriptor needs End Of Packet (EOP) */
1207 td_cmd |= I40E_TX_DESC_CMD_EOP;
1208 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1209 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1211 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1212 PMD_TX_FREE_LOG(DEBUG,
1213 "Setting RS bit on TXD id="
1214 "%4u (port=%d queue=%d)",
1215 tx_last, txq->port_id, txq->queue_id);
1217 td_cmd |= I40E_TX_DESC_CMD_RS;
1219 /* Update txq RS bit counters */
1220 txq->nb_tx_used = 0;
1223 txd->cmd_type_offset_bsz |=
1224 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1225 I40E_TXD_QW1_CMD_SHIFT);
1231 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1232 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1233 (unsigned) tx_id, (unsigned) nb_tx);
1235 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1236 txq->tx_tail = tx_id;
1241 static inline int __attribute__((always_inline))
1242 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1244 struct i40e_tx_entry *txep;
1247 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1248 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1249 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1252 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1254 for (i = 0; i < txq->tx_rs_thresh; i++)
1255 rte_prefetch0((txep + i)->mbuf);
1257 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1258 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1259 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1263 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1264 rte_pktmbuf_free_seg(txep->mbuf);
1269 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1270 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1271 if (txq->tx_next_dd >= txq->nb_tx_desc)
1272 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1274 return txq->tx_rs_thresh;
1277 /* Populate 4 descriptors with data from 4 mbufs */
1279 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1284 for (i = 0; i < 4; i++, txdp++, pkts++) {
1285 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1286 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1287 txdp->cmd_type_offset_bsz =
1288 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1289 (*pkts)->data_len, 0);
1293 /* Populate 1 descriptor with data from 1 mbuf */
1295 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1299 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1300 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1301 txdp->cmd_type_offset_bsz =
1302 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1303 (*pkts)->data_len, 0);
1306 /* Fill hardware descriptor ring with mbuf data */
1308 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1309 struct rte_mbuf **pkts,
1312 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1313 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1314 const int N_PER_LOOP = 4;
1315 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1316 int mainpart, leftover;
1319 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1320 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1321 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1322 for (j = 0; j < N_PER_LOOP; ++j) {
1323 (txep + i + j)->mbuf = *(pkts + i + j);
1325 tx4(txdp + i, pkts + i);
1327 if (unlikely(leftover > 0)) {
1328 for (i = 0; i < leftover; ++i) {
1329 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1330 tx1(txdp + mainpart + i, pkts + mainpart + i);
1335 static inline uint16_t
1336 tx_xmit_pkts(struct i40e_tx_queue *txq,
1337 struct rte_mbuf **tx_pkts,
1340 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1344 * Begin scanning the H/W ring for done descriptors when the number
1345 * of available descriptors drops below tx_free_thresh. For each done
1346 * descriptor, free the associated buffer.
1348 if (txq->nb_tx_free < txq->tx_free_thresh)
1349 i40e_tx_free_bufs(txq);
1351 /* Use available descriptor only */
1352 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1353 if (unlikely(!nb_pkts))
1356 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1357 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1358 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1359 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1360 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1361 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1362 I40E_TXD_QW1_CMD_SHIFT);
1363 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1367 /* Fill hardware descriptor ring with mbuf data */
1368 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1369 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1371 /* Determin if RS bit needs to be set */
1372 if (txq->tx_tail > txq->tx_next_rs) {
1373 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1374 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1375 I40E_TXD_QW1_CMD_SHIFT);
1377 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1378 if (txq->tx_next_rs >= txq->nb_tx_desc)
1379 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1382 if (txq->tx_tail >= txq->nb_tx_desc)
1385 /* Update the tx tail register */
1387 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1393 i40e_xmit_pkts_simple(void *tx_queue,
1394 struct rte_mbuf **tx_pkts,
1399 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1400 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1404 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1407 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1408 &tx_pkts[nb_tx], num);
1409 nb_tx = (uint16_t)(nb_tx + ret);
1410 nb_pkts = (uint16_t)(nb_pkts - ret);
1418 /*********************************************************************
1422 **********************************************************************/
1424 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1431 for (i = 0; i < nb_pkts; i++) {
1433 ol_flags = m->ol_flags;
1436 * m->nb_segs is uint8_t, so nb_segs is always less than
1438 * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1440 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1441 if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1442 rte_errno = -EINVAL;
1445 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1446 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1447 /* MSS outside the range (256B - 9674B) are considered
1450 rte_errno = -EINVAL;
1454 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1455 rte_errno = -ENOTSUP;
1459 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1460 ret = rte_validate_tx_offload(m);
1466 ret = rte_net_intel_cksum_prepare(m);
1476 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1477 * application used, which assume having sequential ones. But from driver's
1478 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1479 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1480 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1481 * use queue_idx from 0 to 95 to access queues, while real queue would be
1482 * different. This function will do a queue mapping to find VSI the queue
1485 static struct i40e_vsi*
1486 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1488 /* the queue in MAIN VSI range */
1489 if (queue_idx < pf->main_vsi->nb_qps)
1490 return pf->main_vsi;
1492 queue_idx -= pf->main_vsi->nb_qps;
1494 /* queue_idx is greater than VMDQ VSIs range */
1495 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1496 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1500 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1504 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1506 /* the queue in MAIN VSI range */
1507 if (queue_idx < pf->main_vsi->nb_qps)
1510 /* It's VMDQ queues */
1511 queue_idx -= pf->main_vsi->nb_qps;
1513 if (pf->nb_cfg_vmdq_vsi)
1514 return queue_idx % pf->vmdq_nb_qps;
1516 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1517 return (uint16_t)(-1);
1522 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1524 struct i40e_rx_queue *rxq;
1526 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1528 PMD_INIT_FUNC_TRACE();
1530 if (rx_queue_id < dev->data->nb_rx_queues) {
1531 rxq = dev->data->rx_queues[rx_queue_id];
1533 err = i40e_alloc_rx_queue_mbufs(rxq);
1535 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1541 /* Init the RX tail regieter. */
1542 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1544 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1547 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1550 i40e_rx_queue_release_mbufs(rxq);
1551 i40e_reset_rx_queue(rxq);
1553 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1560 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1562 struct i40e_rx_queue *rxq;
1564 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566 if (rx_queue_id < dev->data->nb_rx_queues) {
1567 rxq = dev->data->rx_queues[rx_queue_id];
1570 * rx_queue_id is queue id aplication refers to, while
1571 * rxq->reg_idx is the real queue index.
1573 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1576 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1580 i40e_rx_queue_release_mbufs(rxq);
1581 i40e_reset_rx_queue(rxq);
1582 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1589 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1592 struct i40e_tx_queue *txq;
1593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595 PMD_INIT_FUNC_TRACE();
1597 if (tx_queue_id < dev->data->nb_tx_queues) {
1598 txq = dev->data->tx_queues[tx_queue_id];
1601 * tx_queue_id is queue id aplication refers to, while
1602 * rxq->reg_idx is the real queue index.
1604 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1606 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1609 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1616 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1618 struct i40e_tx_queue *txq;
1620 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1622 if (tx_queue_id < dev->data->nb_tx_queues) {
1623 txq = dev->data->tx_queues[tx_queue_id];
1626 * tx_queue_id is queue id aplication refers to, while
1627 * txq->reg_idx is the real queue index.
1629 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1632 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1637 i40e_tx_queue_release_mbufs(txq);
1638 i40e_reset_tx_queue(txq);
1639 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1646 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1648 static const uint32_t ptypes[] = {
1649 /* refers to i40e_rxd_pkt_type_mapping() */
1651 RTE_PTYPE_L2_ETHER_TIMESYNC,
1652 RTE_PTYPE_L2_ETHER_LLDP,
1653 RTE_PTYPE_L2_ETHER_ARP,
1654 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1655 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1658 RTE_PTYPE_L4_NONFRAG,
1662 RTE_PTYPE_TUNNEL_GRENAT,
1663 RTE_PTYPE_TUNNEL_IP,
1664 RTE_PTYPE_INNER_L2_ETHER,
1665 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1666 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1667 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1668 RTE_PTYPE_INNER_L4_FRAG,
1669 RTE_PTYPE_INNER_L4_ICMP,
1670 RTE_PTYPE_INNER_L4_NONFRAG,
1671 RTE_PTYPE_INNER_L4_SCTP,
1672 RTE_PTYPE_INNER_L4_TCP,
1673 RTE_PTYPE_INNER_L4_UDP,
1677 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1678 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1679 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1681 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1682 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1683 dev->rx_pkt_burst == i40e_recv_pkts_vec)
1689 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1692 unsigned int socket_id,
1693 const struct rte_eth_rxconf *rx_conf,
1694 struct rte_mempool *mp)
1696 struct i40e_vsi *vsi;
1697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699 struct i40e_adapter *ad =
1700 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1701 struct i40e_rx_queue *rxq;
1702 const struct rte_memzone *rz;
1705 uint16_t base, bsf, tc_mapping;
1706 int use_def_burst_func = 1;
1708 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1709 struct i40e_vf *vf =
1710 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1713 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1716 PMD_DRV_LOG(ERR, "VSI not available or queue "
1717 "index exceeds the maximum");
1718 return I40E_ERR_PARAM;
1720 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1721 (nb_desc > I40E_MAX_RING_DESC) ||
1722 (nb_desc < I40E_MIN_RING_DESC)) {
1723 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1724 "invalid", nb_desc);
1725 return I40E_ERR_PARAM;
1728 /* Free memory if needed */
1729 if (dev->data->rx_queues[queue_idx]) {
1730 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1731 dev->data->rx_queues[queue_idx] = NULL;
1734 /* Allocate the rx queue data structure */
1735 rxq = rte_zmalloc_socket("i40e rx queue",
1736 sizeof(struct i40e_rx_queue),
1737 RTE_CACHE_LINE_SIZE,
1740 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1741 "rx queue data structure");
1745 rxq->nb_rx_desc = nb_desc;
1746 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1747 rxq->queue_id = queue_idx;
1748 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1749 rxq->reg_idx = queue_idx;
1750 else /* PF device */
1751 rxq->reg_idx = vsi->base_queue +
1752 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1754 rxq->port_id = dev->data->port_id;
1755 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1757 rxq->drop_en = rx_conf->rx_drop_en;
1759 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1761 /* Allocate the maximun number of RX ring hardware descriptor. */
1762 len = I40E_MAX_RING_DESC;
1764 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1766 * Allocating a little more memory because vectorized/bulk_alloc Rx
1767 * functions doesn't check boundaries each time.
1769 len += RTE_PMD_I40E_RX_MAX_BURST;
1772 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1773 I40E_DMA_MEM_ALIGN);
1775 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1776 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1778 i40e_dev_rx_queue_release(rxq);
1779 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1783 /* Zero all the descriptors in the ring. */
1784 memset(rz->addr, 0, ring_size);
1786 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1787 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1789 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1790 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1795 /* Allocate the software ring. */
1797 rte_zmalloc_socket("i40e rx sw ring",
1798 sizeof(struct i40e_rx_entry) * len,
1799 RTE_CACHE_LINE_SIZE,
1801 if (!rxq->sw_ring) {
1802 i40e_dev_rx_queue_release(rxq);
1803 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1807 i40e_reset_rx_queue(rxq);
1809 dev->data->rx_queues[queue_idx] = rxq;
1811 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1813 if (!use_def_burst_func) {
1814 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1815 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1816 "satisfied. Rx Burst Bulk Alloc function will be "
1817 "used on port=%d, queue=%d.",
1818 rxq->port_id, rxq->queue_id);
1819 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1821 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1822 "not satisfied, Scattered Rx is requested, "
1823 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1824 "not enabled on port=%d, queue=%d.",
1825 rxq->port_id, rxq->queue_id);
1826 ad->rx_bulk_alloc_allowed = false;
1829 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1830 if (!(vsi->enabled_tc & (1 << i)))
1832 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1833 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1834 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1835 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1836 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1838 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1846 i40e_dev_rx_queue_release(void *rxq)
1848 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1851 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1855 i40e_rx_queue_release_mbufs(q);
1856 rte_free(q->sw_ring);
1861 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1863 #define I40E_RXQ_SCAN_INTERVAL 4
1864 volatile union i40e_rx_desc *rxdp;
1865 struct i40e_rx_queue *rxq;
1868 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1869 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1873 rxq = dev->data->rx_queues[rx_queue_id];
1874 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1875 while ((desc < rxq->nb_rx_desc) &&
1876 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1877 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1878 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1880 * Check the DD bit of a rx descriptor of each 4 in a group,
1881 * to avoid checking too frequently and downgrading performance
1884 desc += I40E_RXQ_SCAN_INTERVAL;
1885 rxdp += I40E_RXQ_SCAN_INTERVAL;
1886 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1887 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1888 desc - rxq->nb_rx_desc]);
1895 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1897 volatile union i40e_rx_desc *rxdp;
1898 struct i40e_rx_queue *rxq = rx_queue;
1902 if (unlikely(offset >= rxq->nb_rx_desc)) {
1903 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1907 desc = rxq->rx_tail + offset;
1908 if (desc >= rxq->nb_rx_desc)
1909 desc -= rxq->nb_rx_desc;
1911 rxdp = &(rxq->rx_ring[desc]);
1913 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1914 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1915 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1921 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1924 unsigned int socket_id,
1925 const struct rte_eth_txconf *tx_conf)
1927 struct i40e_vsi *vsi;
1928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1930 struct i40e_tx_queue *txq;
1931 const struct rte_memzone *tz;
1933 uint16_t tx_rs_thresh, tx_free_thresh;
1934 uint16_t i, base, bsf, tc_mapping;
1936 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1937 struct i40e_vf *vf =
1938 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1941 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1944 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1945 "exceeds the maximum", queue_idx);
1946 return I40E_ERR_PARAM;
1949 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1950 (nb_desc > I40E_MAX_RING_DESC) ||
1951 (nb_desc < I40E_MIN_RING_DESC)) {
1952 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1953 "invalid", nb_desc);
1954 return I40E_ERR_PARAM;
1958 * The following two parameters control the setting of the RS bit on
1959 * transmit descriptors. TX descriptors will have their RS bit set
1960 * after txq->tx_rs_thresh descriptors have been used. The TX
1961 * descriptor ring will be cleaned after txq->tx_free_thresh
1962 * descriptors are used or if the number of descriptors required to
1963 * transmit a packet is greater than the number of free TX descriptors.
1965 * The following constraints must be satisfied:
1966 * - tx_rs_thresh must be greater than 0.
1967 * - tx_rs_thresh must be less than the size of the ring minus 2.
1968 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1969 * - tx_rs_thresh must be a divisor of the ring size.
1970 * - tx_free_thresh must be greater than 0.
1971 * - tx_free_thresh must be less than the size of the ring minus 3.
1973 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1974 * race condition, hence the maximum threshold constraints. When set
1975 * to zero use default values.
1977 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1978 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1979 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1980 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1981 if (tx_rs_thresh >= (nb_desc - 2)) {
1982 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1983 "number of TX descriptors minus 2. "
1984 "(tx_rs_thresh=%u port=%d queue=%d)",
1985 (unsigned int)tx_rs_thresh,
1986 (int)dev->data->port_id,
1988 return I40E_ERR_PARAM;
1990 if (tx_free_thresh >= (nb_desc - 3)) {
1991 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1992 "number of TX descriptors minus 3. "
1993 "(tx_free_thresh=%u port=%d queue=%d)",
1994 (unsigned int)tx_free_thresh,
1995 (int)dev->data->port_id,
1997 return I40E_ERR_PARAM;
1999 if (tx_rs_thresh > tx_free_thresh) {
2000 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2001 "equal to tx_free_thresh. (tx_free_thresh=%u"
2002 " tx_rs_thresh=%u port=%d queue=%d)",
2003 (unsigned int)tx_free_thresh,
2004 (unsigned int)tx_rs_thresh,
2005 (int)dev->data->port_id,
2007 return I40E_ERR_PARAM;
2009 if ((nb_desc % tx_rs_thresh) != 0) {
2010 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2011 "number of TX descriptors. (tx_rs_thresh=%u"
2012 " port=%d queue=%d)",
2013 (unsigned int)tx_rs_thresh,
2014 (int)dev->data->port_id,
2016 return I40E_ERR_PARAM;
2018 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2019 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2020 "tx_rs_thresh is greater than 1. "
2021 "(tx_rs_thresh=%u port=%d queue=%d)",
2022 (unsigned int)tx_rs_thresh,
2023 (int)dev->data->port_id,
2025 return I40E_ERR_PARAM;
2028 /* Free memory if needed. */
2029 if (dev->data->tx_queues[queue_idx]) {
2030 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2031 dev->data->tx_queues[queue_idx] = NULL;
2034 /* Allocate the TX queue data structure. */
2035 txq = rte_zmalloc_socket("i40e tx queue",
2036 sizeof(struct i40e_tx_queue),
2037 RTE_CACHE_LINE_SIZE,
2040 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2041 "tx queue structure");
2045 /* Allocate TX hardware ring descriptors. */
2046 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2047 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2048 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2049 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2051 i40e_dev_tx_queue_release(txq);
2052 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2056 txq->nb_tx_desc = nb_desc;
2057 txq->tx_rs_thresh = tx_rs_thresh;
2058 txq->tx_free_thresh = tx_free_thresh;
2059 txq->pthresh = tx_conf->tx_thresh.pthresh;
2060 txq->hthresh = tx_conf->tx_thresh.hthresh;
2061 txq->wthresh = tx_conf->tx_thresh.wthresh;
2062 txq->queue_id = queue_idx;
2063 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2064 txq->reg_idx = queue_idx;
2065 else /* PF device */
2066 txq->reg_idx = vsi->base_queue +
2067 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2069 txq->port_id = dev->data->port_id;
2070 txq->txq_flags = tx_conf->txq_flags;
2072 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2074 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2075 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2077 /* Allocate software ring */
2079 rte_zmalloc_socket("i40e tx sw ring",
2080 sizeof(struct i40e_tx_entry) * nb_desc,
2081 RTE_CACHE_LINE_SIZE,
2083 if (!txq->sw_ring) {
2084 i40e_dev_tx_queue_release(txq);
2085 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2089 i40e_reset_tx_queue(txq);
2091 dev->data->tx_queues[queue_idx] = txq;
2093 /* Use a simple TX queue without offloads or multi segs if possible */
2094 i40e_set_tx_function_flag(dev, txq);
2096 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2097 if (!(vsi->enabled_tc & (1 << i)))
2099 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2100 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2101 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2102 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2103 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2105 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2113 i40e_dev_tx_queue_release(void *txq)
2115 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2118 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2122 i40e_tx_queue_release_mbufs(q);
2123 rte_free(q->sw_ring);
2127 const struct rte_memzone *
2128 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2130 const struct rte_memzone *mz;
2132 mz = rte_memzone_lookup(name);
2136 if (rte_xen_dom0_supported())
2137 mz = rte_memzone_reserve_bounded(name, len,
2138 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2140 mz = rte_memzone_reserve_aligned(name, len,
2141 socket_id, 0, I40E_RING_BASE_ALIGN);
2146 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2150 /* SSE Vector driver has a different way of releasing mbufs. */
2151 if (rxq->rx_using_sse) {
2152 i40e_rx_queue_release_mbufs_vec(rxq);
2156 if (!rxq->sw_ring) {
2157 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2161 for (i = 0; i < rxq->nb_rx_desc; i++) {
2162 if (rxq->sw_ring[i].mbuf) {
2163 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2164 rxq->sw_ring[i].mbuf = NULL;
2167 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2168 if (rxq->rx_nb_avail == 0)
2170 for (i = 0; i < rxq->rx_nb_avail; i++) {
2171 struct rte_mbuf *mbuf;
2173 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2174 rte_pktmbuf_free_seg(mbuf);
2176 rxq->rx_nb_avail = 0;
2177 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2181 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2187 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2191 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2192 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2193 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2195 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2196 len = rxq->nb_rx_desc;
2198 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2199 ((volatile char *)rxq->rx_ring)[i] = 0;
2201 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2202 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2203 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2204 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2206 rxq->rx_nb_avail = 0;
2207 rxq->rx_next_avail = 0;
2208 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2209 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2211 rxq->nb_rx_hold = 0;
2212 rxq->pkt_first_seg = NULL;
2213 rxq->pkt_last_seg = NULL;
2215 rxq->rxrearm_start = 0;
2216 rxq->rxrearm_nb = 0;
2220 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2224 if (!txq || !txq->sw_ring) {
2225 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2229 for (i = 0; i < txq->nb_tx_desc; i++) {
2230 if (txq->sw_ring[i].mbuf) {
2231 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2232 txq->sw_ring[i].mbuf = NULL;
2238 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2240 struct i40e_tx_entry *txe;
2241 uint16_t i, prev, size;
2244 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2249 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2250 for (i = 0; i < size; i++)
2251 ((volatile char *)txq->tx_ring)[i] = 0;
2253 prev = (uint16_t)(txq->nb_tx_desc - 1);
2254 for (i = 0; i < txq->nb_tx_desc; i++) {
2255 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2257 txd->cmd_type_offset_bsz =
2258 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2261 txe[prev].next_id = i;
2265 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2266 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2269 txq->nb_tx_used = 0;
2271 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2272 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2275 /* Init the TX queue in hardware */
2277 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2279 enum i40e_status_code err = I40E_SUCCESS;
2280 struct i40e_vsi *vsi = txq->vsi;
2281 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2282 uint16_t pf_q = txq->reg_idx;
2283 struct i40e_hmc_obj_txq tx_ctx;
2286 /* clear the context structure first */
2287 memset(&tx_ctx, 0, sizeof(tx_ctx));
2288 tx_ctx.new_context = 1;
2289 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2290 tx_ctx.qlen = txq->nb_tx_desc;
2292 #ifdef RTE_LIBRTE_IEEE1588
2293 tx_ctx.timesync_ena = 1;
2295 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2296 if (vsi->type == I40E_VSI_FDIR)
2297 tx_ctx.fd_ena = TRUE;
2299 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2300 if (err != I40E_SUCCESS) {
2301 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2305 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2306 if (err != I40E_SUCCESS) {
2307 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2311 /* Now associate this queue with this PCI function */
2312 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2313 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2314 I40E_QTX_CTL_PF_INDX_MASK);
2315 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2316 I40E_WRITE_FLUSH(hw);
2318 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2324 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2326 struct i40e_rx_entry *rxe = rxq->sw_ring;
2330 for (i = 0; i < rxq->nb_rx_desc; i++) {
2331 volatile union i40e_rx_desc *rxd;
2332 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2334 if (unlikely(!mbuf)) {
2335 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2339 rte_mbuf_refcnt_set(mbuf, 1);
2341 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2343 mbuf->port = rxq->port_id;
2346 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2348 rxd = &rxq->rx_ring[i];
2349 rxd->read.pkt_addr = dma_addr;
2350 rxd->read.hdr_addr = 0;
2351 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2352 rxd->read.rsvd1 = 0;
2353 rxd->read.rsvd2 = 0;
2354 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2363 * Calculate the buffer length, and check the jumbo frame
2364 * and maximum packet length.
2367 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2369 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2370 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2371 struct rte_eth_dev_data *data = pf->dev_data;
2372 uint16_t buf_size, len;
2374 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2375 RTE_PKTMBUF_HEADROOM);
2377 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2378 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2379 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2380 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2381 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2382 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2383 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2384 rxq->hs_mode = i40e_header_split_enabled;
2386 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2388 rxq->rx_hdr_len = 0;
2389 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2390 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2391 rxq->hs_mode = i40e_header_split_none;
2395 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2396 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2397 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2398 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2399 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2400 PMD_DRV_LOG(ERR, "maximum packet length must "
2401 "be larger than %u and smaller than %u,"
2402 "as jumbo frame is enabled",
2403 (uint32_t)ETHER_MAX_LEN,
2404 (uint32_t)I40E_FRAME_SIZE_MAX);
2405 return I40E_ERR_CONFIG;
2408 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2409 rxq->max_pkt_len > ETHER_MAX_LEN) {
2410 PMD_DRV_LOG(ERR, "maximum packet length must be "
2411 "larger than %u and smaller than %u, "
2412 "as jumbo frame is disabled",
2413 (uint32_t)ETHER_MIN_LEN,
2414 (uint32_t)ETHER_MAX_LEN);
2415 return I40E_ERR_CONFIG;
2422 /* Init the RX queue in hardware */
2424 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2426 int err = I40E_SUCCESS;
2427 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2428 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2429 uint16_t pf_q = rxq->reg_idx;
2431 struct i40e_hmc_obj_rxq rx_ctx;
2433 err = i40e_rx_queue_config(rxq);
2435 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2439 /* Clear the context structure first */
2440 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2441 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2442 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2444 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2445 rx_ctx.qlen = rxq->nb_rx_desc;
2446 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2449 rx_ctx.dtype = rxq->hs_mode;
2451 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2453 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2454 rx_ctx.rxmax = rxq->max_pkt_len;
2455 rx_ctx.tphrdesc_ena = 1;
2456 rx_ctx.tphwdesc_ena = 1;
2457 rx_ctx.tphdata_ena = 1;
2458 rx_ctx.tphhead_ena = 1;
2459 rx_ctx.lrxqthresh = 2;
2460 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2462 /* showiv indicates if inner VLAN is stripped inside of tunnel
2463 * packet. When set it to 1, vlan information is stripped from
2464 * the inner header, but the hardware does not put it in the
2465 * descriptor. So set it zero by default.
2470 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2471 if (err != I40E_SUCCESS) {
2472 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2475 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2476 if (err != I40E_SUCCESS) {
2477 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2481 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2483 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2484 RTE_PKTMBUF_HEADROOM);
2486 /* Check if scattered RX needs to be used. */
2487 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2488 dev_data->scattered_rx = 1;
2491 /* Init the RX tail regieter. */
2492 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2498 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2502 PMD_INIT_FUNC_TRACE();
2504 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2505 if (!dev->data->tx_queues[i])
2507 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2508 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2511 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2512 if (!dev->data->rx_queues[i])
2514 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2515 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2520 i40e_dev_free_queues(struct rte_eth_dev *dev)
2524 PMD_INIT_FUNC_TRACE();
2526 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2527 if (!dev->data->rx_queues[i])
2529 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2530 dev->data->rx_queues[i] = NULL;
2532 dev->data->nb_rx_queues = 0;
2534 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2535 if (!dev->data->tx_queues[i])
2537 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2538 dev->data->tx_queues[i] = NULL;
2540 dev->data->nb_tx_queues = 0;
2543 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2544 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2546 enum i40e_status_code
2547 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2549 struct i40e_tx_queue *txq;
2550 const struct rte_memzone *tz = NULL;
2552 struct rte_eth_dev *dev;
2555 PMD_DRV_LOG(ERR, "PF is not available");
2556 return I40E_ERR_BAD_PTR;
2559 dev = pf->adapter->eth_dev;
2561 /* Allocate the TX queue data structure. */
2562 txq = rte_zmalloc_socket("i40e fdir tx queue",
2563 sizeof(struct i40e_tx_queue),
2564 RTE_CACHE_LINE_SIZE,
2567 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2568 "tx queue structure.");
2569 return I40E_ERR_NO_MEMORY;
2572 /* Allocate TX hardware ring descriptors. */
2573 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2574 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2576 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2577 I40E_FDIR_QUEUE_ID, ring_size,
2578 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2580 i40e_dev_tx_queue_release(txq);
2581 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2582 return I40E_ERR_NO_MEMORY;
2585 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2586 txq->queue_id = I40E_FDIR_QUEUE_ID;
2587 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2588 txq->vsi = pf->fdir.fdir_vsi;
2590 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2591 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2593 * don't need to allocate software ring and reset for the fdir
2594 * program queue just set the queue has been configured.
2599 return I40E_SUCCESS;
2602 enum i40e_status_code
2603 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2605 struct i40e_rx_queue *rxq;
2606 const struct rte_memzone *rz = NULL;
2608 struct rte_eth_dev *dev;
2611 PMD_DRV_LOG(ERR, "PF is not available");
2612 return I40E_ERR_BAD_PTR;
2615 dev = pf->adapter->eth_dev;
2617 /* Allocate the RX queue data structure. */
2618 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2619 sizeof(struct i40e_rx_queue),
2620 RTE_CACHE_LINE_SIZE,
2623 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2624 "rx queue structure.");
2625 return I40E_ERR_NO_MEMORY;
2628 /* Allocate RX hardware ring descriptors. */
2629 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2630 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2632 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2633 I40E_FDIR_QUEUE_ID, ring_size,
2634 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2636 i40e_dev_rx_queue_release(rxq);
2637 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2638 return I40E_ERR_NO_MEMORY;
2641 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2642 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2643 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2644 rxq->vsi = pf->fdir.fdir_vsi;
2646 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2647 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2650 * Don't need to allocate software ring and reset for the fdir
2651 * rx queue, just set the queue has been configured.
2656 return I40E_SUCCESS;
2660 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2661 struct rte_eth_rxq_info *qinfo)
2663 struct i40e_rx_queue *rxq;
2665 rxq = dev->data->rx_queues[queue_id];
2667 qinfo->mp = rxq->mp;
2668 qinfo->scattered_rx = dev->data->scattered_rx;
2669 qinfo->nb_desc = rxq->nb_rx_desc;
2671 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2672 qinfo->conf.rx_drop_en = rxq->drop_en;
2673 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2677 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2678 struct rte_eth_txq_info *qinfo)
2680 struct i40e_tx_queue *txq;
2682 txq = dev->data->tx_queues[queue_id];
2684 qinfo->nb_desc = txq->nb_tx_desc;
2686 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2687 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2688 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2690 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2691 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2692 qinfo->conf.txq_flags = txq->txq_flags;
2693 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2696 void __attribute__((cold))
2697 i40e_set_rx_function(struct rte_eth_dev *dev)
2699 struct i40e_adapter *ad =
2700 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2701 uint16_t rx_using_sse, i;
2702 /* In order to allow Vector Rx there are a few configuration
2703 * conditions to be met and Rx Bulk Allocation should be allowed.
2705 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2706 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2707 !ad->rx_bulk_alloc_allowed) {
2708 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2709 " Vector Rx preconditions",
2710 dev->data->port_id);
2712 ad->rx_vec_allowed = false;
2714 if (ad->rx_vec_allowed) {
2715 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2716 struct i40e_rx_queue *rxq =
2717 dev->data->rx_queues[i];
2719 if (rxq && i40e_rxq_vec_setup(rxq)) {
2720 ad->rx_vec_allowed = false;
2727 if (dev->data->scattered_rx) {
2728 /* Set the non-LRO scattered callback: there are Vector and
2729 * single allocation versions.
2731 if (ad->rx_vec_allowed) {
2732 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2733 "callback (port=%d).",
2734 dev->data->port_id);
2736 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2738 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2739 "allocation callback (port=%d).",
2740 dev->data->port_id);
2741 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2743 /* If parameters allow we are going to choose between the following
2747 * - Single buffer allocation (the simplest one)
2749 } else if (ad->rx_vec_allowed) {
2750 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2751 "burst size no less than %d (port=%d).",
2752 RTE_I40E_DESCS_PER_LOOP,
2753 dev->data->port_id);
2755 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2756 } else if (ad->rx_bulk_alloc_allowed) {
2757 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2758 "satisfied. Rx Burst Bulk Alloc function "
2759 "will be used on port=%d.",
2760 dev->data->port_id);
2762 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2764 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2765 "satisfied, or Scattered Rx is requested "
2767 dev->data->port_id);
2769 dev->rx_pkt_burst = i40e_recv_pkts;
2772 /* Propagate information about RX function choice through all queues. */
2773 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2775 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2776 dev->rx_pkt_burst == i40e_recv_pkts_vec);
2778 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2779 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2782 rxq->rx_using_sse = rx_using_sse;
2787 void __attribute__((cold))
2788 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2790 struct i40e_adapter *ad =
2791 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2793 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2794 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2795 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2796 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2797 PMD_INIT_LOG(DEBUG, "Vector tx"
2798 " can be enabled on this txq.");
2801 ad->tx_vec_allowed = false;
2804 ad->tx_simple_allowed = false;
2808 void __attribute__((cold))
2809 i40e_set_tx_function(struct rte_eth_dev *dev)
2811 struct i40e_adapter *ad =
2812 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2815 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2816 if (ad->tx_vec_allowed) {
2817 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2818 struct i40e_tx_queue *txq =
2819 dev->data->tx_queues[i];
2821 if (txq && i40e_txq_vec_setup(txq)) {
2822 ad->tx_vec_allowed = false;
2829 if (ad->tx_simple_allowed) {
2830 if (ad->tx_vec_allowed) {
2831 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2832 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2834 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2835 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2837 dev->tx_pkt_prepare = NULL;
2839 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2840 dev->tx_pkt_burst = i40e_xmit_pkts;
2841 dev->tx_pkt_prepare = i40e_prep_pkts;
2845 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2846 int __attribute__((weak))
2847 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2852 uint16_t __attribute__((weak))
2854 void __rte_unused *rx_queue,
2855 struct rte_mbuf __rte_unused **rx_pkts,
2856 uint16_t __rte_unused nb_pkts)
2861 uint16_t __attribute__((weak))
2862 i40e_recv_scattered_pkts_vec(
2863 void __rte_unused *rx_queue,
2864 struct rte_mbuf __rte_unused **rx_pkts,
2865 uint16_t __rte_unused nb_pkts)
2870 int __attribute__((weak))
2871 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2876 int __attribute__((weak))
2877 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2882 void __attribute__((weak))
2883 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2888 uint16_t __attribute__((weak))
2889 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2890 struct rte_mbuf __rte_unused **tx_pkts,
2891 uint16_t __rte_unused nb_pkts)