drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "i40e_logs.h"
  29 #include "base/i40e_prototype.h"
  30 #include "base/i40e_type.h"
  31 #include "i40e_ethdev.h"
  32 #include "i40e_rxtx.h"
  33
  34 #define DEFAULT_TX_RS_THRESH   32
  35 #define DEFAULT_TX_FREE_THRESH 32
  36
  37 #define I40E_TX_MAX_BURST  32
  38
  39 #define I40E_DMA_MEM_ALIGN 4096
  40
  41 /* Base address of the HW descriptor ring should be 128B aligned. */
  42 #define I40E_RING_BASE_ALIGN    128
  43
  44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  45
  46 #ifdef RTE_LIBRTE_IEEE1588
  47 #define I40E_TX_IEEE1588_TMST RTE_MBUF_F_TX_IEEE1588_TMST
  48 #else
  49 #define I40E_TX_IEEE1588_TMST 0
  50 #endif
  51
  52 #define I40E_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |             \
  53                 RTE_MBUF_F_TX_L4_MASK |          \
  54                 RTE_MBUF_F_TX_TCP_SEG |          \
  55                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_IPV4 |        \
  58                 RTE_MBUF_F_TX_OUTER_IPV6 |      \
  59                 RTE_MBUF_F_TX_IPV4 |            \
  60                 RTE_MBUF_F_TX_IPV6 |            \
  61                 RTE_MBUF_F_TX_IP_CKSUM |       \
  62                 RTE_MBUF_F_TX_L4_MASK |        \
  63                 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \
  64                 RTE_MBUF_F_TX_TCP_SEG |        \
  65                 RTE_MBUF_F_TX_QINQ |       \
  66                 RTE_MBUF_F_TX_VLAN |    \
  67                 RTE_MBUF_F_TX_TUNNEL_MASK |     \
  68                 RTE_MBUF_F_TX_OUTER_UDP_CKSUM | \
  69                 I40E_TX_IEEE1588_TMST)
  70
  71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  72                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  73
  74 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK (RTE_MBUF_F_TX_IPV4 | \
  75                 RTE_MBUF_F_TX_IPV6 | \
  76                 RTE_MBUF_F_TX_OUTER_IPV4 | \
  77                 RTE_MBUF_F_TX_OUTER_IPV6)
  78
  79 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
  80                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
  81
  82 static int
  83 i40e_monitor_callback(const uint64_t value,
  84                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  85 {
  86         const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
  87         /*
  88          * we expect the DD bit to be set to 1 if this descriptor was already
  89          * written to.
  90          */
  91         return (value & m) == m ? -1 : 0;
  92 }
  93
  94 int
  95 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  96 {
  97         struct i40e_rx_queue *rxq = rx_queue;
  98         volatile union i40e_rx_desc *rxdp;
  99         uint16_t desc;
 100
 101         desc = rxq->rx_tail;
 102         rxdp = &rxq->rx_ring[desc];
 103         /* watch for changes in status bit */
 104         pmc->addr = &rxdp->wb.qword1.status_error_len;
 105
 106         /* comparison callback */
 107         pmc->fn = i40e_monitor_callback;
 108
 109         /* registers are 64-bit */
 110         pmc->size = sizeof(uint64_t);
 111
 112         return 0;
 113 }
 114
 115 static inline void
 116 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 117 {
 118         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 119                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 120                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
 121                 mb->vlan_tci =
 122                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 123                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 124                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 125         } else {
 126                 mb->vlan_tci = 0;
 127         }
 128 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 129         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 130                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 131                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
 132                         RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
 133                 mb->vlan_tci_outer = mb->vlan_tci;
 134                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 135                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 136                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 137                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 138         } else {
 139                 mb->vlan_tci_outer = 0;
 140         }
 141 #endif
 142         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 143                    mb->vlan_tci, mb->vlan_tci_outer);
 144 }
 145
 146 /* Translate the rx descriptor status to pkt flags */
 147 static inline uint64_t
 148 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 149 {
 150         uint64_t flags;
 151
 152         /* Check if RSS_HASH */
 153         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 154                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 155                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
 156
 157         /* Check if FDIR Match */
 158         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 159                                                         RTE_MBUF_F_RX_FDIR : 0);
 160
 161         return flags;
 162 }
 163
 164 static inline uint64_t
 165 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 166 {
 167         uint64_t flags = 0;
 168         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 169
 170 #define I40E_RX_ERR_BITS 0x3f
 171         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 172                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
 173                 return flags;
 174         }
 175
 176         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 177                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 178         else
 179                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 180
 181         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 182                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 183         else
 184                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 185
 186         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 187                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
 188
 189         return flags;
 190 }
 191
 192 /* Function to check and set the ieee1588 timesync index and get the
 193  * appropriate flags.
 194  */
 195 #ifdef RTE_LIBRTE_IEEE1588
 196 static inline uint64_t
 197 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 198 {
 199         uint64_t pkt_flags = 0;
 200         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 201                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 202                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 203
 204         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 205                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 206                 pkt_flags = RTE_MBUF_F_RX_IEEE1588_PTP;
 207         if (tsyn & 0x04) {
 208                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
 209                 mb->timesync = tsyn & 0x03;
 210         }
 211
 212         return pkt_flags;
 213 }
 214 #endif
 215
 216 static inline uint64_t
 217 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 218 {
 219         uint64_t flags = 0;
 220 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 221         uint16_t flexbh, flexbl;
 222
 223         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 225                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 226         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 227                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 228                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 229
 230
 231         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 232                 mb->hash.fdir.hi =
 233                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 234                 flags |= RTE_MBUF_F_RX_FDIR_ID;
 235         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 236                 mb->hash.fdir.hi =
 237                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 238                 flags |= RTE_MBUF_F_RX_FDIR_FLX;
 239         }
 240         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 241                 mb->hash.fdir.lo =
 242                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 243                 flags |= RTE_MBUF_F_RX_FDIR_FLX;
 244         }
 245 #else
 246         mb->hash.fdir.hi =
 247                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 248         flags |= RTE_MBUF_F_RX_FDIR_ID;
 249 #endif
 250         return flags;
 251 }
 252
 253 static inline void
 254 i40e_parse_tunneling_params(uint64_t ol_flags,
 255                             union i40e_tx_offload tx_offload,
 256                             uint32_t *cd_tunneling)
 257 {
 258         /* EIPT: External (outer) IP header type */
 259         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
 260                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 261         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
 262                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 263         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
 264                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 265
 266         /* EIPLEN: External (outer) IP header length, in DWords */
 267         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 268                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 269
 270         /* L4TUNT: L4 Tunneling Type */
 271         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
 272         case RTE_MBUF_F_TX_TUNNEL_IPIP:
 273                 /* for non UDP / GRE tunneling, set to 00b */
 274                 break;
 275         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
 276         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
 277                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 278                 break;
 279         case RTE_MBUF_F_TX_TUNNEL_GRE:
 280                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 281                 break;
 282         default:
 283                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 284                 return;
 285         }
 286
 287         /* L4TUNLEN: L4 Tunneling Length, in Words
 288          *
 289          * We depend on app to set rte_mbuf.l2_len correctly.
 290          * For IP in GRE it should be set to the length of the GRE
 291          * header;
 292          * for MAC in GRE or MAC in UDP it should be set to the length
 293          * of the GRE or UDP headers plus the inner MAC up to including
 294          * its last Ethertype.
 295          */
 296         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 297                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 298 }
 299
 300 static inline void
 301 i40e_txd_enable_checksum(uint64_t ol_flags,
 302                         uint32_t *td_cmd,
 303                         uint32_t *td_offset,
 304                         union i40e_tx_offload tx_offload)
 305 {
 306         /* Set MACLEN */
 307         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
 308                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 309                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 310         else
 311                 *td_offset |= (tx_offload.l2_len >> 1)
 312                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 313
 314         /* Enable L3 checksum offloads */
 315         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
 316                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 317                 *td_offset |= (tx_offload.l3_len >> 2)
 318                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 319         } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
 320                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 321                 *td_offset |= (tx_offload.l3_len >> 2)
 322                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 323         } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
 324                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 325                 *td_offset |= (tx_offload.l3_len >> 2)
 326                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 327         }
 328
 329         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
 330                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 331                 *td_offset |= (tx_offload.l4_len >> 2)
 332                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 333                 return;
 334         }
 335
 336         /* Enable L4 checksum offloads */
 337         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
 338         case RTE_MBUF_F_TX_TCP_CKSUM:
 339                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 340                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 341                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 342                 break;
 343         case RTE_MBUF_F_TX_SCTP_CKSUM:
 344                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 345                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 346                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 347                 break;
 348         case RTE_MBUF_F_TX_UDP_CKSUM:
 349                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 350                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 351                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 352                 break;
 353         default:
 354                 break;
 355         }
 356 }
 357
 358 /* Construct the tx flags */
 359 static inline uint64_t
 360 i40e_build_ctob(uint32_t td_cmd,
 361                 uint32_t td_offset,
 362                 unsigned int size,
 363                 uint32_t td_tag)
 364 {
 365         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 366                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 367                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 368                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 369                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 370 }
 371
 372 static inline int
 373 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 374 {
 375         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 376         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 377         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 378         uint16_t nb_tx_desc = txq->nb_tx_desc;
 379         uint16_t desc_to_clean_to;
 380         uint16_t nb_tx_to_clean;
 381
 382         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 383         if (desc_to_clean_to >= nb_tx_desc)
 384                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 385
 386         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 387         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 388                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 389                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 390                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
 391                            "(port=%d queue=%d)", desc_to_clean_to,
 392                            txq->port_id, txq->queue_id);
 393                 return -1;
 394         }
 395
 396         if (last_desc_cleaned > desc_to_clean_to)
 397                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 398                                                         desc_to_clean_to);
 399         else
 400                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 401                                         last_desc_cleaned);
 402
 403         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 404
 405         txq->last_desc_cleaned = desc_to_clean_to;
 406         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 407
 408         return 0;
 409 }
 410
 411 static inline int
 412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 413 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 414 #else
 415 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 416 #endif
 417 {
 418         int ret = 0;
 419
 420 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 421         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 422                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 423                              "rxq->rx_free_thresh=%d, "
 424                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 425                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 426                 ret = -EINVAL;
 427         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 428                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 429                              "rxq->rx_free_thresh=%d, "
 430                              "rxq->nb_rx_desc=%d",
 431                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 432                 ret = -EINVAL;
 433         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 434                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 435                              "rxq->nb_rx_desc=%d, "
 436                              "rxq->rx_free_thresh=%d",
 437                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 438                 ret = -EINVAL;
 439         }
 440 #else
 441         ret = -EINVAL;
 442 #endif
 443
 444         return ret;
 445 }
 446
 447 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 448 #define I40E_LOOK_AHEAD 8
 449 #if (I40E_LOOK_AHEAD != 8)
 450 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 451 #endif
 452 static inline int
 453 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 454 {
 455         volatile union i40e_rx_desc *rxdp;
 456         struct i40e_rx_entry *rxep;
 457         struct rte_mbuf *mb;
 458         uint16_t pkt_len;
 459         uint64_t qword1;
 460         uint32_t rx_status;
 461         int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
 462         int32_t i, j, nb_rx = 0;
 463         uint64_t pkt_flags;
 464         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 465
 466         rxdp = &rxq->rx_ring[rxq->rx_tail];
 467         rxep = &rxq->sw_ring[rxq->rx_tail];
 468
 469         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 470         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 471                                 I40E_RXD_QW1_STATUS_SHIFT;
 472
 473         /* Make sure there is at least 1 packet to receive */
 474         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 475                 return 0;
 476
 477         /**
 478          * Scan LOOK_AHEAD descriptors at a time to determine which
 479          * descriptors reference packets that are ready to be received.
 480          */
 481         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 482                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 483                 /* Read desc statuses backwards to avoid race condition */
 484                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 485                         qword1 = rte_le_to_cpu_64(\
 486                                 rxdp[j].wb.qword1.status_error_len);
 487                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 488                                         I40E_RXD_QW1_STATUS_SHIFT;
 489                 }
 490
 491                 /* This barrier is to order loads of different words in the descriptor */
 492                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 493
 494                 /* Compute how many status bits were set */
 495                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
 496                         var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 497 #ifdef RTE_ARCH_ARM
 498                         /* For Arm platforms, only compute continuous status bits */
 499                         if (var)
 500                                 nb_dd += 1;
 501                         else
 502                                 break;
 503 #else
 504                         nb_dd += var;
 505 #endif
 506                 }
 507
 508                 nb_rx += nb_dd;
 509
 510                 /* Translate descriptor info to mbuf parameters */
 511                 for (j = 0; j < nb_dd; j++) {
 512                         mb = rxep[j].mbuf;
 513                         qword1 = rte_le_to_cpu_64(\
 514                                 rxdp[j].wb.qword1.status_error_len);
 515                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 516                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 517                         mb->data_len = pkt_len;
 518                         mb->pkt_len = pkt_len;
 519                         mb->ol_flags = 0;
 520                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 521                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 522                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 523                         mb->packet_type =
 524                                 ptype_tbl[(uint8_t)((qword1 &
 525                                 I40E_RXD_QW1_PTYPE_MASK) >>
 526                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 527                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 528                                 mb->hash.rss = rte_le_to_cpu_32(\
 529                                         rxdp[j].wb.qword0.hi_dword.rss);
 530                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 531                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 532
 533 #ifdef RTE_LIBRTE_IEEE1588
 534                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 535 #endif
 536                         mb->ol_flags |= pkt_flags;
 537
 538                 }
 539
 540                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 541                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 542
 543                 if (nb_dd != I40E_LOOK_AHEAD)
 544                         break;
 545         }
 546
 547         /* Clear software ring entries */
 548         for (i = 0; i < nb_rx; i++)
 549                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 550
 551         return nb_rx;
 552 }
 553
 554 static inline uint16_t
 555 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 556                         struct rte_mbuf **rx_pkts,
 557                         uint16_t nb_pkts)
 558 {
 559         uint16_t i;
 560         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 561
 562         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 563
 564         for (i = 0; i < nb_pkts; i++)
 565                 rx_pkts[i] = stage[i];
 566
 567         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 568         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 569
 570         return nb_pkts;
 571 }
 572
 573 static inline int
 574 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 575 {
 576         volatile union i40e_rx_desc *rxdp;
 577         struct i40e_rx_entry *rxep;
 578         struct rte_mbuf *mb;
 579         uint16_t alloc_idx, i;
 580         uint64_t dma_addr;
 581         int diag;
 582
 583         /* Allocate buffers in bulk */
 584         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 585                                 (rxq->rx_free_thresh - 1));
 586         rxep = &(rxq->sw_ring[alloc_idx]);
 587         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 588                                         rxq->rx_free_thresh);
 589         if (unlikely(diag != 0)) {
 590                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 591                 return -ENOMEM;
 592         }
 593
 594         rxdp = &rxq->rx_ring[alloc_idx];
 595         for (i = 0; i < rxq->rx_free_thresh; i++) {
 596                 if (likely(i < (rxq->rx_free_thresh - 1)))
 597                         /* Prefetch next mbuf */
 598                         rte_prefetch0(rxep[i + 1].mbuf);
 599
 600                 mb = rxep[i].mbuf;
 601                 rte_mbuf_refcnt_set(mb, 1);
 602                 mb->next = NULL;
 603                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 604                 mb->nb_segs = 1;
 605                 mb->port = rxq->port_id;
 606                 dma_addr = rte_cpu_to_le_64(\
 607                         rte_mbuf_data_iova_default(mb));
 608                 rxdp[i].read.hdr_addr = 0;
 609                 rxdp[i].read.pkt_addr = dma_addr;
 610         }
 611
 612         /* Update rx tail regsiter */
 613         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 614
 615         rxq->rx_free_trigger =
 616                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 617         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 618                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 619
 620         return 0;
 621 }
 622
 623 static inline uint16_t
 624 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 625 {
 626         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 627         struct rte_eth_dev *dev;
 628         uint16_t nb_rx = 0;
 629
 630         if (!nb_pkts)
 631                 return 0;
 632
 633         if (rxq->rx_nb_avail)
 634                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 635
 636         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 637         rxq->rx_next_avail = 0;
 638         rxq->rx_nb_avail = nb_rx;
 639         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 640
 641         if (rxq->rx_tail > rxq->rx_free_trigger) {
 642                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 643                         uint16_t i, j;
 644
 645                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 646                         dev->data->rx_mbuf_alloc_failed +=
 647                                 rxq->rx_free_thresh;
 648
 649                         rxq->rx_nb_avail = 0;
 650                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 651                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 652                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 653
 654                         return 0;
 655                 }
 656         }
 657
 658         if (rxq->rx_tail >= rxq->nb_rx_desc)
 659                 rxq->rx_tail = 0;
 660
 661         if (rxq->rx_nb_avail)
 662                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 663
 664         return 0;
 665 }
 666
 667 static uint16_t
 668 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 669                           struct rte_mbuf **rx_pkts,
 670                           uint16_t nb_pkts)
 671 {
 672         uint16_t nb_rx = 0, n, count;
 673
 674         if (unlikely(nb_pkts == 0))
 675                 return 0;
 676
 677         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 678                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 679
 680         while (nb_pkts) {
 681                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 682                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 683                 nb_rx = (uint16_t)(nb_rx + count);
 684                 nb_pkts = (uint16_t)(nb_pkts - count);
 685                 if (count < n)
 686                         break;
 687         }
 688
 689         return nb_rx;
 690 }
 691 #else
 692 static uint16_t
 693 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 694                           struct rte_mbuf __rte_unused **rx_pkts,
 695                           uint16_t __rte_unused nb_pkts)
 696 {
 697         return 0;
 698 }
 699 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 700
 701 uint16_t
 702 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 703 {
 704         struct i40e_rx_queue *rxq;
 705         volatile union i40e_rx_desc *rx_ring;
 706         volatile union i40e_rx_desc *rxdp;
 707         union i40e_rx_desc rxd;
 708         struct i40e_rx_entry *sw_ring;
 709         struct i40e_rx_entry *rxe;
 710         struct rte_eth_dev *dev;
 711         struct rte_mbuf *rxm;
 712         struct rte_mbuf *nmb;
 713         uint16_t nb_rx;
 714         uint32_t rx_status;
 715         uint64_t qword1;
 716         uint16_t rx_packet_len;
 717         uint16_t rx_id, nb_hold;
 718         uint64_t dma_addr;
 719         uint64_t pkt_flags;
 720         uint32_t *ptype_tbl;
 721
 722         nb_rx = 0;
 723         nb_hold = 0;
 724         rxq = rx_queue;
 725         rx_id = rxq->rx_tail;
 726         rx_ring = rxq->rx_ring;
 727         sw_ring = rxq->sw_ring;
 728         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 729
 730         while (nb_rx < nb_pkts) {
 731                 rxdp = &rx_ring[rx_id];
 732                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 733                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 734                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 735
 736                 /* Check the DD bit first */
 737                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 738                         break;
 739
 740                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 741                 if (unlikely(!nmb)) {
 742                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 743                         dev->data->rx_mbuf_alloc_failed++;
 744                         break;
 745                 }
 746
 747                 /**
 748                  * Use acquire fence to ensure that qword1 which includes DD
 749                  * bit is loaded before loading of other descriptor words.
 750                  */
 751                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 752
 753                 rxd = *rxdp;
 754                 nb_hold++;
 755                 rxe = &sw_ring[rx_id];
 756                 rx_id++;
 757                 if (unlikely(rx_id == rxq->nb_rx_desc))
 758                         rx_id = 0;
 759
 760                 /* Prefetch next mbuf */
 761                 rte_prefetch0(sw_ring[rx_id].mbuf);
 762
 763                 /**
 764                  * When next RX descriptor is on a cache line boundary,
 765                  * prefetch the next 4 RX descriptors and next 8 pointers
 766                  * to mbufs.
 767                  */
 768                 if ((rx_id & 0x3) == 0) {
 769                         rte_prefetch0(&rx_ring[rx_id]);
 770                         rte_prefetch0(&sw_ring[rx_id]);
 771                 }
 772                 rxm = rxe->mbuf;
 773                 rxe->mbuf = nmb;
 774                 dma_addr =
 775                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 776                 rxdp->read.hdr_addr = 0;
 777                 rxdp->read.pkt_addr = dma_addr;
 778
 779                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 780                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 781
 782                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 783                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 784                 rxm->nb_segs = 1;
 785                 rxm->next = NULL;
 786                 rxm->pkt_len = rx_packet_len;
 787                 rxm->data_len = rx_packet_len;
 788                 rxm->port = rxq->port_id;
 789                 rxm->ol_flags = 0;
 790                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 791                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 792                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 793                 rxm->packet_type =
 794                         ptype_tbl[(uint8_t)((qword1 &
 795                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 796                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 797                         rxm->hash.rss =
 798                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 799                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 800                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 801
 802 #ifdef RTE_LIBRTE_IEEE1588
 803                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 804 #endif
 805                 rxm->ol_flags |= pkt_flags;
 806
 807                 rx_pkts[nb_rx++] = rxm;
 808         }
 809         rxq->rx_tail = rx_id;
 810
 811         /**
 812          * If the number of free RX descriptors is greater than the RX free
 813          * threshold of the queue, advance the receive tail register of queue.
 814          * Update that register with the value of the last processed RX
 815          * descriptor minus 1.
 816          */
 817         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 818         if (nb_hold > rxq->rx_free_thresh) {
 819                 rx_id = (uint16_t) ((rx_id == 0) ?
 820                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 821                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 822                 nb_hold = 0;
 823         }
 824         rxq->nb_rx_hold = nb_hold;
 825
 826         return nb_rx;
 827 }
 828
 829 uint16_t
 830 i40e_recv_scattered_pkts(void *rx_queue,
 831                          struct rte_mbuf **rx_pkts,
 832                          uint16_t nb_pkts)
 833 {
 834         struct i40e_rx_queue *rxq = rx_queue;
 835         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 836         volatile union i40e_rx_desc *rxdp;
 837         union i40e_rx_desc rxd;
 838         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 839         struct i40e_rx_entry *rxe;
 840         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 841         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 842         struct rte_mbuf *nmb, *rxm;
 843         uint16_t rx_id = rxq->rx_tail;
 844         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 845         struct rte_eth_dev *dev;
 846         uint32_t rx_status;
 847         uint64_t qword1;
 848         uint64_t dma_addr;
 849         uint64_t pkt_flags;
 850         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 851
 852         while (nb_rx < nb_pkts) {
 853                 rxdp = &rx_ring[rx_id];
 854                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 855                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 856                                         I40E_RXD_QW1_STATUS_SHIFT;
 857
 858                 /* Check the DD bit */
 859                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 860                         break;
 861
 862                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 863                 if (unlikely(!nmb)) {
 864                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 865                         dev->data->rx_mbuf_alloc_failed++;
 866                         break;
 867                 }
 868
 869                 /**
 870                  * Use acquire fence to ensure that qword1 which includes DD
 871                  * bit is loaded before loading of other descriptor words.
 872                  */
 873                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 874
 875                 rxd = *rxdp;
 876                 nb_hold++;
 877                 rxe = &sw_ring[rx_id];
 878                 rx_id++;
 879                 if (rx_id == rxq->nb_rx_desc)
 880                         rx_id = 0;
 881
 882                 /* Prefetch next mbuf */
 883                 rte_prefetch0(sw_ring[rx_id].mbuf);
 884
 885                 /**
 886                  * When next RX descriptor is on a cache line boundary,
 887                  * prefetch the next 4 RX descriptors and next 8 pointers
 888                  * to mbufs.
 889                  */
 890                 if ((rx_id & 0x3) == 0) {
 891                         rte_prefetch0(&rx_ring[rx_id]);
 892                         rte_prefetch0(&sw_ring[rx_id]);
 893                 }
 894
 895                 rxm = rxe->mbuf;
 896                 rxe->mbuf = nmb;
 897                 dma_addr =
 898                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 899
 900                 /* Set data buffer address and data length of the mbuf */
 901                 rxdp->read.hdr_addr = 0;
 902                 rxdp->read.pkt_addr = dma_addr;
 903                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 904                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 905                 rxm->data_len = rx_packet_len;
 906                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 907
 908                 /**
 909                  * If this is the first buffer of the received packet, set the
 910                  * pointer to the first mbuf of the packet and initialize its
 911                  * context. Otherwise, update the total length and the number
 912                  * of segments of the current scattered packet, and update the
 913                  * pointer to the last mbuf of the current packet.
 914                  */
 915                 if (!first_seg) {
 916                         first_seg = rxm;
 917                         first_seg->nb_segs = 1;
 918                         first_seg->pkt_len = rx_packet_len;
 919                 } else {
 920                         first_seg->pkt_len =
 921                                 (uint16_t)(first_seg->pkt_len +
 922                                                 rx_packet_len);
 923                         first_seg->nb_segs++;
 924                         last_seg->next = rxm;
 925                 }
 926
 927                 /**
 928                  * If this is not the last buffer of the received packet,
 929                  * update the pointer to the last mbuf of the current scattered
 930                  * packet and continue to parse the RX ring.
 931                  */
 932                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 933                         last_seg = rxm;
 934                         continue;
 935                 }
 936
 937                 /**
 938                  * This is the last buffer of the received packet. If the CRC
 939                  * is not stripped by the hardware:
 940                  *  - Subtract the CRC length from the total packet length.
 941                  *  - If the last buffer only contains the whole CRC or a part
 942                  *  of it, free the mbuf associated to the last buffer. If part
 943                  *  of the CRC is also contained in the previous mbuf, subtract
 944                  *  the length of that CRC part from the data length of the
 945                  *  previous mbuf.
 946                  */
 947                 rxm->next = NULL;
 948                 if (unlikely(rxq->crc_len > 0)) {
 949                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 950                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 951                                 rte_pktmbuf_free_seg(rxm);
 952                                 first_seg->nb_segs--;
 953                                 last_seg->data_len =
 954                                         (uint16_t)(last_seg->data_len -
 955                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 956                                 last_seg->next = NULL;
 957                         } else
 958                                 rxm->data_len = (uint16_t)(rx_packet_len -
 959                                                         RTE_ETHER_CRC_LEN);
 960                 }
 961
 962                 first_seg->port = rxq->port_id;
 963                 first_seg->ol_flags = 0;
 964                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 965                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 966                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 967                 first_seg->packet_type =
 968                         ptype_tbl[(uint8_t)((qword1 &
 969                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 970                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 971                         first_seg->hash.rss =
 972                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 973                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 974                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 975
 976 #ifdef RTE_LIBRTE_IEEE1588
 977                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 978 #endif
 979                 first_seg->ol_flags |= pkt_flags;
 980
 981                 /* Prefetch data of first segment, if configured to do so. */
 982                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 983                         first_seg->data_off));
 984                 rx_pkts[nb_rx++] = first_seg;
 985                 first_seg = NULL;
 986         }
 987
 988         /* Record index of the next RX descriptor to probe. */
 989         rxq->rx_tail = rx_id;
 990         rxq->pkt_first_seg = first_seg;
 991         rxq->pkt_last_seg = last_seg;
 992
 993         /**
 994          * If the number of free RX descriptors is greater than the RX free
 995          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 996          * register. Update the RDT with the value of the last processed RX
 997          * descriptor minus 1, to guarantee that the RDT register is never
 998          * equal to the RDH register, which creates a "full" ring situtation
 999          * from the hardware point of view.
1000          */
1001         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1002         if (nb_hold > rxq->rx_free_thresh) {
1003                 rx_id = (uint16_t)(rx_id == 0 ?
1004                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1005                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1006                 nb_hold = 0;
1007         }
1008         rxq->nb_rx_hold = nb_hold;
1009
1010         return nb_rx;
1011 }
1012
1013 /* Check if the context descriptor is needed for TX offloading */
1014 static inline uint16_t
1015 i40e_calc_context_desc(uint64_t flags)
1016 {
1017         static uint64_t mask = RTE_MBUF_F_TX_OUTER_IP_CKSUM |
1018                 RTE_MBUF_F_TX_TCP_SEG |
1019                 RTE_MBUF_F_TX_QINQ |
1020                 RTE_MBUF_F_TX_TUNNEL_MASK;
1021
1022 #ifdef RTE_LIBRTE_IEEE1588
1023         mask |= RTE_MBUF_F_TX_IEEE1588_TMST;
1024 #endif
1025
1026         return (flags & mask) ? 1 : 0;
1027 }
1028
1029 /* set i40e TSO context descriptor */
1030 static inline uint64_t
1031 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1032 {
1033         uint64_t ctx_desc = 0;
1034         uint32_t cd_cmd, hdr_len, cd_tso_len;
1035
1036         if (!tx_offload.l4_len) {
1037                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1038                 return ctx_desc;
1039         }
1040
1041         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1042         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
1043                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1044
1045         cd_cmd = I40E_TX_CTX_DESC_TSO;
1046         cd_tso_len = mbuf->pkt_len - hdr_len;
1047         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1048                 ((uint64_t)cd_tso_len <<
1049                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1050                 ((uint64_t)mbuf->tso_segsz <<
1051                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1052
1053         return ctx_desc;
1054 }
1055
1056 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1057 #define I40E_MAX_DATA_PER_TXD \
1058         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1059 /* Calculate the number of TX descriptors needed for each pkt */
1060 static inline uint16_t
1061 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1062 {
1063         struct rte_mbuf *txd = tx_pkt;
1064         uint16_t count = 0;
1065
1066         while (txd != NULL) {
1067                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1068                 txd = txd->next;
1069         }
1070
1071         return count;
1072 }
1073
1074 uint16_t
1075 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1076 {
1077         struct i40e_tx_queue *txq;
1078         struct i40e_tx_entry *sw_ring;
1079         struct i40e_tx_entry *txe, *txn;
1080         volatile struct i40e_tx_desc *txd;
1081         volatile struct i40e_tx_desc *txr;
1082         struct rte_mbuf *tx_pkt;
1083         struct rte_mbuf *m_seg;
1084         uint32_t cd_tunneling_params;
1085         uint16_t tx_id;
1086         uint16_t nb_tx;
1087         uint32_t td_cmd;
1088         uint32_t td_offset;
1089         uint32_t td_tag;
1090         uint64_t ol_flags;
1091         uint16_t nb_used;
1092         uint16_t nb_ctx;
1093         uint16_t tx_last;
1094         uint16_t slen;
1095         uint64_t buf_dma_addr;
1096         union i40e_tx_offload tx_offload = {0};
1097
1098         txq = tx_queue;
1099         sw_ring = txq->sw_ring;
1100         txr = txq->tx_ring;
1101         tx_id = txq->tx_tail;
1102         txe = &sw_ring[tx_id];
1103
1104         /* Check if the descriptor ring needs to be cleaned. */
1105         if (txq->nb_tx_free < txq->tx_free_thresh)
1106                 (void)i40e_xmit_cleanup(txq);
1107
1108         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1109                 td_cmd = 0;
1110                 td_tag = 0;
1111                 td_offset = 0;
1112
1113                 tx_pkt = *tx_pkts++;
1114                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1115
1116                 ol_flags = tx_pkt->ol_flags;
1117                 tx_offload.l2_len = tx_pkt->l2_len;
1118                 tx_offload.l3_len = tx_pkt->l3_len;
1119                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1120                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1121                 tx_offload.l4_len = tx_pkt->l4_len;
1122                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1123
1124                 /* Calculate the number of context descriptors needed. */
1125                 nb_ctx = i40e_calc_context_desc(ol_flags);
1126
1127                 /**
1128                  * The number of descriptors that must be allocated for
1129                  * a packet equals to the number of the segments of that
1130                  * packet plus 1 context descriptor if needed.
1131                  * Recalculate the needed tx descs when TSO enabled in case
1132                  * the mbuf data size exceeds max data size that hw allows
1133                  * per tx desc.
1134                  */
1135                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1136                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1137                                              nb_ctx);
1138                 else
1139                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1140                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1141
1142                 /* Circular ring */
1143                 if (tx_last >= txq->nb_tx_desc)
1144                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1145
1146                 if (nb_used > txq->nb_tx_free) {
1147                         if (i40e_xmit_cleanup(txq) != 0) {
1148                                 if (nb_tx == 0)
1149                                         return 0;
1150                                 goto end_of_tx;
1151                         }
1152                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1153                                 while (nb_used > txq->nb_tx_free) {
1154                                         if (i40e_xmit_cleanup(txq) != 0) {
1155                                                 if (nb_tx == 0)
1156                                                         return 0;
1157                                                 goto end_of_tx;
1158                                         }
1159                                 }
1160                         }
1161                 }
1162
1163                 /* Descriptor based VLAN insertion */
1164                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
1165                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1166                         td_tag = tx_pkt->vlan_tci;
1167                 }
1168
1169                 /* Always enable CRC offload insertion */
1170                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1171
1172                 /* Fill in tunneling parameters if necessary */
1173                 cd_tunneling_params = 0;
1174                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
1175                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1176                                                     &cd_tunneling_params);
1177                 /* Enable checksum offloading */
1178                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1179                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1180                                                  &td_offset, tx_offload);
1181
1182                 if (nb_ctx) {
1183                         /* Setup TX context descriptor if required */
1184                         volatile struct i40e_tx_context_desc *ctx_txd =
1185                                 (volatile struct i40e_tx_context_desc *)\
1186                                                         &txr[tx_id];
1187                         uint16_t cd_l2tag2 = 0;
1188                         uint64_t cd_type_cmd_tso_mss =
1189                                 I40E_TX_DESC_DTYPE_CONTEXT;
1190
1191                         txn = &sw_ring[txe->next_id];
1192                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1193                         if (txe->mbuf != NULL) {
1194                                 rte_pktmbuf_free_seg(txe->mbuf);
1195                                 txe->mbuf = NULL;
1196                         }
1197
1198                         /* TSO enabled means no timestamp */
1199                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1200                                 cd_type_cmd_tso_mss |=
1201                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1202                         else {
1203 #ifdef RTE_LIBRTE_IEEE1588
1204                                 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
1205                                         cd_type_cmd_tso_mss |=
1206                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1207                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1208 #endif
1209                         }
1210
1211                         ctx_txd->tunneling_params =
1212                                 rte_cpu_to_le_32(cd_tunneling_params);
1213                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
1214                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1215                                 cd_type_cmd_tso_mss |=
1216                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1217                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1218                         }
1219                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1220                         ctx_txd->type_cmd_tso_mss =
1221                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1222
1223                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1224                                 "tunneling_params: %#x;\n"
1225                                 "l2tag2: %#hx;\n"
1226                                 "rsvd: %#hx;\n"
1227                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1228                                 tx_pkt, tx_id,
1229                                 ctx_txd->tunneling_params,
1230                                 ctx_txd->l2tag2,
1231                                 ctx_txd->rsvd,
1232                                 ctx_txd->type_cmd_tso_mss);
1233
1234                         txe->last_id = tx_last;
1235                         tx_id = txe->next_id;
1236                         txe = txn;
1237                 }
1238
1239                 m_seg = tx_pkt;
1240                 do {
1241                         txd = &txr[tx_id];
1242                         txn = &sw_ring[txe->next_id];
1243
1244                         if (txe->mbuf)
1245                                 rte_pktmbuf_free_seg(txe->mbuf);
1246                         txe->mbuf = m_seg;
1247
1248                         /* Setup TX Descriptor */
1249                         slen = m_seg->data_len;
1250                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1251
1252                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
1253                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1254                                 txd->buffer_addr =
1255                                         rte_cpu_to_le_64(buf_dma_addr);
1256                                 txd->cmd_type_offset_bsz =
1257                                         i40e_build_ctob(td_cmd,
1258                                         td_offset, I40E_MAX_DATA_PER_TXD,
1259                                         td_tag);
1260
1261                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1262                                 slen -= I40E_MAX_DATA_PER_TXD;
1263
1264                                 txe->last_id = tx_last;
1265                                 tx_id = txe->next_id;
1266                                 txe = txn;
1267                                 txd = &txr[tx_id];
1268                                 txn = &sw_ring[txe->next_id];
1269                         }
1270                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1271                                 "buf_dma_addr: %#"PRIx64";\n"
1272                                 "td_cmd: %#x;\n"
1273                                 "td_offset: %#x;\n"
1274                                 "td_len: %u;\n"
1275                                 "td_tag: %#x;\n",
1276                                 tx_pkt, tx_id, buf_dma_addr,
1277                                 td_cmd, td_offset, slen, td_tag);
1278
1279                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1280                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1281                                                 td_offset, slen, td_tag);
1282                         txe->last_id = tx_last;
1283                         tx_id = txe->next_id;
1284                         txe = txn;
1285                         m_seg = m_seg->next;
1286                 } while (m_seg != NULL);
1287
1288                 /* The last packet data descriptor needs End Of Packet (EOP) */
1289                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1290                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1291                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1292
1293                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1294                         PMD_TX_LOG(DEBUG,
1295                                    "Setting RS bit on TXD id="
1296                                    "%4u (port=%d queue=%d)",
1297                                    tx_last, txq->port_id, txq->queue_id);
1298
1299                         td_cmd |= I40E_TX_DESC_CMD_RS;
1300
1301                         /* Update txq RS bit counters */
1302                         txq->nb_tx_used = 0;
1303                 }
1304
1305                 txd->cmd_type_offset_bsz |=
1306                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1307                                         I40E_TXD_QW1_CMD_SHIFT);
1308         }
1309
1310 end_of_tx:
1311         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1312                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1313                    (unsigned) tx_id, (unsigned) nb_tx);
1314
1315         rte_io_wmb();
1316         I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1317         txq->tx_tail = tx_id;
1318
1319         return nb_tx;
1320 }
1321
1322 static __rte_always_inline int
1323 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1324 {
1325         struct i40e_tx_entry *txep;
1326         uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1327         uint16_t i = 0, j = 0;
1328         struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1329         const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1330         const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1331
1332         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1333                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1334                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1335                 return 0;
1336
1337         txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1338
1339         for (i = 0; i < tx_rs_thresh; i++)
1340                 rte_prefetch0((txep + i)->mbuf);
1341
1342         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
1343                 if (k) {
1344                         for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1345                                 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1346                                         free[i] = txep->mbuf;
1347                                         txep->mbuf = NULL;
1348                                 }
1349                                 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1350                                                 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1351                         }
1352                 }
1353
1354                 if (m) {
1355                         for (i = 0; i < m; ++i, ++txep) {
1356                                 free[i] = txep->mbuf;
1357                                 txep->mbuf = NULL;
1358                         }
1359                         rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1360                 }
1361         } else {
1362                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1363                         rte_pktmbuf_free_seg(txep->mbuf);
1364                         txep->mbuf = NULL;
1365                 }
1366         }
1367
1368         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1369         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1370         if (txq->tx_next_dd >= txq->nb_tx_desc)
1371                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1372
1373         return txq->tx_rs_thresh;
1374 }
1375
1376 /* Populate 4 descriptors with data from 4 mbufs */
1377 static inline void
1378 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1379 {
1380         uint64_t dma_addr;
1381         uint32_t i;
1382
1383         for (i = 0; i < 4; i++, txdp++, pkts++) {
1384                 dma_addr = rte_mbuf_data_iova(*pkts);
1385                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1386                 txdp->cmd_type_offset_bsz =
1387                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1388                                         (*pkts)->data_len, 0);
1389         }
1390 }
1391
1392 /* Populate 1 descriptor with data from 1 mbuf */
1393 static inline void
1394 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1395 {
1396         uint64_t dma_addr;
1397
1398         dma_addr = rte_mbuf_data_iova(*pkts);
1399         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1400         txdp->cmd_type_offset_bsz =
1401                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1402                                 (*pkts)->data_len, 0);
1403 }
1404
1405 /* Fill hardware descriptor ring with mbuf data */
1406 static inline void
1407 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1408                      struct rte_mbuf **pkts,
1409                      uint16_t nb_pkts)
1410 {
1411         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1412         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1413         const int N_PER_LOOP = 4;
1414         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1415         int mainpart, leftover;
1416         int i, j;
1417
1418         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1419         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1420         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1421                 for (j = 0; j < N_PER_LOOP; ++j) {
1422                         (txep + i + j)->mbuf = *(pkts + i + j);
1423                 }
1424                 tx4(txdp + i, pkts + i);
1425         }
1426         if (unlikely(leftover > 0)) {
1427                 for (i = 0; i < leftover; ++i) {
1428                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1429                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1430                 }
1431         }
1432 }
1433
1434 static inline uint16_t
1435 tx_xmit_pkts(struct i40e_tx_queue *txq,
1436              struct rte_mbuf **tx_pkts,
1437              uint16_t nb_pkts)
1438 {
1439         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1440         uint16_t n = 0;
1441
1442         /**
1443          * Begin scanning the H/W ring for done descriptors when the number
1444          * of available descriptors drops below tx_free_thresh. For each done
1445          * descriptor, free the associated buffer.
1446          */
1447         if (txq->nb_tx_free < txq->tx_free_thresh)
1448                 i40e_tx_free_bufs(txq);
1449
1450         /* Use available descriptor only */
1451         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1452         if (unlikely(!nb_pkts))
1453                 return 0;
1454
1455         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1456         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1457                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1458                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1459                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1460                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1461                                                 I40E_TXD_QW1_CMD_SHIFT);
1462                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1463                 txq->tx_tail = 0;
1464         }
1465
1466         /* Fill hardware descriptor ring with mbuf data */
1467         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1468         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1469
1470         /* Determin if RS bit needs to be set */
1471         if (txq->tx_tail > txq->tx_next_rs) {
1472                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1473                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1474                                                 I40E_TXD_QW1_CMD_SHIFT);
1475                 txq->tx_next_rs =
1476                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1477                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1478                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1479         }
1480
1481         if (txq->tx_tail >= txq->nb_tx_desc)
1482                 txq->tx_tail = 0;
1483
1484         /* Update the tx tail register */
1485         I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1486
1487         return nb_pkts;
1488 }
1489
1490 static uint16_t
1491 i40e_xmit_pkts_simple(void *tx_queue,
1492                       struct rte_mbuf **tx_pkts,
1493                       uint16_t nb_pkts)
1494 {
1495         uint16_t nb_tx = 0;
1496
1497         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1498                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1499                                                 tx_pkts, nb_pkts);
1500
1501         while (nb_pkts) {
1502                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1503                                                 I40E_TX_MAX_BURST);
1504
1505                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1506                                                 &tx_pkts[nb_tx], num);
1507                 nb_tx = (uint16_t)(nb_tx + ret);
1508                 nb_pkts = (uint16_t)(nb_pkts - ret);
1509                 if (ret < num)
1510                         break;
1511         }
1512
1513         return nb_tx;
1514 }
1515
1516 static uint16_t
1517 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1518                    uint16_t nb_pkts)
1519 {
1520         uint16_t nb_tx = 0;
1521         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1522
1523         while (nb_pkts) {
1524                 uint16_t ret, num;
1525
1526                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1527                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1528                                                 num);
1529                 nb_tx += ret;
1530                 nb_pkts -= ret;
1531                 if (ret < num)
1532                         break;
1533         }
1534
1535         return nb_tx;
1536 }
1537
1538 /*********************************************************************
1539  *
1540  *  TX simple prep functions
1541  *
1542  **********************************************************************/
1543 uint16_t
1544 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1545                       uint16_t nb_pkts)
1546 {
1547         int i;
1548         uint64_t ol_flags;
1549         struct rte_mbuf *m;
1550
1551         for (i = 0; i < nb_pkts; i++) {
1552                 m = tx_pkts[i];
1553                 ol_flags = m->ol_flags;
1554
1555                 if (m->nb_segs != 1) {
1556                         rte_errno = EINVAL;
1557                         return i;
1558                 }
1559
1560                 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1561                         rte_errno = ENOTSUP;
1562                         return i;
1563                 }
1564
1565                 /* check the size of packet */
1566                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1567                     m->pkt_len > I40E_FRAME_SIZE_MAX) {
1568                         rte_errno = EINVAL;
1569                         return i;
1570                 }
1571         }
1572         return i;
1573 }
1574
1575 /*********************************************************************
1576  *
1577  *  TX prep functions
1578  *
1579  **********************************************************************/
1580 uint16_t
1581 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1582                 uint16_t nb_pkts)
1583 {
1584         int i, ret;
1585         uint64_t ol_flags;
1586         struct rte_mbuf *m;
1587
1588         for (i = 0; i < nb_pkts; i++) {
1589                 m = tx_pkts[i];
1590                 ol_flags = m->ol_flags;
1591
1592                 /* Check for m->nb_segs to not exceed the limits. */
1593                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
1594                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1595                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1596                                 rte_errno = EINVAL;
1597                                 return i;
1598                         }
1599                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1600                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1601                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1602                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1603                         /* MSS outside the range (256B - 9674B) are considered
1604                          * malicious
1605                          */
1606                         rte_errno = EINVAL;
1607                         return i;
1608                 }
1609
1610                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1611                         rte_errno = ENOTSUP;
1612                         return i;
1613                 }
1614
1615                 /* check the size of packet */
1616                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1617                         rte_errno = EINVAL;
1618                         return i;
1619                 }
1620
1621 #ifdef RTE_ETHDEV_DEBUG_TX
1622                 ret = rte_validate_tx_offload(m);
1623                 if (ret != 0) {
1624                         rte_errno = -ret;
1625                         return i;
1626                 }
1627 #endif
1628                 ret = rte_net_intel_cksum_prepare(m);
1629                 if (ret != 0) {
1630                         rte_errno = -ret;
1631                         return i;
1632                 }
1633         }
1634         return i;
1635 }
1636
1637 /*
1638  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1639  * application used, which assume having sequential ones. But from driver's
1640  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1641  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1642  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1643  * use queue_idx from 0 to 95 to access queues, while real queue would be
1644  * different. This function will do a queue mapping to find VSI the queue
1645  * belongs to.
1646  */
1647 static struct i40e_vsi*
1648 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1649 {
1650         /* the queue in MAIN VSI range */
1651         if (queue_idx < pf->main_vsi->nb_qps)
1652                 return pf->main_vsi;
1653
1654         queue_idx -= pf->main_vsi->nb_qps;
1655
1656         /* queue_idx is greater than VMDQ VSIs range */
1657         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1658                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1659                 return NULL;
1660         }
1661
1662         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1663 }
1664
1665 static uint16_t
1666 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1667 {
1668         /* the queue in MAIN VSI range */
1669         if (queue_idx < pf->main_vsi->nb_qps)
1670                 return queue_idx;
1671
1672         /* It's VMDQ queues */
1673         queue_idx -= pf->main_vsi->nb_qps;
1674
1675         if (pf->nb_cfg_vmdq_vsi)
1676                 return queue_idx % pf->vmdq_nb_qps;
1677         else {
1678                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1679                 return (uint16_t)(-1);
1680         }
1681 }
1682
1683 int
1684 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1685 {
1686         struct i40e_rx_queue *rxq;
1687         int err;
1688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689
1690         PMD_INIT_FUNC_TRACE();
1691
1692         rxq = dev->data->rx_queues[rx_queue_id];
1693         if (!rxq || !rxq->q_set) {
1694                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1695                             rx_queue_id);
1696                 return -EINVAL;
1697         }
1698
1699         if (rxq->rx_deferred_start)
1700                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1701                             rx_queue_id);
1702
1703         err = i40e_alloc_rx_queue_mbufs(rxq);
1704         if (err) {
1705                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1706                 return err;
1707         }
1708
1709         /* Init the RX tail regieter. */
1710         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1711
1712         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1713         if (err) {
1714                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1715                             rx_queue_id);
1716
1717                 i40e_rx_queue_release_mbufs(rxq);
1718                 i40e_reset_rx_queue(rxq);
1719                 return err;
1720         }
1721         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1722
1723         return 0;
1724 }
1725
1726 int
1727 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1728 {
1729         struct i40e_rx_queue *rxq;
1730         int err;
1731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732
1733         rxq = dev->data->rx_queues[rx_queue_id];
1734         if (!rxq || !rxq->q_set) {
1735                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1736                                 rx_queue_id);
1737                 return -EINVAL;
1738         }
1739
1740         /*
1741          * rx_queue_id is queue id application refers to, while
1742          * rxq->reg_idx is the real queue index.
1743          */
1744         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1745         if (err) {
1746                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1747                             rx_queue_id);
1748                 return err;
1749         }
1750         i40e_rx_queue_release_mbufs(rxq);
1751         i40e_reset_rx_queue(rxq);
1752         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1753
1754         return 0;
1755 }
1756
1757 int
1758 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1759 {
1760         int err;
1761         struct i40e_tx_queue *txq;
1762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763
1764         PMD_INIT_FUNC_TRACE();
1765
1766         txq = dev->data->tx_queues[tx_queue_id];
1767         if (!txq || !txq->q_set) {
1768                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1769                             tx_queue_id);
1770                 return -EINVAL;
1771         }
1772
1773         if (txq->tx_deferred_start)
1774                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1775                             tx_queue_id);
1776
1777         /*
1778          * tx_queue_id is queue id application refers to, while
1779          * rxq->reg_idx is the real queue index.
1780          */
1781         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1782         if (err) {
1783                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1784                             tx_queue_id);
1785                 return err;
1786         }
1787         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1788
1789         return 0;
1790 }
1791
1792 int
1793 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1794 {
1795         struct i40e_tx_queue *txq;
1796         int err;
1797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798
1799         txq = dev->data->tx_queues[tx_queue_id];
1800         if (!txq || !txq->q_set) {
1801                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1802                         tx_queue_id);
1803                 return -EINVAL;
1804         }
1805
1806         /*
1807          * tx_queue_id is queue id application refers to, while
1808          * txq->reg_idx is the real queue index.
1809          */
1810         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1811         if (err) {
1812                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1813                             tx_queue_id);
1814                 return err;
1815         }
1816
1817         i40e_tx_queue_release_mbufs(txq);
1818         i40e_reset_tx_queue(txq);
1819         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1820
1821         return 0;
1822 }
1823
1824 const uint32_t *
1825 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1826 {
1827         static const uint32_t ptypes[] = {
1828                 /* refers to i40e_rxd_pkt_type_mapping() */
1829                 RTE_PTYPE_L2_ETHER,
1830                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1831                 RTE_PTYPE_L2_ETHER_LLDP,
1832                 RTE_PTYPE_L2_ETHER_ARP,
1833                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1834                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1835                 RTE_PTYPE_L4_FRAG,
1836                 RTE_PTYPE_L4_ICMP,
1837                 RTE_PTYPE_L4_NONFRAG,
1838                 RTE_PTYPE_L4_SCTP,
1839                 RTE_PTYPE_L4_TCP,
1840                 RTE_PTYPE_L4_UDP,
1841                 RTE_PTYPE_TUNNEL_GRENAT,
1842                 RTE_PTYPE_TUNNEL_IP,
1843                 RTE_PTYPE_INNER_L2_ETHER,
1844                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1845                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1846                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1847                 RTE_PTYPE_INNER_L4_FRAG,
1848                 RTE_PTYPE_INNER_L4_ICMP,
1849                 RTE_PTYPE_INNER_L4_NONFRAG,
1850                 RTE_PTYPE_INNER_L4_SCTP,
1851                 RTE_PTYPE_INNER_L4_TCP,
1852                 RTE_PTYPE_INNER_L4_UDP,
1853                 RTE_PTYPE_UNKNOWN
1854         };
1855
1856         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1857 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1858             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1859 #endif
1860             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1861             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1862             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1863 #ifdef CC_AVX512_SUPPORT
1864             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1865             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1866 #endif
1867             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1868             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1869                 return ptypes;
1870         return NULL;
1871 }
1872
1873 static int
1874 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1875 {
1876         uint16_t i;
1877
1878         for (i = 0; i < num; i++) {
1879                 if (i != idx && queues[i])
1880                         return 0;
1881         }
1882
1883         return 1;
1884 }
1885
1886 static int
1887 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1888                                 struct i40e_rx_queue *rxq)
1889 {
1890         struct i40e_adapter *ad =
1891                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1892         int use_def_burst_func =
1893                 check_rx_burst_bulk_alloc_preconditions(rxq);
1894         uint16_t buf_size =
1895                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1896                            RTE_PKTMBUF_HEADROOM);
1897         int use_scattered_rx =
1898                 (rxq->max_pkt_len > buf_size);
1899
1900         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1901                 PMD_DRV_LOG(ERR,
1902                             "Failed to do RX queue initialization");
1903                 return -EINVAL;
1904         }
1905
1906         if (i40e_dev_first_queue(rxq->queue_id,
1907                                  dev->data->rx_queues,
1908                                  dev->data->nb_rx_queues)) {
1909                 /**
1910                  * If it is the first queue to setup,
1911                  * set all flags to default and call
1912                  * i40e_set_rx_function.
1913                  */
1914                 ad->rx_bulk_alloc_allowed = true;
1915                 ad->rx_vec_allowed = true;
1916                 dev->data->scattered_rx = use_scattered_rx;
1917                 if (use_def_burst_func)
1918                         ad->rx_bulk_alloc_allowed = false;
1919                 i40e_set_rx_function(dev);
1920                 return 0;
1921         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1922                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1923                             " number %d of queue %d isn't power of 2",
1924                             rxq->nb_rx_desc, rxq->queue_id);
1925                 return -EINVAL;
1926         }
1927
1928         /* check bulk alloc conflict */
1929         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1930                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1931                 return -EINVAL;
1932         }
1933         /* check scatterred conflict */
1934         if (!dev->data->scattered_rx && use_scattered_rx) {
1935                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1936                 return -EINVAL;
1937         }
1938         /* check vector conflict */
1939         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1940                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1941                 return -EINVAL;
1942         }
1943
1944         return 0;
1945 }
1946
1947 int
1948 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1949                         uint16_t queue_idx,
1950                         uint16_t nb_desc,
1951                         unsigned int socket_id,
1952                         const struct rte_eth_rxconf *rx_conf,
1953                         struct rte_mempool *mp)
1954 {
1955         struct i40e_adapter *ad =
1956                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1957         struct i40e_vsi *vsi;
1958         struct i40e_pf *pf = NULL;
1959         struct i40e_rx_queue *rxq;
1960         const struct rte_memzone *rz;
1961         uint32_t ring_size;
1962         uint16_t len, i;
1963         uint16_t reg_idx, base, bsf, tc_mapping;
1964         int q_offset, use_def_burst_func = 1;
1965         uint64_t offloads;
1966
1967         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1968
1969         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1970         vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1971         if (!vsi)
1972                 return -EINVAL;
1973         q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1974         if (q_offset < 0)
1975                 return -EINVAL;
1976         reg_idx = vsi->base_queue + q_offset;
1977
1978         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1979             (nb_desc > I40E_MAX_RING_DESC) ||
1980             (nb_desc < I40E_MIN_RING_DESC)) {
1981                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1982                             "invalid", nb_desc);
1983                 return -EINVAL;
1984         }
1985
1986         /* Free memory if needed */
1987         if (dev->data->rx_queues[queue_idx]) {
1988                 i40e_rx_queue_release(dev->data->rx_queues[queue_idx]);
1989                 dev->data->rx_queues[queue_idx] = NULL;
1990         }
1991
1992         /* Allocate the rx queue data structure */
1993         rxq = rte_zmalloc_socket("i40e rx queue",
1994                                  sizeof(struct i40e_rx_queue),
1995                                  RTE_CACHE_LINE_SIZE,
1996                                  socket_id);
1997         if (!rxq) {
1998                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1999                             "rx queue data structure");
2000                 return -ENOMEM;
2001         }
2002         rxq->mp = mp;
2003         rxq->nb_rx_desc = nb_desc;
2004         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2005         rxq->queue_id = queue_idx;
2006         rxq->reg_idx = reg_idx;
2007         rxq->port_id = dev->data->port_id;
2008         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2009                 rxq->crc_len = RTE_ETHER_CRC_LEN;
2010         else
2011                 rxq->crc_len = 0;
2012         rxq->drop_en = rx_conf->rx_drop_en;
2013         rxq->vsi = vsi;
2014         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2015         rxq->offloads = offloads;
2016
2017         /* Allocate the maximun number of RX ring hardware descriptor. */
2018         len = I40E_MAX_RING_DESC;
2019
2020         /**
2021          * Allocating a little more memory because vectorized/bulk_alloc Rx
2022          * functions doesn't check boundaries each time.
2023          */
2024         len += RTE_PMD_I40E_RX_MAX_BURST;
2025
2026         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2027                               I40E_DMA_MEM_ALIGN);
2028
2029         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2030                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2031         if (!rz) {
2032                 i40e_rx_queue_release(rxq);
2033                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2034                 return -ENOMEM;
2035         }
2036
2037         rxq->mz = rz;
2038         /* Zero all the descriptors in the ring. */
2039         memset(rz->addr, 0, ring_size);
2040
2041         rxq->rx_ring_phys_addr = rz->iova;
2042         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2043
2044         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2045
2046         /* Allocate the software ring. */
2047         rxq->sw_ring =
2048                 rte_zmalloc_socket("i40e rx sw ring",
2049                                    sizeof(struct i40e_rx_entry) * len,
2050                                    RTE_CACHE_LINE_SIZE,
2051                                    socket_id);
2052         if (!rxq->sw_ring) {
2053                 i40e_rx_queue_release(rxq);
2054                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2055                 return -ENOMEM;
2056         }
2057
2058         i40e_reset_rx_queue(rxq);
2059         rxq->q_set = TRUE;
2060
2061         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2062                 if (!(vsi->enabled_tc & (1 << i)))
2063                         continue;
2064                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2065                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2066                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2067                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2068                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2069
2070                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2071                         rxq->dcb_tc = i;
2072         }
2073
2074         if (dev->data->dev_started) {
2075                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2076                         i40e_rx_queue_release(rxq);
2077                         return -EINVAL;
2078                 }
2079         } else {
2080                 use_def_burst_func =
2081                         check_rx_burst_bulk_alloc_preconditions(rxq);
2082                 if (!use_def_burst_func) {
2083 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2084                         PMD_INIT_LOG(DEBUG,
2085                           "Rx Burst Bulk Alloc Preconditions are "
2086                           "satisfied. Rx Burst Bulk Alloc function will be "
2087                           "used on port=%d, queue=%d.",
2088                           rxq->port_id, rxq->queue_id);
2089 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2090                 } else {
2091                         PMD_INIT_LOG(DEBUG,
2092                           "Rx Burst Bulk Alloc Preconditions are "
2093                           "not satisfied, Scattered Rx is requested, "
2094                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2095                           "not enabled on port=%d, queue=%d.",
2096                           rxq->port_id, rxq->queue_id);
2097                         ad->rx_bulk_alloc_allowed = false;
2098                 }
2099         }
2100
2101         dev->data->rx_queues[queue_idx] = rxq;
2102         return 0;
2103 }
2104
2105 void
2106 i40e_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2107 {
2108         i40e_rx_queue_release(dev->data->rx_queues[qid]);
2109 }
2110
2111 void
2112 i40e_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2113 {
2114         i40e_tx_queue_release(dev->data->tx_queues[qid]);
2115 }
2116
2117 void
2118 i40e_rx_queue_release(void *rxq)
2119 {
2120         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2121
2122         if (!q) {
2123                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2124                 return;
2125         }
2126
2127         i40e_rx_queue_release_mbufs(q);
2128         rte_free(q->sw_ring);
2129         rte_memzone_free(q->mz);
2130         rte_free(q);
2131 }
2132
2133 uint32_t
2134 i40e_dev_rx_queue_count(void *rx_queue)
2135 {
2136 #define I40E_RXQ_SCAN_INTERVAL 4
2137         volatile union i40e_rx_desc *rxdp;
2138         struct i40e_rx_queue *rxq;
2139         uint16_t desc = 0;
2140
2141         rxq = rx_queue;
2142         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2143         while ((desc < rxq->nb_rx_desc) &&
2144                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2145                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2146                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2147                 /**
2148                  * Check the DD bit of a rx descriptor of each 4 in a group,
2149                  * to avoid checking too frequently and downgrading performance
2150                  * too much.
2151                  */
2152                 desc += I40E_RXQ_SCAN_INTERVAL;
2153                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2154                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2155                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2156                                         desc - rxq->nb_rx_desc]);
2157         }
2158
2159         return desc;
2160 }
2161
2162 int
2163 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2164 {
2165         struct i40e_rx_queue *rxq = rx_queue;
2166         volatile uint64_t *status;
2167         uint64_t mask;
2168         uint32_t desc;
2169
2170         if (unlikely(offset >= rxq->nb_rx_desc))
2171                 return -EINVAL;
2172
2173         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2174                 return RTE_ETH_RX_DESC_UNAVAIL;
2175
2176         desc = rxq->rx_tail + offset;
2177         if (desc >= rxq->nb_rx_desc)
2178                 desc -= rxq->nb_rx_desc;
2179
2180         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2181         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2182                 << I40E_RXD_QW1_STATUS_SHIFT);
2183         if (*status & mask)
2184                 return RTE_ETH_RX_DESC_DONE;
2185
2186         return RTE_ETH_RX_DESC_AVAIL;
2187 }
2188
2189 int
2190 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2191 {
2192         struct i40e_tx_queue *txq = tx_queue;
2193         volatile uint64_t *status;
2194         uint64_t mask, expect;
2195         uint32_t desc;
2196
2197         if (unlikely(offset >= txq->nb_tx_desc))
2198                 return -EINVAL;
2199
2200         desc = txq->tx_tail + offset;
2201         /* go to next desc that has the RS bit */
2202         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2203                 txq->tx_rs_thresh;
2204         if (desc >= txq->nb_tx_desc) {
2205                 desc -= txq->nb_tx_desc;
2206                 if (desc >= txq->nb_tx_desc)
2207                         desc -= txq->nb_tx_desc;
2208         }
2209
2210         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2211         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2212         expect = rte_cpu_to_le_64(
2213                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2214         if ((*status & mask) == expect)
2215                 return RTE_ETH_TX_DESC_DONE;
2216
2217         return RTE_ETH_TX_DESC_FULL;
2218 }
2219
2220 static int
2221 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2222                                 struct i40e_tx_queue *txq)
2223 {
2224         struct i40e_adapter *ad =
2225                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2226
2227         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2228                 PMD_DRV_LOG(ERR,
2229                             "Failed to do TX queue initialization");
2230                 return -EINVAL;
2231         }
2232
2233         if (i40e_dev_first_queue(txq->queue_id,
2234                                  dev->data->tx_queues,
2235                                  dev->data->nb_tx_queues)) {
2236                 /**
2237                  * If it is the first queue to setup,
2238                  * set all flags and call
2239                  * i40e_set_tx_function.
2240                  */
2241                 i40e_set_tx_function_flag(dev, txq);
2242                 i40e_set_tx_function(dev);
2243                 return 0;
2244         }
2245
2246         /* check vector conflict */
2247         if (ad->tx_vec_allowed) {
2248                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2249                     i40e_txq_vec_setup(txq)) {
2250                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2251                         return -EINVAL;
2252                 }
2253         }
2254         /* check simple tx conflict */
2255         if (ad->tx_simple_allowed) {
2256                 if ((txq->offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2257                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2258                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2259                         return -EINVAL;
2260                 }
2261         }
2262
2263         return 0;
2264 }
2265
2266 int
2267 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2268                         uint16_t queue_idx,
2269                         uint16_t nb_desc,
2270                         unsigned int socket_id,
2271                         const struct rte_eth_txconf *tx_conf)
2272 {
2273         struct i40e_vsi *vsi;
2274         struct i40e_pf *pf = NULL;
2275         struct i40e_tx_queue *txq;
2276         const struct rte_memzone *tz;
2277         uint32_t ring_size;
2278         uint16_t tx_rs_thresh, tx_free_thresh;
2279         uint16_t reg_idx, i, base, bsf, tc_mapping;
2280         int q_offset;
2281         uint64_t offloads;
2282
2283         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2284
2285         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286         vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2287         if (!vsi)
2288                 return -EINVAL;
2289         q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2290         if (q_offset < 0)
2291                 return -EINVAL;
2292         reg_idx = vsi->base_queue + q_offset;
2293
2294         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2295             (nb_desc > I40E_MAX_RING_DESC) ||
2296             (nb_desc < I40E_MIN_RING_DESC)) {
2297                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2298                             "invalid", nb_desc);
2299                 return -EINVAL;
2300         }
2301
2302         /**
2303          * The following two parameters control the setting of the RS bit on
2304          * transmit descriptors. TX descriptors will have their RS bit set
2305          * after txq->tx_rs_thresh descriptors have been used. The TX
2306          * descriptor ring will be cleaned after txq->tx_free_thresh
2307          * descriptors are used or if the number of descriptors required to
2308          * transmit a packet is greater than the number of free TX descriptors.
2309          *
2310          * The following constraints must be satisfied:
2311          *  - tx_rs_thresh must be greater than 0.
2312          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2313          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2314          *  - tx_rs_thresh must be a divisor of the ring size.
2315          *  - tx_free_thresh must be greater than 0.
2316          *  - tx_free_thresh must be less than the size of the ring minus 3.
2317          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2318          *
2319          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2320          * race condition, hence the maximum threshold constraints. When set
2321          * to zero use default values.
2322          */
2323         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2324                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2325         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2326         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2327                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2328         if (tx_conf->tx_rs_thresh > 0)
2329                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2330         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2331                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2332                                 "exceed nb_desc. (tx_rs_thresh=%u "
2333                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2334                                 (unsigned int)tx_rs_thresh,
2335                                 (unsigned int)tx_free_thresh,
2336                                 (unsigned int)nb_desc,
2337                                 (int)dev->data->port_id,
2338                                 (int)queue_idx);
2339                 return I40E_ERR_PARAM;
2340         }
2341         if (tx_rs_thresh >= (nb_desc - 2)) {
2342                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2343                              "number of TX descriptors minus 2. "
2344                              "(tx_rs_thresh=%u port=%d queue=%d)",
2345                              (unsigned int)tx_rs_thresh,
2346                              (int)dev->data->port_id,
2347                              (int)queue_idx);
2348                 return I40E_ERR_PARAM;
2349         }
2350         if (tx_free_thresh >= (nb_desc - 3)) {
2351                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2352                              "number of TX descriptors minus 3. "
2353                              "(tx_free_thresh=%u port=%d queue=%d)",
2354                              (unsigned int)tx_free_thresh,
2355                              (int)dev->data->port_id,
2356                              (int)queue_idx);
2357                 return I40E_ERR_PARAM;
2358         }
2359         if (tx_rs_thresh > tx_free_thresh) {
2360                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2361                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2362                              " tx_rs_thresh=%u port=%d queue=%d)",
2363                              (unsigned int)tx_free_thresh,
2364                              (unsigned int)tx_rs_thresh,
2365                              (int)dev->data->port_id,
2366                              (int)queue_idx);
2367                 return I40E_ERR_PARAM;
2368         }
2369         if ((nb_desc % tx_rs_thresh) != 0) {
2370                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2371                              "number of TX descriptors. (tx_rs_thresh=%u"
2372                              " port=%d queue=%d)",
2373                              (unsigned int)tx_rs_thresh,
2374                              (int)dev->data->port_id,
2375                              (int)queue_idx);
2376                 return I40E_ERR_PARAM;
2377         }
2378         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2379                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2380                              "tx_rs_thresh is greater than 1. "
2381                              "(tx_rs_thresh=%u port=%d queue=%d)",
2382                              (unsigned int)tx_rs_thresh,
2383                              (int)dev->data->port_id,
2384                              (int)queue_idx);
2385                 return I40E_ERR_PARAM;
2386         }
2387
2388         /* Free memory if needed. */
2389         if (dev->data->tx_queues[queue_idx]) {
2390                 i40e_tx_queue_release(dev->data->tx_queues[queue_idx]);
2391                 dev->data->tx_queues[queue_idx] = NULL;
2392         }
2393
2394         /* Allocate the TX queue data structure. */
2395         txq = rte_zmalloc_socket("i40e tx queue",
2396                                   sizeof(struct i40e_tx_queue),
2397                                   RTE_CACHE_LINE_SIZE,
2398                                   socket_id);
2399         if (!txq) {
2400                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2401                             "tx queue structure");
2402                 return -ENOMEM;
2403         }
2404
2405         /* Allocate TX hardware ring descriptors. */
2406         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2407         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2408         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2409                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2410         if (!tz) {
2411                 i40e_tx_queue_release(txq);
2412                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2413                 return -ENOMEM;
2414         }
2415
2416         txq->mz = tz;
2417         txq->nb_tx_desc = nb_desc;
2418         txq->tx_rs_thresh = tx_rs_thresh;
2419         txq->tx_free_thresh = tx_free_thresh;
2420         txq->pthresh = tx_conf->tx_thresh.pthresh;
2421         txq->hthresh = tx_conf->tx_thresh.hthresh;
2422         txq->wthresh = tx_conf->tx_thresh.wthresh;
2423         txq->queue_id = queue_idx;
2424         txq->reg_idx = reg_idx;
2425         txq->port_id = dev->data->port_id;
2426         txq->offloads = offloads;
2427         txq->vsi = vsi;
2428         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2429
2430         txq->tx_ring_phys_addr = tz->iova;
2431         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2432
2433         /* Allocate software ring */
2434         txq->sw_ring =
2435                 rte_zmalloc_socket("i40e tx sw ring",
2436                                    sizeof(struct i40e_tx_entry) * nb_desc,
2437                                    RTE_CACHE_LINE_SIZE,
2438                                    socket_id);
2439         if (!txq->sw_ring) {
2440                 i40e_tx_queue_release(txq);
2441                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2442                 return -ENOMEM;
2443         }
2444
2445         i40e_reset_tx_queue(txq);
2446         txq->q_set = TRUE;
2447
2448         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2449                 if (!(vsi->enabled_tc & (1 << i)))
2450                         continue;
2451                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2452                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2453                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2454                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2455                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2456
2457                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2458                         txq->dcb_tc = i;
2459         }
2460
2461         if (dev->data->dev_started) {
2462                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2463                         i40e_tx_queue_release(txq);
2464                         return -EINVAL;
2465                 }
2466         } else {
2467                 /**
2468                  * Use a simple TX queue without offloads or
2469                  * multi segs if possible
2470                  */
2471                 i40e_set_tx_function_flag(dev, txq);
2472         }
2473         dev->data->tx_queues[queue_idx] = txq;
2474
2475         return 0;
2476 }
2477
2478 void
2479 i40e_tx_queue_release(void *txq)
2480 {
2481         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2482
2483         if (!q) {
2484                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2485                 return;
2486         }
2487
2488         i40e_tx_queue_release_mbufs(q);
2489         rte_free(q->sw_ring);
2490         rte_memzone_free(q->mz);
2491         rte_free(q);
2492 }
2493
2494 const struct rte_memzone *
2495 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2496 {
2497         const struct rte_memzone *mz;
2498
2499         mz = rte_memzone_lookup(name);
2500         if (mz)
2501                 return mz;
2502
2503         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2504                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2505         return mz;
2506 }
2507
2508 void
2509 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2510 {
2511         uint16_t i;
2512
2513         /* SSE Vector driver has a different way of releasing mbufs. */
2514         if (rxq->rx_using_sse) {
2515                 i40e_rx_queue_release_mbufs_vec(rxq);
2516                 return;
2517         }
2518
2519         if (!rxq->sw_ring) {
2520                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2521                 return;
2522         }
2523
2524         for (i = 0; i < rxq->nb_rx_desc; i++) {
2525                 if (rxq->sw_ring[i].mbuf) {
2526                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2527                         rxq->sw_ring[i].mbuf = NULL;
2528                 }
2529         }
2530 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2531         if (rxq->rx_nb_avail == 0)
2532                 return;
2533         for (i = 0; i < rxq->rx_nb_avail; i++) {
2534                 struct rte_mbuf *mbuf;
2535
2536                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2537                 rte_pktmbuf_free_seg(mbuf);
2538         }
2539         rxq->rx_nb_avail = 0;
2540 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2541 }
2542
2543 void
2544 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2545 {
2546         unsigned i;
2547         uint16_t len;
2548
2549         if (!rxq) {
2550                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2551                 return;
2552         }
2553
2554 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2555         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2556                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2557         else
2558 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2559                 len = rxq->nb_rx_desc;
2560
2561         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2562                 ((volatile char *)rxq->rx_ring)[i] = 0;
2563
2564         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2565         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2566                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2567
2568 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2569         rxq->rx_nb_avail = 0;
2570         rxq->rx_next_avail = 0;
2571         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2572 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2573         rxq->rx_tail = 0;
2574         rxq->nb_rx_hold = 0;
2575
2576         if (rxq->pkt_first_seg != NULL)
2577                 rte_pktmbuf_free(rxq->pkt_first_seg);
2578
2579         rxq->pkt_first_seg = NULL;
2580         rxq->pkt_last_seg = NULL;
2581
2582         rxq->rxrearm_start = 0;
2583         rxq->rxrearm_nb = 0;
2584 }
2585
2586 void
2587 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2588 {
2589         struct rte_eth_dev *dev;
2590         uint16_t i;
2591
2592         if (!txq || !txq->sw_ring) {
2593                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2594                 return;
2595         }
2596
2597         dev = &rte_eth_devices[txq->port_id];
2598
2599         /**
2600          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2601          *  so need to free remains more carefully.
2602          */
2603 #ifdef CC_AVX512_SUPPORT
2604         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2605                 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2606
2607                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2608                 if (txq->tx_tail < i) {
2609                         for (; i < txq->nb_tx_desc; i++) {
2610                                 rte_pktmbuf_free_seg(swr[i].mbuf);
2611                                 swr[i].mbuf = NULL;
2612                         }
2613                         i = 0;
2614                 }
2615                 for (; i < txq->tx_tail; i++) {
2616                         rte_pktmbuf_free_seg(swr[i].mbuf);
2617                         swr[i].mbuf = NULL;
2618                 }
2619                 return;
2620         }
2621 #endif
2622         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2623                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2624                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2625                 if (txq->tx_tail < i) {
2626                         for (; i < txq->nb_tx_desc; i++) {
2627                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2628                                 txq->sw_ring[i].mbuf = NULL;
2629                         }
2630                         i = 0;
2631                 }
2632                 for (; i < txq->tx_tail; i++) {
2633                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2634                         txq->sw_ring[i].mbuf = NULL;
2635                 }
2636         } else {
2637                 for (i = 0; i < txq->nb_tx_desc; i++) {
2638                         if (txq->sw_ring[i].mbuf) {
2639                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2640                                 txq->sw_ring[i].mbuf = NULL;
2641                         }
2642                 }
2643         }
2644 }
2645
2646 static int
2647 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2648                         uint32_t free_cnt)
2649 {
2650         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2651         uint16_t i, tx_last, tx_id;
2652         uint16_t nb_tx_free_last;
2653         uint16_t nb_tx_to_clean;
2654         uint32_t pkt_cnt;
2655
2656         /* Start free mbuf from the next of tx_tail */
2657         tx_last = txq->tx_tail;
2658         tx_id  = swr_ring[tx_last].next_id;
2659
2660         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2661                 return 0;
2662
2663         nb_tx_to_clean = txq->nb_tx_free;
2664         nb_tx_free_last = txq->nb_tx_free;
2665         if (!free_cnt)
2666                 free_cnt = txq->nb_tx_desc;
2667
2668         /* Loop through swr_ring to count the amount of
2669          * freeable mubfs and packets.
2670          */
2671         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2672                 for (i = 0; i < nb_tx_to_clean &&
2673                         pkt_cnt < free_cnt &&
2674                         tx_id != tx_last; i++) {
2675                         if (swr_ring[tx_id].mbuf != NULL) {
2676                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2677                                 swr_ring[tx_id].mbuf = NULL;
2678
2679                                 /*
2680                                  * last segment in the packet,
2681                                  * increment packet count
2682                                  */
2683                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2684                         }
2685
2686                         tx_id = swr_ring[tx_id].next_id;
2687                 }
2688
2689                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2690                         txq->nb_tx_free || tx_id == tx_last)
2691                         break;
2692
2693                 if (pkt_cnt < free_cnt) {
2694                         if (i40e_xmit_cleanup(txq))
2695                                 break;
2696
2697                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2698                         nb_tx_free_last = txq->nb_tx_free;
2699                 }
2700         }
2701
2702         return (int)pkt_cnt;
2703 }
2704
2705 static int
2706 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2707                         uint32_t free_cnt)
2708 {
2709         int i, n, cnt;
2710
2711         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2712                 free_cnt = txq->nb_tx_desc;
2713
2714         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2715
2716         for (i = 0; i < cnt; i += n) {
2717                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2718                         break;
2719
2720                 n = i40e_tx_free_bufs(txq);
2721
2722                 if (n == 0)
2723                         break;
2724         }
2725
2726         return i;
2727 }
2728
2729 static int
2730 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2731                         uint32_t free_cnt __rte_unused)
2732 {
2733         return -ENOTSUP;
2734 }
2735 int
2736 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2737 {
2738         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2739         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2740         struct i40e_adapter *ad =
2741                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2742
2743         if (ad->tx_simple_allowed) {
2744                 if (ad->tx_vec_allowed)
2745                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2746                 else
2747                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2748         } else {
2749                 return i40e_tx_done_cleanup_full(q, free_cnt);
2750         }
2751 }
2752
2753 void
2754 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2755 {
2756         struct i40e_tx_entry *txe;
2757         uint16_t i, prev, size;
2758
2759         if (!txq) {
2760                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2761                 return;
2762         }
2763
2764         txe = txq->sw_ring;
2765         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2766         for (i = 0; i < size; i++)
2767                 ((volatile char *)txq->tx_ring)[i] = 0;
2768
2769         prev = (uint16_t)(txq->nb_tx_desc - 1);
2770         for (i = 0; i < txq->nb_tx_desc; i++) {
2771                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2772
2773                 txd->cmd_type_offset_bsz =
2774                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2775                 txe[i].mbuf =  NULL;
2776                 txe[i].last_id = i;
2777                 txe[prev].next_id = i;
2778                 prev = i;
2779         }
2780
2781         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2782         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2783
2784         txq->tx_tail = 0;
2785         txq->nb_tx_used = 0;
2786
2787         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2788         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2789 }
2790
2791 /* Init the TX queue in hardware */
2792 int
2793 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2794 {
2795         enum i40e_status_code err = I40E_SUCCESS;
2796         struct i40e_vsi *vsi = txq->vsi;
2797         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2798         uint16_t pf_q = txq->reg_idx;
2799         struct i40e_hmc_obj_txq tx_ctx;
2800         uint32_t qtx_ctl;
2801
2802         /* clear the context structure first */
2803         memset(&tx_ctx, 0, sizeof(tx_ctx));
2804         tx_ctx.new_context = 1;
2805         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2806         tx_ctx.qlen = txq->nb_tx_desc;
2807
2808 #ifdef RTE_LIBRTE_IEEE1588
2809         tx_ctx.timesync_ena = 1;
2810 #endif
2811         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2812         if (vsi->type == I40E_VSI_FDIR)
2813                 tx_ctx.fd_ena = TRUE;
2814
2815         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2816         if (err != I40E_SUCCESS) {
2817                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2818                 return err;
2819         }
2820
2821         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2822         if (err != I40E_SUCCESS) {
2823                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2824                 return err;
2825         }
2826
2827         /* Now associate this queue with this PCI function */
2828         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2829         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2830                                         I40E_QTX_CTL_PF_INDX_MASK);
2831         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2832         I40E_WRITE_FLUSH(hw);
2833
2834         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2835
2836         return err;
2837 }
2838
2839 int
2840 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2841 {
2842         struct i40e_rx_entry *rxe = rxq->sw_ring;
2843         uint64_t dma_addr;
2844         uint16_t i;
2845
2846         for (i = 0; i < rxq->nb_rx_desc; i++) {
2847                 volatile union i40e_rx_desc *rxd;
2848                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2849
2850                 if (unlikely(!mbuf)) {
2851                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2852                         return -ENOMEM;
2853                 }
2854
2855                 rte_mbuf_refcnt_set(mbuf, 1);
2856                 mbuf->next = NULL;
2857                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2858                 mbuf->nb_segs = 1;
2859                 mbuf->port = rxq->port_id;
2860
2861                 dma_addr =
2862                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2863
2864                 rxd = &rxq->rx_ring[i];
2865                 rxd->read.pkt_addr = dma_addr;
2866                 rxd->read.hdr_addr = 0;
2867 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2868                 rxd->read.rsvd1 = 0;
2869                 rxd->read.rsvd2 = 0;
2870 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2871
2872                 rxe[i].mbuf = mbuf;
2873         }
2874
2875         return 0;
2876 }
2877
2878 /*
2879  * Calculate the buffer length, and check the jumbo frame
2880  * and maximum packet length.
2881  */
2882 static int
2883 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2884 {
2885         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2886         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2887         struct rte_eth_dev_data *data = pf->dev_data;
2888         uint16_t buf_size;
2889
2890         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2891                 RTE_PKTMBUF_HEADROOM);
2892
2893         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2894                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2895         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2896                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2897                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2898                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2899                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2900                 rxq->hs_mode = i40e_header_split_enabled;
2901                 break;
2902         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2903         default:
2904                 rxq->rx_hdr_len = 0;
2905                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2906                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2907                 rxq->hs_mode = i40e_header_split_none;
2908                 break;
2909         }
2910
2911         rxq->max_pkt_len =
2912                 RTE_MIN(hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len,
2913                                 data->mtu + I40E_ETH_OVERHEAD);
2914         if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2915                 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2916                 PMD_DRV_LOG(ERR, "maximum packet length must be "
2917                             "larger than %u and smaller than %u",
2918                             (uint32_t)RTE_ETHER_MIN_LEN,
2919                             (uint32_t)I40E_FRAME_SIZE_MAX);
2920                 return I40E_ERR_CONFIG;
2921         }
2922
2923         return 0;
2924 }
2925
2926 /* Init the RX queue in hardware */
2927 int
2928 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2929 {
2930         int err = I40E_SUCCESS;
2931         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2932         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2933         uint16_t pf_q = rxq->reg_idx;
2934         uint16_t buf_size;
2935         struct i40e_hmc_obj_rxq rx_ctx;
2936
2937         err = i40e_rx_queue_config(rxq);
2938         if (err < 0) {
2939                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2940                 return err;
2941         }
2942
2943         /* Clear the context structure first */
2944         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2945         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2946         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2947
2948         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2949         rx_ctx.qlen = rxq->nb_rx_desc;
2950 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2951         rx_ctx.dsize = 1;
2952 #endif
2953         rx_ctx.dtype = rxq->hs_mode;
2954         if (rxq->hs_mode)
2955                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2956         else
2957                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2958         rx_ctx.rxmax = rxq->max_pkt_len;
2959         rx_ctx.tphrdesc_ena = 1;
2960         rx_ctx.tphwdesc_ena = 1;
2961         rx_ctx.tphdata_ena = 1;
2962         rx_ctx.tphhead_ena = 1;
2963         rx_ctx.lrxqthresh = 2;
2964         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2965         rx_ctx.l2tsel = 1;
2966         /* showiv indicates if inner VLAN is stripped inside of tunnel
2967          * packet. When set it to 1, vlan information is stripped from
2968          * the inner header, but the hardware does not put it in the
2969          * descriptor. So set it zero by default.
2970          */
2971         rx_ctx.showiv = 0;
2972         rx_ctx.prefena = 1;
2973
2974         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2975         if (err != I40E_SUCCESS) {
2976                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2977                 return err;
2978         }
2979         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2980         if (err != I40E_SUCCESS) {
2981                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2982                 return err;
2983         }
2984
2985         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2986
2987         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2988                 RTE_PKTMBUF_HEADROOM);
2989
2990         /* Check if scattered RX needs to be used. */
2991         if (rxq->max_pkt_len > buf_size)
2992                 dev_data->scattered_rx = 1;
2993
2994         /* Init the RX tail regieter. */
2995         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2996
2997         return 0;
2998 }
2999
3000 void
3001 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3002 {
3003         uint16_t i;
3004
3005         PMD_INIT_FUNC_TRACE();
3006
3007         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3008                 if (!dev->data->tx_queues[i])
3009                         continue;
3010                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3011                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3012         }
3013
3014         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3015                 if (!dev->data->rx_queues[i])
3016                         continue;
3017                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3018                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3019         }
3020 }
3021
3022 void
3023 i40e_dev_free_queues(struct rte_eth_dev *dev)
3024 {
3025         uint16_t i;
3026
3027         PMD_INIT_FUNC_TRACE();
3028
3029         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3030                 if (!dev->data->rx_queues[i])
3031                         continue;
3032                 i40e_rx_queue_release(dev->data->rx_queues[i]);
3033                 dev->data->rx_queues[i] = NULL;
3034         }
3035
3036         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3037                 if (!dev->data->tx_queues[i])
3038                         continue;
3039                 i40e_tx_queue_release(dev->data->tx_queues[i]);
3040                 dev->data->tx_queues[i] = NULL;
3041         }
3042 }
3043
3044 enum i40e_status_code
3045 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3046 {
3047         struct i40e_tx_queue *txq;
3048         const struct rte_memzone *tz = NULL;
3049         struct rte_eth_dev *dev;
3050         uint32_t ring_size;
3051
3052         if (!pf) {
3053                 PMD_DRV_LOG(ERR, "PF is not available");
3054                 return I40E_ERR_BAD_PTR;
3055         }
3056
3057         dev = &rte_eth_devices[pf->dev_data->port_id];
3058
3059         /* Allocate the TX queue data structure. */
3060         txq = rte_zmalloc_socket("i40e fdir tx queue",
3061                                   sizeof(struct i40e_tx_queue),
3062                                   RTE_CACHE_LINE_SIZE,
3063                                   SOCKET_ID_ANY);
3064         if (!txq) {
3065                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3066                                         "tx queue structure.");
3067                 return I40E_ERR_NO_MEMORY;
3068         }
3069
3070         /* Allocate TX hardware ring descriptors. */
3071         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3072         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3073
3074         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3075                                       I40E_FDIR_QUEUE_ID, ring_size,
3076                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3077         if (!tz) {
3078                 i40e_tx_queue_release(txq);
3079                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3080                 return I40E_ERR_NO_MEMORY;
3081         }
3082
3083         txq->mz = tz;
3084         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3085         txq->queue_id = I40E_FDIR_QUEUE_ID;
3086         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3087         txq->vsi = pf->fdir.fdir_vsi;
3088
3089         txq->tx_ring_phys_addr = tz->iova;
3090         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3091
3092         /*
3093          * don't need to allocate software ring and reset for the fdir
3094          * program queue just set the queue has been configured.
3095          */
3096         txq->q_set = TRUE;
3097         pf->fdir.txq = txq;
3098         pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3099
3100         return I40E_SUCCESS;
3101 }
3102
3103 enum i40e_status_code
3104 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3105 {
3106         struct i40e_rx_queue *rxq;
3107         const struct rte_memzone *rz = NULL;
3108         uint32_t ring_size;
3109         struct rte_eth_dev *dev;
3110
3111         if (!pf) {
3112                 PMD_DRV_LOG(ERR, "PF is not available");
3113                 return I40E_ERR_BAD_PTR;
3114         }
3115
3116         dev = &rte_eth_devices[pf->dev_data->port_id];
3117
3118         /* Allocate the RX queue data structure. */
3119         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3120                                   sizeof(struct i40e_rx_queue),
3121                                   RTE_CACHE_LINE_SIZE,
3122                                   SOCKET_ID_ANY);
3123         if (!rxq) {
3124                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3125                                         "rx queue structure.");
3126                 return I40E_ERR_NO_MEMORY;
3127         }
3128
3129         /* Allocate RX hardware ring descriptors. */
3130         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3131         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3132
3133         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3134                                       I40E_FDIR_QUEUE_ID, ring_size,
3135                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3136         if (!rz) {
3137                 i40e_rx_queue_release(rxq);
3138                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3139                 return I40E_ERR_NO_MEMORY;
3140         }
3141
3142         rxq->mz = rz;
3143         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3144         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3145         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3146         rxq->vsi = pf->fdir.fdir_vsi;
3147
3148         rxq->rx_ring_phys_addr = rz->iova;
3149         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3150         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3151
3152         /*
3153          * Don't need to allocate software ring and reset for the fdir
3154          * rx queue, just set the queue has been configured.
3155          */
3156         rxq->q_set = TRUE;
3157         pf->fdir.rxq = rxq;
3158
3159         return I40E_SUCCESS;
3160 }
3161
3162 void
3163 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3164         struct rte_eth_rxq_info *qinfo)
3165 {
3166         struct i40e_rx_queue *rxq;
3167
3168         rxq = dev->data->rx_queues[queue_id];
3169
3170         qinfo->mp = rxq->mp;
3171         qinfo->scattered_rx = dev->data->scattered_rx;
3172         qinfo->nb_desc = rxq->nb_rx_desc;
3173
3174         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3175         qinfo->conf.rx_drop_en = rxq->drop_en;
3176         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3177         qinfo->conf.offloads = rxq->offloads;
3178 }
3179
3180 void
3181 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3182         struct rte_eth_txq_info *qinfo)
3183 {
3184         struct i40e_tx_queue *txq;
3185
3186         txq = dev->data->tx_queues[queue_id];
3187
3188         qinfo->nb_desc = txq->nb_tx_desc;
3189
3190         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3191         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3192         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3193
3194         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3195         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3196         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3197         qinfo->conf.offloads = txq->offloads;
3198 }
3199
3200 #ifdef RTE_ARCH_X86
3201 static inline bool
3202 get_avx_supported(bool request_avx512)
3203 {
3204         if (request_avx512) {
3205                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3206                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3207                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3208 #ifdef CC_AVX512_SUPPORT
3209                         return true;
3210 #else
3211                 PMD_DRV_LOG(NOTICE,
3212                         "AVX512 is not supported in build env");
3213                 return false;
3214 #endif
3215         } else {
3216                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3217                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3218                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3219 #ifdef CC_AVX2_SUPPORT
3220                         return true;
3221 #else
3222                 PMD_DRV_LOG(NOTICE,
3223                         "AVX2 is not supported in build env");
3224                 return false;
3225 #endif
3226         }
3227
3228         return false;
3229 }
3230 #endif /* RTE_ARCH_X86 */
3231
3232
3233 void __rte_cold
3234 i40e_set_rx_function(struct rte_eth_dev *dev)
3235 {
3236         struct i40e_adapter *ad =
3237                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3238         uint16_t rx_using_sse, i;
3239         /* In order to allow Vector Rx there are a few configuration
3240          * conditions to be met and Rx Bulk Allocation should be allowed.
3241          */
3242         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3243 #ifdef RTE_ARCH_X86
3244                 ad->rx_use_avx512 = false;
3245                 ad->rx_use_avx2 = false;
3246 #endif
3247                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3248                     !ad->rx_bulk_alloc_allowed) {
3249                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3250                                      " Vector Rx preconditions",
3251                                      dev->data->port_id);
3252
3253                         ad->rx_vec_allowed = false;
3254                 }
3255                 if (ad->rx_vec_allowed) {
3256                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3257                                 struct i40e_rx_queue *rxq =
3258                                         dev->data->rx_queues[i];
3259
3260                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3261                                         ad->rx_vec_allowed = false;
3262                                         break;
3263                                 }
3264                         }
3265 #ifdef RTE_ARCH_X86
3266                         ad->rx_use_avx512 = get_avx_supported(1);
3267
3268                         if (!ad->rx_use_avx512)
3269                                 ad->rx_use_avx2 = get_avx_supported(0);
3270 #endif
3271                 }
3272         }
3273
3274         if (ad->rx_vec_allowed  &&
3275             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3276 #ifdef RTE_ARCH_X86
3277                 if (dev->data->scattered_rx) {
3278                         if (ad->rx_use_avx512) {
3279 #ifdef CC_AVX512_SUPPORT
3280                                 PMD_DRV_LOG(NOTICE,
3281                                         "Using AVX512 Vector Scattered Rx (port %d).",
3282                                         dev->data->port_id);
3283                                 dev->rx_pkt_burst =
3284                                         i40e_recv_scattered_pkts_vec_avx512;
3285 #endif
3286                         } else {
3287                                 PMD_INIT_LOG(DEBUG,
3288                                         "Using %sVector Scattered Rx (port %d).",
3289                                         ad->rx_use_avx2 ? "avx2 " : "",
3290                                         dev->data->port_id);
3291                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3292                                         i40e_recv_scattered_pkts_vec_avx2 :
3293                                         i40e_recv_scattered_pkts_vec;
3294                         }
3295                 } else {
3296                         if (ad->rx_use_avx512) {
3297 #ifdef CC_AVX512_SUPPORT
3298                                 PMD_DRV_LOG(NOTICE,
3299                                         "Using AVX512 Vector Rx (port %d).",
3300                                         dev->data->port_id);
3301                                 dev->rx_pkt_burst =
3302                                         i40e_recv_pkts_vec_avx512;
3303 #endif
3304                         } else {
3305                                 PMD_INIT_LOG(DEBUG,
3306                                         "Using %sVector Rx (port %d).",
3307                                         ad->rx_use_avx2 ? "avx2 " : "",
3308                                         dev->data->port_id);
3309                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3310                                         i40e_recv_pkts_vec_avx2 :
3311                                         i40e_recv_pkts_vec;
3312                         }
3313                 }
3314 #else /* RTE_ARCH_X86 */
3315                 if (dev->data->scattered_rx) {
3316                         PMD_INIT_LOG(DEBUG,
3317                                      "Using Vector Scattered Rx (port %d).",
3318                                      dev->data->port_id);
3319                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3320                 } else {
3321                         PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3322                                      dev->data->port_id);
3323                         dev->rx_pkt_burst = i40e_recv_pkts_vec;
3324                 }
3325 #endif /* RTE_ARCH_X86 */
3326         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3327                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3328                                     "satisfied. Rx Burst Bulk Alloc function "
3329                                     "will be used on port=%d.",
3330                              dev->data->port_id);
3331
3332                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3333         } else {
3334                 /* Simple Rx Path. */
3335                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3336                              dev->data->port_id);
3337                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3338                                         i40e_recv_scattered_pkts :
3339                                         i40e_recv_pkts;
3340         }
3341
3342         /* Propagate information about RX function choice through all queues. */
3343         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3344                 rx_using_sse =
3345                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3346                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3347 #ifdef CC_AVX512_SUPPORT
3348                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3349                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3350 #endif
3351                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3352                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3353
3354                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3355                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3356
3357                         if (rxq)
3358                                 rxq->rx_using_sse = rx_using_sse;
3359                 }
3360         }
3361 }
3362
3363 static const struct {
3364         eth_rx_burst_t pkt_burst;
3365         const char *info;
3366 } i40e_rx_burst_infos[] = {
3367         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3368         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3369         { i40e_recv_pkts,                    "Scalar" },
3370 #ifdef RTE_ARCH_X86
3371 #ifdef CC_AVX512_SUPPORT
3372         { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3373         { i40e_recv_pkts_vec_avx512,           "Vector AVX512" },
3374 #endif
3375         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3376         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3377         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3378         { i40e_recv_pkts_vec,                "Vector SSE" },
3379 #elif defined(RTE_ARCH_ARM64)
3380         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3381         { i40e_recv_pkts_vec,                "Vector Neon" },
3382 #elif defined(RTE_ARCH_PPC_64)
3383         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3384         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3385 #endif
3386 };
3387
3388 int
3389 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3390                        struct rte_eth_burst_mode *mode)
3391 {
3392         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3393         int ret = -EINVAL;
3394         unsigned int i;
3395
3396         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3397                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3398                         snprintf(mode->info, sizeof(mode->info), "%s",
3399                                  i40e_rx_burst_infos[i].info);
3400                         ret = 0;
3401                         break;
3402                 }
3403         }
3404
3405         return ret;
3406 }
3407
3408 void __rte_cold
3409 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3410 {
3411         struct i40e_adapter *ad =
3412                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3413
3414         /* Use a simple Tx queue if possible (only fast free is allowed) */
3415         ad->tx_simple_allowed =
3416                 (txq->offloads ==
3417                  (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3418                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3419         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3420                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3421
3422         if (ad->tx_vec_allowed)
3423                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3424                                 txq->queue_id);
3425         else if (ad->tx_simple_allowed)
3426                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3427                                 txq->queue_id);
3428         else
3429                 PMD_INIT_LOG(DEBUG,
3430                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3431                                 txq->queue_id);
3432 }
3433
3434 void __rte_cold
3435 i40e_set_tx_function(struct rte_eth_dev *dev)
3436 {
3437         struct i40e_adapter *ad =
3438                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3439         int i;
3440
3441         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3442 #ifdef RTE_ARCH_X86
3443                 ad->tx_use_avx2 = false;
3444                 ad->tx_use_avx512 = false;
3445 #endif
3446                 if (ad->tx_vec_allowed) {
3447                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3448                                 struct i40e_tx_queue *txq =
3449                                         dev->data->tx_queues[i];
3450
3451                                 if (txq && i40e_txq_vec_setup(txq)) {
3452                                         ad->tx_vec_allowed = false;
3453                                         break;
3454                                 }
3455                         }
3456 #ifdef RTE_ARCH_X86
3457                         ad->tx_use_avx512 = get_avx_supported(1);
3458
3459                         if (!ad->tx_use_avx512)
3460                                 ad->tx_use_avx2 = get_avx_supported(0);
3461 #endif
3462                 }
3463         }
3464
3465         if (ad->tx_simple_allowed) {
3466                 if (ad->tx_vec_allowed &&
3467                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3468 #ifdef RTE_ARCH_X86
3469                         if (ad->tx_use_avx512) {
3470 #ifdef CC_AVX512_SUPPORT
3471                                 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3472                                             dev->data->port_id);
3473                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3474 #endif
3475                         } else {
3476                                 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3477                                              ad->tx_use_avx2 ? "avx2 " : "",
3478                                              dev->data->port_id);
3479                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3480                                                     i40e_xmit_pkts_vec_avx2 :
3481                                                     i40e_xmit_pkts_vec;
3482                         }
3483 #else /* RTE_ARCH_X86 */
3484                         PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3485                                      dev->data->port_id);
3486                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3487 #endif /* RTE_ARCH_X86 */
3488                 } else {
3489                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3490                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3491                 }
3492                 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3493         } else {
3494                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3495                 dev->tx_pkt_burst = i40e_xmit_pkts;
3496                 dev->tx_pkt_prepare = i40e_prep_pkts;
3497         }
3498 }
3499
3500 static const struct {
3501         eth_tx_burst_t pkt_burst;
3502         const char *info;
3503 } i40e_tx_burst_infos[] = {
3504         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3505         { i40e_xmit_pkts,          "Scalar" },
3506 #ifdef RTE_ARCH_X86
3507 #ifdef CC_AVX512_SUPPORT
3508         { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3509 #endif
3510         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3511         { i40e_xmit_pkts_vec,      "Vector SSE" },
3512 #elif defined(RTE_ARCH_ARM64)
3513         { i40e_xmit_pkts_vec,      "Vector Neon" },
3514 #elif defined(RTE_ARCH_PPC_64)
3515         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3516 #endif
3517 };
3518
3519 int
3520 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3521                        struct rte_eth_burst_mode *mode)
3522 {
3523         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3524         int ret = -EINVAL;
3525         unsigned int i;
3526
3527         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3528                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3529                         snprintf(mode->info, sizeof(mode->info), "%s",
3530                                  i40e_tx_burst_infos[i].info);
3531                         ret = 0;
3532                         break;
3533                 }
3534         }
3535
3536         return ret;
3537 }
3538
3539 void __rte_cold
3540 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3541 {
3542         struct i40e_adapter *ad =
3543                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3544         int i;
3545
3546         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3547                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3548 }
3549
3550 void __rte_cold
3551 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3552 {
3553         struct i40e_adapter *ad =
3554                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3556         int i;
3557
3558         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3559                 ad->pctypes_tbl[i] = 0ULL;
3560         ad->flow_types_mask = 0ULL;
3561         ad->pctypes_mask = 0ULL;
3562
3563         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3564                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3565         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3566                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3567         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3568                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3569         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3570                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3571         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3572                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3573         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3574                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3575         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3576                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3577         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3578                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3579         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3580                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3581         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3582                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3583         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3584                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3585
3586         if (hw->mac.type == I40E_MAC_X722 ||
3587                 hw->mac.type == I40E_MAC_X722_VF) {
3588                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3589                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3590                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3591                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3592                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3593                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3594                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3595                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3596                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3597                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3598                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3599                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3600         }
3601
3602         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3603                 if (ad->pctypes_tbl[i])
3604                         ad->flow_types_mask |= (1ULL << i);
3605                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3606         }
3607 }
3608
3609 #ifndef CC_AVX2_SUPPORT
3610 uint16_t
3611 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3612                         struct rte_mbuf __rte_unused **rx_pkts,
3613                         uint16_t __rte_unused nb_pkts)
3614 {
3615         return 0;
3616 }
3617
3618 uint16_t
3619 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3620                         struct rte_mbuf __rte_unused **rx_pkts,
3621                         uint16_t __rte_unused nb_pkts)
3622 {
3623         return 0;
3624 }
3625
3626 uint16_t
3627 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3628                           struct rte_mbuf __rte_unused **tx_pkts,
3629                           uint16_t __rte_unused nb_pkts)
3630 {
3631         return 0;
3632 }
3633 #endif /* ifndef CC_AVX2_SUPPORT */