1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
27 #include "i40e_logs.h"
28 #include "base/i40e_prototype.h"
29 #include "base/i40e_type.h"
30 #include "i40e_ethdev.h"
31 #include "i40e_rxtx.h"
33 #define DEFAULT_TX_RS_THRESH 32
34 #define DEFAULT_TX_FREE_THRESH 32
36 #define I40E_TX_MAX_BURST 32
38 #define I40E_DMA_MEM_ALIGN 4096
40 /* Base address of the HW descriptor ring should be 128B aligned. */
41 #define I40E_RING_BASE_ALIGN 128
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
45 #ifdef RTE_LIBRTE_IEEE1588
46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
48 #define I40E_TX_IEEE1588_TMST 0
51 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
55 PKT_TX_OUTER_IP_CKSUM)
57 #define I40E_TX_OFFLOAD_MASK ( \
64 PKT_TX_OUTER_IP_CKSUM | \
68 PKT_TX_TUNNEL_MASK | \
69 I40E_TX_IEEE1588_TMST)
71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
72 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
77 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
78 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
79 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
81 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
82 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
83 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
88 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
89 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
90 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
91 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
92 mb->vlan_tci_outer = mb->vlan_tci;
93 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
94 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
95 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
96 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
98 mb->vlan_tci_outer = 0;
101 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
102 mb->vlan_tci, mb->vlan_tci_outer);
105 /* Translate the rx descriptor status to pkt flags */
106 static inline uint64_t
107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
111 /* Check if RSS_HASH */
112 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
113 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
114 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
116 /* Check if FDIR Match */
117 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
123 static inline uint64_t
124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
127 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
129 #define I40E_RX_ERR_BITS 0x3f
130 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
131 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
136 flags |= PKT_RX_IP_CKSUM_BAD;
138 flags |= PKT_RX_IP_CKSUM_GOOD;
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
141 flags |= PKT_RX_L4_CKSUM_BAD;
143 flags |= PKT_RX_L4_CKSUM_GOOD;
145 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
146 flags |= PKT_RX_EIP_CKSUM_BAD;
151 /* Function to check and set the ieee1588 timesync index and get the
154 #ifdef RTE_LIBRTE_IEEE1588
155 static inline uint64_t
156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
158 uint64_t pkt_flags = 0;
159 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
160 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
161 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
163 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
164 == RTE_PTYPE_L2_ETHER_TIMESYNC)
165 pkt_flags = PKT_RX_IEEE1588_PTP;
167 pkt_flags |= PKT_RX_IEEE1588_TMST;
168 mb->timesync = tsyn & 0x03;
175 static inline uint64_t
176 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
179 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
180 uint16_t flexbh, flexbl;
182 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
183 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
184 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
185 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
186 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
187 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
190 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
192 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
193 flags |= PKT_RX_FDIR_ID;
194 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
196 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
197 flags |= PKT_RX_FDIR_FLX;
199 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
201 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
202 flags |= PKT_RX_FDIR_FLX;
206 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
207 flags |= PKT_RX_FDIR_ID;
213 i40e_parse_tunneling_params(uint64_t ol_flags,
214 union i40e_tx_offload tx_offload,
215 uint32_t *cd_tunneling)
217 /* EIPT: External (outer) IP header type */
218 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
219 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
220 else if (ol_flags & PKT_TX_OUTER_IPV4)
221 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
222 else if (ol_flags & PKT_TX_OUTER_IPV6)
223 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
225 /* EIPLEN: External (outer) IP header length, in DWords */
226 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
227 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
229 /* L4TUNT: L4 Tunneling Type */
230 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
231 case PKT_TX_TUNNEL_IPIP:
232 /* for non UDP / GRE tunneling, set to 00b */
234 case PKT_TX_TUNNEL_VXLAN:
235 case PKT_TX_TUNNEL_GENEVE:
236 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
238 case PKT_TX_TUNNEL_GRE:
239 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
242 PMD_TX_LOG(ERR, "Tunnel type not supported");
246 /* L4TUNLEN: L4 Tunneling Length, in Words
248 * We depend on app to set rte_mbuf.l2_len correctly.
249 * For IP in GRE it should be set to the length of the GRE
251 * for MAC in GRE or MAC in UDP it should be set to the length
252 * of the GRE or UDP headers plus the inner MAC up to including
253 * its last Ethertype.
255 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
256 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
260 i40e_txd_enable_checksum(uint64_t ol_flags,
263 union i40e_tx_offload tx_offload)
266 if (ol_flags & PKT_TX_TUNNEL_MASK)
267 *td_offset |= (tx_offload.outer_l2_len >> 1)
268 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
270 *td_offset |= (tx_offload.l2_len >> 1)
271 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
273 /* Enable L3 checksum offloads */
274 if (ol_flags & PKT_TX_IP_CKSUM) {
275 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
276 *td_offset |= (tx_offload.l3_len >> 2)
277 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
278 } else if (ol_flags & PKT_TX_IPV4) {
279 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
280 *td_offset |= (tx_offload.l3_len >> 2)
281 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
282 } else if (ol_flags & PKT_TX_IPV6) {
283 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
284 *td_offset |= (tx_offload.l3_len >> 2)
285 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
288 if (ol_flags & PKT_TX_TCP_SEG) {
289 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
290 *td_offset |= (tx_offload.l4_len >> 2)
291 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
295 /* Enable L4 checksum offloads */
296 switch (ol_flags & PKT_TX_L4_MASK) {
297 case PKT_TX_TCP_CKSUM:
298 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
299 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
300 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
302 case PKT_TX_SCTP_CKSUM:
303 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
304 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
305 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
307 case PKT_TX_UDP_CKSUM:
308 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
309 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
310 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
317 /* Construct the tx flags */
318 static inline uint64_t
319 i40e_build_ctob(uint32_t td_cmd,
324 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
325 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
326 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
327 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
328 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
332 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
334 struct i40e_tx_entry *sw_ring = txq->sw_ring;
335 volatile struct i40e_tx_desc *txd = txq->tx_ring;
336 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
337 uint16_t nb_tx_desc = txq->nb_tx_desc;
338 uint16_t desc_to_clean_to;
339 uint16_t nb_tx_to_clean;
341 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
342 if (desc_to_clean_to >= nb_tx_desc)
343 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
345 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
346 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
347 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
348 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
349 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
350 "(port=%d queue=%d)", desc_to_clean_to,
351 txq->port_id, txq->queue_id);
355 if (last_desc_cleaned > desc_to_clean_to)
356 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
359 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
362 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
364 txq->last_desc_cleaned = desc_to_clean_to;
365 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
371 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
372 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
374 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
379 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
380 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
381 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
382 "rxq->rx_free_thresh=%d, "
383 "RTE_PMD_I40E_RX_MAX_BURST=%d",
384 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
386 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
387 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
388 "rxq->rx_free_thresh=%d, "
389 "rxq->nb_rx_desc=%d",
390 rxq->rx_free_thresh, rxq->nb_rx_desc);
392 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
393 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
394 "rxq->nb_rx_desc=%d, "
395 "rxq->rx_free_thresh=%d",
396 rxq->nb_rx_desc, rxq->rx_free_thresh);
406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
407 #define I40E_LOOK_AHEAD 8
408 #if (I40E_LOOK_AHEAD != 8)
409 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
412 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
414 volatile union i40e_rx_desc *rxdp;
415 struct i40e_rx_entry *rxep;
420 int32_t s[I40E_LOOK_AHEAD], nb_dd;
421 int32_t i, j, nb_rx = 0;
423 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
425 rxdp = &rxq->rx_ring[rxq->rx_tail];
426 rxep = &rxq->sw_ring[rxq->rx_tail];
428 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
429 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
430 I40E_RXD_QW1_STATUS_SHIFT;
432 /* Make sure there is at least 1 packet to receive */
433 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
437 * Scan LOOK_AHEAD descriptors at a time to determine which
438 * descriptors reference packets that are ready to be received.
440 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
441 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
442 /* Read desc statuses backwards to avoid race condition */
443 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
444 qword1 = rte_le_to_cpu_64(\
445 rxdp[j].wb.qword1.status_error_len);
446 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
447 I40E_RXD_QW1_STATUS_SHIFT;
452 /* Compute how many status bits were set */
453 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
454 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
458 /* Translate descriptor info to mbuf parameters */
459 for (j = 0; j < nb_dd; j++) {
461 qword1 = rte_le_to_cpu_64(\
462 rxdp[j].wb.qword1.status_error_len);
463 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
464 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
465 mb->data_len = pkt_len;
466 mb->pkt_len = pkt_len;
468 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
469 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
470 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
472 ptype_tbl[(uint8_t)((qword1 &
473 I40E_RXD_QW1_PTYPE_MASK) >>
474 I40E_RXD_QW1_PTYPE_SHIFT)];
475 if (pkt_flags & PKT_RX_RSS_HASH)
476 mb->hash.rss = rte_le_to_cpu_32(\
477 rxdp[j].wb.qword0.hi_dword.rss);
478 if (pkt_flags & PKT_RX_FDIR)
479 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
481 #ifdef RTE_LIBRTE_IEEE1588
482 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
484 mb->ol_flags |= pkt_flags;
488 for (j = 0; j < I40E_LOOK_AHEAD; j++)
489 rxq->rx_stage[i + j] = rxep[j].mbuf;
491 if (nb_dd != I40E_LOOK_AHEAD)
495 /* Clear software ring entries */
496 for (i = 0; i < nb_rx; i++)
497 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
502 static inline uint16_t
503 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
504 struct rte_mbuf **rx_pkts,
508 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
510 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
512 for (i = 0; i < nb_pkts; i++)
513 rx_pkts[i] = stage[i];
515 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
516 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
522 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
524 volatile union i40e_rx_desc *rxdp;
525 struct i40e_rx_entry *rxep;
527 uint16_t alloc_idx, i;
531 /* Allocate buffers in bulk */
532 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
533 (rxq->rx_free_thresh - 1));
534 rxep = &(rxq->sw_ring[alloc_idx]);
535 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
536 rxq->rx_free_thresh);
537 if (unlikely(diag != 0)) {
538 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
542 rxdp = &rxq->rx_ring[alloc_idx];
543 for (i = 0; i < rxq->rx_free_thresh; i++) {
544 if (likely(i < (rxq->rx_free_thresh - 1)))
545 /* Prefetch next mbuf */
546 rte_prefetch0(rxep[i + 1].mbuf);
549 rte_mbuf_refcnt_set(mb, 1);
551 mb->data_off = RTE_PKTMBUF_HEADROOM;
553 mb->port = rxq->port_id;
554 dma_addr = rte_cpu_to_le_64(\
555 rte_mbuf_data_iova_default(mb));
556 rxdp[i].read.hdr_addr = 0;
557 rxdp[i].read.pkt_addr = dma_addr;
560 /* Update rx tail regsiter */
561 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
563 rxq->rx_free_trigger =
564 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
565 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
566 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
571 static inline uint16_t
572 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
574 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
575 struct rte_eth_dev *dev;
581 if (rxq->rx_nb_avail)
582 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
584 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
585 rxq->rx_next_avail = 0;
586 rxq->rx_nb_avail = nb_rx;
587 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
589 if (rxq->rx_tail > rxq->rx_free_trigger) {
590 if (i40e_rx_alloc_bufs(rxq) != 0) {
593 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
594 dev->data->rx_mbuf_alloc_failed +=
597 rxq->rx_nb_avail = 0;
598 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
599 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
600 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
606 if (rxq->rx_tail >= rxq->nb_rx_desc)
609 if (rxq->rx_nb_avail)
610 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
616 i40e_recv_pkts_bulk_alloc(void *rx_queue,
617 struct rte_mbuf **rx_pkts,
620 uint16_t nb_rx = 0, n, count;
622 if (unlikely(nb_pkts == 0))
625 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
626 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
629 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
630 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
631 nb_rx = (uint16_t)(nb_rx + count);
632 nb_pkts = (uint16_t)(nb_pkts - count);
641 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
642 struct rte_mbuf __rte_unused **rx_pkts,
643 uint16_t __rte_unused nb_pkts)
647 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
650 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
652 struct i40e_rx_queue *rxq;
653 volatile union i40e_rx_desc *rx_ring;
654 volatile union i40e_rx_desc *rxdp;
655 union i40e_rx_desc rxd;
656 struct i40e_rx_entry *sw_ring;
657 struct i40e_rx_entry *rxe;
658 struct rte_eth_dev *dev;
659 struct rte_mbuf *rxm;
660 struct rte_mbuf *nmb;
664 uint16_t rx_packet_len;
665 uint16_t rx_id, nb_hold;
673 rx_id = rxq->rx_tail;
674 rx_ring = rxq->rx_ring;
675 sw_ring = rxq->sw_ring;
676 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
678 while (nb_rx < nb_pkts) {
679 rxdp = &rx_ring[rx_id];
680 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
681 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
682 >> I40E_RXD_QW1_STATUS_SHIFT;
684 /* Check the DD bit first */
685 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
688 nmb = rte_mbuf_raw_alloc(rxq->mp);
689 if (unlikely(!nmb)) {
690 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
691 dev->data->rx_mbuf_alloc_failed++;
697 rxe = &sw_ring[rx_id];
699 if (unlikely(rx_id == rxq->nb_rx_desc))
702 /* Prefetch next mbuf */
703 rte_prefetch0(sw_ring[rx_id].mbuf);
706 * When next RX descriptor is on a cache line boundary,
707 * prefetch the next 4 RX descriptors and next 8 pointers
710 if ((rx_id & 0x3) == 0) {
711 rte_prefetch0(&rx_ring[rx_id]);
712 rte_prefetch0(&sw_ring[rx_id]);
717 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
718 rxdp->read.hdr_addr = 0;
719 rxdp->read.pkt_addr = dma_addr;
721 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
722 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
724 rxm->data_off = RTE_PKTMBUF_HEADROOM;
725 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
728 rxm->pkt_len = rx_packet_len;
729 rxm->data_len = rx_packet_len;
730 rxm->port = rxq->port_id;
732 i40e_rxd_to_vlan_tci(rxm, &rxd);
733 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
734 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
736 ptype_tbl[(uint8_t)((qword1 &
737 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
738 if (pkt_flags & PKT_RX_RSS_HASH)
740 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
741 if (pkt_flags & PKT_RX_FDIR)
742 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
744 #ifdef RTE_LIBRTE_IEEE1588
745 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
747 rxm->ol_flags |= pkt_flags;
749 rx_pkts[nb_rx++] = rxm;
751 rxq->rx_tail = rx_id;
754 * If the number of free RX descriptors is greater than the RX free
755 * threshold of the queue, advance the receive tail register of queue.
756 * Update that register with the value of the last processed RX
757 * descriptor minus 1.
759 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
760 if (nb_hold > rxq->rx_free_thresh) {
761 rx_id = (uint16_t) ((rx_id == 0) ?
762 (rxq->nb_rx_desc - 1) : (rx_id - 1));
763 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
766 rxq->nb_rx_hold = nb_hold;
772 i40e_recv_scattered_pkts(void *rx_queue,
773 struct rte_mbuf **rx_pkts,
776 struct i40e_rx_queue *rxq = rx_queue;
777 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
778 volatile union i40e_rx_desc *rxdp;
779 union i40e_rx_desc rxd;
780 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
781 struct i40e_rx_entry *rxe;
782 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
783 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
784 struct rte_mbuf *nmb, *rxm;
785 uint16_t rx_id = rxq->rx_tail;
786 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
787 struct rte_eth_dev *dev;
792 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
794 while (nb_rx < nb_pkts) {
795 rxdp = &rx_ring[rx_id];
796 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
797 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
798 I40E_RXD_QW1_STATUS_SHIFT;
800 /* Check the DD bit */
801 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
804 nmb = rte_mbuf_raw_alloc(rxq->mp);
805 if (unlikely(!nmb)) {
806 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
807 dev->data->rx_mbuf_alloc_failed++;
813 rxe = &sw_ring[rx_id];
815 if (rx_id == rxq->nb_rx_desc)
818 /* Prefetch next mbuf */
819 rte_prefetch0(sw_ring[rx_id].mbuf);
822 * When next RX descriptor is on a cache line boundary,
823 * prefetch the next 4 RX descriptors and next 8 pointers
826 if ((rx_id & 0x3) == 0) {
827 rte_prefetch0(&rx_ring[rx_id]);
828 rte_prefetch0(&sw_ring[rx_id]);
834 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
836 /* Set data buffer address and data length of the mbuf */
837 rxdp->read.hdr_addr = 0;
838 rxdp->read.pkt_addr = dma_addr;
839 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
840 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
841 rxm->data_len = rx_packet_len;
842 rxm->data_off = RTE_PKTMBUF_HEADROOM;
845 * If this is the first buffer of the received packet, set the
846 * pointer to the first mbuf of the packet and initialize its
847 * context. Otherwise, update the total length and the number
848 * of segments of the current scattered packet, and update the
849 * pointer to the last mbuf of the current packet.
853 first_seg->nb_segs = 1;
854 first_seg->pkt_len = rx_packet_len;
857 (uint16_t)(first_seg->pkt_len +
859 first_seg->nb_segs++;
860 last_seg->next = rxm;
864 * If this is not the last buffer of the received packet,
865 * update the pointer to the last mbuf of the current scattered
866 * packet and continue to parse the RX ring.
868 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
874 * This is the last buffer of the received packet. If the CRC
875 * is not stripped by the hardware:
876 * - Subtract the CRC length from the total packet length.
877 * - If the last buffer only contains the whole CRC or a part
878 * of it, free the mbuf associated to the last buffer. If part
879 * of the CRC is also contained in the previous mbuf, subtract
880 * the length of that CRC part from the data length of the
884 if (unlikely(rxq->crc_len > 0)) {
885 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
886 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
887 rte_pktmbuf_free_seg(rxm);
888 first_seg->nb_segs--;
890 (uint16_t)(last_seg->data_len -
891 (RTE_ETHER_CRC_LEN - rx_packet_len));
892 last_seg->next = NULL;
894 rxm->data_len = (uint16_t)(rx_packet_len -
898 first_seg->port = rxq->port_id;
899 first_seg->ol_flags = 0;
900 i40e_rxd_to_vlan_tci(first_seg, &rxd);
901 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
902 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
903 first_seg->packet_type =
904 ptype_tbl[(uint8_t)((qword1 &
905 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
906 if (pkt_flags & PKT_RX_RSS_HASH)
907 first_seg->hash.rss =
908 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
909 if (pkt_flags & PKT_RX_FDIR)
910 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
912 #ifdef RTE_LIBRTE_IEEE1588
913 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
915 first_seg->ol_flags |= pkt_flags;
917 /* Prefetch data of first segment, if configured to do so. */
918 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
919 first_seg->data_off));
920 rx_pkts[nb_rx++] = first_seg;
924 /* Record index of the next RX descriptor to probe. */
925 rxq->rx_tail = rx_id;
926 rxq->pkt_first_seg = first_seg;
927 rxq->pkt_last_seg = last_seg;
930 * If the number of free RX descriptors is greater than the RX free
931 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
932 * register. Update the RDT with the value of the last processed RX
933 * descriptor minus 1, to guarantee that the RDT register is never
934 * equal to the RDH register, which creates a "full" ring situtation
935 * from the hardware point of view.
937 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
938 if (nb_hold > rxq->rx_free_thresh) {
939 rx_id = (uint16_t)(rx_id == 0 ?
940 (rxq->nb_rx_desc - 1) : (rx_id - 1));
941 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
944 rxq->nb_rx_hold = nb_hold;
949 /* Check if the context descriptor is needed for TX offloading */
950 static inline uint16_t
951 i40e_calc_context_desc(uint64_t flags)
953 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
958 #ifdef RTE_LIBRTE_IEEE1588
959 mask |= PKT_TX_IEEE1588_TMST;
962 return (flags & mask) ? 1 : 0;
965 /* set i40e TSO context descriptor */
966 static inline uint64_t
967 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
969 uint64_t ctx_desc = 0;
970 uint32_t cd_cmd, hdr_len, cd_tso_len;
972 if (!tx_offload.l4_len) {
973 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
977 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
978 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
979 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
981 cd_cmd = I40E_TX_CTX_DESC_TSO;
982 cd_tso_len = mbuf->pkt_len - hdr_len;
983 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
984 ((uint64_t)cd_tso_len <<
985 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
986 ((uint64_t)mbuf->tso_segsz <<
987 I40E_TXD_CTX_QW1_MSS_SHIFT);
992 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
993 #define I40E_MAX_DATA_PER_TXD \
994 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
995 /* Calculate the number of TX descriptors needed for each pkt */
996 static inline uint16_t
997 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
999 struct rte_mbuf *txd = tx_pkt;
1002 while (txd != NULL) {
1003 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1011 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1013 struct i40e_tx_queue *txq;
1014 struct i40e_tx_entry *sw_ring;
1015 struct i40e_tx_entry *txe, *txn;
1016 volatile struct i40e_tx_desc *txd;
1017 volatile struct i40e_tx_desc *txr;
1018 struct rte_mbuf *tx_pkt;
1019 struct rte_mbuf *m_seg;
1020 uint32_t cd_tunneling_params;
1031 uint64_t buf_dma_addr;
1032 union i40e_tx_offload tx_offload = {0};
1035 sw_ring = txq->sw_ring;
1037 tx_id = txq->tx_tail;
1038 txe = &sw_ring[tx_id];
1040 /* Check if the descriptor ring needs to be cleaned. */
1041 if (txq->nb_tx_free < txq->tx_free_thresh)
1042 i40e_xmit_cleanup(txq);
1044 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1049 tx_pkt = *tx_pkts++;
1050 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1052 ol_flags = tx_pkt->ol_flags;
1053 tx_offload.l2_len = tx_pkt->l2_len;
1054 tx_offload.l3_len = tx_pkt->l3_len;
1055 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1056 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1057 tx_offload.l4_len = tx_pkt->l4_len;
1058 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1060 /* Calculate the number of context descriptors needed. */
1061 nb_ctx = i40e_calc_context_desc(ol_flags);
1064 * The number of descriptors that must be allocated for
1065 * a packet equals to the number of the segments of that
1066 * packet plus 1 context descriptor if needed.
1067 * Recalculate the needed tx descs when TSO enabled in case
1068 * the mbuf data size exceeds max data size that hw allows
1071 if (ol_flags & PKT_TX_TCP_SEG)
1072 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1075 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1076 tx_last = (uint16_t)(tx_id + nb_used - 1);
1079 if (tx_last >= txq->nb_tx_desc)
1080 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1082 if (nb_used > txq->nb_tx_free) {
1083 if (i40e_xmit_cleanup(txq) != 0) {
1088 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1089 while (nb_used > txq->nb_tx_free) {
1090 if (i40e_xmit_cleanup(txq) != 0) {
1099 /* Descriptor based VLAN insertion */
1100 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1101 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1102 td_tag = tx_pkt->vlan_tci;
1105 /* Always enable CRC offload insertion */
1106 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1108 /* Fill in tunneling parameters if necessary */
1109 cd_tunneling_params = 0;
1110 if (ol_flags & PKT_TX_TUNNEL_MASK)
1111 i40e_parse_tunneling_params(ol_flags, tx_offload,
1112 &cd_tunneling_params);
1113 /* Enable checksum offloading */
1114 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1115 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1116 &td_offset, tx_offload);
1119 /* Setup TX context descriptor if required */
1120 volatile struct i40e_tx_context_desc *ctx_txd =
1121 (volatile struct i40e_tx_context_desc *)\
1123 uint16_t cd_l2tag2 = 0;
1124 uint64_t cd_type_cmd_tso_mss =
1125 I40E_TX_DESC_DTYPE_CONTEXT;
1127 txn = &sw_ring[txe->next_id];
1128 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1129 if (txe->mbuf != NULL) {
1130 rte_pktmbuf_free_seg(txe->mbuf);
1134 /* TSO enabled means no timestamp */
1135 if (ol_flags & PKT_TX_TCP_SEG)
1136 cd_type_cmd_tso_mss |=
1137 i40e_set_tso_ctx(tx_pkt, tx_offload);
1139 #ifdef RTE_LIBRTE_IEEE1588
1140 if (ol_flags & PKT_TX_IEEE1588_TMST)
1141 cd_type_cmd_tso_mss |=
1142 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1143 I40E_TXD_CTX_QW1_CMD_SHIFT);
1147 ctx_txd->tunneling_params =
1148 rte_cpu_to_le_32(cd_tunneling_params);
1149 if (ol_flags & PKT_TX_QINQ_PKT) {
1150 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1151 cd_type_cmd_tso_mss |=
1152 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1153 I40E_TXD_CTX_QW1_CMD_SHIFT);
1155 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1156 ctx_txd->type_cmd_tso_mss =
1157 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1159 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1160 "tunneling_params: %#x;\n"
1163 "type_cmd_tso_mss: %#"PRIx64";\n",
1165 ctx_txd->tunneling_params,
1168 ctx_txd->type_cmd_tso_mss);
1170 txe->last_id = tx_last;
1171 tx_id = txe->next_id;
1178 txn = &sw_ring[txe->next_id];
1181 rte_pktmbuf_free_seg(txe->mbuf);
1184 /* Setup TX Descriptor */
1185 slen = m_seg->data_len;
1186 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1188 while ((ol_flags & PKT_TX_TCP_SEG) &&
1189 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1191 rte_cpu_to_le_64(buf_dma_addr);
1192 txd->cmd_type_offset_bsz =
1193 i40e_build_ctob(td_cmd,
1194 td_offset, I40E_MAX_DATA_PER_TXD,
1197 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1198 slen -= I40E_MAX_DATA_PER_TXD;
1200 txe->last_id = tx_last;
1201 tx_id = txe->next_id;
1204 txn = &sw_ring[txe->next_id];
1206 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1207 "buf_dma_addr: %#"PRIx64";\n"
1212 tx_pkt, tx_id, buf_dma_addr,
1213 td_cmd, td_offset, slen, td_tag);
1215 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1216 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1217 td_offset, slen, td_tag);
1218 txe->last_id = tx_last;
1219 tx_id = txe->next_id;
1221 m_seg = m_seg->next;
1222 } while (m_seg != NULL);
1224 /* The last packet data descriptor needs End Of Packet (EOP) */
1225 td_cmd |= I40E_TX_DESC_CMD_EOP;
1226 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1227 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1229 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1230 PMD_TX_FREE_LOG(DEBUG,
1231 "Setting RS bit on TXD id="
1232 "%4u (port=%d queue=%d)",
1233 tx_last, txq->port_id, txq->queue_id);
1235 td_cmd |= I40E_TX_DESC_CMD_RS;
1237 /* Update txq RS bit counters */
1238 txq->nb_tx_used = 0;
1241 txd->cmd_type_offset_bsz |=
1242 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1243 I40E_TXD_QW1_CMD_SHIFT);
1247 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1248 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1249 (unsigned) tx_id, (unsigned) nb_tx);
1251 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1252 txq->tx_tail = tx_id;
1257 static __rte_always_inline int
1258 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1260 struct i40e_tx_entry *txep;
1263 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1264 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1265 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1268 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1270 for (i = 0; i < txq->tx_rs_thresh; i++)
1271 rte_prefetch0((txep + i)->mbuf);
1273 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1274 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1275 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1279 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1280 rte_pktmbuf_free_seg(txep->mbuf);
1285 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1286 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1287 if (txq->tx_next_dd >= txq->nb_tx_desc)
1288 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1290 return txq->tx_rs_thresh;
1293 /* Populate 4 descriptors with data from 4 mbufs */
1295 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1300 for (i = 0; i < 4; i++, txdp++, pkts++) {
1301 dma_addr = rte_mbuf_data_iova(*pkts);
1302 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1303 txdp->cmd_type_offset_bsz =
1304 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1305 (*pkts)->data_len, 0);
1309 /* Populate 1 descriptor with data from 1 mbuf */
1311 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1315 dma_addr = rte_mbuf_data_iova(*pkts);
1316 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1317 txdp->cmd_type_offset_bsz =
1318 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1319 (*pkts)->data_len, 0);
1322 /* Fill hardware descriptor ring with mbuf data */
1324 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1325 struct rte_mbuf **pkts,
1328 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1329 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1330 const int N_PER_LOOP = 4;
1331 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1332 int mainpart, leftover;
1335 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1336 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1337 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1338 for (j = 0; j < N_PER_LOOP; ++j) {
1339 (txep + i + j)->mbuf = *(pkts + i + j);
1341 tx4(txdp + i, pkts + i);
1343 if (unlikely(leftover > 0)) {
1344 for (i = 0; i < leftover; ++i) {
1345 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1346 tx1(txdp + mainpart + i, pkts + mainpart + i);
1351 static inline uint16_t
1352 tx_xmit_pkts(struct i40e_tx_queue *txq,
1353 struct rte_mbuf **tx_pkts,
1356 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1360 * Begin scanning the H/W ring for done descriptors when the number
1361 * of available descriptors drops below tx_free_thresh. For each done
1362 * descriptor, free the associated buffer.
1364 if (txq->nb_tx_free < txq->tx_free_thresh)
1365 i40e_tx_free_bufs(txq);
1367 /* Use available descriptor only */
1368 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1369 if (unlikely(!nb_pkts))
1372 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1373 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1374 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1375 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1376 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1377 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1378 I40E_TXD_QW1_CMD_SHIFT);
1379 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1383 /* Fill hardware descriptor ring with mbuf data */
1384 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1385 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1387 /* Determin if RS bit needs to be set */
1388 if (txq->tx_tail > txq->tx_next_rs) {
1389 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1390 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1391 I40E_TXD_QW1_CMD_SHIFT);
1393 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1394 if (txq->tx_next_rs >= txq->nb_tx_desc)
1395 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1398 if (txq->tx_tail >= txq->nb_tx_desc)
1401 /* Update the tx tail register */
1402 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1408 i40e_xmit_pkts_simple(void *tx_queue,
1409 struct rte_mbuf **tx_pkts,
1414 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1415 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1419 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1422 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1423 &tx_pkts[nb_tx], num);
1424 nb_tx = (uint16_t)(nb_tx + ret);
1425 nb_pkts = (uint16_t)(nb_pkts - ret);
1434 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1438 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1443 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1444 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1455 /*********************************************************************
1459 **********************************************************************/
1461 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1468 for (i = 0; i < nb_pkts; i++) {
1470 ol_flags = m->ol_flags;
1472 /* Check for m->nb_segs to not exceed the limits. */
1473 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1474 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1475 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1479 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1480 m->tso_segsz < I40E_MIN_TSO_MSS ||
1481 m->tso_segsz > I40E_MAX_TSO_MSS ||
1482 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1483 /* MSS outside the range (256B - 9674B) are considered
1490 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1491 rte_errno = ENOTSUP;
1495 /* check the size of packet */
1496 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1501 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1502 ret = rte_validate_tx_offload(m);
1508 ret = rte_net_intel_cksum_prepare(m);
1518 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1519 * application used, which assume having sequential ones. But from driver's
1520 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1521 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1522 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1523 * use queue_idx from 0 to 95 to access queues, while real queue would be
1524 * different. This function will do a queue mapping to find VSI the queue
1527 static struct i40e_vsi*
1528 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1530 /* the queue in MAIN VSI range */
1531 if (queue_idx < pf->main_vsi->nb_qps)
1532 return pf->main_vsi;
1534 queue_idx -= pf->main_vsi->nb_qps;
1536 /* queue_idx is greater than VMDQ VSIs range */
1537 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1538 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1542 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1546 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1548 /* the queue in MAIN VSI range */
1549 if (queue_idx < pf->main_vsi->nb_qps)
1552 /* It's VMDQ queues */
1553 queue_idx -= pf->main_vsi->nb_qps;
1555 if (pf->nb_cfg_vmdq_vsi)
1556 return queue_idx % pf->vmdq_nb_qps;
1558 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1559 return (uint16_t)(-1);
1564 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1566 struct i40e_rx_queue *rxq;
1568 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570 PMD_INIT_FUNC_TRACE();
1572 rxq = dev->data->rx_queues[rx_queue_id];
1574 err = i40e_alloc_rx_queue_mbufs(rxq);
1576 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1580 /* Init the RX tail regieter. */
1581 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1583 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1585 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1588 i40e_rx_queue_release_mbufs(rxq);
1589 i40e_reset_rx_queue(rxq);
1592 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1598 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1600 struct i40e_rx_queue *rxq;
1602 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604 rxq = dev->data->rx_queues[rx_queue_id];
1607 * rx_queue_id is queue id application refers to, while
1608 * rxq->reg_idx is the real queue index.
1610 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1612 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1616 i40e_rx_queue_release_mbufs(rxq);
1617 i40e_reset_rx_queue(rxq);
1618 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1624 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1627 struct i40e_tx_queue *txq;
1628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630 PMD_INIT_FUNC_TRACE();
1632 txq = dev->data->tx_queues[tx_queue_id];
1635 * tx_queue_id is queue id application refers to, while
1636 * rxq->reg_idx is the real queue index.
1638 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1640 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1644 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1650 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1652 struct i40e_tx_queue *txq;
1654 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656 txq = dev->data->tx_queues[tx_queue_id];
1659 * tx_queue_id is queue id application refers to, while
1660 * txq->reg_idx is the real queue index.
1662 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1664 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1669 i40e_tx_queue_release_mbufs(txq);
1670 i40e_reset_tx_queue(txq);
1671 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1677 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1679 static const uint32_t ptypes[] = {
1680 /* refers to i40e_rxd_pkt_type_mapping() */
1682 RTE_PTYPE_L2_ETHER_TIMESYNC,
1683 RTE_PTYPE_L2_ETHER_LLDP,
1684 RTE_PTYPE_L2_ETHER_ARP,
1685 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1686 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1689 RTE_PTYPE_L4_NONFRAG,
1693 RTE_PTYPE_TUNNEL_GRENAT,
1694 RTE_PTYPE_TUNNEL_IP,
1695 RTE_PTYPE_INNER_L2_ETHER,
1696 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1697 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1698 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1699 RTE_PTYPE_INNER_L4_FRAG,
1700 RTE_PTYPE_INNER_L4_ICMP,
1701 RTE_PTYPE_INNER_L4_NONFRAG,
1702 RTE_PTYPE_INNER_L4_SCTP,
1703 RTE_PTYPE_INNER_L4_TCP,
1704 RTE_PTYPE_INNER_L4_UDP,
1708 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1709 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1710 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1712 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1713 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1714 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1715 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1716 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1722 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1726 for (i = 0; i < num; i++) {
1727 if (i != idx && queues[i])
1735 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1736 struct i40e_rx_queue *rxq)
1738 struct i40e_adapter *ad =
1739 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1740 int use_def_burst_func =
1741 check_rx_burst_bulk_alloc_preconditions(rxq);
1743 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1744 RTE_PKTMBUF_HEADROOM);
1745 int use_scattered_rx =
1746 (rxq->max_pkt_len > buf_size);
1748 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1750 "Failed to do RX queue initialization");
1754 if (i40e_dev_first_queue(rxq->queue_id,
1755 dev->data->rx_queues,
1756 dev->data->nb_rx_queues)) {
1758 * If it is the first queue to setup,
1759 * set all flags to default and call
1760 * i40e_set_rx_function.
1762 ad->rx_bulk_alloc_allowed = true;
1763 ad->rx_vec_allowed = true;
1764 dev->data->scattered_rx = use_scattered_rx;
1765 if (use_def_burst_func)
1766 ad->rx_bulk_alloc_allowed = false;
1767 i40e_set_rx_function(dev);
1769 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1770 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1771 " number %d of queue %d isn't power of 2",
1772 rxq->nb_rx_desc, rxq->queue_id);
1776 /* check bulk alloc conflict */
1777 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1778 PMD_DRV_LOG(ERR, "Can't use default burst.");
1781 /* check scatterred conflict */
1782 if (!dev->data->scattered_rx && use_scattered_rx) {
1783 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1786 /* check vector conflict */
1787 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1788 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1796 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1799 unsigned int socket_id,
1800 const struct rte_eth_rxconf *rx_conf,
1801 struct rte_mempool *mp)
1803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 struct i40e_adapter *ad =
1805 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1806 struct i40e_vsi *vsi;
1807 struct i40e_pf *pf = NULL;
1808 struct i40e_vf *vf = NULL;
1809 struct i40e_rx_queue *rxq;
1810 const struct rte_memzone *rz;
1813 uint16_t reg_idx, base, bsf, tc_mapping;
1814 int q_offset, use_def_burst_func = 1;
1817 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1819 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1820 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1824 reg_idx = queue_idx;
1826 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1827 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1830 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1833 reg_idx = vsi->base_queue + q_offset;
1836 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1837 (nb_desc > I40E_MAX_RING_DESC) ||
1838 (nb_desc < I40E_MIN_RING_DESC)) {
1839 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1840 "invalid", nb_desc);
1844 /* Free memory if needed */
1845 if (dev->data->rx_queues[queue_idx]) {
1846 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1847 dev->data->rx_queues[queue_idx] = NULL;
1850 /* Allocate the rx queue data structure */
1851 rxq = rte_zmalloc_socket("i40e rx queue",
1852 sizeof(struct i40e_rx_queue),
1853 RTE_CACHE_LINE_SIZE,
1856 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1857 "rx queue data structure");
1861 rxq->nb_rx_desc = nb_desc;
1862 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1863 rxq->queue_id = queue_idx;
1864 rxq->reg_idx = reg_idx;
1865 rxq->port_id = dev->data->port_id;
1866 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1867 rxq->crc_len = RTE_ETHER_CRC_LEN;
1870 rxq->drop_en = rx_conf->rx_drop_en;
1872 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1873 rxq->offloads = offloads;
1875 /* Allocate the maximun number of RX ring hardware descriptor. */
1876 len = I40E_MAX_RING_DESC;
1879 * Allocating a little more memory because vectorized/bulk_alloc Rx
1880 * functions doesn't check boundaries each time.
1882 len += RTE_PMD_I40E_RX_MAX_BURST;
1884 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1885 I40E_DMA_MEM_ALIGN);
1887 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1888 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1890 i40e_dev_rx_queue_release(rxq);
1891 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1895 /* Zero all the descriptors in the ring. */
1896 memset(rz->addr, 0, ring_size);
1898 rxq->rx_ring_phys_addr = rz->iova;
1899 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1901 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1903 /* Allocate the software ring. */
1905 rte_zmalloc_socket("i40e rx sw ring",
1906 sizeof(struct i40e_rx_entry) * len,
1907 RTE_CACHE_LINE_SIZE,
1909 if (!rxq->sw_ring) {
1910 i40e_dev_rx_queue_release(rxq);
1911 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1915 i40e_reset_rx_queue(rxq);
1918 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1919 if (!(vsi->enabled_tc & (1 << i)))
1921 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1922 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1923 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1924 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1925 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1927 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1931 if (dev->data->dev_started) {
1932 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1933 i40e_dev_rx_queue_release(rxq);
1937 use_def_burst_func =
1938 check_rx_burst_bulk_alloc_preconditions(rxq);
1939 if (!use_def_burst_func) {
1940 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1942 "Rx Burst Bulk Alloc Preconditions are "
1943 "satisfied. Rx Burst Bulk Alloc function will be "
1944 "used on port=%d, queue=%d.",
1945 rxq->port_id, rxq->queue_id);
1946 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1949 "Rx Burst Bulk Alloc Preconditions are "
1950 "not satisfied, Scattered Rx is requested, "
1951 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1952 "not enabled on port=%d, queue=%d.",
1953 rxq->port_id, rxq->queue_id);
1954 ad->rx_bulk_alloc_allowed = false;
1958 dev->data->rx_queues[queue_idx] = rxq;
1963 i40e_dev_rx_queue_release(void *rxq)
1965 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1968 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1972 i40e_rx_queue_release_mbufs(q);
1973 rte_free(q->sw_ring);
1978 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1980 #define I40E_RXQ_SCAN_INTERVAL 4
1981 volatile union i40e_rx_desc *rxdp;
1982 struct i40e_rx_queue *rxq;
1985 rxq = dev->data->rx_queues[rx_queue_id];
1986 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1987 while ((desc < rxq->nb_rx_desc) &&
1988 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1989 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1990 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1992 * Check the DD bit of a rx descriptor of each 4 in a group,
1993 * to avoid checking too frequently and downgrading performance
1996 desc += I40E_RXQ_SCAN_INTERVAL;
1997 rxdp += I40E_RXQ_SCAN_INTERVAL;
1998 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1999 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2000 desc - rxq->nb_rx_desc]);
2007 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2009 volatile union i40e_rx_desc *rxdp;
2010 struct i40e_rx_queue *rxq = rx_queue;
2014 if (unlikely(offset >= rxq->nb_rx_desc)) {
2015 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2019 desc = rxq->rx_tail + offset;
2020 if (desc >= rxq->nb_rx_desc)
2021 desc -= rxq->nb_rx_desc;
2023 rxdp = &(rxq->rx_ring[desc]);
2025 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2026 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2027 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2033 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2035 struct i40e_rx_queue *rxq = rx_queue;
2036 volatile uint64_t *status;
2040 if (unlikely(offset >= rxq->nb_rx_desc))
2043 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2044 return RTE_ETH_RX_DESC_UNAVAIL;
2046 desc = rxq->rx_tail + offset;
2047 if (desc >= rxq->nb_rx_desc)
2048 desc -= rxq->nb_rx_desc;
2050 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2051 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2052 << I40E_RXD_QW1_STATUS_SHIFT);
2054 return RTE_ETH_RX_DESC_DONE;
2056 return RTE_ETH_RX_DESC_AVAIL;
2060 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2062 struct i40e_tx_queue *txq = tx_queue;
2063 volatile uint64_t *status;
2064 uint64_t mask, expect;
2067 if (unlikely(offset >= txq->nb_tx_desc))
2070 desc = txq->tx_tail + offset;
2071 /* go to next desc that has the RS bit */
2072 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2074 if (desc >= txq->nb_tx_desc) {
2075 desc -= txq->nb_tx_desc;
2076 if (desc >= txq->nb_tx_desc)
2077 desc -= txq->nb_tx_desc;
2080 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2081 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2082 expect = rte_cpu_to_le_64(
2083 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2084 if ((*status & mask) == expect)
2085 return RTE_ETH_TX_DESC_DONE;
2087 return RTE_ETH_TX_DESC_FULL;
2091 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2092 struct i40e_tx_queue *txq)
2094 struct i40e_adapter *ad =
2095 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2097 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2099 "Failed to do TX queue initialization");
2103 if (i40e_dev_first_queue(txq->queue_id,
2104 dev->data->tx_queues,
2105 dev->data->nb_tx_queues)) {
2107 * If it is the first queue to setup,
2108 * set all flags and call
2109 * i40e_set_tx_function.
2111 i40e_set_tx_function_flag(dev, txq);
2112 i40e_set_tx_function(dev);
2116 /* check vector conflict */
2117 if (ad->tx_vec_allowed) {
2118 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2119 i40e_txq_vec_setup(txq)) {
2120 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2124 /* check simple tx conflict */
2125 if (ad->tx_simple_allowed) {
2126 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2127 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2128 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2137 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2140 unsigned int socket_id,
2141 const struct rte_eth_txconf *tx_conf)
2143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct i40e_vsi *vsi;
2145 struct i40e_pf *pf = NULL;
2146 struct i40e_vf *vf = NULL;
2147 struct i40e_tx_queue *txq;
2148 const struct rte_memzone *tz;
2150 uint16_t tx_rs_thresh, tx_free_thresh;
2151 uint16_t reg_idx, i, base, bsf, tc_mapping;
2155 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2157 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2158 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2162 reg_idx = queue_idx;
2164 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2165 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2168 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2171 reg_idx = vsi->base_queue + q_offset;
2174 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2175 (nb_desc > I40E_MAX_RING_DESC) ||
2176 (nb_desc < I40E_MIN_RING_DESC)) {
2177 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2178 "invalid", nb_desc);
2183 * The following two parameters control the setting of the RS bit on
2184 * transmit descriptors. TX descriptors will have their RS bit set
2185 * after txq->tx_rs_thresh descriptors have been used. The TX
2186 * descriptor ring will be cleaned after txq->tx_free_thresh
2187 * descriptors are used or if the number of descriptors required to
2188 * transmit a packet is greater than the number of free TX descriptors.
2190 * The following constraints must be satisfied:
2191 * - tx_rs_thresh must be greater than 0.
2192 * - tx_rs_thresh must be less than the size of the ring minus 2.
2193 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2194 * - tx_rs_thresh must be a divisor of the ring size.
2195 * - tx_free_thresh must be greater than 0.
2196 * - tx_free_thresh must be less than the size of the ring minus 3.
2197 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2199 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2200 * race condition, hence the maximum threshold constraints. When set
2201 * to zero use default values.
2203 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2204 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2205 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2206 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2207 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2208 if (tx_conf->tx_rs_thresh > 0)
2209 tx_rs_thresh = tx_conf->tx_rs_thresh;
2210 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2211 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2212 "exceed nb_desc. (tx_rs_thresh=%u "
2213 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2214 (unsigned int)tx_rs_thresh,
2215 (unsigned int)tx_free_thresh,
2216 (unsigned int)nb_desc,
2217 (int)dev->data->port_id,
2219 return I40E_ERR_PARAM;
2221 if (tx_rs_thresh >= (nb_desc - 2)) {
2222 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2223 "number of TX descriptors minus 2. "
2224 "(tx_rs_thresh=%u port=%d queue=%d)",
2225 (unsigned int)tx_rs_thresh,
2226 (int)dev->data->port_id,
2228 return I40E_ERR_PARAM;
2230 if (tx_free_thresh >= (nb_desc - 3)) {
2231 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2232 "number of TX descriptors minus 3. "
2233 "(tx_free_thresh=%u port=%d queue=%d)",
2234 (unsigned int)tx_free_thresh,
2235 (int)dev->data->port_id,
2237 return I40E_ERR_PARAM;
2239 if (tx_rs_thresh > tx_free_thresh) {
2240 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2241 "equal to tx_free_thresh. (tx_free_thresh=%u"
2242 " tx_rs_thresh=%u port=%d queue=%d)",
2243 (unsigned int)tx_free_thresh,
2244 (unsigned int)tx_rs_thresh,
2245 (int)dev->data->port_id,
2247 return I40E_ERR_PARAM;
2249 if ((nb_desc % tx_rs_thresh) != 0) {
2250 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2251 "number of TX descriptors. (tx_rs_thresh=%u"
2252 " port=%d queue=%d)",
2253 (unsigned int)tx_rs_thresh,
2254 (int)dev->data->port_id,
2256 return I40E_ERR_PARAM;
2258 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2259 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2260 "tx_rs_thresh is greater than 1. "
2261 "(tx_rs_thresh=%u port=%d queue=%d)",
2262 (unsigned int)tx_rs_thresh,
2263 (int)dev->data->port_id,
2265 return I40E_ERR_PARAM;
2268 /* Free memory if needed. */
2269 if (dev->data->tx_queues[queue_idx]) {
2270 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2271 dev->data->tx_queues[queue_idx] = NULL;
2274 /* Allocate the TX queue data structure. */
2275 txq = rte_zmalloc_socket("i40e tx queue",
2276 sizeof(struct i40e_tx_queue),
2277 RTE_CACHE_LINE_SIZE,
2280 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2281 "tx queue structure");
2285 /* Allocate TX hardware ring descriptors. */
2286 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2287 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2288 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2289 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2291 i40e_dev_tx_queue_release(txq);
2292 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2296 txq->nb_tx_desc = nb_desc;
2297 txq->tx_rs_thresh = tx_rs_thresh;
2298 txq->tx_free_thresh = tx_free_thresh;
2299 txq->pthresh = tx_conf->tx_thresh.pthresh;
2300 txq->hthresh = tx_conf->tx_thresh.hthresh;
2301 txq->wthresh = tx_conf->tx_thresh.wthresh;
2302 txq->queue_id = queue_idx;
2303 txq->reg_idx = reg_idx;
2304 txq->port_id = dev->data->port_id;
2305 txq->offloads = offloads;
2307 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2309 txq->tx_ring_phys_addr = tz->iova;
2310 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2312 /* Allocate software ring */
2314 rte_zmalloc_socket("i40e tx sw ring",
2315 sizeof(struct i40e_tx_entry) * nb_desc,
2316 RTE_CACHE_LINE_SIZE,
2318 if (!txq->sw_ring) {
2319 i40e_dev_tx_queue_release(txq);
2320 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2324 i40e_reset_tx_queue(txq);
2327 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2328 if (!(vsi->enabled_tc & (1 << i)))
2330 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2331 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2332 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2333 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2334 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2336 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2340 if (dev->data->dev_started) {
2341 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2342 i40e_dev_tx_queue_release(txq);
2347 * Use a simple TX queue without offloads or
2348 * multi segs if possible
2350 i40e_set_tx_function_flag(dev, txq);
2352 dev->data->tx_queues[queue_idx] = txq;
2358 i40e_dev_tx_queue_release(void *txq)
2360 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2363 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2367 i40e_tx_queue_release_mbufs(q);
2368 rte_free(q->sw_ring);
2372 const struct rte_memzone *
2373 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2375 const struct rte_memzone *mz;
2377 mz = rte_memzone_lookup(name);
2381 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2382 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2387 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2391 /* SSE Vector driver has a different way of releasing mbufs. */
2392 if (rxq->rx_using_sse) {
2393 i40e_rx_queue_release_mbufs_vec(rxq);
2397 if (!rxq->sw_ring) {
2398 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2402 for (i = 0; i < rxq->nb_rx_desc; i++) {
2403 if (rxq->sw_ring[i].mbuf) {
2404 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2405 rxq->sw_ring[i].mbuf = NULL;
2408 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2409 if (rxq->rx_nb_avail == 0)
2411 for (i = 0; i < rxq->rx_nb_avail; i++) {
2412 struct rte_mbuf *mbuf;
2414 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2415 rte_pktmbuf_free_seg(mbuf);
2417 rxq->rx_nb_avail = 0;
2418 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2422 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2428 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2432 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2433 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2434 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2436 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2437 len = rxq->nb_rx_desc;
2439 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2440 ((volatile char *)rxq->rx_ring)[i] = 0;
2442 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2443 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2444 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2446 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2447 rxq->rx_nb_avail = 0;
2448 rxq->rx_next_avail = 0;
2449 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2450 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2452 rxq->nb_rx_hold = 0;
2453 rxq->pkt_first_seg = NULL;
2454 rxq->pkt_last_seg = NULL;
2456 rxq->rxrearm_start = 0;
2457 rxq->rxrearm_nb = 0;
2461 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2463 struct rte_eth_dev *dev;
2466 if (!txq || !txq->sw_ring) {
2467 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2471 dev = &rte_eth_devices[txq->port_id];
2474 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2475 * so need to free remains more carefully.
2477 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2478 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2479 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2480 if (txq->tx_tail < i) {
2481 for (; i < txq->nb_tx_desc; i++) {
2482 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2483 txq->sw_ring[i].mbuf = NULL;
2487 for (; i < txq->tx_tail; i++) {
2488 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2489 txq->sw_ring[i].mbuf = NULL;
2492 for (i = 0; i < txq->nb_tx_desc; i++) {
2493 if (txq->sw_ring[i].mbuf) {
2494 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2495 txq->sw_ring[i].mbuf = NULL;
2502 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2505 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2506 uint16_t i, tx_last, tx_id;
2507 uint16_t nb_tx_free_last;
2508 uint16_t nb_tx_to_clean;
2511 /* Start free mbuf from the next of tx_tail */
2512 tx_last = txq->tx_tail;
2513 tx_id = swr_ring[tx_last].next_id;
2515 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2518 nb_tx_to_clean = txq->nb_tx_free;
2519 nb_tx_free_last = txq->nb_tx_free;
2521 free_cnt = txq->nb_tx_desc;
2523 /* Loop through swr_ring to count the amount of
2524 * freeable mubfs and packets.
2526 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2527 for (i = 0; i < nb_tx_to_clean &&
2528 pkt_cnt < free_cnt &&
2529 tx_id != tx_last; i++) {
2530 if (swr_ring[tx_id].mbuf != NULL) {
2531 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2532 swr_ring[tx_id].mbuf = NULL;
2535 * last segment in the packet,
2536 * increment packet count
2538 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2541 tx_id = swr_ring[tx_id].next_id;
2544 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2545 txq->nb_tx_free || tx_id == tx_last)
2548 if (pkt_cnt < free_cnt) {
2549 if (i40e_xmit_cleanup(txq))
2552 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2553 nb_tx_free_last = txq->nb_tx_free;
2557 return (int)pkt_cnt;
2561 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2566 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2567 free_cnt = txq->nb_tx_desc;
2569 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2571 for (i = 0; i < cnt; i += n) {
2572 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2575 n = i40e_tx_free_bufs(txq);
2585 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2586 uint32_t free_cnt __rte_unused)
2591 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2593 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2594 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2595 struct i40e_adapter *ad =
2596 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2598 if (ad->tx_simple_allowed) {
2599 if (ad->tx_vec_allowed)
2600 return i40e_tx_done_cleanup_vec(q, free_cnt);
2602 return i40e_tx_done_cleanup_simple(q, free_cnt);
2604 return i40e_tx_done_cleanup_full(q, free_cnt);
2609 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2611 struct i40e_tx_entry *txe;
2612 uint16_t i, prev, size;
2615 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2620 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2621 for (i = 0; i < size; i++)
2622 ((volatile char *)txq->tx_ring)[i] = 0;
2624 prev = (uint16_t)(txq->nb_tx_desc - 1);
2625 for (i = 0; i < txq->nb_tx_desc; i++) {
2626 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2628 txd->cmd_type_offset_bsz =
2629 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2632 txe[prev].next_id = i;
2636 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2637 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2640 txq->nb_tx_used = 0;
2642 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2643 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2646 /* Init the TX queue in hardware */
2648 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2650 enum i40e_status_code err = I40E_SUCCESS;
2651 struct i40e_vsi *vsi = txq->vsi;
2652 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2653 uint16_t pf_q = txq->reg_idx;
2654 struct i40e_hmc_obj_txq tx_ctx;
2657 /* clear the context structure first */
2658 memset(&tx_ctx, 0, sizeof(tx_ctx));
2659 tx_ctx.new_context = 1;
2660 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2661 tx_ctx.qlen = txq->nb_tx_desc;
2663 #ifdef RTE_LIBRTE_IEEE1588
2664 tx_ctx.timesync_ena = 1;
2666 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2667 if (vsi->type == I40E_VSI_FDIR)
2668 tx_ctx.fd_ena = TRUE;
2670 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2671 if (err != I40E_SUCCESS) {
2672 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2676 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2677 if (err != I40E_SUCCESS) {
2678 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2682 /* Now associate this queue with this PCI function */
2683 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2684 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2685 I40E_QTX_CTL_PF_INDX_MASK);
2686 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2687 I40E_WRITE_FLUSH(hw);
2689 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2695 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2697 struct i40e_rx_entry *rxe = rxq->sw_ring;
2701 for (i = 0; i < rxq->nb_rx_desc; i++) {
2702 volatile union i40e_rx_desc *rxd;
2703 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2705 if (unlikely(!mbuf)) {
2706 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2710 rte_mbuf_refcnt_set(mbuf, 1);
2712 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2714 mbuf->port = rxq->port_id;
2717 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2719 rxd = &rxq->rx_ring[i];
2720 rxd->read.pkt_addr = dma_addr;
2721 rxd->read.hdr_addr = 0;
2722 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2723 rxd->read.rsvd1 = 0;
2724 rxd->read.rsvd2 = 0;
2725 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2734 * Calculate the buffer length, and check the jumbo frame
2735 * and maximum packet length.
2738 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2740 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2741 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2742 struct rte_eth_dev_data *data = pf->dev_data;
2745 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2746 RTE_PKTMBUF_HEADROOM);
2748 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2749 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2750 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2751 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2752 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2753 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2754 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2755 rxq->hs_mode = i40e_header_split_enabled;
2757 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2759 rxq->rx_hdr_len = 0;
2760 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2761 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2762 rxq->hs_mode = i40e_header_split_none;
2767 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2768 rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2769 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2770 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
2771 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2772 PMD_DRV_LOG(ERR, "maximum packet length must "
2773 "be larger than %u and smaller than %u,"
2774 "as jumbo frame is enabled",
2775 (uint32_t)RTE_ETHER_MAX_LEN,
2776 (uint32_t)I40E_FRAME_SIZE_MAX);
2777 return I40E_ERR_CONFIG;
2780 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2781 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
2782 PMD_DRV_LOG(ERR, "maximum packet length must be "
2783 "larger than %u and smaller than %u, "
2784 "as jumbo frame is disabled",
2785 (uint32_t)RTE_ETHER_MIN_LEN,
2786 (uint32_t)RTE_ETHER_MAX_LEN);
2787 return I40E_ERR_CONFIG;
2794 /* Init the RX queue in hardware */
2796 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2798 int err = I40E_SUCCESS;
2799 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2800 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2801 uint16_t pf_q = rxq->reg_idx;
2803 struct i40e_hmc_obj_rxq rx_ctx;
2805 err = i40e_rx_queue_config(rxq);
2807 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2811 /* Clear the context structure first */
2812 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2813 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2814 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2816 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2817 rx_ctx.qlen = rxq->nb_rx_desc;
2818 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2821 rx_ctx.dtype = rxq->hs_mode;
2823 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2825 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2826 rx_ctx.rxmax = rxq->max_pkt_len;
2827 rx_ctx.tphrdesc_ena = 1;
2828 rx_ctx.tphwdesc_ena = 1;
2829 rx_ctx.tphdata_ena = 1;
2830 rx_ctx.tphhead_ena = 1;
2831 rx_ctx.lrxqthresh = 2;
2832 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2834 /* showiv indicates if inner VLAN is stripped inside of tunnel
2835 * packet. When set it to 1, vlan information is stripped from
2836 * the inner header, but the hardware does not put it in the
2837 * descriptor. So set it zero by default.
2842 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2843 if (err != I40E_SUCCESS) {
2844 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2847 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2848 if (err != I40E_SUCCESS) {
2849 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2853 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2855 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2856 RTE_PKTMBUF_HEADROOM);
2858 /* Check if scattered RX needs to be used. */
2859 if (rxq->max_pkt_len > buf_size)
2860 dev_data->scattered_rx = 1;
2862 /* Init the RX tail regieter. */
2863 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2869 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2873 PMD_INIT_FUNC_TRACE();
2875 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2876 if (!dev->data->tx_queues[i])
2878 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2879 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2882 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2883 if (!dev->data->rx_queues[i])
2885 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2886 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2891 i40e_dev_free_queues(struct rte_eth_dev *dev)
2895 PMD_INIT_FUNC_TRACE();
2897 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2898 if (!dev->data->rx_queues[i])
2900 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2901 dev->data->rx_queues[i] = NULL;
2904 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2905 if (!dev->data->tx_queues[i])
2907 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2908 dev->data->tx_queues[i] = NULL;
2912 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2913 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2915 enum i40e_status_code
2916 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2918 struct i40e_tx_queue *txq;
2919 const struct rte_memzone *tz = NULL;
2921 struct rte_eth_dev *dev;
2924 PMD_DRV_LOG(ERR, "PF is not available");
2925 return I40E_ERR_BAD_PTR;
2928 dev = pf->adapter->eth_dev;
2930 /* Allocate the TX queue data structure. */
2931 txq = rte_zmalloc_socket("i40e fdir tx queue",
2932 sizeof(struct i40e_tx_queue),
2933 RTE_CACHE_LINE_SIZE,
2936 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2937 "tx queue structure.");
2938 return I40E_ERR_NO_MEMORY;
2941 /* Allocate TX hardware ring descriptors. */
2942 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2943 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2945 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2946 I40E_FDIR_QUEUE_ID, ring_size,
2947 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2949 i40e_dev_tx_queue_release(txq);
2950 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2951 return I40E_ERR_NO_MEMORY;
2954 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2955 txq->queue_id = I40E_FDIR_QUEUE_ID;
2956 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2957 txq->vsi = pf->fdir.fdir_vsi;
2959 txq->tx_ring_phys_addr = tz->iova;
2960 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2962 * don't need to allocate software ring and reset for the fdir
2963 * program queue just set the queue has been configured.
2968 return I40E_SUCCESS;
2971 enum i40e_status_code
2972 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2974 struct i40e_rx_queue *rxq;
2975 const struct rte_memzone *rz = NULL;
2977 struct rte_eth_dev *dev;
2980 PMD_DRV_LOG(ERR, "PF is not available");
2981 return I40E_ERR_BAD_PTR;
2984 dev = pf->adapter->eth_dev;
2986 /* Allocate the RX queue data structure. */
2987 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2988 sizeof(struct i40e_rx_queue),
2989 RTE_CACHE_LINE_SIZE,
2992 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2993 "rx queue structure.");
2994 return I40E_ERR_NO_MEMORY;
2997 /* Allocate RX hardware ring descriptors. */
2998 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2999 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3001 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3002 I40E_FDIR_QUEUE_ID, ring_size,
3003 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3005 i40e_dev_rx_queue_release(rxq);
3006 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3007 return I40E_ERR_NO_MEMORY;
3010 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3011 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3012 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3013 rxq->vsi = pf->fdir.fdir_vsi;
3015 rxq->rx_ring_phys_addr = rz->iova;
3016 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3017 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3020 * Don't need to allocate software ring and reset for the fdir
3021 * rx queue, just set the queue has been configured.
3026 return I40E_SUCCESS;
3030 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3031 struct rte_eth_rxq_info *qinfo)
3033 struct i40e_rx_queue *rxq;
3035 rxq = dev->data->rx_queues[queue_id];
3037 qinfo->mp = rxq->mp;
3038 qinfo->scattered_rx = dev->data->scattered_rx;
3039 qinfo->nb_desc = rxq->nb_rx_desc;
3041 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3042 qinfo->conf.rx_drop_en = rxq->drop_en;
3043 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3044 qinfo->conf.offloads = rxq->offloads;
3048 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3049 struct rte_eth_txq_info *qinfo)
3051 struct i40e_tx_queue *txq;
3053 txq = dev->data->tx_queues[queue_id];
3055 qinfo->nb_desc = txq->nb_tx_desc;
3057 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3058 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3059 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3061 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3062 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3063 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3064 qinfo->conf.offloads = txq->offloads;
3067 static eth_rx_burst_t
3068 i40e_get_latest_rx_vec(bool scatter)
3070 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3071 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3072 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
3073 i40e_recv_pkts_vec_avx2;
3075 return scatter ? i40e_recv_scattered_pkts_vec :
3079 static eth_rx_burst_t
3080 i40e_get_recommend_rx_vec(bool scatter)
3082 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3084 * since AVX frequency can be different to base frequency, limit
3085 * use of AVX2 version to later plaforms, not all those that could
3086 * theoretically run it.
3088 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3089 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
3090 i40e_recv_pkts_vec_avx2;
3092 return scatter ? i40e_recv_scattered_pkts_vec :
3096 void __attribute__((cold))
3097 i40e_set_rx_function(struct rte_eth_dev *dev)
3099 struct i40e_adapter *ad =
3100 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3101 uint16_t rx_using_sse, i;
3102 /* In order to allow Vector Rx there are a few configuration
3103 * conditions to be met and Rx Bulk Allocation should be allowed.
3105 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3106 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3107 !ad->rx_bulk_alloc_allowed) {
3108 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3109 " Vector Rx preconditions",
3110 dev->data->port_id);
3112 ad->rx_vec_allowed = false;
3114 if (ad->rx_vec_allowed) {
3115 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3116 struct i40e_rx_queue *rxq =
3117 dev->data->rx_queues[i];
3119 if (rxq && i40e_rxq_vec_setup(rxq)) {
3120 ad->rx_vec_allowed = false;
3127 if (ad->rx_vec_allowed) {
3129 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
3130 dev->data->port_id);
3131 if (ad->use_latest_vec)
3133 i40e_get_latest_rx_vec(dev->data->scattered_rx);
3136 i40e_get_recommend_rx_vec(dev->data->scattered_rx);
3137 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3138 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3139 "satisfied. Rx Burst Bulk Alloc function "
3140 "will be used on port=%d.",
3141 dev->data->port_id);
3143 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3145 /* Simple Rx Path. */
3146 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3147 dev->data->port_id);
3148 dev->rx_pkt_burst = dev->data->scattered_rx ?
3149 i40e_recv_scattered_pkts :
3153 /* Propagate information about RX function choice through all queues. */
3154 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3156 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3157 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3158 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3159 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3161 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3162 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3165 rxq->rx_using_sse = rx_using_sse;
3170 static const struct {
3171 eth_rx_burst_t pkt_burst;
3173 } i40e_rx_burst_infos[] = {
3174 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3175 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3176 { i40e_recv_pkts, "Scalar" },
3178 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3179 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3180 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3181 { i40e_recv_pkts_vec, "Vector SSE" },
3182 #elif defined(RTE_ARCH_ARM64)
3183 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3184 { i40e_recv_pkts_vec, "Vector Neon" },
3185 #elif defined(RTE_ARCH_PPC_64)
3186 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3187 { i40e_recv_pkts_vec, "Vector AltiVec" },
3192 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3193 struct rte_eth_burst_mode *mode)
3195 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3199 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3200 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3201 snprintf(mode->info, sizeof(mode->info), "%s",
3202 i40e_rx_burst_infos[i].info);
3211 void __attribute__((cold))
3212 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3214 struct i40e_adapter *ad =
3215 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3217 /* Use a simple Tx queue if possible (only fast free is allowed) */
3218 ad->tx_simple_allowed =
3220 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3221 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3222 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3223 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3225 if (ad->tx_vec_allowed)
3226 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3228 else if (ad->tx_simple_allowed)
3229 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3233 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3237 static eth_tx_burst_t
3238 i40e_get_latest_tx_vec(void)
3240 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3241 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3242 return i40e_xmit_pkts_vec_avx2;
3244 return i40e_xmit_pkts_vec;
3247 static eth_tx_burst_t
3248 i40e_get_recommend_tx_vec(void)
3250 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3252 * since AVX frequency can be different to base frequency, limit
3253 * use of AVX2 version to later plaforms, not all those that could
3254 * theoretically run it.
3256 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3257 return i40e_xmit_pkts_vec_avx2;
3259 return i40e_xmit_pkts_vec;
3262 void __attribute__((cold))
3263 i40e_set_tx_function(struct rte_eth_dev *dev)
3265 struct i40e_adapter *ad =
3266 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3269 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3270 if (ad->tx_vec_allowed) {
3271 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3272 struct i40e_tx_queue *txq =
3273 dev->data->tx_queues[i];
3275 if (txq && i40e_txq_vec_setup(txq)) {
3276 ad->tx_vec_allowed = false;
3283 if (ad->tx_simple_allowed) {
3284 if (ad->tx_vec_allowed) {
3285 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3286 if (ad->use_latest_vec)
3288 i40e_get_latest_tx_vec();
3291 i40e_get_recommend_tx_vec();
3293 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3294 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3296 dev->tx_pkt_prepare = NULL;
3298 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3299 dev->tx_pkt_burst = i40e_xmit_pkts;
3300 dev->tx_pkt_prepare = i40e_prep_pkts;
3304 static const struct {
3305 eth_tx_burst_t pkt_burst;
3307 } i40e_tx_burst_infos[] = {
3308 { i40e_xmit_pkts_simple, "Scalar Simple" },
3309 { i40e_xmit_pkts, "Scalar" },
3311 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3312 { i40e_xmit_pkts_vec, "Vector SSE" },
3313 #elif defined(RTE_ARCH_ARM64)
3314 { i40e_xmit_pkts_vec, "Vector Neon" },
3315 #elif defined(RTE_ARCH_PPC_64)
3316 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3321 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3322 struct rte_eth_burst_mode *mode)
3324 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3328 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3329 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3330 snprintf(mode->info, sizeof(mode->info), "%s",
3331 i40e_tx_burst_infos[i].info);
3340 void __attribute__((cold))
3341 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3343 struct i40e_adapter *ad =
3344 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3347 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3348 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3351 void __attribute__((cold))
3352 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3354 struct i40e_adapter *ad =
3355 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3360 ad->pctypes_tbl[i] = 0ULL;
3361 ad->flow_types_mask = 0ULL;
3362 ad->pctypes_mask = 0ULL;
3364 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3365 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3366 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3367 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3368 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3369 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3370 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3371 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3372 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3373 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3374 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3375 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3376 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3377 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3378 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3379 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3380 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3381 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3382 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3383 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3384 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3385 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3387 if (hw->mac.type == I40E_MAC_X722 ||
3388 hw->mac.type == I40E_MAC_X722_VF) {
3389 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3390 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3391 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3392 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3393 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3394 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3395 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3396 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3397 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3398 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3399 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3400 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3403 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3404 if (ad->pctypes_tbl[i])
3405 ad->flow_types_mask |= (1ULL << i);
3406 ad->pctypes_mask |= ad->pctypes_tbl[i];
3410 #ifndef RTE_LIBRTE_I40E_INC_VECTOR
3411 /* Stubs needed for linkage when CONFIG_RTE_LIBRTE_I40E_INC_VECTOR is set to 'n' */
3413 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3420 void __rte_unused *rx_queue,
3421 struct rte_mbuf __rte_unused **rx_pkts,
3422 uint16_t __rte_unused nb_pkts)
3428 i40e_recv_scattered_pkts_vec(
3429 void __rte_unused *rx_queue,
3430 struct rte_mbuf __rte_unused **rx_pkts,
3431 uint16_t __rte_unused nb_pkts)
3437 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3443 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3449 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3455 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3456 struct rte_mbuf __rte_unused **tx_pkts,
3457 uint16_t __rte_unused nb_pkts)
3461 #endif /* ifndef RTE_LIBRTE_I40E_INC_VECTOR */
3463 #ifndef CC_AVX2_SUPPORT
3465 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3466 struct rte_mbuf __rte_unused **rx_pkts,
3467 uint16_t __rte_unused nb_pkts)
3473 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3474 struct rte_mbuf __rte_unused **rx_pkts,
3475 uint16_t __rte_unused nb_pkts)
3481 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3482 struct rte_mbuf __rte_unused **tx_pkts,
3483 uint16_t __rte_unused nb_pkts)
3487 #endif /* ifndef CC_AVX2_SUPPORT */