1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
28 #include "i40e_logs.h"
29 #include "base/i40e_prototype.h"
30 #include "base/i40e_type.h"
31 #include "i40e_ethdev.h"
32 #include "i40e_rxtx.h"
34 #define DEFAULT_TX_RS_THRESH 32
35 #define DEFAULT_TX_FREE_THRESH 32
37 #define I40E_TX_MAX_BURST 32
39 #define I40E_DMA_MEM_ALIGN 4096
41 /* Base address of the HW descriptor ring should be 128B aligned. */
42 #define I40E_RING_BASE_ALIGN 128
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define I40E_TX_IEEE1588_TMST RTE_MBUF_F_TX_IEEE1588_TMST
49 #define I40E_TX_IEEE1588_TMST 0
52 #define I40E_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM | \
53 RTE_MBUF_F_TX_L4_MASK | \
54 RTE_MBUF_F_TX_TCP_SEG | \
55 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
57 #define I40E_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_IPV4 | \
58 RTE_MBUF_F_TX_OUTER_IPV6 | \
59 RTE_MBUF_F_TX_IPV4 | \
60 RTE_MBUF_F_TX_IPV6 | \
61 RTE_MBUF_F_TX_IP_CKSUM | \
62 RTE_MBUF_F_TX_L4_MASK | \
63 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \
64 RTE_MBUF_F_TX_TCP_SEG | \
65 RTE_MBUF_F_TX_QINQ | \
66 RTE_MBUF_F_TX_VLAN | \
67 RTE_MBUF_F_TX_TUNNEL_MASK | \
68 RTE_MBUF_F_TX_OUTER_UDP_CKSUM | \
69 I40E_TX_IEEE1588_TMST)
71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
72 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
74 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK (RTE_MBUF_F_TX_IPV4 | \
75 RTE_MBUF_F_TX_IPV6 | \
76 RTE_MBUF_F_TX_OUTER_IPV4 | \
77 RTE_MBUF_F_TX_OUTER_IPV6)
79 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
80 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
83 i40e_monitor_callback(const uint64_t value,
84 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
86 const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
88 * we expect the DD bit to be set to 1 if this descriptor was already
91 return (value & m) == m ? -1 : 0;
95 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
97 struct i40e_rx_queue *rxq = rx_queue;
98 volatile union i40e_rx_desc *rxdp;
102 rxdp = &rxq->rx_ring[desc];
103 /* watch for changes in status bit */
104 pmc->addr = &rxdp->wb.qword1.status_error_len;
106 /* comparison callback */
107 pmc->fn = i40e_monitor_callback;
109 /* registers are 64-bit */
110 pmc->size = sizeof(uint64_t);
116 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
118 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
119 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
120 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
122 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
123 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
124 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
128 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
129 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
130 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
131 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
132 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
133 mb->vlan_tci_outer = mb->vlan_tci;
134 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
135 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
136 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
137 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
139 mb->vlan_tci_outer = 0;
142 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
143 mb->vlan_tci, mb->vlan_tci_outer);
146 /* Translate the rx descriptor status to pkt flags */
147 static inline uint64_t
148 i40e_rxd_status_to_pkt_flags(uint64_t qword)
152 /* Check if RSS_HASH */
153 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
154 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
155 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
157 /* Check if FDIR Match */
158 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
159 RTE_MBUF_F_RX_FDIR : 0);
164 static inline uint64_t
165 i40e_rxd_error_to_pkt_flags(uint64_t qword)
168 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
170 #define I40E_RX_ERR_BITS 0x3f
171 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
172 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
176 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
177 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
179 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
181 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
182 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
184 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
186 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
187 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
192 /* Function to check and set the ieee1588 timesync index and get the
195 #ifdef RTE_LIBRTE_IEEE1588
196 static inline uint64_t
197 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
199 uint64_t pkt_flags = 0;
200 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
201 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
202 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
204 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
205 == RTE_PTYPE_L2_ETHER_TIMESYNC)
206 pkt_flags = RTE_MBUF_F_RX_IEEE1588_PTP;
208 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
209 mb->timesync = tsyn & 0x03;
216 static inline uint64_t
217 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
220 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
221 uint16_t flexbh, flexbl;
223 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
224 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
225 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
226 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
227 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
228 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
231 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
233 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
234 flags |= RTE_MBUF_F_RX_FDIR_ID;
235 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
237 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
238 flags |= RTE_MBUF_F_RX_FDIR_FLX;
240 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
242 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
243 flags |= RTE_MBUF_F_RX_FDIR_FLX;
247 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
248 flags |= RTE_MBUF_F_RX_FDIR_ID;
254 i40e_parse_tunneling_params(uint64_t ol_flags,
255 union i40e_tx_offload tx_offload,
256 uint32_t *cd_tunneling)
258 /* EIPT: External (outer) IP header type */
259 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
260 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
261 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
262 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
263 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
264 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
266 /* EIPLEN: External (outer) IP header length, in DWords */
267 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
268 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
270 /* L4TUNT: L4 Tunneling Type */
271 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
272 case RTE_MBUF_F_TX_TUNNEL_IPIP:
273 /* for non UDP / GRE tunneling, set to 00b */
275 case RTE_MBUF_F_TX_TUNNEL_VXLAN:
276 case RTE_MBUF_F_TX_TUNNEL_GENEVE:
277 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
279 case RTE_MBUF_F_TX_TUNNEL_GRE:
280 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
283 PMD_TX_LOG(ERR, "Tunnel type not supported");
287 /* L4TUNLEN: L4 Tunneling Length, in Words
289 * We depend on app to set rte_mbuf.l2_len correctly.
290 * For IP in GRE it should be set to the length of the GRE
292 * for MAC in GRE or MAC in UDP it should be set to the length
293 * of the GRE or UDP headers plus the inner MAC up to including
294 * its last Ethertype.
296 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
297 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
301 i40e_txd_enable_checksum(uint64_t ol_flags,
304 union i40e_tx_offload tx_offload)
307 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
308 *td_offset |= (tx_offload.outer_l2_len >> 1)
309 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
311 *td_offset |= (tx_offload.l2_len >> 1)
312 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
314 /* Enable L3 checksum offloads */
315 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
316 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
317 *td_offset |= (tx_offload.l3_len >> 2)
318 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
319 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
320 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
321 *td_offset |= (tx_offload.l3_len >> 2)
322 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
323 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
324 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
325 *td_offset |= (tx_offload.l3_len >> 2)
326 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
329 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
330 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
331 *td_offset |= (tx_offload.l4_len >> 2)
332 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
336 /* Enable L4 checksum offloads */
337 switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
338 case RTE_MBUF_F_TX_TCP_CKSUM:
339 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
340 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
341 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
343 case RTE_MBUF_F_TX_SCTP_CKSUM:
344 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
345 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
346 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
348 case RTE_MBUF_F_TX_UDP_CKSUM:
349 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
350 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
351 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
358 /* Construct the tx flags */
359 static inline uint64_t
360 i40e_build_ctob(uint32_t td_cmd,
365 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
366 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
367 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
368 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
369 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
373 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
375 struct i40e_tx_entry *sw_ring = txq->sw_ring;
376 volatile struct i40e_tx_desc *txd = txq->tx_ring;
377 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
378 uint16_t nb_tx_desc = txq->nb_tx_desc;
379 uint16_t desc_to_clean_to;
380 uint16_t nb_tx_to_clean;
382 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
383 if (desc_to_clean_to >= nb_tx_desc)
384 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
386 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
387 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
388 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
389 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
390 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
391 "(port=%d queue=%d)", desc_to_clean_to,
392 txq->port_id, txq->queue_id);
396 if (last_desc_cleaned > desc_to_clean_to)
397 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
400 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
403 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
405 txq->last_desc_cleaned = desc_to_clean_to;
406 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
413 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
415 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
420 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
421 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
422 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
423 "rxq->rx_free_thresh=%d, "
424 "RTE_PMD_I40E_RX_MAX_BURST=%d",
425 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
427 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
428 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
429 "rxq->rx_free_thresh=%d, "
430 "rxq->nb_rx_desc=%d",
431 rxq->rx_free_thresh, rxq->nb_rx_desc);
433 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
434 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
435 "rxq->nb_rx_desc=%d, "
436 "rxq->rx_free_thresh=%d",
437 rxq->nb_rx_desc, rxq->rx_free_thresh);
447 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
448 #define I40E_LOOK_AHEAD 8
449 #if (I40E_LOOK_AHEAD != 8)
450 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
453 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
455 volatile union i40e_rx_desc *rxdp;
456 struct i40e_rx_entry *rxep;
461 int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
462 int32_t i, j, nb_rx = 0;
464 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
466 rxdp = &rxq->rx_ring[rxq->rx_tail];
467 rxep = &rxq->sw_ring[rxq->rx_tail];
469 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
470 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
471 I40E_RXD_QW1_STATUS_SHIFT;
473 /* Make sure there is at least 1 packet to receive */
474 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
478 * Scan LOOK_AHEAD descriptors at a time to determine which
479 * descriptors reference packets that are ready to be received.
481 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
482 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
483 /* Read desc statuses backwards to avoid race condition */
484 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
485 qword1 = rte_le_to_cpu_64(\
486 rxdp[j].wb.qword1.status_error_len);
487 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
488 I40E_RXD_QW1_STATUS_SHIFT;
491 /* This barrier is to order loads of different words in the descriptor */
492 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
494 /* Compute how many status bits were set */
495 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
496 var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
498 /* For Arm platforms, only compute continuous status bits */
510 /* Translate descriptor info to mbuf parameters */
511 for (j = 0; j < nb_dd; j++) {
513 qword1 = rte_le_to_cpu_64(\
514 rxdp[j].wb.qword1.status_error_len);
515 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
516 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
517 mb->data_len = pkt_len;
518 mb->pkt_len = pkt_len;
520 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
521 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
522 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
524 ptype_tbl[(uint8_t)((qword1 &
525 I40E_RXD_QW1_PTYPE_MASK) >>
526 I40E_RXD_QW1_PTYPE_SHIFT)];
527 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
528 mb->hash.rss = rte_le_to_cpu_32(\
529 rxdp[j].wb.qword0.hi_dword.rss);
530 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
531 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
533 #ifdef RTE_LIBRTE_IEEE1588
534 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
536 mb->ol_flags |= pkt_flags;
540 for (j = 0; j < I40E_LOOK_AHEAD; j++)
541 rxq->rx_stage[i + j] = rxep[j].mbuf;
543 if (nb_dd != I40E_LOOK_AHEAD)
547 /* Clear software ring entries */
548 for (i = 0; i < nb_rx; i++)
549 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
554 static inline uint16_t
555 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
556 struct rte_mbuf **rx_pkts,
560 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
562 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
564 for (i = 0; i < nb_pkts; i++)
565 rx_pkts[i] = stage[i];
567 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
568 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
574 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
576 volatile union i40e_rx_desc *rxdp;
577 struct i40e_rx_entry *rxep;
579 uint16_t alloc_idx, i;
583 /* Allocate buffers in bulk */
584 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
585 (rxq->rx_free_thresh - 1));
586 rxep = &(rxq->sw_ring[alloc_idx]);
587 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
588 rxq->rx_free_thresh);
589 if (unlikely(diag != 0)) {
590 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
594 rxdp = &rxq->rx_ring[alloc_idx];
595 for (i = 0; i < rxq->rx_free_thresh; i++) {
596 if (likely(i < (rxq->rx_free_thresh - 1)))
597 /* Prefetch next mbuf */
598 rte_prefetch0(rxep[i + 1].mbuf);
601 rte_mbuf_refcnt_set(mb, 1);
603 mb->data_off = RTE_PKTMBUF_HEADROOM;
605 mb->port = rxq->port_id;
606 dma_addr = rte_cpu_to_le_64(\
607 rte_mbuf_data_iova_default(mb));
608 rxdp[i].read.hdr_addr = 0;
609 rxdp[i].read.pkt_addr = dma_addr;
612 /* Update rx tail register */
613 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
615 rxq->rx_free_trigger =
616 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
617 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
618 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
623 static inline uint16_t
624 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
626 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
627 struct rte_eth_dev *dev;
633 if (rxq->rx_nb_avail)
634 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
636 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
637 rxq->rx_next_avail = 0;
638 rxq->rx_nb_avail = nb_rx;
639 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
641 if (rxq->rx_tail > rxq->rx_free_trigger) {
642 if (i40e_rx_alloc_bufs(rxq) != 0) {
645 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
646 dev->data->rx_mbuf_alloc_failed +=
649 rxq->rx_nb_avail = 0;
650 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
651 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
652 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
658 if (rxq->rx_tail >= rxq->nb_rx_desc)
661 if (rxq->rx_nb_avail)
662 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
668 i40e_recv_pkts_bulk_alloc(void *rx_queue,
669 struct rte_mbuf **rx_pkts,
672 uint16_t nb_rx = 0, n, count;
674 if (unlikely(nb_pkts == 0))
677 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
678 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
681 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
682 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
683 nb_rx = (uint16_t)(nb_rx + count);
684 nb_pkts = (uint16_t)(nb_pkts - count);
693 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
694 struct rte_mbuf __rte_unused **rx_pkts,
695 uint16_t __rte_unused nb_pkts)
699 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
702 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
704 struct i40e_rx_queue *rxq;
705 volatile union i40e_rx_desc *rx_ring;
706 volatile union i40e_rx_desc *rxdp;
707 union i40e_rx_desc rxd;
708 struct i40e_rx_entry *sw_ring;
709 struct i40e_rx_entry *rxe;
710 struct rte_eth_dev *dev;
711 struct rte_mbuf *rxm;
712 struct rte_mbuf *nmb;
716 uint16_t rx_packet_len;
717 uint16_t rx_id, nb_hold;
725 rx_id = rxq->rx_tail;
726 rx_ring = rxq->rx_ring;
727 sw_ring = rxq->sw_ring;
728 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
730 while (nb_rx < nb_pkts) {
731 rxdp = &rx_ring[rx_id];
732 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
733 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
734 >> I40E_RXD_QW1_STATUS_SHIFT;
736 /* Check the DD bit first */
737 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
740 nmb = rte_mbuf_raw_alloc(rxq->mp);
741 if (unlikely(!nmb)) {
742 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
743 dev->data->rx_mbuf_alloc_failed++;
748 * Use acquire fence to ensure that qword1 which includes DD
749 * bit is loaded before loading of other descriptor words.
751 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
755 rxe = &sw_ring[rx_id];
757 if (unlikely(rx_id == rxq->nb_rx_desc))
760 /* Prefetch next mbuf */
761 rte_prefetch0(sw_ring[rx_id].mbuf);
764 * When next RX descriptor is on a cache line boundary,
765 * prefetch the next 4 RX descriptors and next 8 pointers
768 if ((rx_id & 0x3) == 0) {
769 rte_prefetch0(&rx_ring[rx_id]);
770 rte_prefetch0(&sw_ring[rx_id]);
775 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
776 rxdp->read.hdr_addr = 0;
777 rxdp->read.pkt_addr = dma_addr;
779 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
780 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
782 rxm->data_off = RTE_PKTMBUF_HEADROOM;
783 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
786 rxm->pkt_len = rx_packet_len;
787 rxm->data_len = rx_packet_len;
788 rxm->port = rxq->port_id;
790 i40e_rxd_to_vlan_tci(rxm, &rxd);
791 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
792 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
794 ptype_tbl[(uint8_t)((qword1 &
795 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
796 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
798 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
799 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
800 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
802 #ifdef RTE_LIBRTE_IEEE1588
803 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
805 rxm->ol_flags |= pkt_flags;
807 rx_pkts[nb_rx++] = rxm;
809 rxq->rx_tail = rx_id;
812 * If the number of free RX descriptors is greater than the RX free
813 * threshold of the queue, advance the receive tail register of queue.
814 * Update that register with the value of the last processed RX
815 * descriptor minus 1.
817 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
818 if (nb_hold > rxq->rx_free_thresh) {
819 rx_id = (uint16_t) ((rx_id == 0) ?
820 (rxq->nb_rx_desc - 1) : (rx_id - 1));
821 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
824 rxq->nb_rx_hold = nb_hold;
830 i40e_recv_scattered_pkts(void *rx_queue,
831 struct rte_mbuf **rx_pkts,
834 struct i40e_rx_queue *rxq = rx_queue;
835 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
836 volatile union i40e_rx_desc *rxdp;
837 union i40e_rx_desc rxd;
838 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
839 struct i40e_rx_entry *rxe;
840 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
841 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
842 struct rte_mbuf *nmb, *rxm;
843 uint16_t rx_id = rxq->rx_tail;
844 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
845 struct rte_eth_dev *dev;
850 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
852 while (nb_rx < nb_pkts) {
853 rxdp = &rx_ring[rx_id];
854 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
855 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
856 I40E_RXD_QW1_STATUS_SHIFT;
858 /* Check the DD bit */
859 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
862 nmb = rte_mbuf_raw_alloc(rxq->mp);
863 if (unlikely(!nmb)) {
864 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
865 dev->data->rx_mbuf_alloc_failed++;
870 * Use acquire fence to ensure that qword1 which includes DD
871 * bit is loaded before loading of other descriptor words.
873 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
877 rxe = &sw_ring[rx_id];
879 if (rx_id == rxq->nb_rx_desc)
882 /* Prefetch next mbuf */
883 rte_prefetch0(sw_ring[rx_id].mbuf);
886 * When next RX descriptor is on a cache line boundary,
887 * prefetch the next 4 RX descriptors and next 8 pointers
890 if ((rx_id & 0x3) == 0) {
891 rte_prefetch0(&rx_ring[rx_id]);
892 rte_prefetch0(&sw_ring[rx_id]);
898 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
900 /* Set data buffer address and data length of the mbuf */
901 rxdp->read.hdr_addr = 0;
902 rxdp->read.pkt_addr = dma_addr;
903 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
904 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
905 rxm->data_len = rx_packet_len;
906 rxm->data_off = RTE_PKTMBUF_HEADROOM;
909 * If this is the first buffer of the received packet, set the
910 * pointer to the first mbuf of the packet and initialize its
911 * context. Otherwise, update the total length and the number
912 * of segments of the current scattered packet, and update the
913 * pointer to the last mbuf of the current packet.
917 first_seg->nb_segs = 1;
918 first_seg->pkt_len = rx_packet_len;
921 (uint16_t)(first_seg->pkt_len +
923 first_seg->nb_segs++;
924 last_seg->next = rxm;
928 * If this is not the last buffer of the received packet,
929 * update the pointer to the last mbuf of the current scattered
930 * packet and continue to parse the RX ring.
932 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
938 * This is the last buffer of the received packet. If the CRC
939 * is not stripped by the hardware:
940 * - Subtract the CRC length from the total packet length.
941 * - If the last buffer only contains the whole CRC or a part
942 * of it, free the mbuf associated to the last buffer. If part
943 * of the CRC is also contained in the previous mbuf, subtract
944 * the length of that CRC part from the data length of the
948 if (unlikely(rxq->crc_len > 0)) {
949 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
950 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
951 rte_pktmbuf_free_seg(rxm);
952 first_seg->nb_segs--;
954 (uint16_t)(last_seg->data_len -
955 (RTE_ETHER_CRC_LEN - rx_packet_len));
956 last_seg->next = NULL;
958 rxm->data_len = (uint16_t)(rx_packet_len -
962 first_seg->port = rxq->port_id;
963 first_seg->ol_flags = 0;
964 i40e_rxd_to_vlan_tci(first_seg, &rxd);
965 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
966 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
967 first_seg->packet_type =
968 ptype_tbl[(uint8_t)((qword1 &
969 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
970 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
971 first_seg->hash.rss =
972 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
973 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
974 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
976 #ifdef RTE_LIBRTE_IEEE1588
977 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
979 first_seg->ol_flags |= pkt_flags;
981 /* Prefetch data of first segment, if configured to do so. */
982 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
983 first_seg->data_off));
984 rx_pkts[nb_rx++] = first_seg;
988 /* Record index of the next RX descriptor to probe. */
989 rxq->rx_tail = rx_id;
990 rxq->pkt_first_seg = first_seg;
991 rxq->pkt_last_seg = last_seg;
994 * If the number of free RX descriptors is greater than the RX free
995 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
996 * register. Update the RDT with the value of the last processed RX
997 * descriptor minus 1, to guarantee that the RDT register is never
998 * equal to the RDH register, which creates a "full" ring situation
999 * from the hardware point of view.
1001 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1002 if (nb_hold > rxq->rx_free_thresh) {
1003 rx_id = (uint16_t)(rx_id == 0 ?
1004 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1005 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1008 rxq->nb_rx_hold = nb_hold;
1013 /* Check if the context descriptor is needed for TX offloading */
1014 static inline uint16_t
1015 i40e_calc_context_desc(uint64_t flags)
1017 static uint64_t mask = RTE_MBUF_F_TX_OUTER_IP_CKSUM |
1018 RTE_MBUF_F_TX_TCP_SEG |
1019 RTE_MBUF_F_TX_QINQ |
1020 RTE_MBUF_F_TX_TUNNEL_MASK;
1022 #ifdef RTE_LIBRTE_IEEE1588
1023 mask |= RTE_MBUF_F_TX_IEEE1588_TMST;
1026 return (flags & mask) ? 1 : 0;
1029 /* set i40e TSO context descriptor */
1030 static inline uint64_t
1031 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1033 uint64_t ctx_desc = 0;
1034 uint32_t cd_cmd, hdr_len, cd_tso_len;
1036 if (!tx_offload.l4_len) {
1037 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1041 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1042 hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
1043 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1045 cd_cmd = I40E_TX_CTX_DESC_TSO;
1046 cd_tso_len = mbuf->pkt_len - hdr_len;
1047 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1048 ((uint64_t)cd_tso_len <<
1049 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1050 ((uint64_t)mbuf->tso_segsz <<
1051 I40E_TXD_CTX_QW1_MSS_SHIFT);
1056 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1057 #define I40E_MAX_DATA_PER_TXD \
1058 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1059 /* Calculate the number of TX descriptors needed for each pkt */
1060 static inline uint16_t
1061 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1063 struct rte_mbuf *txd = tx_pkt;
1066 while (txd != NULL) {
1067 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1075 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1077 struct i40e_tx_queue *txq;
1078 struct i40e_tx_entry *sw_ring;
1079 struct i40e_tx_entry *txe, *txn;
1080 volatile struct i40e_tx_desc *txd;
1081 volatile struct i40e_tx_desc *txr;
1082 struct rte_mbuf *tx_pkt;
1083 struct rte_mbuf *m_seg;
1084 uint32_t cd_tunneling_params;
1095 uint64_t buf_dma_addr;
1096 union i40e_tx_offload tx_offload = {0};
1099 sw_ring = txq->sw_ring;
1101 tx_id = txq->tx_tail;
1102 txe = &sw_ring[tx_id];
1104 /* Check if the descriptor ring needs to be cleaned. */
1105 if (txq->nb_tx_free < txq->tx_free_thresh)
1106 (void)i40e_xmit_cleanup(txq);
1108 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1113 tx_pkt = *tx_pkts++;
1114 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1116 ol_flags = tx_pkt->ol_flags;
1117 tx_offload.l2_len = tx_pkt->l2_len;
1118 tx_offload.l3_len = tx_pkt->l3_len;
1119 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1120 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1121 tx_offload.l4_len = tx_pkt->l4_len;
1122 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1124 /* Calculate the number of context descriptors needed. */
1125 nb_ctx = i40e_calc_context_desc(ol_flags);
1128 * The number of descriptors that must be allocated for
1129 * a packet equals to the number of the segments of that
1130 * packet plus 1 context descriptor if needed.
1131 * Recalculate the needed tx descs when TSO enabled in case
1132 * the mbuf data size exceeds max data size that hw allows
1135 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1136 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1139 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1140 tx_last = (uint16_t)(tx_id + nb_used - 1);
1143 if (tx_last >= txq->nb_tx_desc)
1144 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1146 if (nb_used > txq->nb_tx_free) {
1147 if (i40e_xmit_cleanup(txq) != 0) {
1152 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1153 while (nb_used > txq->nb_tx_free) {
1154 if (i40e_xmit_cleanup(txq) != 0) {
1163 /* Descriptor based VLAN insertion */
1164 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
1165 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1166 td_tag = tx_pkt->vlan_tci;
1169 /* Always enable CRC offload insertion */
1170 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1172 /* Fill in tunneling parameters if necessary */
1173 cd_tunneling_params = 0;
1174 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
1175 i40e_parse_tunneling_params(ol_flags, tx_offload,
1176 &cd_tunneling_params);
1177 /* Enable checksum offloading */
1178 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1179 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1180 &td_offset, tx_offload);
1183 /* Setup TX context descriptor if required */
1184 volatile struct i40e_tx_context_desc *ctx_txd =
1185 (volatile struct i40e_tx_context_desc *)\
1187 uint16_t cd_l2tag2 = 0;
1188 uint64_t cd_type_cmd_tso_mss =
1189 I40E_TX_DESC_DTYPE_CONTEXT;
1191 txn = &sw_ring[txe->next_id];
1192 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1193 if (txe->mbuf != NULL) {
1194 rte_pktmbuf_free_seg(txe->mbuf);
1198 /* TSO enabled means no timestamp */
1199 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1200 cd_type_cmd_tso_mss |=
1201 i40e_set_tso_ctx(tx_pkt, tx_offload);
1203 #ifdef RTE_LIBRTE_IEEE1588
1204 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
1205 cd_type_cmd_tso_mss |=
1206 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1207 I40E_TXD_CTX_QW1_CMD_SHIFT);
1211 ctx_txd->tunneling_params =
1212 rte_cpu_to_le_32(cd_tunneling_params);
1213 if (ol_flags & RTE_MBUF_F_TX_QINQ) {
1214 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1215 cd_type_cmd_tso_mss |=
1216 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1217 I40E_TXD_CTX_QW1_CMD_SHIFT);
1219 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1220 ctx_txd->type_cmd_tso_mss =
1221 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1223 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1224 "tunneling_params: %#x;\n"
1227 "type_cmd_tso_mss: %#"PRIx64";\n",
1229 ctx_txd->tunneling_params,
1232 ctx_txd->type_cmd_tso_mss);
1234 txe->last_id = tx_last;
1235 tx_id = txe->next_id;
1242 txn = &sw_ring[txe->next_id];
1245 rte_pktmbuf_free_seg(txe->mbuf);
1248 /* Setup TX Descriptor */
1249 slen = m_seg->data_len;
1250 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1252 while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
1253 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1255 rte_cpu_to_le_64(buf_dma_addr);
1256 txd->cmd_type_offset_bsz =
1257 i40e_build_ctob(td_cmd,
1258 td_offset, I40E_MAX_DATA_PER_TXD,
1261 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1262 slen -= I40E_MAX_DATA_PER_TXD;
1264 txe->last_id = tx_last;
1265 tx_id = txe->next_id;
1268 txn = &sw_ring[txe->next_id];
1270 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1271 "buf_dma_addr: %#"PRIx64";\n"
1276 tx_pkt, tx_id, buf_dma_addr,
1277 td_cmd, td_offset, slen, td_tag);
1279 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1280 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1281 td_offset, slen, td_tag);
1282 txe->last_id = tx_last;
1283 tx_id = txe->next_id;
1285 m_seg = m_seg->next;
1286 } while (m_seg != NULL);
1288 /* The last packet data descriptor needs End Of Packet (EOP) */
1289 td_cmd |= I40E_TX_DESC_CMD_EOP;
1290 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1291 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1293 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1295 "Setting RS bit on TXD id="
1296 "%4u (port=%d queue=%d)",
1297 tx_last, txq->port_id, txq->queue_id);
1299 td_cmd |= I40E_TX_DESC_CMD_RS;
1301 /* Update txq RS bit counters */
1302 txq->nb_tx_used = 0;
1305 txd->cmd_type_offset_bsz |=
1306 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1307 I40E_TXD_QW1_CMD_SHIFT);
1311 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1312 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1313 (unsigned) tx_id, (unsigned) nb_tx);
1316 I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1317 txq->tx_tail = tx_id;
1322 static __rte_always_inline int
1323 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1325 struct i40e_tx_entry *txep;
1326 uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1327 uint16_t i = 0, j = 0;
1328 struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1329 const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1330 const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1332 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1333 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1334 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1337 txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1339 for (i = 0; i < tx_rs_thresh; i++)
1340 rte_prefetch0((txep + i)->mbuf);
1342 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
1344 for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1345 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1346 free[i] = txep->mbuf;
1349 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1350 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1355 for (i = 0; i < m; ++i, ++txep) {
1356 free[i] = txep->mbuf;
1359 rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1362 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1363 rte_pktmbuf_free_seg(txep->mbuf);
1368 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1369 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1370 if (txq->tx_next_dd >= txq->nb_tx_desc)
1371 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1373 return txq->tx_rs_thresh;
1376 /* Populate 4 descriptors with data from 4 mbufs */
1378 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1383 for (i = 0; i < 4; i++, txdp++, pkts++) {
1384 dma_addr = rte_mbuf_data_iova(*pkts);
1385 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1386 txdp->cmd_type_offset_bsz =
1387 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1388 (*pkts)->data_len, 0);
1392 /* Populate 1 descriptor with data from 1 mbuf */
1394 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1398 dma_addr = rte_mbuf_data_iova(*pkts);
1399 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1400 txdp->cmd_type_offset_bsz =
1401 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1402 (*pkts)->data_len, 0);
1405 /* Fill hardware descriptor ring with mbuf data */
1407 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1408 struct rte_mbuf **pkts,
1411 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1412 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1413 const int N_PER_LOOP = 4;
1414 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1415 int mainpart, leftover;
1418 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1419 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1420 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1421 for (j = 0; j < N_PER_LOOP; ++j) {
1422 (txep + i + j)->mbuf = *(pkts + i + j);
1424 tx4(txdp + i, pkts + i);
1426 if (unlikely(leftover > 0)) {
1427 for (i = 0; i < leftover; ++i) {
1428 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1429 tx1(txdp + mainpart + i, pkts + mainpart + i);
1434 static inline uint16_t
1435 tx_xmit_pkts(struct i40e_tx_queue *txq,
1436 struct rte_mbuf **tx_pkts,
1439 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1443 * Begin scanning the H/W ring for done descriptors when the number
1444 * of available descriptors drops below tx_free_thresh. For each done
1445 * descriptor, free the associated buffer.
1447 if (txq->nb_tx_free < txq->tx_free_thresh)
1448 i40e_tx_free_bufs(txq);
1450 /* Use available descriptor only */
1451 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1452 if (unlikely(!nb_pkts))
1455 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1456 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1457 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1458 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1459 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1460 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1461 I40E_TXD_QW1_CMD_SHIFT);
1462 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1466 /* Fill hardware descriptor ring with mbuf data */
1467 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1468 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1470 /* Determine if RS bit needs to be set */
1471 if (txq->tx_tail > txq->tx_next_rs) {
1472 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1473 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1474 I40E_TXD_QW1_CMD_SHIFT);
1476 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1477 if (txq->tx_next_rs >= txq->nb_tx_desc)
1478 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1481 if (txq->tx_tail >= txq->nb_tx_desc)
1484 /* Update the tx tail register */
1485 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1491 i40e_xmit_pkts_simple(void *tx_queue,
1492 struct rte_mbuf **tx_pkts,
1497 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1498 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1502 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1505 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1506 &tx_pkts[nb_tx], num);
1507 nb_tx = (uint16_t)(nb_tx + ret);
1508 nb_pkts = (uint16_t)(nb_pkts - ret);
1517 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1521 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1526 /* cross rs_thresh boundary is not allowed */
1527 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1528 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1539 /*********************************************************************
1541 * TX simple prep functions
1543 **********************************************************************/
1545 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1552 for (i = 0; i < nb_pkts; i++) {
1554 ol_flags = m->ol_flags;
1556 if (m->nb_segs != 1) {
1561 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1562 rte_errno = ENOTSUP;
1566 /* check the size of packet */
1567 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1568 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1576 /*********************************************************************
1580 **********************************************************************/
1582 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1589 for (i = 0; i < nb_pkts; i++) {
1591 ol_flags = m->ol_flags;
1593 /* Check for m->nb_segs to not exceed the limits. */
1594 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
1595 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1596 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1600 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1601 m->tso_segsz < I40E_MIN_TSO_MSS ||
1602 m->tso_segsz > I40E_MAX_TSO_MSS ||
1603 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1604 /* MSS outside the range (256B - 9674B) are considered
1611 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1612 rte_errno = ENOTSUP;
1616 /* check the size of packet */
1617 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1622 #ifdef RTE_ETHDEV_DEBUG_TX
1623 ret = rte_validate_tx_offload(m);
1629 ret = rte_net_intel_cksum_prepare(m);
1639 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1640 * application used, which assume having sequential ones. But from driver's
1641 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1642 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1643 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1644 * use queue_idx from 0 to 95 to access queues, while real queue would be
1645 * different. This function will do a queue mapping to find VSI the queue
1648 static struct i40e_vsi*
1649 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1651 /* the queue in MAIN VSI range */
1652 if (queue_idx < pf->main_vsi->nb_qps)
1653 return pf->main_vsi;
1655 queue_idx -= pf->main_vsi->nb_qps;
1657 /* queue_idx is greater than VMDQ VSIs range */
1658 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1659 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1663 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1667 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1669 /* the queue in MAIN VSI range */
1670 if (queue_idx < pf->main_vsi->nb_qps)
1673 /* It's VMDQ queues */
1674 queue_idx -= pf->main_vsi->nb_qps;
1676 if (pf->nb_cfg_vmdq_vsi)
1677 return queue_idx % pf->vmdq_nb_qps;
1679 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1680 return (uint16_t)(-1);
1685 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1687 struct i40e_rx_queue *rxq;
1689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 PMD_INIT_FUNC_TRACE();
1693 rxq = dev->data->rx_queues[rx_queue_id];
1694 if (!rxq || !rxq->q_set) {
1695 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1700 if (rxq->rx_deferred_start)
1701 PMD_DRV_LOG(WARNING, "RX queue %u is deferred start",
1704 err = i40e_alloc_rx_queue_mbufs(rxq);
1706 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1710 /* Init the RX tail register. */
1711 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1713 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1715 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1718 i40e_rx_queue_release_mbufs(rxq);
1719 i40e_reset_rx_queue(rxq);
1722 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1728 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1730 struct i40e_rx_queue *rxq;
1732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734 rxq = dev->data->rx_queues[rx_queue_id];
1735 if (!rxq || !rxq->q_set) {
1736 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1742 * rx_queue_id is queue id application refers to, while
1743 * rxq->reg_idx is the real queue index.
1745 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1747 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1751 i40e_rx_queue_release_mbufs(rxq);
1752 i40e_reset_rx_queue(rxq);
1753 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1759 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1762 struct i40e_tx_queue *txq;
1763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1765 PMD_INIT_FUNC_TRACE();
1767 txq = dev->data->tx_queues[tx_queue_id];
1768 if (!txq || !txq->q_set) {
1769 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1774 if (txq->tx_deferred_start)
1775 PMD_DRV_LOG(WARNING, "TX queue %u is deferred start",
1779 * tx_queue_id is queue id application refers to, while
1780 * rxq->reg_idx is the real queue index.
1782 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1784 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1788 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1794 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1796 struct i40e_tx_queue *txq;
1798 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800 txq = dev->data->tx_queues[tx_queue_id];
1801 if (!txq || !txq->q_set) {
1802 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1808 * tx_queue_id is queue id application refers to, while
1809 * txq->reg_idx is the real queue index.
1811 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1813 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1818 i40e_tx_queue_release_mbufs(txq);
1819 i40e_reset_tx_queue(txq);
1820 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1826 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1828 static const uint32_t ptypes[] = {
1829 /* refers to i40e_rxd_pkt_type_mapping() */
1831 RTE_PTYPE_L2_ETHER_TIMESYNC,
1832 RTE_PTYPE_L2_ETHER_LLDP,
1833 RTE_PTYPE_L2_ETHER_ARP,
1834 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1835 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1838 RTE_PTYPE_L4_NONFRAG,
1842 RTE_PTYPE_TUNNEL_GRENAT,
1843 RTE_PTYPE_TUNNEL_IP,
1844 RTE_PTYPE_INNER_L2_ETHER,
1845 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1846 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1847 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1848 RTE_PTYPE_INNER_L4_FRAG,
1849 RTE_PTYPE_INNER_L4_ICMP,
1850 RTE_PTYPE_INNER_L4_NONFRAG,
1851 RTE_PTYPE_INNER_L4_SCTP,
1852 RTE_PTYPE_INNER_L4_TCP,
1853 RTE_PTYPE_INNER_L4_UDP,
1857 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1858 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1859 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1861 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1862 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1863 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1864 #ifdef CC_AVX512_SUPPORT
1865 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1866 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1868 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1869 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1875 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1879 for (i = 0; i < num; i++) {
1880 if (i != idx && queues[i])
1888 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1889 struct i40e_rx_queue *rxq)
1891 struct i40e_adapter *ad =
1892 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1893 int use_def_burst_func =
1894 check_rx_burst_bulk_alloc_preconditions(rxq);
1896 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1897 RTE_PKTMBUF_HEADROOM);
1898 int use_scattered_rx =
1899 (rxq->max_pkt_len > buf_size);
1901 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1903 "Failed to do RX queue initialization");
1907 if (i40e_dev_first_queue(rxq->queue_id,
1908 dev->data->rx_queues,
1909 dev->data->nb_rx_queues)) {
1911 * If it is the first queue to setup,
1912 * set all flags to default and call
1913 * i40e_set_rx_function.
1915 ad->rx_bulk_alloc_allowed = true;
1916 ad->rx_vec_allowed = true;
1917 dev->data->scattered_rx = use_scattered_rx;
1918 if (use_def_burst_func)
1919 ad->rx_bulk_alloc_allowed = false;
1920 i40e_set_rx_function(dev);
1922 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1923 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1924 " number %d of queue %d isn't power of 2",
1925 rxq->nb_rx_desc, rxq->queue_id);
1929 /* check bulk alloc conflict */
1930 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1931 PMD_DRV_LOG(ERR, "Can't use default burst.");
1934 /* check scattered conflict */
1935 if (!dev->data->scattered_rx && use_scattered_rx) {
1936 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1939 /* check vector conflict */
1940 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1941 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1949 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1952 unsigned int socket_id,
1953 const struct rte_eth_rxconf *rx_conf,
1954 struct rte_mempool *mp)
1956 struct i40e_adapter *ad =
1957 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1958 struct i40e_vsi *vsi;
1959 struct i40e_pf *pf = NULL;
1960 struct i40e_rx_queue *rxq;
1961 const struct rte_memzone *rz;
1964 uint16_t reg_idx, base, bsf, tc_mapping;
1965 int q_offset, use_def_burst_func = 1;
1968 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1970 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1971 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1974 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1977 reg_idx = vsi->base_queue + q_offset;
1979 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1980 (nb_desc > I40E_MAX_RING_DESC) ||
1981 (nb_desc < I40E_MIN_RING_DESC)) {
1982 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1983 "invalid", nb_desc);
1987 /* Free memory if needed */
1988 if (dev->data->rx_queues[queue_idx]) {
1989 i40e_rx_queue_release(dev->data->rx_queues[queue_idx]);
1990 dev->data->rx_queues[queue_idx] = NULL;
1993 /* Allocate the rx queue data structure */
1994 rxq = rte_zmalloc_socket("i40e rx queue",
1995 sizeof(struct i40e_rx_queue),
1996 RTE_CACHE_LINE_SIZE,
1999 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2000 "rx queue data structure");
2004 rxq->nb_rx_desc = nb_desc;
2005 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2006 rxq->queue_id = queue_idx;
2007 rxq->reg_idx = reg_idx;
2008 rxq->port_id = dev->data->port_id;
2009 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2010 rxq->crc_len = RTE_ETHER_CRC_LEN;
2013 rxq->drop_en = rx_conf->rx_drop_en;
2015 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2016 rxq->offloads = offloads;
2018 /* Allocate the maximum number of RX ring hardware descriptor. */
2019 len = I40E_MAX_RING_DESC;
2022 * Allocating a little more memory because vectorized/bulk_alloc Rx
2023 * functions doesn't check boundaries each time.
2025 len += RTE_PMD_I40E_RX_MAX_BURST;
2027 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2028 I40E_DMA_MEM_ALIGN);
2030 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2031 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2033 i40e_rx_queue_release(rxq);
2034 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2039 /* Zero all the descriptors in the ring. */
2040 memset(rz->addr, 0, ring_size);
2042 rxq->rx_ring_phys_addr = rz->iova;
2043 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2045 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2047 /* Allocate the software ring. */
2049 rte_zmalloc_socket("i40e rx sw ring",
2050 sizeof(struct i40e_rx_entry) * len,
2051 RTE_CACHE_LINE_SIZE,
2053 if (!rxq->sw_ring) {
2054 i40e_rx_queue_release(rxq);
2055 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2059 i40e_reset_rx_queue(rxq);
2062 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2063 if (!(vsi->enabled_tc & (1 << i)))
2065 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2066 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2067 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2068 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2069 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2071 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2075 if (dev->data->dev_started) {
2076 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2077 i40e_rx_queue_release(rxq);
2081 use_def_burst_func =
2082 check_rx_burst_bulk_alloc_preconditions(rxq);
2083 if (!use_def_burst_func) {
2084 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2086 "Rx Burst Bulk Alloc Preconditions are "
2087 "satisfied. Rx Burst Bulk Alloc function will be "
2088 "used on port=%d, queue=%d.",
2089 rxq->port_id, rxq->queue_id);
2090 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2093 "Rx Burst Bulk Alloc Preconditions are "
2094 "not satisfied, Scattered Rx is requested, "
2095 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2096 "not enabled on port=%d, queue=%d.",
2097 rxq->port_id, rxq->queue_id);
2098 ad->rx_bulk_alloc_allowed = false;
2102 dev->data->rx_queues[queue_idx] = rxq;
2107 i40e_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2109 i40e_rx_queue_release(dev->data->rx_queues[qid]);
2113 i40e_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2115 i40e_tx_queue_release(dev->data->tx_queues[qid]);
2119 i40e_rx_queue_release(void *rxq)
2121 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2124 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2128 i40e_rx_queue_release_mbufs(q);
2129 rte_free(q->sw_ring);
2130 rte_memzone_free(q->mz);
2135 i40e_dev_rx_queue_count(void *rx_queue)
2137 #define I40E_RXQ_SCAN_INTERVAL 4
2138 volatile union i40e_rx_desc *rxdp;
2139 struct i40e_rx_queue *rxq;
2143 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2144 while ((desc < rxq->nb_rx_desc) &&
2145 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2146 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2147 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2149 * Check the DD bit of a rx descriptor of each 4 in a group,
2150 * to avoid checking too frequently and downgrading performance
2153 desc += I40E_RXQ_SCAN_INTERVAL;
2154 rxdp += I40E_RXQ_SCAN_INTERVAL;
2155 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2156 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2157 desc - rxq->nb_rx_desc]);
2164 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2166 struct i40e_rx_queue *rxq = rx_queue;
2167 volatile uint64_t *status;
2171 if (unlikely(offset >= rxq->nb_rx_desc))
2174 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2175 return RTE_ETH_RX_DESC_UNAVAIL;
2177 desc = rxq->rx_tail + offset;
2178 if (desc >= rxq->nb_rx_desc)
2179 desc -= rxq->nb_rx_desc;
2181 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2182 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2183 << I40E_RXD_QW1_STATUS_SHIFT);
2185 return RTE_ETH_RX_DESC_DONE;
2187 return RTE_ETH_RX_DESC_AVAIL;
2191 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2193 struct i40e_tx_queue *txq = tx_queue;
2194 volatile uint64_t *status;
2195 uint64_t mask, expect;
2198 if (unlikely(offset >= txq->nb_tx_desc))
2201 desc = txq->tx_tail + offset;
2202 /* go to next desc that has the RS bit */
2203 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2205 if (desc >= txq->nb_tx_desc) {
2206 desc -= txq->nb_tx_desc;
2207 if (desc >= txq->nb_tx_desc)
2208 desc -= txq->nb_tx_desc;
2211 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2212 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2213 expect = rte_cpu_to_le_64(
2214 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2215 if ((*status & mask) == expect)
2216 return RTE_ETH_TX_DESC_DONE;
2218 return RTE_ETH_TX_DESC_FULL;
2222 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2223 struct i40e_tx_queue *txq)
2225 struct i40e_adapter *ad =
2226 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2228 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2230 "Failed to do TX queue initialization");
2234 if (i40e_dev_first_queue(txq->queue_id,
2235 dev->data->tx_queues,
2236 dev->data->nb_tx_queues)) {
2238 * If it is the first queue to setup,
2239 * set all flags and call
2240 * i40e_set_tx_function.
2242 i40e_set_tx_function_flag(dev, txq);
2243 i40e_set_tx_function(dev);
2247 /* check vector conflict */
2248 if (ad->tx_vec_allowed) {
2249 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2250 i40e_txq_vec_setup(txq)) {
2251 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2255 /* check simple tx conflict */
2256 if (ad->tx_simple_allowed) {
2257 if ((txq->offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2258 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2259 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2268 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2271 unsigned int socket_id,
2272 const struct rte_eth_txconf *tx_conf)
2274 struct i40e_vsi *vsi;
2275 struct i40e_pf *pf = NULL;
2276 struct i40e_tx_queue *txq;
2277 const struct rte_memzone *tz;
2279 uint16_t tx_rs_thresh, tx_free_thresh;
2280 uint16_t reg_idx, i, base, bsf, tc_mapping;
2284 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2286 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2287 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2290 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2293 reg_idx = vsi->base_queue + q_offset;
2295 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2296 (nb_desc > I40E_MAX_RING_DESC) ||
2297 (nb_desc < I40E_MIN_RING_DESC)) {
2298 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2299 "invalid", nb_desc);
2304 * The following two parameters control the setting of the RS bit on
2305 * transmit descriptors. TX descriptors will have their RS bit set
2306 * after txq->tx_rs_thresh descriptors have been used. The TX
2307 * descriptor ring will be cleaned after txq->tx_free_thresh
2308 * descriptors are used or if the number of descriptors required to
2309 * transmit a packet is greater than the number of free TX descriptors.
2311 * The following constraints must be satisfied:
2312 * - tx_rs_thresh must be greater than 0.
2313 * - tx_rs_thresh must be less than the size of the ring minus 2.
2314 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2315 * - tx_rs_thresh must be a divisor of the ring size.
2316 * - tx_free_thresh must be greater than 0.
2317 * - tx_free_thresh must be less than the size of the ring minus 3.
2318 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2320 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2321 * race condition, hence the maximum threshold constraints. When set
2322 * to zero use default values.
2324 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2325 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2326 /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
2327 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2328 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2329 if (tx_conf->tx_rs_thresh > 0)
2330 tx_rs_thresh = tx_conf->tx_rs_thresh;
2331 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2332 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2333 "exceed nb_desc. (tx_rs_thresh=%u "
2334 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2335 (unsigned int)tx_rs_thresh,
2336 (unsigned int)tx_free_thresh,
2337 (unsigned int)nb_desc,
2338 (int)dev->data->port_id,
2340 return I40E_ERR_PARAM;
2342 if (tx_rs_thresh >= (nb_desc - 2)) {
2343 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2344 "number of TX descriptors minus 2. "
2345 "(tx_rs_thresh=%u port=%d queue=%d)",
2346 (unsigned int)tx_rs_thresh,
2347 (int)dev->data->port_id,
2349 return I40E_ERR_PARAM;
2351 if (tx_free_thresh >= (nb_desc - 3)) {
2352 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2353 "number of TX descriptors minus 3. "
2354 "(tx_free_thresh=%u port=%d queue=%d)",
2355 (unsigned int)tx_free_thresh,
2356 (int)dev->data->port_id,
2358 return I40E_ERR_PARAM;
2360 if (tx_rs_thresh > tx_free_thresh) {
2361 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2362 "equal to tx_free_thresh. (tx_free_thresh=%u"
2363 " tx_rs_thresh=%u port=%d queue=%d)",
2364 (unsigned int)tx_free_thresh,
2365 (unsigned int)tx_rs_thresh,
2366 (int)dev->data->port_id,
2368 return I40E_ERR_PARAM;
2370 if ((nb_desc % tx_rs_thresh) != 0) {
2371 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2372 "number of TX descriptors. (tx_rs_thresh=%u"
2373 " port=%d queue=%d)",
2374 (unsigned int)tx_rs_thresh,
2375 (int)dev->data->port_id,
2377 return I40E_ERR_PARAM;
2379 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2380 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2381 "tx_rs_thresh is greater than 1. "
2382 "(tx_rs_thresh=%u port=%d queue=%d)",
2383 (unsigned int)tx_rs_thresh,
2384 (int)dev->data->port_id,
2386 return I40E_ERR_PARAM;
2389 /* Free memory if needed. */
2390 if (dev->data->tx_queues[queue_idx]) {
2391 i40e_tx_queue_release(dev->data->tx_queues[queue_idx]);
2392 dev->data->tx_queues[queue_idx] = NULL;
2395 /* Allocate the TX queue data structure. */
2396 txq = rte_zmalloc_socket("i40e tx queue",
2397 sizeof(struct i40e_tx_queue),
2398 RTE_CACHE_LINE_SIZE,
2401 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2402 "tx queue structure");
2406 /* Allocate TX hardware ring descriptors. */
2407 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2408 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2409 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2410 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2412 i40e_tx_queue_release(txq);
2413 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2418 txq->nb_tx_desc = nb_desc;
2419 txq->tx_rs_thresh = tx_rs_thresh;
2420 txq->tx_free_thresh = tx_free_thresh;
2421 txq->pthresh = tx_conf->tx_thresh.pthresh;
2422 txq->hthresh = tx_conf->tx_thresh.hthresh;
2423 txq->wthresh = tx_conf->tx_thresh.wthresh;
2424 txq->queue_id = queue_idx;
2425 txq->reg_idx = reg_idx;
2426 txq->port_id = dev->data->port_id;
2427 txq->offloads = offloads;
2429 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2431 txq->tx_ring_phys_addr = tz->iova;
2432 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2434 /* Allocate software ring */
2436 rte_zmalloc_socket("i40e tx sw ring",
2437 sizeof(struct i40e_tx_entry) * nb_desc,
2438 RTE_CACHE_LINE_SIZE,
2440 if (!txq->sw_ring) {
2441 i40e_tx_queue_release(txq);
2442 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2446 i40e_reset_tx_queue(txq);
2449 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2450 if (!(vsi->enabled_tc & (1 << i)))
2452 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2453 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2454 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2455 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2456 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2458 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2462 if (dev->data->dev_started) {
2463 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2464 i40e_tx_queue_release(txq);
2469 * Use a simple TX queue without offloads or
2470 * multi segs if possible
2472 i40e_set_tx_function_flag(dev, txq);
2474 dev->data->tx_queues[queue_idx] = txq;
2480 i40e_tx_queue_release(void *txq)
2482 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2485 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2489 i40e_tx_queue_release_mbufs(q);
2490 rte_free(q->sw_ring);
2491 rte_memzone_free(q->mz);
2495 const struct rte_memzone *
2496 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2498 const struct rte_memzone *mz;
2500 mz = rte_memzone_lookup(name);
2504 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2505 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2510 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2514 /* SSE Vector driver has a different way of releasing mbufs. */
2515 if (rxq->rx_using_sse) {
2516 i40e_rx_queue_release_mbufs_vec(rxq);
2520 if (!rxq->sw_ring) {
2521 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2525 for (i = 0; i < rxq->nb_rx_desc; i++) {
2526 if (rxq->sw_ring[i].mbuf) {
2527 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2528 rxq->sw_ring[i].mbuf = NULL;
2531 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2532 if (rxq->rx_nb_avail == 0)
2534 for (i = 0; i < rxq->rx_nb_avail; i++) {
2535 struct rte_mbuf *mbuf;
2537 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2538 rte_pktmbuf_free_seg(mbuf);
2540 rxq->rx_nb_avail = 0;
2541 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2545 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2551 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2555 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2556 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2557 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2559 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2560 len = rxq->nb_rx_desc;
2562 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2563 ((volatile char *)rxq->rx_ring)[i] = 0;
2565 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2566 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2567 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2569 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2570 rxq->rx_nb_avail = 0;
2571 rxq->rx_next_avail = 0;
2572 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2573 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2575 rxq->nb_rx_hold = 0;
2577 rte_pktmbuf_free(rxq->pkt_first_seg);
2579 rxq->pkt_first_seg = NULL;
2580 rxq->pkt_last_seg = NULL;
2582 rxq->rxrearm_start = 0;
2583 rxq->rxrearm_nb = 0;
2587 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2589 struct rte_eth_dev *dev;
2592 if (!txq || !txq->sw_ring) {
2593 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2597 dev = &rte_eth_devices[txq->port_id];
2600 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2601 * so need to free remains more carefully.
2603 #ifdef CC_AVX512_SUPPORT
2604 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2605 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2607 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2608 if (txq->tx_tail < i) {
2609 for (; i < txq->nb_tx_desc; i++) {
2610 rte_pktmbuf_free_seg(swr[i].mbuf);
2615 for (; i < txq->tx_tail; i++) {
2616 rte_pktmbuf_free_seg(swr[i].mbuf);
2622 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2623 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2624 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2625 if (txq->tx_tail < i) {
2626 for (; i < txq->nb_tx_desc; i++) {
2627 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2628 txq->sw_ring[i].mbuf = NULL;
2632 for (; i < txq->tx_tail; i++) {
2633 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2634 txq->sw_ring[i].mbuf = NULL;
2637 for (i = 0; i < txq->nb_tx_desc; i++) {
2638 if (txq->sw_ring[i].mbuf) {
2639 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2640 txq->sw_ring[i].mbuf = NULL;
2647 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2650 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2651 uint16_t i, tx_last, tx_id;
2652 uint16_t nb_tx_free_last;
2653 uint16_t nb_tx_to_clean;
2656 /* Start free mbuf from the next of tx_tail */
2657 tx_last = txq->tx_tail;
2658 tx_id = swr_ring[tx_last].next_id;
2660 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2663 nb_tx_to_clean = txq->nb_tx_free;
2664 nb_tx_free_last = txq->nb_tx_free;
2666 free_cnt = txq->nb_tx_desc;
2668 /* Loop through swr_ring to count the amount of
2669 * freeable mubfs and packets.
2671 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2672 for (i = 0; i < nb_tx_to_clean &&
2673 pkt_cnt < free_cnt &&
2674 tx_id != tx_last; i++) {
2675 if (swr_ring[tx_id].mbuf != NULL) {
2676 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2677 swr_ring[tx_id].mbuf = NULL;
2680 * last segment in the packet,
2681 * increment packet count
2683 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2686 tx_id = swr_ring[tx_id].next_id;
2689 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2690 txq->nb_tx_free || tx_id == tx_last)
2693 if (pkt_cnt < free_cnt) {
2694 if (i40e_xmit_cleanup(txq))
2697 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2698 nb_tx_free_last = txq->nb_tx_free;
2702 return (int)pkt_cnt;
2706 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2711 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2712 free_cnt = txq->nb_tx_desc;
2714 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2716 for (i = 0; i < cnt; i += n) {
2717 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2720 n = i40e_tx_free_bufs(txq);
2730 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2731 uint32_t free_cnt __rte_unused)
2736 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2738 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2739 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2740 struct i40e_adapter *ad =
2741 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2743 if (ad->tx_simple_allowed) {
2744 if (ad->tx_vec_allowed)
2745 return i40e_tx_done_cleanup_vec(q, free_cnt);
2747 return i40e_tx_done_cleanup_simple(q, free_cnt);
2749 return i40e_tx_done_cleanup_full(q, free_cnt);
2754 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2756 struct i40e_tx_entry *txe;
2757 uint16_t i, prev, size;
2760 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2765 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2766 for (i = 0; i < size; i++)
2767 ((volatile char *)txq->tx_ring)[i] = 0;
2769 prev = (uint16_t)(txq->nb_tx_desc - 1);
2770 for (i = 0; i < txq->nb_tx_desc; i++) {
2771 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2773 txd->cmd_type_offset_bsz =
2774 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2777 txe[prev].next_id = i;
2781 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2782 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2785 txq->nb_tx_used = 0;
2787 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2788 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2791 /* Init the TX queue in hardware */
2793 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2795 enum i40e_status_code err = I40E_SUCCESS;
2796 struct i40e_vsi *vsi = txq->vsi;
2797 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2798 uint16_t pf_q = txq->reg_idx;
2799 struct i40e_hmc_obj_txq tx_ctx;
2802 /* clear the context structure first */
2803 memset(&tx_ctx, 0, sizeof(tx_ctx));
2804 tx_ctx.new_context = 1;
2805 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2806 tx_ctx.qlen = txq->nb_tx_desc;
2808 #ifdef RTE_LIBRTE_IEEE1588
2809 tx_ctx.timesync_ena = 1;
2811 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2812 if (vsi->type == I40E_VSI_FDIR)
2813 tx_ctx.fd_ena = TRUE;
2815 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2816 if (err != I40E_SUCCESS) {
2817 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2821 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2822 if (err != I40E_SUCCESS) {
2823 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2827 /* Now associate this queue with this PCI function */
2828 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2829 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2830 I40E_QTX_CTL_PF_INDX_MASK);
2831 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2832 I40E_WRITE_FLUSH(hw);
2834 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2840 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2842 struct i40e_rx_entry *rxe = rxq->sw_ring;
2846 for (i = 0; i < rxq->nb_rx_desc; i++) {
2847 volatile union i40e_rx_desc *rxd;
2848 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2850 if (unlikely(!mbuf)) {
2851 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2855 rte_mbuf_refcnt_set(mbuf, 1);
2857 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2859 mbuf->port = rxq->port_id;
2862 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2864 rxd = &rxq->rx_ring[i];
2865 rxd->read.pkt_addr = dma_addr;
2866 rxd->read.hdr_addr = 0;
2867 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2868 rxd->read.rsvd1 = 0;
2869 rxd->read.rsvd2 = 0;
2870 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2879 * Calculate the buffer length, and check the jumbo frame
2880 * and maximum packet length.
2883 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2885 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2886 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2887 struct rte_eth_dev_data *data = pf->dev_data;
2890 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2891 RTE_PKTMBUF_HEADROOM);
2893 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2894 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2895 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2896 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2897 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2898 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2899 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2900 rxq->hs_mode = i40e_header_split_enabled;
2902 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2904 rxq->rx_hdr_len = 0;
2905 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2906 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2907 rxq->hs_mode = i40e_header_split_none;
2912 RTE_MIN(hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len,
2913 data->mtu + I40E_ETH_OVERHEAD);
2914 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2915 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2916 PMD_DRV_LOG(ERR, "maximum packet length must be "
2917 "larger than %u and smaller than %u",
2918 (uint32_t)RTE_ETHER_MIN_LEN,
2919 (uint32_t)I40E_FRAME_SIZE_MAX);
2920 return I40E_ERR_CONFIG;
2926 /* Init the RX queue in hardware */
2928 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2930 int err = I40E_SUCCESS;
2931 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2932 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2933 uint16_t pf_q = rxq->reg_idx;
2935 struct i40e_hmc_obj_rxq rx_ctx;
2937 err = i40e_rx_queue_config(rxq);
2939 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2943 /* Clear the context structure first */
2944 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2945 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2946 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2948 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2949 rx_ctx.qlen = rxq->nb_rx_desc;
2950 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2953 rx_ctx.dtype = rxq->hs_mode;
2955 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2957 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2958 rx_ctx.rxmax = rxq->max_pkt_len;
2959 rx_ctx.tphrdesc_ena = 1;
2960 rx_ctx.tphwdesc_ena = 1;
2961 rx_ctx.tphdata_ena = 1;
2962 rx_ctx.tphhead_ena = 1;
2963 rx_ctx.lrxqthresh = 2;
2964 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2966 /* showiv indicates if inner VLAN is stripped inside of tunnel
2967 * packet. When set it to 1, vlan information is stripped from
2968 * the inner header, but the hardware does not put it in the
2969 * descriptor. So set it zero by default.
2974 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2975 if (err != I40E_SUCCESS) {
2976 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2979 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2980 if (err != I40E_SUCCESS) {
2981 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2985 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2987 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2988 RTE_PKTMBUF_HEADROOM);
2990 /* Check if scattered RX needs to be used. */
2991 if (rxq->max_pkt_len > buf_size)
2992 dev_data->scattered_rx = 1;
2994 /* Init the RX tail register. */
2995 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3001 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3005 PMD_INIT_FUNC_TRACE();
3007 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3008 if (!dev->data->tx_queues[i])
3010 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3011 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3014 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3015 if (!dev->data->rx_queues[i])
3017 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3018 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3023 i40e_dev_free_queues(struct rte_eth_dev *dev)
3027 PMD_INIT_FUNC_TRACE();
3029 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3030 if (!dev->data->rx_queues[i])
3032 i40e_rx_queue_release(dev->data->rx_queues[i]);
3033 dev->data->rx_queues[i] = NULL;
3036 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3037 if (!dev->data->tx_queues[i])
3039 i40e_tx_queue_release(dev->data->tx_queues[i]);
3040 dev->data->tx_queues[i] = NULL;
3044 enum i40e_status_code
3045 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3047 struct i40e_tx_queue *txq;
3048 const struct rte_memzone *tz = NULL;
3049 struct rte_eth_dev *dev;
3053 PMD_DRV_LOG(ERR, "PF is not available");
3054 return I40E_ERR_BAD_PTR;
3057 dev = &rte_eth_devices[pf->dev_data->port_id];
3059 /* Allocate the TX queue data structure. */
3060 txq = rte_zmalloc_socket("i40e fdir tx queue",
3061 sizeof(struct i40e_tx_queue),
3062 RTE_CACHE_LINE_SIZE,
3065 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3066 "tx queue structure.");
3067 return I40E_ERR_NO_MEMORY;
3070 /* Allocate TX hardware ring descriptors. */
3071 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3072 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3074 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3075 I40E_FDIR_QUEUE_ID, ring_size,
3076 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3078 i40e_tx_queue_release(txq);
3079 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3080 return I40E_ERR_NO_MEMORY;
3084 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3085 txq->queue_id = I40E_FDIR_QUEUE_ID;
3086 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3087 txq->vsi = pf->fdir.fdir_vsi;
3089 txq->tx_ring_phys_addr = tz->iova;
3090 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3093 * don't need to allocate software ring and reset for the fdir
3094 * program queue just set the queue has been configured.
3098 pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3100 return I40E_SUCCESS;
3103 enum i40e_status_code
3104 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3106 struct i40e_rx_queue *rxq;
3107 const struct rte_memzone *rz = NULL;
3109 struct rte_eth_dev *dev;
3112 PMD_DRV_LOG(ERR, "PF is not available");
3113 return I40E_ERR_BAD_PTR;
3116 dev = &rte_eth_devices[pf->dev_data->port_id];
3118 /* Allocate the RX queue data structure. */
3119 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3120 sizeof(struct i40e_rx_queue),
3121 RTE_CACHE_LINE_SIZE,
3124 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3125 "rx queue structure.");
3126 return I40E_ERR_NO_MEMORY;
3129 /* Allocate RX hardware ring descriptors. */
3130 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3131 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3133 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3134 I40E_FDIR_QUEUE_ID, ring_size,
3135 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3137 i40e_rx_queue_release(rxq);
3138 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3139 return I40E_ERR_NO_MEMORY;
3143 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3144 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3145 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3146 rxq->vsi = pf->fdir.fdir_vsi;
3148 rxq->rx_ring_phys_addr = rz->iova;
3149 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3150 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3153 * Don't need to allocate software ring and reset for the fdir
3154 * rx queue, just set the queue has been configured.
3159 return I40E_SUCCESS;
3163 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3164 struct rte_eth_rxq_info *qinfo)
3166 struct i40e_rx_queue *rxq;
3168 rxq = dev->data->rx_queues[queue_id];
3170 qinfo->mp = rxq->mp;
3171 qinfo->scattered_rx = dev->data->scattered_rx;
3172 qinfo->nb_desc = rxq->nb_rx_desc;
3174 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3175 qinfo->conf.rx_drop_en = rxq->drop_en;
3176 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3177 qinfo->conf.offloads = rxq->offloads;
3181 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3182 struct rte_eth_txq_info *qinfo)
3184 struct i40e_tx_queue *txq;
3186 txq = dev->data->tx_queues[queue_id];
3188 qinfo->nb_desc = txq->nb_tx_desc;
3190 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3191 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3192 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3194 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3195 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3196 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3197 qinfo->conf.offloads = txq->offloads;
3202 get_avx_supported(bool request_avx512)
3204 if (request_avx512) {
3205 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3206 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3207 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3208 #ifdef CC_AVX512_SUPPORT
3212 "AVX512 is not supported in build env");
3216 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3217 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3218 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3219 #ifdef CC_AVX2_SUPPORT
3223 "AVX2 is not supported in build env");
3230 #endif /* RTE_ARCH_X86 */
3234 i40e_set_rx_function(struct rte_eth_dev *dev)
3236 struct i40e_adapter *ad =
3237 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3238 uint16_t rx_using_sse, i;
3239 /* In order to allow Vector Rx there are a few configuration
3240 * conditions to be met and Rx Bulk Allocation should be allowed.
3242 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3244 ad->rx_use_avx512 = false;
3245 ad->rx_use_avx2 = false;
3247 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3248 !ad->rx_bulk_alloc_allowed) {
3249 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3250 " Vector Rx preconditions",
3251 dev->data->port_id);
3253 ad->rx_vec_allowed = false;
3255 if (ad->rx_vec_allowed) {
3256 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3257 struct i40e_rx_queue *rxq =
3258 dev->data->rx_queues[i];
3260 if (rxq && i40e_rxq_vec_setup(rxq)) {
3261 ad->rx_vec_allowed = false;
3266 ad->rx_use_avx512 = get_avx_supported(1);
3268 if (!ad->rx_use_avx512)
3269 ad->rx_use_avx2 = get_avx_supported(0);
3274 if (ad->rx_vec_allowed &&
3275 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3277 if (dev->data->scattered_rx) {
3278 if (ad->rx_use_avx512) {
3279 #ifdef CC_AVX512_SUPPORT
3281 "Using AVX512 Vector Scattered Rx (port %d).",
3282 dev->data->port_id);
3284 i40e_recv_scattered_pkts_vec_avx512;
3288 "Using %sVector Scattered Rx (port %d).",
3289 ad->rx_use_avx2 ? "avx2 " : "",
3290 dev->data->port_id);
3291 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3292 i40e_recv_scattered_pkts_vec_avx2 :
3293 i40e_recv_scattered_pkts_vec;
3296 if (ad->rx_use_avx512) {
3297 #ifdef CC_AVX512_SUPPORT
3299 "Using AVX512 Vector Rx (port %d).",
3300 dev->data->port_id);
3302 i40e_recv_pkts_vec_avx512;
3306 "Using %sVector Rx (port %d).",
3307 ad->rx_use_avx2 ? "avx2 " : "",
3308 dev->data->port_id);
3309 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3310 i40e_recv_pkts_vec_avx2 :
3314 #else /* RTE_ARCH_X86 */
3315 if (dev->data->scattered_rx) {
3317 "Using Vector Scattered Rx (port %d).",
3318 dev->data->port_id);
3319 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3321 PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3322 dev->data->port_id);
3323 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3325 #endif /* RTE_ARCH_X86 */
3326 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3327 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3328 "satisfied. Rx Burst Bulk Alloc function "
3329 "will be used on port=%d.",
3330 dev->data->port_id);
3332 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3334 /* Simple Rx Path. */
3335 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3336 dev->data->port_id);
3337 dev->rx_pkt_burst = dev->data->scattered_rx ?
3338 i40e_recv_scattered_pkts :
3342 /* Propagate information about RX function choice through all queues. */
3343 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3345 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3346 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3347 #ifdef CC_AVX512_SUPPORT
3348 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3349 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3351 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3352 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3354 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3355 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3358 rxq->rx_using_sse = rx_using_sse;
3363 static const struct {
3364 eth_rx_burst_t pkt_burst;
3366 } i40e_rx_burst_infos[] = {
3367 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3368 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3369 { i40e_recv_pkts, "Scalar" },
3371 #ifdef CC_AVX512_SUPPORT
3372 { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3373 { i40e_recv_pkts_vec_avx512, "Vector AVX512" },
3375 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3376 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3377 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3378 { i40e_recv_pkts_vec, "Vector SSE" },
3379 #elif defined(RTE_ARCH_ARM64)
3380 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3381 { i40e_recv_pkts_vec, "Vector Neon" },
3382 #elif defined(RTE_ARCH_PPC_64)
3383 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3384 { i40e_recv_pkts_vec, "Vector AltiVec" },
3389 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3390 struct rte_eth_burst_mode *mode)
3392 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3396 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3397 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3398 snprintf(mode->info, sizeof(mode->info), "%s",
3399 i40e_rx_burst_infos[i].info);
3409 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3411 struct i40e_adapter *ad =
3412 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3414 /* Use a simple Tx queue if possible (only fast free is allowed) */
3415 ad->tx_simple_allowed =
3417 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3418 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3419 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3420 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3422 if (ad->tx_vec_allowed)
3423 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3425 else if (ad->tx_simple_allowed)
3426 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3430 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3435 i40e_set_tx_function(struct rte_eth_dev *dev)
3437 struct i40e_adapter *ad =
3438 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3441 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3443 ad->tx_use_avx2 = false;
3444 ad->tx_use_avx512 = false;
3446 if (ad->tx_vec_allowed) {
3447 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3448 struct i40e_tx_queue *txq =
3449 dev->data->tx_queues[i];
3451 if (txq && i40e_txq_vec_setup(txq)) {
3452 ad->tx_vec_allowed = false;
3457 ad->tx_use_avx512 = get_avx_supported(1);
3459 if (!ad->tx_use_avx512)
3460 ad->tx_use_avx2 = get_avx_supported(0);
3465 if (ad->tx_simple_allowed) {
3466 if (ad->tx_vec_allowed &&
3467 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3469 if (ad->tx_use_avx512) {
3470 #ifdef CC_AVX512_SUPPORT
3471 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3472 dev->data->port_id);
3473 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3476 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3477 ad->tx_use_avx2 ? "avx2 " : "",
3478 dev->data->port_id);
3479 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3480 i40e_xmit_pkts_vec_avx2 :
3483 #else /* RTE_ARCH_X86 */
3484 PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3485 dev->data->port_id);
3486 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3487 #endif /* RTE_ARCH_X86 */
3489 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3490 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3492 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3494 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3495 dev->tx_pkt_burst = i40e_xmit_pkts;
3496 dev->tx_pkt_prepare = i40e_prep_pkts;
3500 static const struct {
3501 eth_tx_burst_t pkt_burst;
3503 } i40e_tx_burst_infos[] = {
3504 { i40e_xmit_pkts_simple, "Scalar Simple" },
3505 { i40e_xmit_pkts, "Scalar" },
3507 #ifdef CC_AVX512_SUPPORT
3508 { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3510 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3511 { i40e_xmit_pkts_vec, "Vector SSE" },
3512 #elif defined(RTE_ARCH_ARM64)
3513 { i40e_xmit_pkts_vec, "Vector Neon" },
3514 #elif defined(RTE_ARCH_PPC_64)
3515 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3520 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3521 struct rte_eth_burst_mode *mode)
3523 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3527 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3528 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3529 snprintf(mode->info, sizeof(mode->info), "%s",
3530 i40e_tx_burst_infos[i].info);
3540 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3542 struct i40e_adapter *ad =
3543 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3546 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3547 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3551 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3553 struct i40e_adapter *ad =
3554 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3559 ad->pctypes_tbl[i] = 0ULL;
3560 ad->flow_types_mask = 0ULL;
3561 ad->pctypes_mask = 0ULL;
3563 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3564 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3565 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3566 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3567 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3568 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3569 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3570 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3571 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3572 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3573 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3574 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3575 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3576 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3577 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3578 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3579 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3580 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3581 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3582 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3583 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3584 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3586 if (hw->mac.type == I40E_MAC_X722 ||
3587 hw->mac.type == I40E_MAC_X722_VF) {
3588 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3589 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3590 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3591 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3592 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3593 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3594 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3595 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3596 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3597 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3598 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3599 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3602 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3603 if (ad->pctypes_tbl[i])
3604 ad->flow_types_mask |= (1ULL << i);
3605 ad->pctypes_mask |= ad->pctypes_tbl[i];
3609 #ifndef CC_AVX2_SUPPORT
3611 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3612 struct rte_mbuf __rte_unused **rx_pkts,
3613 uint16_t __rte_unused nb_pkts)
3619 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3620 struct rte_mbuf __rte_unused **rx_pkts,
3621 uint16_t __rte_unused nb_pkts)
3627 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3628 struct rte_mbuf __rte_unused **tx_pkts,
3629 uint16_t __rte_unused nb_pkts)
3633 #endif /* ifndef CC_AVX2_SUPPORT */